1 /******************************************************************************
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #ifndef __iwl_trans_int_pcie_h__
30 #define __iwl_trans_int_pcie_h__
32 #include <linux/spinlock.h>
33 #include <linux/interrupt.h>
34 #include <linux/skbuff.h>
35 #include <linux/wait.h>
36 #include <linux/pci.h>
37 #include <linux/timer.h>
41 #include "iwl-shared.h"
42 #include "iwl-trans.h"
43 #include "iwl-debug.h"
45 #include "iwl-op-mode.h"
49 /*This file includes the declaration that are internal to the
52 struct iwl_rx_mem_buffer {
55 struct list_head list;
59 * struct isr_statistics - interrupt statistics
62 struct isr_statistics {
77 * struct iwl_rx_queue - Rx queue
78 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
79 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
82 * @read: Shared index to newest available Rx buffer
83 * @write: Shared index to oldest written Rx packet
84 * @free_count: Number of pre-allocated buffers in rx_free
86 * @rx_free: list of free SKBs for use
87 * @rx_used: List of Rx buffers with no SKB
88 * @need_update: flag to indicate we need to update read/write index
89 * @rb_stts: driver's pointer to receive buffer status
90 * @rb_stts_dma: bus address of receive buffer status
93 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
98 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
99 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
104 struct list_head rx_free;
105 struct list_head rx_used;
107 struct iwl_rb_status *rb_stts;
108 dma_addr_t rb_stts_dma;
119 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
120 * @index -- current index
121 * @n_bd -- total number of entries in queue (must be power of 2)
123 static inline int iwl_queue_inc_wrap(int index, int n_bd)
125 return ++index & (n_bd - 1);
129 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
130 * @index -- current index
131 * @n_bd -- total number of entries in queue (must be power of 2)
133 static inline int iwl_queue_dec_wrap(int index, int n_bd)
135 return --index & (n_bd - 1);
138 struct iwl_cmd_meta {
139 /* only for SYNC commands, iff the reply skb is wanted */
140 struct iwl_host_cmd *source;
144 DEFINE_DMA_UNMAP_ADDR(mapping);
145 DEFINE_DMA_UNMAP_LEN(len);
149 * Generic queue structure
151 * Contains common data for Rx and Tx queues.
153 * Note the difference between n_bd and n_window: the hardware
154 * always assumes 256 descriptors, so n_bd is always 256 (unless
155 * there might be HW changes in the future). For the normal TX
156 * queues, n_window, which is the size of the software queue data
157 * is also 256; however, for the command queue, n_window is only
158 * 32 since we don't need so many commands pending. Since the HW
159 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
160 * the software buffers (in the variables @meta, @txb in struct
161 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
162 * in the same struct) have 256.
163 * This means that we end up with the following:
164 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
165 * SW entries: | 0 | ... | 31 |
166 * where N is a number between 0 and 7. This means that the SW
167 * data is a window overlayed over the HW queue.
170 int n_bd; /* number of BDs in this queue */
171 int write_ptr; /* 1-st empty entry (index) host_w*/
172 int read_ptr; /* last used entry (index) host_r*/
173 /* use for monitoring and recovering the stuck queue */
174 dma_addr_t dma_addr; /* physical addr for BD's */
175 int n_window; /* safe queue window */
177 int low_mark; /* low watermark, resume queue if free
178 * space more than this */
179 int high_mark; /* high watermark, stop queue if free
180 * space less than this */
184 * struct iwl_tx_queue - Tx Queue for DMA
185 * @q: generic Rx/Tx queue descriptor
186 * @bd: base of circular buffer of TFDs
187 * @cmd: array of command/TX buffer pointers
188 * @meta: array of meta data for each command/tx buffer
189 * @dma_addr_cmd: physical address of cmd/tx buffer array
190 * @txb: array of per-TFD driver data
192 * @time_stamp: time (in jiffies) of last read_ptr change
193 * @need_update: indicates need to update read/write index
195 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
196 * descriptors) and required locking structures.
198 #define TFD_TX_CMD_SLOTS 256
199 #define TFD_CMD_SLOTS 32
201 struct iwl_tx_queue {
203 struct iwl_tfd *tfds;
204 struct iwl_device_cmd **cmd;
205 struct iwl_cmd_meta *meta;
206 struct sk_buff **skbs;
208 struct timer_list stuck_timer;
209 struct iwl_trans_pcie *trans_pcie;
215 * struct iwl_trans_pcie - PCIe transport specific data
216 * @rxq: all the RX queue data
217 * @rx_replenish: work that will be called when buffers need to be allocated
218 * @trans: pointer to the generic transport area
219 * @irq - the irq number for the device
220 * @irq_requested: true when the irq has been requested
221 * @scd_base_addr: scheduler sram base address in SRAM
222 * @scd_bc_tbls: pointer to the byte count table of the scheduler
223 * @kw: keep warm address
224 * @pci_dev: basic pci-network driver stuff
225 * @hw_base: pci hardware address support
226 * @ucode_write_complete: indicates that the ucode has been copied.
227 * @ucode_write_waitq: wait queue for uCode load
228 * @status - transport specific status flags
229 * @cmd_queue - command queue number
230 * @rx_buf_size_8k: 8 kB RX buffer size
231 * @rx_page_order: page order for receive buffer size
232 * @wd_timeout: queue watchdog timeout (jiffies)
234 struct iwl_trans_pcie {
235 struct iwl_rx_queue rxq;
236 struct work_struct rx_replenish;
237 struct iwl_trans *trans;
241 dma_addr_t ict_tbl_dma;
246 struct tasklet_struct irq_tasklet;
247 struct isr_statistics isr_stats;
253 struct iwl_dma_ptr scd_bc_tbls;
254 struct iwl_dma_ptr kw;
256 struct iwl_tx_queue *txq;
257 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
258 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
260 /* PCI bus related data */
261 struct pci_dev *pci_dev;
262 void __iomem *hw_base;
264 bool ucode_write_complete;
265 wait_queue_head_t ucode_write_waitq;
266 unsigned long status;
268 u8 n_no_reclaim_cmds;
269 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
270 u8 setup_q_to_fifo[IWL_MAX_HW_QUEUES];
278 unsigned long wd_timeout;
281 /*****************************************************
282 * DRIVER STATUS FUNCTIONS
283 ******************************************************/
284 #define STATUS_HCMD_ACTIVE 0
285 #define STATUS_DEVICE_ENABLED 1
286 #define STATUS_TPOWER_PMI 2
287 #define STATUS_INT_ENABLED 3
289 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
290 ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
292 static inline struct iwl_trans *
293 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
295 return container_of((void *)trans_pcie, struct iwl_trans,
299 /*****************************************************
301 ******************************************************/
302 void iwl_bg_rx_replenish(struct work_struct *data);
303 void iwl_irq_tasklet(struct iwl_trans *trans);
304 void iwlagn_rx_replenish(struct iwl_trans *trans);
305 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
306 struct iwl_rx_queue *q);
308 /*****************************************************
310 ******************************************************/
311 void iwl_reset_ict(struct iwl_trans *trans);
312 void iwl_disable_ict(struct iwl_trans *trans);
313 int iwl_alloc_isr_ict(struct iwl_trans *trans);
314 void iwl_free_isr_ict(struct iwl_trans *trans);
315 irqreturn_t iwl_isr_ict(int irq, void *data);
317 /*****************************************************
319 ******************************************************/
320 void iwl_txq_update_write_ptr(struct iwl_trans *trans,
321 struct iwl_tx_queue *txq);
322 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
323 struct iwl_tx_queue *txq,
324 dma_addr_t addr, u16 len, u8 reset);
325 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
326 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
327 void iwl_tx_cmd_complete(struct iwl_trans *trans,
328 struct iwl_rx_cmd_buffer *rxb, int handler_status);
329 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
330 struct iwl_tx_queue *txq,
332 void iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int queue);
333 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
334 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
335 struct iwl_tx_queue *txq,
336 int tx_fifo_id, bool active);
337 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, int queue, int fifo,
338 int sta_id, int tid, int frame_limit, u16 ssn);
339 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
340 int index, enum dma_data_direction dma_dir);
341 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
342 struct sk_buff_head *skbs);
343 int iwl_queue_space(const struct iwl_queue *q);
345 /*****************************************************
347 ******************************************************/
348 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
349 void iwl_dump_csr(struct iwl_trans *trans);
351 /*****************************************************
353 ******************************************************/
354 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
356 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
357 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
359 /* disable interrupts from uCode/NIC to host */
360 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
362 /* acknowledge/clear/reset any interrupts still pending
363 * from uCode or flow handler (Rx/Tx DMA) */
364 iwl_write32(trans, CSR_INT, 0xffffffff);
365 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
366 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
369 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
371 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
373 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
374 set_bit(STATUS_INT_ENABLED, &trans_pcie->status);
375 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
378 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
380 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
381 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
384 static inline void iwl_wake_queue(struct iwl_trans *trans,
385 struct iwl_tx_queue *txq)
387 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
389 if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
390 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
391 iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
395 static inline void iwl_stop_queue(struct iwl_trans *trans,
396 struct iwl_tx_queue *txq)
398 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
400 if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
401 iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
402 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
404 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
408 static inline int iwl_queue_used(const struct iwl_queue *q, int i)
410 return q->write_ptr >= q->read_ptr ?
411 (i >= q->read_ptr && i < q->write_ptr) :
412 !(i < q->read_ptr && i >= q->write_ptr);
415 static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
417 return index & (q->n_window - 1);
420 #endif /* __iwl_trans_int_pcie_h__ */