1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #ifndef __iwl_trans_int_pcie_h__
30 #define __iwl_trans_int_pcie_h__
32 #include <linux/spinlock.h>
33 #include <linux/interrupt.h>
34 #include <linux/skbuff.h>
38 #include "iwl-shared.h"
39 #include "iwl-trans.h"
40 #include "iwl-debug.h"
47 /*This file includes the declaration that are internal to the
51 * struct isr_statistics - interrupt statistics
54 struct isr_statistics {
69 * struct iwl_rx_queue - Rx queue
70 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
71 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
74 * @read: Shared index to newest available Rx buffer
75 * @write: Shared index to oldest written Rx packet
76 * @free_count: Number of pre-allocated buffers in rx_free
78 * @rx_free: list of free SKBs for use
79 * @rx_used: List of Rx buffers with no SKB
80 * @need_update: flag to indicate we need to update read/write index
81 * @rb_stts: driver's pointer to receive buffer status
82 * @rb_stts_dma: bus address of receive buffer status
85 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
90 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
91 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
96 struct list_head rx_free;
97 struct list_head rx_used;
99 struct iwl_rb_status *rb_stts;
100 dma_addr_t rb_stts_dma;
111 * This queue number is required for proper operation
112 * because the ucode will stop/start the scheduler as
115 #define IWL_IPAN_MCAST_QUEUE 8
118 * struct iwl_trans_pcie - PCIe transport specific data
119 * @rxq: all the RX queue data
120 * @rx_replenish: work that will be called when buffers need to be allocated
121 * @trans: pointer to the generic transport area
122 * @scd_base_addr: scheduler sram base address in SRAM
123 * @scd_bc_tbls: pointer to the byte count table of the scheduler
124 * @kw: keep warm address
125 * @ac_to_fifo: to what fifo is a specifc AC mapped ?
126 * @ac_to_queue: to what tx queue is a specifc AC mapped ?
129 struct iwl_trans_pcie {
130 struct iwl_rx_queue rxq;
131 struct work_struct rx_replenish;
132 struct iwl_trans *trans;
137 dma_addr_t ict_tbl_dma;
138 dma_addr_t aligned_ict_tbl_dma;
142 struct tasklet_struct irq_tasklet;
143 struct isr_statistics isr_stats;
147 struct iwl_dma_ptr scd_bc_tbls;
148 struct iwl_dma_ptr kw;
150 const u8 *ac_to_fifo[NUM_IWL_RXON_CTX];
151 const u8 *ac_to_queue[NUM_IWL_RXON_CTX];
152 u8 mcast_queue[NUM_IWL_RXON_CTX];
155 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
156 ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
158 /*****************************************************
160 ******************************************************/
161 void iwl_bg_rx_replenish(struct work_struct *data);
162 void iwl_irq_tasklet(struct iwl_trans *trans);
163 void iwlagn_rx_replenish(struct iwl_trans *trans);
164 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
165 struct iwl_rx_queue *q);
167 /*****************************************************
169 ******************************************************/
170 int iwl_reset_ict(struct iwl_trans *trans);
171 void iwl_disable_ict(struct iwl_trans *trans);
172 int iwl_alloc_isr_ict(struct iwl_trans *trans);
173 void iwl_free_isr_ict(struct iwl_trans *trans);
174 irqreturn_t iwl_isr_ict(int irq, void *data);
176 /*****************************************************
178 ******************************************************/
179 void iwl_txq_update_write_ptr(struct iwl_trans *trans,
180 struct iwl_tx_queue *txq);
181 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
182 struct iwl_tx_queue *txq,
183 dma_addr_t addr, u16 len, u8 reset);
184 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
185 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
186 int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id,
187 u32 flags, u16 len, const void *data);
188 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
189 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
190 struct iwl_tx_queue *txq,
192 int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id);
193 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
194 void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
195 struct iwl_tx_queue *txq,
196 int tx_fifo_id, int scd_retry);
197 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
198 enum iwl_rxon_context_id ctx, int sta_id,
200 void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
201 enum iwl_rxon_context_id ctx,
202 int sta_id, int tid, int frame_limit);
203 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
205 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
206 struct sk_buff_head *skbs);
208 /*****************************************************
210 ******************************************************/
211 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
212 char **buf, bool display);
213 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
214 void iwl_dump_csr(struct iwl_trans *trans);
216 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
218 clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
220 /* disable interrupts from uCode/NIC to host */
221 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
223 /* acknowledge/clear/reset any interrupts still pending
224 * from uCode or flow handler (Rx/Tx DMA) */
225 iwl_write32(bus(trans), CSR_INT, 0xffffffff);
226 iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
227 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
230 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
232 struct iwl_trans_pcie *trans_pcie =
233 IWL_TRANS_GET_PCIE_TRANS(trans);
235 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
236 set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
237 iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
240 #endif /* __iwl_trans_int_pcie_h__ */