1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
23 * Contact Information:
24 * Intel Linux Wireless <ilw@linux.intel.com>
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
31 #define IWL_POLL_INTERVAL 10 /* microseconds */
33 static inline void __iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
35 iwl_write32(priv, reg, iwl_read32(priv, reg) | mask);
38 static inline void __iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
40 iwl_write32(priv, reg, iwl_read32(priv, reg) & ~mask);
43 void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
47 spin_lock_irqsave(&priv->reg_lock, flags);
48 __iwl_set_bit(priv, reg, mask);
49 spin_unlock_irqrestore(&priv->reg_lock, flags);
52 void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
56 spin_lock_irqsave(&priv->reg_lock, flags);
57 __iwl_clear_bit(priv, reg, mask);
58 spin_unlock_irqrestore(&priv->reg_lock, flags);
61 int iwl_poll_bit(struct iwl_priv *priv, u32 addr,
62 u32 bits, u32 mask, int timeout)
67 if ((iwl_read32(priv, addr) & mask) == (bits & mask))
69 udelay(IWL_POLL_INTERVAL);
70 t += IWL_POLL_INTERVAL;
71 } while (t < timeout);
76 int iwl_grab_nic_access_silent(struct iwl_priv *priv)
80 lockdep_assert_held(&priv->reg_lock);
82 /* this bit wakes up the NIC */
83 __iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
86 * These bits say the device is running, and should keep running for
87 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
88 * but they do not indicate that embedded SRAM is restored yet;
89 * 3945 and 4965 have volatile SRAM, and must save/restore contents
90 * to/from host DRAM when sleeping/waking for power-saving.
91 * Each direction takes approximately 1/4 millisecond; with this
92 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
93 * series of register accesses are expected (e.g. reading Event Log),
94 * to keep device from sleeping.
96 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
97 * SRAM is okay/restored. We don't check that here because this call
98 * is just for hardware register access; but GP1 MAC_SLEEP check is a
99 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
101 * 5000 series and later (including 1000 series) have non-volatile SRAM,
102 * and do not save/restore SRAM when power cycling.
104 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
105 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
106 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
107 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
109 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
116 int iwl_grab_nic_access(struct iwl_priv *priv)
118 int ret = iwl_grab_nic_access_silent(priv);
120 u32 val = iwl_read32(priv, CSR_GP_CNTRL);
122 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
128 void iwl_release_nic_access(struct iwl_priv *priv)
130 lockdep_assert_held(&priv->reg_lock);
131 __iwl_clear_bit(priv, CSR_GP_CNTRL,
132 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
135 u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg)
140 spin_lock_irqsave(&priv->reg_lock, flags);
141 iwl_grab_nic_access(priv);
142 value = iwl_read32(priv, reg);
143 iwl_release_nic_access(priv);
144 spin_unlock_irqrestore(&priv->reg_lock, flags);
149 void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value)
153 spin_lock_irqsave(&priv->reg_lock, flags);
154 if (!iwl_grab_nic_access(priv)) {
155 iwl_write32(priv, reg, value);
156 iwl_release_nic_access(priv);
158 spin_unlock_irqrestore(&priv->reg_lock, flags);
161 int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask,
167 if ((iwl_read_direct32(priv, addr) & mask) == mask)
169 udelay(IWL_POLL_INTERVAL);
170 t += IWL_POLL_INTERVAL;
171 } while (t < timeout);
176 static inline u32 __iwl_read_prph(struct iwl_priv *priv, u32 reg)
178 iwl_write32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
180 return iwl_read32(priv, HBUS_TARG_PRPH_RDAT);
183 static inline void __iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
185 iwl_write32(priv, HBUS_TARG_PRPH_WADDR,
186 ((addr & 0x0000FFFF) | (3 << 24)));
188 iwl_write32(priv, HBUS_TARG_PRPH_WDAT, val);
191 u32 iwl_read_prph(struct iwl_priv *priv, u32 reg)
196 spin_lock_irqsave(&priv->reg_lock, flags);
197 iwl_grab_nic_access(priv);
198 val = __iwl_read_prph(priv, reg);
199 iwl_release_nic_access(priv);
200 spin_unlock_irqrestore(&priv->reg_lock, flags);
204 void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
208 spin_lock_irqsave(&priv->reg_lock, flags);
209 if (!iwl_grab_nic_access(priv)) {
210 __iwl_write_prph(priv, addr, val);
211 iwl_release_nic_access(priv);
213 spin_unlock_irqrestore(&priv->reg_lock, flags);
216 void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
220 spin_lock_irqsave(&priv->reg_lock, flags);
221 iwl_grab_nic_access(priv);
222 __iwl_write_prph(priv, reg, __iwl_read_prph(priv, reg) | mask);
223 iwl_release_nic_access(priv);
224 spin_unlock_irqrestore(&priv->reg_lock, flags);
227 void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg,
232 spin_lock_irqsave(&priv->reg_lock, flags);
233 iwl_grab_nic_access(priv);
234 __iwl_write_prph(priv, reg,
235 (__iwl_read_prph(priv, reg) & mask) | bits);
236 iwl_release_nic_access(priv);
237 spin_unlock_irqrestore(&priv->reg_lock, flags);
240 void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
245 spin_lock_irqsave(&priv->reg_lock, flags);
246 iwl_grab_nic_access(priv);
247 val = __iwl_read_prph(priv, reg);
248 __iwl_write_prph(priv, reg, (val & ~mask));
249 iwl_release_nic_access(priv);
250 spin_unlock_irqrestore(&priv->reg_lock, flags);
253 void _iwl_read_targ_mem_words(struct iwl_priv *priv, u32 addr,
254 void *buf, int words)
260 spin_lock_irqsave(&priv->reg_lock, flags);
261 iwl_grab_nic_access(priv);
263 iwl_write32(priv, HBUS_TARG_MEM_RADDR, addr);
266 for (offs = 0; offs < words; offs++)
267 vals[offs] = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
269 iwl_release_nic_access(priv);
270 spin_unlock_irqrestore(&priv->reg_lock, flags);
273 u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
277 _iwl_read_targ_mem_words(priv, addr, &value, 1);
282 void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
286 spin_lock_irqsave(&priv->reg_lock, flags);
287 if (!iwl_grab_nic_access(priv)) {
288 iwl_write32(priv, HBUS_TARG_MEM_WADDR, addr);
290 iwl_write32(priv, HBUS_TARG_MEM_WDAT, val);
291 iwl_release_nic_access(priv);
293 spin_unlock_irqrestore(&priv->reg_lock, flags);