drivers/net/wireless/iwlwifi/iwl-eeprom.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *****************************************************************************/
  62
  63
  64 #include <linux/kernel.h>
  65 #include <linux/module.h>
  66 #include <linux/slab.h>
  67 #include <linux/init.h>
  68
  69 #include <net/mac80211.h>
  70
  71 #include "iwl-commands.h"
  72 #include "iwl-dev.h"
  73 #include "iwl-core.h"
  74 #include "iwl-debug.h"
  75 #include "iwl-eeprom.h"
  76 #include "iwl-io.h"
  77
  78 /************************** EEPROM BANDS ****************************
  79  *
  80  * The iwl_eeprom_band definitions below provide the mapping from the
  81  * EEPROM contents to the specific channel number supported for each
  82  * band.
  83  *
  84  * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
  85  * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  86  * The specific geography and calibration information for that channel
  87  * is contained in the eeprom map itself.
  88  *
  89  * During init, we copy the eeprom information and channel map
  90  * information into priv->channel_info_24/52 and priv->channel_map_24/52
  91  *
  92  * channel_map_24/52 provides the index in the channel_info array for a
  93  * given channel.  We have to have two separate maps as there is channel
  94  * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  95  * band_2
  96  *
  97  * A value of 0xff stored in the channel_map indicates that the channel
  98  * is not supported by the hardware at all.
  99  *
 100  * A value of 0xfe in the channel_map indicates that the channel is not
 101  * valid for Tx with the current hardware.  This means that
 102  * while the system can tune and receive on a given channel, it may not
 103  * be able to associate or transmit any frames on that
 104  * channel.  There is no corresponding channel information for that
 105  * entry.
 106  *
 107  *********************************************************************/
 108
 109 /* 2.4 GHz */
 110 const u8 iwl_eeprom_band_1[14] = {
 111         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 112 };
 113
 114 /* 5.2 GHz bands */
 115 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
 116         183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
 117 };
 118
 119 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
 120         34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 121 };
 122
 123 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
 124         100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 125 };
 126
 127 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
 128         145, 149, 153, 157, 161, 165
 129 };
 130
 131 static const u8 iwl_eeprom_band_6[] = {       /* 2.4 ht40 channel */
 132         1, 2, 3, 4, 5, 6, 7
 133 };
 134
 135 static const u8 iwl_eeprom_band_7[] = {       /* 5.2 ht40 channel */
 136         36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
 137 };
 138
 139 /******************************************************************************
 140  *
 141  * EEPROM related functions
 142  *
 143 ******************************************************************************/
 144
 145 static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
 146 {
 147         u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
 148         int ret = 0;
 149
 150         IWL_DEBUG_EEPROM(priv, "EEPROM signature=0x%08x\n", gp);
 151         switch (gp) {
 152         case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
 153                 if (priv->nvm_device_type != NVM_DEVICE_TYPE_OTP) {
 154                         IWL_ERR(priv, "EEPROM with bad signature: 0x%08x\n",
 155                                 gp);
 156                         ret = -ENOENT;
 157                 }
 158                 break;
 159         case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
 160         case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
 161                 if (priv->nvm_device_type != NVM_DEVICE_TYPE_EEPROM) {
 162                         IWL_ERR(priv, "OTP with bad signature: 0x%08x\n", gp);
 163                         ret = -ENOENT;
 164                 }
 165                 break;
 166         case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
 167         default:
 168                 IWL_ERR(priv, "bad EEPROM/OTP signature, type=%s, "
 169                         "EEPROM_GP=0x%08x\n",
 170                         (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
 171                         ? "OTP" : "EEPROM", gp);
 172                 ret = -ENOENT;
 173                 break;
 174         }
 175         return ret;
 176 }
 177
 178 static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
 179 {
 180         u32 otpgp;
 181
 182         otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
 183         if (mode == IWL_OTP_ACCESS_ABSOLUTE)
 184                 iwl_clear_bit(priv, CSR_OTP_GP_REG,
 185                                 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 186         else
 187                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 188                                 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 189 }
 190
 191 static int iwlcore_get_nvm_type(struct iwl_priv *priv)
 192 {
 193         u32 otpgp;
 194         int nvm_type;
 195
 196         /* OTP only valid for CP/PP and after */
 197         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 198         case CSR_HW_REV_TYPE_NONE:
 199                 IWL_ERR(priv, "Unknown hardware type\n");
 200                 return -ENOENT;
 201         case CSR_HW_REV_TYPE_3945:
 202         case CSR_HW_REV_TYPE_4965:
 203         case CSR_HW_REV_TYPE_5300:
 204         case CSR_HW_REV_TYPE_5350:
 205         case CSR_HW_REV_TYPE_5100:
 206         case CSR_HW_REV_TYPE_5150:
 207                 nvm_type = NVM_DEVICE_TYPE_EEPROM;
 208                 break;
 209         default:
 210                 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
 211                 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
 212                         nvm_type = NVM_DEVICE_TYPE_OTP;
 213                 else
 214                         nvm_type = NVM_DEVICE_TYPE_EEPROM;
 215                 break;
 216         }
 217         return  nvm_type;
 218 }
 219
 220 const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
 221 {
 222         BUG_ON(offset >= priv->cfg->base_params->eeprom_size);
 223         return &priv->eeprom[offset];
 224 }
 225
 226 static int iwl_init_otp_access(struct iwl_priv *priv)
 227 {
 228         int ret;
 229
 230         /* Enable 40MHz radio clock */
 231         _iwl_write32(priv, CSR_GP_CNTRL,
 232                      _iwl_read32(priv, CSR_GP_CNTRL) |
 233                      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 234
 235         /* wait for clock to be ready */
 236         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 237                                   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 238                                   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 239                                   25000);
 240         if (ret < 0)
 241                 IWL_ERR(priv, "Time out access OTP\n");
 242         else {
 243                 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
 244                                   APMG_PS_CTRL_VAL_RESET_REQ);
 245                 udelay(5);
 246                 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
 247                                     APMG_PS_CTRL_VAL_RESET_REQ);
 248
 249                 /*
 250                  * CSR auto clock gate disable bit -
 251                  * this is only applicable for HW with OTP shadow RAM
 252                  */
 253                 if (priv->cfg->base_params->shadow_ram_support)
 254                         iwl_set_bit(priv, CSR_DBG_LINK_PWR_MGMT_REG,
 255                                 CSR_RESET_LINK_PWR_MGMT_DISABLED);
 256         }
 257         return ret;
 258 }
 259
 260 static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_data)
 261 {
 262         int ret = 0;
 263         u32 r;
 264         u32 otpgp;
 265
 266         _iwl_write32(priv, CSR_EEPROM_REG,
 267                      CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 268         ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
 269                                   CSR_EEPROM_REG_READ_VALID_MSK,
 270                                   CSR_EEPROM_REG_READ_VALID_MSK,
 271                                   IWL_EEPROM_ACCESS_TIMEOUT);
 272         if (ret < 0) {
 273                 IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
 274                 return ret;
 275         }
 276         r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
 277         /* check for ECC errors: */
 278         otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
 279         if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
 280                 /* stop in this case */
 281                 /* set the uncorrectable OTP ECC bit for acknowledgement */
 282                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 283                         CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 284                 IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
 285                 return -EINVAL;
 286         }
 287         if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
 288                 /* continue in this case */
 289                 /* set the correctable OTP ECC bit for acknowledgement */
 290                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 291                                 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
 292                 IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
 293         }
 294         *eeprom_data = cpu_to_le16(r >> 16);
 295         return 0;
 296 }
 297
 298 /*
 299  * iwl_is_otp_empty: check for empty OTP
 300  */
 301 static bool iwl_is_otp_empty(struct iwl_priv *priv)
 302 {
 303         u16 next_link_addr = 0;
 304         __le16 link_value;
 305         bool is_empty = false;
 306
 307         /* locate the beginning of OTP link list */
 308         if (!iwl_read_otp_word(priv, next_link_addr, &link_value)) {
 309                 if (!link_value) {
 310                         IWL_ERR(priv, "OTP is empty\n");
 311                         is_empty = true;
 312                 }
 313         } else {
 314                 IWL_ERR(priv, "Unable to read first block of OTP list.\n");
 315                 is_empty = true;
 316         }
 317
 318         return is_empty;
 319 }
 320
 321
 322 /*
 323  * iwl_find_otp_image: find EEPROM image in OTP
 324  *   finding the OTP block that contains the EEPROM image.
 325  *   the last valid block on the link list (the block _before_ the last block)
 326  *   is the block we should read and used to configure the device.
 327  *   If all the available OTP blocks are full, the last block will be the block
 328  *   we should read and used to configure the device.
 329  *   only perform this operation if shadow RAM is disabled
 330  */
 331 static int iwl_find_otp_image(struct iwl_priv *priv,
 332                                         u16 *validblockaddr)
 333 {
 334         u16 next_link_addr = 0, valid_addr;
 335         __le16 link_value = 0;
 336         int usedblocks = 0;
 337
 338         /* set addressing mode to absolute to traverse the link list */
 339         iwl_set_otp_access(priv, IWL_OTP_ACCESS_ABSOLUTE);
 340
 341         /* checking for empty OTP or error */
 342         if (iwl_is_otp_empty(priv))
 343                 return -EINVAL;
 344
 345         /*
 346          * start traverse link list
 347          * until reach the max number of OTP blocks
 348          * different devices have different number of OTP blocks
 349          */
 350         do {
 351                 /* save current valid block address
 352                  * check for more block on the link list
 353                  */
 354                 valid_addr = next_link_addr;
 355                 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
 356                 IWL_DEBUG_EEPROM(priv, "OTP blocks %d addr 0x%x\n",
 357                                usedblocks, next_link_addr);
 358                 if (iwl_read_otp_word(priv, next_link_addr, &link_value))
 359                         return -EINVAL;
 360                 if (!link_value) {
 361                         /*
 362                          * reach the end of link list, return success and
 363                          * set address point to the starting address
 364                          * of the image
 365                          */
 366                         *validblockaddr = valid_addr;
 367                         /* skip first 2 bytes (link list pointer) */
 368                         *validblockaddr += 2;
 369                         return 0;
 370                 }
 371                 /* more in the link list, continue */
 372                 usedblocks++;
 373         } while (usedblocks <= priv->cfg->base_params->max_ll_items);
 374
 375         /* OTP has no valid blocks */
 376         IWL_DEBUG_EEPROM(priv, "OTP has no valid blocks\n");
 377         return -EINVAL;
 378 }
 379
 380 const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
 381 {
 382         return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset);
 383 }
 384
 385 u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
 386 {
 387         if (!priv->eeprom)
 388                 return 0;
 389         return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
 390 }
 391
 392 /**
 393  * iwl_eeprom_init - read EEPROM contents
 394  *
 395  * Load the EEPROM contents from adapter into priv->eeprom
 396  *
 397  * NOTE:  This routine uses the non-debug IO access functions.
 398  */
 399 int iwl_eeprom_init(struct iwl_priv *priv)
 400 {
 401         __le16 *e;
 402         u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
 403         int sz;
 404         int ret;
 405         u16 addr;
 406         u16 validblockaddr = 0;
 407         u16 cache_addr = 0;
 408
 409         priv->nvm_device_type = iwlcore_get_nvm_type(priv);
 410         if (priv->nvm_device_type == -ENOENT)
 411                 return -ENOENT;
 412         /* allocate eeprom */
 413         sz = priv->cfg->base_params->eeprom_size;
 414         IWL_DEBUG_EEPROM(priv, "NVM size = %d\n", sz);
 415         priv->eeprom = kzalloc(sz, GFP_KERNEL);
 416         if (!priv->eeprom) {
 417                 ret = -ENOMEM;
 418                 goto alloc_err;
 419         }
 420         e = (__le16 *)priv->eeprom;
 421
 422         priv->cfg->ops->lib->apm_ops.init(priv);
 423
 424         ret = iwl_eeprom_verify_signature(priv);
 425         if (ret < 0) {
 426                 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
 427                 ret = -ENOENT;
 428                 goto err;
 429         }
 430
 431         /* Make sure driver (instead of uCode) is allowed to read EEPROM */
 432         ret = priv->cfg->ops->lib->eeprom_ops.acquire_semaphore(priv);
 433         if (ret < 0) {
 434                 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
 435                 ret = -ENOENT;
 436                 goto err;
 437         }
 438
 439         if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
 440
 441                 ret = iwl_init_otp_access(priv);
 442                 if (ret) {
 443                         IWL_ERR(priv, "Failed to initialize OTP access.\n");
 444                         ret = -ENOENT;
 445                         goto done;
 446                 }
 447                 _iwl_write32(priv, CSR_EEPROM_GP,
 448                              iwl_read32(priv, CSR_EEPROM_GP) &
 449                              ~CSR_EEPROM_GP_IF_OWNER_MSK);
 450
 451                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 452                              CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
 453                              CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 454                 /* traversing the linked list if no shadow ram supported */
 455                 if (!priv->cfg->base_params->shadow_ram_support) {
 456                         if (iwl_find_otp_image(priv, &validblockaddr)) {
 457                                 ret = -ENOENT;
 458                                 goto done;
 459                         }
 460                 }
 461                 for (addr = validblockaddr; addr < validblockaddr + sz;
 462                      addr += sizeof(u16)) {
 463                         __le16 eeprom_data;
 464
 465                         ret = iwl_read_otp_word(priv, addr, &eeprom_data);
 466                         if (ret)
 467                                 goto done;
 468                         e[cache_addr / 2] = eeprom_data;
 469                         cache_addr += sizeof(u16);
 470                 }
 471         } else {
 472                 /* eeprom is an array of 16bit values */
 473                 for (addr = 0; addr < sz; addr += sizeof(u16)) {
 474                         u32 r;
 475
 476                         _iwl_write32(priv, CSR_EEPROM_REG,
 477                                      CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 478
 479                         ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
 480                                                   CSR_EEPROM_REG_READ_VALID_MSK,
 481                                                   CSR_EEPROM_REG_READ_VALID_MSK,
 482                                                   IWL_EEPROM_ACCESS_TIMEOUT);
 483                         if (ret < 0) {
 484                                 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
 485                                 goto done;
 486                         }
 487                         r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
 488                         e[addr / 2] = cpu_to_le16(r >> 16);
 489                 }
 490         }
 491
 492         IWL_DEBUG_EEPROM(priv, "NVM Type: %s, version: 0x%x\n",
 493                        (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
 494                        ? "OTP" : "EEPROM",
 495                        iwl_eeprom_query16(priv, EEPROM_VERSION));
 496
 497         ret = 0;
 498 done:
 499         priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv);
 500
 501 err:
 502         if (ret)
 503                 iwl_eeprom_free(priv);
 504         /* Reset chip to save power until we load uCode during "up". */
 505         iwl_apm_stop(priv);
 506 alloc_err:
 507         return ret;
 508 }
 509
 510 void iwl_eeprom_free(struct iwl_priv *priv)
 511 {
 512         kfree(priv->eeprom);
 513         priv->eeprom = NULL;
 514 }
 515
 516 static void iwl_init_band_reference(const struct iwl_priv *priv,
 517                         int eep_band, int *eeprom_ch_count,
 518                         const struct iwl_eeprom_channel **eeprom_ch_info,
 519                         const u8 **eeprom_ch_index)
 520 {
 521         u32 offset = priv->cfg->ops->lib->
 522                         eeprom_ops.regulatory_bands[eep_band - 1];
 523         switch (eep_band) {
 524         case 1:         /* 2.4GHz band */
 525                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
 526                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 527                                 iwl_eeprom_query_addr(priv, offset);
 528                 *eeprom_ch_index = iwl_eeprom_band_1;
 529                 break;
 530         case 2:         /* 4.9GHz band */
 531                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
 532                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 533                                 iwl_eeprom_query_addr(priv, offset);
 534                 *eeprom_ch_index = iwl_eeprom_band_2;
 535                 break;
 536         case 3:         /* 5.2GHz band */
 537                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
 538                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 539                                 iwl_eeprom_query_addr(priv, offset);
 540                 *eeprom_ch_index = iwl_eeprom_band_3;
 541                 break;
 542         case 4:         /* 5.5GHz band */
 543                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
 544                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 545                                 iwl_eeprom_query_addr(priv, offset);
 546                 *eeprom_ch_index = iwl_eeprom_band_4;
 547                 break;
 548         case 5:         /* 5.7GHz band */
 549                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
 550                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 551                                 iwl_eeprom_query_addr(priv, offset);
 552                 *eeprom_ch_index = iwl_eeprom_band_5;
 553                 break;
 554         case 6:         /* 2.4GHz ht40 channels */
 555                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
 556                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 557                                 iwl_eeprom_query_addr(priv, offset);
 558                 *eeprom_ch_index = iwl_eeprom_band_6;
 559                 break;
 560         case 7:         /* 5 GHz ht40 channels */
 561                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
 562                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 563                                 iwl_eeprom_query_addr(priv, offset);
 564                 *eeprom_ch_index = iwl_eeprom_band_7;
 565                 break;
 566         default:
 567                 BUG();
 568                 return;
 569         }
 570 }
 571
 572 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
 573                             ? # x " " : "")
 574 /**
 575  * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
 576  *
 577  * Does not set up a command, or touch hardware.
 578  */
 579 static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
 580                               enum ieee80211_band band, u16 channel,
 581                               const struct iwl_eeprom_channel *eeprom_ch,
 582                               u8 clear_ht40_extension_channel)
 583 {
 584         struct iwl_channel_info *ch_info;
 585
 586         ch_info = (struct iwl_channel_info *)
 587                         iwl_get_channel_info(priv, band, channel);
 588
 589         if (!is_channel_valid(ch_info))
 590                 return -1;
 591
 592         IWL_DEBUG_EEPROM(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
 593                         " Ad-Hoc %ssupported\n",
 594                         ch_info->channel,
 595                         is_channel_a_band(ch_info) ?
 596                         "5.2" : "2.4",
 597                         CHECK_AND_PRINT(IBSS),
 598                         CHECK_AND_PRINT(ACTIVE),
 599                         CHECK_AND_PRINT(RADAR),
 600                         CHECK_AND_PRINT(WIDE),
 601                         CHECK_AND_PRINT(DFS),
 602                         eeprom_ch->flags,
 603                         eeprom_ch->max_power_avg,
 604                         ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
 605                          && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
 606                         "" : "not ");
 607
 608         ch_info->ht40_eeprom = *eeprom_ch;
 609         ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
 610         ch_info->ht40_flags = eeprom_ch->flags;
 611         if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
 612                 ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel;
 613
 614         return 0;
 615 }
 616
 617 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
 618                             ? # x " " : "")
 619
 620 /**
 621  * iwl_init_channel_map - Set up driver's info for all possible channels
 622  */
 623 int iwl_init_channel_map(struct iwl_priv *priv)
 624 {
 625         int eeprom_ch_count = 0;
 626         const u8 *eeprom_ch_index = NULL;
 627         const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
 628         int band, ch;
 629         struct iwl_channel_info *ch_info;
 630
 631         if (priv->channel_count) {
 632                 IWL_DEBUG_EEPROM(priv, "Channel map already initialized.\n");
 633                 return 0;
 634         }
 635
 636         IWL_DEBUG_EEPROM(priv, "Initializing regulatory info from EEPROM\n");
 637
 638         priv->channel_count =
 639             ARRAY_SIZE(iwl_eeprom_band_1) +
 640             ARRAY_SIZE(iwl_eeprom_band_2) +
 641             ARRAY_SIZE(iwl_eeprom_band_3) +
 642             ARRAY_SIZE(iwl_eeprom_band_4) +
 643             ARRAY_SIZE(iwl_eeprom_band_5);
 644
 645         IWL_DEBUG_EEPROM(priv, "Parsing data for %d channels.\n",
 646                         priv->channel_count);
 647
 648         priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
 649                                      priv->channel_count, GFP_KERNEL);
 650         if (!priv->channel_info) {
 651                 IWL_ERR(priv, "Could not allocate channel_info\n");
 652                 priv->channel_count = 0;
 653                 return -ENOMEM;
 654         }
 655
 656         ch_info = priv->channel_info;
 657
 658         /* Loop through the 5 EEPROM bands adding them in order to the
 659          * channel map we maintain (that contains additional information than
 660          * what just in the EEPROM) */
 661         for (band = 1; band <= 5; band++) {
 662
 663                 iwl_init_band_reference(priv, band, &eeprom_ch_count,
 664                                         &eeprom_ch_info, &eeprom_ch_index);
 665
 666                 /* Loop through each band adding each of the channels */
 667                 for (ch = 0; ch < eeprom_ch_count; ch++) {
 668                         ch_info->channel = eeprom_ch_index[ch];
 669                         ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
 670                             IEEE80211_BAND_5GHZ;
 671
 672                         /* permanently store EEPROM's channel regulatory flags
 673                          *   and max power in channel info database. */
 674                         ch_info->eeprom = eeprom_ch_info[ch];
 675
 676                         /* Copy the run-time flags so they are there even on
 677                          * invalid channels */
 678                         ch_info->flags = eeprom_ch_info[ch].flags;
 679                         /* First write that ht40 is not enabled, and then enable
 680                          * one by one */
 681                         ch_info->ht40_extension_channel =
 682                                         IEEE80211_CHAN_NO_HT40;
 683
 684                         if (!(is_channel_valid(ch_info))) {
 685                                 IWL_DEBUG_EEPROM(priv,
 686                                                "Ch. %d Flags %x [%sGHz] - "
 687                                                "No traffic\n",
 688                                                ch_info->channel,
 689                                                ch_info->flags,
 690                                                is_channel_a_band(ch_info) ?
 691                                                "5.2" : "2.4");
 692                                 ch_info++;
 693                                 continue;
 694                         }
 695
 696                         /* Initialize regulatory-based run-time data */
 697                         ch_info->max_power_avg = ch_info->curr_txpow =
 698                             eeprom_ch_info[ch].max_power_avg;
 699                         ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
 700                         ch_info->min_power = 0;
 701
 702                         IWL_DEBUG_EEPROM(priv, "Ch. %d [%sGHz] "
 703                                        "%s%s%s%s%s%s(0x%02x %ddBm):"
 704                                        " Ad-Hoc %ssupported\n",
 705                                        ch_info->channel,
 706                                        is_channel_a_band(ch_info) ?
 707                                        "5.2" : "2.4",
 708                                        CHECK_AND_PRINT_I(VALID),
 709                                        CHECK_AND_PRINT_I(IBSS),
 710                                        CHECK_AND_PRINT_I(ACTIVE),
 711                                        CHECK_AND_PRINT_I(RADAR),
 712                                        CHECK_AND_PRINT_I(WIDE),
 713                                        CHECK_AND_PRINT_I(DFS),
 714                                        eeprom_ch_info[ch].flags,
 715                                        eeprom_ch_info[ch].max_power_avg,
 716                                        ((eeprom_ch_info[ch].
 717                                          flags & EEPROM_CHANNEL_IBSS)
 718                                         && !(eeprom_ch_info[ch].
 719                                              flags & EEPROM_CHANNEL_RADAR))
 720                                        ? "" : "not ");
 721
 722                         /* Set the tx_power_user_lmt to the highest power
 723                          * supported by any channel */
 724                         if (eeprom_ch_info[ch].max_power_avg >
 725                                                 priv->tx_power_user_lmt)
 726                                 priv->tx_power_user_lmt =
 727                                     eeprom_ch_info[ch].max_power_avg;
 728
 729                         ch_info++;
 730                 }
 731         }
 732
 733         /* Check if we do have HT40 channels */
 734         if (priv->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
 735             EEPROM_REGULATORY_BAND_NO_HT40 &&
 736             priv->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
 737             EEPROM_REGULATORY_BAND_NO_HT40)
 738                 return 0;
 739
 740         /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
 741         for (band = 6; band <= 7; band++) {
 742                 enum ieee80211_band ieeeband;
 743
 744                 iwl_init_band_reference(priv, band, &eeprom_ch_count,
 745                                         &eeprom_ch_info, &eeprom_ch_index);
 746
 747                 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
 748                 ieeeband =
 749                         (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 750
 751                 /* Loop through each band adding each of the channels */
 752                 for (ch = 0; ch < eeprom_ch_count; ch++) {
 753                         /* Set up driver's info for lower half */
 754                         iwl_mod_ht40_chan_info(priv, ieeeband,
 755                                                 eeprom_ch_index[ch],
 756                                                 &eeprom_ch_info[ch],
 757                                                 IEEE80211_CHAN_NO_HT40PLUS);
 758
 759                         /* Set up driver's info for upper half */
 760                         iwl_mod_ht40_chan_info(priv, ieeeband,
 761                                                 eeprom_ch_index[ch] + 4,
 762                                                 &eeprom_ch_info[ch],
 763                                                 IEEE80211_CHAN_NO_HT40MINUS);
 764                 }
 765         }
 766
 767         /* for newer device (6000 series and up)
 768          * EEPROM contain enhanced tx power information
 769          * driver need to process addition information
 770          * to determine the max channel tx power limits
 771          */
 772         if (priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower)
 773                 priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower(priv);
 774
 775         return 0;
 776 }
 777
 778 /*
 779  * iwl_free_channel_map - undo allocations in iwl_init_channel_map
 780  */
 781 void iwl_free_channel_map(struct iwl_priv *priv)
 782 {
 783         kfree(priv->channel_info);
 784         priv->channel_count = 0;
 785 }
 786
 787 /**
 788  * iwl_get_channel_info - Find driver's private channel info
 789  *
 790  * Based on band and channel number.
 791  */
 792 const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
 793                                         enum ieee80211_band band, u16 channel)
 794 {
 795         int i;
 796
 797         switch (band) {
 798         case IEEE80211_BAND_5GHZ:
 799                 for (i = 14; i < priv->channel_count; i++) {
 800                         if (priv->channel_info[i].channel == channel)
 801                                 return &priv->channel_info[i];
 802                 }
 803                 break;
 804         case IEEE80211_BAND_2GHZ:
 805                 if (channel >= 1 && channel <= 14)
 806                         return &priv->channel_info[channel - 1];
 807                 break;
 808         default:
 809                 BUG();
 810         }
 811
 812         return NULL;
 813 }