1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
64 #include <linux/kernel.h>
65 #include <linux/module.h>
66 #include <linux/init.h>
68 #include <net/mac80211.h>
70 #include "iwl-commands.h"
73 #include "iwl-debug.h"
74 #include "iwl-eeprom.h"
77 /************************** EEPROM BANDS ****************************
79 * The iwl_eeprom_band definitions below provide the mapping from the
80 * EEPROM contents to the specific channel number supported for each
83 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
84 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
85 * The specific geography and calibration information for that channel
86 * is contained in the eeprom map itself.
88 * During init, we copy the eeprom information and channel map
89 * information into priv->channel_info_24/52 and priv->channel_map_24/52
91 * channel_map_24/52 provides the index in the channel_info array for a
92 * given channel. We have to have two separate maps as there is channel
93 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
96 * A value of 0xff stored in the channel_map indicates that the channel
97 * is not supported by the hardware at all.
99 * A value of 0xfe in the channel_map indicates that the channel is not
100 * valid for Tx with the current hardware. This means that
101 * while the system can tune and receive on a given channel, it may not
102 * be able to associate or transmit any frames on that
103 * channel. There is no corresponding channel information for that
106 *********************************************************************/
109 const u8 iwl_eeprom_band_1[14] = {
110 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
114 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
115 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
118 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
119 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
122 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
123 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
126 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
127 145, 149, 153, 157, 161, 165
130 static const u8 iwl_eeprom_band_6[] = { /* 2.4 FAT channel */
134 static const u8 iwl_eeprom_band_7[] = { /* 5.2 FAT channel */
135 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
138 /******************************************************************************
140 * EEPROM related functions
142 ******************************************************************************/
144 int iwlcore_eeprom_verify_signature(struct iwl_priv *priv)
146 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
147 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
148 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
153 EXPORT_SYMBOL(iwlcore_eeprom_verify_signature);
155 static int iwlcore_get_nvm_type(struct iwl_priv *priv)
160 /* OTP only valid for CP/PP and after */
161 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
162 case CSR_HW_REV_TYPE_NONE:
163 IWL_ERR(priv, "Unknown hardware type\n");
165 case CSR_HW_REV_TYPE_3945:
166 case CSR_HW_REV_TYPE_4965:
167 case CSR_HW_REV_TYPE_5300:
168 case CSR_HW_REV_TYPE_5350:
169 case CSR_HW_REV_TYPE_5100:
170 case CSR_HW_REV_TYPE_5150:
171 nvm_type = NVM_DEVICE_TYPE_EEPROM;
174 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
175 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
176 nvm_type = NVM_DEVICE_TYPE_OTP;
178 nvm_type = NVM_DEVICE_TYPE_EEPROM;
185 * The device's EEPROM semaphore prevents conflicts between driver and uCode
186 * when accessing the EEPROM; each access is a series of pulses to/from the
187 * EEPROM chip, not a single event, so even reads could conflict if they
188 * weren't arbitrated by the semaphore.
190 int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv)
195 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
196 /* Request semaphore */
197 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
198 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
200 /* See if we got it */
201 ret = iwl_poll_direct_bit(priv, CSR_HW_IF_CONFIG_REG,
202 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
205 IWL_DEBUG_IO(priv, "Acquired semaphore after %d tries.\n",
213 EXPORT_SYMBOL(iwlcore_eeprom_acquire_semaphore);
215 void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv)
217 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
218 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
221 EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore);
223 const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
225 BUG_ON(offset >= priv->cfg->eeprom_size);
226 return &priv->eeprom[offset];
228 EXPORT_SYMBOL(iwlcore_eeprom_query_addr);
230 static int iwl_init_otp_access(struct iwl_priv *priv)
234 /* Enable 40MHz radio clock */
235 _iwl_write32(priv, CSR_GP_CNTRL,
236 _iwl_read32(priv, CSR_GP_CNTRL) |
237 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
239 /* wait for clock to be ready */
240 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
241 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
244 IWL_ERR(priv, "Time out access OTP\n");
246 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
247 APMG_PS_CTRL_VAL_RESET_REQ);
249 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
250 APMG_PS_CTRL_VAL_RESET_REQ);
256 * iwl_eeprom_init - read EEPROM contents
258 * Load the EEPROM contents from adapter into priv->eeprom
260 * NOTE: This routine uses the non-debug IO access functions.
262 int iwl_eeprom_init(struct iwl_priv *priv)
265 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
271 priv->nvm_device_type = iwlcore_get_nvm_type(priv);
272 if (priv->nvm_device_type == -ENOENT)
274 /* allocate eeprom */
275 if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
276 priv->cfg->eeprom_size =
277 OTP_BLOCK_SIZE * OTP_LOWER_BLOCKS_TOTAL;
278 sz = priv->cfg->eeprom_size;
279 priv->eeprom = kzalloc(sz, GFP_KERNEL);
284 e = (u16 *)priv->eeprom;
286 ret = priv->cfg->ops->lib->eeprom_ops.verify_signature(priv);
288 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
293 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
294 ret = priv->cfg->ops->lib->eeprom_ops.acquire_semaphore(priv);
296 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
300 if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
301 ret = iwl_init_otp_access(priv);
303 IWL_ERR(priv, "Failed to initialize OTP access.\n");
307 _iwl_write32(priv, CSR_EEPROM_GP,
308 iwl_read32(priv, CSR_EEPROM_GP) &
309 ~CSR_EEPROM_GP_IF_OWNER_MSK);
311 _iwl_write32(priv, CSR_OTP_GP_REG,
312 iwl_read32(priv, CSR_OTP_GP_REG) |
313 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
314 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
316 for (addr = 0; addr < sz; addr += sizeof(u16)) {
319 _iwl_write32(priv, CSR_EEPROM_REG,
320 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
322 ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
323 CSR_EEPROM_REG_READ_VALID_MSK,
324 IWL_EEPROM_ACCESS_TIMEOUT);
326 IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
329 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
330 /* check for ECC errors: */
331 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
332 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
333 /* stop in this case */
334 IWL_ERR(priv, "Uncorrectable OTP ECC error, Abort OTP read\n");
337 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
338 /* continue in this case */
339 _iwl_write32(priv, CSR_OTP_GP_REG,
340 iwl_read32(priv, CSR_OTP_GP_REG) |
341 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
342 IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
344 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
347 /* eeprom is an array of 16bit values */
348 for (addr = 0; addr < sz; addr += sizeof(u16)) {
351 _iwl_write32(priv, CSR_EEPROM_REG,
352 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
354 ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
355 CSR_EEPROM_REG_READ_VALID_MSK,
356 IWL_EEPROM_ACCESS_TIMEOUT);
358 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
361 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
362 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
367 priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv);
370 iwl_eeprom_free(priv);
374 EXPORT_SYMBOL(iwl_eeprom_init);
376 void iwl_eeprom_free(struct iwl_priv *priv)
381 EXPORT_SYMBOL(iwl_eeprom_free);
383 int iwl_eeprom_check_version(struct iwl_priv *priv)
388 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
389 calib_ver = priv->cfg->ops->lib->eeprom_ops.calib_version(priv);
391 if (eeprom_ver < priv->cfg->eeprom_ver ||
392 calib_ver < priv->cfg->eeprom_calib_ver)
397 IWL_ERR(priv, "Unsupported (too old) EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
398 eeprom_ver, priv->cfg->eeprom_ver,
399 calib_ver, priv->cfg->eeprom_calib_ver);
403 EXPORT_SYMBOL(iwl_eeprom_check_version);
405 const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
407 return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset);
409 EXPORT_SYMBOL(iwl_eeprom_query_addr);
411 u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
415 return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
417 EXPORT_SYMBOL(iwl_eeprom_query16);
419 void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac)
421 const u8 *addr = priv->cfg->ops->lib->eeprom_ops.query_addr(priv,
423 memcpy(mac, addr, ETH_ALEN);
425 EXPORT_SYMBOL(iwl_eeprom_get_mac);
427 static void iwl_init_band_reference(const struct iwl_priv *priv,
428 int eep_band, int *eeprom_ch_count,
429 const struct iwl_eeprom_channel **eeprom_ch_info,
430 const u8 **eeprom_ch_index)
432 u32 offset = priv->cfg->ops->lib->
433 eeprom_ops.regulatory_bands[eep_band - 1];
435 case 1: /* 2.4GHz band */
436 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
437 *eeprom_ch_info = (struct iwl_eeprom_channel *)
438 iwl_eeprom_query_addr(priv, offset);
439 *eeprom_ch_index = iwl_eeprom_band_1;
441 case 2: /* 4.9GHz band */
442 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
443 *eeprom_ch_info = (struct iwl_eeprom_channel *)
444 iwl_eeprom_query_addr(priv, offset);
445 *eeprom_ch_index = iwl_eeprom_band_2;
447 case 3: /* 5.2GHz band */
448 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
449 *eeprom_ch_info = (struct iwl_eeprom_channel *)
450 iwl_eeprom_query_addr(priv, offset);
451 *eeprom_ch_index = iwl_eeprom_band_3;
453 case 4: /* 5.5GHz band */
454 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
455 *eeprom_ch_info = (struct iwl_eeprom_channel *)
456 iwl_eeprom_query_addr(priv, offset);
457 *eeprom_ch_index = iwl_eeprom_band_4;
459 case 5: /* 5.7GHz band */
460 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
461 *eeprom_ch_info = (struct iwl_eeprom_channel *)
462 iwl_eeprom_query_addr(priv, offset);
463 *eeprom_ch_index = iwl_eeprom_band_5;
465 case 6: /* 2.4GHz FAT channels */
466 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
467 *eeprom_ch_info = (struct iwl_eeprom_channel *)
468 iwl_eeprom_query_addr(priv, offset);
469 *eeprom_ch_index = iwl_eeprom_band_6;
471 case 7: /* 5 GHz FAT channels */
472 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
473 *eeprom_ch_info = (struct iwl_eeprom_channel *)
474 iwl_eeprom_query_addr(priv, offset);
475 *eeprom_ch_index = iwl_eeprom_band_7;
483 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
487 * iwl_set_fat_chan_info - Copy fat channel info into driver's priv.
489 * Does not set up a command, or touch hardware.
491 static int iwl_set_fat_chan_info(struct iwl_priv *priv,
492 enum ieee80211_band band, u16 channel,
493 const struct iwl_eeprom_channel *eeprom_ch,
494 u8 fat_extension_channel)
496 struct iwl_channel_info *ch_info;
498 ch_info = (struct iwl_channel_info *)
499 iwl_get_channel_info(priv, band, channel);
501 if (!is_channel_valid(ch_info))
504 IWL_DEBUG_INFO(priv, "FAT Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
505 " Ad-Hoc %ssupported\n",
507 is_channel_a_band(ch_info) ?
509 CHECK_AND_PRINT(IBSS),
510 CHECK_AND_PRINT(ACTIVE),
511 CHECK_AND_PRINT(RADAR),
512 CHECK_AND_PRINT(WIDE),
513 CHECK_AND_PRINT(DFS),
515 eeprom_ch->max_power_avg,
516 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
517 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
520 ch_info->fat_eeprom = *eeprom_ch;
521 ch_info->fat_max_power_avg = eeprom_ch->max_power_avg;
522 ch_info->fat_curr_txpow = eeprom_ch->max_power_avg;
523 ch_info->fat_min_power = 0;
524 ch_info->fat_scan_power = eeprom_ch->max_power_avg;
525 ch_info->fat_flags = eeprom_ch->flags;
526 ch_info->fat_extension_channel = fat_extension_channel;
531 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
535 * iwl_init_channel_map - Set up driver's info for all possible channels
537 int iwl_init_channel_map(struct iwl_priv *priv)
539 int eeprom_ch_count = 0;
540 const u8 *eeprom_ch_index = NULL;
541 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
543 struct iwl_channel_info *ch_info;
545 if (priv->channel_count) {
546 IWL_DEBUG_INFO(priv, "Channel map already initialized.\n");
550 IWL_DEBUG_INFO(priv, "Initializing regulatory info from EEPROM\n");
552 priv->channel_count =
553 ARRAY_SIZE(iwl_eeprom_band_1) +
554 ARRAY_SIZE(iwl_eeprom_band_2) +
555 ARRAY_SIZE(iwl_eeprom_band_3) +
556 ARRAY_SIZE(iwl_eeprom_band_4) +
557 ARRAY_SIZE(iwl_eeprom_band_5);
559 IWL_DEBUG_INFO(priv, "Parsing data for %d channels.\n", priv->channel_count);
561 priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
562 priv->channel_count, GFP_KERNEL);
563 if (!priv->channel_info) {
564 IWL_ERR(priv, "Could not allocate channel_info\n");
565 priv->channel_count = 0;
569 ch_info = priv->channel_info;
571 /* Loop through the 5 EEPROM bands adding them in order to the
572 * channel map we maintain (that contains additional information than
573 * what just in the EEPROM) */
574 for (band = 1; band <= 5; band++) {
576 iwl_init_band_reference(priv, band, &eeprom_ch_count,
577 &eeprom_ch_info, &eeprom_ch_index);
579 /* Loop through each band adding each of the channels */
580 for (ch = 0; ch < eeprom_ch_count; ch++) {
581 ch_info->channel = eeprom_ch_index[ch];
582 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
585 /* permanently store EEPROM's channel regulatory flags
586 * and max power in channel info database. */
587 ch_info->eeprom = eeprom_ch_info[ch];
589 /* Copy the run-time flags so they are there even on
590 * invalid channels */
591 ch_info->flags = eeprom_ch_info[ch].flags;
592 /* First write that fat is not enabled, and then enable
594 ch_info->fat_extension_channel =
595 (IEEE80211_CHAN_NO_HT40PLUS |
596 IEEE80211_CHAN_NO_HT40MINUS);
598 if (!(is_channel_valid(ch_info))) {
599 IWL_DEBUG_INFO(priv, "Ch. %d Flags %x [%sGHz] - "
603 is_channel_a_band(ch_info) ?
609 /* Initialize regulatory-based run-time data */
610 ch_info->max_power_avg = ch_info->curr_txpow =
611 eeprom_ch_info[ch].max_power_avg;
612 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
613 ch_info->min_power = 0;
615 IWL_DEBUG_INFO(priv, "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm):"
616 " Ad-Hoc %ssupported\n",
618 is_channel_a_band(ch_info) ?
620 CHECK_AND_PRINT_I(VALID),
621 CHECK_AND_PRINT_I(IBSS),
622 CHECK_AND_PRINT_I(ACTIVE),
623 CHECK_AND_PRINT_I(RADAR),
624 CHECK_AND_PRINT_I(WIDE),
625 CHECK_AND_PRINT_I(DFS),
626 eeprom_ch_info[ch].flags,
627 eeprom_ch_info[ch].max_power_avg,
628 ((eeprom_ch_info[ch].
629 flags & EEPROM_CHANNEL_IBSS)
630 && !(eeprom_ch_info[ch].
631 flags & EEPROM_CHANNEL_RADAR))
634 /* Set the tx_power_user_lmt to the highest power
635 * supported by any channel */
636 if (eeprom_ch_info[ch].max_power_avg >
637 priv->tx_power_user_lmt)
638 priv->tx_power_user_lmt =
639 eeprom_ch_info[ch].max_power_avg;
645 /* Check if we do have FAT channels */
646 if (priv->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
647 EEPROM_REGULATORY_BAND_NO_FAT &&
648 priv->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
649 EEPROM_REGULATORY_BAND_NO_FAT)
652 /* Two additional EEPROM bands for 2.4 and 5 GHz FAT channels */
653 for (band = 6; band <= 7; band++) {
654 enum ieee80211_band ieeeband;
655 u8 fat_extension_chan;
657 iwl_init_band_reference(priv, band, &eeprom_ch_count,
658 &eeprom_ch_info, &eeprom_ch_index);
660 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
662 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
664 /* Loop through each band adding each of the channels */
665 for (ch = 0; ch < eeprom_ch_count; ch++) {
668 ((eeprom_ch_index[ch] == 5) ||
669 (eeprom_ch_index[ch] == 6) ||
670 (eeprom_ch_index[ch] == 7)))
671 /* both are allowed: above and below */
672 fat_extension_chan = 0;
675 IEEE80211_CHAN_NO_HT40MINUS;
677 /* Set up driver's info for lower half */
678 iwl_set_fat_chan_info(priv, ieeeband,
680 &(eeprom_ch_info[ch]),
683 /* Set up driver's info for upper half */
684 iwl_set_fat_chan_info(priv, ieeeband,
685 (eeprom_ch_index[ch] + 4),
686 &(eeprom_ch_info[ch]),
687 IEEE80211_CHAN_NO_HT40PLUS);
693 EXPORT_SYMBOL(iwl_init_channel_map);
696 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
698 void iwl_free_channel_map(struct iwl_priv *priv)
700 kfree(priv->channel_info);
701 priv->channel_count = 0;
703 EXPORT_SYMBOL(iwl_free_channel_map);
706 * iwl_get_channel_info - Find driver's private channel info
708 * Based on band and channel number.
710 const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
711 enum ieee80211_band band, u16 channel)
716 case IEEE80211_BAND_5GHZ:
717 for (i = 14; i < priv->channel_count; i++) {
718 if (priv->channel_info[i].channel == channel)
719 return &priv->channel_info[i];
722 case IEEE80211_BAND_2GHZ:
723 if (channel >= 1 && channel <= 14)
724 return &priv->channel_info[channel - 1];
732 EXPORT_SYMBOL(iwl_get_channel_info);