1 /******************************************************************************
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/version.h>
32 #include <net/mac80211.h>
34 struct iwl_priv; /* FIXME: remove */
35 #include "iwl-debug.h"
36 #include "iwl-eeprom.h"
37 #include "iwl-dev.h" /* FIXME: remove */
40 #include "iwl-rfkill.h"
41 #include "iwl-power.h"
44 MODULE_DESCRIPTION("iwl core");
45 MODULE_VERSION(IWLWIFI_VERSION);
46 MODULE_AUTHOR(DRV_COPYRIGHT);
47 MODULE_LICENSE("GPL");
49 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
70 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
71 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
86 EXPORT_SYMBOL(iwl_rates);
89 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
90 EXPORT_SYMBOL(iwl_bcast_addr);
93 /* This function both allocates and initializes hw and priv. */
94 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
95 struct ieee80211_ops *hw_ops)
97 struct iwl_priv *priv;
99 /* mac80211 allocates memory for this device instance, including
100 * space for this driver's private structure */
101 struct ieee80211_hw *hw =
102 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
104 IWL_ERROR("Can not allocate network device\n");
114 EXPORT_SYMBOL(iwl_alloc_all);
116 void iwl_hw_detect(struct iwl_priv *priv)
118 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
119 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
120 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
122 EXPORT_SYMBOL(iwl_hw_detect);
124 /* Tell nic where to find the "keep warm" buffer */
125 int iwl_kw_init(struct iwl_priv *priv)
130 spin_lock_irqsave(&priv->lock, flags);
131 ret = iwl_grab_nic_access(priv);
135 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
136 priv->kw.dma_addr >> 4);
137 iwl_release_nic_access(priv);
139 spin_unlock_irqrestore(&priv->lock, flags);
143 int iwl_kw_alloc(struct iwl_priv *priv)
145 struct pci_dev *dev = priv->pci_dev;
146 struct iwl_kw *kw = &priv->kw;
148 kw->size = IWL_KW_SIZE;
149 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
157 * iwl_kw_free - Free the "keep warm" buffer
159 void iwl_kw_free(struct iwl_priv *priv)
161 struct pci_dev *dev = priv->pci_dev;
162 struct iwl_kw *kw = &priv->kw;
165 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
166 memset(kw, 0, sizeof(*kw));
170 int iwl_hw_nic_init(struct iwl_priv *priv)
173 struct iwl_rx_queue *rxq = &priv->rxq;
177 spin_lock_irqsave(&priv->lock, flags);
178 priv->cfg->ops->lib->apm_ops.init(priv);
179 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
180 spin_unlock_irqrestore(&priv->lock, flags);
182 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
184 priv->cfg->ops->lib->apm_ops.config(priv);
186 /* Allocate the RX queue, or reset if it is already allocated */
188 ret = iwl_rx_queue_alloc(priv);
190 IWL_ERROR("Unable to initialize Rx queue\n");
194 iwl_rx_queue_reset(priv, rxq);
196 iwl_rx_replenish(priv);
198 iwl_rx_init(priv, rxq);
200 spin_lock_irqsave(&priv->lock, flags);
202 rxq->need_update = 1;
203 iwl_rx_queue_update_write_ptr(priv, rxq);
205 spin_unlock_irqrestore(&priv->lock, flags);
207 /* Allocate and init all Tx and Command queues */
208 ret = iwl_txq_ctx_reset(priv);
212 set_bit(STATUS_INIT, &priv->status);
216 EXPORT_SYMBOL(iwl_hw_nic_init);
219 * iwlcore_clear_stations_table - Clear the driver's station table
221 * NOTE: This does not clear or otherwise alter the device's station table.
223 void iwlcore_clear_stations_table(struct iwl_priv *priv)
227 spin_lock_irqsave(&priv->sta_lock, flags);
229 priv->num_stations = 0;
230 memset(priv->stations, 0, sizeof(priv->stations));
232 spin_unlock_irqrestore(&priv->sta_lock, flags);
234 EXPORT_SYMBOL(iwlcore_clear_stations_table);
236 void iwl_reset_qos(struct iwl_priv *priv)
245 spin_lock_irqsave(&priv->lock, flags);
246 priv->qos_data.qos_active = 0;
248 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
249 if (priv->qos_data.qos_enable)
250 priv->qos_data.qos_active = 1;
251 if (!(priv->active_rate & 0xfff0)) {
255 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
256 if (priv->qos_data.qos_enable)
257 priv->qos_data.qos_active = 1;
258 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
263 if (priv->qos_data.qos_active)
266 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
267 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
268 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
269 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
270 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
272 if (priv->qos_data.qos_active) {
274 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
275 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
276 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
277 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
278 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
281 priv->qos_data.def_qos_parm.ac[i].cw_min =
282 cpu_to_le16((cw_min + 1) / 2 - 1);
283 priv->qos_data.def_qos_parm.ac[i].cw_max =
285 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
287 priv->qos_data.def_qos_parm.ac[i].edca_txop =
290 priv->qos_data.def_qos_parm.ac[i].edca_txop =
292 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
295 priv->qos_data.def_qos_parm.ac[i].cw_min =
296 cpu_to_le16((cw_min + 1) / 4 - 1);
297 priv->qos_data.def_qos_parm.ac[i].cw_max =
298 cpu_to_le16((cw_max + 1) / 2 - 1);
299 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
300 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
302 priv->qos_data.def_qos_parm.ac[i].edca_txop =
305 priv->qos_data.def_qos_parm.ac[i].edca_txop =
308 for (i = 1; i < 4; i++) {
309 priv->qos_data.def_qos_parm.ac[i].cw_min =
311 priv->qos_data.def_qos_parm.ac[i].cw_max =
313 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
314 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
315 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
318 IWL_DEBUG_QOS("set QoS to default \n");
320 spin_unlock_irqrestore(&priv->lock, flags);
322 EXPORT_SYMBOL(iwl_reset_qos);
324 #ifdef CONFIG_IWL4965_HT
325 #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
326 #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
327 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
328 struct ieee80211_ht_info *ht_info,
329 enum ieee80211_band band)
331 u16 max_bit_rate = 0;
332 u8 rx_chains_num = priv->hw_params.rx_chains_num;
333 u8 tx_chains_num = priv->hw_params.tx_chains_num;
336 memset(ht_info->supp_mcs_set, 0, 16);
338 ht_info->ht_supported = 1;
340 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
341 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
342 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
343 (IWL_MIMO_PS_NONE << 2));
345 max_bit_rate = MAX_BIT_RATE_20_MHZ;
346 if (priv->hw_params.fat_channel & BIT(band)) {
347 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
348 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
349 ht_info->supp_mcs_set[4] = 0x01;
350 max_bit_rate = MAX_BIT_RATE_40_MHZ;
353 if (priv->cfg->mod_params->amsdu_size_8K)
354 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
356 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
357 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
359 ht_info->supp_mcs_set[0] = 0xFF;
360 if (rx_chains_num >= 2)
361 ht_info->supp_mcs_set[1] = 0xFF;
362 if (rx_chains_num >= 3)
363 ht_info->supp_mcs_set[2] = 0xFF;
365 /* Highest supported Rx data rate */
366 max_bit_rate *= rx_chains_num;
367 ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
368 ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
370 /* Tx MCS capabilities */
371 ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
372 if (tx_chains_num != rx_chains_num) {
373 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
374 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
378 static inline void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
379 struct ieee80211_ht_info *ht_info,
380 enum ieee80211_band band)
383 #endif /* CONFIG_IWL4965_HT */
385 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
386 struct ieee80211_rate *rates)
390 for (i = 0; i < IWL_RATE_COUNT; i++) {
391 rates[i].bitrate = iwl_rates[i].ieee * 5;
392 rates[i].hw_value = i; /* Rate scaling will work on indexes */
393 rates[i].hw_value_short = i;
395 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
397 * If CCK != 1M then set short preamble rate flag.
400 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
401 0 : IEEE80211_RATE_SHORT_PREAMBLE;
407 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
409 static int iwlcore_init_geos(struct iwl_priv *priv)
411 struct iwl_channel_info *ch;
412 struct ieee80211_supported_band *sband;
413 struct ieee80211_channel *channels;
414 struct ieee80211_channel *geo_ch;
415 struct ieee80211_rate *rates;
418 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
419 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
420 IWL_DEBUG_INFO("Geography modes already initialized.\n");
421 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
425 channels = kzalloc(sizeof(struct ieee80211_channel) *
426 priv->channel_count, GFP_KERNEL);
430 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
437 /* 5.2GHz channels start after the 2.4GHz channels */
438 sband = &priv->bands[IEEE80211_BAND_5GHZ];
439 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
441 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
442 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
444 iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
446 sband = &priv->bands[IEEE80211_BAND_2GHZ];
447 sband->channels = channels;
449 sband->bitrates = rates;
450 sband->n_bitrates = IWL_RATE_COUNT;
452 iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
454 priv->ieee_channels = channels;
455 priv->ieee_rates = rates;
457 iwlcore_init_hw_rates(priv, rates);
459 for (i = 0; i < priv->channel_count; i++) {
460 ch = &priv->channel_info[i];
462 /* FIXME: might be removed if scan is OK */
463 if (!is_channel_valid(ch))
466 if (is_channel_a_band(ch))
467 sband = &priv->bands[IEEE80211_BAND_5GHZ];
469 sband = &priv->bands[IEEE80211_BAND_2GHZ];
471 geo_ch = &sband->channels[sband->n_channels++];
473 geo_ch->center_freq =
474 ieee80211_channel_to_frequency(ch->channel);
475 geo_ch->max_power = ch->max_power_avg;
476 geo_ch->max_antenna_gain = 0xff;
477 geo_ch->hw_value = ch->channel;
479 if (is_channel_valid(ch)) {
480 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
481 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
483 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
484 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
486 if (ch->flags & EEPROM_CHANNEL_RADAR)
487 geo_ch->flags |= IEEE80211_CHAN_RADAR;
489 switch (ch->fat_extension_channel) {
490 case HT_IE_EXT_CHANNEL_ABOVE:
491 /* only above is allowed, disable below */
492 geo_ch->flags |= IEEE80211_CHAN_NO_FAT_BELOW;
494 case HT_IE_EXT_CHANNEL_BELOW:
495 /* only below is allowed, disable above */
496 geo_ch->flags |= IEEE80211_CHAN_NO_FAT_ABOVE;
498 case HT_IE_EXT_CHANNEL_NONE:
499 /* fat not allowed: disable both*/
500 geo_ch->flags |= (IEEE80211_CHAN_NO_FAT_ABOVE |
501 IEEE80211_CHAN_NO_FAT_BELOW);
503 case HT_IE_EXT_CHANNEL_MAX:
504 /* both above and below are permitted */
508 if (ch->max_power_avg > priv->max_channel_txpower_limit)
509 priv->max_channel_txpower_limit =
512 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
515 /* Save flags for reg domain usage */
516 geo_ch->orig_flags = geo_ch->flags;
518 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
519 ch->channel, geo_ch->center_freq,
520 is_channel_a_band(ch) ? "5.2" : "2.4",
521 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
522 "restricted" : "valid",
526 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
527 priv->cfg->sku & IWL_SKU_A) {
528 printk(KERN_INFO DRV_NAME
529 ": Incorrectly detected BG card as ABG. Please send "
530 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
531 priv->pci_dev->device, priv->pci_dev->subsystem_device);
532 priv->cfg->sku &= ~IWL_SKU_A;
535 printk(KERN_INFO DRV_NAME
536 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
537 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
538 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
541 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
547 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
549 static void iwlcore_free_geos(struct iwl_priv *priv)
551 kfree(priv->ieee_channels);
552 kfree(priv->ieee_rates);
553 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
556 #ifdef CONFIG_IWL4965_HT
557 static u8 is_single_rx_stream(struct iwl_priv *priv)
559 return !priv->current_ht_config.is_ht ||
560 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
561 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
562 priv->ps_mode == IWL_MIMO_PS_STATIC;
564 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
565 enum ieee80211_band band,
566 u16 channel, u8 extension_chan_offset)
568 const struct iwl_channel_info *ch_info;
570 ch_info = iwl_get_channel_info(priv, band, channel);
571 if (!is_channel_valid(ch_info))
574 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
577 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
578 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
584 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
585 struct ieee80211_ht_info *sta_ht_inf)
587 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
589 if ((!iwl_ht_conf->is_ht) ||
590 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
591 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
595 if ((!sta_ht_inf->ht_supported) ||
596 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
600 return iwl_is_channel_extension(priv, priv->band,
601 iwl_ht_conf->control_channel,
602 iwl_ht_conf->extension_chan_offset);
604 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
606 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
608 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
614 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
615 if (iwl_is_fat_tx_allowed(priv, NULL))
616 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
618 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
619 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
621 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
622 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
623 le16_to_cpu(rxon->channel),
624 ht_info->control_channel);
625 rxon->channel = cpu_to_le16(ht_info->control_channel);
629 /* Note: control channel is opposite of extension channel */
630 switch (ht_info->extension_chan_offset) {
631 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
632 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
634 case IWL_EXT_CHANNEL_OFFSET_BELOW:
635 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
637 case IWL_EXT_CHANNEL_OFFSET_NONE:
639 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
643 val = ht_info->ht_protection;
645 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
647 iwl_set_rxon_chain(priv);
649 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
650 "rxon flags 0x%X operation mode :0x%X "
651 "extension channel offset 0x%x "
653 ht_info->supp_mcs_set[0],
654 ht_info->supp_mcs_set[1],
655 ht_info->supp_mcs_set[2],
656 le32_to_cpu(rxon->flags), ht_info->ht_protection,
657 ht_info->extension_chan_offset,
658 ht_info->control_channel);
661 EXPORT_SYMBOL(iwl_set_rxon_ht);
664 static inline u8 is_single_rx_stream(struct iwl_priv *priv)
668 #endif /*CONFIG_IWL4965_HT */
671 * Determine how many receiver/antenna chains to use.
672 * More provides better reception via diversity. Fewer saves power.
673 * MIMO (dual stream) requires at least 2, but works better with 3.
674 * This does not determine *which* chains to use, just how many.
676 static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
677 u8 *idle_state, u8 *rx_state)
679 u8 is_single = is_single_rx_stream(priv);
680 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
682 /* # of Rx chains to use when expecting MIMO. */
683 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
688 /* # Rx chains when idling and maybe trying to save power */
689 switch (priv->ps_mode) {
690 case IWL_MIMO_PS_STATIC:
691 case IWL_MIMO_PS_DYNAMIC:
692 *idle_state = (is_cam) ? 2 : 1;
694 case IWL_MIMO_PS_NONE:
695 *idle_state = (is_cam) ? *rx_state : 1;
706 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
708 * Selects how many and which Rx receivers/antennas/chains to use.
709 * This should not be used for scan command ... it puts data in wrong place.
711 void iwl_set_rxon_chain(struct iwl_priv *priv)
713 u8 is_single = is_single_rx_stream(priv);
714 u8 idle_state, rx_state;
716 priv->staging_rxon.rx_chain = 0;
717 rx_state = idle_state = 3;
719 /* Tell uCode which antennas are actually connected.
720 * Before first association, we assume all antennas are connected.
721 * Just after first association, iwl_chain_noise_calibration()
722 * checks which antennas actually *are* connected. */
723 priv->staging_rxon.rx_chain |=
724 cpu_to_le16(priv->hw_params.valid_rx_ant <<
725 RXON_RX_CHAIN_VALID_POS);
727 /* How many receivers should we use? */
728 iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
729 priv->staging_rxon.rx_chain |=
730 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
731 priv->staging_rxon.rx_chain |=
732 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
734 if (!is_single && (rx_state >= 2) &&
735 !test_bit(STATUS_POWER_PMI, &priv->status))
736 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
738 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
740 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
742 EXPORT_SYMBOL(iwl_set_rxon_chain);
745 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
746 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
747 * @channel: Any channel valid for the requested phymode
749 * In addition to setting the staging RXON, priv->phymode is also set.
751 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
752 * in the staging RXON flag structure based on the phymode
754 int iwl_set_rxon_channel(struct iwl_priv *priv,
755 enum ieee80211_band band,
758 if (!iwl_get_channel_info(priv, band, channel)) {
759 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
764 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
765 (priv->band == band))
768 priv->staging_rxon.channel = cpu_to_le16(channel);
769 if (band == IEEE80211_BAND_5GHZ)
770 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
772 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
776 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
780 EXPORT_SYMBOL(iwl_set_rxon_channel);
782 int iwl_setup_mac(struct iwl_priv *priv)
785 struct ieee80211_hw *hw = priv->hw;
786 hw->rate_control_algorithm = "iwl-4965-rs";
788 /* Tell mac80211 our characteristics */
789 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
790 IEEE80211_HW_SIGNAL_DBM |
791 IEEE80211_HW_NOISE_DBM;
792 /* Default value; 4 EDCA QOS priorities */
794 #ifdef CONFIG_IWL4965_HT
795 /* Enhanced value; more queues, to support 11n aggregation */
796 hw->ampdu_queues = 12;
797 #endif /* CONFIG_IWL4965_HT */
799 hw->conf.beacon_int = 100;
801 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
802 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
803 &priv->bands[IEEE80211_BAND_2GHZ];
804 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
805 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
806 &priv->bands[IEEE80211_BAND_5GHZ];
808 ret = ieee80211_register_hw(priv->hw);
810 IWL_ERROR("Failed to register hw (error %d)\n", ret);
813 priv->mac80211_registered = 1;
817 EXPORT_SYMBOL(iwl_setup_mac);
820 int iwl_init_drv(struct iwl_priv *priv)
825 priv->retry_rate = 1;
826 priv->ibss_beacon = NULL;
828 spin_lock_init(&priv->lock);
829 spin_lock_init(&priv->power_data.lock);
830 spin_lock_init(&priv->sta_lock);
831 spin_lock_init(&priv->hcmd_lock);
832 spin_lock_init(&priv->lq_mngr.lock);
834 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
835 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
837 INIT_LIST_HEAD(&priv->free_frames);
839 mutex_init(&priv->mutex);
841 /* Clear the driver's (not device's) station table */
842 iwlcore_clear_stations_table(priv);
844 priv->data_retry_limit = -1;
845 priv->ieee_channels = NULL;
846 priv->ieee_rates = NULL;
847 priv->band = IEEE80211_BAND_2GHZ;
849 priv->iw_mode = IEEE80211_IF_TYPE_STA;
851 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
852 priv->ps_mode = IWL_MIMO_PS_NONE;
854 /* Choose which receivers/antennas to use */
855 iwl_set_rxon_chain(priv);
857 if (priv->cfg->mod_params->enable_qos)
858 priv->qos_data.qos_enable = 1;
862 priv->qos_data.qos_active = 0;
863 priv->qos_data.qos_cap.val = 0;
865 iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
867 priv->rates_mask = IWL_RATES_MASK;
868 /* If power management is turned on, default to AC mode */
869 priv->power_mode = IWL_POWER_AC;
870 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
872 ret = iwl_init_channel_map(priv);
874 IWL_ERROR("initializing regulatory failed: %d\n", ret);
878 ret = iwlcore_init_geos(priv);
880 IWL_ERROR("initializing geos failed: %d\n", ret);
881 goto err_free_channel_map;
886 err_free_channel_map:
887 iwl_free_channel_map(priv);
891 EXPORT_SYMBOL(iwl_init_drv);
893 void iwl_free_calib_results(struct iwl_priv *priv)
895 kfree(priv->calib_results.lo_res);
896 priv->calib_results.lo_res = NULL;
897 priv->calib_results.lo_res_len = 0;
899 kfree(priv->calib_results.tx_iq_res);
900 priv->calib_results.tx_iq_res = NULL;
901 priv->calib_results.tx_iq_res_len = 0;
903 kfree(priv->calib_results.tx_iq_perd_res);
904 priv->calib_results.tx_iq_perd_res = NULL;
905 priv->calib_results.tx_iq_perd_res_len = 0;
907 EXPORT_SYMBOL(iwl_free_calib_results);
909 void iwl_uninit_drv(struct iwl_priv *priv)
911 iwl_free_calib_results(priv);
912 iwlcore_free_geos(priv);
913 iwl_free_channel_map(priv);
915 EXPORT_SYMBOL(iwl_uninit_drv);
917 /* Low level driver call this function to update iwlcore with
920 int iwlcore_low_level_notify(struct iwl_priv *priv,
921 enum iwlcore_card_notify notify)
925 case IWLCORE_INIT_EVT:
926 ret = iwl_rfkill_init(priv);
928 IWL_ERROR("Unable to initialize RFKILL system. "
929 "Ignoring error: %d\n", ret);
930 iwl_power_initialize(priv);
932 case IWLCORE_START_EVT:
933 iwl_power_update_mode(priv, 1);
935 case IWLCORE_STOP_EVT:
937 case IWLCORE_REMOVE_EVT:
938 iwl_rfkill_unregister(priv);
944 EXPORT_SYMBOL(iwlcore_low_level_notify);
946 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
949 struct iwl_host_cmd cmd = {
950 .id = REPLY_STATISTICS_CMD,
952 .len = sizeof(stat_flags),
953 .data = (u8 *) &stat_flags,
955 return iwl_send_cmd(priv, &cmd);
957 EXPORT_SYMBOL(iwl_send_statistics_request);
960 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
961 * using sample data 100 bytes apart. If these sample points are good,
962 * it's a pretty good bet that everything between them is good, too.
964 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
971 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
973 ret = iwl_grab_nic_access(priv);
977 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
978 /* read data comes through single port, auto-incr addr */
979 /* NOTE: Use the debugless read so we don't flood kernel log
980 * if IWL_DL_IO is set */
981 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
982 i + RTC_INST_LOWER_BOUND);
983 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
984 if (val != le32_to_cpu(*image)) {
992 iwl_release_nic_access(priv);
998 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
999 * looking at all data.
1001 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1009 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1011 ret = iwl_grab_nic_access(priv);
1015 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1018 for (; len > 0; len -= sizeof(u32), image++) {
1019 /* read data comes through single port, auto-incr addr */
1020 /* NOTE: Use the debugless read so we don't flood kernel log
1021 * if IWL_DL_IO is set */
1022 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1023 if (val != le32_to_cpu(*image)) {
1024 IWL_ERROR("uCode INST section is invalid at "
1025 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1026 save_len - len, val, le32_to_cpu(*image));
1034 iwl_release_nic_access(priv);
1038 ("ucode image in INSTRUCTION memory is good\n");
1044 * iwl_verify_ucode - determine which instruction image is in SRAM,
1045 * and verify its contents
1047 int iwl_verify_ucode(struct iwl_priv *priv)
1054 image = (__le32 *)priv->ucode_boot.v_addr;
1055 len = priv->ucode_boot.len;
1056 ret = iwlcore_verify_inst_sparse(priv, image, len);
1058 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1062 /* Try initialize */
1063 image = (__le32 *)priv->ucode_init.v_addr;
1064 len = priv->ucode_init.len;
1065 ret = iwlcore_verify_inst_sparse(priv, image, len);
1067 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1071 /* Try runtime/protocol */
1072 image = (__le32 *)priv->ucode_code.v_addr;
1073 len = priv->ucode_code.len;
1074 ret = iwlcore_verify_inst_sparse(priv, image, len);
1076 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1080 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1082 /* Since nothing seems to match, show first several data entries in
1083 * instruction SRAM, so maybe visual inspection will give a clue.
1084 * Selection of bootstrap image (vs. other images) is arbitrary. */
1085 image = (__le32 *)priv->ucode_boot.v_addr;
1086 len = priv->ucode_boot.len;
1087 ret = iwl_verify_inst_full(priv, image, len);
1091 EXPORT_SYMBOL(iwl_verify_ucode);
1094 static const char *desc_lookup(int i)
1102 return "BAD_CHECKSUM";
1104 return "NMI_INTERRUPT";
1108 return "FATAL_ERROR";
1114 #define ERROR_START_OFFSET (1 * sizeof(u32))
1115 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1117 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1120 u32 desc, time, count, base, data1;
1121 u32 blink1, blink2, ilink1, ilink2;
1124 if (priv->ucode_type == UCODE_INIT)
1125 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1127 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1129 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1130 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1134 ret = iwl_grab_nic_access(priv);
1136 IWL_WARNING("Can not read from adapter at this time.\n");
1140 count = iwl_read_targ_mem(priv, base);
1142 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1143 IWL_ERROR("Start IWL Error Log Dump:\n");
1144 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1147 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1148 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1149 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1150 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1151 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1152 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1153 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1154 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1155 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1157 IWL_ERROR("Desc Time "
1158 "data1 data2 line\n");
1159 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1160 desc_lookup(desc), desc, time, data1, data2, line);
1161 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1162 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1165 iwl_release_nic_access(priv);
1167 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1169 #define EVENT_START_OFFSET (4 * sizeof(u32))
1172 * iwl_print_event_log - Dump error event log to syslog
1174 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1176 void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1177 u32 num_events, u32 mode)
1180 u32 base; /* SRAM byte address of event log header */
1181 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1182 u32 ptr; /* SRAM byte address of log data */
1183 u32 ev, time, data; /* event log data */
1185 if (num_events == 0)
1187 if (priv->ucode_type == UCODE_INIT)
1188 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1190 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1193 event_size = 2 * sizeof(u32);
1195 event_size = 3 * sizeof(u32);
1197 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1199 /* "time" is actually "data" for mode 0 (no timestamp).
1200 * place event id # at far right for easier visual parsing. */
1201 for (i = 0; i < num_events; i++) {
1202 ev = iwl_read_targ_mem(priv, ptr);
1204 time = iwl_read_targ_mem(priv, ptr);
1207 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
1209 data = iwl_read_targ_mem(priv, ptr);
1211 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
1215 EXPORT_SYMBOL(iwl_print_event_log);
1218 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1221 u32 base; /* SRAM byte address of event log header */
1222 u32 capacity; /* event log capacity in # entries */
1223 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1224 u32 num_wraps; /* # times uCode wrapped to top of log */
1225 u32 next_entry; /* index of next entry to be written by uCode */
1226 u32 size; /* # entries that we'll print */
1228 if (priv->ucode_type == UCODE_INIT)
1229 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1231 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1233 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1234 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1238 ret = iwl_grab_nic_access(priv);
1240 IWL_WARNING("Can not read from adapter at this time.\n");
1244 /* event log header */
1245 capacity = iwl_read_targ_mem(priv, base);
1246 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1247 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1248 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1250 size = num_wraps ? capacity : next_entry;
1252 /* bail out if nothing in log */
1254 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1255 iwl_release_nic_access(priv);
1259 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1262 /* if uCode has wrapped back to top of log, start at the oldest entry,
1263 * i.e the next one that uCode would fill. */
1265 iwl_print_event_log(priv, next_entry,
1266 capacity - next_entry, mode);
1267 /* (then/else) start at top of log */
1268 iwl_print_event_log(priv, 0, next_entry, mode);
1270 iwl_release_nic_access(priv);
1272 EXPORT_SYMBOL(iwl_dump_nic_event_log);