drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62
  63
  64 /******************************************************************************
  65  *
  66  * module boiler plate
  67  *
  68  ******************************************************************************/
  69
  70 /*
  71  * module name, copyright, version, etc.
  72  */
  73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  74
  75 #ifdef CONFIG_IWLWIFI_DEBUG
  76 #define VD "d"
  77 #else
  78 #define VD
  79 #endif
  80
  81 #define DRV_VERSION     IWLWIFI_VERSION VD
  82
  83
  84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  85 MODULE_VERSION(DRV_VERSION);
  86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  87 MODULE_LICENSE("GPL");
  88
  89 static int iwlagn_ant_coupling;
  90 static bool iwlagn_bt_ch_announce = 1;
  91
  92 void iwl_update_chain_flags(struct iwl_priv *priv)
  93 {
  94         struct iwl_rxon_context *ctx;
  95
  96         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  97                 for_each_context(priv, ctx) {
  98                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  99                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 100                                 iwlcore_commit_rxon(priv, ctx);
 101                 }
 102         }
 103 }
 104
 105 static void iwl_clear_free_frames(struct iwl_priv *priv)
 106 {
 107         struct list_head *element;
 108
 109         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 110                        priv->frames_count);
 111
 112         while (!list_empty(&priv->free_frames)) {
 113                 element = priv->free_frames.next;
 114                 list_del(element);
 115                 kfree(list_entry(element, struct iwl_frame, list));
 116                 priv->frames_count--;
 117         }
 118
 119         if (priv->frames_count) {
 120                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 121                             priv->frames_count);
 122                 priv->frames_count = 0;
 123         }
 124 }
 125
 126 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 127 {
 128         struct iwl_frame *frame;
 129         struct list_head *element;
 130         if (list_empty(&priv->free_frames)) {
 131                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 132                 if (!frame) {
 133                         IWL_ERR(priv, "Could not allocate frame!\n");
 134                         return NULL;
 135                 }
 136
 137                 priv->frames_count++;
 138                 return frame;
 139         }
 140
 141         element = priv->free_frames.next;
 142         list_del(element);
 143         return list_entry(element, struct iwl_frame, list);
 144 }
 145
 146 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 147 {
 148         memset(frame, 0, sizeof(*frame));
 149         list_add(&frame->list, &priv->free_frames);
 150 }
 151
 152 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 153                                  struct ieee80211_hdr *hdr,
 154                                  int left)
 155 {
 156         lockdep_assert_held(&priv->mutex);
 157
 158         if (!priv->beacon_skb)
 159                 return 0;
 160
 161         if (priv->beacon_skb->len > left)
 162                 return 0;
 163
 164         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 165
 166         return priv->beacon_skb->len;
 167 }
 168
 169 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 170 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 171                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 172                                u8 *beacon, u32 frame_size)
 173 {
 174         u16 tim_idx;
 175         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 176
 177         /*
 178          * The index is relative to frame start but we start looking at the
 179          * variable-length part of the beacon.
 180          */
 181         tim_idx = mgmt->u.beacon.variable - beacon;
 182
 183         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 184         while ((tim_idx < (frame_size - 2)) &&
 185                         (beacon[tim_idx] != WLAN_EID_TIM))
 186                 tim_idx += beacon[tim_idx+1] + 2;
 187
 188         /* If TIM field was found, set variables */
 189         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 190                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 191                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 192         } else
 193                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 194 }
 195
 196 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 197                                        struct iwl_frame *frame)
 198 {
 199         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 200         u32 frame_size;
 201         u32 rate_flags;
 202         u32 rate;
 203         /*
 204          * We have to set up the TX command, the TX Beacon command, and the
 205          * beacon contents.
 206          */
 207
 208         lockdep_assert_held(&priv->mutex);
 209
 210         if (!priv->beacon_ctx) {
 211                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 212                 return 0;
 213         }
 214
 215         /* Initialize memory */
 216         tx_beacon_cmd = &frame->u.beacon;
 217         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 218
 219         /* Set up TX beacon contents */
 220         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 221                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 222         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 223                 return 0;
 224         if (!frame_size)
 225                 return 0;
 226
 227         /* Set up TX command fields */
 228         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 229         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 230         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 231         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 232                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 233
 234         /* Set up TX beacon command fields */
 235         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 236                            frame_size);
 237
 238         /* Set up packet rate and flags */
 239         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 240         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 241                                               priv->hw_params.valid_tx_ant);
 242         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 243         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 244                 rate_flags |= RATE_MCS_CCK_MSK;
 245         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 246                         rate_flags);
 247
 248         return sizeof(*tx_beacon_cmd) + frame_size;
 249 }
 250
 251 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 252 {
 253         struct iwl_frame *frame;
 254         unsigned int frame_size;
 255         int rc;
 256         struct iwl_host_cmd cmd = {
 257                 .id = REPLY_TX_BEACON,
 258                 .flags = CMD_SIZE_HUGE,
 259         };
 260
 261         frame = iwl_get_free_frame(priv);
 262         if (!frame) {
 263                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 264                           "command.\n");
 265                 return -ENOMEM;
 266         }
 267
 268         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 269         if (!frame_size) {
 270                 IWL_ERR(priv, "Error configuring the beacon command\n");
 271                 iwl_free_frame(priv, frame);
 272                 return -EINVAL;
 273         }
 274
 275         cmd.len = frame_size;
 276         cmd.data = &frame->u.cmd[0];
 277
 278         rc = iwl_send_cmd_sync(priv, &cmd);
 279
 280         iwl_free_frame(priv, frame);
 281
 282         return rc;
 283 }
 284
 285 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 286 {
 287         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 288
 289         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 290         if (sizeof(dma_addr_t) > sizeof(u32))
 291                 addr |=
 292                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 293
 294         return addr;
 295 }
 296
 297 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 298 {
 299         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 300
 301         return le16_to_cpu(tb->hi_n_len) >> 4;
 302 }
 303
 304 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 305                                   dma_addr_t addr, u16 len)
 306 {
 307         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 308         u16 hi_n_len = len << 4;
 309
 310         put_unaligned_le32(addr, &tb->lo);
 311         if (sizeof(dma_addr_t) > sizeof(u32))
 312                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 313
 314         tb->hi_n_len = cpu_to_le16(hi_n_len);
 315
 316         tfd->num_tbs = idx + 1;
 317 }
 318
 319 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 320 {
 321         return tfd->num_tbs & 0x1f;
 322 }
 323
 324 /**
 325  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 326  * @priv - driver private data
 327  * @txq - tx queue
 328  *
 329  * Does NOT advance any TFD circular buffer read/write indexes
 330  * Does NOT free the TFD itself (which is within circular buffer)
 331  */
 332 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 333 {
 334         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 335         struct iwl_tfd *tfd;
 336         struct pci_dev *dev = priv->pci_dev;
 337         int index = txq->q.read_ptr;
 338         int i;
 339         int num_tbs;
 340
 341         tfd = &tfd_tmp[index];
 342
 343         /* Sanity check on number of chunks */
 344         num_tbs = iwl_tfd_get_num_tbs(tfd);
 345
 346         if (num_tbs >= IWL_NUM_OF_TBS) {
 347                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 348                 /* @todo issue fatal error, it is quite serious situation */
 349                 return;
 350         }
 351
 352         /* Unmap tx_cmd */
 353         if (num_tbs)
 354                 pci_unmap_single(dev,
 355                                 dma_unmap_addr(&txq->meta[index], mapping),
 356                                 dma_unmap_len(&txq->meta[index], len),
 357                                 PCI_DMA_BIDIRECTIONAL);
 358
 359         /* Unmap chunks, if any. */
 360         for (i = 1; i < num_tbs; i++)
 361                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 362                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 363
 364         /* free SKB */
 365         if (txq->txb) {
 366                 struct sk_buff *skb;
 367
 368                 skb = txq->txb[txq->q.read_ptr].skb;
 369
 370                 /* can be called from irqs-disabled context */
 371                 if (skb) {
 372                         dev_kfree_skb_any(skb);
 373                         txq->txb[txq->q.read_ptr].skb = NULL;
 374                 }
 375         }
 376 }
 377
 378 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 379                                  struct iwl_tx_queue *txq,
 380                                  dma_addr_t addr, u16 len,
 381                                  u8 reset, u8 pad)
 382 {
 383         struct iwl_queue *q;
 384         struct iwl_tfd *tfd, *tfd_tmp;
 385         u32 num_tbs;
 386
 387         q = &txq->q;
 388         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 389         tfd = &tfd_tmp[q->write_ptr];
 390
 391         if (reset)
 392                 memset(tfd, 0, sizeof(*tfd));
 393
 394         num_tbs = iwl_tfd_get_num_tbs(tfd);
 395
 396         /* Each TFD can point to a maximum 20 Tx buffers */
 397         if (num_tbs >= IWL_NUM_OF_TBS) {
 398                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 399                           IWL_NUM_OF_TBS);
 400                 return -EINVAL;
 401         }
 402
 403         if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
 404                 return -EINVAL;
 405
 406         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 407                 IWL_ERR(priv, "Unaligned address = %llx\n",
 408                           (unsigned long long)addr);
 409
 410         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 411
 412         return 0;
 413 }
 414
 415 /*
 416  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 417  * given Tx queue, and enable the DMA channel used for that queue.
 418  *
 419  * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 420  * channels supported in hardware.
 421  */
 422 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 423                          struct iwl_tx_queue *txq)
 424 {
 425         int txq_id = txq->q.id;
 426
 427         /* Circular buffer (TFD queue in DRAM) physical base address */
 428         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 429                              txq->q.dma_addr >> 8);
 430
 431         return 0;
 432 }
 433
 434 static void iwl_bg_beacon_update(struct work_struct *work)
 435 {
 436         struct iwl_priv *priv =
 437                 container_of(work, struct iwl_priv, beacon_update);
 438         struct sk_buff *beacon;
 439
 440         mutex_lock(&priv->mutex);
 441         if (!priv->beacon_ctx) {
 442                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 443                 goto out;
 444         }
 445
 446         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 447                 /*
 448                  * The ucode will send beacon notifications even in
 449                  * IBSS mode, but we don't want to process them. But
 450                  * we need to defer the type check to here due to
 451                  * requiring locking around the beacon_ctx access.
 452                  */
 453                 goto out;
 454         }
 455
 456         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 457         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 458         if (!beacon) {
 459                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 460                 goto out;
 461         }
 462
 463         /* new beacon skb is allocated every time; dispose previous.*/
 464         dev_kfree_skb(priv->beacon_skb);
 465
 466         priv->beacon_skb = beacon;
 467
 468         iwlagn_send_beacon_cmd(priv);
 469  out:
 470         mutex_unlock(&priv->mutex);
 471 }
 472
 473 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 474 {
 475         struct iwl_priv *priv =
 476                 container_of(work, struct iwl_priv, bt_runtime_config);
 477
 478         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 479                 return;
 480
 481         /* dont send host command if rf-kill is on */
 482         if (!iwl_is_ready_rf(priv))
 483                 return;
 484         priv->cfg->ops->hcmd->send_bt_config(priv);
 485 }
 486
 487 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 488 {
 489         struct iwl_priv *priv =
 490                 container_of(work, struct iwl_priv, bt_full_concurrency);
 491         struct iwl_rxon_context *ctx;
 492
 493         mutex_lock(&priv->mutex);
 494
 495         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 496                 goto out;
 497
 498         /* dont send host command if rf-kill is on */
 499         if (!iwl_is_ready_rf(priv))
 500                 goto out;
 501
 502         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 503                        priv->bt_full_concurrent ?
 504                        "full concurrency" : "3-wire");
 505
 506         /*
 507          * LQ & RXON updated cmds must be sent before BT Config cmd
 508          * to avoid 3-wire collisions
 509          */
 510         for_each_context(priv, ctx) {
 511                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 512                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 513                 iwlcore_commit_rxon(priv, ctx);
 514         }
 515
 516         priv->cfg->ops->hcmd->send_bt_config(priv);
 517 out:
 518         mutex_unlock(&priv->mutex);
 519 }
 520
 521 /**
 522  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 523  *
 524  * This callback is provided in order to send a statistics request.
 525  *
 526  * This timer function is continually reset to execute within
 527  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 528  * was received.  We need to ensure we receive the statistics in order
 529  * to update the temperature used for calibrating the TXPOWER.
 530  */
 531 static void iwl_bg_statistics_periodic(unsigned long data)
 532 {
 533         struct iwl_priv *priv = (struct iwl_priv *)data;
 534
 535         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 536                 return;
 537
 538         /* dont send host command if rf-kill is on */
 539         if (!iwl_is_ready_rf(priv))
 540                 return;
 541
 542         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 543 }
 544
 545
 546 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 547                                         u32 start_idx, u32 num_events,
 548                                         u32 mode)
 549 {
 550         u32 i;
 551         u32 ptr;        /* SRAM byte address of log data */
 552         u32 ev, time, data; /* event log data */
 553         unsigned long reg_flags;
 554
 555         if (mode == 0)
 556                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 557         else
 558                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 559
 560         /* Make sure device is powered up for SRAM reads */
 561         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 562         if (iwl_grab_nic_access(priv)) {
 563                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 564                 return;
 565         }
 566
 567         /* Set starting address; reads will auto-increment */
 568         iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
 569         rmb();
 570
 571         /*
 572          * "time" is actually "data" for mode 0 (no timestamp).
 573          * place event id # at far right for easier visual parsing.
 574          */
 575         for (i = 0; i < num_events; i++) {
 576                 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 577                 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 578                 if (mode == 0) {
 579                         trace_iwlwifi_dev_ucode_cont_event(priv,
 580                                                         0, time, ev);
 581                 } else {
 582                         data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 583                         trace_iwlwifi_dev_ucode_cont_event(priv,
 584                                                 time, data, ev);
 585                 }
 586         }
 587         /* Allow device to power down */
 588         iwl_release_nic_access(priv);
 589         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 590 }
 591
 592 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 593 {
 594         u32 capacity;   /* event log capacity in # entries */
 595         u32 base;       /* SRAM byte address of event log header */
 596         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 597         u32 num_wraps;  /* # times uCode wrapped to top of log */
 598         u32 next_entry; /* index of next entry to be written by uCode */
 599
 600         base = priv->device_pointers.error_event_table;
 601         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 602                 capacity = iwl_read_targ_mem(priv, base);
 603                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 604                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 605                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 606         } else
 607                 return;
 608
 609         if (num_wraps == priv->event_log.num_wraps) {
 610                 iwl_print_cont_event_trace(priv,
 611                                        base, priv->event_log.next_entry,
 612                                        next_entry - priv->event_log.next_entry,
 613                                        mode);
 614                 priv->event_log.non_wraps_count++;
 615         } else {
 616                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 617                         priv->event_log.wraps_more_count++;
 618                 else
 619                         priv->event_log.wraps_once_count++;
 620                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 621                                 num_wraps - priv->event_log.num_wraps,
 622                                 next_entry, priv->event_log.next_entry);
 623                 if (next_entry < priv->event_log.next_entry) {
 624                         iwl_print_cont_event_trace(priv, base,
 625                                priv->event_log.next_entry,
 626                                capacity - priv->event_log.next_entry,
 627                                mode);
 628
 629                         iwl_print_cont_event_trace(priv, base, 0,
 630                                 next_entry, mode);
 631                 } else {
 632                         iwl_print_cont_event_trace(priv, base,
 633                                next_entry, capacity - next_entry,
 634                                mode);
 635
 636                         iwl_print_cont_event_trace(priv, base, 0,
 637                                 next_entry, mode);
 638                 }
 639         }
 640         priv->event_log.num_wraps = num_wraps;
 641         priv->event_log.next_entry = next_entry;
 642 }
 643
 644 /**
 645  * iwl_bg_ucode_trace - Timer callback to log ucode event
 646  *
 647  * The timer is continually set to execute every
 648  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 649  * this function is to perform continuous uCode event logging operation
 650  * if enabled
 651  */
 652 static void iwl_bg_ucode_trace(unsigned long data)
 653 {
 654         struct iwl_priv *priv = (struct iwl_priv *)data;
 655
 656         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 657                 return;
 658
 659         if (priv->event_log.ucode_trace) {
 660                 iwl_continuous_event_trace(priv);
 661                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 662                 mod_timer(&priv->ucode_trace,
 663                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 664         }
 665 }
 666
 667 static void iwl_bg_tx_flush(struct work_struct *work)
 668 {
 669         struct iwl_priv *priv =
 670                 container_of(work, struct iwl_priv, tx_flush);
 671
 672         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 673                 return;
 674
 675         /* do nothing if rf-kill is on */
 676         if (!iwl_is_ready_rf(priv))
 677                 return;
 678
 679         if (priv->cfg->ops->lib->txfifo_flush) {
 680                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 681                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 682         }
 683 }
 684
 685 /**
 686  * iwl_rx_handle - Main entry function for receiving responses from uCode
 687  *
 688  * Uses the priv->rx_handlers callback function array to invoke
 689  * the appropriate handlers, including command responses,
 690  * frame-received notifications, and other notifications.
 691  */
 692 static void iwl_rx_handle(struct iwl_priv *priv)
 693 {
 694         struct iwl_rx_mem_buffer *rxb;
 695         struct iwl_rx_packet *pkt;
 696         struct iwl_rx_queue *rxq = &priv->rxq;
 697         u32 r, i;
 698         int reclaim;
 699         unsigned long flags;
 700         u8 fill_rx = 0;
 701         u32 count = 8;
 702         int total_empty;
 703
 704         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 705          * buffer that the driver may process (last buffer filled by ucode). */
 706         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 707         i = rxq->read;
 708
 709         /* Rx interrupt, but nothing sent from uCode */
 710         if (i == r)
 711                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 712
 713         /* calculate total frames need to be restock after handling RX */
 714         total_empty = r - rxq->write_actual;
 715         if (total_empty < 0)
 716                 total_empty += RX_QUEUE_SIZE;
 717
 718         if (total_empty > (RX_QUEUE_SIZE / 2))
 719                 fill_rx = 1;
 720
 721         while (i != r) {
 722                 int len;
 723
 724                 rxb = rxq->queue[i];
 725
 726                 /* If an RXB doesn't have a Rx queue slot associated with it,
 727                  * then a bug has been introduced in the queue refilling
 728                  * routines -- catch it here */
 729                 if (WARN_ON(rxb == NULL)) {
 730                         i = (i + 1) & RX_QUEUE_MASK;
 731                         continue;
 732                 }
 733
 734                 rxq->queue[i] = NULL;
 735
 736                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 737                                PAGE_SIZE << priv->hw_params.rx_page_order,
 738                                PCI_DMA_FROMDEVICE);
 739                 pkt = rxb_addr(rxb);
 740
 741                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 742                 len += sizeof(u32); /* account for status word */
 743                 trace_iwlwifi_dev_rx(priv, pkt, len);
 744
 745                 /* Reclaim a command buffer only if this packet is a response
 746                  *   to a (driver-originated) command.
 747                  * If the packet (e.g. Rx frame) originated from uCode,
 748                  *   there is no command buffer to reclaim.
 749                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 750                  *   but apparently a few don't get set; catch them here. */
 751                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 752                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 753                         (pkt->hdr.cmd != REPLY_RX) &&
 754                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 755                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 756                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 757                         (pkt->hdr.cmd != REPLY_TX);
 758
 759                 /*
 760                  * Do the notification wait before RX handlers so
 761                  * even if the RX handler consumes the RXB we have
 762                  * access to it in the notification wait entry.
 763                  */
 764                 if (!list_empty(&priv->_agn.notif_waits)) {
 765                         struct iwl_notification_wait *w;
 766
 767                         spin_lock(&priv->_agn.notif_wait_lock);
 768                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 769                                 if (w->cmd == pkt->hdr.cmd) {
 770                                         w->triggered = true;
 771                                         if (w->fn)
 772                                                 w->fn(priv, pkt, w->fn_data);
 773                                 }
 774                         }
 775                         spin_unlock(&priv->_agn.notif_wait_lock);
 776
 777                         wake_up_all(&priv->_agn.notif_waitq);
 778                 }
 779
 780                 /* Based on type of command response or notification,
 781                  *   handle those that need handling via function in
 782                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 783                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 784                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 785                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 786                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 787                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 788                 } else {
 789                         /* No handling needed */
 790                         IWL_DEBUG_RX(priv,
 791                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 792                                 r, i, get_cmd_string(pkt->hdr.cmd),
 793                                 pkt->hdr.cmd);
 794                 }
 795
 796                 /*
 797                  * XXX: After here, we should always check rxb->page
 798                  * against NULL before touching it or its virtual
 799                  * memory (pkt). Because some rx_handler might have
 800                  * already taken or freed the pages.
 801                  */
 802
 803                 if (reclaim) {
 804                         /* Invoke any callbacks, transfer the buffer to caller,
 805                          * and fire off the (possibly) blocking iwl_send_cmd()
 806                          * as we reclaim the driver command queue */
 807                         if (rxb->page)
 808                                 iwl_tx_cmd_complete(priv, rxb);
 809                         else
 810                                 IWL_WARN(priv, "Claim null rxb?\n");
 811                 }
 812
 813                 /* Reuse the page if possible. For notification packets and
 814                  * SKBs that fail to Rx correctly, add them back into the
 815                  * rx_free list for reuse later. */
 816                 spin_lock_irqsave(&rxq->lock, flags);
 817                 if (rxb->page != NULL) {
 818                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 819                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 820                                 PCI_DMA_FROMDEVICE);
 821                         list_add_tail(&rxb->list, &rxq->rx_free);
 822                         rxq->free_count++;
 823                 } else
 824                         list_add_tail(&rxb->list, &rxq->rx_used);
 825
 826                 spin_unlock_irqrestore(&rxq->lock, flags);
 827
 828                 i = (i + 1) & RX_QUEUE_MASK;
 829                 /* If there are a lot of unused frames,
 830                  * restock the Rx queue so ucode wont assert. */
 831                 if (fill_rx) {
 832                         count++;
 833                         if (count >= 8) {
 834                                 rxq->read = i;
 835                                 iwlagn_rx_replenish_now(priv);
 836                                 count = 0;
 837                         }
 838                 }
 839         }
 840
 841         /* Backtrack one entry */
 842         rxq->read = i;
 843         if (fill_rx)
 844                 iwlagn_rx_replenish_now(priv);
 845         else
 846                 iwlagn_rx_queue_restock(priv);
 847 }
 848
 849 /* tasklet for iwlagn interrupt */
 850 static void iwl_irq_tasklet(struct iwl_priv *priv)
 851 {
 852         u32 inta = 0;
 853         u32 handled = 0;
 854         unsigned long flags;
 855         u32 i;
 856 #ifdef CONFIG_IWLWIFI_DEBUG
 857         u32 inta_mask;
 858 #endif
 859
 860         spin_lock_irqsave(&priv->lock, flags);
 861
 862         /* Ack/clear/reset pending uCode interrupts.
 863          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 864          */
 865         /* There is a hardware bug in the interrupt mask function that some
 866          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 867          * they are disabled in the CSR_INT_MASK register. Furthermore the
 868          * ICT interrupt handling mechanism has another bug that might cause
 869          * these unmasked interrupts fail to be detected. We workaround the
 870          * hardware bugs here by ACKing all the possible interrupts so that
 871          * interrupt coalescing can still be achieved.
 872          */
 873         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
 874
 875         inta = priv->_agn.inta;
 876
 877 #ifdef CONFIG_IWLWIFI_DEBUG
 878         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
 879                 /* just for debug */
 880                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
 881                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
 882                                 inta, inta_mask);
 883         }
 884 #endif
 885
 886         spin_unlock_irqrestore(&priv->lock, flags);
 887
 888         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
 889         priv->_agn.inta = 0;
 890
 891         /* Now service all interrupt bits discovered above. */
 892         if (inta & CSR_INT_BIT_HW_ERR) {
 893                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
 894
 895                 /* Tell the device to stop sending interrupts */
 896                 iwl_disable_interrupts(priv);
 897
 898                 priv->isr_stats.hw++;
 899                 iwl_irq_handle_error(priv);
 900
 901                 handled |= CSR_INT_BIT_HW_ERR;
 902
 903                 return;
 904         }
 905
 906 #ifdef CONFIG_IWLWIFI_DEBUG
 907         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
 908                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 909                 if (inta & CSR_INT_BIT_SCD) {
 910                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
 911                                       "the frame/frames.\n");
 912                         priv->isr_stats.sch++;
 913                 }
 914
 915                 /* Alive notification via Rx interrupt will do the real work */
 916                 if (inta & CSR_INT_BIT_ALIVE) {
 917                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
 918                         priv->isr_stats.alive++;
 919                 }
 920         }
 921 #endif
 922         /* Safely ignore these bits for debug checks below */
 923         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 924
 925         /* HW RF KILL switch toggled */
 926         if (inta & CSR_INT_BIT_RF_KILL) {
 927                 int hw_rf_kill = 0;
 928                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
 929                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
 930                         hw_rf_kill = 1;
 931
 932                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
 933                                 hw_rf_kill ? "disable radio" : "enable radio");
 934
 935                 priv->isr_stats.rfkill++;
 936
 937                 /* driver only loads ucode once setting the interface up.
 938                  * the driver allows loading the ucode even if the radio
 939                  * is killed. Hence update the killswitch state here. The
 940                  * rfkill handler will care about restarting if needed.
 941                  */
 942                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
 943                         if (hw_rf_kill)
 944                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 945                         else
 946                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 947                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
 948                 }
 949
 950                 handled |= CSR_INT_BIT_RF_KILL;
 951         }
 952
 953         /* Chip got too hot and stopped itself */
 954         if (inta & CSR_INT_BIT_CT_KILL) {
 955                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
 956                 priv->isr_stats.ctkill++;
 957                 handled |= CSR_INT_BIT_CT_KILL;
 958         }
 959
 960         /* Error detected by uCode */
 961         if (inta & CSR_INT_BIT_SW_ERR) {
 962                 IWL_ERR(priv, "Microcode SW error detected. "
 963                         " Restarting 0x%X.\n", inta);
 964                 priv->isr_stats.sw++;
 965                 iwl_irq_handle_error(priv);
 966                 handled |= CSR_INT_BIT_SW_ERR;
 967         }
 968
 969         /* uCode wakes up after power-down sleep */
 970         if (inta & CSR_INT_BIT_WAKEUP) {
 971                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
 972                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
 973                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
 974                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
 975
 976                 priv->isr_stats.wakeup++;
 977
 978                 handled |= CSR_INT_BIT_WAKEUP;
 979         }
 980
 981         /* All uCode command responses, including Tx command responses,
 982          * Rx "responses" (frame-received notification), and other
 983          * notifications from uCode come through here*/
 984         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 985                         CSR_INT_BIT_RX_PERIODIC)) {
 986                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
 987                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 988                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 989                         iwl_write32(priv, CSR_FH_INT_STATUS,
 990                                         CSR_FH_INT_RX_MASK);
 991                 }
 992                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 993                         handled |= CSR_INT_BIT_RX_PERIODIC;
 994                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 995                 }
 996                 /* Sending RX interrupt require many steps to be done in the
 997                  * the device:
 998                  * 1- write interrupt to current index in ICT table.
 999                  * 2- dma RX frame.
1000                  * 3- update RX shared data to indicate last write index.
1001                  * 4- send interrupt.
1002                  * This could lead to RX race, driver could receive RX interrupt
1003                  * but the shared data changes does not reflect this;
1004                  * periodic interrupt will detect any dangling Rx activity.
1005                  */
1006
1007                 /* Disable periodic interrupt; we use it as just a one-shot. */
1008                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1009                             CSR_INT_PERIODIC_DIS);
1010                 iwl_rx_handle(priv);
1011
1012                 /*
1013                  * Enable periodic interrupt in 8 msec only if we received
1014                  * real RX interrupt (instead of just periodic int), to catch
1015                  * any dangling Rx interrupt.  If it was just the periodic
1016                  * interrupt, there was no dangling Rx activity, and no need
1017                  * to extend the periodic interrupt; one-shot is enough.
1018                  */
1019                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1020                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1021                                     CSR_INT_PERIODIC_ENA);
1022
1023                 priv->isr_stats.rx++;
1024         }
1025
1026         /* This "Tx" DMA channel is used only for loading uCode */
1027         if (inta & CSR_INT_BIT_FH_TX) {
1028                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1029                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1030                 priv->isr_stats.tx++;
1031                 handled |= CSR_INT_BIT_FH_TX;
1032                 /* Wake up uCode load routine, now that load is complete */
1033                 priv->ucode_write_complete = 1;
1034                 wake_up_interruptible(&priv->wait_command_queue);
1035         }
1036
1037         if (inta & ~handled) {
1038                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1039                 priv->isr_stats.unhandled++;
1040         }
1041
1042         if (inta & ~(priv->inta_mask)) {
1043                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1044                          inta & ~priv->inta_mask);
1045         }
1046
1047         /* Re-enable all interrupts */
1048         /* only Re-enable if disabled by irq */
1049         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1050                 iwl_enable_interrupts(priv);
1051         /* Re-enable RF_KILL if it occurred */
1052         else if (handled & CSR_INT_BIT_RF_KILL)
1053                 iwl_enable_rfkill_int(priv);
1054 }
1055
1056 /*****************************************************************************
1057  *
1058  * sysfs attributes
1059  *
1060  *****************************************************************************/
1061
1062 #ifdef CONFIG_IWLWIFI_DEBUG
1063
1064 /*
1065  * The following adds a new attribute to the sysfs representation
1066  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1067  * used for controlling the debug level.
1068  *
1069  * See the level definitions in iwl for details.
1070  *
1071  * The debug_level being managed using sysfs below is a per device debug
1072  * level that is used instead of the global debug level if it (the per
1073  * device debug level) is set.
1074  */
1075 static ssize_t show_debug_level(struct device *d,
1076                                 struct device_attribute *attr, char *buf)
1077 {
1078         struct iwl_priv *priv = dev_get_drvdata(d);
1079         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1080 }
1081 static ssize_t store_debug_level(struct device *d,
1082                                 struct device_attribute *attr,
1083                                  const char *buf, size_t count)
1084 {
1085         struct iwl_priv *priv = dev_get_drvdata(d);
1086         unsigned long val;
1087         int ret;
1088
1089         ret = strict_strtoul(buf, 0, &val);
1090         if (ret)
1091                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1092         else {
1093                 priv->debug_level = val;
1094                 if (iwl_alloc_traffic_mem(priv))
1095                         IWL_ERR(priv,
1096                                 "Not enough memory to generate traffic log\n");
1097         }
1098         return strnlen(buf, count);
1099 }
1100
1101 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1102                         show_debug_level, store_debug_level);
1103
1104
1105 #endif /* CONFIG_IWLWIFI_DEBUG */
1106
1107
1108 static ssize_t show_temperature(struct device *d,
1109                                 struct device_attribute *attr, char *buf)
1110 {
1111         struct iwl_priv *priv = dev_get_drvdata(d);
1112
1113         if (!iwl_is_alive(priv))
1114                 return -EAGAIN;
1115
1116         return sprintf(buf, "%d\n", priv->temperature);
1117 }
1118
1119 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1120
1121 static ssize_t show_tx_power(struct device *d,
1122                              struct device_attribute *attr, char *buf)
1123 {
1124         struct iwl_priv *priv = dev_get_drvdata(d);
1125
1126         if (!iwl_is_ready_rf(priv))
1127                 return sprintf(buf, "off\n");
1128         else
1129                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1130 }
1131
1132 static ssize_t store_tx_power(struct device *d,
1133                               struct device_attribute *attr,
1134                               const char *buf, size_t count)
1135 {
1136         struct iwl_priv *priv = dev_get_drvdata(d);
1137         unsigned long val;
1138         int ret;
1139
1140         ret = strict_strtoul(buf, 10, &val);
1141         if (ret)
1142                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1143         else {
1144                 ret = iwl_set_tx_power(priv, val, false);
1145                 if (ret)
1146                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1147                                 ret);
1148                 else
1149                         ret = count;
1150         }
1151         return ret;
1152 }
1153
1154 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1155
1156 static struct attribute *iwl_sysfs_entries[] = {
1157         &dev_attr_temperature.attr,
1158         &dev_attr_tx_power.attr,
1159 #ifdef CONFIG_IWLWIFI_DEBUG
1160         &dev_attr_debug_level.attr,
1161 #endif
1162         NULL
1163 };
1164
1165 static struct attribute_group iwl_attribute_group = {
1166         .name = NULL,           /* put in device directory */
1167         .attrs = iwl_sysfs_entries,
1168 };
1169
1170 /******************************************************************************
1171  *
1172  * uCode download functions
1173  *
1174  ******************************************************************************/
1175
1176 static void iwl_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
1177 {
1178         if (desc->v_addr)
1179                 dma_free_coherent(&pci_dev->dev, desc->len,
1180                                   desc->v_addr, desc->p_addr);
1181         desc->v_addr = NULL;
1182         desc->len = 0;
1183 }
1184
1185 static void iwl_free_fw_img(struct pci_dev *pci_dev, struct fw_img *img)
1186 {
1187         iwl_free_fw_desc(pci_dev, &img->code);
1188         iwl_free_fw_desc(pci_dev, &img->data);
1189 }
1190
1191 static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc,
1192                              const void *data, size_t len)
1193 {
1194         if (!len) {
1195                 desc->v_addr = NULL;
1196                 return -EINVAL;
1197         }
1198
1199         desc->v_addr = dma_alloc_coherent(&pci_dev->dev, len,
1200                                           &desc->p_addr, GFP_KERNEL);
1201         if (!desc->v_addr)
1202                 return -ENOMEM;
1203         desc->len = len;
1204         memcpy(desc->v_addr, data, len);
1205         return 0;
1206 }
1207
1208 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1209 {
1210         iwl_free_fw_img(priv->pci_dev, &priv->ucode_rt);
1211         iwl_free_fw_img(priv->pci_dev, &priv->ucode_init);
1212 }
1213
1214 struct iwlagn_ucode_capabilities {
1215         u32 max_probe_length;
1216         u32 standard_phy_calibration_size;
1217         u32 flags;
1218 };
1219
1220 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1221 static int iwl_mac_setup_register(struct iwl_priv *priv,
1222                                   struct iwlagn_ucode_capabilities *capa);
1223
1224 #define UCODE_EXPERIMENTAL_INDEX        100
1225 #define UCODE_EXPERIMENTAL_TAG          "exp"
1226
1227 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1228 {
1229         const char *name_pre = priv->cfg->fw_name_pre;
1230         char tag[8];
1231
1232         if (first) {
1233 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1234                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1235                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1236         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1237 #endif
1238                 priv->fw_index = priv->cfg->ucode_api_max;
1239                 sprintf(tag, "%d", priv->fw_index);
1240         } else {
1241                 priv->fw_index--;
1242                 sprintf(tag, "%d", priv->fw_index);
1243         }
1244
1245         if (priv->fw_index < priv->cfg->ucode_api_min) {
1246                 IWL_ERR(priv, "no suitable firmware found!\n");
1247                 return -ENOENT;
1248         }
1249
1250         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1251
1252         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1253                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1254                                 ? "EXPERIMENTAL " : "",
1255                        priv->firmware_name);
1256
1257         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1258                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1259                                        iwl_ucode_callback);
1260 }
1261
1262 struct iwlagn_firmware_pieces {
1263         const void *inst, *data, *init, *init_data;
1264         size_t inst_size, data_size, init_size, init_data_size;
1265
1266         u32 build;
1267
1268         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1269         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1270 };
1271
1272 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1273                                        const struct firmware *ucode_raw,
1274                                        struct iwlagn_firmware_pieces *pieces)
1275 {
1276         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1277         u32 api_ver, hdr_size;
1278         const u8 *src;
1279
1280         priv->ucode_ver = le32_to_cpu(ucode->ver);
1281         api_ver = IWL_UCODE_API(priv->ucode_ver);
1282
1283         switch (api_ver) {
1284         default:
1285                 hdr_size = 28;
1286                 if (ucode_raw->size < hdr_size) {
1287                         IWL_ERR(priv, "File size too small!\n");
1288                         return -EINVAL;
1289                 }
1290                 pieces->build = le32_to_cpu(ucode->u.v2.build);
1291                 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1292                 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1293                 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1294                 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1295                 src = ucode->u.v2.data;
1296                 break;
1297         case 0:
1298         case 1:
1299         case 2:
1300                 hdr_size = 24;
1301                 if (ucode_raw->size < hdr_size) {
1302                         IWL_ERR(priv, "File size too small!\n");
1303                         return -EINVAL;
1304                 }
1305                 pieces->build = 0;
1306                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1307                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1308                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1309                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1310                 src = ucode->u.v1.data;
1311                 break;
1312         }
1313
1314         /* Verify size of file vs. image size info in file's header */
1315         if (ucode_raw->size != hdr_size + pieces->inst_size +
1316                                 pieces->data_size + pieces->init_size +
1317                                 pieces->init_data_size) {
1318
1319                 IWL_ERR(priv,
1320                         "uCode file size %d does not match expected size\n",
1321                         (int)ucode_raw->size);
1322                 return -EINVAL;
1323         }
1324
1325         pieces->inst = src;
1326         src += pieces->inst_size;
1327         pieces->data = src;
1328         src += pieces->data_size;
1329         pieces->init = src;
1330         src += pieces->init_size;
1331         pieces->init_data = src;
1332         src += pieces->init_data_size;
1333
1334         return 0;
1335 }
1336
1337 static int iwlagn_wanted_ucode_alternative = 1;
1338
1339 static int iwlagn_load_firmware(struct iwl_priv *priv,
1340                                 const struct firmware *ucode_raw,
1341                                 struct iwlagn_firmware_pieces *pieces,
1342                                 struct iwlagn_ucode_capabilities *capa)
1343 {
1344         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1345         struct iwl_ucode_tlv *tlv;
1346         size_t len = ucode_raw->size;
1347         const u8 *data;
1348         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1349         u64 alternatives;
1350         u32 tlv_len;
1351         enum iwl_ucode_tlv_type tlv_type;
1352         const u8 *tlv_data;
1353
1354         if (len < sizeof(*ucode)) {
1355                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1356                 return -EINVAL;
1357         }
1358
1359         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1360                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1361                         le32_to_cpu(ucode->magic));
1362                 return -EINVAL;
1363         }
1364
1365         /*
1366          * Check which alternatives are present, and "downgrade"
1367          * when the chosen alternative is not present, warning
1368          * the user when that happens. Some files may not have
1369          * any alternatives, so don't warn in that case.
1370          */
1371         alternatives = le64_to_cpu(ucode->alternatives);
1372         tmp = wanted_alternative;
1373         if (wanted_alternative > 63)
1374                 wanted_alternative = 63;
1375         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1376                 wanted_alternative--;
1377         if (wanted_alternative && wanted_alternative != tmp)
1378                 IWL_WARN(priv,
1379                          "uCode alternative %d not available, choosing %d\n",
1380                          tmp, wanted_alternative);
1381
1382         priv->ucode_ver = le32_to_cpu(ucode->ver);
1383         pieces->build = le32_to_cpu(ucode->build);
1384         data = ucode->data;
1385
1386         len -= sizeof(*ucode);
1387
1388         while (len >= sizeof(*tlv)) {
1389                 u16 tlv_alt;
1390
1391                 len -= sizeof(*tlv);
1392                 tlv = (void *)data;
1393
1394                 tlv_len = le32_to_cpu(tlv->length);
1395                 tlv_type = le16_to_cpu(tlv->type);
1396                 tlv_alt = le16_to_cpu(tlv->alternative);
1397                 tlv_data = tlv->data;
1398
1399                 if (len < tlv_len) {
1400                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1401                                 len, tlv_len);
1402                         return -EINVAL;
1403                 }
1404                 len -= ALIGN(tlv_len, 4);
1405                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1406
1407                 /*
1408                  * Alternative 0 is always valid.
1409                  *
1410                  * Skip alternative TLVs that are not selected.
1411                  */
1412                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1413                         continue;
1414
1415                 switch (tlv_type) {
1416                 case IWL_UCODE_TLV_INST:
1417                         pieces->inst = tlv_data;
1418                         pieces->inst_size = tlv_len;
1419                         break;
1420                 case IWL_UCODE_TLV_DATA:
1421                         pieces->data = tlv_data;
1422                         pieces->data_size = tlv_len;
1423                         break;
1424                 case IWL_UCODE_TLV_INIT:
1425                         pieces->init = tlv_data;
1426                         pieces->init_size = tlv_len;
1427                         break;
1428                 case IWL_UCODE_TLV_INIT_DATA:
1429                         pieces->init_data = tlv_data;
1430                         pieces->init_data_size = tlv_len;
1431                         break;
1432                 case IWL_UCODE_TLV_BOOT:
1433                         IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1434                         break;
1435                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1436                         if (tlv_len != sizeof(u32))
1437                                 goto invalid_tlv_len;
1438                         capa->max_probe_length =
1439                                         le32_to_cpup((__le32 *)tlv_data);
1440                         break;
1441                 case IWL_UCODE_TLV_PAN:
1442                         if (tlv_len)
1443                                 goto invalid_tlv_len;
1444                         capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1445                         break;
1446                 case IWL_UCODE_TLV_FLAGS:
1447                         /* must be at least one u32 */
1448                         if (tlv_len < sizeof(u32))
1449                                 goto invalid_tlv_len;
1450                         /* and a proper number of u32s */
1451                         if (tlv_len % sizeof(u32))
1452                                 goto invalid_tlv_len;
1453                         /*
1454                          * This driver only reads the first u32 as
1455                          * right now no more features are defined,
1456                          * if that changes then either the driver
1457                          * will not work with the new firmware, or
1458                          * it'll not take advantage of new features.
1459                          */
1460                         capa->flags = le32_to_cpup((__le32 *)tlv_data);
1461                         break;
1462                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1463                         if (tlv_len != sizeof(u32))
1464                                 goto invalid_tlv_len;
1465                         pieces->init_evtlog_ptr =
1466                                         le32_to_cpup((__le32 *)tlv_data);
1467                         break;
1468                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1469                         if (tlv_len != sizeof(u32))
1470                                 goto invalid_tlv_len;
1471                         pieces->init_evtlog_size =
1472                                         le32_to_cpup((__le32 *)tlv_data);
1473                         break;
1474                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1475                         if (tlv_len != sizeof(u32))
1476                                 goto invalid_tlv_len;
1477                         pieces->init_errlog_ptr =
1478                                         le32_to_cpup((__le32 *)tlv_data);
1479                         break;
1480                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1481                         if (tlv_len != sizeof(u32))
1482                                 goto invalid_tlv_len;
1483                         pieces->inst_evtlog_ptr =
1484                                         le32_to_cpup((__le32 *)tlv_data);
1485                         break;
1486                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1487                         if (tlv_len != sizeof(u32))
1488                                 goto invalid_tlv_len;
1489                         pieces->inst_evtlog_size =
1490                                         le32_to_cpup((__le32 *)tlv_data);
1491                         break;
1492                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1493                         if (tlv_len != sizeof(u32))
1494                                 goto invalid_tlv_len;
1495                         pieces->inst_errlog_ptr =
1496                                         le32_to_cpup((__le32 *)tlv_data);
1497                         break;
1498                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1499                         if (tlv_len)
1500                                 goto invalid_tlv_len;
1501                         priv->enhance_sensitivity_table = true;
1502                         break;
1503                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1504                         if (tlv_len != sizeof(u32))
1505                                 goto invalid_tlv_len;
1506                         capa->standard_phy_calibration_size =
1507                                         le32_to_cpup((__le32 *)tlv_data);
1508                         break;
1509                 default:
1510                         IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
1511                         break;
1512                 }
1513         }
1514
1515         if (len) {
1516                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1517                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1518                 return -EINVAL;
1519         }
1520
1521         return 0;
1522
1523  invalid_tlv_len:
1524         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1525         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1526
1527         return -EINVAL;
1528 }
1529
1530 /**
1531  * iwl_ucode_callback - callback when firmware was loaded
1532  *
1533  * If loaded successfully, copies the firmware into buffers
1534  * for the card to fetch (via DMA).
1535  */
1536 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1537 {
1538         struct iwl_priv *priv = context;
1539         struct iwl_ucode_header *ucode;
1540         int err;
1541         struct iwlagn_firmware_pieces pieces;
1542         const unsigned int api_max = priv->cfg->ucode_api_max;
1543         const unsigned int api_min = priv->cfg->ucode_api_min;
1544         u32 api_ver;
1545         char buildstr[25];
1546         u32 build;
1547         struct iwlagn_ucode_capabilities ucode_capa = {
1548                 .max_probe_length = 200,
1549                 .standard_phy_calibration_size =
1550                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1551         };
1552
1553         memset(&pieces, 0, sizeof(pieces));
1554
1555         if (!ucode_raw) {
1556                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1557                         IWL_ERR(priv,
1558                                 "request for firmware file '%s' failed.\n",
1559                                 priv->firmware_name);
1560                 goto try_again;
1561         }
1562
1563         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1564                        priv->firmware_name, ucode_raw->size);
1565
1566         /* Make sure that we got at least the API version number */
1567         if (ucode_raw->size < 4) {
1568                 IWL_ERR(priv, "File size way too small!\n");
1569                 goto try_again;
1570         }
1571
1572         /* Data from ucode file:  header followed by uCode images */
1573         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1574
1575         if (ucode->ver)
1576                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1577         else
1578                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1579                                            &ucode_capa);
1580
1581         if (err)
1582                 goto try_again;
1583
1584         api_ver = IWL_UCODE_API(priv->ucode_ver);
1585         build = pieces.build;
1586
1587         /*
1588          * api_ver should match the api version forming part of the
1589          * firmware filename ... but we don't check for that and only rely
1590          * on the API version read from firmware header from here on forward
1591          */
1592         /* no api version check required for experimental uCode */
1593         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1594                 if (api_ver < api_min || api_ver > api_max) {
1595                         IWL_ERR(priv,
1596                                 "Driver unable to support your firmware API. "
1597                                 "Driver supports v%u, firmware is v%u.\n",
1598                                 api_max, api_ver);
1599                         goto try_again;
1600                 }
1601
1602                 if (api_ver != api_max)
1603                         IWL_ERR(priv,
1604                                 "Firmware has old API version. Expected v%u, "
1605                                 "got v%u. New firmware can be obtained "
1606                                 "from http://www.intellinuxwireless.org.\n",
1607                                 api_max, api_ver);
1608         }
1609
1610         if (build)
1611                 sprintf(buildstr, " build %u%s", build,
1612                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1613                                 ? " (EXP)" : "");
1614         else
1615                 buildstr[0] = '\0';
1616
1617         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1618                  IWL_UCODE_MAJOR(priv->ucode_ver),
1619                  IWL_UCODE_MINOR(priv->ucode_ver),
1620                  IWL_UCODE_API(priv->ucode_ver),
1621                  IWL_UCODE_SERIAL(priv->ucode_ver),
1622                  buildstr);
1623
1624         snprintf(priv->hw->wiphy->fw_version,
1625                  sizeof(priv->hw->wiphy->fw_version),
1626                  "%u.%u.%u.%u%s",
1627                  IWL_UCODE_MAJOR(priv->ucode_ver),
1628                  IWL_UCODE_MINOR(priv->ucode_ver),
1629                  IWL_UCODE_API(priv->ucode_ver),
1630                  IWL_UCODE_SERIAL(priv->ucode_ver),
1631                  buildstr);
1632
1633         /*
1634          * For any of the failures below (before allocating pci memory)
1635          * we will try to load a version with a smaller API -- maybe the
1636          * user just got a corrupted version of the latest API.
1637          */
1638
1639         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1640                        priv->ucode_ver);
1641         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1642                        pieces.inst_size);
1643         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1644                        pieces.data_size);
1645         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1646                        pieces.init_size);
1647         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1648                        pieces.init_data_size);
1649
1650         /* Verify that uCode images will fit in card's SRAM */
1651         if (pieces.inst_size > priv->hw_params.max_inst_size) {
1652                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1653                         pieces.inst_size);
1654                 goto try_again;
1655         }
1656
1657         if (pieces.data_size > priv->hw_params.max_data_size) {
1658                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1659                         pieces.data_size);
1660                 goto try_again;
1661         }
1662
1663         if (pieces.init_size > priv->hw_params.max_inst_size) {
1664                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1665                         pieces.init_size);
1666                 goto try_again;
1667         }
1668
1669         if (pieces.init_data_size > priv->hw_params.max_data_size) {
1670                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1671                         pieces.init_data_size);
1672                 goto try_again;
1673         }
1674
1675         /* Allocate ucode buffers for card's bus-master loading ... */
1676
1677         /* Runtime instructions and 2 copies of data:
1678          * 1) unmodified from disk
1679          * 2) backup cache for save/restore during power-downs */
1680         if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.code,
1681                               pieces.inst, pieces.inst_size))
1682                 goto err_pci_alloc;
1683         if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.data,
1684                               pieces.data, pieces.data_size))
1685                 goto err_pci_alloc;
1686
1687         /* Initialization instructions and data */
1688         if (pieces.init_size && pieces.init_data_size) {
1689                 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.code,
1690                                       pieces.init, pieces.init_size))
1691                         goto err_pci_alloc;
1692                 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.data,
1693                                       pieces.init_data, pieces.init_data_size))
1694                         goto err_pci_alloc;
1695         }
1696
1697         /* Now that we can no longer fail, copy information */
1698
1699         /*
1700          * The (size - 16) / 12 formula is based on the information recorded
1701          * for each event, which is of mode 1 (including timestamp) for all
1702          * new microcodes that include this information.
1703          */
1704         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1705         if (pieces.init_evtlog_size)
1706                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1707         else
1708                 priv->_agn.init_evtlog_size =
1709                         priv->cfg->base_params->max_event_log_size;
1710         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1711         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1712         if (pieces.inst_evtlog_size)
1713                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1714         else
1715                 priv->_agn.inst_evtlog_size =
1716                         priv->cfg->base_params->max_event_log_size;
1717         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1718
1719         if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
1720                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1721                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1722         } else
1723                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1724
1725         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1726                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1727         else
1728                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1729
1730         /*
1731          * figure out the offset of chain noise reset and gain commands
1732          * base on the size of standard phy calibration commands table size
1733          */
1734         if (ucode_capa.standard_phy_calibration_size >
1735             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1736                 ucode_capa.standard_phy_calibration_size =
1737                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1738
1739         priv->_agn.phy_calib_chain_noise_reset_cmd =
1740                 ucode_capa.standard_phy_calibration_size;
1741         priv->_agn.phy_calib_chain_noise_gain_cmd =
1742                 ucode_capa.standard_phy_calibration_size + 1;
1743
1744         /**************************************************
1745          * This is still part of probe() in a sense...
1746          *
1747          * 9. Setup and register with mac80211 and debugfs
1748          **************************************************/
1749         err = iwl_mac_setup_register(priv, &ucode_capa);
1750         if (err)
1751                 goto out_unbind;
1752
1753         err = iwl_dbgfs_register(priv, DRV_NAME);
1754         if (err)
1755                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1756
1757         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1758                                         &iwl_attribute_group);
1759         if (err) {
1760                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1761                 goto out_unbind;
1762         }
1763
1764         /* We have our copies now, allow OS release its copies */
1765         release_firmware(ucode_raw);
1766         complete(&priv->_agn.firmware_loading_complete);
1767         return;
1768
1769  try_again:
1770         /* try next, if any */
1771         if (iwl_request_firmware(priv, false))
1772                 goto out_unbind;
1773         release_firmware(ucode_raw);
1774         return;
1775
1776  err_pci_alloc:
1777         IWL_ERR(priv, "failed to allocate pci memory\n");
1778         iwl_dealloc_ucode_pci(priv);
1779  out_unbind:
1780         complete(&priv->_agn.firmware_loading_complete);
1781         device_release_driver(&priv->pci_dev->dev);
1782         release_firmware(ucode_raw);
1783 }
1784
1785 static const char *desc_lookup_text[] = {
1786         "OK",
1787         "FAIL",
1788         "BAD_PARAM",
1789         "BAD_CHECKSUM",
1790         "NMI_INTERRUPT_WDG",
1791         "SYSASSERT",
1792         "FATAL_ERROR",
1793         "BAD_COMMAND",
1794         "HW_ERROR_TUNE_LOCK",
1795         "HW_ERROR_TEMPERATURE",
1796         "ILLEGAL_CHAN_FREQ",
1797         "VCC_NOT_STABLE",
1798         "FH_ERROR",
1799         "NMI_INTERRUPT_HOST",
1800         "NMI_INTERRUPT_ACTION_PT",
1801         "NMI_INTERRUPT_UNKNOWN",
1802         "UCODE_VERSION_MISMATCH",
1803         "HW_ERROR_ABS_LOCK",
1804         "HW_ERROR_CAL_LOCK_FAIL",
1805         "NMI_INTERRUPT_INST_ACTION_PT",
1806         "NMI_INTERRUPT_DATA_ACTION_PT",
1807         "NMI_TRM_HW_ER",
1808         "NMI_INTERRUPT_TRM",
1809         "NMI_INTERRUPT_BREAK_POINT"
1810         "DEBUG_0",
1811         "DEBUG_1",
1812         "DEBUG_2",
1813         "DEBUG_3",
1814 };
1815
1816 static struct { char *name; u8 num; } advanced_lookup[] = {
1817         { "NMI_INTERRUPT_WDG", 0x34 },
1818         { "SYSASSERT", 0x35 },
1819         { "UCODE_VERSION_MISMATCH", 0x37 },
1820         { "BAD_COMMAND", 0x38 },
1821         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1822         { "FATAL_ERROR", 0x3D },
1823         { "NMI_TRM_HW_ERR", 0x46 },
1824         { "NMI_INTERRUPT_TRM", 0x4C },
1825         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1826         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1827         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1828         { "NMI_INTERRUPT_HOST", 0x66 },
1829         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1830         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1831         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1832         { "ADVANCED_SYSASSERT", 0 },
1833 };
1834
1835 static const char *desc_lookup(u32 num)
1836 {
1837         int i;
1838         int max = ARRAY_SIZE(desc_lookup_text);
1839
1840         if (num < max)
1841                 return desc_lookup_text[num];
1842
1843         max = ARRAY_SIZE(advanced_lookup) - 1;
1844         for (i = 0; i < max; i++) {
1845                 if (advanced_lookup[i].num == num)
1846                         break;;
1847         }
1848         return advanced_lookup[i].name;
1849 }
1850
1851 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1852 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1853
1854 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1855 {
1856         u32 data2, line;
1857         u32 desc, time, count, base, data1;
1858         u32 blink1, blink2, ilink1, ilink2;
1859         u32 pc, hcmd;
1860         struct iwl_error_event_table table;
1861
1862         base = priv->device_pointers.error_event_table;
1863         if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
1864                 if (!base)
1865                         base = priv->_agn.init_errlog_ptr;
1866         } else {
1867                 if (!base)
1868                         base = priv->_agn.inst_errlog_ptr;
1869         }
1870
1871         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1872                 IWL_ERR(priv,
1873                         "Not valid error log pointer 0x%08X for %s uCode\n",
1874                         base,
1875                         (priv->ucode_type == UCODE_SUBTYPE_INIT)
1876                                         ? "Init" : "RT");
1877                 return;
1878         }
1879
1880         iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
1881
1882         count = table.valid;
1883
1884         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1885                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1886                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1887                         priv->status, count);
1888         }
1889
1890         desc = table.error_id;
1891         priv->isr_stats.err_code = desc;
1892         pc = table.pc;
1893         blink1 = table.blink1;
1894         blink2 = table.blink2;
1895         ilink1 = table.ilink1;
1896         ilink2 = table.ilink2;
1897         data1 = table.data1;
1898         data2 = table.data2;
1899         line = table.line;
1900         time = table.tsf_low;
1901         hcmd = table.hcmd;
1902
1903         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1904                                       blink1, blink2, ilink1, ilink2);
1905
1906         IWL_ERR(priv, "Desc                                  Time       "
1907                 "data1      data2      line\n");
1908         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1909                 desc_lookup(desc), desc, time, data1, data2, line);
1910         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
1911         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1912                 pc, blink1, blink2, ilink1, ilink2, hcmd);
1913 }
1914
1915 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1916
1917 /**
1918  * iwl_print_event_log - Dump error event log to syslog
1919  *
1920  */
1921 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1922                                u32 num_events, u32 mode,
1923                                int pos, char **buf, size_t bufsz)
1924 {
1925         u32 i;
1926         u32 base;       /* SRAM byte address of event log header */
1927         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1928         u32 ptr;        /* SRAM byte address of log data */
1929         u32 ev, time, data; /* event log data */
1930         unsigned long reg_flags;
1931
1932         if (num_events == 0)
1933                 return pos;
1934
1935         base = priv->device_pointers.log_event_table;
1936         if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
1937                 if (!base)
1938                         base = priv->_agn.init_evtlog_ptr;
1939         } else {
1940                 if (!base)
1941                         base = priv->_agn.inst_evtlog_ptr;
1942         }
1943
1944         if (mode == 0)
1945                 event_size = 2 * sizeof(u32);
1946         else
1947                 event_size = 3 * sizeof(u32);
1948
1949         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1950
1951         /* Make sure device is powered up for SRAM reads */
1952         spin_lock_irqsave(&priv->reg_lock, reg_flags);
1953         iwl_grab_nic_access(priv);
1954
1955         /* Set starting address; reads will auto-increment */
1956         iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
1957         rmb();
1958
1959         /* "time" is actually "data" for mode 0 (no timestamp).
1960         * place event id # at far right for easier visual parsing. */
1961         for (i = 0; i < num_events; i++) {
1962                 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1963                 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1964                 if (mode == 0) {
1965                         /* data, ev */
1966                         if (bufsz) {
1967                                 pos += scnprintf(*buf + pos, bufsz - pos,
1968                                                 "EVT_LOG:0x%08x:%04u\n",
1969                                                 time, ev);
1970                         } else {
1971                                 trace_iwlwifi_dev_ucode_event(priv, 0,
1972                                         time, ev);
1973                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1974                                         time, ev);
1975                         }
1976                 } else {
1977                         data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1978                         if (bufsz) {
1979                                 pos += scnprintf(*buf + pos, bufsz - pos,
1980                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
1981                                                  time, data, ev);
1982                         } else {
1983                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1984                                         time, data, ev);
1985                                 trace_iwlwifi_dev_ucode_event(priv, time,
1986                                         data, ev);
1987                         }
1988                 }
1989         }
1990
1991         /* Allow device to power down */
1992         iwl_release_nic_access(priv);
1993         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
1994         return pos;
1995 }
1996
1997 /**
1998  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1999  */
2000 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2001                                     u32 num_wraps, u32 next_entry,
2002                                     u32 size, u32 mode,
2003                                     int pos, char **buf, size_t bufsz)
2004 {
2005         /*
2006          * display the newest DEFAULT_LOG_ENTRIES entries
2007          * i.e the entries just before the next ont that uCode would fill.
2008          */
2009         if (num_wraps) {
2010                 if (next_entry < size) {
2011                         pos = iwl_print_event_log(priv,
2012                                                 capacity - (size - next_entry),
2013                                                 size - next_entry, mode,
2014                                                 pos, buf, bufsz);
2015                         pos = iwl_print_event_log(priv, 0,
2016                                                   next_entry, mode,
2017                                                   pos, buf, bufsz);
2018                 } else
2019                         pos = iwl_print_event_log(priv, next_entry - size,
2020                                                   size, mode, pos, buf, bufsz);
2021         } else {
2022                 if (next_entry < size) {
2023                         pos = iwl_print_event_log(priv, 0, next_entry,
2024                                                   mode, pos, buf, bufsz);
2025                 } else {
2026                         pos = iwl_print_event_log(priv, next_entry - size,
2027                                                   size, mode, pos, buf, bufsz);
2028                 }
2029         }
2030         return pos;
2031 }
2032
2033 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2034
2035 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2036                             char **buf, bool display)
2037 {
2038         u32 base;       /* SRAM byte address of event log header */
2039         u32 capacity;   /* event log capacity in # entries */
2040         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2041         u32 num_wraps;  /* # times uCode wrapped to top of log */
2042         u32 next_entry; /* index of next entry to be written by uCode */
2043         u32 size;       /* # entries that we'll print */
2044         u32 logsize;
2045         int pos = 0;
2046         size_t bufsz = 0;
2047
2048         base = priv->device_pointers.log_event_table;
2049         if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
2050                 logsize = priv->_agn.init_evtlog_size;
2051                 if (!base)
2052                         base = priv->_agn.init_evtlog_ptr;
2053         } else {
2054                 logsize = priv->_agn.inst_evtlog_size;
2055                 if (!base)
2056                         base = priv->_agn.inst_evtlog_ptr;
2057         }
2058
2059         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2060                 IWL_ERR(priv,
2061                         "Invalid event log pointer 0x%08X for %s uCode\n",
2062                         base,
2063                         (priv->ucode_type == UCODE_SUBTYPE_INIT)
2064                                         ? "Init" : "RT");
2065                 return -EINVAL;
2066         }
2067
2068         /* event log header */
2069         capacity = iwl_read_targ_mem(priv, base);
2070         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2071         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2072         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2073
2074         if (capacity > logsize) {
2075                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2076                         capacity, logsize);
2077                 capacity = logsize;
2078         }
2079
2080         if (next_entry > logsize) {
2081                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2082                         next_entry, logsize);
2083                 next_entry = logsize;
2084         }
2085
2086         size = num_wraps ? capacity : next_entry;
2087
2088         /* bail out if nothing in log */
2089         if (size == 0) {
2090                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2091                 return pos;
2092         }
2093
2094         /* enable/disable bt channel inhibition */
2095         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2096
2097 #ifdef CONFIG_IWLWIFI_DEBUG
2098         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2099                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2100                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2101 #else
2102         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2103                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2104 #endif
2105         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2106                 size);
2107
2108 #ifdef CONFIG_IWLWIFI_DEBUG
2109         if (display) {
2110                 if (full_log)
2111                         bufsz = capacity * 48;
2112                 else
2113                         bufsz = size * 48;
2114                 *buf = kmalloc(bufsz, GFP_KERNEL);
2115                 if (!*buf)
2116                         return -ENOMEM;
2117         }
2118         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2119                 /*
2120                  * if uCode has wrapped back to top of log,
2121                  * start at the oldest entry,
2122                  * i.e the next one that uCode would fill.
2123                  */
2124                 if (num_wraps)
2125                         pos = iwl_print_event_log(priv, next_entry,
2126                                                 capacity - next_entry, mode,
2127                                                 pos, buf, bufsz);
2128                 /* (then/else) start at top of log */
2129                 pos = iwl_print_event_log(priv, 0,
2130                                           next_entry, mode, pos, buf, bufsz);
2131         } else
2132                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2133                                                 next_entry, size, mode,
2134                                                 pos, buf, bufsz);
2135 #else
2136         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2137                                         next_entry, size, mode,
2138                                         pos, buf, bufsz);
2139 #endif
2140         return pos;
2141 }
2142
2143 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2144 {
2145         struct iwl_ct_kill_config cmd;
2146         struct iwl_ct_kill_throttling_config adv_cmd;
2147         unsigned long flags;
2148         int ret = 0;
2149
2150         spin_lock_irqsave(&priv->lock, flags);
2151         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2152                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2153         spin_unlock_irqrestore(&priv->lock, flags);
2154         priv->thermal_throttle.ct_kill_toggle = false;
2155
2156         if (priv->cfg->base_params->support_ct_kill_exit) {
2157                 adv_cmd.critical_temperature_enter =
2158                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2159                 adv_cmd.critical_temperature_exit =
2160                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2161
2162                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2163                                        sizeof(adv_cmd), &adv_cmd);
2164                 if (ret)
2165                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2166                 else
2167                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2168                                         "succeeded, "
2169                                         "critical temperature enter is %d,"
2170                                         "exit is %d\n",
2171                                        priv->hw_params.ct_kill_threshold,
2172                                        priv->hw_params.ct_kill_exit_threshold);
2173         } else {
2174                 cmd.critical_temperature_R =
2175                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2176
2177                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2178                                        sizeof(cmd), &cmd);
2179                 if (ret)
2180                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2181                 else
2182                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2183                                         "succeeded, "
2184                                         "critical temperature is %d\n",
2185                                         priv->hw_params.ct_kill_threshold);
2186         }
2187 }
2188
2189 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2190 {
2191         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2192         struct iwl_host_cmd cmd = {
2193                 .id = CALIBRATION_CFG_CMD,
2194                 .len = sizeof(struct iwl_calib_cfg_cmd),
2195                 .data = &calib_cfg_cmd,
2196         };
2197
2198         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2199         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2200         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2201
2202         return iwl_send_cmd(priv, &cmd);
2203 }
2204
2205
2206 /**
2207  * iwl_alive_start - called after REPLY_ALIVE notification received
2208  *                   from protocol/runtime uCode (initialization uCode's
2209  *                   Alive gets handled by iwl_init_alive_start()).
2210  */
2211 static int iwl_alive_start(struct iwl_priv *priv)
2212 {
2213         int ret = 0;
2214         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2215
2216         iwl_reset_ict(priv);
2217
2218         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2219
2220         /* After the ALIVE response, we can send host commands to the uCode */
2221         set_bit(STATUS_ALIVE, &priv->status);
2222
2223         /* Enable watchdog to monitor the driver tx queues */
2224         iwl_setup_watchdog(priv);
2225
2226         if (iwl_is_rfkill(priv))
2227                 return -ERFKILL;
2228
2229         /* download priority table before any calibration request */
2230         if (priv->cfg->bt_params &&
2231             priv->cfg->bt_params->advanced_bt_coexist) {
2232                 /* Configure Bluetooth device coexistence support */
2233                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2234                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2235                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2236                 priv->cfg->ops->hcmd->send_bt_config(priv);
2237                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2238                 iwlagn_send_prio_tbl(priv);
2239
2240                 /* FIXME: w/a to force change uCode BT state machine */
2241                 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2242                                          BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2243                 if (ret)
2244                         return ret;
2245                 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2246                                          BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2247                 if (ret)
2248                         return ret;
2249         }
2250         if (priv->hw_params.calib_rt_cfg)
2251                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2252
2253         ieee80211_wake_queues(priv->hw);
2254
2255         priv->active_rate = IWL_RATES_MASK;
2256
2257         /* Configure Tx antenna selection based on H/W config */
2258         if (priv->cfg->ops->hcmd->set_tx_ant)
2259                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2260
2261         if (iwl_is_associated_ctx(ctx)) {
2262                 struct iwl_rxon_cmd *active_rxon =
2263                                 (struct iwl_rxon_cmd *)&ctx->active;
2264                 /* apply any changes in staging */
2265                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2266                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2267         } else {
2268                 struct iwl_rxon_context *tmp;
2269                 /* Initialize our rx_config data */
2270                 for_each_context(priv, tmp)
2271                         iwl_connection_init_rx_config(priv, tmp);
2272
2273                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2274                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2275         }
2276
2277         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2278             !priv->cfg->bt_params->advanced_bt_coexist)) {
2279                 /*
2280                  * default is 2-wire BT coexexistence support
2281                  */
2282                 priv->cfg->ops->hcmd->send_bt_config(priv);
2283         }
2284
2285         iwl_reset_run_time_calib(priv);
2286
2287         set_bit(STATUS_READY, &priv->status);
2288
2289         /* Configure the adapter for unassociated operation */
2290         ret = iwlcore_commit_rxon(priv, ctx);
2291         if (ret)
2292                 return ret;
2293
2294         /* At this point, the NIC is initialized and operational */
2295         iwl_rf_kill_ct_config(priv);
2296
2297         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2298
2299         return iwl_power_update_mode(priv, true);
2300 }
2301
2302 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2303
2304 static void __iwl_down(struct iwl_priv *priv)
2305 {
2306         int exit_pending;
2307
2308         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2309
2310         iwl_scan_cancel_timeout(priv, 200);
2311
2312         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2313
2314         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2315          * to prevent rearm timer */
2316         del_timer_sync(&priv->watchdog);
2317
2318         iwl_clear_ucode_stations(priv, NULL);
2319         iwl_dealloc_bcast_stations(priv);
2320         iwl_clear_driver_stations(priv);
2321
2322         /* reset BT coex data */
2323         priv->bt_status = 0;
2324         if (priv->cfg->bt_params)
2325                 priv->bt_traffic_load =
2326                          priv->cfg->bt_params->bt_init_traffic_load;
2327         else
2328                 priv->bt_traffic_load = 0;
2329         priv->bt_full_concurrent = false;
2330         priv->bt_ci_compliance = 0;
2331
2332         /* Wipe out the EXIT_PENDING status bit if we are not actually
2333          * exiting the module */
2334         if (!exit_pending)
2335                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2336
2337         if (priv->mac80211_registered)
2338                 ieee80211_stop_queues(priv->hw);
2339
2340         /* Clear out all status bits but a few that are stable across reset */
2341         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2342                                 STATUS_RF_KILL_HW |
2343                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2344                                 STATUS_GEO_CONFIGURED |
2345                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2346                                 STATUS_FW_ERROR |
2347                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2348                                 STATUS_EXIT_PENDING;
2349
2350         iwlagn_stop_device(priv);
2351
2352         dev_kfree_skb(priv->beacon_skb);
2353         priv->beacon_skb = NULL;
2354
2355         /* clear out any free frames */
2356         iwl_clear_free_frames(priv);
2357 }
2358
2359 static void iwl_down(struct iwl_priv *priv)
2360 {
2361         mutex_lock(&priv->mutex);
2362         __iwl_down(priv);
2363         mutex_unlock(&priv->mutex);
2364
2365         iwl_cancel_deferred_work(priv);
2366 }
2367
2368 #define HW_READY_TIMEOUT (50)
2369
2370 /* Note: returns poll_bit return value, which is >= 0 if success */
2371 static int iwl_set_hw_ready(struct iwl_priv *priv)
2372 {
2373         int ret;
2374
2375         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2376                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2377
2378         /* See if we got it */
2379         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2380                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2381                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2382                                 HW_READY_TIMEOUT);
2383
2384         IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
2385         return ret;
2386 }
2387
2388 /* Note: returns standard 0/-ERROR code */
2389 int iwl_prepare_card_hw(struct iwl_priv *priv)
2390 {
2391         int ret;
2392
2393         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2394
2395         ret = iwl_set_hw_ready(priv);
2396         if (ret >= 0)
2397                 return 0;
2398
2399         /* If HW is not ready, prepare the conditions to check again */
2400         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2401                         CSR_HW_IF_CONFIG_REG_PREPARE);
2402
2403         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2404                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2405                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2406
2407         if (ret < 0)
2408                 return ret;
2409
2410         /* HW should be ready by now, check again. */
2411         ret = iwl_set_hw_ready(priv);
2412         if (ret >= 0)
2413                 return 0;
2414         return ret;
2415 }
2416
2417 #define MAX_HW_RESTARTS 5
2418
2419 static int __iwl_up(struct iwl_priv *priv)
2420 {
2421         struct iwl_rxon_context *ctx;
2422         int ret;
2423
2424         lockdep_assert_held(&priv->mutex);
2425
2426         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2427                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2428                 return -EIO;
2429         }
2430
2431         for_each_context(priv, ctx) {
2432                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2433                 if (ret) {
2434                         iwl_dealloc_bcast_stations(priv);
2435                         return ret;
2436                 }
2437         }
2438
2439         ret = iwlagn_run_init_ucode(priv);
2440         if (ret) {
2441                 IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret);
2442                 goto error;
2443         }
2444
2445         ret = iwlagn_load_ucode_wait_alive(priv,
2446                                            &priv->ucode_rt,
2447                                            UCODE_SUBTYPE_REGULAR,
2448                                            UCODE_SUBTYPE_REGULAR_NEW);
2449         if (ret) {
2450                 IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
2451                 goto error;
2452         }
2453
2454         ret = iwl_alive_start(priv);
2455         if (ret)
2456                 goto error;
2457         return 0;
2458
2459  error:
2460         set_bit(STATUS_EXIT_PENDING, &priv->status);
2461         __iwl_down(priv);
2462         clear_bit(STATUS_EXIT_PENDING, &priv->status);
2463
2464         IWL_ERR(priv, "Unable to initialize device.\n");
2465         return ret;
2466 }
2467
2468
2469 /*****************************************************************************
2470  *
2471  * Workqueue callbacks
2472  *
2473  *****************************************************************************/
2474
2475 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2476 {
2477         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2478                         run_time_calib_work);
2479
2480         mutex_lock(&priv->mutex);
2481
2482         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2483             test_bit(STATUS_SCANNING, &priv->status)) {
2484                 mutex_unlock(&priv->mutex);
2485                 return;
2486         }
2487
2488         if (priv->start_calib) {
2489                 iwl_chain_noise_calibration(priv);
2490                 iwl_sensitivity_calibration(priv);
2491         }
2492
2493         mutex_unlock(&priv->mutex);
2494 }
2495
2496 static void iwlagn_prepare_restart(struct iwl_priv *priv)
2497 {
2498         struct iwl_rxon_context *ctx;
2499         bool bt_full_concurrent;
2500         u8 bt_ci_compliance;
2501         u8 bt_load;
2502         u8 bt_status;
2503
2504         lockdep_assert_held(&priv->mutex);
2505
2506         for_each_context(priv, ctx)
2507                 ctx->vif = NULL;
2508         priv->is_open = 0;
2509
2510         /*
2511          * __iwl_down() will clear the BT status variables,
2512          * which is correct, but when we restart we really
2513          * want to keep them so restore them afterwards.
2514          *
2515          * The restart process will later pick them up and
2516          * re-configure the hw when we reconfigure the BT
2517          * command.
2518          */
2519         bt_full_concurrent = priv->bt_full_concurrent;
2520         bt_ci_compliance = priv->bt_ci_compliance;
2521         bt_load = priv->bt_traffic_load;
2522         bt_status = priv->bt_status;
2523
2524         __iwl_down(priv);
2525
2526         priv->bt_full_concurrent = bt_full_concurrent;
2527         priv->bt_ci_compliance = bt_ci_compliance;
2528         priv->bt_traffic_load = bt_load;
2529         priv->bt_status = bt_status;
2530 }
2531
2532 static void iwl_bg_restart(struct work_struct *data)
2533 {
2534         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2535
2536         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2537                 return;
2538
2539         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2540                 mutex_lock(&priv->mutex);
2541                 iwlagn_prepare_restart(priv);
2542                 mutex_unlock(&priv->mutex);
2543                 iwl_cancel_deferred_work(priv);
2544                 ieee80211_restart_hw(priv->hw);
2545         } else {
2546                 WARN_ON(1);
2547         }
2548 }
2549
2550 static void iwl_bg_rx_replenish(struct work_struct *data)
2551 {
2552         struct iwl_priv *priv =
2553             container_of(data, struct iwl_priv, rx_replenish);
2554
2555         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2556                 return;
2557
2558         mutex_lock(&priv->mutex);
2559         iwlagn_rx_replenish(priv);
2560         mutex_unlock(&priv->mutex);
2561 }
2562
2563 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2564                                  struct ieee80211_channel *chan,
2565                                  enum nl80211_channel_type channel_type,
2566                                  unsigned int wait)
2567 {
2568         struct iwl_priv *priv = hw->priv;
2569         int ret;
2570
2571         /* Not supported if we don't have PAN */
2572         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2573                 ret = -EOPNOTSUPP;
2574                 goto free;
2575         }
2576
2577         /* Not supported on pre-P2P firmware */
2578         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2579                                         BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2580                 ret = -EOPNOTSUPP;
2581                 goto free;
2582         }
2583
2584         mutex_lock(&priv->mutex);
2585
2586         if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2587                 /*
2588                  * If the PAN context is free, use the normal
2589                  * way of doing remain-on-channel offload + TX.
2590                  */
2591                 ret = 1;
2592                 goto out;
2593         }
2594
2595         /* TODO: queue up if scanning? */
2596         if (test_bit(STATUS_SCANNING, &priv->status) ||
2597             priv->_agn.offchan_tx_skb) {
2598                 ret = -EBUSY;
2599                 goto out;
2600         }
2601
2602         /*
2603          * max_scan_ie_len doesn't include the blank SSID or the header,
2604          * so need to add that again here.
2605          */
2606         if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2607                 ret = -ENOBUFS;
2608                 goto out;
2609         }
2610
2611         priv->_agn.offchan_tx_skb = skb;
2612         priv->_agn.offchan_tx_timeout = wait;
2613         priv->_agn.offchan_tx_chan = chan;
2614
2615         ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2616                                 IWL_SCAN_OFFCH_TX, chan->band);
2617         if (ret)
2618                 priv->_agn.offchan_tx_skb = NULL;
2619  out:
2620         mutex_unlock(&priv->mutex);
2621  free:
2622         if (ret < 0)
2623                 kfree_skb(skb);
2624
2625         return ret;
2626 }
2627
2628 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2629 {
2630         struct iwl_priv *priv = hw->priv;
2631         int ret;
2632
2633         mutex_lock(&priv->mutex);
2634
2635         if (!priv->_agn.offchan_tx_skb) {
2636                 ret = -EINVAL;
2637                 goto unlock;
2638         }
2639
2640         priv->_agn.offchan_tx_skb = NULL;
2641
2642         ret = iwl_scan_cancel_timeout(priv, 200);
2643         if (ret)
2644                 ret = -EIO;
2645 unlock:
2646         mutex_unlock(&priv->mutex);
2647
2648         return ret;
2649 }
2650
2651 /*****************************************************************************
2652  *
2653  * mac80211 entry point functions
2654  *
2655  *****************************************************************************/
2656
2657 /*
2658  * Not a mac80211 entry point function, but it fits in with all the
2659  * other mac80211 functions grouped here.
2660  */
2661 static int iwl_mac_setup_register(struct iwl_priv *priv,
2662                                   struct iwlagn_ucode_capabilities *capa)
2663 {
2664         int ret;
2665         struct ieee80211_hw *hw = priv->hw;
2666         struct iwl_rxon_context *ctx;
2667
2668         hw->rate_control_algorithm = "iwl-agn-rs";
2669
2670         /* Tell mac80211 our characteristics */
2671         hw->flags = IEEE80211_HW_SIGNAL_DBM |
2672                     IEEE80211_HW_AMPDU_AGGREGATION |
2673                     IEEE80211_HW_NEED_DTIM_PERIOD |
2674                     IEEE80211_HW_SPECTRUM_MGMT |
2675                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2676
2677         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2678
2679         hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2680                      IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2681
2682         if (priv->cfg->sku & IWL_SKU_N)
2683                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2684                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2685
2686         if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2687                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2688
2689         hw->sta_data_size = sizeof(struct iwl_station_priv);
2690         hw->vif_data_size = sizeof(struct iwl_vif_priv);
2691
2692         for_each_context(priv, ctx) {
2693                 hw->wiphy->interface_modes |= ctx->interface_modes;
2694                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2695         }
2696
2697         hw->wiphy->max_remain_on_channel_duration = 1000;
2698
2699         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2700                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
2701                             WIPHY_FLAG_IBSS_RSN;
2702
2703         /*
2704          * For now, disable PS by default because it affects
2705          * RX performance significantly.
2706          */
2707         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2708
2709         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2710         /* we create the 802.11 header and a zero-length SSID element */
2711         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2712
2713         /* Default value; 4 EDCA QOS priorities */
2714         hw->queues = 4;
2715
2716         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2717
2718         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2719                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2720                         &priv->bands[IEEE80211_BAND_2GHZ];
2721         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2722                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2723                         &priv->bands[IEEE80211_BAND_5GHZ];
2724
2725         iwl_leds_init(priv);
2726
2727         ret = ieee80211_register_hw(priv->hw);
2728         if (ret) {
2729                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2730                 return ret;
2731         }
2732         priv->mac80211_registered = 1;
2733
2734         return 0;
2735 }
2736
2737
2738 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2739 {
2740         struct iwl_priv *priv = hw->priv;
2741         int ret;
2742
2743         IWL_DEBUG_MAC80211(priv, "enter\n");
2744
2745         /* we should be verifying the device is ready to be opened */
2746         mutex_lock(&priv->mutex);
2747         ret = __iwl_up(priv);
2748         mutex_unlock(&priv->mutex);
2749         if (ret)
2750                 return ret;
2751
2752         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2753
2754         /* Now we should be done, and the READY bit should be set. */
2755         if (WARN_ON(!test_bit(STATUS_READY, &priv->status)))
2756                 ret = -EIO;
2757
2758         iwlagn_led_enable(priv);
2759
2760         priv->is_open = 1;
2761         IWL_DEBUG_MAC80211(priv, "leave\n");
2762         return 0;
2763 }
2764
2765 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2766 {
2767         struct iwl_priv *priv = hw->priv;
2768
2769         IWL_DEBUG_MAC80211(priv, "enter\n");
2770
2771         if (!priv->is_open)
2772                 return;
2773
2774         priv->is_open = 0;
2775
2776         iwl_down(priv);
2777
2778         flush_workqueue(priv->workqueue);
2779
2780         /* User space software may expect getting rfkill changes
2781          * even if interface is down */
2782         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2783         iwl_enable_rfkill_int(priv);
2784
2785         IWL_DEBUG_MAC80211(priv, "leave\n");
2786 }
2787
2788 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2789 {
2790         struct iwl_priv *priv = hw->priv;
2791
2792         IWL_DEBUG_MACDUMP(priv, "enter\n");
2793
2794         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2795                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2796
2797         if (iwlagn_tx_skb(priv, skb))
2798                 dev_kfree_skb_any(skb);
2799
2800         IWL_DEBUG_MACDUMP(priv, "leave\n");
2801 }
2802
2803 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2804                                        struct ieee80211_vif *vif,
2805                                        struct ieee80211_key_conf *keyconf,
2806                                        struct ieee80211_sta *sta,
2807                                        u32 iv32, u16 *phase1key)
2808 {
2809         struct iwl_priv *priv = hw->priv;
2810         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2811
2812         IWL_DEBUG_MAC80211(priv, "enter\n");
2813
2814         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2815                             iv32, phase1key);
2816
2817         IWL_DEBUG_MAC80211(priv, "leave\n");
2818 }
2819
2820 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2821                               struct ieee80211_vif *vif,
2822                               struct ieee80211_sta *sta,
2823                               struct ieee80211_key_conf *key)
2824 {
2825         struct iwl_priv *priv = hw->priv;
2826         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2827         struct iwl_rxon_context *ctx = vif_priv->ctx;
2828         int ret;
2829         u8 sta_id;
2830         bool is_default_wep_key = false;
2831
2832         IWL_DEBUG_MAC80211(priv, "enter\n");
2833
2834         if (priv->cfg->mod_params->sw_crypto) {
2835                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2836                 return -EOPNOTSUPP;
2837         }
2838
2839         /*
2840          * To support IBSS RSN, don't program group keys in IBSS, the
2841          * hardware will then not attempt to decrypt the frames.
2842          */
2843         if (vif->type == NL80211_IFTYPE_ADHOC &&
2844             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
2845                 return -EOPNOTSUPP;
2846
2847         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
2848         if (sta_id == IWL_INVALID_STATION)
2849                 return -EINVAL;
2850
2851         mutex_lock(&priv->mutex);
2852         iwl_scan_cancel_timeout(priv, 100);
2853
2854         /*
2855          * If we are getting WEP group key and we didn't receive any key mapping
2856          * so far, we are in legacy wep mode (group key only), otherwise we are
2857          * in 1X mode.
2858          * In legacy wep mode, we use another host command to the uCode.
2859          */
2860         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2861              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
2862             !sta) {
2863                 if (cmd == SET_KEY)
2864                         is_default_wep_key = !ctx->key_mapping_keys;
2865                 else
2866                         is_default_wep_key =
2867                                         (key->hw_key_idx == HW_KEY_DEFAULT);
2868         }
2869
2870         switch (cmd) {
2871         case SET_KEY:
2872                 if (is_default_wep_key)
2873                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
2874                 else
2875                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
2876                                                   key, sta_id);
2877
2878                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2879                 break;
2880         case DISABLE_KEY:
2881                 if (is_default_wep_key)
2882                         ret = iwl_remove_default_wep_key(priv, ctx, key);
2883                 else
2884                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
2885
2886                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2887                 break;
2888         default:
2889                 ret = -EINVAL;
2890         }
2891
2892         mutex_unlock(&priv->mutex);
2893         IWL_DEBUG_MAC80211(priv, "leave\n");
2894
2895         return ret;
2896 }
2897
2898 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2899                                    struct ieee80211_vif *vif,
2900                                    enum ieee80211_ampdu_mlme_action action,
2901                                    struct ieee80211_sta *sta, u16 tid, u16 *ssn,
2902                                    u8 buf_size)
2903 {
2904         struct iwl_priv *priv = hw->priv;
2905         int ret = -EINVAL;
2906         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
2907
2908         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2909                      sta->addr, tid);
2910
2911         if (!(priv->cfg->sku & IWL_SKU_N))
2912                 return -EACCES;
2913
2914         mutex_lock(&priv->mutex);
2915
2916         switch (action) {
2917         case IEEE80211_AMPDU_RX_START:
2918                 IWL_DEBUG_HT(priv, "start Rx\n");
2919                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
2920                 break;
2921         case IEEE80211_AMPDU_RX_STOP:
2922                 IWL_DEBUG_HT(priv, "stop Rx\n");
2923                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
2924                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2925                         ret = 0;
2926                 break;
2927         case IEEE80211_AMPDU_TX_START:
2928                 IWL_DEBUG_HT(priv, "start Tx\n");
2929                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
2930                 if (ret == 0) {
2931                         priv->_agn.agg_tids_count++;
2932                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2933                                      priv->_agn.agg_tids_count);
2934                 }
2935                 break;
2936         case IEEE80211_AMPDU_TX_STOP:
2937                 IWL_DEBUG_HT(priv, "stop Tx\n");
2938                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
2939                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
2940                         priv->_agn.agg_tids_count--;
2941                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2942                                      priv->_agn.agg_tids_count);
2943                 }
2944                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2945                         ret = 0;
2946                 if (priv->cfg->ht_params &&
2947                     priv->cfg->ht_params->use_rts_for_aggregation) {
2948                         struct iwl_station_priv *sta_priv =
2949                                 (void *) sta->drv_priv;
2950                         /*
2951                          * switch off RTS/CTS if it was previously enabled
2952                          */
2953
2954                         sta_priv->lq_sta.lq.general_params.flags &=
2955                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
2956                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2957                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
2958                 }
2959                 break;
2960         case IEEE80211_AMPDU_TX_OPERATIONAL:
2961                 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
2962
2963                 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
2964
2965                 /*
2966                  * If the limit is 0, then it wasn't initialised yet,
2967                  * use the default. We can do that since we take the
2968                  * minimum below, and we don't want to go above our
2969                  * default due to hardware restrictions.
2970                  */
2971                 if (sta_priv->max_agg_bufsize == 0)
2972                         sta_priv->max_agg_bufsize =
2973                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2974
2975                 /*
2976                  * Even though in theory the peer could have different
2977                  * aggregation reorder buffer sizes for different sessions,
2978                  * our ucode doesn't allow for that and has a global limit
2979                  * for each station. Therefore, use the minimum of all the
2980                  * aggregation sessions and our default value.
2981                  */
2982                 sta_priv->max_agg_bufsize =
2983                         min(sta_priv->max_agg_bufsize, buf_size);
2984
2985                 if (priv->cfg->ht_params &&
2986                     priv->cfg->ht_params->use_rts_for_aggregation) {
2987                         /*
2988                          * switch to RTS/CTS if it is the prefer protection
2989                          * method for HT traffic
2990                          */
2991
2992                         sta_priv->lq_sta.lq.general_params.flags |=
2993                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
2994                 }
2995
2996                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
2997                         sta_priv->max_agg_bufsize;
2998
2999                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3000                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3001                 ret = 0;
3002                 break;
3003         }
3004         mutex_unlock(&priv->mutex);
3005
3006         return ret;
3007 }
3008
3009 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3010                               struct ieee80211_vif *vif,
3011                               struct ieee80211_sta *sta)
3012 {
3013         struct iwl_priv *priv = hw->priv;
3014         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3015         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3016         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3017         int ret;
3018         u8 sta_id;
3019
3020         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3021                         sta->addr);
3022         mutex_lock(&priv->mutex);
3023         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3024                         sta->addr);
3025         sta_priv->common.sta_id = IWL_INVALID_STATION;
3026
3027         atomic_set(&sta_priv->pending_frames, 0);
3028         if (vif->type == NL80211_IFTYPE_AP)
3029                 sta_priv->client = true;
3030
3031         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3032                                      is_ap, sta, &sta_id);
3033         if (ret) {
3034                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3035                         sta->addr, ret);
3036                 /* Should we return success if return code is EEXIST ? */
3037                 mutex_unlock(&priv->mutex);
3038                 return ret;
3039         }
3040
3041         sta_priv->common.sta_id = sta_id;
3042
3043         /* Initialize rate scaling */
3044         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3045                        sta->addr);
3046         iwl_rs_rate_init(priv, sta, sta_id);
3047         mutex_unlock(&priv->mutex);
3048
3049         return 0;
3050 }
3051
3052 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3053                                 struct ieee80211_channel_switch *ch_switch)
3054 {
3055         struct iwl_priv *priv = hw->priv;
3056         const struct iwl_channel_info *ch_info;
3057         struct ieee80211_conf *conf = &hw->conf;
3058         struct ieee80211_channel *channel = ch_switch->channel;
3059         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3060         /*
3061          * MULTI-FIXME
3062          * When we add support for multiple interfaces, we need to
3063          * revisit this. The channel switch command in the device
3064          * only affects the BSS context, but what does that really
3065          * mean? And what if we get a CSA on the second interface?
3066          * This needs a lot of work.
3067          */
3068         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3069         u16 ch;
3070         unsigned long flags = 0;
3071
3072         IWL_DEBUG_MAC80211(priv, "enter\n");
3073
3074         mutex_lock(&priv->mutex);
3075
3076         if (iwl_is_rfkill(priv))
3077                 goto out;
3078
3079         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3080             test_bit(STATUS_SCANNING, &priv->status))
3081                 goto out;
3082
3083         if (!iwl_is_associated_ctx(ctx))
3084                 goto out;
3085
3086         /* channel switch in progress */
3087         if (priv->switch_rxon.switch_in_progress == true)
3088                 goto out;
3089
3090         if (priv->cfg->ops->lib->set_channel_switch) {
3091
3092                 ch = channel->hw_value;
3093                 if (le16_to_cpu(ctx->active.channel) != ch) {
3094                         ch_info = iwl_get_channel_info(priv,
3095                                                        channel->band,
3096                                                        ch);
3097                         if (!is_channel_valid(ch_info)) {
3098                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3099                                 goto out;
3100                         }
3101                         spin_lock_irqsave(&priv->lock, flags);
3102
3103                         priv->current_ht_config.smps = conf->smps_mode;
3104
3105                         /* Configure HT40 channels */
3106                         ctx->ht.enabled = conf_is_ht(conf);
3107                         if (ctx->ht.enabled) {
3108                                 if (conf_is_ht40_minus(conf)) {
3109                                         ctx->ht.extension_chan_offset =
3110                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3111                                         ctx->ht.is_40mhz = true;
3112                                 } else if (conf_is_ht40_plus(conf)) {
3113                                         ctx->ht.extension_chan_offset =
3114                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3115                                         ctx->ht.is_40mhz = true;
3116                                 } else {
3117                                         ctx->ht.extension_chan_offset =
3118                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3119                                         ctx->ht.is_40mhz = false;
3120                                 }
3121                         } else
3122                                 ctx->ht.is_40mhz = false;
3123
3124                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3125                                 ctx->staging.flags = 0;
3126
3127                         iwl_set_rxon_channel(priv, channel, ctx);
3128                         iwl_set_rxon_ht(priv, ht_conf);
3129                         iwl_set_flags_for_band(priv, ctx, channel->band,
3130                                                ctx->vif);
3131                         spin_unlock_irqrestore(&priv->lock, flags);
3132
3133                         iwl_set_rate(priv);
3134                         /*
3135                          * at this point, staging_rxon has the
3136                          * configuration for channel switch
3137                          */
3138                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3139                                                                     ch_switch))
3140                                 priv->switch_rxon.switch_in_progress = false;
3141                 }
3142         }
3143 out:
3144         mutex_unlock(&priv->mutex);
3145         if (!priv->switch_rxon.switch_in_progress)
3146                 ieee80211_chswitch_done(ctx->vif, false);
3147         IWL_DEBUG_MAC80211(priv, "leave\n");
3148 }
3149
3150 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3151                                     unsigned int changed_flags,
3152                                     unsigned int *total_flags,
3153                                     u64 multicast)
3154 {
3155         struct iwl_priv *priv = hw->priv;
3156         __le32 filter_or = 0, filter_nand = 0;
3157         struct iwl_rxon_context *ctx;
3158
3159 #define CHK(test, flag) do { \
3160         if (*total_flags & (test))              \
3161                 filter_or |= (flag);            \
3162         else                                    \
3163                 filter_nand |= (flag);          \
3164         } while (0)
3165
3166         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3167                         changed_flags, *total_flags);
3168
3169         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3170         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3171         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3172         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3173
3174 #undef CHK
3175
3176         mutex_lock(&priv->mutex);
3177
3178         for_each_context(priv, ctx) {
3179                 ctx->staging.filter_flags &= ~filter_nand;
3180                 ctx->staging.filter_flags |= filter_or;
3181
3182                 /*
3183                  * Not committing directly because hardware can perform a scan,
3184                  * but we'll eventually commit the filter flags change anyway.
3185                  */
3186         }
3187
3188         mutex_unlock(&priv->mutex);
3189
3190         /*
3191          * Receiving all multicast frames is always enabled by the
3192          * default flags setup in iwl_connection_init_rx_config()
3193          * since we currently do not support programming multicast
3194          * filters into the device.
3195          */
3196         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3197                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3198 }
3199
3200 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3201 {
3202         struct iwl_priv *priv = hw->priv;
3203
3204         mutex_lock(&priv->mutex);
3205         IWL_DEBUG_MAC80211(priv, "enter\n");
3206
3207         /* do not support "flush" */
3208         if (!priv->cfg->ops->lib->txfifo_flush)
3209                 goto done;
3210
3211         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3212                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3213                 goto done;
3214         }
3215         if (iwl_is_rfkill(priv)) {
3216                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3217                 goto done;
3218         }
3219
3220         /*
3221          * mac80211 will not push any more frames for transmit
3222          * until the flush is completed
3223          */
3224         if (drop) {
3225                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3226                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3227                         IWL_ERR(priv, "flush request fail\n");
3228                         goto done;
3229                 }
3230         }
3231         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3232         iwlagn_wait_tx_queue_empty(priv);
3233 done:
3234         mutex_unlock(&priv->mutex);
3235         IWL_DEBUG_MAC80211(priv, "leave\n");
3236 }
3237
3238 static void iwlagn_disable_roc(struct iwl_priv *priv)
3239 {
3240         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3241         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3242
3243         lockdep_assert_held(&priv->mutex);
3244
3245         if (!ctx->is_active)
3246                 return;
3247
3248         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3249         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3250         iwl_set_rxon_channel(priv, chan, ctx);
3251         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3252
3253         priv->_agn.hw_roc_channel = NULL;
3254
3255         iwlcore_commit_rxon(priv, ctx);
3256
3257         ctx->is_active = false;
3258 }
3259
3260 static void iwlagn_bg_roc_done(struct work_struct *work)
3261 {
3262         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3263                                              _agn.hw_roc_work.work);
3264
3265         mutex_lock(&priv->mutex);
3266         ieee80211_remain_on_channel_expired(priv->hw);
3267         iwlagn_disable_roc(priv);
3268         mutex_unlock(&priv->mutex);
3269 }
3270
3271 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3272                                      struct ieee80211_channel *channel,
3273                                      enum nl80211_channel_type channel_type,
3274                                      int duration)
3275 {
3276         struct iwl_priv *priv = hw->priv;
3277         int err = 0;
3278
3279         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3280                 return -EOPNOTSUPP;
3281
3282         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3283                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3284                 return -EOPNOTSUPP;
3285
3286         mutex_lock(&priv->mutex);
3287
3288         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3289             test_bit(STATUS_SCAN_HW, &priv->status)) {
3290                 err = -EBUSY;
3291                 goto out;
3292         }
3293
3294         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3295         priv->_agn.hw_roc_channel = channel;
3296         priv->_agn.hw_roc_chantype = channel_type;
3297         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3298         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3299         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3300                            msecs_to_jiffies(duration + 20));
3301
3302         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3303         ieee80211_ready_on_channel(priv->hw);
3304
3305  out:
3306         mutex_unlock(&priv->mutex);
3307
3308         return err;
3309 }
3310
3311 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3312 {
3313         struct iwl_priv *priv = hw->priv;
3314
3315         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3316                 return -EOPNOTSUPP;
3317
3318         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3319
3320         mutex_lock(&priv->mutex);
3321         iwlagn_disable_roc(priv);
3322         mutex_unlock(&priv->mutex);
3323
3324         return 0;
3325 }
3326
3327 /*****************************************************************************
3328  *
3329  * driver setup and teardown
3330  *
3331  *****************************************************************************/
3332
3333 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3334 {
3335         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3336
3337         init_waitqueue_head(&priv->wait_command_queue);
3338
3339         INIT_WORK(&priv->restart, iwl_bg_restart);
3340         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3341         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3342         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3343         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3344         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3345         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3346         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3347
3348         iwl_setup_scan_deferred_work(priv);
3349
3350         if (priv->cfg->ops->lib->setup_deferred_work)
3351                 priv->cfg->ops->lib->setup_deferred_work(priv);
3352
3353         init_timer(&priv->statistics_periodic);
3354         priv->statistics_periodic.data = (unsigned long)priv;
3355         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3356
3357         init_timer(&priv->ucode_trace);
3358         priv->ucode_trace.data = (unsigned long)priv;
3359         priv->ucode_trace.function = iwl_bg_ucode_trace;
3360
3361         init_timer(&priv->watchdog);
3362         priv->watchdog.data = (unsigned long)priv;
3363         priv->watchdog.function = iwl_bg_watchdog;
3364
3365         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3366                 iwl_irq_tasklet, (unsigned long)priv);
3367 }
3368
3369 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3370 {
3371         if (priv->cfg->ops->lib->cancel_deferred_work)
3372                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3373
3374         cancel_work_sync(&priv->run_time_calib_work);
3375         cancel_work_sync(&priv->beacon_update);
3376
3377         iwl_cancel_scan_deferred_work(priv);
3378
3379         cancel_work_sync(&priv->bt_full_concurrency);
3380         cancel_work_sync(&priv->bt_runtime_config);
3381
3382         del_timer_sync(&priv->statistics_periodic);
3383         del_timer_sync(&priv->ucode_trace);
3384 }
3385
3386 static void iwl_init_hw_rates(struct iwl_priv *priv,
3387                               struct ieee80211_rate *rates)
3388 {
3389         int i;
3390
3391         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3392                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3393                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3394                 rates[i].hw_value_short = i;
3395                 rates[i].flags = 0;
3396                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3397                         /*
3398                          * If CCK != 1M then set short preamble rate flag.
3399                          */
3400                         rates[i].flags |=
3401                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3402                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3403                 }
3404         }
3405 }
3406
3407 static int iwl_init_drv(struct iwl_priv *priv)
3408 {
3409         int ret;
3410
3411         spin_lock_init(&priv->sta_lock);
3412         spin_lock_init(&priv->hcmd_lock);
3413
3414         INIT_LIST_HEAD(&priv->free_frames);
3415
3416         mutex_init(&priv->mutex);
3417
3418         priv->ieee_channels = NULL;
3419         priv->ieee_rates = NULL;
3420         priv->band = IEEE80211_BAND_2GHZ;
3421
3422         priv->iw_mode = NL80211_IFTYPE_STATION;
3423         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3424         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3425         priv->_agn.agg_tids_count = 0;
3426
3427         /* initialize force reset */
3428         priv->force_reset[IWL_RF_RESET].reset_duration =
3429                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3430         priv->force_reset[IWL_FW_RESET].reset_duration =
3431                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3432
3433         priv->rx_statistics_jiffies = jiffies;
3434
3435         /* Choose which receivers/antennas to use */
3436         if (priv->cfg->ops->hcmd->set_rxon_chain)
3437                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3438                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3439
3440         iwl_init_scan_params(priv);
3441
3442         /* init bt coex */
3443         if (priv->cfg->bt_params &&
3444             priv->cfg->bt_params->advanced_bt_coexist) {
3445                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3446                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3447                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3448                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3449                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3450                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3451         }
3452
3453         ret = iwl_init_channel_map(priv);
3454         if (ret) {
3455                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3456                 goto err;
3457         }
3458
3459         ret = iwlcore_init_geos(priv);
3460         if (ret) {
3461                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3462                 goto err_free_channel_map;
3463         }
3464         iwl_init_hw_rates(priv, priv->ieee_rates);
3465
3466         return 0;
3467
3468 err_free_channel_map:
3469         iwl_free_channel_map(priv);
3470 err:
3471         return ret;
3472 }
3473
3474 static void iwl_uninit_drv(struct iwl_priv *priv)
3475 {
3476         iwl_calib_free_results(priv);
3477         iwlcore_free_geos(priv);
3478         iwl_free_channel_map(priv);
3479         kfree(priv->scan_cmd);
3480 }
3481
3482 struct ieee80211_ops iwlagn_hw_ops = {
3483         .tx = iwlagn_mac_tx,
3484         .start = iwlagn_mac_start,
3485         .stop = iwlagn_mac_stop,
3486         .add_interface = iwl_mac_add_interface,
3487         .remove_interface = iwl_mac_remove_interface,
3488         .change_interface = iwl_mac_change_interface,
3489         .config = iwlagn_mac_config,
3490         .configure_filter = iwlagn_configure_filter,
3491         .set_key = iwlagn_mac_set_key,
3492         .update_tkip_key = iwlagn_mac_update_tkip_key,
3493         .conf_tx = iwl_mac_conf_tx,
3494         .bss_info_changed = iwlagn_bss_info_changed,
3495         .ampdu_action = iwlagn_mac_ampdu_action,
3496         .hw_scan = iwl_mac_hw_scan,
3497         .sta_notify = iwlagn_mac_sta_notify,
3498         .sta_add = iwlagn_mac_sta_add,
3499         .sta_remove = iwl_mac_sta_remove,
3500         .channel_switch = iwlagn_mac_channel_switch,
3501         .flush = iwlagn_mac_flush,
3502         .tx_last_beacon = iwl_mac_tx_last_beacon,
3503         .remain_on_channel = iwl_mac_remain_on_channel,
3504         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3505         .offchannel_tx = iwl_mac_offchannel_tx,
3506         .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3507 };
3508
3509 static u32 iwl_hw_detect(struct iwl_priv *priv)
3510 {
3511         u8 rev_id;
3512
3513         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3514         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
3515         return iwl_read32(priv, CSR_HW_REV);
3516 }
3517
3518 static int iwl_set_hw_params(struct iwl_priv *priv)
3519 {
3520         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3521         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3522         if (priv->cfg->mod_params->amsdu_size_8K)
3523                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3524         else
3525                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3526
3527         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3528
3529         if (priv->cfg->mod_params->disable_11n)
3530                 priv->cfg->sku &= ~IWL_SKU_N;
3531
3532         /* Device-specific setup */
3533         return priv->cfg->ops->lib->set_hw_params(priv);
3534 }
3535
3536 static const u8 iwlagn_bss_ac_to_fifo[] = {
3537         IWL_TX_FIFO_VO,
3538         IWL_TX_FIFO_VI,
3539         IWL_TX_FIFO_BE,
3540         IWL_TX_FIFO_BK,
3541 };
3542
3543 static const u8 iwlagn_bss_ac_to_queue[] = {
3544         0, 1, 2, 3,
3545 };
3546
3547 static const u8 iwlagn_pan_ac_to_fifo[] = {
3548         IWL_TX_FIFO_VO_IPAN,
3549         IWL_TX_FIFO_VI_IPAN,
3550         IWL_TX_FIFO_BE_IPAN,
3551         IWL_TX_FIFO_BK_IPAN,
3552 };
3553
3554 static const u8 iwlagn_pan_ac_to_queue[] = {
3555         7, 6, 5, 4,
3556 };
3557
3558 /* This function both allocates and initializes hw and priv. */
3559 static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
3560 {
3561         struct iwl_priv *priv;
3562         /* mac80211 allocates memory for this device instance, including
3563          *   space for this driver's private structure */
3564         struct ieee80211_hw *hw;
3565
3566         hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops);
3567         if (hw == NULL) {
3568                 pr_err("%s: Can not allocate network device\n",
3569                        cfg->name);
3570                 goto out;
3571         }
3572
3573         priv = hw->priv;
3574         priv->hw = hw;
3575
3576 out:
3577         return hw;
3578 }
3579
3580 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3581 {
3582         int err = 0, i;
3583         struct iwl_priv *priv;
3584         struct ieee80211_hw *hw;
3585         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3586         unsigned long flags;
3587         u16 pci_cmd, num_mac;
3588         u32 hw_rev;
3589
3590         /************************
3591          * 1. Allocating HW data
3592          ************************/
3593
3594         hw = iwl_alloc_all(cfg);
3595         if (!hw) {
3596                 err = -ENOMEM;
3597                 goto out;
3598         }
3599         priv = hw->priv;
3600         /* At this point both hw and priv are allocated. */
3601
3602         priv->ucode_type = UCODE_SUBTYPE_NONE_LOADED;
3603
3604         /*
3605          * The default context is always valid,
3606          * more may be discovered when firmware
3607          * is loaded.
3608          */
3609         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3610
3611         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3612                 priv->contexts[i].ctxid = i;
3613
3614         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3615         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3616         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3617         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3618         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3619         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3620         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3621         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3622         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3623         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3624         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3625                 BIT(NL80211_IFTYPE_ADHOC);
3626         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3627                 BIT(NL80211_IFTYPE_STATION);
3628         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3629         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3630         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3631         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3632
3633         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3634         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3635         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3636         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3637         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3638         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3639         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3640         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3641         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3642         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3643         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3644         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3645                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3646 #ifdef CONFIG_IWL_P2P
3647         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3648                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3649 #endif
3650         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3651         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3652         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3653
3654         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3655
3656         SET_IEEE80211_DEV(hw, &pdev->dev);
3657
3658         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3659         priv->cfg = cfg;
3660         priv->pci_dev = pdev;
3661         priv->inta_mask = CSR_INI_SET_MASK;
3662
3663         /* is antenna coupling more than 35dB ? */
3664         priv->bt_ant_couple_ok =
3665                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3666                 true : false;
3667
3668         /* enable/disable bt channel inhibition */
3669         priv->bt_ch_announce = iwlagn_bt_ch_announce;
3670         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3671                        (priv->bt_ch_announce) ? "On" : "Off");
3672
3673         if (iwl_alloc_traffic_mem(priv))
3674                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3675
3676         /**************************
3677          * 2. Initializing PCI bus
3678          **************************/
3679         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3680                                 PCIE_LINK_STATE_CLKPM);
3681
3682         if (pci_enable_device(pdev)) {
3683                 err = -ENODEV;
3684                 goto out_ieee80211_free_hw;
3685         }
3686
3687         pci_set_master(pdev);
3688
3689         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3690         if (!err)
3691                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3692         if (err) {
3693                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3694                 if (!err)
3695                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3696                 /* both attempts failed: */
3697                 if (err) {
3698                         IWL_WARN(priv, "No suitable DMA available.\n");
3699                         goto out_pci_disable_device;
3700                 }
3701         }
3702
3703         err = pci_request_regions(pdev, DRV_NAME);
3704         if (err)
3705                 goto out_pci_disable_device;
3706
3707         pci_set_drvdata(pdev, priv);
3708
3709
3710         /***********************
3711          * 3. Read REV register
3712          ***********************/
3713         priv->hw_base = pci_iomap(pdev, 0, 0);
3714         if (!priv->hw_base) {
3715                 err = -ENODEV;
3716                 goto out_pci_release_regions;
3717         }
3718
3719         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3720                 (unsigned long long) pci_resource_len(pdev, 0));
3721         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3722
3723         /* these spin locks will be used in apm_ops.init and EEPROM access
3724          * we should init now
3725          */
3726         spin_lock_init(&priv->reg_lock);
3727         spin_lock_init(&priv->lock);
3728
3729         /*
3730          * stop and reset the on-board processor just in case it is in a
3731          * strange state ... like being left stranded by a primary kernel
3732          * and this is now the kdump kernel trying to start up
3733          */
3734         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3735
3736         hw_rev = iwl_hw_detect(priv);
3737         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3738                 priv->cfg->name, hw_rev);
3739
3740         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3741          * PCI Tx retries from interfering with C3 CPU state */
3742         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3743
3744         if (iwl_prepare_card_hw(priv)) {
3745                 IWL_WARN(priv, "Failed, HW not ready\n");
3746                 goto out_iounmap;
3747         }
3748
3749         /*****************
3750          * 4. Read EEPROM
3751          *****************/
3752         /* Read the EEPROM */
3753         err = iwl_eeprom_init(priv, hw_rev);
3754         if (err) {
3755                 IWL_ERR(priv, "Unable to init EEPROM\n");
3756                 goto out_iounmap;
3757         }
3758         err = iwl_eeprom_check_version(priv);
3759         if (err)
3760                 goto out_free_eeprom;
3761
3762         err = iwl_eeprom_check_sku(priv);
3763         if (err)
3764                 goto out_free_eeprom;
3765
3766         /* extract MAC Address */
3767         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3768         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3769         priv->hw->wiphy->addresses = priv->addresses;
3770         priv->hw->wiphy->n_addresses = 1;
3771         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3772         if (num_mac > 1) {
3773                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3774                        ETH_ALEN);
3775                 priv->addresses[1].addr[5]++;
3776                 priv->hw->wiphy->n_addresses++;
3777         }
3778
3779         /************************
3780          * 5. Setup HW constants
3781          ************************/
3782         if (iwl_set_hw_params(priv)) {
3783                 IWL_ERR(priv, "failed to set hw parameters\n");
3784                 goto out_free_eeprom;
3785         }
3786
3787         /*******************
3788          * 6. Setup priv
3789          *******************/
3790
3791         err = iwl_init_drv(priv);
3792         if (err)
3793                 goto out_free_eeprom;
3794         /* At this point both hw and priv are initialized. */
3795
3796         /********************
3797          * 7. Setup services
3798          ********************/
3799         spin_lock_irqsave(&priv->lock, flags);
3800         iwl_disable_interrupts(priv);
3801         spin_unlock_irqrestore(&priv->lock, flags);
3802
3803         pci_enable_msi(priv->pci_dev);
3804
3805         iwl_alloc_isr_ict(priv);
3806
3807         err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
3808                           IRQF_SHARED, DRV_NAME, priv);
3809         if (err) {
3810                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3811                 goto out_disable_msi;
3812         }
3813
3814         iwl_setup_deferred_work(priv);
3815         iwl_setup_rx_handlers(priv);
3816
3817         /*********************************************
3818          * 8. Enable interrupts and read RFKILL state
3819          *********************************************/
3820
3821         /* enable rfkill interrupt: hw bug w/a */
3822         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3823         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3824                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3825                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3826         }
3827
3828         iwl_enable_rfkill_int(priv);
3829
3830         /* If platform's RF_KILL switch is NOT set to KILL */
3831         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3832                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3833         else
3834                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3835
3836         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3837                 test_bit(STATUS_RF_KILL_HW, &priv->status));
3838
3839         iwl_power_initialize(priv);
3840         iwl_tt_initialize(priv);
3841
3842         init_completion(&priv->_agn.firmware_loading_complete);
3843
3844         err = iwl_request_firmware(priv, true);
3845         if (err)
3846                 goto out_destroy_workqueue;
3847
3848         return 0;
3849
3850  out_destroy_workqueue:
3851         destroy_workqueue(priv->workqueue);
3852         priv->workqueue = NULL;
3853         free_irq(priv->pci_dev->irq, priv);
3854         iwl_free_isr_ict(priv);
3855  out_disable_msi:
3856         pci_disable_msi(priv->pci_dev);
3857         iwl_uninit_drv(priv);
3858  out_free_eeprom:
3859         iwl_eeprom_free(priv);
3860  out_iounmap:
3861         pci_iounmap(pdev, priv->hw_base);
3862  out_pci_release_regions:
3863         pci_set_drvdata(pdev, NULL);
3864         pci_release_regions(pdev);
3865  out_pci_disable_device:
3866         pci_disable_device(pdev);
3867  out_ieee80211_free_hw:
3868         iwl_free_traffic_mem(priv);
3869         ieee80211_free_hw(priv->hw);
3870  out:
3871         return err;
3872 }
3873
3874 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3875 {
3876         struct iwl_priv *priv = pci_get_drvdata(pdev);
3877         unsigned long flags;
3878
3879         if (!priv)
3880                 return;
3881
3882         wait_for_completion(&priv->_agn.firmware_loading_complete);
3883
3884         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3885
3886         iwl_dbgfs_unregister(priv);
3887         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3888
3889         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3890          * to be called and iwl_down since we are removing the device
3891          * we need to set STATUS_EXIT_PENDING bit.
3892          */
3893         set_bit(STATUS_EXIT_PENDING, &priv->status);
3894
3895         iwl_leds_exit(priv);
3896
3897         if (priv->mac80211_registered) {
3898                 ieee80211_unregister_hw(priv->hw);
3899                 priv->mac80211_registered = 0;
3900         }
3901
3902         /* Reset to low power before unloading driver. */
3903         iwl_apm_stop(priv);
3904
3905         iwl_tt_exit(priv);
3906
3907         /* make sure we flush any pending irq or
3908          * tasklet for the driver
3909          */
3910         spin_lock_irqsave(&priv->lock, flags);
3911         iwl_disable_interrupts(priv);
3912         spin_unlock_irqrestore(&priv->lock, flags);
3913
3914         iwl_synchronize_irq(priv);
3915
3916         iwl_dealloc_ucode_pci(priv);
3917
3918         if (priv->rxq.bd)
3919                 iwlagn_rx_queue_free(priv, &priv->rxq);
3920         iwlagn_hw_txq_ctx_free(priv);
3921
3922         iwl_eeprom_free(priv);
3923
3924
3925         /*netif_stop_queue(dev); */
3926         flush_workqueue(priv->workqueue);
3927
3928         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3929          * priv->workqueue... so we can't take down the workqueue
3930          * until now... */
3931         destroy_workqueue(priv->workqueue);
3932         priv->workqueue = NULL;
3933         iwl_free_traffic_mem(priv);
3934
3935         free_irq(priv->pci_dev->irq, priv);
3936         pci_disable_msi(priv->pci_dev);
3937         pci_iounmap(pdev, priv->hw_base);
3938         pci_release_regions(pdev);
3939         pci_disable_device(pdev);
3940         pci_set_drvdata(pdev, NULL);
3941
3942         iwl_uninit_drv(priv);
3943
3944         iwl_free_isr_ict(priv);
3945
3946         dev_kfree_skb(priv->beacon_skb);
3947
3948         ieee80211_free_hw(priv->hw);
3949 }
3950
3951
3952 /*****************************************************************************
3953  *
3954  * driver and module entry point
3955  *
3956  *****************************************************************************/
3957
3958 /* Hardware specific file defines the PCI IDs table for that hardware module */
3959 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
3960         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3961         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3962         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3963         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3964         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3965         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3966         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3967         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3968         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3969         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3970         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3971         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3972         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3973         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3974         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3975         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3976         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3977         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3978         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3979         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3980         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3981         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3982         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3983         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3984
3985 /* 5300 Series WiFi */
3986         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3987         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3988         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3989         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3990         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3991         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3992         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3993         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3994         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3995         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3996         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3997         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3998
3999 /* 5350 Series WiFi/WiMax */
4000         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4001         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4002         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4003
4004 /* 5150 Series Wifi/WiMax */
4005         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4006         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4007         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4008         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4009         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4010         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4011
4012         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4013         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4014         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4015         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4016
4017 /* 6x00 Series */
4018         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4019         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4020         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4021         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4022         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4023         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4024         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4025         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4026         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4027         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4028
4029 /* 6x05 Series */
4030         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4031         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4032         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4033         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4034         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4035         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4036         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4037
4038 /* 6x30 Series */
4039         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4040         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4041         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4042         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4043         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4044         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4045         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4046         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4047         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4048         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4049         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4050         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4051         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4052         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4053         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4054         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4055
4056 /* 6x50 WiFi/WiMax Series */
4057         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4058         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4059         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4060         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4061         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4062         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4063
4064 /* 6150 WiFi/WiMax Series */
4065         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4066         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4067         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4068         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4069         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4070         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4071
4072 /* 1000 Series WiFi */
4073         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4074         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4075         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4076         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4077         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4078         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4079         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4080         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4081         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4082         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4083         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4084         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4085
4086 /* 100 Series WiFi */
4087         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4088         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4089         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4090         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4091         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4092         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4093
4094 /* 130 Series WiFi */
4095         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4096         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4097         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4098         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4099         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4100         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4101
4102 /* 2x00 Series */
4103         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4104         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4105         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4106         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4107         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4108         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4109
4110 /* 2x30 Series */
4111         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4112         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4113         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4114         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4115         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4116         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4117
4118 /* 6x35 Series */
4119         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4120         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4121         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4122         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4123         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4124         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4125         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4126         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4127         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4128
4129 /* 200 Series */
4130         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4131         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4132         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4133         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4134         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4135         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4136
4137 /* 230 Series */
4138         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4139         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4140         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4141         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4142         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4143         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4144
4145         {0}
4146 };
4147 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4148
4149 static struct pci_driver iwl_driver = {
4150         .name = DRV_NAME,
4151         .id_table = iwl_hw_card_ids,
4152         .probe = iwl_pci_probe,
4153         .remove = __devexit_p(iwl_pci_remove),
4154         .driver.pm = IWL_PM_OPS,
4155 };
4156
4157 static int __init iwl_init(void)
4158 {
4159
4160         int ret;
4161         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4162         pr_info(DRV_COPYRIGHT "\n");
4163
4164         ret = iwlagn_rate_control_register();
4165         if (ret) {
4166                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4167                 return ret;
4168         }
4169
4170         ret = pci_register_driver(&iwl_driver);
4171         if (ret) {
4172                 pr_err("Unable to initialize PCI module\n");
4173                 goto error_register;
4174         }
4175
4176         return ret;
4177
4178 error_register:
4179         iwlagn_rate_control_unregister();
4180         return ret;
4181 }
4182
4183 static void __exit iwl_exit(void)
4184 {
4185         pci_unregister_driver(&iwl_driver);
4186         iwlagn_rate_control_unregister();
4187 }
4188
4189 module_exit(iwl_exit);
4190 module_init(iwl_init);
4191
4192 #ifdef CONFIG_IWLWIFI_DEBUG
4193 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4194 MODULE_PARM_DESC(debug, "debug output mask");
4195 #endif
4196
4197 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4198 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4199 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4200 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4201 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4202 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4203 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4204                    int, S_IRUGO);
4205 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4206 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4207 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4208
4209 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4210                    S_IRUGO);
4211 MODULE_PARM_DESC(ucode_alternative,
4212                  "specify ucode alternative to use from ucode file");
4213
4214 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4215 MODULE_PARM_DESC(antenna_coupling,
4216                  "specify antenna coupling in dB (defualt: 0 dB)");
4217
4218 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4219 MODULE_PARM_DESC(bt_ch_inhibition,
4220                  "Disable BT channel inhibition (default: enable)");
4221
4222 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4223 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4224
4225 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4226 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");