1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
48 #include <net/mac80211.h>
50 #include <asm/div64.h>
52 #define DRV_NAME "iwlagn"
54 #include "iwl-eeprom.h"
58 #include "iwl-helpers.h"
60 #include "iwl-calib.h"
64 /******************************************************************************
68 ******************************************************************************/
71 * module name, copyright, version, etc.
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
75 #ifdef CONFIG_IWLWIFI_DEBUG
81 #define DRV_VERSION IWLWIFI_VERSION VD
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88 MODULE_ALIAS("iwl4965");
90 static int iwlagn_ant_coupling;
91 static bool iwlagn_bt_ch_announce = 1;
94 * iwl_commit_rxon - commit staging_rxon to hardware
96 * The RXON command in staging_rxon is committed to the hardware and
97 * the active_rxon structure is updated with the new data. This
98 * function correctly transitions out of the RXON_ASSOC_MSK state if
99 * a HW tune is required based on the RXON structure changes.
101 int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
103 /* cast away the const for active_rxon in this function */
104 struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
107 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
109 if (!iwl_is_alive(priv))
112 /* always get timestamp with Rx frame */
113 ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
115 ret = iwl_check_rxon_cmd(priv, ctx);
117 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
122 * receive commit_rxon request
123 * abort any previous channel switch if still in process
125 if (priv->switch_rxon.switch_in_progress &&
126 (priv->switch_rxon.channel != ctx->staging.channel)) {
127 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
128 le16_to_cpu(priv->switch_rxon.channel));
129 iwl_chswitch_done(priv, false);
132 /* If we don't need to send a full RXON, we can use
133 * iwl_rxon_assoc_cmd which is used to reconfigure filter
134 * and other flags for the current radio configuration. */
135 if (!iwl_full_rxon_required(priv, ctx)) {
136 ret = iwl_send_rxon_assoc(priv, ctx);
138 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
142 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
143 iwl_print_rx_config_cmd(priv, ctx);
147 /* If we are currently associated and the new config requires
148 * an RXON_ASSOC and the new config wants the associated mask enabled,
149 * we must clear the associated from the active configuration
150 * before we apply the new config */
151 if (iwl_is_associated_ctx(ctx) && new_assoc) {
152 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
153 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
155 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
156 sizeof(struct iwl_rxon_cmd),
159 /* If the mask clearing failed then we set
160 * active_rxon back to what it was previously */
162 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
163 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
166 iwl_clear_ucode_stations(priv, ctx);
167 iwl_restore_stations(priv, ctx);
168 ret = iwl_restore_default_wep_keys(priv);
170 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
175 IWL_DEBUG_INFO(priv, "Sending RXON\n"
176 "* with%s RXON_FILTER_ASSOC_MSK\n"
179 (new_assoc ? "" : "out"),
180 le16_to_cpu(ctx->staging.channel),
181 ctx->staging.bssid_addr);
183 iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
185 /* Apply the new configuration
186 * RXON unassoc clears the station table in uCode so restoration of
187 * stations is needed after it (the RXON command) completes
190 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
191 sizeof(struct iwl_rxon_cmd), &ctx->staging);
193 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
196 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
197 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
198 iwl_clear_ucode_stations(priv, ctx);
199 iwl_restore_stations(priv, ctx);
200 ret = iwl_restore_default_wep_keys(priv);
202 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
207 priv->start_calib = 0;
209 /* Apply the new configuration
210 * RXON assoc doesn't clear the station table in uCode,
212 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
213 sizeof(struct iwl_rxon_cmd), &ctx->staging);
215 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
218 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
220 iwl_print_rx_config_cmd(priv, ctx);
222 iwl_init_sensitivity(priv);
224 /* If we issue a new RXON command which required a tune then we must
225 * send a new TXPOWER command or we won't be able to Tx any frames */
226 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
228 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
235 void iwl_update_chain_flags(struct iwl_priv *priv)
237 struct iwl_rxon_context *ctx;
239 if (priv->cfg->ops->hcmd->set_rxon_chain) {
240 for_each_context(priv, ctx) {
241 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
242 iwlcore_commit_rxon(priv, ctx);
247 static void iwl_clear_free_frames(struct iwl_priv *priv)
249 struct list_head *element;
251 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
254 while (!list_empty(&priv->free_frames)) {
255 element = priv->free_frames.next;
257 kfree(list_entry(element, struct iwl_frame, list));
258 priv->frames_count--;
261 if (priv->frames_count) {
262 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
264 priv->frames_count = 0;
268 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
270 struct iwl_frame *frame;
271 struct list_head *element;
272 if (list_empty(&priv->free_frames)) {
273 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
275 IWL_ERR(priv, "Could not allocate frame!\n");
279 priv->frames_count++;
283 element = priv->free_frames.next;
285 return list_entry(element, struct iwl_frame, list);
288 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
290 memset(frame, 0, sizeof(*frame));
291 list_add(&frame->list, &priv->free_frames);
294 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
295 struct ieee80211_hdr *hdr,
298 if (!priv->ibss_beacon)
301 if (priv->ibss_beacon->len > left)
304 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
306 return priv->ibss_beacon->len;
309 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
310 static void iwl_set_beacon_tim(struct iwl_priv *priv,
311 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
312 u8 *beacon, u32 frame_size)
315 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
318 * The index is relative to frame start but we start looking at the
319 * variable-length part of the beacon.
321 tim_idx = mgmt->u.beacon.variable - beacon;
323 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
324 while ((tim_idx < (frame_size - 2)) &&
325 (beacon[tim_idx] != WLAN_EID_TIM))
326 tim_idx += beacon[tim_idx+1] + 2;
328 /* If TIM field was found, set variables */
329 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
330 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
331 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
333 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
336 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
337 struct iwl_frame *frame)
339 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
344 * We have to set up the TX command, the TX Beacon command, and the
348 /* Initialize memory */
349 tx_beacon_cmd = &frame->u.beacon;
350 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
352 /* Set up TX beacon contents */
353 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
354 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
355 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
358 /* Set up TX command fields */
359 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
360 #warning "Use proper STA ID"
361 tx_beacon_cmd->tx.sta_id =
362 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
363 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
364 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
365 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
367 /* Set up TX beacon command fields */
368 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
371 /* Set up packet rate and flags */
372 rate = iwl_rate_get_lowest_plcp(priv);
373 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
374 priv->hw_params.valid_tx_ant);
375 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
376 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
377 rate_flags |= RATE_MCS_CCK_MSK;
378 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
381 return sizeof(*tx_beacon_cmd) + frame_size;
383 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
385 struct iwl_frame *frame;
386 unsigned int frame_size;
389 frame = iwl_get_free_frame(priv);
391 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
396 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
398 IWL_ERR(priv, "Error configuring the beacon command\n");
399 iwl_free_frame(priv, frame);
403 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
406 iwl_free_frame(priv, frame);
411 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
413 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
415 dma_addr_t addr = get_unaligned_le32(&tb->lo);
416 if (sizeof(dma_addr_t) > sizeof(u32))
418 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
423 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
425 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
427 return le16_to_cpu(tb->hi_n_len) >> 4;
430 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
431 dma_addr_t addr, u16 len)
433 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
434 u16 hi_n_len = len << 4;
436 put_unaligned_le32(addr, &tb->lo);
437 if (sizeof(dma_addr_t) > sizeof(u32))
438 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
440 tb->hi_n_len = cpu_to_le16(hi_n_len);
442 tfd->num_tbs = idx + 1;
445 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
447 return tfd->num_tbs & 0x1f;
451 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
452 * @priv - driver private data
455 * Does NOT advance any TFD circular buffer read/write indexes
456 * Does NOT free the TFD itself (which is within circular buffer)
458 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
460 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
462 struct pci_dev *dev = priv->pci_dev;
463 int index = txq->q.read_ptr;
467 tfd = &tfd_tmp[index];
469 /* Sanity check on number of chunks */
470 num_tbs = iwl_tfd_get_num_tbs(tfd);
472 if (num_tbs >= IWL_NUM_OF_TBS) {
473 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
474 /* @todo issue fatal error, it is quite serious situation */
480 pci_unmap_single(dev,
481 dma_unmap_addr(&txq->meta[index], mapping),
482 dma_unmap_len(&txq->meta[index], len),
483 PCI_DMA_BIDIRECTIONAL);
485 /* Unmap chunks, if any. */
486 for (i = 1; i < num_tbs; i++)
487 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
488 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
494 skb = txq->txb[txq->q.read_ptr].skb;
496 /* can be called from irqs-disabled context */
498 dev_kfree_skb_any(skb);
499 txq->txb[txq->q.read_ptr].skb = NULL;
504 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
505 struct iwl_tx_queue *txq,
506 dma_addr_t addr, u16 len,
510 struct iwl_tfd *tfd, *tfd_tmp;
514 tfd_tmp = (struct iwl_tfd *)txq->tfds;
515 tfd = &tfd_tmp[q->write_ptr];
518 memset(tfd, 0, sizeof(*tfd));
520 num_tbs = iwl_tfd_get_num_tbs(tfd);
522 /* Each TFD can point to a maximum 20 Tx buffers */
523 if (num_tbs >= IWL_NUM_OF_TBS) {
524 IWL_ERR(priv, "Error can not send more than %d chunks\n",
529 BUG_ON(addr & ~DMA_BIT_MASK(36));
530 if (unlikely(addr & ~IWL_TX_DMA_MASK))
531 IWL_ERR(priv, "Unaligned address = %llx\n",
532 (unsigned long long)addr);
534 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
540 * Tell nic where to find circular buffer of Tx Frame Descriptors for
541 * given Tx queue, and enable the DMA channel used for that queue.
543 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
544 * channels supported in hardware.
546 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
547 struct iwl_tx_queue *txq)
549 int txq_id = txq->q.id;
551 /* Circular buffer (TFD queue in DRAM) physical base address */
552 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
553 txq->q.dma_addr >> 8);
558 /******************************************************************************
560 * Generic RX handler implementations
562 ******************************************************************************/
563 static void iwl_rx_reply_alive(struct iwl_priv *priv,
564 struct iwl_rx_mem_buffer *rxb)
566 struct iwl_rx_packet *pkt = rxb_addr(rxb);
567 struct iwl_alive_resp *palive;
568 struct delayed_work *pwork;
570 palive = &pkt->u.alive_frame;
572 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
574 palive->is_valid, palive->ver_type,
575 palive->ver_subtype);
577 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
578 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
579 memcpy(&priv->card_alive_init,
581 sizeof(struct iwl_init_alive_resp));
582 pwork = &priv->init_alive_start;
584 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
585 memcpy(&priv->card_alive, &pkt->u.alive_frame,
586 sizeof(struct iwl_alive_resp));
587 pwork = &priv->alive_start;
590 /* We delay the ALIVE response by 5ms to
591 * give the HW RF Kill time to activate... */
592 if (palive->is_valid == UCODE_VALID_OK)
593 queue_delayed_work(priv->workqueue, pwork,
594 msecs_to_jiffies(5));
596 IWL_WARN(priv, "uCode did not respond OK.\n");
599 static void iwl_bg_beacon_update(struct work_struct *work)
601 struct iwl_priv *priv =
602 container_of(work, struct iwl_priv, beacon_update);
603 struct sk_buff *beacon;
605 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
606 #warning "introduce and use beacon context"
607 beacon = ieee80211_beacon_get(priv->hw,
608 priv->contexts[IWL_RXON_CTX_BSS].vif);
611 IWL_ERR(priv, "update beacon failed\n");
615 mutex_lock(&priv->mutex);
616 /* new beacon skb is allocated every time; dispose previous.*/
617 if (priv->ibss_beacon)
618 dev_kfree_skb(priv->ibss_beacon);
620 priv->ibss_beacon = beacon;
621 mutex_unlock(&priv->mutex);
623 iwl_send_beacon_cmd(priv);
626 static void iwl_bg_bt_runtime_config(struct work_struct *work)
628 struct iwl_priv *priv =
629 container_of(work, struct iwl_priv, bt_runtime_config);
631 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
634 /* dont send host command if rf-kill is on */
635 if (!iwl_is_ready_rf(priv))
637 priv->cfg->ops->hcmd->send_bt_config(priv);
640 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
642 struct iwl_priv *priv =
643 container_of(work, struct iwl_priv, bt_full_concurrency);
644 struct iwl_rxon_context *ctx;
646 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
649 /* dont send host command if rf-kill is on */
650 if (!iwl_is_ready_rf(priv))
653 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
654 priv->bt_full_concurrent ?
655 "full concurrency" : "3-wire");
658 * LQ & RXON updated cmds must be sent before BT Config cmd
659 * to avoid 3-wire collisions
661 mutex_lock(&priv->mutex);
662 for_each_context(priv, ctx) {
663 if (priv->cfg->ops->hcmd->set_rxon_chain)
664 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
665 iwlcore_commit_rxon(priv, ctx);
667 mutex_unlock(&priv->mutex);
669 priv->cfg->ops->hcmd->send_bt_config(priv);
673 * iwl_bg_statistics_periodic - Timer callback to queue statistics
675 * This callback is provided in order to send a statistics request.
677 * This timer function is continually reset to execute within
678 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
679 * was received. We need to ensure we receive the statistics in order
680 * to update the temperature used for calibrating the TXPOWER.
682 static void iwl_bg_statistics_periodic(unsigned long data)
684 struct iwl_priv *priv = (struct iwl_priv *)data;
686 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
689 /* dont send host command if rf-kill is on */
690 if (!iwl_is_ready_rf(priv))
693 iwl_send_statistics_request(priv, CMD_ASYNC, false);
697 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
698 u32 start_idx, u32 num_events,
702 u32 ptr; /* SRAM byte address of log data */
703 u32 ev, time, data; /* event log data */
704 unsigned long reg_flags;
707 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
709 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
711 /* Make sure device is powered up for SRAM reads */
712 spin_lock_irqsave(&priv->reg_lock, reg_flags);
713 if (iwl_grab_nic_access(priv)) {
714 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
718 /* Set starting address; reads will auto-increment */
719 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
723 * "time" is actually "data" for mode 0 (no timestamp).
724 * place event id # at far right for easier visual parsing.
726 for (i = 0; i < num_events; i++) {
727 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
728 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
730 trace_iwlwifi_dev_ucode_cont_event(priv,
733 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
734 trace_iwlwifi_dev_ucode_cont_event(priv,
738 /* Allow device to power down */
739 iwl_release_nic_access(priv);
740 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
743 static void iwl_continuous_event_trace(struct iwl_priv *priv)
745 u32 capacity; /* event log capacity in # entries */
746 u32 base; /* SRAM byte address of event log header */
747 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
748 u32 num_wraps; /* # times uCode wrapped to top of log */
749 u32 next_entry; /* index of next entry to be written by uCode */
751 if (priv->ucode_type == UCODE_INIT)
752 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
754 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
755 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
756 capacity = iwl_read_targ_mem(priv, base);
757 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
758 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
759 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
763 if (num_wraps == priv->event_log.num_wraps) {
764 iwl_print_cont_event_trace(priv,
765 base, priv->event_log.next_entry,
766 next_entry - priv->event_log.next_entry,
768 priv->event_log.non_wraps_count++;
770 if ((num_wraps - priv->event_log.num_wraps) > 1)
771 priv->event_log.wraps_more_count++;
773 priv->event_log.wraps_once_count++;
774 trace_iwlwifi_dev_ucode_wrap_event(priv,
775 num_wraps - priv->event_log.num_wraps,
776 next_entry, priv->event_log.next_entry);
777 if (next_entry < priv->event_log.next_entry) {
778 iwl_print_cont_event_trace(priv, base,
779 priv->event_log.next_entry,
780 capacity - priv->event_log.next_entry,
783 iwl_print_cont_event_trace(priv, base, 0,
786 iwl_print_cont_event_trace(priv, base,
787 next_entry, capacity - next_entry,
790 iwl_print_cont_event_trace(priv, base, 0,
794 priv->event_log.num_wraps = num_wraps;
795 priv->event_log.next_entry = next_entry;
799 * iwl_bg_ucode_trace - Timer callback to log ucode event
801 * The timer is continually set to execute every
802 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
803 * this function is to perform continuous uCode event logging operation
806 static void iwl_bg_ucode_trace(unsigned long data)
808 struct iwl_priv *priv = (struct iwl_priv *)data;
810 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
813 if (priv->event_log.ucode_trace) {
814 iwl_continuous_event_trace(priv);
815 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
816 mod_timer(&priv->ucode_trace,
817 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
821 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
822 struct iwl_rx_mem_buffer *rxb)
824 struct iwl_rx_packet *pkt = rxb_addr(rxb);
825 struct iwl4965_beacon_notif *beacon =
826 (struct iwl4965_beacon_notif *)pkt->u.raw;
827 #ifdef CONFIG_IWLWIFI_DEBUG
828 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
830 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
831 "tsf %d %d rate %d\n",
832 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
833 beacon->beacon_notify_hdr.failure_frame,
834 le32_to_cpu(beacon->ibss_mgr_status),
835 le32_to_cpu(beacon->high_tsf),
836 le32_to_cpu(beacon->low_tsf), rate);
839 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
841 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
842 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
843 queue_work(priv->workqueue, &priv->beacon_update);
846 /* Handle notification from uCode that card's power state is changing
847 * due to software, hardware, or critical temperature RFKILL */
848 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
849 struct iwl_rx_mem_buffer *rxb)
851 struct iwl_rx_packet *pkt = rxb_addr(rxb);
852 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
853 unsigned long status = priv->status;
855 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
856 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
857 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
858 (flags & CT_CARD_DISABLED) ?
859 "Reached" : "Not reached");
861 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
864 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
865 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
867 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
868 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
870 if (!(flags & RXON_CARD_DISABLED)) {
871 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
872 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
873 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
874 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
876 if (flags & CT_CARD_DISABLED)
877 iwl_tt_enter_ct_kill(priv);
879 if (!(flags & CT_CARD_DISABLED))
880 iwl_tt_exit_ct_kill(priv);
882 if (flags & HW_CARD_DISABLED)
883 set_bit(STATUS_RF_KILL_HW, &priv->status);
885 clear_bit(STATUS_RF_KILL_HW, &priv->status);
888 if (!(flags & RXON_CARD_DISABLED))
889 iwl_scan_cancel(priv);
891 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
892 test_bit(STATUS_RF_KILL_HW, &priv->status)))
893 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
894 test_bit(STATUS_RF_KILL_HW, &priv->status));
896 wake_up_interruptible(&priv->wait_command_queue);
899 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
901 if (src == IWL_PWR_SRC_VAUX) {
902 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
903 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
904 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
905 ~APMG_PS_CTRL_MSK_PWR_SRC);
907 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
908 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
909 ~APMG_PS_CTRL_MSK_PWR_SRC);
915 static void iwl_bg_tx_flush(struct work_struct *work)
917 struct iwl_priv *priv =
918 container_of(work, struct iwl_priv, tx_flush);
920 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
923 /* do nothing if rf-kill is on */
924 if (!iwl_is_ready_rf(priv))
927 if (priv->cfg->ops->lib->txfifo_flush) {
928 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
929 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
934 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
936 * Setup the RX handlers for each of the reply types sent from the uCode
939 * This function chains into the hardware specific files for them to setup
940 * any hardware specific handlers as well.
942 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
944 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
945 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
946 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
947 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
948 iwl_rx_spectrum_measure_notif;
949 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
950 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
951 iwl_rx_pm_debug_statistics_notif;
952 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
955 * The same handler is used for both the REPLY to a discrete
956 * statistics request from the host as well as for the periodic
957 * statistics notifications (after received beacons) from the uCode.
959 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
960 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
962 iwl_setup_rx_scan_handlers(priv);
964 /* status change handler */
965 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
967 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
968 iwl_rx_missed_beacon_notif;
970 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
971 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
973 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
974 /* Set up hardware specific Rx handlers */
975 priv->cfg->ops->lib->rx_handler_setup(priv);
979 * iwl_rx_handle - Main entry function for receiving responses from uCode
981 * Uses the priv->rx_handlers callback function array to invoke
982 * the appropriate handlers, including command responses,
983 * frame-received notifications, and other notifications.
985 void iwl_rx_handle(struct iwl_priv *priv)
987 struct iwl_rx_mem_buffer *rxb;
988 struct iwl_rx_packet *pkt;
989 struct iwl_rx_queue *rxq = &priv->rxq;
997 /* uCode's read index (stored in shared DRAM) indicates the last Rx
998 * buffer that the driver may process (last buffer filled by ucode). */
999 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
1002 /* Rx interrupt, but nothing sent from uCode */
1004 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
1006 /* calculate total frames need to be restock after handling RX */
1007 total_empty = r - rxq->write_actual;
1008 if (total_empty < 0)
1009 total_empty += RX_QUEUE_SIZE;
1011 if (total_empty > (RX_QUEUE_SIZE / 2))
1017 rxb = rxq->queue[i];
1019 /* If an RXB doesn't have a Rx queue slot associated with it,
1020 * then a bug has been introduced in the queue refilling
1021 * routines -- catch it here */
1022 BUG_ON(rxb == NULL);
1024 rxq->queue[i] = NULL;
1026 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1027 PAGE_SIZE << priv->hw_params.rx_page_order,
1028 PCI_DMA_FROMDEVICE);
1029 pkt = rxb_addr(rxb);
1031 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1032 len += sizeof(u32); /* account for status word */
1033 trace_iwlwifi_dev_rx(priv, pkt, len);
1035 /* Reclaim a command buffer only if this packet is a response
1036 * to a (driver-originated) command.
1037 * If the packet (e.g. Rx frame) originated from uCode,
1038 * there is no command buffer to reclaim.
1039 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1040 * but apparently a few don't get set; catch them here. */
1041 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1042 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
1043 (pkt->hdr.cmd != REPLY_RX) &&
1044 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
1045 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
1046 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1047 (pkt->hdr.cmd != REPLY_TX);
1049 /* Based on type of command response or notification,
1050 * handle those that need handling via function in
1051 * rx_handlers table. See iwl_setup_rx_handlers() */
1052 if (priv->rx_handlers[pkt->hdr.cmd]) {
1053 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
1054 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1055 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1056 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1058 /* No handling needed */
1060 "r %d i %d No handler needed for %s, 0x%02x\n",
1061 r, i, get_cmd_string(pkt->hdr.cmd),
1066 * XXX: After here, we should always check rxb->page
1067 * against NULL before touching it or its virtual
1068 * memory (pkt). Because some rx_handler might have
1069 * already taken or freed the pages.
1073 /* Invoke any callbacks, transfer the buffer to caller,
1074 * and fire off the (possibly) blocking iwl_send_cmd()
1075 * as we reclaim the driver command queue */
1077 iwl_tx_cmd_complete(priv, rxb);
1079 IWL_WARN(priv, "Claim null rxb?\n");
1082 /* Reuse the page if possible. For notification packets and
1083 * SKBs that fail to Rx correctly, add them back into the
1084 * rx_free list for reuse later. */
1085 spin_lock_irqsave(&rxq->lock, flags);
1086 if (rxb->page != NULL) {
1087 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1088 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1089 PCI_DMA_FROMDEVICE);
1090 list_add_tail(&rxb->list, &rxq->rx_free);
1093 list_add_tail(&rxb->list, &rxq->rx_used);
1095 spin_unlock_irqrestore(&rxq->lock, flags);
1097 i = (i + 1) & RX_QUEUE_MASK;
1098 /* If there are a lot of unused frames,
1099 * restock the Rx queue so ucode wont assert. */
1104 iwlagn_rx_replenish_now(priv);
1110 /* Backtrack one entry */
1113 iwlagn_rx_replenish_now(priv);
1115 iwlagn_rx_queue_restock(priv);
1118 /* call this function to flush any scheduled tasklet */
1119 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1121 /* wait to make sure we flush pending tasklet*/
1122 synchronize_irq(priv->pci_dev->irq);
1123 tasklet_kill(&priv->irq_tasklet);
1126 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1128 u32 inta, handled = 0;
1130 unsigned long flags;
1132 #ifdef CONFIG_IWLWIFI_DEBUG
1136 spin_lock_irqsave(&priv->lock, flags);
1138 /* Ack/clear/reset pending uCode interrupts.
1139 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1140 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
1141 inta = iwl_read32(priv, CSR_INT);
1142 iwl_write32(priv, CSR_INT, inta);
1144 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1145 * Any new interrupts that happen after this, either while we're
1146 * in this tasklet, or later, will show up in next ISR/tasklet. */
1147 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1148 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1150 #ifdef CONFIG_IWLWIFI_DEBUG
1151 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1152 /* just for debug */
1153 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1154 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1155 inta, inta_mask, inta_fh);
1159 spin_unlock_irqrestore(&priv->lock, flags);
1161 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1162 * atomic, make sure that inta covers all the interrupts that
1163 * we've discovered, even if FH interrupt came in just after
1164 * reading CSR_INT. */
1165 if (inta_fh & CSR49_FH_INT_RX_MASK)
1166 inta |= CSR_INT_BIT_FH_RX;
1167 if (inta_fh & CSR49_FH_INT_TX_MASK)
1168 inta |= CSR_INT_BIT_FH_TX;
1170 /* Now service all interrupt bits discovered above. */
1171 if (inta & CSR_INT_BIT_HW_ERR) {
1172 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1174 /* Tell the device to stop sending interrupts */
1175 iwl_disable_interrupts(priv);
1177 priv->isr_stats.hw++;
1178 iwl_irq_handle_error(priv);
1180 handled |= CSR_INT_BIT_HW_ERR;
1185 #ifdef CONFIG_IWLWIFI_DEBUG
1186 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1187 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1188 if (inta & CSR_INT_BIT_SCD) {
1189 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1190 "the frame/frames.\n");
1191 priv->isr_stats.sch++;
1194 /* Alive notification via Rx interrupt will do the real work */
1195 if (inta & CSR_INT_BIT_ALIVE) {
1196 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1197 priv->isr_stats.alive++;
1201 /* Safely ignore these bits for debug checks below */
1202 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1204 /* HW RF KILL switch toggled */
1205 if (inta & CSR_INT_BIT_RF_KILL) {
1207 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1208 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1211 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1212 hw_rf_kill ? "disable radio" : "enable radio");
1214 priv->isr_stats.rfkill++;
1216 /* driver only loads ucode once setting the interface up.
1217 * the driver allows loading the ucode even if the radio
1218 * is killed. Hence update the killswitch state here. The
1219 * rfkill handler will care about restarting if needed.
1221 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1223 set_bit(STATUS_RF_KILL_HW, &priv->status);
1225 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1226 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1229 handled |= CSR_INT_BIT_RF_KILL;
1232 /* Chip got too hot and stopped itself */
1233 if (inta & CSR_INT_BIT_CT_KILL) {
1234 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1235 priv->isr_stats.ctkill++;
1236 handled |= CSR_INT_BIT_CT_KILL;
1239 /* Error detected by uCode */
1240 if (inta & CSR_INT_BIT_SW_ERR) {
1241 IWL_ERR(priv, "Microcode SW error detected. "
1242 " Restarting 0x%X.\n", inta);
1243 priv->isr_stats.sw++;
1244 priv->isr_stats.sw_err = inta;
1245 iwl_irq_handle_error(priv);
1246 handled |= CSR_INT_BIT_SW_ERR;
1250 * uCode wakes up after power-down sleep.
1251 * Tell device about any new tx or host commands enqueued,
1252 * and about any Rx buffers made available while asleep.
1254 if (inta & CSR_INT_BIT_WAKEUP) {
1255 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1256 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1257 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1258 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1259 priv->isr_stats.wakeup++;
1260 handled |= CSR_INT_BIT_WAKEUP;
1263 /* All uCode command responses, including Tx command responses,
1264 * Rx "responses" (frame-received notification), and other
1265 * notifications from uCode come through here*/
1266 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1267 iwl_rx_handle(priv);
1268 priv->isr_stats.rx++;
1269 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1272 /* This "Tx" DMA channel is used only for loading uCode */
1273 if (inta & CSR_INT_BIT_FH_TX) {
1274 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1275 priv->isr_stats.tx++;
1276 handled |= CSR_INT_BIT_FH_TX;
1277 /* Wake up uCode load routine, now that load is complete */
1278 priv->ucode_write_complete = 1;
1279 wake_up_interruptible(&priv->wait_command_queue);
1282 if (inta & ~handled) {
1283 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1284 priv->isr_stats.unhandled++;
1287 if (inta & ~(priv->inta_mask)) {
1288 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1289 inta & ~priv->inta_mask);
1290 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1293 /* Re-enable all interrupts */
1294 /* only Re-enable if diabled by irq */
1295 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1296 iwl_enable_interrupts(priv);
1298 #ifdef CONFIG_IWLWIFI_DEBUG
1299 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1300 inta = iwl_read32(priv, CSR_INT);
1301 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1302 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1303 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1304 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1309 /* tasklet for iwlagn interrupt */
1310 static void iwl_irq_tasklet(struct iwl_priv *priv)
1314 unsigned long flags;
1316 #ifdef CONFIG_IWLWIFI_DEBUG
1320 spin_lock_irqsave(&priv->lock, flags);
1322 /* Ack/clear/reset pending uCode interrupts.
1323 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1325 /* There is a hardware bug in the interrupt mask function that some
1326 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1327 * they are disabled in the CSR_INT_MASK register. Furthermore the
1328 * ICT interrupt handling mechanism has another bug that might cause
1329 * these unmasked interrupts fail to be detected. We workaround the
1330 * hardware bugs here by ACKing all the possible interrupts so that
1331 * interrupt coalescing can still be achieved.
1333 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1335 inta = priv->_agn.inta;
1337 #ifdef CONFIG_IWLWIFI_DEBUG
1338 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1339 /* just for debug */
1340 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1341 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1346 spin_unlock_irqrestore(&priv->lock, flags);
1348 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1349 priv->_agn.inta = 0;
1351 /* Now service all interrupt bits discovered above. */
1352 if (inta & CSR_INT_BIT_HW_ERR) {
1353 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1355 /* Tell the device to stop sending interrupts */
1356 iwl_disable_interrupts(priv);
1358 priv->isr_stats.hw++;
1359 iwl_irq_handle_error(priv);
1361 handled |= CSR_INT_BIT_HW_ERR;
1366 #ifdef CONFIG_IWLWIFI_DEBUG
1367 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1368 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1369 if (inta & CSR_INT_BIT_SCD) {
1370 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1371 "the frame/frames.\n");
1372 priv->isr_stats.sch++;
1375 /* Alive notification via Rx interrupt will do the real work */
1376 if (inta & CSR_INT_BIT_ALIVE) {
1377 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1378 priv->isr_stats.alive++;
1382 /* Safely ignore these bits for debug checks below */
1383 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1385 /* HW RF KILL switch toggled */
1386 if (inta & CSR_INT_BIT_RF_KILL) {
1388 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1389 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1392 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1393 hw_rf_kill ? "disable radio" : "enable radio");
1395 priv->isr_stats.rfkill++;
1397 /* driver only loads ucode once setting the interface up.
1398 * the driver allows loading the ucode even if the radio
1399 * is killed. Hence update the killswitch state here. The
1400 * rfkill handler will care about restarting if needed.
1402 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1404 set_bit(STATUS_RF_KILL_HW, &priv->status);
1406 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1407 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1410 handled |= CSR_INT_BIT_RF_KILL;
1413 /* Chip got too hot and stopped itself */
1414 if (inta & CSR_INT_BIT_CT_KILL) {
1415 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1416 priv->isr_stats.ctkill++;
1417 handled |= CSR_INT_BIT_CT_KILL;
1420 /* Error detected by uCode */
1421 if (inta & CSR_INT_BIT_SW_ERR) {
1422 IWL_ERR(priv, "Microcode SW error detected. "
1423 " Restarting 0x%X.\n", inta);
1424 priv->isr_stats.sw++;
1425 priv->isr_stats.sw_err = inta;
1426 iwl_irq_handle_error(priv);
1427 handled |= CSR_INT_BIT_SW_ERR;
1430 /* uCode wakes up after power-down sleep */
1431 if (inta & CSR_INT_BIT_WAKEUP) {
1432 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1433 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1434 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1435 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1437 priv->isr_stats.wakeup++;
1439 handled |= CSR_INT_BIT_WAKEUP;
1442 /* All uCode command responses, including Tx command responses,
1443 * Rx "responses" (frame-received notification), and other
1444 * notifications from uCode come through here*/
1445 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1446 CSR_INT_BIT_RX_PERIODIC)) {
1447 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1448 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1449 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1450 iwl_write32(priv, CSR_FH_INT_STATUS,
1451 CSR49_FH_INT_RX_MASK);
1453 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1454 handled |= CSR_INT_BIT_RX_PERIODIC;
1455 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1457 /* Sending RX interrupt require many steps to be done in the
1459 * 1- write interrupt to current index in ICT table.
1461 * 3- update RX shared data to indicate last write index.
1462 * 4- send interrupt.
1463 * This could lead to RX race, driver could receive RX interrupt
1464 * but the shared data changes does not reflect this;
1465 * periodic interrupt will detect any dangling Rx activity.
1468 /* Disable periodic interrupt; we use it as just a one-shot. */
1469 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1470 CSR_INT_PERIODIC_DIS);
1471 iwl_rx_handle(priv);
1474 * Enable periodic interrupt in 8 msec only if we received
1475 * real RX interrupt (instead of just periodic int), to catch
1476 * any dangling Rx interrupt. If it was just the periodic
1477 * interrupt, there was no dangling Rx activity, and no need
1478 * to extend the periodic interrupt; one-shot is enough.
1480 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1481 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1482 CSR_INT_PERIODIC_ENA);
1484 priv->isr_stats.rx++;
1487 /* This "Tx" DMA channel is used only for loading uCode */
1488 if (inta & CSR_INT_BIT_FH_TX) {
1489 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1490 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1491 priv->isr_stats.tx++;
1492 handled |= CSR_INT_BIT_FH_TX;
1493 /* Wake up uCode load routine, now that load is complete */
1494 priv->ucode_write_complete = 1;
1495 wake_up_interruptible(&priv->wait_command_queue);
1498 if (inta & ~handled) {
1499 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1500 priv->isr_stats.unhandled++;
1503 if (inta & ~(priv->inta_mask)) {
1504 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1505 inta & ~priv->inta_mask);
1508 /* Re-enable all interrupts */
1509 /* only Re-enable if diabled by irq */
1510 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1511 iwl_enable_interrupts(priv);
1514 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1515 #define ACK_CNT_RATIO (50)
1516 #define BA_TIMEOUT_CNT (5)
1517 #define BA_TIMEOUT_MAX (16)
1520 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1522 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1523 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1526 bool iwl_good_ack_health(struct iwl_priv *priv,
1527 struct iwl_rx_packet *pkt)
1530 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1531 int ba_timeout_delta;
1533 actual_ack_cnt_delta =
1534 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1535 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1536 expected_ack_cnt_delta =
1537 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1538 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1540 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1541 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1542 if ((priv->_agn.agg_tids_count > 0) &&
1543 (expected_ack_cnt_delta > 0) &&
1544 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1546 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1547 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1548 " expected_ack_cnt = %d\n",
1549 actual_ack_cnt_delta, expected_ack_cnt_delta);
1551 #ifdef CONFIG_IWLWIFI_DEBUGFS
1553 * This is ifdef'ed on DEBUGFS because otherwise the
1554 * statistics aren't available. If DEBUGFS is set but
1555 * DEBUG is not, these will just compile out.
1557 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1558 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1559 IWL_DEBUG_RADIO(priv,
1560 "ack_or_ba_timeout_collision delta = %d\n",
1561 priv->_agn.delta_statistics.tx.
1562 ack_or_ba_timeout_collision);
1564 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1566 if (!actual_ack_cnt_delta &&
1567 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1574 /*****************************************************************************
1578 *****************************************************************************/
1580 #ifdef CONFIG_IWLWIFI_DEBUG
1583 * The following adds a new attribute to the sysfs representation
1584 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1585 * used for controlling the debug level.
1587 * See the level definitions in iwl for details.
1589 * The debug_level being managed using sysfs below is a per device debug
1590 * level that is used instead of the global debug level if it (the per
1591 * device debug level) is set.
1593 static ssize_t show_debug_level(struct device *d,
1594 struct device_attribute *attr, char *buf)
1596 struct iwl_priv *priv = dev_get_drvdata(d);
1597 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1599 static ssize_t store_debug_level(struct device *d,
1600 struct device_attribute *attr,
1601 const char *buf, size_t count)
1603 struct iwl_priv *priv = dev_get_drvdata(d);
1607 ret = strict_strtoul(buf, 0, &val);
1609 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1611 priv->debug_level = val;
1612 if (iwl_alloc_traffic_mem(priv))
1614 "Not enough memory to generate traffic log\n");
1616 return strnlen(buf, count);
1619 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1620 show_debug_level, store_debug_level);
1623 #endif /* CONFIG_IWLWIFI_DEBUG */
1626 static ssize_t show_temperature(struct device *d,
1627 struct device_attribute *attr, char *buf)
1629 struct iwl_priv *priv = dev_get_drvdata(d);
1631 if (!iwl_is_alive(priv))
1634 return sprintf(buf, "%d\n", priv->temperature);
1637 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1639 static ssize_t show_tx_power(struct device *d,
1640 struct device_attribute *attr, char *buf)
1642 struct iwl_priv *priv = dev_get_drvdata(d);
1644 if (!iwl_is_ready_rf(priv))
1645 return sprintf(buf, "off\n");
1647 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1650 static ssize_t store_tx_power(struct device *d,
1651 struct device_attribute *attr,
1652 const char *buf, size_t count)
1654 struct iwl_priv *priv = dev_get_drvdata(d);
1658 ret = strict_strtoul(buf, 10, &val);
1660 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1662 ret = iwl_set_tx_power(priv, val, false);
1664 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1672 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1674 static struct attribute *iwl_sysfs_entries[] = {
1675 &dev_attr_temperature.attr,
1676 &dev_attr_tx_power.attr,
1677 #ifdef CONFIG_IWLWIFI_DEBUG
1678 &dev_attr_debug_level.attr,
1683 static struct attribute_group iwl_attribute_group = {
1684 .name = NULL, /* put in device directory */
1685 .attrs = iwl_sysfs_entries,
1688 /******************************************************************************
1690 * uCode download functions
1692 ******************************************************************************/
1694 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1696 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1697 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1698 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1699 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1700 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1701 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1704 static void iwl_nic_start(struct iwl_priv *priv)
1706 /* Remove all resets to allow NIC to operate */
1707 iwl_write32(priv, CSR_RESET, 0);
1710 struct iwlagn_ucode_capabilities {
1711 u32 max_probe_length;
1712 u32 standard_phy_calibration_size;
1715 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1716 static int iwl_mac_setup_register(struct iwl_priv *priv,
1717 struct iwlagn_ucode_capabilities *capa);
1719 #define UCODE_EXPERIMENTAL_INDEX 100
1720 #define UCODE_EXPERIMENTAL_TAG "exp"
1722 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1724 const char *name_pre = priv->cfg->fw_name_pre;
1728 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1729 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1730 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1731 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1733 priv->fw_index = priv->cfg->ucode_api_max;
1734 sprintf(tag, "%d", priv->fw_index);
1737 sprintf(tag, "%d", priv->fw_index);
1740 if (priv->fw_index < priv->cfg->ucode_api_min) {
1741 IWL_ERR(priv, "no suitable firmware found!\n");
1745 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1747 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1748 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1749 ? "EXPERIMENTAL " : "",
1750 priv->firmware_name);
1752 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1753 &priv->pci_dev->dev, GFP_KERNEL, priv,
1754 iwl_ucode_callback);
1757 struct iwlagn_firmware_pieces {
1758 const void *inst, *data, *init, *init_data, *boot;
1759 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1763 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1764 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1767 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1768 const struct firmware *ucode_raw,
1769 struct iwlagn_firmware_pieces *pieces)
1771 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1772 u32 api_ver, hdr_size;
1775 priv->ucode_ver = le32_to_cpu(ucode->ver);
1776 api_ver = IWL_UCODE_API(priv->ucode_ver);
1781 * 4965 doesn't revision the firmware file format
1782 * along with the API version, it always uses v1
1785 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1786 CSR_HW_REV_TYPE_4965) {
1788 if (ucode_raw->size < hdr_size) {
1789 IWL_ERR(priv, "File size too small!\n");
1792 pieces->build = le32_to_cpu(ucode->u.v2.build);
1793 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1794 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1795 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1796 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1797 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1798 src = ucode->u.v2.data;
1801 /* fall through for 4965 */
1806 if (ucode_raw->size < hdr_size) {
1807 IWL_ERR(priv, "File size too small!\n");
1811 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1812 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1813 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1814 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1815 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1816 src = ucode->u.v1.data;
1820 /* Verify size of file vs. image size info in file's header */
1821 if (ucode_raw->size != hdr_size + pieces->inst_size +
1822 pieces->data_size + pieces->init_size +
1823 pieces->init_data_size + pieces->boot_size) {
1826 "uCode file size %d does not match expected size\n",
1827 (int)ucode_raw->size);
1832 src += pieces->inst_size;
1834 src += pieces->data_size;
1836 src += pieces->init_size;
1837 pieces->init_data = src;
1838 src += pieces->init_data_size;
1840 src += pieces->boot_size;
1845 static int iwlagn_wanted_ucode_alternative = 1;
1847 static int iwlagn_load_firmware(struct iwl_priv *priv,
1848 const struct firmware *ucode_raw,
1849 struct iwlagn_firmware_pieces *pieces,
1850 struct iwlagn_ucode_capabilities *capa)
1852 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1853 struct iwl_ucode_tlv *tlv;
1854 size_t len = ucode_raw->size;
1856 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1859 enum iwl_ucode_tlv_type tlv_type;
1862 if (len < sizeof(*ucode)) {
1863 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1867 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1868 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1869 le32_to_cpu(ucode->magic));
1874 * Check which alternatives are present, and "downgrade"
1875 * when the chosen alternative is not present, warning
1876 * the user when that happens. Some files may not have
1877 * any alternatives, so don't warn in that case.
1879 alternatives = le64_to_cpu(ucode->alternatives);
1880 tmp = wanted_alternative;
1881 if (wanted_alternative > 63)
1882 wanted_alternative = 63;
1883 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1884 wanted_alternative--;
1885 if (wanted_alternative && wanted_alternative != tmp)
1887 "uCode alternative %d not available, choosing %d\n",
1888 tmp, wanted_alternative);
1890 priv->ucode_ver = le32_to_cpu(ucode->ver);
1891 pieces->build = le32_to_cpu(ucode->build);
1894 len -= sizeof(*ucode);
1896 while (len >= sizeof(*tlv)) {
1899 len -= sizeof(*tlv);
1902 tlv_len = le32_to_cpu(tlv->length);
1903 tlv_type = le16_to_cpu(tlv->type);
1904 tlv_alt = le16_to_cpu(tlv->alternative);
1905 tlv_data = tlv->data;
1907 if (len < tlv_len) {
1908 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1912 len -= ALIGN(tlv_len, 4);
1913 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1916 * Alternative 0 is always valid.
1918 * Skip alternative TLVs that are not selected.
1920 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1924 case IWL_UCODE_TLV_INST:
1925 pieces->inst = tlv_data;
1926 pieces->inst_size = tlv_len;
1928 case IWL_UCODE_TLV_DATA:
1929 pieces->data = tlv_data;
1930 pieces->data_size = tlv_len;
1932 case IWL_UCODE_TLV_INIT:
1933 pieces->init = tlv_data;
1934 pieces->init_size = tlv_len;
1936 case IWL_UCODE_TLV_INIT_DATA:
1937 pieces->init_data = tlv_data;
1938 pieces->init_data_size = tlv_len;
1940 case IWL_UCODE_TLV_BOOT:
1941 pieces->boot = tlv_data;
1942 pieces->boot_size = tlv_len;
1944 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1945 if (tlv_len != sizeof(u32))
1946 goto invalid_tlv_len;
1947 capa->max_probe_length =
1948 le32_to_cpup((__le32 *)tlv_data);
1950 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1951 if (tlv_len != sizeof(u32))
1952 goto invalid_tlv_len;
1953 pieces->init_evtlog_ptr =
1954 le32_to_cpup((__le32 *)tlv_data);
1956 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1957 if (tlv_len != sizeof(u32))
1958 goto invalid_tlv_len;
1959 pieces->init_evtlog_size =
1960 le32_to_cpup((__le32 *)tlv_data);
1962 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1963 if (tlv_len != sizeof(u32))
1964 goto invalid_tlv_len;
1965 pieces->init_errlog_ptr =
1966 le32_to_cpup((__le32 *)tlv_data);
1968 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1969 if (tlv_len != sizeof(u32))
1970 goto invalid_tlv_len;
1971 pieces->inst_evtlog_ptr =
1972 le32_to_cpup((__le32 *)tlv_data);
1974 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1975 if (tlv_len != sizeof(u32))
1976 goto invalid_tlv_len;
1977 pieces->inst_evtlog_size =
1978 le32_to_cpup((__le32 *)tlv_data);
1980 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1981 if (tlv_len != sizeof(u32))
1982 goto invalid_tlv_len;
1983 pieces->inst_errlog_ptr =
1984 le32_to_cpup((__le32 *)tlv_data);
1986 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1988 goto invalid_tlv_len;
1989 priv->enhance_sensitivity_table = true;
1991 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1992 if (tlv_len != sizeof(u32))
1993 goto invalid_tlv_len;
1994 capa->standard_phy_calibration_size =
1995 le32_to_cpup((__le32 *)tlv_data);
1998 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
2004 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2005 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
2012 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2013 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2019 * iwl_ucode_callback - callback when firmware was loaded
2021 * If loaded successfully, copies the firmware into buffers
2022 * for the card to fetch (via DMA).
2024 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
2026 struct iwl_priv *priv = context;
2027 struct iwl_ucode_header *ucode;
2029 struct iwlagn_firmware_pieces pieces;
2030 const unsigned int api_max = priv->cfg->ucode_api_max;
2031 const unsigned int api_min = priv->cfg->ucode_api_min;
2035 struct iwlagn_ucode_capabilities ucode_capa = {
2036 .max_probe_length = 200,
2037 .standard_phy_calibration_size =
2038 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
2041 memset(&pieces, 0, sizeof(pieces));
2044 if (priv->fw_index <= priv->cfg->ucode_api_max)
2046 "request for firmware file '%s' failed.\n",
2047 priv->firmware_name);
2051 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2052 priv->firmware_name, ucode_raw->size);
2054 /* Make sure that we got at least the API version number */
2055 if (ucode_raw->size < 4) {
2056 IWL_ERR(priv, "File size way too small!\n");
2060 /* Data from ucode file: header followed by uCode images */
2061 ucode = (struct iwl_ucode_header *)ucode_raw->data;
2064 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2066 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2072 api_ver = IWL_UCODE_API(priv->ucode_ver);
2073 build = pieces.build;
2076 * api_ver should match the api version forming part of the
2077 * firmware filename ... but we don't check for that and only rely
2078 * on the API version read from firmware header from here on forward
2080 if (api_ver < api_min || api_ver > api_max) {
2081 IWL_ERR(priv, "Driver unable to support your firmware API. "
2082 "Driver supports v%u, firmware is v%u.\n",
2087 if (api_ver != api_max)
2088 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
2089 "got v%u. New firmware can be obtained "
2090 "from http://www.intellinuxwireless.org.\n",
2094 sprintf(buildstr, " build %u%s", build,
2095 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2100 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2101 IWL_UCODE_MAJOR(priv->ucode_ver),
2102 IWL_UCODE_MINOR(priv->ucode_ver),
2103 IWL_UCODE_API(priv->ucode_ver),
2104 IWL_UCODE_SERIAL(priv->ucode_ver),
2107 snprintf(priv->hw->wiphy->fw_version,
2108 sizeof(priv->hw->wiphy->fw_version),
2110 IWL_UCODE_MAJOR(priv->ucode_ver),
2111 IWL_UCODE_MINOR(priv->ucode_ver),
2112 IWL_UCODE_API(priv->ucode_ver),
2113 IWL_UCODE_SERIAL(priv->ucode_ver),
2117 * For any of the failures below (before allocating pci memory)
2118 * we will try to load a version with a smaller API -- maybe the
2119 * user just got a corrupted version of the latest API.
2122 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2124 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2126 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2128 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2130 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2131 pieces.init_data_size);
2132 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2135 /* Verify that uCode images will fit in card's SRAM */
2136 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2137 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2142 if (pieces.data_size > priv->hw_params.max_data_size) {
2143 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2148 if (pieces.init_size > priv->hw_params.max_inst_size) {
2149 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2154 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2155 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2156 pieces.init_data_size);
2160 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2161 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2166 /* Allocate ucode buffers for card's bus-master loading ... */
2168 /* Runtime instructions and 2 copies of data:
2169 * 1) unmodified from disk
2170 * 2) backup cache for save/restore during power-downs */
2171 priv->ucode_code.len = pieces.inst_size;
2172 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2174 priv->ucode_data.len = pieces.data_size;
2175 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2177 priv->ucode_data_backup.len = pieces.data_size;
2178 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2180 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2181 !priv->ucode_data_backup.v_addr)
2184 /* Initialization instructions and data */
2185 if (pieces.init_size && pieces.init_data_size) {
2186 priv->ucode_init.len = pieces.init_size;
2187 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2189 priv->ucode_init_data.len = pieces.init_data_size;
2190 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2192 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2196 /* Bootstrap (instructions only, no data) */
2197 if (pieces.boot_size) {
2198 priv->ucode_boot.len = pieces.boot_size;
2199 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2201 if (!priv->ucode_boot.v_addr)
2205 /* Now that we can no longer fail, copy information */
2208 * The (size - 16) / 12 formula is based on the information recorded
2209 * for each event, which is of mode 1 (including timestamp) for all
2210 * new microcodes that include this information.
2212 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2213 if (pieces.init_evtlog_size)
2214 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2216 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2217 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2218 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2219 if (pieces.inst_evtlog_size)
2220 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2222 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2223 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2225 /* Copy images into buffers for card's bus-master reads ... */
2227 /* Runtime instructions (first block of data in file) */
2228 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2230 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2232 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2233 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2237 * NOTE: Copy into backup buffer will be done in iwl_up()
2239 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2241 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2242 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2244 /* Initialization instructions */
2245 if (pieces.init_size) {
2246 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2248 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2251 /* Initialization data */
2252 if (pieces.init_data_size) {
2253 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2254 pieces.init_data_size);
2255 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2256 pieces.init_data_size);
2259 /* Bootstrap instructions */
2260 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2262 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2265 * figure out the offset of chain noise reset and gain commands
2266 * base on the size of standard phy calibration commands table size
2268 if (ucode_capa.standard_phy_calibration_size >
2269 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2270 ucode_capa.standard_phy_calibration_size =
2271 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2273 priv->_agn.phy_calib_chain_noise_reset_cmd =
2274 ucode_capa.standard_phy_calibration_size;
2275 priv->_agn.phy_calib_chain_noise_gain_cmd =
2276 ucode_capa.standard_phy_calibration_size + 1;
2278 /**************************************************
2279 * This is still part of probe() in a sense...
2281 * 9. Setup and register with mac80211 and debugfs
2282 **************************************************/
2283 err = iwl_mac_setup_register(priv, &ucode_capa);
2287 err = iwl_dbgfs_register(priv, DRV_NAME);
2289 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2291 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2292 &iwl_attribute_group);
2294 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2298 /* We have our copies now, allow OS release its copies */
2299 release_firmware(ucode_raw);
2300 complete(&priv->_agn.firmware_loading_complete);
2304 /* try next, if any */
2305 if (iwl_request_firmware(priv, false))
2307 release_firmware(ucode_raw);
2311 IWL_ERR(priv, "failed to allocate pci memory\n");
2312 iwl_dealloc_ucode_pci(priv);
2314 complete(&priv->_agn.firmware_loading_complete);
2315 device_release_driver(&priv->pci_dev->dev);
2316 release_firmware(ucode_raw);
2319 static const char *desc_lookup_text[] = {
2324 "NMI_INTERRUPT_WDG",
2328 "HW_ERROR_TUNE_LOCK",
2329 "HW_ERROR_TEMPERATURE",
2330 "ILLEGAL_CHAN_FREQ",
2333 "NMI_INTERRUPT_HOST",
2334 "NMI_INTERRUPT_ACTION_PT",
2335 "NMI_INTERRUPT_UNKNOWN",
2336 "UCODE_VERSION_MISMATCH",
2337 "HW_ERROR_ABS_LOCK",
2338 "HW_ERROR_CAL_LOCK_FAIL",
2339 "NMI_INTERRUPT_INST_ACTION_PT",
2340 "NMI_INTERRUPT_DATA_ACTION_PT",
2342 "NMI_INTERRUPT_TRM",
2343 "NMI_INTERRUPT_BREAK_POINT"
2350 static struct { char *name; u8 num; } advanced_lookup[] = {
2351 { "NMI_INTERRUPT_WDG", 0x34 },
2352 { "SYSASSERT", 0x35 },
2353 { "UCODE_VERSION_MISMATCH", 0x37 },
2354 { "BAD_COMMAND", 0x38 },
2355 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2356 { "FATAL_ERROR", 0x3D },
2357 { "NMI_TRM_HW_ERR", 0x46 },
2358 { "NMI_INTERRUPT_TRM", 0x4C },
2359 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2360 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2361 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2362 { "NMI_INTERRUPT_HOST", 0x66 },
2363 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2364 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2365 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2366 { "ADVANCED_SYSASSERT", 0 },
2369 static const char *desc_lookup(u32 num)
2372 int max = ARRAY_SIZE(desc_lookup_text);
2375 return desc_lookup_text[num];
2377 max = ARRAY_SIZE(advanced_lookup) - 1;
2378 for (i = 0; i < max; i++) {
2379 if (advanced_lookup[i].num == num)
2382 return advanced_lookup[i].name;
2385 #define ERROR_START_OFFSET (1 * sizeof(u32))
2386 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
2388 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2391 u32 desc, time, count, base, data1;
2392 u32 blink1, blink2, ilink1, ilink2;
2395 if (priv->ucode_type == UCODE_INIT) {
2396 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2398 base = priv->_agn.init_errlog_ptr;
2400 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2402 base = priv->_agn.inst_errlog_ptr;
2405 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2407 "Not valid error log pointer 0x%08X for %s uCode\n",
2408 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2412 count = iwl_read_targ_mem(priv, base);
2414 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2415 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2416 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2417 priv->status, count);
2420 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2421 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2422 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2423 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2424 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2425 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2426 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2427 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2428 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2429 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2430 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2432 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2433 blink1, blink2, ilink1, ilink2);
2435 IWL_ERR(priv, "Desc Time "
2436 "data1 data2 line\n");
2437 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2438 desc_lookup(desc), desc, time, data1, data2, line);
2439 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2440 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2441 pc, blink1, blink2, ilink1, ilink2, hcmd);
2444 #define EVENT_START_OFFSET (4 * sizeof(u32))
2447 * iwl_print_event_log - Dump error event log to syslog
2450 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2451 u32 num_events, u32 mode,
2452 int pos, char **buf, size_t bufsz)
2455 u32 base; /* SRAM byte address of event log header */
2456 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2457 u32 ptr; /* SRAM byte address of log data */
2458 u32 ev, time, data; /* event log data */
2459 unsigned long reg_flags;
2461 if (num_events == 0)
2464 if (priv->ucode_type == UCODE_INIT) {
2465 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2467 base = priv->_agn.init_evtlog_ptr;
2469 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2471 base = priv->_agn.inst_evtlog_ptr;
2475 event_size = 2 * sizeof(u32);
2477 event_size = 3 * sizeof(u32);
2479 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2481 /* Make sure device is powered up for SRAM reads */
2482 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2483 iwl_grab_nic_access(priv);
2485 /* Set starting address; reads will auto-increment */
2486 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2489 /* "time" is actually "data" for mode 0 (no timestamp).
2490 * place event id # at far right for easier visual parsing. */
2491 for (i = 0; i < num_events; i++) {
2492 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2493 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2497 pos += scnprintf(*buf + pos, bufsz - pos,
2498 "EVT_LOG:0x%08x:%04u\n",
2501 trace_iwlwifi_dev_ucode_event(priv, 0,
2503 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2507 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2509 pos += scnprintf(*buf + pos, bufsz - pos,
2510 "EVT_LOGT:%010u:0x%08x:%04u\n",
2513 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2515 trace_iwlwifi_dev_ucode_event(priv, time,
2521 /* Allow device to power down */
2522 iwl_release_nic_access(priv);
2523 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2528 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2530 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2531 u32 num_wraps, u32 next_entry,
2533 int pos, char **buf, size_t bufsz)
2536 * display the newest DEFAULT_LOG_ENTRIES entries
2537 * i.e the entries just before the next ont that uCode would fill.
2540 if (next_entry < size) {
2541 pos = iwl_print_event_log(priv,
2542 capacity - (size - next_entry),
2543 size - next_entry, mode,
2545 pos = iwl_print_event_log(priv, 0,
2549 pos = iwl_print_event_log(priv, next_entry - size,
2550 size, mode, pos, buf, bufsz);
2552 if (next_entry < size) {
2553 pos = iwl_print_event_log(priv, 0, next_entry,
2554 mode, pos, buf, bufsz);
2556 pos = iwl_print_event_log(priv, next_entry - size,
2557 size, mode, pos, buf, bufsz);
2563 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2565 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2566 char **buf, bool display)
2568 u32 base; /* SRAM byte address of event log header */
2569 u32 capacity; /* event log capacity in # entries */
2570 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2571 u32 num_wraps; /* # times uCode wrapped to top of log */
2572 u32 next_entry; /* index of next entry to be written by uCode */
2573 u32 size; /* # entries that we'll print */
2578 if (priv->ucode_type == UCODE_INIT) {
2579 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2580 logsize = priv->_agn.init_evtlog_size;
2582 base = priv->_agn.init_evtlog_ptr;
2584 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2585 logsize = priv->_agn.inst_evtlog_size;
2587 base = priv->_agn.inst_evtlog_ptr;
2590 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2592 "Invalid event log pointer 0x%08X for %s uCode\n",
2593 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2597 /* event log header */
2598 capacity = iwl_read_targ_mem(priv, base);
2599 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2600 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2601 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2603 if (capacity > logsize) {
2604 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2609 if (next_entry > logsize) {
2610 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2611 next_entry, logsize);
2612 next_entry = logsize;
2615 size = num_wraps ? capacity : next_entry;
2617 /* bail out if nothing in log */
2619 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2623 /* enable/disable bt channel announcement */
2624 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2626 #ifdef CONFIG_IWLWIFI_DEBUG
2627 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2628 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2629 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2631 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2632 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2634 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2637 #ifdef CONFIG_IWLWIFI_DEBUG
2640 bufsz = capacity * 48;
2643 *buf = kmalloc(bufsz, GFP_KERNEL);
2647 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2649 * if uCode has wrapped back to top of log,
2650 * start at the oldest entry,
2651 * i.e the next one that uCode would fill.
2654 pos = iwl_print_event_log(priv, next_entry,
2655 capacity - next_entry, mode,
2657 /* (then/else) start at top of log */
2658 pos = iwl_print_event_log(priv, 0,
2659 next_entry, mode, pos, buf, bufsz);
2661 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2662 next_entry, size, mode,
2665 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2666 next_entry, size, mode,
2672 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2674 struct iwl_ct_kill_config cmd;
2675 struct iwl_ct_kill_throttling_config adv_cmd;
2676 unsigned long flags;
2679 spin_lock_irqsave(&priv->lock, flags);
2680 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2681 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2682 spin_unlock_irqrestore(&priv->lock, flags);
2683 priv->thermal_throttle.ct_kill_toggle = false;
2685 if (priv->cfg->support_ct_kill_exit) {
2686 adv_cmd.critical_temperature_enter =
2687 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2688 adv_cmd.critical_temperature_exit =
2689 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2691 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2692 sizeof(adv_cmd), &adv_cmd);
2694 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2696 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2698 "critical temperature enter is %d,"
2700 priv->hw_params.ct_kill_threshold,
2701 priv->hw_params.ct_kill_exit_threshold);
2703 cmd.critical_temperature_R =
2704 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2706 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2709 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2711 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2713 "critical temperature is %d\n",
2714 priv->hw_params.ct_kill_threshold);
2719 * iwl_alive_start - called after REPLY_ALIVE notification received
2720 * from protocol/runtime uCode (initialization uCode's
2721 * Alive gets handled by iwl_init_alive_start()).
2723 static void iwl_alive_start(struct iwl_priv *priv)
2726 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2728 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2730 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2731 /* We had an error bringing up the hardware, so take it
2732 * all the way back down so we can try again */
2733 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2737 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2738 * This is a paranoid check, because we would not have gotten the
2739 * "runtime" alive if code weren't properly loaded. */
2740 if (iwl_verify_ucode(priv)) {
2741 /* Runtime instruction load was bad;
2742 * take it all the way back down so we can try again */
2743 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2747 ret = priv->cfg->ops->lib->alive_notify(priv);
2750 "Could not complete ALIVE transition [ntf]: %d\n", ret);
2754 /* After the ALIVE response, we can send host commands to the uCode */
2755 set_bit(STATUS_ALIVE, &priv->status);
2757 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2758 /* Enable timer to monitor the driver queues */
2759 mod_timer(&priv->monitor_recover,
2761 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2764 if (iwl_is_rfkill(priv))
2767 ieee80211_wake_queues(priv->hw);
2769 priv->active_rate = IWL_RATES_MASK;
2771 /* Configure Tx antenna selection based on H/W config */
2772 if (priv->cfg->ops->hcmd->set_tx_ant)
2773 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2775 if (iwl_is_associated_ctx(ctx)) {
2776 struct iwl_rxon_cmd *active_rxon =
2777 (struct iwl_rxon_cmd *)&ctx->active;
2778 /* apply any changes in staging */
2779 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2780 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2782 /* Initialize our rx_config data */
2783 iwl_connection_init_rx_config(priv, NULL);
2785 if (priv->cfg->ops->hcmd->set_rxon_chain)
2786 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2789 if (!priv->cfg->advanced_bt_coexist) {
2790 /* Configure Bluetooth device coexistence support */
2791 priv->cfg->ops->hcmd->send_bt_config(priv);
2794 iwl_reset_run_time_calib(priv);
2796 /* Configure the adapter for unassociated operation */
2797 iwlcore_commit_rxon(priv, ctx);
2799 /* At this point, the NIC is initialized and operational */
2800 iwl_rf_kill_ct_config(priv);
2802 iwl_leds_init(priv);
2804 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2805 set_bit(STATUS_READY, &priv->status);
2806 wake_up_interruptible(&priv->wait_command_queue);
2808 iwl_power_update_mode(priv, true);
2809 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2815 queue_work(priv->workqueue, &priv->restart);
2818 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2820 static void __iwl_down(struct iwl_priv *priv)
2822 unsigned long flags;
2823 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2825 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2828 set_bit(STATUS_EXIT_PENDING, &priv->status);
2830 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2831 * to prevent rearm timer */
2832 if (priv->cfg->ops->lib->recover_from_tx_stall)
2833 del_timer_sync(&priv->monitor_recover);
2835 iwl_clear_ucode_stations(priv, NULL);
2836 iwl_dealloc_bcast_stations(priv);
2837 iwl_clear_driver_stations(priv);
2839 /* reset BT coex data */
2840 priv->bt_status = 0;
2841 priv->bt_traffic_load = priv->cfg->bt_init_traffic_load;
2842 priv->bt_sco_active = false;
2843 priv->bt_full_concurrent = false;
2844 priv->bt_ci_compliance = 0;
2846 /* Unblock any waiting calls */
2847 wake_up_interruptible_all(&priv->wait_command_queue);
2849 /* Wipe out the EXIT_PENDING status bit if we are not actually
2850 * exiting the module */
2852 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2854 /* stop and reset the on-board processor */
2855 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2857 /* tell the device to stop sending interrupts */
2858 spin_lock_irqsave(&priv->lock, flags);
2859 iwl_disable_interrupts(priv);
2860 spin_unlock_irqrestore(&priv->lock, flags);
2861 iwl_synchronize_irq(priv);
2863 if (priv->mac80211_registered)
2864 ieee80211_stop_queues(priv->hw);
2866 /* If we have not previously called iwl_init() then
2867 * clear all bits but the RF Kill bit and return */
2868 if (!iwl_is_init(priv)) {
2869 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2871 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2872 STATUS_GEO_CONFIGURED |
2873 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2874 STATUS_EXIT_PENDING;
2878 /* ...otherwise clear out all the status bits but the RF Kill
2879 * bit and continue taking the NIC down. */
2880 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2882 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2883 STATUS_GEO_CONFIGURED |
2884 test_bit(STATUS_FW_ERROR, &priv->status) <<
2886 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2887 STATUS_EXIT_PENDING;
2889 /* device going down, Stop using ICT table */
2890 iwl_disable_ict(priv);
2892 iwlagn_txq_ctx_stop(priv);
2893 iwlagn_rxq_stop(priv);
2895 /* Power-down device's busmaster DMA clocks */
2896 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2899 /* Make sure (redundant) we've released our request to stay awake */
2900 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2902 /* Stop the device, and put it in low power state */
2903 priv->cfg->ops->lib->apm_ops.stop(priv);
2906 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2908 if (priv->ibss_beacon)
2909 dev_kfree_skb(priv->ibss_beacon);
2910 priv->ibss_beacon = NULL;
2912 /* clear out any free frames */
2913 iwl_clear_free_frames(priv);
2916 static void iwl_down(struct iwl_priv *priv)
2918 mutex_lock(&priv->mutex);
2920 mutex_unlock(&priv->mutex);
2922 iwl_cancel_deferred_work(priv);
2925 #define HW_READY_TIMEOUT (50)
2927 static int iwl_set_hw_ready(struct iwl_priv *priv)
2931 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2932 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2934 /* See if we got it */
2935 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2936 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2937 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2939 if (ret != -ETIMEDOUT)
2940 priv->hw_ready = true;
2942 priv->hw_ready = false;
2944 IWL_DEBUG_INFO(priv, "hardware %s\n",
2945 (priv->hw_ready == 1) ? "ready" : "not ready");
2949 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2953 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2955 ret = iwl_set_hw_ready(priv);
2959 /* If HW is not ready, prepare the conditions to check again */
2960 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2961 CSR_HW_IF_CONFIG_REG_PREPARE);
2963 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2964 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2965 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2967 /* HW should be ready by now, check again. */
2968 if (ret != -ETIMEDOUT)
2969 iwl_set_hw_ready(priv);
2974 #define MAX_HW_RESTARTS 5
2976 static int __iwl_up(struct iwl_priv *priv)
2978 struct iwl_rxon_context *ctx;
2982 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2983 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2987 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2988 IWL_ERR(priv, "ucode not available for device bringup\n");
2992 for_each_context(priv, ctx) {
2993 ret = iwl_alloc_bcast_station(priv, ctx, true);
2995 iwl_dealloc_bcast_stations(priv);
3000 iwl_prepare_card_hw(priv);
3002 if (!priv->hw_ready) {
3003 IWL_WARN(priv, "Exit HW not ready\n");
3007 /* If platform's RF_KILL switch is NOT set to KILL */
3008 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3009 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3011 set_bit(STATUS_RF_KILL_HW, &priv->status);
3013 if (iwl_is_rfkill(priv)) {
3014 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3016 iwl_enable_interrupts(priv);
3017 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
3021 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3023 /* must be initialised before iwl_hw_nic_init */
3024 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3025 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3027 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
3029 ret = iwlagn_hw_nic_init(priv);
3031 IWL_ERR(priv, "Unable to init nic\n");
3035 /* make sure rfkill handshake bits are cleared */
3036 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3037 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3038 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3040 /* clear (again), then enable host interrupts */
3041 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3042 iwl_enable_interrupts(priv);
3044 /* really make sure rfkill handshake bits are cleared */
3045 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3046 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3048 /* Copy original ucode data image from disk into backup cache.
3049 * This will be used to initialize the on-board processor's
3050 * data SRAM for a clean start when the runtime program first loads. */
3051 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3052 priv->ucode_data.len);
3054 for (i = 0; i < MAX_HW_RESTARTS; i++) {
3056 /* load bootstrap state machine,
3057 * load bootstrap program into processor's memory,
3058 * prepare to load the "initialize" uCode */
3059 ret = priv->cfg->ops->lib->load_ucode(priv);
3062 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3067 /* start card; "initialize" will load runtime ucode */
3068 iwl_nic_start(priv);
3070 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3075 set_bit(STATUS_EXIT_PENDING, &priv->status);
3077 clear_bit(STATUS_EXIT_PENDING, &priv->status);
3079 /* tried to restart and config the device for as long as our
3080 * patience could withstand */
3081 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3086 /*****************************************************************************
3088 * Workqueue callbacks
3090 *****************************************************************************/
3092 static void iwl_bg_init_alive_start(struct work_struct *data)
3094 struct iwl_priv *priv =
3095 container_of(data, struct iwl_priv, init_alive_start.work);
3097 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3100 mutex_lock(&priv->mutex);
3101 priv->cfg->ops->lib->init_alive_start(priv);
3102 mutex_unlock(&priv->mutex);
3105 static void iwl_bg_alive_start(struct work_struct *data)
3107 struct iwl_priv *priv =
3108 container_of(data, struct iwl_priv, alive_start.work);
3110 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3113 /* enable dram interrupt */
3114 iwl_reset_ict(priv);
3116 mutex_lock(&priv->mutex);
3117 iwl_alive_start(priv);
3118 mutex_unlock(&priv->mutex);
3121 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3123 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3124 run_time_calib_work);
3126 mutex_lock(&priv->mutex);
3128 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3129 test_bit(STATUS_SCANNING, &priv->status)) {
3130 mutex_unlock(&priv->mutex);
3134 if (priv->start_calib) {
3135 if (priv->cfg->bt_statistics) {
3136 iwl_chain_noise_calibration(priv,
3137 (void *)&priv->_agn.statistics_bt);
3138 iwl_sensitivity_calibration(priv,
3139 (void *)&priv->_agn.statistics_bt);
3141 iwl_chain_noise_calibration(priv,
3142 (void *)&priv->_agn.statistics);
3143 iwl_sensitivity_calibration(priv,
3144 (void *)&priv->_agn.statistics);
3148 mutex_unlock(&priv->mutex);
3151 static void iwl_bg_restart(struct work_struct *data)
3153 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3155 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3158 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3159 struct iwl_rxon_context *ctx;
3160 bool bt_sco, bt_full_concurrent;
3161 u8 bt_ci_compliance;
3165 mutex_lock(&priv->mutex);
3166 for_each_context(priv, ctx)
3171 * __iwl_down() will clear the BT status variables,
3172 * which is correct, but when we restart we really
3173 * want to keep them so restore them afterwards.
3175 * The restart process will later pick them up and
3176 * re-configure the hw when we reconfigure the BT
3179 bt_sco = priv->bt_sco_active;
3180 bt_full_concurrent = priv->bt_full_concurrent;
3181 bt_ci_compliance = priv->bt_ci_compliance;
3182 bt_load = priv->bt_traffic_load;
3183 bt_status = priv->bt_status;
3187 priv->bt_sco_active = bt_sco;
3188 priv->bt_full_concurrent = bt_full_concurrent;
3189 priv->bt_ci_compliance = bt_ci_compliance;
3190 priv->bt_traffic_load = bt_load;
3191 priv->bt_status = bt_status;
3193 mutex_unlock(&priv->mutex);
3194 iwl_cancel_deferred_work(priv);
3195 ieee80211_restart_hw(priv->hw);
3199 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3202 mutex_lock(&priv->mutex);
3204 mutex_unlock(&priv->mutex);
3208 static void iwl_bg_rx_replenish(struct work_struct *data)
3210 struct iwl_priv *priv =
3211 container_of(data, struct iwl_priv, rx_replenish);
3213 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3216 mutex_lock(&priv->mutex);
3217 iwlagn_rx_replenish(priv);
3218 mutex_unlock(&priv->mutex);
3221 #define IWL_DELAY_NEXT_SCAN (HZ*2)
3223 void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
3225 struct iwl_rxon_context *ctx;
3226 struct ieee80211_conf *conf = NULL;
3229 if (!vif || !priv->is_open)
3232 ctx = iwl_rxon_ctx_from_vif(vif);
3234 if (vif->type == NL80211_IFTYPE_AP) {
3235 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
3239 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3242 iwl_scan_cancel_timeout(priv, 200);
3244 conf = ieee80211_get_hw_conf(priv->hw);
3246 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3247 iwlcore_commit_rxon(priv, ctx);
3249 ret = iwl_send_rxon_timing(priv, vif);
3251 IWL_WARN(priv, "RXON timing - "
3252 "Attempting to continue.\n");
3254 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3256 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3258 if (priv->cfg->ops->hcmd->set_rxon_chain)
3259 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3261 ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
3263 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
3264 vif->bss_conf.aid, vif->bss_conf.beacon_int);
3266 if (vif->bss_conf.use_short_preamble)
3267 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3269 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3271 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3272 if (vif->bss_conf.use_short_slot)
3273 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3275 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3278 iwlcore_commit_rxon(priv, ctx);
3280 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
3281 vif->bss_conf.aid, ctx->active.bssid_addr);
3283 switch (vif->type) {
3284 case NL80211_IFTYPE_STATION:
3286 case NL80211_IFTYPE_ADHOC:
3287 iwl_send_beacon_cmd(priv);
3290 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3291 __func__, vif->type);
3295 /* the chain noise calibration will enabled PM upon completion
3296 * If chain noise has already been run, then we need to enable
3297 * power management here */
3298 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
3299 iwl_power_update_mode(priv, false);
3301 /* Enable Rx differential gain and sensitivity calibrations */
3302 iwl_chain_noise_reset(priv);
3303 priv->start_calib = 1;
3307 /*****************************************************************************
3309 * mac80211 entry point functions
3311 *****************************************************************************/
3313 #define UCODE_READY_TIMEOUT (4 * HZ)
3316 * Not a mac80211 entry point function, but it fits in with all the
3317 * other mac80211 functions grouped here.
3319 static int iwl_mac_setup_register(struct iwl_priv *priv,
3320 struct iwlagn_ucode_capabilities *capa)
3323 struct ieee80211_hw *hw = priv->hw;
3324 hw->rate_control_algorithm = "iwl-agn-rs";
3326 /* Tell mac80211 our characteristics */
3327 hw->flags = IEEE80211_HW_SIGNAL_DBM |
3328 IEEE80211_HW_AMPDU_AGGREGATION |
3329 IEEE80211_HW_SPECTRUM_MGMT;
3331 if (!priv->cfg->broken_powersave)
3332 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3333 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3335 if (priv->cfg->sku & IWL_SKU_N)
3336 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3337 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3339 hw->sta_data_size = sizeof(struct iwl_station_priv);
3340 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3342 hw->wiphy->interface_modes =
3343 BIT(NL80211_IFTYPE_STATION) |
3344 BIT(NL80211_IFTYPE_ADHOC);
3346 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3347 WIPHY_FLAG_DISABLE_BEACON_HINTS;
3350 * For now, disable PS by default because it affects
3351 * RX performance significantly.
3353 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3355 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3356 /* we create the 802.11 header and a zero-length SSID element */
3357 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3359 /* Default value; 4 EDCA QOS priorities */
3362 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3364 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3365 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3366 &priv->bands[IEEE80211_BAND_2GHZ];
3367 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3368 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3369 &priv->bands[IEEE80211_BAND_5GHZ];
3371 ret = ieee80211_register_hw(priv->hw);
3373 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3376 priv->mac80211_registered = 1;
3382 static int iwl_mac_start(struct ieee80211_hw *hw)
3384 struct iwl_priv *priv = hw->priv;
3387 IWL_DEBUG_MAC80211(priv, "enter\n");
3389 /* we should be verifying the device is ready to be opened */
3390 mutex_lock(&priv->mutex);
3391 ret = __iwl_up(priv);
3392 mutex_unlock(&priv->mutex);
3397 if (iwl_is_rfkill(priv))
3400 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3402 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3403 * mac80211 will not be run successfully. */
3404 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3405 test_bit(STATUS_READY, &priv->status),
3406 UCODE_READY_TIMEOUT);
3408 if (!test_bit(STATUS_READY, &priv->status)) {
3409 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3410 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3415 iwl_led_start(priv);
3419 IWL_DEBUG_MAC80211(priv, "leave\n");
3423 static void iwl_mac_stop(struct ieee80211_hw *hw)
3425 struct iwl_priv *priv = hw->priv;
3427 IWL_DEBUG_MAC80211(priv, "enter\n");
3434 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
3435 /* stop mac, cancel any scan request and clear
3436 * RXON_FILTER_ASSOC_MSK BIT
3438 mutex_lock(&priv->mutex);
3439 iwl_scan_cancel_timeout(priv, 100);
3440 mutex_unlock(&priv->mutex);
3445 flush_workqueue(priv->workqueue);
3447 /* enable interrupts again in order to receive rfkill changes */
3448 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3449 iwl_enable_interrupts(priv);
3451 IWL_DEBUG_MAC80211(priv, "leave\n");
3454 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3456 struct iwl_priv *priv = hw->priv;
3458 IWL_DEBUG_MACDUMP(priv, "enter\n");
3460 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3461 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3463 if (iwlagn_tx_skb(priv, skb))
3464 dev_kfree_skb_any(skb);
3466 IWL_DEBUG_MACDUMP(priv, "leave\n");
3467 return NETDEV_TX_OK;
3470 void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
3472 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
3475 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3478 /* The following should be done only at AP bring up */
3479 if (!iwl_is_associated_ctx(ctx)) {
3481 /* RXON - unassoc (to set timing command) */
3482 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3483 iwlcore_commit_rxon(priv, ctx);
3486 ret = iwl_send_rxon_timing(priv, vif);
3488 IWL_WARN(priv, "RXON timing failed - "
3489 "Attempting to continue.\n");
3491 /* AP has all antennas */
3492 priv->chain_noise_data.active_chains =
3493 priv->hw_params.valid_rx_ant;
3494 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3495 if (priv->cfg->ops->hcmd->set_rxon_chain)
3496 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3498 ctx->staging.assoc_id = 0;
3500 if (vif->bss_conf.use_short_preamble)
3501 ctx->staging.flags |=
3502 RXON_FLG_SHORT_PREAMBLE_MSK;
3504 ctx->staging.flags &=
3505 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3507 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3508 if (vif->bss_conf.use_short_slot)
3509 ctx->staging.flags |=
3510 RXON_FLG_SHORT_SLOT_MSK;
3512 ctx->staging.flags &=
3513 ~RXON_FLG_SHORT_SLOT_MSK;
3515 /* restore RXON assoc */
3516 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3517 iwlcore_commit_rxon(priv, ctx);
3519 iwl_send_beacon_cmd(priv);
3521 /* FIXME - we need to add code here to detect a totally new
3522 * configuration, reset the AP, unassoc, rxon timing, assoc,
3523 * clear sta table, add BCAST sta... */
3526 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
3527 struct ieee80211_vif *vif,
3528 struct ieee80211_key_conf *keyconf,
3529 struct ieee80211_sta *sta,
3530 u32 iv32, u16 *phase1key)
3533 struct iwl_priv *priv = hw->priv;
3534 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3536 IWL_DEBUG_MAC80211(priv, "enter\n");
3538 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3541 IWL_DEBUG_MAC80211(priv, "leave\n");
3544 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3545 struct ieee80211_vif *vif,
3546 struct ieee80211_sta *sta,
3547 struct ieee80211_key_conf *key)
3549 struct iwl_priv *priv = hw->priv;
3550 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3553 bool is_default_wep_key = false;
3555 IWL_DEBUG_MAC80211(priv, "enter\n");
3557 if (priv->cfg->mod_params->sw_crypto) {
3558 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3562 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3563 if (sta_id == IWL_INVALID_STATION)
3566 mutex_lock(&priv->mutex);
3567 iwl_scan_cancel_timeout(priv, 100);
3570 * If we are getting WEP group key and we didn't receive any key mapping
3571 * so far, we are in legacy wep mode (group key only), otherwise we are
3573 * In legacy wep mode, we use another host command to the uCode.
3575 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3576 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3579 is_default_wep_key = !priv->key_mapping_key;
3581 is_default_wep_key =
3582 (key->hw_key_idx == HW_KEY_DEFAULT);
3587 if (is_default_wep_key)
3588 ret = iwl_set_default_wep_key(priv, key);
3590 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3593 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3596 if (is_default_wep_key)
3597 ret = iwl_remove_default_wep_key(priv, key);
3599 ret = iwl_remove_dynamic_key(priv, key, sta_id);
3601 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3607 mutex_unlock(&priv->mutex);
3608 IWL_DEBUG_MAC80211(priv, "leave\n");
3613 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3614 struct ieee80211_vif *vif,
3615 enum ieee80211_ampdu_mlme_action action,
3616 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3618 struct iwl_priv *priv = hw->priv;
3621 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3624 if (!(priv->cfg->sku & IWL_SKU_N))
3627 mutex_lock(&priv->mutex);
3630 case IEEE80211_AMPDU_RX_START:
3631 IWL_DEBUG_HT(priv, "start Rx\n");
3632 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3634 case IEEE80211_AMPDU_RX_STOP:
3635 IWL_DEBUG_HT(priv, "stop Rx\n");
3636 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3637 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3640 case IEEE80211_AMPDU_TX_START:
3641 IWL_DEBUG_HT(priv, "start Tx\n");
3642 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3644 priv->_agn.agg_tids_count++;
3645 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3646 priv->_agn.agg_tids_count);
3649 case IEEE80211_AMPDU_TX_STOP:
3650 IWL_DEBUG_HT(priv, "stop Tx\n");
3651 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3652 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3653 priv->_agn.agg_tids_count--;
3654 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3655 priv->_agn.agg_tids_count);
3657 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3659 if (priv->cfg->use_rts_for_aggregation) {
3660 struct iwl_station_priv *sta_priv =
3661 (void *) sta->drv_priv;
3663 * switch off RTS/CTS if it was previously enabled
3666 sta_priv->lq_sta.lq.general_params.flags &=
3667 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3668 iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3672 case IEEE80211_AMPDU_TX_OPERATIONAL:
3673 if (priv->cfg->use_rts_for_aggregation) {
3674 struct iwl_station_priv *sta_priv =
3675 (void *) sta->drv_priv;
3678 * switch to RTS/CTS if it is the prefer protection
3679 * method for HT traffic
3682 sta_priv->lq_sta.lq.general_params.flags |=
3683 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3684 iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3690 mutex_unlock(&priv->mutex);
3695 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3696 struct ieee80211_vif *vif,
3697 enum sta_notify_cmd cmd,
3698 struct ieee80211_sta *sta)
3700 struct iwl_priv *priv = hw->priv;
3701 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3705 case STA_NOTIFY_SLEEP:
3706 WARN_ON(!sta_priv->client);
3707 sta_priv->asleep = true;
3708 if (atomic_read(&sta_priv->pending_frames) > 0)
3709 ieee80211_sta_block_awake(hw, sta, true);
3711 case STA_NOTIFY_AWAKE:
3712 WARN_ON(!sta_priv->client);
3713 if (!sta_priv->asleep)
3715 sta_priv->asleep = false;
3716 sta_id = iwl_sta_id(sta);
3717 if (sta_id != IWL_INVALID_STATION)
3718 iwl_sta_modify_ps_wake(priv, sta_id);
3725 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3726 struct ieee80211_vif *vif,
3727 struct ieee80211_sta *sta)
3729 struct iwl_priv *priv = hw->priv;
3730 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3731 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3732 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3736 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3738 mutex_lock(&priv->mutex);
3739 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3741 sta_priv->common.sta_id = IWL_INVALID_STATION;
3743 atomic_set(&sta_priv->pending_frames, 0);
3744 if (vif->type == NL80211_IFTYPE_AP)
3745 sta_priv->client = true;
3747 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3748 is_ap, &sta->ht_cap, &sta_id);
3750 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3752 /* Should we return success if return code is EEXIST ? */
3753 mutex_unlock(&priv->mutex);
3757 sta_priv->common.sta_id = sta_id;
3759 /* Initialize rate scaling */
3760 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3762 iwl_rs_rate_init(priv, sta, sta_id);
3763 mutex_unlock(&priv->mutex);
3768 static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3769 struct ieee80211_channel_switch *ch_switch)
3771 struct iwl_priv *priv = hw->priv;
3772 const struct iwl_channel_info *ch_info;
3773 struct ieee80211_conf *conf = &hw->conf;
3774 struct ieee80211_channel *channel = ch_switch->channel;
3775 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3778 * When we add support for multiple interfaces, we need to
3779 * revisit this. The channel switch command in the device
3780 * only affects the BSS context, but what does that really
3781 * mean? And what if we get a CSA on the second interface?
3782 * This needs a lot of work.
3784 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3786 unsigned long flags = 0;
3788 IWL_DEBUG_MAC80211(priv, "enter\n");
3790 if (iwl_is_rfkill(priv))
3793 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3794 test_bit(STATUS_SCANNING, &priv->status))
3797 if (!iwl_is_associated_ctx(ctx))
3800 /* channel switch in progress */
3801 if (priv->switch_rxon.switch_in_progress == true)
3804 mutex_lock(&priv->mutex);
3805 if (priv->cfg->ops->lib->set_channel_switch) {
3807 ch = channel->hw_value;
3808 if (le16_to_cpu(ctx->active.channel) != ch) {
3809 ch_info = iwl_get_channel_info(priv,
3812 if (!is_channel_valid(ch_info)) {
3813 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3816 spin_lock_irqsave(&priv->lock, flags);
3818 priv->current_ht_config.smps = conf->smps_mode;
3820 /* Configure HT40 channels */
3821 ht_conf->is_ht = conf_is_ht(conf);
3822 if (ht_conf->is_ht) {
3823 if (conf_is_ht40_minus(conf)) {
3824 ht_conf->extension_chan_offset =
3825 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3826 ht_conf->is_40mhz = true;
3827 } else if (conf_is_ht40_plus(conf)) {
3828 ht_conf->extension_chan_offset =
3829 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3830 ht_conf->is_40mhz = true;
3832 ht_conf->extension_chan_offset =
3833 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3834 ht_conf->is_40mhz = false;
3837 ht_conf->is_40mhz = false;
3839 if ((le16_to_cpu(ctx->staging.channel) != ch))
3840 ctx->staging.flags = 0;
3842 iwl_set_rxon_channel(priv, channel, ctx);
3843 iwl_set_rxon_ht(priv, ht_conf);
3844 iwl_set_flags_for_band(priv, ctx, channel->band,
3846 spin_unlock_irqrestore(&priv->lock, flags);
3850 * at this point, staging_rxon has the
3851 * configuration for channel switch
3853 if (priv->cfg->ops->lib->set_channel_switch(priv,
3855 priv->switch_rxon.switch_in_progress = false;
3859 mutex_unlock(&priv->mutex);
3861 if (!priv->switch_rxon.switch_in_progress)
3862 ieee80211_chswitch_done(ctx->vif, false);
3863 IWL_DEBUG_MAC80211(priv, "leave\n");
3866 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3867 unsigned int changed_flags,
3868 unsigned int *total_flags,
3871 struct iwl_priv *priv = hw->priv;
3872 __le32 filter_or = 0, filter_nand = 0;
3873 struct iwl_rxon_context *ctx;
3875 #define CHK(test, flag) do { \
3876 if (*total_flags & (test)) \
3877 filter_or |= (flag); \
3879 filter_nand |= (flag); \
3882 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3883 changed_flags, *total_flags);
3885 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3886 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3887 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3891 mutex_lock(&priv->mutex);
3893 for_each_context(priv, ctx) {
3894 ctx->staging.filter_flags &= ~filter_nand;
3895 ctx->staging.filter_flags |= filter_or;
3896 iwlcore_commit_rxon(priv, ctx);
3899 mutex_unlock(&priv->mutex);
3902 * Receiving all multicast frames is always enabled by the
3903 * default flags setup in iwl_connection_init_rx_config()
3904 * since we currently do not support programming multicast
3905 * filters into the device.
3907 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3908 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3911 static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3913 struct iwl_priv *priv = hw->priv;
3915 mutex_lock(&priv->mutex);
3916 IWL_DEBUG_MAC80211(priv, "enter\n");
3918 /* do not support "flush" */
3919 if (!priv->cfg->ops->lib->txfifo_flush)
3922 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3923 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3926 if (iwl_is_rfkill(priv)) {
3927 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3932 * mac80211 will not push any more frames for transmit
3933 * until the flush is completed
3936 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3937 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3938 IWL_ERR(priv, "flush request fail\n");
3942 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3943 iwlagn_wait_tx_queue_empty(priv);
3945 mutex_unlock(&priv->mutex);
3946 IWL_DEBUG_MAC80211(priv, "leave\n");
3949 /*****************************************************************************
3951 * driver setup and teardown
3953 *****************************************************************************/
3955 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3957 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3959 init_waitqueue_head(&priv->wait_command_queue);
3961 INIT_WORK(&priv->restart, iwl_bg_restart);
3962 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3963 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3964 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3965 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3966 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3967 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3968 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3969 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3971 iwl_setup_scan_deferred_work(priv);
3973 if (priv->cfg->ops->lib->setup_deferred_work)
3974 priv->cfg->ops->lib->setup_deferred_work(priv);
3976 init_timer(&priv->statistics_periodic);
3977 priv->statistics_periodic.data = (unsigned long)priv;
3978 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3980 init_timer(&priv->ucode_trace);
3981 priv->ucode_trace.data = (unsigned long)priv;
3982 priv->ucode_trace.function = iwl_bg_ucode_trace;
3984 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3985 init_timer(&priv->monitor_recover);
3986 priv->monitor_recover.data = (unsigned long)priv;
3987 priv->monitor_recover.function =
3988 priv->cfg->ops->lib->recover_from_tx_stall;
3991 if (!priv->cfg->use_isr_legacy)
3992 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3993 iwl_irq_tasklet, (unsigned long)priv);
3995 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3996 iwl_irq_tasklet_legacy, (unsigned long)priv);
3999 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
4001 if (priv->cfg->ops->lib->cancel_deferred_work)
4002 priv->cfg->ops->lib->cancel_deferred_work(priv);
4004 cancel_delayed_work_sync(&priv->init_alive_start);
4005 cancel_delayed_work(&priv->scan_check);
4006 cancel_work_sync(&priv->start_internal_scan);
4007 cancel_delayed_work(&priv->alive_start);
4008 cancel_work_sync(&priv->run_time_calib_work);
4009 cancel_work_sync(&priv->beacon_update);
4010 cancel_work_sync(&priv->bt_full_concurrency);
4011 cancel_work_sync(&priv->bt_runtime_config);
4012 del_timer_sync(&priv->statistics_periodic);
4013 del_timer_sync(&priv->ucode_trace);
4016 static void iwl_init_hw_rates(struct iwl_priv *priv,
4017 struct ieee80211_rate *rates)
4021 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4022 rates[i].bitrate = iwl_rates[i].ieee * 5;
4023 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4024 rates[i].hw_value_short = i;
4026 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4028 * If CCK != 1M then set short preamble rate flag.
4031 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4032 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4037 static int iwl_init_drv(struct iwl_priv *priv)
4041 priv->ibss_beacon = NULL;
4043 spin_lock_init(&priv->sta_lock);
4044 spin_lock_init(&priv->hcmd_lock);
4046 INIT_LIST_HEAD(&priv->free_frames);
4048 mutex_init(&priv->mutex);
4049 mutex_init(&priv->sync_cmd_mutex);
4051 priv->ieee_channels = NULL;
4052 priv->ieee_rates = NULL;
4053 priv->band = IEEE80211_BAND_2GHZ;
4055 priv->iw_mode = NL80211_IFTYPE_STATION;
4056 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
4057 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
4058 priv->_agn.agg_tids_count = 0;
4060 /* initialize force reset */
4061 priv->force_reset[IWL_RF_RESET].reset_duration =
4062 IWL_DELAY_NEXT_FORCE_RF_RESET;
4063 priv->force_reset[IWL_FW_RESET].reset_duration =
4064 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
4066 /* Choose which receivers/antennas to use */
4067 if (priv->cfg->ops->hcmd->set_rxon_chain)
4068 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4069 &priv->contexts[IWL_RXON_CTX_BSS]);
4071 iwl_init_scan_params(priv);
4074 if (priv->cfg->advanced_bt_coexist) {
4075 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4076 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4077 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
4078 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4079 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4080 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4081 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4084 /* Set the tx_power_user_lmt to the lowest power level
4085 * this value will get overwritten by channel max power avg
4087 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4089 ret = iwl_init_channel_map(priv);
4091 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4095 ret = iwlcore_init_geos(priv);
4097 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4098 goto err_free_channel_map;
4100 iwl_init_hw_rates(priv, priv->ieee_rates);
4104 err_free_channel_map:
4105 iwl_free_channel_map(priv);
4110 static void iwl_uninit_drv(struct iwl_priv *priv)
4112 iwl_calib_free_results(priv);
4113 iwlcore_free_geos(priv);
4114 iwl_free_channel_map(priv);
4115 kfree(priv->scan_cmd);
4118 static struct ieee80211_ops iwl_hw_ops = {
4120 .start = iwl_mac_start,
4121 .stop = iwl_mac_stop,
4122 .add_interface = iwl_mac_add_interface,
4123 .remove_interface = iwl_mac_remove_interface,
4124 .config = iwl_mac_config,
4125 .configure_filter = iwlagn_configure_filter,
4126 .set_key = iwl_mac_set_key,
4127 .update_tkip_key = iwl_mac_update_tkip_key,
4128 .conf_tx = iwl_mac_conf_tx,
4129 .reset_tsf = iwl_mac_reset_tsf,
4130 .bss_info_changed = iwl_bss_info_changed,
4131 .ampdu_action = iwl_mac_ampdu_action,
4132 .hw_scan = iwl_mac_hw_scan,
4133 .sta_notify = iwl_mac_sta_notify,
4134 .sta_add = iwlagn_mac_sta_add,
4135 .sta_remove = iwl_mac_sta_remove,
4136 .channel_switch = iwl_mac_channel_switch,
4137 .flush = iwl_mac_flush,
4138 .tx_last_beacon = iwl_mac_tx_last_beacon,
4141 static void iwl_hw_detect(struct iwl_priv *priv)
4143 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4144 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4145 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4146 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4149 static int iwl_set_hw_params(struct iwl_priv *priv)
4151 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4152 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4153 if (priv->cfg->mod_params->amsdu_size_8K)
4154 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4156 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4158 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4160 if (priv->cfg->mod_params->disable_11n)
4161 priv->cfg->sku &= ~IWL_SKU_N;
4163 /* Device-specific setup */
4164 return priv->cfg->ops->lib->set_hw_params(priv);
4167 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4170 struct iwl_priv *priv;
4171 struct ieee80211_hw *hw;
4172 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4173 unsigned long flags;
4174 u16 pci_cmd, num_mac;
4176 /************************
4177 * 1. Allocating HW data
4178 ************************/
4180 /* Disabling hardware scan means that mac80211 will perform scans
4181 * "the hard way", rather than using device's scan. */
4182 if (cfg->mod_params->disable_hw_scan) {
4183 if (iwl_debug_level & IWL_DL_INFO)
4184 dev_printk(KERN_DEBUG, &(pdev->dev),
4185 "Disabling hw_scan\n");
4186 iwl_hw_ops.hw_scan = NULL;
4189 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
4195 /* At this point both hw and priv are allocated. */
4198 * The default context is always valid,
4199 * more may be discovered when firmware
4202 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4204 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4205 priv->contexts[i].ctxid = i;
4207 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4208 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4209 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4210 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4211 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 1);
4213 SET_IEEE80211_DEV(hw, &pdev->dev);
4215 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4217 priv->pci_dev = pdev;
4218 priv->inta_mask = CSR_INI_SET_MASK;
4220 /* is antenna coupling more than 35dB ? */
4221 priv->bt_ant_couple_ok =
4222 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4225 /* enable/disable bt channel announcement */
4226 priv->bt_ch_announce = iwlagn_bt_ch_announce;
4228 if (iwl_alloc_traffic_mem(priv))
4229 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4231 /**************************
4232 * 2. Initializing PCI bus
4233 **************************/
4234 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4235 PCIE_LINK_STATE_CLKPM);
4237 if (pci_enable_device(pdev)) {
4239 goto out_ieee80211_free_hw;
4242 pci_set_master(pdev);
4244 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4246 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4248 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4250 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4251 /* both attempts failed: */
4253 IWL_WARN(priv, "No suitable DMA available.\n");
4254 goto out_pci_disable_device;
4258 err = pci_request_regions(pdev, DRV_NAME);
4260 goto out_pci_disable_device;
4262 pci_set_drvdata(pdev, priv);
4265 /***********************
4266 * 3. Read REV register
4267 ***********************/
4268 priv->hw_base = pci_iomap(pdev, 0, 0);
4269 if (!priv->hw_base) {
4271 goto out_pci_release_regions;
4274 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4275 (unsigned long long) pci_resource_len(pdev, 0));
4276 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4278 /* these spin locks will be used in apm_ops.init and EEPROM access
4279 * we should init now
4281 spin_lock_init(&priv->reg_lock);
4282 spin_lock_init(&priv->lock);
4285 * stop and reset the on-board processor just in case it is in a
4286 * strange state ... like being left stranded by a primary kernel
4287 * and this is now the kdump kernel trying to start up
4289 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4291 iwl_hw_detect(priv);
4292 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4293 priv->cfg->name, priv->hw_rev);
4295 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4296 * PCI Tx retries from interfering with C3 CPU state */
4297 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4299 iwl_prepare_card_hw(priv);
4300 if (!priv->hw_ready) {
4301 IWL_WARN(priv, "Failed, HW not ready\n");
4308 /* Read the EEPROM */
4309 err = iwl_eeprom_init(priv);
4311 IWL_ERR(priv, "Unable to init EEPROM\n");
4314 err = iwl_eeprom_check_version(priv);
4316 goto out_free_eeprom;
4318 /* extract MAC Address */
4319 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4320 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4321 priv->hw->wiphy->addresses = priv->addresses;
4322 priv->hw->wiphy->n_addresses = 1;
4323 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4325 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4327 priv->addresses[1].addr[5]++;
4328 priv->hw->wiphy->n_addresses++;
4331 /************************
4332 * 5. Setup HW constants
4333 ************************/
4334 if (iwl_set_hw_params(priv)) {
4335 IWL_ERR(priv, "failed to set hw parameters\n");
4336 goto out_free_eeprom;
4339 /*******************
4341 *******************/
4343 err = iwl_init_drv(priv);
4345 goto out_free_eeprom;
4346 /* At this point both hw and priv are initialized. */
4348 /********************
4350 ********************/
4351 spin_lock_irqsave(&priv->lock, flags);
4352 iwl_disable_interrupts(priv);
4353 spin_unlock_irqrestore(&priv->lock, flags);
4355 pci_enable_msi(priv->pci_dev);
4357 iwl_alloc_isr_ict(priv);
4358 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4359 IRQF_SHARED, DRV_NAME, priv);
4361 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4362 goto out_disable_msi;
4365 iwl_setup_deferred_work(priv);
4366 iwl_setup_rx_handlers(priv);
4368 /*********************************************
4369 * 8. Enable interrupts and read RFKILL state
4370 *********************************************/
4372 /* enable interrupts if needed: hw bug w/a */
4373 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4374 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4375 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4376 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4379 iwl_enable_interrupts(priv);
4381 /* If platform's RF_KILL switch is NOT set to KILL */
4382 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4383 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4385 set_bit(STATUS_RF_KILL_HW, &priv->status);
4387 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4388 test_bit(STATUS_RF_KILL_HW, &priv->status));
4390 iwl_power_initialize(priv);
4391 iwl_tt_initialize(priv);
4393 init_completion(&priv->_agn.firmware_loading_complete);
4395 err = iwl_request_firmware(priv, true);
4397 goto out_destroy_workqueue;
4401 out_destroy_workqueue:
4402 destroy_workqueue(priv->workqueue);
4403 priv->workqueue = NULL;
4404 free_irq(priv->pci_dev->irq, priv);
4405 iwl_free_isr_ict(priv);
4407 pci_disable_msi(priv->pci_dev);
4408 iwl_uninit_drv(priv);
4410 iwl_eeprom_free(priv);
4412 pci_iounmap(pdev, priv->hw_base);
4413 out_pci_release_regions:
4414 pci_set_drvdata(pdev, NULL);
4415 pci_release_regions(pdev);
4416 out_pci_disable_device:
4417 pci_disable_device(pdev);
4418 out_ieee80211_free_hw:
4419 iwl_free_traffic_mem(priv);
4420 ieee80211_free_hw(priv->hw);
4425 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4427 struct iwl_priv *priv = pci_get_drvdata(pdev);
4428 unsigned long flags;
4433 wait_for_completion(&priv->_agn.firmware_loading_complete);
4435 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4437 iwl_dbgfs_unregister(priv);
4438 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4440 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4441 * to be called and iwl_down since we are removing the device
4442 * we need to set STATUS_EXIT_PENDING bit.
4444 set_bit(STATUS_EXIT_PENDING, &priv->status);
4445 if (priv->mac80211_registered) {
4446 ieee80211_unregister_hw(priv->hw);
4447 priv->mac80211_registered = 0;
4453 * Make sure device is reset to low power before unloading driver.
4454 * This may be redundant with iwl_down(), but there are paths to
4455 * run iwl_down() without calling apm_ops.stop(), and there are
4456 * paths to avoid running iwl_down() at all before leaving driver.
4457 * This (inexpensive) call *makes sure* device is reset.
4459 priv->cfg->ops->lib->apm_ops.stop(priv);
4463 /* make sure we flush any pending irq or
4464 * tasklet for the driver
4466 spin_lock_irqsave(&priv->lock, flags);
4467 iwl_disable_interrupts(priv);
4468 spin_unlock_irqrestore(&priv->lock, flags);
4470 iwl_synchronize_irq(priv);
4472 iwl_dealloc_ucode_pci(priv);
4475 iwlagn_rx_queue_free(priv, &priv->rxq);
4476 iwlagn_hw_txq_ctx_free(priv);
4478 iwl_eeprom_free(priv);
4481 /*netif_stop_queue(dev); */
4482 flush_workqueue(priv->workqueue);
4484 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4485 * priv->workqueue... so we can't take down the workqueue
4487 destroy_workqueue(priv->workqueue);
4488 priv->workqueue = NULL;
4489 iwl_free_traffic_mem(priv);
4491 free_irq(priv->pci_dev->irq, priv);
4492 pci_disable_msi(priv->pci_dev);
4493 pci_iounmap(pdev, priv->hw_base);
4494 pci_release_regions(pdev);
4495 pci_disable_device(pdev);
4496 pci_set_drvdata(pdev, NULL);
4498 iwl_uninit_drv(priv);
4500 iwl_free_isr_ict(priv);
4502 if (priv->ibss_beacon)
4503 dev_kfree_skb(priv->ibss_beacon);
4505 ieee80211_free_hw(priv->hw);
4509 /*****************************************************************************
4511 * driver and module entry point
4513 *****************************************************************************/
4515 /* Hardware specific file defines the PCI IDs table for that hardware module */
4516 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4517 #ifdef CONFIG_IWL4965
4518 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4519 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4520 #endif /* CONFIG_IWL4965 */
4521 #ifdef CONFIG_IWL5000
4522 /* 5100 Series WiFi */
4523 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4524 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4525 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4526 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4527 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4528 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4529 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4530 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4531 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4532 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4533 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4534 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4535 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4536 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4537 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4538 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4539 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4540 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4541 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4542 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4543 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4544 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4545 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4546 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4548 /* 5300 Series WiFi */
4549 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4550 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4551 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4552 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4553 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4554 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4555 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4556 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4557 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4558 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4559 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4560 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4562 /* 5350 Series WiFi/WiMax */
4563 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4564 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4565 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4567 /* 5150 Series Wifi/WiMax */
4568 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4569 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4570 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4571 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4572 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4573 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4575 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4576 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4577 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4578 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4581 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4582 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4583 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4584 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4585 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4586 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4587 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4588 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4589 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4590 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4592 /* 6x00 Series Gen2a */
4593 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4594 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4595 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
4596 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4597 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4598 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4599 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
4600 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4601 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4602 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4603 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4604 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4605 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4606 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
4608 /* 6x00 Series Gen2b */
4609 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4610 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4611 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4612 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4613 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4614 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4615 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4616 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4617 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4618 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4619 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
4620 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4621 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4622 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4623 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4624 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4625 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4626 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4627 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4628 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4629 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4630 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4631 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4632 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4633 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4634 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4635 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4636 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
4638 /* 6x50 WiFi/WiMax Series */
4639 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4640 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4641 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4642 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4643 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4644 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4646 /* 6x50 WiFi/WiMax Series Gen2 */
4647 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4648 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4649 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4650 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4651 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4652 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4654 /* 1000 Series WiFi */
4655 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4656 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4657 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4658 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4659 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4660 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4661 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4662 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4663 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4664 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4665 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4666 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4667 #endif /* CONFIG_IWL5000 */
4671 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4673 static struct pci_driver iwl_driver = {
4675 .id_table = iwl_hw_card_ids,
4676 .probe = iwl_pci_probe,
4677 .remove = __devexit_p(iwl_pci_remove),
4679 .suspend = iwl_pci_suspend,
4680 .resume = iwl_pci_resume,
4684 static int __init iwl_init(void)
4688 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4689 pr_info(DRV_COPYRIGHT "\n");
4691 ret = iwlagn_rate_control_register();
4693 pr_err("Unable to register rate control algorithm: %d\n", ret);
4697 ret = pci_register_driver(&iwl_driver);
4699 pr_err("Unable to initialize PCI module\n");
4700 goto error_register;
4706 iwlagn_rate_control_unregister();
4710 static void __exit iwl_exit(void)
4712 pci_unregister_driver(&iwl_driver);
4713 iwlagn_rate_control_unregister();
4716 module_exit(iwl_exit);
4717 module_init(iwl_init);
4719 #ifdef CONFIG_IWLWIFI_DEBUG
4720 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4721 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4722 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4723 MODULE_PARM_DESC(debug, "debug output mask");
4726 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4727 MODULE_PARM_DESC(swcrypto50,
4728 "using crypto in software (default 0 [hardware]) (deprecated)");
4729 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4730 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4731 module_param_named(queues_num50,
4732 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4733 MODULE_PARM_DESC(queues_num50,
4734 "number of hw queues in 50xx series (deprecated)");
4735 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4736 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4737 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4738 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4739 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4740 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4741 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4743 MODULE_PARM_DESC(amsdu_size_8K50,
4744 "enable 8K amsdu size in 50XX series (deprecated)");
4745 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4747 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4748 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4749 MODULE_PARM_DESC(fw_restart50,
4750 "restart firmware in case of error (deprecated)");
4751 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4752 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4754 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4755 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4757 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4759 MODULE_PARM_DESC(ucode_alternative,
4760 "specify ucode alternative to use from ucode file");
4762 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4763 MODULE_PARM_DESC(antenna_coupling,
4764 "specify antenna coupling in dB (defualt: 0 dB)");
4766 module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4767 MODULE_PARM_DESC(bt_ch_announce,
4768 "Enable BT channel announcement mode (default: enable)");