drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 void iwl_update_chain_flags(struct iwl_priv *priv)
  94 {
  95         struct iwl_rxon_context *ctx;
  96
  97         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  98                 for_each_context(priv, ctx) {
  99                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 100                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 101                                 iwlcore_commit_rxon(priv, ctx);
 102                 }
 103         }
 104 }
 105
 106 static void iwl_clear_free_frames(struct iwl_priv *priv)
 107 {
 108         struct list_head *element;
 109
 110         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 111                        priv->frames_count);
 112
 113         while (!list_empty(&priv->free_frames)) {
 114                 element = priv->free_frames.next;
 115                 list_del(element);
 116                 kfree(list_entry(element, struct iwl_frame, list));
 117                 priv->frames_count--;
 118         }
 119
 120         if (priv->frames_count) {
 121                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 122                             priv->frames_count);
 123                 priv->frames_count = 0;
 124         }
 125 }
 126
 127 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 128 {
 129         struct iwl_frame *frame;
 130         struct list_head *element;
 131         if (list_empty(&priv->free_frames)) {
 132                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 133                 if (!frame) {
 134                         IWL_ERR(priv, "Could not allocate frame!\n");
 135                         return NULL;
 136                 }
 137
 138                 priv->frames_count++;
 139                 return frame;
 140         }
 141
 142         element = priv->free_frames.next;
 143         list_del(element);
 144         return list_entry(element, struct iwl_frame, list);
 145 }
 146
 147 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 148 {
 149         memset(frame, 0, sizeof(*frame));
 150         list_add(&frame->list, &priv->free_frames);
 151 }
 152
 153 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 154                                  struct ieee80211_hdr *hdr,
 155                                  int left)
 156 {
 157         lockdep_assert_held(&priv->mutex);
 158
 159         if (!priv->beacon_skb)
 160                 return 0;
 161
 162         if (priv->beacon_skb->len > left)
 163                 return 0;
 164
 165         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 166
 167         return priv->beacon_skb->len;
 168 }
 169
 170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 171 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 172                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 173                                u8 *beacon, u32 frame_size)
 174 {
 175         u16 tim_idx;
 176         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 177
 178         /*
 179          * The index is relative to frame start but we start looking at the
 180          * variable-length part of the beacon.
 181          */
 182         tim_idx = mgmt->u.beacon.variable - beacon;
 183
 184         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 185         while ((tim_idx < (frame_size - 2)) &&
 186                         (beacon[tim_idx] != WLAN_EID_TIM))
 187                 tim_idx += beacon[tim_idx+1] + 2;
 188
 189         /* If TIM field was found, set variables */
 190         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 191                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 192                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 193         } else
 194                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 195 }
 196
 197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 198                                        struct iwl_frame *frame)
 199 {
 200         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 201         u32 frame_size;
 202         u32 rate_flags;
 203         u32 rate;
 204         /*
 205          * We have to set up the TX command, the TX Beacon command, and the
 206          * beacon contents.
 207          */
 208
 209         lockdep_assert_held(&priv->mutex);
 210
 211         if (!priv->beacon_ctx) {
 212                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 213                 return 0;
 214         }
 215
 216         /* Initialize memory */
 217         tx_beacon_cmd = &frame->u.beacon;
 218         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 219
 220         /* Set up TX beacon contents */
 221         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 222                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 223         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 224                 return 0;
 225         if (!frame_size)
 226                 return 0;
 227
 228         /* Set up TX command fields */
 229         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 230         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 231         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 232         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 233                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 234
 235         /* Set up TX beacon command fields */
 236         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 237                            frame_size);
 238
 239         /* Set up packet rate and flags */
 240         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 241         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 242                                               priv->hw_params.valid_tx_ant);
 243         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 244         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 245                 rate_flags |= RATE_MCS_CCK_MSK;
 246         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 247                         rate_flags);
 248
 249         return sizeof(*tx_beacon_cmd) + frame_size;
 250 }
 251
 252 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 253 {
 254         struct iwl_frame *frame;
 255         unsigned int frame_size;
 256         int rc;
 257
 258         frame = iwl_get_free_frame(priv);
 259         if (!frame) {
 260                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 261                           "command.\n");
 262                 return -ENOMEM;
 263         }
 264
 265         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 266         if (!frame_size) {
 267                 IWL_ERR(priv, "Error configuring the beacon command\n");
 268                 iwl_free_frame(priv, frame);
 269                 return -EINVAL;
 270         }
 271
 272         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 273                               &frame->u.cmd[0]);
 274
 275         iwl_free_frame(priv, frame);
 276
 277         return rc;
 278 }
 279
 280 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 281 {
 282         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 283
 284         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 285         if (sizeof(dma_addr_t) > sizeof(u32))
 286                 addr |=
 287                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 288
 289         return addr;
 290 }
 291
 292 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 293 {
 294         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 295
 296         return le16_to_cpu(tb->hi_n_len) >> 4;
 297 }
 298
 299 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 300                                   dma_addr_t addr, u16 len)
 301 {
 302         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 303         u16 hi_n_len = len << 4;
 304
 305         put_unaligned_le32(addr, &tb->lo);
 306         if (sizeof(dma_addr_t) > sizeof(u32))
 307                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 308
 309         tb->hi_n_len = cpu_to_le16(hi_n_len);
 310
 311         tfd->num_tbs = idx + 1;
 312 }
 313
 314 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 315 {
 316         return tfd->num_tbs & 0x1f;
 317 }
 318
 319 /**
 320  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 321  * @priv - driver private data
 322  * @txq - tx queue
 323  *
 324  * Does NOT advance any TFD circular buffer read/write indexes
 325  * Does NOT free the TFD itself (which is within circular buffer)
 326  */
 327 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 328 {
 329         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 330         struct iwl_tfd *tfd;
 331         struct pci_dev *dev = priv->pci_dev;
 332         int index = txq->q.read_ptr;
 333         int i;
 334         int num_tbs;
 335
 336         tfd = &tfd_tmp[index];
 337
 338         /* Sanity check on number of chunks */
 339         num_tbs = iwl_tfd_get_num_tbs(tfd);
 340
 341         if (num_tbs >= IWL_NUM_OF_TBS) {
 342                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 343                 /* @todo issue fatal error, it is quite serious situation */
 344                 return;
 345         }
 346
 347         /* Unmap tx_cmd */
 348         if (num_tbs)
 349                 pci_unmap_single(dev,
 350                                 dma_unmap_addr(&txq->meta[index], mapping),
 351                                 dma_unmap_len(&txq->meta[index], len),
 352                                 PCI_DMA_BIDIRECTIONAL);
 353
 354         /* Unmap chunks, if any. */
 355         for (i = 1; i < num_tbs; i++)
 356                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 357                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 358
 359         /* free SKB */
 360         if (txq->txb) {
 361                 struct sk_buff *skb;
 362
 363                 skb = txq->txb[txq->q.read_ptr].skb;
 364
 365                 /* can be called from irqs-disabled context */
 366                 if (skb) {
 367                         dev_kfree_skb_any(skb);
 368                         txq->txb[txq->q.read_ptr].skb = NULL;
 369                 }
 370         }
 371 }
 372
 373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 374                                  struct iwl_tx_queue *txq,
 375                                  dma_addr_t addr, u16 len,
 376                                  u8 reset, u8 pad)
 377 {
 378         struct iwl_queue *q;
 379         struct iwl_tfd *tfd, *tfd_tmp;
 380         u32 num_tbs;
 381
 382         q = &txq->q;
 383         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 384         tfd = &tfd_tmp[q->write_ptr];
 385
 386         if (reset)
 387                 memset(tfd, 0, sizeof(*tfd));
 388
 389         num_tbs = iwl_tfd_get_num_tbs(tfd);
 390
 391         /* Each TFD can point to a maximum 20 Tx buffers */
 392         if (num_tbs >= IWL_NUM_OF_TBS) {
 393                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 394                           IWL_NUM_OF_TBS);
 395                 return -EINVAL;
 396         }
 397
 398         BUG_ON(addr & ~DMA_BIT_MASK(36));
 399         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 400                 IWL_ERR(priv, "Unaligned address = %llx\n",
 401                           (unsigned long long)addr);
 402
 403         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 410  * given Tx queue, and enable the DMA channel used for that queue.
 411  *
 412  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 413  * channels supported in hardware.
 414  */
 415 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 416                          struct iwl_tx_queue *txq)
 417 {
 418         int txq_id = txq->q.id;
 419
 420         /* Circular buffer (TFD queue in DRAM) physical base address */
 421         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 422                              txq->q.dma_addr >> 8);
 423
 424         return 0;
 425 }
 426
 427 /******************************************************************************
 428  *
 429  * Generic RX handler implementations
 430  *
 431  ******************************************************************************/
 432 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 433                                 struct iwl_rx_mem_buffer *rxb)
 434 {
 435         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 436         struct iwl_alive_resp *palive;
 437         struct delayed_work *pwork;
 438
 439         palive = &pkt->u.alive_frame;
 440
 441         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 442                        "0x%01X 0x%01X\n",
 443                        palive->is_valid, palive->ver_type,
 444                        palive->ver_subtype);
 445
 446         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 447                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 448                 memcpy(&priv->card_alive_init,
 449                        &pkt->u.alive_frame,
 450                        sizeof(struct iwl_init_alive_resp));
 451                 pwork = &priv->init_alive_start;
 452         } else {
 453                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 454                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 455                        sizeof(struct iwl_alive_resp));
 456                 pwork = &priv->alive_start;
 457         }
 458
 459         /* We delay the ALIVE response by 5ms to
 460          * give the HW RF Kill time to activate... */
 461         if (palive->is_valid == UCODE_VALID_OK)
 462                 queue_delayed_work(priv->workqueue, pwork,
 463                                    msecs_to_jiffies(5));
 464         else {
 465                 IWL_WARN(priv, "%s uCode did not respond OK.\n",
 466                         (palive->ver_subtype == INITIALIZE_SUBTYPE) ?
 467                         "init" : "runtime");
 468                 /*
 469                  * If fail to load init uCode,
 470                  * let's try to load the init uCode again.
 471                  * We should not get into this situation, but if it
 472                  * does happen, we should not move on and loading "runtime"
 473                  * without proper calibrate the device.
 474                  */
 475                 if (palive->ver_subtype == INITIALIZE_SUBTYPE)
 476                         priv->ucode_type = UCODE_NONE;
 477                 queue_work(priv->workqueue, &priv->restart);
 478         }
 479 }
 480
 481 static void iwl_bg_beacon_update(struct work_struct *work)
 482 {
 483         struct iwl_priv *priv =
 484                 container_of(work, struct iwl_priv, beacon_update);
 485         struct sk_buff *beacon;
 486
 487         mutex_lock(&priv->mutex);
 488         if (!priv->beacon_ctx) {
 489                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 490                 goto out;
 491         }
 492
 493         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 494                 /*
 495                  * The ucode will send beacon notifications even in
 496                  * IBSS mode, but we don't want to process them. But
 497                  * we need to defer the type check to here due to
 498                  * requiring locking around the beacon_ctx access.
 499                  */
 500                 goto out;
 501         }
 502
 503         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 504         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 505         if (!beacon) {
 506                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 507                 goto out;
 508         }
 509
 510         /* new beacon skb is allocated every time; dispose previous.*/
 511         dev_kfree_skb(priv->beacon_skb);
 512
 513         priv->beacon_skb = beacon;
 514
 515         iwlagn_send_beacon_cmd(priv);
 516  out:
 517         mutex_unlock(&priv->mutex);
 518 }
 519
 520 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 521 {
 522         struct iwl_priv *priv =
 523                 container_of(work, struct iwl_priv, bt_runtime_config);
 524
 525         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 526                 return;
 527
 528         /* dont send host command if rf-kill is on */
 529         if (!iwl_is_ready_rf(priv))
 530                 return;
 531         priv->cfg->ops->hcmd->send_bt_config(priv);
 532 }
 533
 534 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 535 {
 536         struct iwl_priv *priv =
 537                 container_of(work, struct iwl_priv, bt_full_concurrency);
 538         struct iwl_rxon_context *ctx;
 539
 540         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 541                 return;
 542
 543         /* dont send host command if rf-kill is on */
 544         if (!iwl_is_ready_rf(priv))
 545                 return;
 546
 547         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 548                        priv->bt_full_concurrent ?
 549                        "full concurrency" : "3-wire");
 550
 551         /*
 552          * LQ & RXON updated cmds must be sent before BT Config cmd
 553          * to avoid 3-wire collisions
 554          */
 555         mutex_lock(&priv->mutex);
 556         for_each_context(priv, ctx) {
 557                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 558                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 559                 iwlcore_commit_rxon(priv, ctx);
 560         }
 561         mutex_unlock(&priv->mutex);
 562
 563         priv->cfg->ops->hcmd->send_bt_config(priv);
 564 }
 565
 566 /**
 567  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 568  *
 569  * This callback is provided in order to send a statistics request.
 570  *
 571  * This timer function is continually reset to execute within
 572  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 573  * was received.  We need to ensure we receive the statistics in order
 574  * to update the temperature used for calibrating the TXPOWER.
 575  */
 576 static void iwl_bg_statistics_periodic(unsigned long data)
 577 {
 578         struct iwl_priv *priv = (struct iwl_priv *)data;
 579
 580         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 581                 return;
 582
 583         /* dont send host command if rf-kill is on */
 584         if (!iwl_is_ready_rf(priv))
 585                 return;
 586
 587         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 588 }
 589
 590
 591 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 592                                         u32 start_idx, u32 num_events,
 593                                         u32 mode)
 594 {
 595         u32 i;
 596         u32 ptr;        /* SRAM byte address of log data */
 597         u32 ev, time, data; /* event log data */
 598         unsigned long reg_flags;
 599
 600         if (mode == 0)
 601                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 602         else
 603                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 604
 605         /* Make sure device is powered up for SRAM reads */
 606         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 607         if (iwl_grab_nic_access(priv)) {
 608                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 609                 return;
 610         }
 611
 612         /* Set starting address; reads will auto-increment */
 613         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 614         rmb();
 615
 616         /*
 617          * "time" is actually "data" for mode 0 (no timestamp).
 618          * place event id # at far right for easier visual parsing.
 619          */
 620         for (i = 0; i < num_events; i++) {
 621                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 622                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 623                 if (mode == 0) {
 624                         trace_iwlwifi_dev_ucode_cont_event(priv,
 625                                                         0, time, ev);
 626                 } else {
 627                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 628                         trace_iwlwifi_dev_ucode_cont_event(priv,
 629                                                 time, data, ev);
 630                 }
 631         }
 632         /* Allow device to power down */
 633         iwl_release_nic_access(priv);
 634         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 635 }
 636
 637 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 638 {
 639         u32 capacity;   /* event log capacity in # entries */
 640         u32 base;       /* SRAM byte address of event log header */
 641         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 642         u32 num_wraps;  /* # times uCode wrapped to top of log */
 643         u32 next_entry; /* index of next entry to be written by uCode */
 644
 645         if (priv->ucode_type == UCODE_INIT)
 646                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 647         else
 648                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 649         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 650                 capacity = iwl_read_targ_mem(priv, base);
 651                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 652                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 653                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 654         } else
 655                 return;
 656
 657         if (num_wraps == priv->event_log.num_wraps) {
 658                 iwl_print_cont_event_trace(priv,
 659                                        base, priv->event_log.next_entry,
 660                                        next_entry - priv->event_log.next_entry,
 661                                        mode);
 662                 priv->event_log.non_wraps_count++;
 663         } else {
 664                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 665                         priv->event_log.wraps_more_count++;
 666                 else
 667                         priv->event_log.wraps_once_count++;
 668                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 669                                 num_wraps - priv->event_log.num_wraps,
 670                                 next_entry, priv->event_log.next_entry);
 671                 if (next_entry < priv->event_log.next_entry) {
 672                         iwl_print_cont_event_trace(priv, base,
 673                                priv->event_log.next_entry,
 674                                capacity - priv->event_log.next_entry,
 675                                mode);
 676
 677                         iwl_print_cont_event_trace(priv, base, 0,
 678                                 next_entry, mode);
 679                 } else {
 680                         iwl_print_cont_event_trace(priv, base,
 681                                next_entry, capacity - next_entry,
 682                                mode);
 683
 684                         iwl_print_cont_event_trace(priv, base, 0,
 685                                 next_entry, mode);
 686                 }
 687         }
 688         priv->event_log.num_wraps = num_wraps;
 689         priv->event_log.next_entry = next_entry;
 690 }
 691
 692 /**
 693  * iwl_bg_ucode_trace - Timer callback to log ucode event
 694  *
 695  * The timer is continually set to execute every
 696  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 697  * this function is to perform continuous uCode event logging operation
 698  * if enabled
 699  */
 700 static void iwl_bg_ucode_trace(unsigned long data)
 701 {
 702         struct iwl_priv *priv = (struct iwl_priv *)data;
 703
 704         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 705                 return;
 706
 707         if (priv->event_log.ucode_trace) {
 708                 iwl_continuous_event_trace(priv);
 709                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 710                 mod_timer(&priv->ucode_trace,
 711                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 712         }
 713 }
 714
 715 static void iwlagn_rx_beacon_notif(struct iwl_priv *priv,
 716                                    struct iwl_rx_mem_buffer *rxb)
 717 {
 718         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 719         struct iwlagn_beacon_notif *beacon = (void *)pkt->u.raw;
 720 #ifdef CONFIG_IWLWIFI_DEBUG
 721         u16 status = le16_to_cpu(beacon->beacon_notify_hdr.status.status);
 722         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 723
 724         IWL_DEBUG_RX(priv, "beacon status %#x, retries:%d ibssmgr:%d "
 725                 "tsf:0x%.8x%.8x rate:%d\n",
 726                 status & TX_STATUS_MSK,
 727                 beacon->beacon_notify_hdr.failure_frame,
 728                 le32_to_cpu(beacon->ibss_mgr_status),
 729                 le32_to_cpu(beacon->high_tsf),
 730                 le32_to_cpu(beacon->low_tsf), rate);
 731 #endif
 732
 733         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 734
 735         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 736                 queue_work(priv->workqueue, &priv->beacon_update);
 737 }
 738
 739 /* Handle notification from uCode that card's power state is changing
 740  * due to software, hardware, or critical temperature RFKILL */
 741 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 742                                     struct iwl_rx_mem_buffer *rxb)
 743 {
 744         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 745         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 746         unsigned long status = priv->status;
 747
 748         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 749                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 750                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 751                           (flags & CT_CARD_DISABLED) ?
 752                           "Reached" : "Not reached");
 753
 754         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 755                      CT_CARD_DISABLED)) {
 756
 757                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 758                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 759
 760                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 761                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 762
 763                 if (!(flags & RXON_CARD_DISABLED)) {
 764                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 765                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 766                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 767                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 768                 }
 769                 if (flags & CT_CARD_DISABLED)
 770                         iwl_tt_enter_ct_kill(priv);
 771         }
 772         if (!(flags & CT_CARD_DISABLED))
 773                 iwl_tt_exit_ct_kill(priv);
 774
 775         if (flags & HW_CARD_DISABLED)
 776                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 777         else
 778                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 779
 780
 781         if (!(flags & RXON_CARD_DISABLED))
 782                 iwl_scan_cancel(priv);
 783
 784         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 785              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 786                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 787                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 788         else
 789                 wake_up_interruptible(&priv->wait_command_queue);
 790 }
 791
 792 static void iwl_bg_tx_flush(struct work_struct *work)
 793 {
 794         struct iwl_priv *priv =
 795                 container_of(work, struct iwl_priv, tx_flush);
 796
 797         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 798                 return;
 799
 800         /* do nothing if rf-kill is on */
 801         if (!iwl_is_ready_rf(priv))
 802                 return;
 803
 804         if (priv->cfg->ops->lib->txfifo_flush) {
 805                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 806                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 807         }
 808 }
 809
 810 /**
 811  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 812  *
 813  * Setup the RX handlers for each of the reply types sent from the uCode
 814  * to the host.
 815  *
 816  * This function chains into the hardware specific files for them to setup
 817  * any hardware specific handlers as well.
 818  */
 819 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 820 {
 821         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 822         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 823         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 824         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 825                         iwl_rx_spectrum_measure_notif;
 826         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 827         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 828             iwl_rx_pm_debug_statistics_notif;
 829         priv->rx_handlers[BEACON_NOTIFICATION] = iwlagn_rx_beacon_notif;
 830
 831         /*
 832          * The same handler is used for both the REPLY to a discrete
 833          * statistics request from the host as well as for the periodic
 834          * statistics notifications (after received beacons) from the uCode.
 835          */
 836         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 837         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 838
 839         iwl_setup_rx_scan_handlers(priv);
 840
 841         /* status change handler */
 842         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 843
 844         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 845             iwl_rx_missed_beacon_notif;
 846         /* Rx handlers */
 847         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 848         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 849         /* block ack */
 850         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 851         /* Set up hardware specific Rx handlers */
 852         priv->cfg->ops->lib->rx_handler_setup(priv);
 853 }
 854
 855 /**
 856  * iwl_rx_handle - Main entry function for receiving responses from uCode
 857  *
 858  * Uses the priv->rx_handlers callback function array to invoke
 859  * the appropriate handlers, including command responses,
 860  * frame-received notifications, and other notifications.
 861  */
 862 static void iwl_rx_handle(struct iwl_priv *priv)
 863 {
 864         struct iwl_rx_mem_buffer *rxb;
 865         struct iwl_rx_packet *pkt;
 866         struct iwl_rx_queue *rxq = &priv->rxq;
 867         u32 r, i;
 868         int reclaim;
 869         unsigned long flags;
 870         u8 fill_rx = 0;
 871         u32 count = 8;
 872         int total_empty;
 873
 874         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 875          * buffer that the driver may process (last buffer filled by ucode). */
 876         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 877         i = rxq->read;
 878
 879         /* Rx interrupt, but nothing sent from uCode */
 880         if (i == r)
 881                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 882
 883         /* calculate total frames need to be restock after handling RX */
 884         total_empty = r - rxq->write_actual;
 885         if (total_empty < 0)
 886                 total_empty += RX_QUEUE_SIZE;
 887
 888         if (total_empty > (RX_QUEUE_SIZE / 2))
 889                 fill_rx = 1;
 890
 891         while (i != r) {
 892                 int len;
 893
 894                 rxb = rxq->queue[i];
 895
 896                 /* If an RXB doesn't have a Rx queue slot associated with it,
 897                  * then a bug has been introduced in the queue refilling
 898                  * routines -- catch it here */
 899                 BUG_ON(rxb == NULL);
 900
 901                 rxq->queue[i] = NULL;
 902
 903                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 904                                PAGE_SIZE << priv->hw_params.rx_page_order,
 905                                PCI_DMA_FROMDEVICE);
 906                 pkt = rxb_addr(rxb);
 907
 908                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 909                 len += sizeof(u32); /* account for status word */
 910                 trace_iwlwifi_dev_rx(priv, pkt, len);
 911
 912                 /* Reclaim a command buffer only if this packet is a response
 913                  *   to a (driver-originated) command.
 914                  * If the packet (e.g. Rx frame) originated from uCode,
 915                  *   there is no command buffer to reclaim.
 916                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 917                  *   but apparently a few don't get set; catch them here. */
 918                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 919                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 920                         (pkt->hdr.cmd != REPLY_RX) &&
 921                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 922                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 923                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 924                         (pkt->hdr.cmd != REPLY_TX);
 925
 926                 /*
 927                  * Do the notification wait before RX handlers so
 928                  * even if the RX handler consumes the RXB we have
 929                  * access to it in the notification wait entry.
 930                  */
 931                 if (!list_empty(&priv->_agn.notif_waits)) {
 932                         struct iwl_notification_wait *w;
 933
 934                         spin_lock(&priv->_agn.notif_wait_lock);
 935                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 936                                 if (w->cmd == pkt->hdr.cmd) {
 937                                         w->triggered = true;
 938                                         if (w->fn)
 939                                                 w->fn(priv, pkt);
 940                                 }
 941                         }
 942                         spin_unlock(&priv->_agn.notif_wait_lock);
 943
 944                         wake_up_all(&priv->_agn.notif_waitq);
 945                 }
 946
 947                 /* Based on type of command response or notification,
 948                  *   handle those that need handling via function in
 949                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 950                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 951                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 952                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 953                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 954                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 955                 } else {
 956                         /* No handling needed */
 957                         IWL_DEBUG_RX(priv,
 958                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 959                                 r, i, get_cmd_string(pkt->hdr.cmd),
 960                                 pkt->hdr.cmd);
 961                 }
 962
 963                 /*
 964                  * XXX: After here, we should always check rxb->page
 965                  * against NULL before touching it or its virtual
 966                  * memory (pkt). Because some rx_handler might have
 967                  * already taken or freed the pages.
 968                  */
 969
 970                 if (reclaim) {
 971                         /* Invoke any callbacks, transfer the buffer to caller,
 972                          * and fire off the (possibly) blocking iwl_send_cmd()
 973                          * as we reclaim the driver command queue */
 974                         if (rxb->page)
 975                                 iwl_tx_cmd_complete(priv, rxb);
 976                         else
 977                                 IWL_WARN(priv, "Claim null rxb?\n");
 978                 }
 979
 980                 /* Reuse the page if possible. For notification packets and
 981                  * SKBs that fail to Rx correctly, add them back into the
 982                  * rx_free list for reuse later. */
 983                 spin_lock_irqsave(&rxq->lock, flags);
 984                 if (rxb->page != NULL) {
 985                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 986                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 987                                 PCI_DMA_FROMDEVICE);
 988                         list_add_tail(&rxb->list, &rxq->rx_free);
 989                         rxq->free_count++;
 990                 } else
 991                         list_add_tail(&rxb->list, &rxq->rx_used);
 992
 993                 spin_unlock_irqrestore(&rxq->lock, flags);
 994
 995                 i = (i + 1) & RX_QUEUE_MASK;
 996                 /* If there are a lot of unused frames,
 997                  * restock the Rx queue so ucode wont assert. */
 998                 if (fill_rx) {
 999                         count++;
1000                         if (count >= 8) {
1001                                 rxq->read = i;
1002                                 iwlagn_rx_replenish_now(priv);
1003                                 count = 0;
1004                         }
1005                 }
1006         }
1007
1008         /* Backtrack one entry */
1009         rxq->read = i;
1010         if (fill_rx)
1011                 iwlagn_rx_replenish_now(priv);
1012         else
1013                 iwlagn_rx_queue_restock(priv);
1014 }
1015
1016 /* call this function to flush any scheduled tasklet */
1017 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1018 {
1019         /* wait to make sure we flush pending tasklet*/
1020         synchronize_irq(priv->pci_dev->irq);
1021         tasklet_kill(&priv->irq_tasklet);
1022 }
1023
1024 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1025 {
1026         u32 inta, handled = 0;
1027         u32 inta_fh;
1028         unsigned long flags;
1029         u32 i;
1030 #ifdef CONFIG_IWLWIFI_DEBUG
1031         u32 inta_mask;
1032 #endif
1033
1034         spin_lock_irqsave(&priv->lock, flags);
1035
1036         /* Ack/clear/reset pending uCode interrupts.
1037          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1038          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1039         inta = iwl_read32(priv, CSR_INT);
1040         iwl_write32(priv, CSR_INT, inta);
1041
1042         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1043          * Any new interrupts that happen after this, either while we're
1044          * in this tasklet, or later, will show up in next ISR/tasklet. */
1045         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1046         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1047
1048 #ifdef CONFIG_IWLWIFI_DEBUG
1049         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1050                 /* just for debug */
1051                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1052                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1053                               inta, inta_mask, inta_fh);
1054         }
1055 #endif
1056
1057         spin_unlock_irqrestore(&priv->lock, flags);
1058
1059         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1060          * atomic, make sure that inta covers all the interrupts that
1061          * we've discovered, even if FH interrupt came in just after
1062          * reading CSR_INT. */
1063         if (inta_fh & CSR49_FH_INT_RX_MASK)
1064                 inta |= CSR_INT_BIT_FH_RX;
1065         if (inta_fh & CSR49_FH_INT_TX_MASK)
1066                 inta |= CSR_INT_BIT_FH_TX;
1067
1068         /* Now service all interrupt bits discovered above. */
1069         if (inta & CSR_INT_BIT_HW_ERR) {
1070                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1071
1072                 /* Tell the device to stop sending interrupts */
1073                 iwl_disable_interrupts(priv);
1074
1075                 priv->isr_stats.hw++;
1076                 iwl_irq_handle_error(priv);
1077
1078                 handled |= CSR_INT_BIT_HW_ERR;
1079
1080                 return;
1081         }
1082
1083 #ifdef CONFIG_IWLWIFI_DEBUG
1084         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1085                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1086                 if (inta & CSR_INT_BIT_SCD) {
1087                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1088                                       "the frame/frames.\n");
1089                         priv->isr_stats.sch++;
1090                 }
1091
1092                 /* Alive notification via Rx interrupt will do the real work */
1093                 if (inta & CSR_INT_BIT_ALIVE) {
1094                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1095                         priv->isr_stats.alive++;
1096                 }
1097         }
1098 #endif
1099         /* Safely ignore these bits for debug checks below */
1100         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1101
1102         /* HW RF KILL switch toggled */
1103         if (inta & CSR_INT_BIT_RF_KILL) {
1104                 int hw_rf_kill = 0;
1105                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1106                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1107                         hw_rf_kill = 1;
1108
1109                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1110                                 hw_rf_kill ? "disable radio" : "enable radio");
1111
1112                 priv->isr_stats.rfkill++;
1113
1114                 /* driver only loads ucode once setting the interface up.
1115                  * the driver allows loading the ucode even if the radio
1116                  * is killed. Hence update the killswitch state here. The
1117                  * rfkill handler will care about restarting if needed.
1118                  */
1119                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1120                         if (hw_rf_kill)
1121                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1122                         else
1123                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1124                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1125                 }
1126
1127                 handled |= CSR_INT_BIT_RF_KILL;
1128         }
1129
1130         /* Chip got too hot and stopped itself */
1131         if (inta & CSR_INT_BIT_CT_KILL) {
1132                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1133                 priv->isr_stats.ctkill++;
1134                 handled |= CSR_INT_BIT_CT_KILL;
1135         }
1136
1137         /* Error detected by uCode */
1138         if (inta & CSR_INT_BIT_SW_ERR) {
1139                 IWL_ERR(priv, "Microcode SW error detected. "
1140                         " Restarting 0x%X.\n", inta);
1141                 priv->isr_stats.sw++;
1142                 iwl_irq_handle_error(priv);
1143                 handled |= CSR_INT_BIT_SW_ERR;
1144         }
1145
1146         /*
1147          * uCode wakes up after power-down sleep.
1148          * Tell device about any new tx or host commands enqueued,
1149          * and about any Rx buffers made available while asleep.
1150          */
1151         if (inta & CSR_INT_BIT_WAKEUP) {
1152                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1153                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1154                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1155                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1156                 priv->isr_stats.wakeup++;
1157                 handled |= CSR_INT_BIT_WAKEUP;
1158         }
1159
1160         /* All uCode command responses, including Tx command responses,
1161          * Rx "responses" (frame-received notification), and other
1162          * notifications from uCode come through here*/
1163         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1164                 iwl_rx_handle(priv);
1165                 priv->isr_stats.rx++;
1166                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1167         }
1168
1169         /* This "Tx" DMA channel is used only for loading uCode */
1170         if (inta & CSR_INT_BIT_FH_TX) {
1171                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1172                 priv->isr_stats.tx++;
1173                 handled |= CSR_INT_BIT_FH_TX;
1174                 /* Wake up uCode load routine, now that load is complete */
1175                 priv->ucode_write_complete = 1;
1176                 wake_up_interruptible(&priv->wait_command_queue);
1177         }
1178
1179         if (inta & ~handled) {
1180                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1181                 priv->isr_stats.unhandled++;
1182         }
1183
1184         if (inta & ~(priv->inta_mask)) {
1185                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1186                          inta & ~priv->inta_mask);
1187                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1188         }
1189
1190         /* Re-enable all interrupts */
1191         /* only Re-enable if disabled by irq */
1192         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1193                 iwl_enable_interrupts(priv);
1194         /* Re-enable RF_KILL if it occurred */
1195         else if (handled & CSR_INT_BIT_RF_KILL)
1196                 iwl_enable_rfkill_int(priv);
1197
1198 #ifdef CONFIG_IWLWIFI_DEBUG
1199         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1200                 inta = iwl_read32(priv, CSR_INT);
1201                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1202                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1203                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1204                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1205         }
1206 #endif
1207 }
1208
1209 /* tasklet for iwlagn interrupt */
1210 static void iwl_irq_tasklet(struct iwl_priv *priv)
1211 {
1212         u32 inta = 0;
1213         u32 handled = 0;
1214         unsigned long flags;
1215         u32 i;
1216 #ifdef CONFIG_IWLWIFI_DEBUG
1217         u32 inta_mask;
1218 #endif
1219
1220         spin_lock_irqsave(&priv->lock, flags);
1221
1222         /* Ack/clear/reset pending uCode interrupts.
1223          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1224          */
1225         /* There is a hardware bug in the interrupt mask function that some
1226          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1227          * they are disabled in the CSR_INT_MASK register. Furthermore the
1228          * ICT interrupt handling mechanism has another bug that might cause
1229          * these unmasked interrupts fail to be detected. We workaround the
1230          * hardware bugs here by ACKing all the possible interrupts so that
1231          * interrupt coalescing can still be achieved.
1232          */
1233         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1234
1235         inta = priv->_agn.inta;
1236
1237 #ifdef CONFIG_IWLWIFI_DEBUG
1238         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1239                 /* just for debug */
1240                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1241                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1242                                 inta, inta_mask);
1243         }
1244 #endif
1245
1246         spin_unlock_irqrestore(&priv->lock, flags);
1247
1248         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1249         priv->_agn.inta = 0;
1250
1251         /* Now service all interrupt bits discovered above. */
1252         if (inta & CSR_INT_BIT_HW_ERR) {
1253                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1254
1255                 /* Tell the device to stop sending interrupts */
1256                 iwl_disable_interrupts(priv);
1257
1258                 priv->isr_stats.hw++;
1259                 iwl_irq_handle_error(priv);
1260
1261                 handled |= CSR_INT_BIT_HW_ERR;
1262
1263                 return;
1264         }
1265
1266 #ifdef CONFIG_IWLWIFI_DEBUG
1267         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1268                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1269                 if (inta & CSR_INT_BIT_SCD) {
1270                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1271                                       "the frame/frames.\n");
1272                         priv->isr_stats.sch++;
1273                 }
1274
1275                 /* Alive notification via Rx interrupt will do the real work */
1276                 if (inta & CSR_INT_BIT_ALIVE) {
1277                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1278                         priv->isr_stats.alive++;
1279                 }
1280         }
1281 #endif
1282         /* Safely ignore these bits for debug checks below */
1283         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1284
1285         /* HW RF KILL switch toggled */
1286         if (inta & CSR_INT_BIT_RF_KILL) {
1287                 int hw_rf_kill = 0;
1288                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1289                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1290                         hw_rf_kill = 1;
1291
1292                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1293                                 hw_rf_kill ? "disable radio" : "enable radio");
1294
1295                 priv->isr_stats.rfkill++;
1296
1297                 /* driver only loads ucode once setting the interface up.
1298                  * the driver allows loading the ucode even if the radio
1299                  * is killed. Hence update the killswitch state here. The
1300                  * rfkill handler will care about restarting if needed.
1301                  */
1302                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1303                         if (hw_rf_kill)
1304                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1305                         else
1306                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1307                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1308                 }
1309
1310                 handled |= CSR_INT_BIT_RF_KILL;
1311         }
1312
1313         /* Chip got too hot and stopped itself */
1314         if (inta & CSR_INT_BIT_CT_KILL) {
1315                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1316                 priv->isr_stats.ctkill++;
1317                 handled |= CSR_INT_BIT_CT_KILL;
1318         }
1319
1320         /* Error detected by uCode */
1321         if (inta & CSR_INT_BIT_SW_ERR) {
1322                 IWL_ERR(priv, "Microcode SW error detected. "
1323                         " Restarting 0x%X.\n", inta);
1324                 priv->isr_stats.sw++;
1325                 iwl_irq_handle_error(priv);
1326                 handled |= CSR_INT_BIT_SW_ERR;
1327         }
1328
1329         /* uCode wakes up after power-down sleep */
1330         if (inta & CSR_INT_BIT_WAKEUP) {
1331                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1332                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1333                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1334                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1335
1336                 priv->isr_stats.wakeup++;
1337
1338                 handled |= CSR_INT_BIT_WAKEUP;
1339         }
1340
1341         /* All uCode command responses, including Tx command responses,
1342          * Rx "responses" (frame-received notification), and other
1343          * notifications from uCode come through here*/
1344         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1345                         CSR_INT_BIT_RX_PERIODIC)) {
1346                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1347                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1348                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1349                         iwl_write32(priv, CSR_FH_INT_STATUS,
1350                                         CSR49_FH_INT_RX_MASK);
1351                 }
1352                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1353                         handled |= CSR_INT_BIT_RX_PERIODIC;
1354                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1355                 }
1356                 /* Sending RX interrupt require many steps to be done in the
1357                  * the device:
1358                  * 1- write interrupt to current index in ICT table.
1359                  * 2- dma RX frame.
1360                  * 3- update RX shared data to indicate last write index.
1361                  * 4- send interrupt.
1362                  * This could lead to RX race, driver could receive RX interrupt
1363                  * but the shared data changes does not reflect this;
1364                  * periodic interrupt will detect any dangling Rx activity.
1365                  */
1366
1367                 /* Disable periodic interrupt; we use it as just a one-shot. */
1368                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1369                             CSR_INT_PERIODIC_DIS);
1370                 iwl_rx_handle(priv);
1371
1372                 /*
1373                  * Enable periodic interrupt in 8 msec only if we received
1374                  * real RX interrupt (instead of just periodic int), to catch
1375                  * any dangling Rx interrupt.  If it was just the periodic
1376                  * interrupt, there was no dangling Rx activity, and no need
1377                  * to extend the periodic interrupt; one-shot is enough.
1378                  */
1379                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1380                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1381                                     CSR_INT_PERIODIC_ENA);
1382
1383                 priv->isr_stats.rx++;
1384         }
1385
1386         /* This "Tx" DMA channel is used only for loading uCode */
1387         if (inta & CSR_INT_BIT_FH_TX) {
1388                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1389                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1390                 priv->isr_stats.tx++;
1391                 handled |= CSR_INT_BIT_FH_TX;
1392                 /* Wake up uCode load routine, now that load is complete */
1393                 priv->ucode_write_complete = 1;
1394                 wake_up_interruptible(&priv->wait_command_queue);
1395         }
1396
1397         if (inta & ~handled) {
1398                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1399                 priv->isr_stats.unhandled++;
1400         }
1401
1402         if (inta & ~(priv->inta_mask)) {
1403                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1404                          inta & ~priv->inta_mask);
1405         }
1406
1407         /* Re-enable all interrupts */
1408         /* only Re-enable if disabled by irq */
1409         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1410                 iwl_enable_interrupts(priv);
1411         /* Re-enable RF_KILL if it occurred */
1412         else if (handled & CSR_INT_BIT_RF_KILL)
1413                 iwl_enable_rfkill_int(priv);
1414 }
1415
1416 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1417 #define ACK_CNT_RATIO (50)
1418 #define BA_TIMEOUT_CNT (5)
1419 #define BA_TIMEOUT_MAX (16)
1420
1421 /**
1422  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1423  *
1424  * When the ACK count ratio is low and aggregated BA timeout retries exceeding
1425  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1426  * operation state.
1427  */
1428 bool iwl_good_ack_health(struct iwl_priv *priv, struct iwl_rx_packet *pkt)
1429 {
1430         int actual_delta, expected_delta, ba_timeout_delta;
1431         struct statistics_tx *cur, *old;
1432
1433         if (priv->_agn.agg_tids_count)
1434                 return true;
1435
1436         if (iwl_bt_statistics(priv)) {
1437                 cur = &pkt->u.stats_bt.tx;
1438                 old = &priv->_agn.statistics_bt.tx;
1439         } else {
1440                 cur = &pkt->u.stats.tx;
1441                 old = &priv->_agn.statistics.tx;
1442         }
1443
1444         actual_delta = le32_to_cpu(cur->actual_ack_cnt) -
1445                        le32_to_cpu(old->actual_ack_cnt);
1446         expected_delta = le32_to_cpu(cur->expected_ack_cnt) -
1447                          le32_to_cpu(old->expected_ack_cnt);
1448
1449         /* Values should not be negative, but we do not trust the firmware */
1450         if (actual_delta <= 0 || expected_delta <= 0)
1451                 return true;
1452
1453         ba_timeout_delta = le32_to_cpu(cur->agg.ba_timeout) -
1454                            le32_to_cpu(old->agg.ba_timeout);
1455
1456         if ((actual_delta * 100 / expected_delta) < ACK_CNT_RATIO &&
1457             ba_timeout_delta > BA_TIMEOUT_CNT) {
1458                 IWL_DEBUG_RADIO(priv, "deltas: actual %d expected %d ba_timeout %d\n",
1459                                 actual_delta, expected_delta, ba_timeout_delta);
1460
1461 #ifdef CONFIG_IWLWIFI_DEBUGFS
1462                 /*
1463                  * This is ifdef'ed on DEBUGFS because otherwise the
1464                  * statistics aren't available. If DEBUGFS is set but
1465                  * DEBUG is not, these will just compile out.
1466                  */
1467                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta %d\n",
1468                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1469                 IWL_DEBUG_RADIO(priv,
1470                                 "ack_or_ba_timeout_collision delta %d\n",
1471                                 priv->_agn.delta_statistics.tx.ack_or_ba_timeout_collision);
1472 #endif
1473
1474                 if (ba_timeout_delta >= BA_TIMEOUT_MAX)
1475                         return false;
1476         }
1477
1478         return true;
1479 }
1480
1481
1482 /*****************************************************************************
1483  *
1484  * sysfs attributes
1485  *
1486  *****************************************************************************/
1487
1488 #ifdef CONFIG_IWLWIFI_DEBUG
1489
1490 /*
1491  * The following adds a new attribute to the sysfs representation
1492  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1493  * used for controlling the debug level.
1494  *
1495  * See the level definitions in iwl for details.
1496  *
1497  * The debug_level being managed using sysfs below is a per device debug
1498  * level that is used instead of the global debug level if it (the per
1499  * device debug level) is set.
1500  */
1501 static ssize_t show_debug_level(struct device *d,
1502                                 struct device_attribute *attr, char *buf)
1503 {
1504         struct iwl_priv *priv = dev_get_drvdata(d);
1505         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1506 }
1507 static ssize_t store_debug_level(struct device *d,
1508                                 struct device_attribute *attr,
1509                                  const char *buf, size_t count)
1510 {
1511         struct iwl_priv *priv = dev_get_drvdata(d);
1512         unsigned long val;
1513         int ret;
1514
1515         ret = strict_strtoul(buf, 0, &val);
1516         if (ret)
1517                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1518         else {
1519                 priv->debug_level = val;
1520                 if (iwl_alloc_traffic_mem(priv))
1521                         IWL_ERR(priv,
1522                                 "Not enough memory to generate traffic log\n");
1523         }
1524         return strnlen(buf, count);
1525 }
1526
1527 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1528                         show_debug_level, store_debug_level);
1529
1530
1531 #endif /* CONFIG_IWLWIFI_DEBUG */
1532
1533
1534 static ssize_t show_temperature(struct device *d,
1535                                 struct device_attribute *attr, char *buf)
1536 {
1537         struct iwl_priv *priv = dev_get_drvdata(d);
1538
1539         if (!iwl_is_alive(priv))
1540                 return -EAGAIN;
1541
1542         return sprintf(buf, "%d\n", priv->temperature);
1543 }
1544
1545 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1546
1547 static ssize_t show_tx_power(struct device *d,
1548                              struct device_attribute *attr, char *buf)
1549 {
1550         struct iwl_priv *priv = dev_get_drvdata(d);
1551
1552         if (!iwl_is_ready_rf(priv))
1553                 return sprintf(buf, "off\n");
1554         else
1555                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1556 }
1557
1558 static ssize_t store_tx_power(struct device *d,
1559                               struct device_attribute *attr,
1560                               const char *buf, size_t count)
1561 {
1562         struct iwl_priv *priv = dev_get_drvdata(d);
1563         unsigned long val;
1564         int ret;
1565
1566         ret = strict_strtoul(buf, 10, &val);
1567         if (ret)
1568                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1569         else {
1570                 ret = iwl_set_tx_power(priv, val, false);
1571                 if (ret)
1572                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1573                                 ret);
1574                 else
1575                         ret = count;
1576         }
1577         return ret;
1578 }
1579
1580 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1581
1582 static struct attribute *iwl_sysfs_entries[] = {
1583         &dev_attr_temperature.attr,
1584         &dev_attr_tx_power.attr,
1585 #ifdef CONFIG_IWLWIFI_DEBUG
1586         &dev_attr_debug_level.attr,
1587 #endif
1588         NULL
1589 };
1590
1591 static struct attribute_group iwl_attribute_group = {
1592         .name = NULL,           /* put in device directory */
1593         .attrs = iwl_sysfs_entries,
1594 };
1595
1596 /******************************************************************************
1597  *
1598  * uCode download functions
1599  *
1600  ******************************************************************************/
1601
1602 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1603 {
1604         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1605         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1606         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1607         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1608         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1609         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1610 }
1611
1612 static void iwl_nic_start(struct iwl_priv *priv)
1613 {
1614         /* Remove all resets to allow NIC to operate */
1615         iwl_write32(priv, CSR_RESET, 0);
1616 }
1617
1618 struct iwlagn_ucode_capabilities {
1619         u32 max_probe_length;
1620         u32 standard_phy_calibration_size;
1621         bool pan;
1622 };
1623
1624 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1625 static int iwl_mac_setup_register(struct iwl_priv *priv,
1626                                   struct iwlagn_ucode_capabilities *capa);
1627
1628 #define UCODE_EXPERIMENTAL_INDEX        100
1629 #define UCODE_EXPERIMENTAL_TAG          "exp"
1630
1631 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1632 {
1633         const char *name_pre = priv->cfg->fw_name_pre;
1634         char tag[8];
1635
1636         if (first) {
1637 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1638                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1639                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1640         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1641 #endif
1642                 priv->fw_index = priv->cfg->ucode_api_max;
1643                 sprintf(tag, "%d", priv->fw_index);
1644         } else {
1645                 priv->fw_index--;
1646                 sprintf(tag, "%d", priv->fw_index);
1647         }
1648
1649         if (priv->fw_index < priv->cfg->ucode_api_min) {
1650                 IWL_ERR(priv, "no suitable firmware found!\n");
1651                 return -ENOENT;
1652         }
1653
1654         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1655
1656         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1657                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1658                                 ? "EXPERIMENTAL " : "",
1659                        priv->firmware_name);
1660
1661         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1662                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1663                                        iwl_ucode_callback);
1664 }
1665
1666 struct iwlagn_firmware_pieces {
1667         const void *inst, *data, *init, *init_data, *boot;
1668         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1669
1670         u32 build;
1671
1672         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1673         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1674 };
1675
1676 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1677                                        const struct firmware *ucode_raw,
1678                                        struct iwlagn_firmware_pieces *pieces)
1679 {
1680         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1681         u32 api_ver, hdr_size;
1682         const u8 *src;
1683
1684         priv->ucode_ver = le32_to_cpu(ucode->ver);
1685         api_ver = IWL_UCODE_API(priv->ucode_ver);
1686
1687         switch (api_ver) {
1688         default:
1689                 /*
1690                  * 4965 doesn't revision the firmware file format
1691                  * along with the API version, it always uses v1
1692                  * file format.
1693                  */
1694                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1695                                 CSR_HW_REV_TYPE_4965) {
1696                         hdr_size = 28;
1697                         if (ucode_raw->size < hdr_size) {
1698                                 IWL_ERR(priv, "File size too small!\n");
1699                                 return -EINVAL;
1700                         }
1701                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1702                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1703                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1704                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1705                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1706                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1707                         src = ucode->u.v2.data;
1708                         break;
1709                 }
1710                 /* fall through for 4965 */
1711         case 0:
1712         case 1:
1713         case 2:
1714                 hdr_size = 24;
1715                 if (ucode_raw->size < hdr_size) {
1716                         IWL_ERR(priv, "File size too small!\n");
1717                         return -EINVAL;
1718                 }
1719                 pieces->build = 0;
1720                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1721                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1722                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1723                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1724                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1725                 src = ucode->u.v1.data;
1726                 break;
1727         }
1728
1729         /* Verify size of file vs. image size info in file's header */
1730         if (ucode_raw->size != hdr_size + pieces->inst_size +
1731                                 pieces->data_size + pieces->init_size +
1732                                 pieces->init_data_size + pieces->boot_size) {
1733
1734                 IWL_ERR(priv,
1735                         "uCode file size %d does not match expected size\n",
1736                         (int)ucode_raw->size);
1737                 return -EINVAL;
1738         }
1739
1740         pieces->inst = src;
1741         src += pieces->inst_size;
1742         pieces->data = src;
1743         src += pieces->data_size;
1744         pieces->init = src;
1745         src += pieces->init_size;
1746         pieces->init_data = src;
1747         src += pieces->init_data_size;
1748         pieces->boot = src;
1749         src += pieces->boot_size;
1750
1751         return 0;
1752 }
1753
1754 static int iwlagn_wanted_ucode_alternative = 1;
1755
1756 static int iwlagn_load_firmware(struct iwl_priv *priv,
1757                                 const struct firmware *ucode_raw,
1758                                 struct iwlagn_firmware_pieces *pieces,
1759                                 struct iwlagn_ucode_capabilities *capa)
1760 {
1761         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1762         struct iwl_ucode_tlv *tlv;
1763         size_t len = ucode_raw->size;
1764         const u8 *data;
1765         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1766         u64 alternatives;
1767         u32 tlv_len;
1768         enum iwl_ucode_tlv_type tlv_type;
1769         const u8 *tlv_data;
1770
1771         if (len < sizeof(*ucode)) {
1772                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1773                 return -EINVAL;
1774         }
1775
1776         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1777                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1778                         le32_to_cpu(ucode->magic));
1779                 return -EINVAL;
1780         }
1781
1782         /*
1783          * Check which alternatives are present, and "downgrade"
1784          * when the chosen alternative is not present, warning
1785          * the user when that happens. Some files may not have
1786          * any alternatives, so don't warn in that case.
1787          */
1788         alternatives = le64_to_cpu(ucode->alternatives);
1789         tmp = wanted_alternative;
1790         if (wanted_alternative > 63)
1791                 wanted_alternative = 63;
1792         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1793                 wanted_alternative--;
1794         if (wanted_alternative && wanted_alternative != tmp)
1795                 IWL_WARN(priv,
1796                          "uCode alternative %d not available, choosing %d\n",
1797                          tmp, wanted_alternative);
1798
1799         priv->ucode_ver = le32_to_cpu(ucode->ver);
1800         pieces->build = le32_to_cpu(ucode->build);
1801         data = ucode->data;
1802
1803         len -= sizeof(*ucode);
1804
1805         while (len >= sizeof(*tlv)) {
1806                 u16 tlv_alt;
1807
1808                 len -= sizeof(*tlv);
1809                 tlv = (void *)data;
1810
1811                 tlv_len = le32_to_cpu(tlv->length);
1812                 tlv_type = le16_to_cpu(tlv->type);
1813                 tlv_alt = le16_to_cpu(tlv->alternative);
1814                 tlv_data = tlv->data;
1815
1816                 if (len < tlv_len) {
1817                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1818                                 len, tlv_len);
1819                         return -EINVAL;
1820                 }
1821                 len -= ALIGN(tlv_len, 4);
1822                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1823
1824                 /*
1825                  * Alternative 0 is always valid.
1826                  *
1827                  * Skip alternative TLVs that are not selected.
1828                  */
1829                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1830                         continue;
1831
1832                 switch (tlv_type) {
1833                 case IWL_UCODE_TLV_INST:
1834                         pieces->inst = tlv_data;
1835                         pieces->inst_size = tlv_len;
1836                         break;
1837                 case IWL_UCODE_TLV_DATA:
1838                         pieces->data = tlv_data;
1839                         pieces->data_size = tlv_len;
1840                         break;
1841                 case IWL_UCODE_TLV_INIT:
1842                         pieces->init = tlv_data;
1843                         pieces->init_size = tlv_len;
1844                         break;
1845                 case IWL_UCODE_TLV_INIT_DATA:
1846                         pieces->init_data = tlv_data;
1847                         pieces->init_data_size = tlv_len;
1848                         break;
1849                 case IWL_UCODE_TLV_BOOT:
1850                         pieces->boot = tlv_data;
1851                         pieces->boot_size = tlv_len;
1852                         break;
1853                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1854                         if (tlv_len != sizeof(u32))
1855                                 goto invalid_tlv_len;
1856                         capa->max_probe_length =
1857                                         le32_to_cpup((__le32 *)tlv_data);
1858                         break;
1859                 case IWL_UCODE_TLV_PAN:
1860                         if (tlv_len)
1861                                 goto invalid_tlv_len;
1862                         capa->pan = true;
1863                         break;
1864                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1865                         if (tlv_len != sizeof(u32))
1866                                 goto invalid_tlv_len;
1867                         pieces->init_evtlog_ptr =
1868                                         le32_to_cpup((__le32 *)tlv_data);
1869                         break;
1870                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1871                         if (tlv_len != sizeof(u32))
1872                                 goto invalid_tlv_len;
1873                         pieces->init_evtlog_size =
1874                                         le32_to_cpup((__le32 *)tlv_data);
1875                         break;
1876                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1877                         if (tlv_len != sizeof(u32))
1878                                 goto invalid_tlv_len;
1879                         pieces->init_errlog_ptr =
1880                                         le32_to_cpup((__le32 *)tlv_data);
1881                         break;
1882                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1883                         if (tlv_len != sizeof(u32))
1884                                 goto invalid_tlv_len;
1885                         pieces->inst_evtlog_ptr =
1886                                         le32_to_cpup((__le32 *)tlv_data);
1887                         break;
1888                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1889                         if (tlv_len != sizeof(u32))
1890                                 goto invalid_tlv_len;
1891                         pieces->inst_evtlog_size =
1892                                         le32_to_cpup((__le32 *)tlv_data);
1893                         break;
1894                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1895                         if (tlv_len != sizeof(u32))
1896                                 goto invalid_tlv_len;
1897                         pieces->inst_errlog_ptr =
1898                                         le32_to_cpup((__le32 *)tlv_data);
1899                         break;
1900                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1901                         if (tlv_len)
1902                                 goto invalid_tlv_len;
1903                         priv->enhance_sensitivity_table = true;
1904                         break;
1905                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1906                         if (tlv_len != sizeof(u32))
1907                                 goto invalid_tlv_len;
1908                         capa->standard_phy_calibration_size =
1909                                         le32_to_cpup((__le32 *)tlv_data);
1910                         break;
1911                 default:
1912                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1913                         break;
1914                 }
1915         }
1916
1917         if (len) {
1918                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1919                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1920                 return -EINVAL;
1921         }
1922
1923         return 0;
1924
1925  invalid_tlv_len:
1926         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1927         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1928
1929         return -EINVAL;
1930 }
1931
1932 /**
1933  * iwl_ucode_callback - callback when firmware was loaded
1934  *
1935  * If loaded successfully, copies the firmware into buffers
1936  * for the card to fetch (via DMA).
1937  */
1938 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1939 {
1940         struct iwl_priv *priv = context;
1941         struct iwl_ucode_header *ucode;
1942         int err;
1943         struct iwlagn_firmware_pieces pieces;
1944         const unsigned int api_max = priv->cfg->ucode_api_max;
1945         const unsigned int api_min = priv->cfg->ucode_api_min;
1946         u32 api_ver;
1947         char buildstr[25];
1948         u32 build;
1949         struct iwlagn_ucode_capabilities ucode_capa = {
1950                 .max_probe_length = 200,
1951                 .standard_phy_calibration_size =
1952                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1953         };
1954
1955         memset(&pieces, 0, sizeof(pieces));
1956
1957         if (!ucode_raw) {
1958                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1959                         IWL_ERR(priv,
1960                                 "request for firmware file '%s' failed.\n",
1961                                 priv->firmware_name);
1962                 goto try_again;
1963         }
1964
1965         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1966                        priv->firmware_name, ucode_raw->size);
1967
1968         /* Make sure that we got at least the API version number */
1969         if (ucode_raw->size < 4) {
1970                 IWL_ERR(priv, "File size way too small!\n");
1971                 goto try_again;
1972         }
1973
1974         /* Data from ucode file:  header followed by uCode images */
1975         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1976
1977         if (ucode->ver)
1978                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1979         else
1980                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1981                                            &ucode_capa);
1982
1983         if (err)
1984                 goto try_again;
1985
1986         api_ver = IWL_UCODE_API(priv->ucode_ver);
1987         build = pieces.build;
1988
1989         /*
1990          * api_ver should match the api version forming part of the
1991          * firmware filename ... but we don't check for that and only rely
1992          * on the API version read from firmware header from here on forward
1993          */
1994         /* no api version check required for experimental uCode */
1995         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1996                 if (api_ver < api_min || api_ver > api_max) {
1997                         IWL_ERR(priv,
1998                                 "Driver unable to support your firmware API. "
1999                                 "Driver supports v%u, firmware is v%u.\n",
2000                                 api_max, api_ver);
2001                         goto try_again;
2002                 }
2003
2004                 if (api_ver != api_max)
2005                         IWL_ERR(priv,
2006                                 "Firmware has old API version. Expected v%u, "
2007                                 "got v%u. New firmware can be obtained "
2008                                 "from http://www.intellinuxwireless.org.\n",
2009                                 api_max, api_ver);
2010         }
2011
2012         if (build)
2013                 sprintf(buildstr, " build %u%s", build,
2014                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2015                                 ? " (EXP)" : "");
2016         else
2017                 buildstr[0] = '\0';
2018
2019         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2020                  IWL_UCODE_MAJOR(priv->ucode_ver),
2021                  IWL_UCODE_MINOR(priv->ucode_ver),
2022                  IWL_UCODE_API(priv->ucode_ver),
2023                  IWL_UCODE_SERIAL(priv->ucode_ver),
2024                  buildstr);
2025
2026         snprintf(priv->hw->wiphy->fw_version,
2027                  sizeof(priv->hw->wiphy->fw_version),
2028                  "%u.%u.%u.%u%s",
2029                  IWL_UCODE_MAJOR(priv->ucode_ver),
2030                  IWL_UCODE_MINOR(priv->ucode_ver),
2031                  IWL_UCODE_API(priv->ucode_ver),
2032                  IWL_UCODE_SERIAL(priv->ucode_ver),
2033                  buildstr);
2034
2035         /*
2036          * For any of the failures below (before allocating pci memory)
2037          * we will try to load a version with a smaller API -- maybe the
2038          * user just got a corrupted version of the latest API.
2039          */
2040
2041         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2042                        priv->ucode_ver);
2043         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2044                        pieces.inst_size);
2045         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2046                        pieces.data_size);
2047         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2048                        pieces.init_size);
2049         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2050                        pieces.init_data_size);
2051         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2052                        pieces.boot_size);
2053
2054         /* Verify that uCode images will fit in card's SRAM */
2055         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2056                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2057                         pieces.inst_size);
2058                 goto try_again;
2059         }
2060
2061         if (pieces.data_size > priv->hw_params.max_data_size) {
2062                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2063                         pieces.data_size);
2064                 goto try_again;
2065         }
2066
2067         if (pieces.init_size > priv->hw_params.max_inst_size) {
2068                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2069                         pieces.init_size);
2070                 goto try_again;
2071         }
2072
2073         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2074                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2075                         pieces.init_data_size);
2076                 goto try_again;
2077         }
2078
2079         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2080                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2081                         pieces.boot_size);
2082                 goto try_again;
2083         }
2084
2085         /* Allocate ucode buffers for card's bus-master loading ... */
2086
2087         /* Runtime instructions and 2 copies of data:
2088          * 1) unmodified from disk
2089          * 2) backup cache for save/restore during power-downs */
2090         priv->ucode_code.len = pieces.inst_size;
2091         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2092
2093         priv->ucode_data.len = pieces.data_size;
2094         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2095
2096         priv->ucode_data_backup.len = pieces.data_size;
2097         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2098
2099         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2100             !priv->ucode_data_backup.v_addr)
2101                 goto err_pci_alloc;
2102
2103         /* Initialization instructions and data */
2104         if (pieces.init_size && pieces.init_data_size) {
2105                 priv->ucode_init.len = pieces.init_size;
2106                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2107
2108                 priv->ucode_init_data.len = pieces.init_data_size;
2109                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2110
2111                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2112                         goto err_pci_alloc;
2113         }
2114
2115         /* Bootstrap (instructions only, no data) */
2116         if (pieces.boot_size) {
2117                 priv->ucode_boot.len = pieces.boot_size;
2118                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2119
2120                 if (!priv->ucode_boot.v_addr)
2121                         goto err_pci_alloc;
2122         }
2123
2124         /* Now that we can no longer fail, copy information */
2125
2126         /*
2127          * The (size - 16) / 12 formula is based on the information recorded
2128          * for each event, which is of mode 1 (including timestamp) for all
2129          * new microcodes that include this information.
2130          */
2131         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2132         if (pieces.init_evtlog_size)
2133                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2134         else
2135                 priv->_agn.init_evtlog_size =
2136                         priv->cfg->base_params->max_event_log_size;
2137         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2138         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2139         if (pieces.inst_evtlog_size)
2140                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2141         else
2142                 priv->_agn.inst_evtlog_size =
2143                         priv->cfg->base_params->max_event_log_size;
2144         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2145
2146         if (ucode_capa.pan) {
2147                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2148                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2149         } else
2150                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2151
2152         /* Copy images into buffers for card's bus-master reads ... */
2153
2154         /* Runtime instructions (first block of data in file) */
2155         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2156                         pieces.inst_size);
2157         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2158
2159         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2160                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2161
2162         /*
2163          * Runtime data
2164          * NOTE:  Copy into backup buffer will be done in iwl_up()
2165          */
2166         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2167                         pieces.data_size);
2168         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2169         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2170
2171         /* Initialization instructions */
2172         if (pieces.init_size) {
2173                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2174                                 pieces.init_size);
2175                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2176         }
2177
2178         /* Initialization data */
2179         if (pieces.init_data_size) {
2180                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2181                                pieces.init_data_size);
2182                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2183                        pieces.init_data_size);
2184         }
2185
2186         /* Bootstrap instructions */
2187         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2188                         pieces.boot_size);
2189         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2190
2191         /*
2192          * figure out the offset of chain noise reset and gain commands
2193          * base on the size of standard phy calibration commands table size
2194          */
2195         if (ucode_capa.standard_phy_calibration_size >
2196             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2197                 ucode_capa.standard_phy_calibration_size =
2198                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2199
2200         priv->_agn.phy_calib_chain_noise_reset_cmd =
2201                 ucode_capa.standard_phy_calibration_size;
2202         priv->_agn.phy_calib_chain_noise_gain_cmd =
2203                 ucode_capa.standard_phy_calibration_size + 1;
2204
2205         /**************************************************
2206          * This is still part of probe() in a sense...
2207          *
2208          * 9. Setup and register with mac80211 and debugfs
2209          **************************************************/
2210         err = iwl_mac_setup_register(priv, &ucode_capa);
2211         if (err)
2212                 goto out_unbind;
2213
2214         err = iwl_dbgfs_register(priv, DRV_NAME);
2215         if (err)
2216                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2217
2218         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2219                                         &iwl_attribute_group);
2220         if (err) {
2221                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2222                 goto out_unbind;
2223         }
2224
2225         /* We have our copies now, allow OS release its copies */
2226         release_firmware(ucode_raw);
2227         complete(&priv->_agn.firmware_loading_complete);
2228         return;
2229
2230  try_again:
2231         /* try next, if any */
2232         if (iwl_request_firmware(priv, false))
2233                 goto out_unbind;
2234         release_firmware(ucode_raw);
2235         return;
2236
2237  err_pci_alloc:
2238         IWL_ERR(priv, "failed to allocate pci memory\n");
2239         iwl_dealloc_ucode_pci(priv);
2240  out_unbind:
2241         complete(&priv->_agn.firmware_loading_complete);
2242         device_release_driver(&priv->pci_dev->dev);
2243         release_firmware(ucode_raw);
2244 }
2245
2246 static const char *desc_lookup_text[] = {
2247         "OK",
2248         "FAIL",
2249         "BAD_PARAM",
2250         "BAD_CHECKSUM",
2251         "NMI_INTERRUPT_WDG",
2252         "SYSASSERT",
2253         "FATAL_ERROR",
2254         "BAD_COMMAND",
2255         "HW_ERROR_TUNE_LOCK",
2256         "HW_ERROR_TEMPERATURE",
2257         "ILLEGAL_CHAN_FREQ",
2258         "VCC_NOT_STABLE",
2259         "FH_ERROR",
2260         "NMI_INTERRUPT_HOST",
2261         "NMI_INTERRUPT_ACTION_PT",
2262         "NMI_INTERRUPT_UNKNOWN",
2263         "UCODE_VERSION_MISMATCH",
2264         "HW_ERROR_ABS_LOCK",
2265         "HW_ERROR_CAL_LOCK_FAIL",
2266         "NMI_INTERRUPT_INST_ACTION_PT",
2267         "NMI_INTERRUPT_DATA_ACTION_PT",
2268         "NMI_TRM_HW_ER",
2269         "NMI_INTERRUPT_TRM",
2270         "NMI_INTERRUPT_BREAK_POINT"
2271         "DEBUG_0",
2272         "DEBUG_1",
2273         "DEBUG_2",
2274         "DEBUG_3",
2275 };
2276
2277 static struct { char *name; u8 num; } advanced_lookup[] = {
2278         { "NMI_INTERRUPT_WDG", 0x34 },
2279         { "SYSASSERT", 0x35 },
2280         { "UCODE_VERSION_MISMATCH", 0x37 },
2281         { "BAD_COMMAND", 0x38 },
2282         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2283         { "FATAL_ERROR", 0x3D },
2284         { "NMI_TRM_HW_ERR", 0x46 },
2285         { "NMI_INTERRUPT_TRM", 0x4C },
2286         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2287         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2288         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2289         { "NMI_INTERRUPT_HOST", 0x66 },
2290         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2291         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2292         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2293         { "ADVANCED_SYSASSERT", 0 },
2294 };
2295
2296 static const char *desc_lookup(u32 num)
2297 {
2298         int i;
2299         int max = ARRAY_SIZE(desc_lookup_text);
2300
2301         if (num < max)
2302                 return desc_lookup_text[num];
2303
2304         max = ARRAY_SIZE(advanced_lookup) - 1;
2305         for (i = 0; i < max; i++) {
2306                 if (advanced_lookup[i].num == num)
2307                         break;;
2308         }
2309         return advanced_lookup[i].name;
2310 }
2311
2312 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2313 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2314
2315 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2316 {
2317         u32 data2, line;
2318         u32 desc, time, count, base, data1;
2319         u32 blink1, blink2, ilink1, ilink2;
2320         u32 pc, hcmd;
2321
2322         if (priv->ucode_type == UCODE_INIT) {
2323                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2324                 if (!base)
2325                         base = priv->_agn.init_errlog_ptr;
2326         } else {
2327                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2328                 if (!base)
2329                         base = priv->_agn.inst_errlog_ptr;
2330         }
2331
2332         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2333                 IWL_ERR(priv,
2334                         "Not valid error log pointer 0x%08X for %s uCode\n",
2335                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2336                 return;
2337         }
2338
2339         count = iwl_read_targ_mem(priv, base);
2340
2341         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2342                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2343                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2344                         priv->status, count);
2345         }
2346
2347         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2348         priv->isr_stats.err_code = desc;
2349         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2350         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2351         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2352         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2353         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2354         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2355         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2356         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2357         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2358         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2359
2360         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2361                                       blink1, blink2, ilink1, ilink2);
2362
2363         IWL_ERR(priv, "Desc                                  Time       "
2364                 "data1      data2      line\n");
2365         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2366                 desc_lookup(desc), desc, time, data1, data2, line);
2367         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2368         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2369                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2370 }
2371
2372 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2373
2374 /**
2375  * iwl_print_event_log - Dump error event log to syslog
2376  *
2377  */
2378 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2379                                u32 num_events, u32 mode,
2380                                int pos, char **buf, size_t bufsz)
2381 {
2382         u32 i;
2383         u32 base;       /* SRAM byte address of event log header */
2384         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2385         u32 ptr;        /* SRAM byte address of log data */
2386         u32 ev, time, data; /* event log data */
2387         unsigned long reg_flags;
2388
2389         if (num_events == 0)
2390                 return pos;
2391
2392         if (priv->ucode_type == UCODE_INIT) {
2393                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2394                 if (!base)
2395                         base = priv->_agn.init_evtlog_ptr;
2396         } else {
2397                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2398                 if (!base)
2399                         base = priv->_agn.inst_evtlog_ptr;
2400         }
2401
2402         if (mode == 0)
2403                 event_size = 2 * sizeof(u32);
2404         else
2405                 event_size = 3 * sizeof(u32);
2406
2407         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2408
2409         /* Make sure device is powered up for SRAM reads */
2410         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2411         iwl_grab_nic_access(priv);
2412
2413         /* Set starting address; reads will auto-increment */
2414         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2415         rmb();
2416
2417         /* "time" is actually "data" for mode 0 (no timestamp).
2418         * place event id # at far right for easier visual parsing. */
2419         for (i = 0; i < num_events; i++) {
2420                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2421                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2422                 if (mode == 0) {
2423                         /* data, ev */
2424                         if (bufsz) {
2425                                 pos += scnprintf(*buf + pos, bufsz - pos,
2426                                                 "EVT_LOG:0x%08x:%04u\n",
2427                                                 time, ev);
2428                         } else {
2429                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2430                                         time, ev);
2431                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2432                                         time, ev);
2433                         }
2434                 } else {
2435                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2436                         if (bufsz) {
2437                                 pos += scnprintf(*buf + pos, bufsz - pos,
2438                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2439                                                  time, data, ev);
2440                         } else {
2441                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2442                                         time, data, ev);
2443                                 trace_iwlwifi_dev_ucode_event(priv, time,
2444                                         data, ev);
2445                         }
2446                 }
2447         }
2448
2449         /* Allow device to power down */
2450         iwl_release_nic_access(priv);
2451         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2452         return pos;
2453 }
2454
2455 /**
2456  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2457  */
2458 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2459                                     u32 num_wraps, u32 next_entry,
2460                                     u32 size, u32 mode,
2461                                     int pos, char **buf, size_t bufsz)
2462 {
2463         /*
2464          * display the newest DEFAULT_LOG_ENTRIES entries
2465          * i.e the entries just before the next ont that uCode would fill.
2466          */
2467         if (num_wraps) {
2468                 if (next_entry < size) {
2469                         pos = iwl_print_event_log(priv,
2470                                                 capacity - (size - next_entry),
2471                                                 size - next_entry, mode,
2472                                                 pos, buf, bufsz);
2473                         pos = iwl_print_event_log(priv, 0,
2474                                                   next_entry, mode,
2475                                                   pos, buf, bufsz);
2476                 } else
2477                         pos = iwl_print_event_log(priv, next_entry - size,
2478                                                   size, mode, pos, buf, bufsz);
2479         } else {
2480                 if (next_entry < size) {
2481                         pos = iwl_print_event_log(priv, 0, next_entry,
2482                                                   mode, pos, buf, bufsz);
2483                 } else {
2484                         pos = iwl_print_event_log(priv, next_entry - size,
2485                                                   size, mode, pos, buf, bufsz);
2486                 }
2487         }
2488         return pos;
2489 }
2490
2491 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2492
2493 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2494                             char **buf, bool display)
2495 {
2496         u32 base;       /* SRAM byte address of event log header */
2497         u32 capacity;   /* event log capacity in # entries */
2498         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2499         u32 num_wraps;  /* # times uCode wrapped to top of log */
2500         u32 next_entry; /* index of next entry to be written by uCode */
2501         u32 size;       /* # entries that we'll print */
2502         u32 logsize;
2503         int pos = 0;
2504         size_t bufsz = 0;
2505
2506         if (priv->ucode_type == UCODE_INIT) {
2507                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2508                 logsize = priv->_agn.init_evtlog_size;
2509                 if (!base)
2510                         base = priv->_agn.init_evtlog_ptr;
2511         } else {
2512                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2513                 logsize = priv->_agn.inst_evtlog_size;
2514                 if (!base)
2515                         base = priv->_agn.inst_evtlog_ptr;
2516         }
2517
2518         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2519                 IWL_ERR(priv,
2520                         "Invalid event log pointer 0x%08X for %s uCode\n",
2521                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2522                 return -EINVAL;
2523         }
2524
2525         /* event log header */
2526         capacity = iwl_read_targ_mem(priv, base);
2527         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2528         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2529         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2530
2531         if (capacity > logsize) {
2532                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2533                         capacity, logsize);
2534                 capacity = logsize;
2535         }
2536
2537         if (next_entry > logsize) {
2538                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2539                         next_entry, logsize);
2540                 next_entry = logsize;
2541         }
2542
2543         size = num_wraps ? capacity : next_entry;
2544
2545         /* bail out if nothing in log */
2546         if (size == 0) {
2547                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2548                 return pos;
2549         }
2550
2551         /* enable/disable bt channel inhibition */
2552         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2553
2554 #ifdef CONFIG_IWLWIFI_DEBUG
2555         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2556                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2557                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2558 #else
2559         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2560                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2561 #endif
2562         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2563                 size);
2564
2565 #ifdef CONFIG_IWLWIFI_DEBUG
2566         if (display) {
2567                 if (full_log)
2568                         bufsz = capacity * 48;
2569                 else
2570                         bufsz = size * 48;
2571                 *buf = kmalloc(bufsz, GFP_KERNEL);
2572                 if (!*buf)
2573                         return -ENOMEM;
2574         }
2575         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2576                 /*
2577                  * if uCode has wrapped back to top of log,
2578                  * start at the oldest entry,
2579                  * i.e the next one that uCode would fill.
2580                  */
2581                 if (num_wraps)
2582                         pos = iwl_print_event_log(priv, next_entry,
2583                                                 capacity - next_entry, mode,
2584                                                 pos, buf, bufsz);
2585                 /* (then/else) start at top of log */
2586                 pos = iwl_print_event_log(priv, 0,
2587                                           next_entry, mode, pos, buf, bufsz);
2588         } else
2589                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2590                                                 next_entry, size, mode,
2591                                                 pos, buf, bufsz);
2592 #else
2593         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2594                                         next_entry, size, mode,
2595                                         pos, buf, bufsz);
2596 #endif
2597         return pos;
2598 }
2599
2600 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2601 {
2602         struct iwl_ct_kill_config cmd;
2603         struct iwl_ct_kill_throttling_config adv_cmd;
2604         unsigned long flags;
2605         int ret = 0;
2606
2607         spin_lock_irqsave(&priv->lock, flags);
2608         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2609                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2610         spin_unlock_irqrestore(&priv->lock, flags);
2611         priv->thermal_throttle.ct_kill_toggle = false;
2612
2613         if (priv->cfg->base_params->support_ct_kill_exit) {
2614                 adv_cmd.critical_temperature_enter =
2615                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2616                 adv_cmd.critical_temperature_exit =
2617                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2618
2619                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2620                                        sizeof(adv_cmd), &adv_cmd);
2621                 if (ret)
2622                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2623                 else
2624                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2625                                         "succeeded, "
2626                                         "critical temperature enter is %d,"
2627                                         "exit is %d\n",
2628                                        priv->hw_params.ct_kill_threshold,
2629                                        priv->hw_params.ct_kill_exit_threshold);
2630         } else {
2631                 cmd.critical_temperature_R =
2632                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2633
2634                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2635                                        sizeof(cmd), &cmd);
2636                 if (ret)
2637                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2638                 else
2639                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2640                                         "succeeded, "
2641                                         "critical temperature is %d\n",
2642                                         priv->hw_params.ct_kill_threshold);
2643         }
2644 }
2645
2646 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2647 {
2648         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2649         struct iwl_host_cmd cmd = {
2650                 .id = CALIBRATION_CFG_CMD,
2651                 .len = sizeof(struct iwl_calib_cfg_cmd),
2652                 .data = &calib_cfg_cmd,
2653         };
2654
2655         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2656         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2657         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2658
2659         return iwl_send_cmd(priv, &cmd);
2660 }
2661
2662
2663 /**
2664  * iwl_alive_start - called after REPLY_ALIVE notification received
2665  *                   from protocol/runtime uCode (initialization uCode's
2666  *                   Alive gets handled by iwl_init_alive_start()).
2667  */
2668 static void iwl_alive_start(struct iwl_priv *priv)
2669 {
2670         int ret = 0;
2671         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2672
2673         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2674
2675         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2676          * This is a paranoid check, because we would not have gotten the
2677          * "runtime" alive if code weren't properly loaded.  */
2678         if (iwl_verify_ucode(priv)) {
2679                 /* Runtime instruction load was bad;
2680                  * take it all the way back down so we can try again */
2681                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2682                 goto restart;
2683         }
2684
2685         ret = priv->cfg->ops->lib->alive_notify(priv);
2686         if (ret) {
2687                 IWL_WARN(priv,
2688                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2689                 goto restart;
2690         }
2691
2692
2693         /* After the ALIVE response, we can send host commands to the uCode */
2694         set_bit(STATUS_ALIVE, &priv->status);
2695
2696         /* Enable watchdog to monitor the driver tx queues */
2697         iwl_setup_watchdog(priv);
2698
2699         if (iwl_is_rfkill(priv))
2700                 return;
2701
2702         /* download priority table before any calibration request */
2703         if (priv->cfg->bt_params &&
2704             priv->cfg->bt_params->advanced_bt_coexist) {
2705                 /* Configure Bluetooth device coexistence support */
2706                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2707                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2708                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2709                 priv->cfg->ops->hcmd->send_bt_config(priv);
2710                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2711                 iwlagn_send_prio_tbl(priv);
2712
2713                 /* FIXME: w/a to force change uCode BT state machine */
2714                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2715                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2716                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2717                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2718         }
2719         if (priv->hw_params.calib_rt_cfg)
2720                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2721
2722         ieee80211_wake_queues(priv->hw);
2723
2724         priv->active_rate = IWL_RATES_MASK;
2725
2726         /* Configure Tx antenna selection based on H/W config */
2727         if (priv->cfg->ops->hcmd->set_tx_ant)
2728                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2729
2730         if (iwl_is_associated_ctx(ctx)) {
2731                 struct iwl_rxon_cmd *active_rxon =
2732                                 (struct iwl_rxon_cmd *)&ctx->active;
2733                 /* apply any changes in staging */
2734                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2735                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2736         } else {
2737                 struct iwl_rxon_context *tmp;
2738                 /* Initialize our rx_config data */
2739                 for_each_context(priv, tmp)
2740                         iwl_connection_init_rx_config(priv, tmp);
2741
2742                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2743                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2744         }
2745
2746         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2747             !priv->cfg->bt_params->advanced_bt_coexist)) {
2748                 /*
2749                  * default is 2-wire BT coexexistence support
2750                  */
2751                 priv->cfg->ops->hcmd->send_bt_config(priv);
2752         }
2753
2754         iwl_reset_run_time_calib(priv);
2755
2756         set_bit(STATUS_READY, &priv->status);
2757
2758         /* Configure the adapter for unassociated operation */
2759         iwlcore_commit_rxon(priv, ctx);
2760
2761         /* At this point, the NIC is initialized and operational */
2762         iwl_rf_kill_ct_config(priv);
2763
2764         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2765         wake_up_interruptible(&priv->wait_command_queue);
2766
2767         iwl_power_update_mode(priv, true);
2768         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2769
2770
2771         return;
2772
2773  restart:
2774         queue_work(priv->workqueue, &priv->restart);
2775 }
2776
2777 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2778
2779 static void __iwl_down(struct iwl_priv *priv)
2780 {
2781         unsigned long flags;
2782         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2783
2784         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2785
2786         iwl_scan_cancel_timeout(priv, 200);
2787
2788         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2789
2790         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2791          * to prevent rearm timer */
2792         del_timer_sync(&priv->watchdog);
2793
2794         iwl_clear_ucode_stations(priv, NULL);
2795         iwl_dealloc_bcast_stations(priv);
2796         iwl_clear_driver_stations(priv);
2797
2798         /* reset BT coex data */
2799         priv->bt_status = 0;
2800         if (priv->cfg->bt_params)
2801                 priv->bt_traffic_load =
2802                          priv->cfg->bt_params->bt_init_traffic_load;
2803         else
2804                 priv->bt_traffic_load = 0;
2805         priv->bt_full_concurrent = false;
2806         priv->bt_ci_compliance = 0;
2807
2808         /* Unblock any waiting calls */
2809         wake_up_interruptible_all(&priv->wait_command_queue);
2810
2811         /* Wipe out the EXIT_PENDING status bit if we are not actually
2812          * exiting the module */
2813         if (!exit_pending)
2814                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2815
2816         /* stop and reset the on-board processor */
2817         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2818
2819         /* tell the device to stop sending interrupts */
2820         spin_lock_irqsave(&priv->lock, flags);
2821         iwl_disable_interrupts(priv);
2822         spin_unlock_irqrestore(&priv->lock, flags);
2823         iwl_synchronize_irq(priv);
2824
2825         if (priv->mac80211_registered)
2826                 ieee80211_stop_queues(priv->hw);
2827
2828         /* If we have not previously called iwl_init() then
2829          * clear all bits but the RF Kill bit and return */
2830         if (!iwl_is_init(priv)) {
2831                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2832                                         STATUS_RF_KILL_HW |
2833                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2834                                         STATUS_GEO_CONFIGURED |
2835                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2836                                         STATUS_EXIT_PENDING;
2837                 goto exit;
2838         }
2839
2840         /* ...otherwise clear out all the status bits but the RF Kill
2841          * bit and continue taking the NIC down. */
2842         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2843                                 STATUS_RF_KILL_HW |
2844                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2845                                 STATUS_GEO_CONFIGURED |
2846                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2847                                 STATUS_FW_ERROR |
2848                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2849                                 STATUS_EXIT_PENDING;
2850
2851         /* device going down, Stop using ICT table */
2852         if (priv->cfg->ops->lib->isr_ops.disable)
2853                 priv->cfg->ops->lib->isr_ops.disable(priv);
2854
2855         iwlagn_txq_ctx_stop(priv);
2856         iwlagn_rxq_stop(priv);
2857
2858         /* Power-down device's busmaster DMA clocks */
2859         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2860         udelay(5);
2861
2862         /* Make sure (redundant) we've released our request to stay awake */
2863         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2864
2865         /* Stop the device, and put it in low power state */
2866         iwl_apm_stop(priv);
2867
2868  exit:
2869         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2870
2871         dev_kfree_skb(priv->beacon_skb);
2872         priv->beacon_skb = NULL;
2873
2874         /* clear out any free frames */
2875         iwl_clear_free_frames(priv);
2876 }
2877
2878 static void iwl_down(struct iwl_priv *priv)
2879 {
2880         mutex_lock(&priv->mutex);
2881         __iwl_down(priv);
2882         mutex_unlock(&priv->mutex);
2883
2884         iwl_cancel_deferred_work(priv);
2885 }
2886
2887 #define HW_READY_TIMEOUT (50)
2888
2889 static int iwl_set_hw_ready(struct iwl_priv *priv)
2890 {
2891         int ret = 0;
2892
2893         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2894                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2895
2896         /* See if we got it */
2897         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2898                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2899                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2900                                 HW_READY_TIMEOUT);
2901         if (ret != -ETIMEDOUT)
2902                 priv->hw_ready = true;
2903         else
2904                 priv->hw_ready = false;
2905
2906         IWL_DEBUG_INFO(priv, "hardware %s\n",
2907                       (priv->hw_ready == 1) ? "ready" : "not ready");
2908         return ret;
2909 }
2910
2911 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2912 {
2913         int ret = 0;
2914
2915         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2916
2917         ret = iwl_set_hw_ready(priv);
2918         if (priv->hw_ready)
2919                 return ret;
2920
2921         /* If HW is not ready, prepare the conditions to check again */
2922         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2923                         CSR_HW_IF_CONFIG_REG_PREPARE);
2924
2925         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2926                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2927                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2928
2929         /* HW should be ready by now, check again. */
2930         if (ret != -ETIMEDOUT)
2931                 iwl_set_hw_ready(priv);
2932
2933         return ret;
2934 }
2935
2936 #define MAX_HW_RESTARTS 5
2937
2938 static int __iwl_up(struct iwl_priv *priv)
2939 {
2940         struct iwl_rxon_context *ctx;
2941         int i;
2942         int ret;
2943
2944         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2945                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2946                 return -EIO;
2947         }
2948
2949         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2950                 IWL_ERR(priv, "ucode not available for device bringup\n");
2951                 return -EIO;
2952         }
2953
2954         for_each_context(priv, ctx) {
2955                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2956                 if (ret) {
2957                         iwl_dealloc_bcast_stations(priv);
2958                         return ret;
2959                 }
2960         }
2961
2962         iwl_prepare_card_hw(priv);
2963
2964         if (!priv->hw_ready) {
2965                 IWL_WARN(priv, "Exit HW not ready\n");
2966                 return -EIO;
2967         }
2968
2969         /* If platform's RF_KILL switch is NOT set to KILL */
2970         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2971                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2972         else
2973                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2974
2975         if (iwl_is_rfkill(priv)) {
2976                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2977
2978                 iwl_enable_interrupts(priv);
2979                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2980                 return 0;
2981         }
2982
2983         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2984
2985         /* must be initialised before iwl_hw_nic_init */
2986         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2987                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2988         else
2989                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2990
2991         ret = iwlagn_hw_nic_init(priv);
2992         if (ret) {
2993                 IWL_ERR(priv, "Unable to init nic\n");
2994                 return ret;
2995         }
2996
2997         /* make sure rfkill handshake bits are cleared */
2998         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2999         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3000                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3001
3002         /* clear (again), then enable host interrupts */
3003         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3004         iwl_enable_interrupts(priv);
3005
3006         /* really make sure rfkill handshake bits are cleared */
3007         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3008         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3009
3010         /* Copy original ucode data image from disk into backup cache.
3011          * This will be used to initialize the on-board processor's
3012          * data SRAM for a clean start when the runtime program first loads. */
3013         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3014                priv->ucode_data.len);
3015
3016         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3017
3018                 /* load bootstrap state machine,
3019                  * load bootstrap program into processor's memory,
3020                  * prepare to load the "initialize" uCode */
3021                 ret = priv->cfg->ops->lib->load_ucode(priv);
3022
3023                 if (ret) {
3024                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3025                                 ret);
3026                         continue;
3027                 }
3028
3029                 /* start card; "initialize" will load runtime ucode */
3030                 iwl_nic_start(priv);
3031
3032                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3033
3034                 return 0;
3035         }
3036
3037         set_bit(STATUS_EXIT_PENDING, &priv->status);
3038         __iwl_down(priv);
3039         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3040
3041         /* tried to restart and config the device for as long as our
3042          * patience could withstand */
3043         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3044         return -EIO;
3045 }
3046
3047
3048 /*****************************************************************************
3049  *
3050  * Workqueue callbacks
3051  *
3052  *****************************************************************************/
3053
3054 static void iwl_bg_init_alive_start(struct work_struct *data)
3055 {
3056         struct iwl_priv *priv =
3057             container_of(data, struct iwl_priv, init_alive_start.work);
3058
3059         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3060                 return;
3061
3062         mutex_lock(&priv->mutex);
3063         priv->cfg->ops->lib->init_alive_start(priv);
3064         mutex_unlock(&priv->mutex);
3065 }
3066
3067 static void iwl_bg_alive_start(struct work_struct *data)
3068 {
3069         struct iwl_priv *priv =
3070             container_of(data, struct iwl_priv, alive_start.work);
3071
3072         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3073                 return;
3074
3075         /* enable dram interrupt */
3076         if (priv->cfg->ops->lib->isr_ops.reset)
3077                 priv->cfg->ops->lib->isr_ops.reset(priv);
3078
3079         mutex_lock(&priv->mutex);
3080         iwl_alive_start(priv);
3081         mutex_unlock(&priv->mutex);
3082 }
3083
3084 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3085 {
3086         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3087                         run_time_calib_work);
3088
3089         mutex_lock(&priv->mutex);
3090
3091         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3092             test_bit(STATUS_SCANNING, &priv->status)) {
3093                 mutex_unlock(&priv->mutex);
3094                 return;
3095         }
3096
3097         if (priv->start_calib) {
3098                 if (iwl_bt_statistics(priv)) {
3099                         iwl_chain_noise_calibration(priv,
3100                                         (void *)&priv->_agn.statistics_bt);
3101                         iwl_sensitivity_calibration(priv,
3102                                         (void *)&priv->_agn.statistics_bt);
3103                 } else {
3104                         iwl_chain_noise_calibration(priv,
3105                                         (void *)&priv->_agn.statistics);
3106                         iwl_sensitivity_calibration(priv,
3107                                         (void *)&priv->_agn.statistics);
3108                 }
3109         }
3110
3111         mutex_unlock(&priv->mutex);
3112 }
3113
3114 static void iwl_bg_restart(struct work_struct *data)
3115 {
3116         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3117
3118         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3119                 return;
3120
3121         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3122                 struct iwl_rxon_context *ctx;
3123                 bool bt_full_concurrent;
3124                 u8 bt_ci_compliance;
3125                 u8 bt_load;
3126                 u8 bt_status;
3127
3128                 mutex_lock(&priv->mutex);
3129                 for_each_context(priv, ctx)
3130                         ctx->vif = NULL;
3131                 priv->is_open = 0;
3132
3133                 /*
3134                  * __iwl_down() will clear the BT status variables,
3135                  * which is correct, but when we restart we really
3136                  * want to keep them so restore them afterwards.
3137                  *
3138                  * The restart process will later pick them up and
3139                  * re-configure the hw when we reconfigure the BT
3140                  * command.
3141                  */
3142                 bt_full_concurrent = priv->bt_full_concurrent;
3143                 bt_ci_compliance = priv->bt_ci_compliance;
3144                 bt_load = priv->bt_traffic_load;
3145                 bt_status = priv->bt_status;
3146
3147                 __iwl_down(priv);
3148
3149                 priv->bt_full_concurrent = bt_full_concurrent;
3150                 priv->bt_ci_compliance = bt_ci_compliance;
3151                 priv->bt_traffic_load = bt_load;
3152                 priv->bt_status = bt_status;
3153
3154                 mutex_unlock(&priv->mutex);
3155                 iwl_cancel_deferred_work(priv);
3156                 ieee80211_restart_hw(priv->hw);
3157         } else {
3158                 iwl_down(priv);
3159
3160                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3161                         return;
3162
3163                 mutex_lock(&priv->mutex);
3164                 __iwl_up(priv);
3165                 mutex_unlock(&priv->mutex);
3166         }
3167 }
3168
3169 static void iwl_bg_rx_replenish(struct work_struct *data)
3170 {
3171         struct iwl_priv *priv =
3172             container_of(data, struct iwl_priv, rx_replenish);
3173
3174         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3175                 return;
3176
3177         mutex_lock(&priv->mutex);
3178         iwlagn_rx_replenish(priv);
3179         mutex_unlock(&priv->mutex);
3180 }
3181
3182 /*****************************************************************************
3183  *
3184  * mac80211 entry point functions
3185  *
3186  *****************************************************************************/
3187
3188 #define UCODE_READY_TIMEOUT     (4 * HZ)
3189
3190 /*
3191  * Not a mac80211 entry point function, but it fits in with all the
3192  * other mac80211 functions grouped here.
3193  */
3194 static int iwl_mac_setup_register(struct iwl_priv *priv,
3195                                   struct iwlagn_ucode_capabilities *capa)
3196 {
3197         int ret;
3198         struct ieee80211_hw *hw = priv->hw;
3199         struct iwl_rxon_context *ctx;
3200
3201         hw->rate_control_algorithm = "iwl-agn-rs";
3202
3203         /* Tell mac80211 our characteristics */
3204         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3205                     IEEE80211_HW_AMPDU_AGGREGATION |
3206                     IEEE80211_HW_NEED_DTIM_PERIOD |
3207                     IEEE80211_HW_SPECTRUM_MGMT |
3208                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3209
3210         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3211
3212         if (!priv->cfg->base_params->broken_powersave)
3213                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3214                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3215
3216         if (priv->cfg->sku & IWL_SKU_N)
3217                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3218                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3219
3220         hw->sta_data_size = sizeof(struct iwl_station_priv);
3221         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3222
3223         for_each_context(priv, ctx) {
3224                 hw->wiphy->interface_modes |= ctx->interface_modes;
3225                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3226         }
3227
3228         hw->wiphy->max_remain_on_channel_duration = 1000;
3229
3230         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3231                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
3232                             WIPHY_FLAG_IBSS_RSN;
3233
3234         /*
3235          * For now, disable PS by default because it affects
3236          * RX performance significantly.
3237          */
3238         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3239
3240         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3241         /* we create the 802.11 header and a zero-length SSID element */
3242         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3243
3244         /* Default value; 4 EDCA QOS priorities */
3245         hw->queues = 4;
3246
3247         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3248
3249         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3250                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3251                         &priv->bands[IEEE80211_BAND_2GHZ];
3252         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3253                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3254                         &priv->bands[IEEE80211_BAND_5GHZ];
3255
3256         iwl_leds_init(priv);
3257
3258         ret = ieee80211_register_hw(priv->hw);
3259         if (ret) {
3260                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3261                 return ret;
3262         }
3263         priv->mac80211_registered = 1;
3264
3265         return 0;
3266 }
3267
3268
3269 int iwlagn_mac_start(struct ieee80211_hw *hw)
3270 {
3271         struct iwl_priv *priv = hw->priv;
3272         int ret;
3273
3274         IWL_DEBUG_MAC80211(priv, "enter\n");
3275
3276         /* we should be verifying the device is ready to be opened */
3277         mutex_lock(&priv->mutex);
3278         ret = __iwl_up(priv);
3279         mutex_unlock(&priv->mutex);
3280
3281         if (ret)
3282                 return ret;
3283
3284         if (iwl_is_rfkill(priv))
3285                 goto out;
3286
3287         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3288
3289         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3290          * mac80211 will not be run successfully. */
3291         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3292                         test_bit(STATUS_READY, &priv->status),
3293                         UCODE_READY_TIMEOUT);
3294         if (!ret) {
3295                 if (!test_bit(STATUS_READY, &priv->status)) {
3296                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3297                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3298                         return -ETIMEDOUT;
3299                 }
3300         }
3301
3302         iwlagn_led_enable(priv);
3303
3304 out:
3305         priv->is_open = 1;
3306         IWL_DEBUG_MAC80211(priv, "leave\n");
3307         return 0;
3308 }
3309
3310 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3311 {
3312         struct iwl_priv *priv = hw->priv;
3313
3314         IWL_DEBUG_MAC80211(priv, "enter\n");
3315
3316         if (!priv->is_open)
3317                 return;
3318
3319         priv->is_open = 0;
3320
3321         iwl_down(priv);
3322
3323         flush_workqueue(priv->workqueue);
3324
3325         /* User space software may expect getting rfkill changes
3326          * even if interface is down */
3327         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3328         iwl_enable_rfkill_int(priv);
3329
3330         IWL_DEBUG_MAC80211(priv, "leave\n");
3331 }
3332
3333 void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3334 {
3335         struct iwl_priv *priv = hw->priv;
3336
3337         IWL_DEBUG_MACDUMP(priv, "enter\n");
3338
3339         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3340                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3341
3342         if (iwlagn_tx_skb(priv, skb))
3343                 dev_kfree_skb_any(skb);
3344
3345         IWL_DEBUG_MACDUMP(priv, "leave\n");
3346 }
3347
3348 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3349                                 struct ieee80211_vif *vif,
3350                                 struct ieee80211_key_conf *keyconf,
3351                                 struct ieee80211_sta *sta,
3352                                 u32 iv32, u16 *phase1key)
3353 {
3354         struct iwl_priv *priv = hw->priv;
3355         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3356
3357         IWL_DEBUG_MAC80211(priv, "enter\n");
3358
3359         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3360                             iv32, phase1key);
3361
3362         IWL_DEBUG_MAC80211(priv, "leave\n");
3363 }
3364
3365 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3366                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3367                        struct ieee80211_key_conf *key)
3368 {
3369         struct iwl_priv *priv = hw->priv;
3370         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3371         struct iwl_rxon_context *ctx = vif_priv->ctx;
3372         int ret;
3373         u8 sta_id;
3374         bool is_default_wep_key = false;
3375
3376         IWL_DEBUG_MAC80211(priv, "enter\n");
3377
3378         if (priv->cfg->mod_params->sw_crypto) {
3379                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3380                 return -EOPNOTSUPP;
3381         }
3382
3383         /*
3384          * To support IBSS RSN, don't program group keys in IBSS, the
3385          * hardware will then not attempt to decrypt the frames.
3386          */
3387         if (vif->type == NL80211_IFTYPE_ADHOC &&
3388             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3389                 return -EOPNOTSUPP;
3390
3391         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3392         if (sta_id == IWL_INVALID_STATION)
3393                 return -EINVAL;
3394
3395         mutex_lock(&priv->mutex);
3396         iwl_scan_cancel_timeout(priv, 100);
3397
3398         /*
3399          * If we are getting WEP group key and we didn't receive any key mapping
3400          * so far, we are in legacy wep mode (group key only), otherwise we are
3401          * in 1X mode.
3402          * In legacy wep mode, we use another host command to the uCode.
3403          */
3404         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3405              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3406             !sta) {
3407                 if (cmd == SET_KEY)
3408                         is_default_wep_key = !ctx->key_mapping_keys;
3409                 else
3410                         is_default_wep_key =
3411                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3412         }
3413
3414         switch (cmd) {
3415         case SET_KEY:
3416                 if (is_default_wep_key)
3417                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3418                 else
3419                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3420                                                   key, sta_id);
3421
3422                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3423                 break;
3424         case DISABLE_KEY:
3425                 if (is_default_wep_key)
3426                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3427                 else
3428                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3429
3430                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3431                 break;
3432         default:
3433                 ret = -EINVAL;
3434         }
3435
3436         mutex_unlock(&priv->mutex);
3437         IWL_DEBUG_MAC80211(priv, "leave\n");
3438
3439         return ret;
3440 }
3441
3442 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3443                             struct ieee80211_vif *vif,
3444                             enum ieee80211_ampdu_mlme_action action,
3445                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3446                             u8 buf_size)
3447 {
3448         struct iwl_priv *priv = hw->priv;
3449         int ret = -EINVAL;
3450         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3451
3452         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3453                      sta->addr, tid);
3454
3455         if (!(priv->cfg->sku & IWL_SKU_N))
3456                 return -EACCES;
3457
3458         mutex_lock(&priv->mutex);
3459
3460         switch (action) {
3461         case IEEE80211_AMPDU_RX_START:
3462                 IWL_DEBUG_HT(priv, "start Rx\n");
3463                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3464                 break;
3465         case IEEE80211_AMPDU_RX_STOP:
3466                 IWL_DEBUG_HT(priv, "stop Rx\n");
3467                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3468                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3469                         ret = 0;
3470                 break;
3471         case IEEE80211_AMPDU_TX_START:
3472                 IWL_DEBUG_HT(priv, "start Tx\n");
3473                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3474                 if (ret == 0) {
3475                         priv->_agn.agg_tids_count++;
3476                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3477                                      priv->_agn.agg_tids_count);
3478                 }
3479                 break;
3480         case IEEE80211_AMPDU_TX_STOP:
3481                 IWL_DEBUG_HT(priv, "stop Tx\n");
3482                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3483                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3484                         priv->_agn.agg_tids_count--;
3485                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3486                                      priv->_agn.agg_tids_count);
3487                 }
3488                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3489                         ret = 0;
3490                 if (priv->cfg->ht_params &&
3491                     priv->cfg->ht_params->use_rts_for_aggregation) {
3492                         struct iwl_station_priv *sta_priv =
3493                                 (void *) sta->drv_priv;
3494                         /*
3495                          * switch off RTS/CTS if it was previously enabled
3496                          */
3497
3498                         sta_priv->lq_sta.lq.general_params.flags &=
3499                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3500                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3501                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3502                 }
3503                 break;
3504         case IEEE80211_AMPDU_TX_OPERATIONAL:
3505                 /*
3506                  * If the limit is 0, then it wasn't initialised yet,
3507                  * use the default. We can do that since we take the
3508                  * minimum below, and we don't want to go above our
3509                  * default due to hardware restrictions.
3510                  */
3511                 if (sta_priv->max_agg_bufsize == 0)
3512                         sta_priv->max_agg_bufsize =
3513                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3514
3515                 /*
3516                  * Even though in theory the peer could have different
3517                  * aggregation reorder buffer sizes for different sessions,
3518                  * our ucode doesn't allow for that and has a global limit
3519                  * for each station. Therefore, use the minimum of all the
3520                  * aggregation sessions and our default value.
3521                  */
3522                 sta_priv->max_agg_bufsize =
3523                         min(sta_priv->max_agg_bufsize, buf_size);
3524
3525                 if (priv->cfg->ht_params &&
3526                     priv->cfg->ht_params->use_rts_for_aggregation) {
3527                         /*
3528                          * switch to RTS/CTS if it is the prefer protection
3529                          * method for HT traffic
3530                          */
3531
3532                         sta_priv->lq_sta.lq.general_params.flags |=
3533                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3534                 }
3535
3536                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3537                         sta_priv->max_agg_bufsize;
3538
3539                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3540                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3541                 ret = 0;
3542                 break;
3543         }
3544         mutex_unlock(&priv->mutex);
3545
3546         return ret;
3547 }
3548
3549 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3550                        struct ieee80211_vif *vif,
3551                        struct ieee80211_sta *sta)
3552 {
3553         struct iwl_priv *priv = hw->priv;
3554         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3555         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3556         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3557         int ret;
3558         u8 sta_id;
3559
3560         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3561                         sta->addr);
3562         mutex_lock(&priv->mutex);
3563         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3564                         sta->addr);
3565         sta_priv->common.sta_id = IWL_INVALID_STATION;
3566
3567         atomic_set(&sta_priv->pending_frames, 0);
3568         if (vif->type == NL80211_IFTYPE_AP)
3569                 sta_priv->client = true;
3570
3571         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3572                                      is_ap, sta, &sta_id);
3573         if (ret) {
3574                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3575                         sta->addr, ret);
3576                 /* Should we return success if return code is EEXIST ? */
3577                 mutex_unlock(&priv->mutex);
3578                 return ret;
3579         }
3580
3581         sta_priv->common.sta_id = sta_id;
3582
3583         /* Initialize rate scaling */
3584         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3585                        sta->addr);
3586         iwl_rs_rate_init(priv, sta, sta_id);
3587         mutex_unlock(&priv->mutex);
3588
3589         return 0;
3590 }
3591
3592 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3593                                struct ieee80211_channel_switch *ch_switch)
3594 {
3595         struct iwl_priv *priv = hw->priv;
3596         const struct iwl_channel_info *ch_info;
3597         struct ieee80211_conf *conf = &hw->conf;
3598         struct ieee80211_channel *channel = ch_switch->channel;
3599         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3600         /*
3601          * MULTI-FIXME
3602          * When we add support for multiple interfaces, we need to
3603          * revisit this. The channel switch command in the device
3604          * only affects the BSS context, but what does that really
3605          * mean? And what if we get a CSA on the second interface?
3606          * This needs a lot of work.
3607          */
3608         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3609         u16 ch;
3610         unsigned long flags = 0;
3611
3612         IWL_DEBUG_MAC80211(priv, "enter\n");
3613
3614         if (iwl_is_rfkill(priv))
3615                 goto out_exit;
3616
3617         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3618             test_bit(STATUS_SCANNING, &priv->status))
3619                 goto out_exit;
3620
3621         if (!iwl_is_associated_ctx(ctx))
3622                 goto out_exit;
3623
3624         /* channel switch in progress */
3625         if (priv->switch_rxon.switch_in_progress == true)
3626                 goto out_exit;
3627
3628         mutex_lock(&priv->mutex);
3629         if (priv->cfg->ops->lib->set_channel_switch) {
3630
3631                 ch = channel->hw_value;
3632                 if (le16_to_cpu(ctx->active.channel) != ch) {
3633                         ch_info = iwl_get_channel_info(priv,
3634                                                        channel->band,
3635                                                        ch);
3636                         if (!is_channel_valid(ch_info)) {
3637                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3638                                 goto out;
3639                         }
3640                         spin_lock_irqsave(&priv->lock, flags);
3641
3642                         priv->current_ht_config.smps = conf->smps_mode;
3643
3644                         /* Configure HT40 channels */
3645                         ctx->ht.enabled = conf_is_ht(conf);
3646                         if (ctx->ht.enabled) {
3647                                 if (conf_is_ht40_minus(conf)) {
3648                                         ctx->ht.extension_chan_offset =
3649                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3650                                         ctx->ht.is_40mhz = true;
3651                                 } else if (conf_is_ht40_plus(conf)) {
3652                                         ctx->ht.extension_chan_offset =
3653                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3654                                         ctx->ht.is_40mhz = true;
3655                                 } else {
3656                                         ctx->ht.extension_chan_offset =
3657                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3658                                         ctx->ht.is_40mhz = false;
3659                                 }
3660                         } else
3661                                 ctx->ht.is_40mhz = false;
3662
3663                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3664                                 ctx->staging.flags = 0;
3665
3666                         iwl_set_rxon_channel(priv, channel, ctx);
3667                         iwl_set_rxon_ht(priv, ht_conf);
3668                         iwl_set_flags_for_band(priv, ctx, channel->band,
3669                                                ctx->vif);
3670                         spin_unlock_irqrestore(&priv->lock, flags);
3671
3672                         iwl_set_rate(priv);
3673                         /*
3674                          * at this point, staging_rxon has the
3675                          * configuration for channel switch
3676                          */
3677                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3678                                                                     ch_switch))
3679                                 priv->switch_rxon.switch_in_progress = false;
3680                 }
3681         }
3682 out:
3683         mutex_unlock(&priv->mutex);
3684 out_exit:
3685         if (!priv->switch_rxon.switch_in_progress)
3686                 ieee80211_chswitch_done(ctx->vif, false);
3687         IWL_DEBUG_MAC80211(priv, "leave\n");
3688 }
3689
3690 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3691                              unsigned int changed_flags,
3692                              unsigned int *total_flags,
3693                              u64 multicast)
3694 {
3695         struct iwl_priv *priv = hw->priv;
3696         __le32 filter_or = 0, filter_nand = 0;
3697         struct iwl_rxon_context *ctx;
3698
3699 #define CHK(test, flag) do { \
3700         if (*total_flags & (test))              \
3701                 filter_or |= (flag);            \
3702         else                                    \
3703                 filter_nand |= (flag);          \
3704         } while (0)
3705
3706         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3707                         changed_flags, *total_flags);
3708
3709         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3710         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3711         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3712         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3713
3714 #undef CHK
3715
3716         mutex_lock(&priv->mutex);
3717
3718         for_each_context(priv, ctx) {
3719                 ctx->staging.filter_flags &= ~filter_nand;
3720                 ctx->staging.filter_flags |= filter_or;
3721
3722                 /*
3723                  * Not committing directly because hardware can perform a scan,
3724                  * but we'll eventually commit the filter flags change anyway.
3725                  */
3726         }
3727
3728         mutex_unlock(&priv->mutex);
3729
3730         /*
3731          * Receiving all multicast frames is always enabled by the
3732          * default flags setup in iwl_connection_init_rx_config()
3733          * since we currently do not support programming multicast
3734          * filters into the device.
3735          */
3736         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3737                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3738 }
3739
3740 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3741 {
3742         struct iwl_priv *priv = hw->priv;
3743
3744         mutex_lock(&priv->mutex);
3745         IWL_DEBUG_MAC80211(priv, "enter\n");
3746
3747         /* do not support "flush" */
3748         if (!priv->cfg->ops->lib->txfifo_flush)
3749                 goto done;
3750
3751         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3752                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3753                 goto done;
3754         }
3755         if (iwl_is_rfkill(priv)) {
3756                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3757                 goto done;
3758         }
3759
3760         /*
3761          * mac80211 will not push any more frames for transmit
3762          * until the flush is completed
3763          */
3764         if (drop) {
3765                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3766                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3767                         IWL_ERR(priv, "flush request fail\n");
3768                         goto done;
3769                 }
3770         }
3771         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3772         iwlagn_wait_tx_queue_empty(priv);
3773 done:
3774         mutex_unlock(&priv->mutex);
3775         IWL_DEBUG_MAC80211(priv, "leave\n");
3776 }
3777
3778 static void iwlagn_disable_roc(struct iwl_priv *priv)
3779 {
3780         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3781         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3782
3783         lockdep_assert_held(&priv->mutex);
3784
3785         if (!ctx->is_active)
3786                 return;
3787
3788         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3789         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3790         iwl_set_rxon_channel(priv, chan, ctx);
3791         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3792
3793         priv->_agn.hw_roc_channel = NULL;
3794
3795         iwlcore_commit_rxon(priv, ctx);
3796
3797         ctx->is_active = false;
3798 }
3799
3800 static void iwlagn_bg_roc_done(struct work_struct *work)
3801 {
3802         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3803                                              _agn.hw_roc_work.work);
3804
3805         mutex_lock(&priv->mutex);
3806         ieee80211_remain_on_channel_expired(priv->hw);
3807         iwlagn_disable_roc(priv);
3808         mutex_unlock(&priv->mutex);
3809 }
3810
3811 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3812                                      struct ieee80211_channel *channel,
3813                                      enum nl80211_channel_type channel_type,
3814                                      int duration)
3815 {
3816         struct iwl_priv *priv = hw->priv;
3817         int err = 0;
3818
3819         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3820                 return -EOPNOTSUPP;
3821
3822         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3823                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3824                 return -EOPNOTSUPP;
3825
3826         mutex_lock(&priv->mutex);
3827
3828         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3829             test_bit(STATUS_SCAN_HW, &priv->status)) {
3830                 err = -EBUSY;
3831                 goto out;
3832         }
3833
3834         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3835         priv->_agn.hw_roc_channel = channel;
3836         priv->_agn.hw_roc_chantype = channel_type;
3837         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3838         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3839         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3840                            msecs_to_jiffies(duration + 20));
3841
3842         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3843         ieee80211_ready_on_channel(priv->hw);
3844
3845  out:
3846         mutex_unlock(&priv->mutex);
3847
3848         return err;
3849 }
3850
3851 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3852 {
3853         struct iwl_priv *priv = hw->priv;
3854
3855         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3856                 return -EOPNOTSUPP;
3857
3858         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3859
3860         mutex_lock(&priv->mutex);
3861         iwlagn_disable_roc(priv);
3862         mutex_unlock(&priv->mutex);
3863
3864         return 0;
3865 }
3866
3867 /*****************************************************************************
3868  *
3869  * driver setup and teardown
3870  *
3871  *****************************************************************************/
3872
3873 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3874 {
3875         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3876
3877         init_waitqueue_head(&priv->wait_command_queue);
3878
3879         INIT_WORK(&priv->restart, iwl_bg_restart);
3880         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3881         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3882         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3883         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3884         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3885         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3886         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3887         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3888         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3889
3890         iwl_setup_scan_deferred_work(priv);
3891
3892         if (priv->cfg->ops->lib->setup_deferred_work)
3893                 priv->cfg->ops->lib->setup_deferred_work(priv);
3894
3895         init_timer(&priv->statistics_periodic);
3896         priv->statistics_periodic.data = (unsigned long)priv;
3897         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3898
3899         init_timer(&priv->ucode_trace);
3900         priv->ucode_trace.data = (unsigned long)priv;
3901         priv->ucode_trace.function = iwl_bg_ucode_trace;
3902
3903         init_timer(&priv->watchdog);
3904         priv->watchdog.data = (unsigned long)priv;
3905         priv->watchdog.function = iwl_bg_watchdog;
3906
3907         if (!priv->cfg->base_params->use_isr_legacy)
3908                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3909                         iwl_irq_tasklet, (unsigned long)priv);
3910         else
3911                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3912                         iwl_irq_tasklet_legacy, (unsigned long)priv);
3913 }
3914
3915 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3916 {
3917         if (priv->cfg->ops->lib->cancel_deferred_work)
3918                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3919
3920         cancel_delayed_work_sync(&priv->init_alive_start);
3921         cancel_delayed_work(&priv->alive_start);
3922         cancel_work_sync(&priv->run_time_calib_work);
3923         cancel_work_sync(&priv->beacon_update);
3924
3925         iwl_cancel_scan_deferred_work(priv);
3926
3927         cancel_work_sync(&priv->bt_full_concurrency);
3928         cancel_work_sync(&priv->bt_runtime_config);
3929
3930         del_timer_sync(&priv->statistics_periodic);
3931         del_timer_sync(&priv->ucode_trace);
3932 }
3933
3934 static void iwl_init_hw_rates(struct iwl_priv *priv,
3935                               struct ieee80211_rate *rates)
3936 {
3937         int i;
3938
3939         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3940                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3941                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3942                 rates[i].hw_value_short = i;
3943                 rates[i].flags = 0;
3944                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3945                         /*
3946                          * If CCK != 1M then set short preamble rate flag.
3947                          */
3948                         rates[i].flags |=
3949                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3950                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3951                 }
3952         }
3953 }
3954
3955 static int iwl_init_drv(struct iwl_priv *priv)
3956 {
3957         int ret;
3958
3959         spin_lock_init(&priv->sta_lock);
3960         spin_lock_init(&priv->hcmd_lock);
3961
3962         INIT_LIST_HEAD(&priv->free_frames);
3963
3964         mutex_init(&priv->mutex);
3965         mutex_init(&priv->sync_cmd_mutex);
3966
3967         priv->ieee_channels = NULL;
3968         priv->ieee_rates = NULL;
3969         priv->band = IEEE80211_BAND_2GHZ;
3970
3971         priv->iw_mode = NL80211_IFTYPE_STATION;
3972         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3973         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3974         priv->_agn.agg_tids_count = 0;
3975
3976         /* initialize force reset */
3977         priv->force_reset[IWL_RF_RESET].reset_duration =
3978                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3979         priv->force_reset[IWL_FW_RESET].reset_duration =
3980                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3981
3982         /* Choose which receivers/antennas to use */
3983         if (priv->cfg->ops->hcmd->set_rxon_chain)
3984                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3985                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3986
3987         iwl_init_scan_params(priv);
3988
3989         /* init bt coex */
3990         if (priv->cfg->bt_params &&
3991             priv->cfg->bt_params->advanced_bt_coexist) {
3992                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3993                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3994                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3995                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3996                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3997                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3998         }
3999
4000         /* Set the tx_power_user_lmt to the lowest power level
4001          * this value will get overwritten by channel max power avg
4002          * from eeprom */
4003         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4004         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4005
4006         ret = iwl_init_channel_map(priv);
4007         if (ret) {
4008                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4009                 goto err;
4010         }
4011
4012         ret = iwlcore_init_geos(priv);
4013         if (ret) {
4014                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4015                 goto err_free_channel_map;
4016         }
4017         iwl_init_hw_rates(priv, priv->ieee_rates);
4018
4019         return 0;
4020
4021 err_free_channel_map:
4022         iwl_free_channel_map(priv);
4023 err:
4024         return ret;
4025 }
4026
4027 static void iwl_uninit_drv(struct iwl_priv *priv)
4028 {
4029         iwl_calib_free_results(priv);
4030         iwlcore_free_geos(priv);
4031         iwl_free_channel_map(priv);
4032         kfree(priv->scan_cmd);
4033 }
4034
4035 struct ieee80211_ops iwlagn_hw_ops = {
4036         .tx = iwlagn_mac_tx,
4037         .start = iwlagn_mac_start,
4038         .stop = iwlagn_mac_stop,
4039         .add_interface = iwl_mac_add_interface,
4040         .remove_interface = iwl_mac_remove_interface,
4041         .change_interface = iwl_mac_change_interface,
4042         .config = iwlagn_mac_config,
4043         .configure_filter = iwlagn_configure_filter,
4044         .set_key = iwlagn_mac_set_key,
4045         .update_tkip_key = iwlagn_mac_update_tkip_key,
4046         .conf_tx = iwl_mac_conf_tx,
4047         .bss_info_changed = iwlagn_bss_info_changed,
4048         .ampdu_action = iwlagn_mac_ampdu_action,
4049         .hw_scan = iwl_mac_hw_scan,
4050         .sta_notify = iwlagn_mac_sta_notify,
4051         .sta_add = iwlagn_mac_sta_add,
4052         .sta_remove = iwl_mac_sta_remove,
4053         .channel_switch = iwlagn_mac_channel_switch,
4054         .flush = iwlagn_mac_flush,
4055         .tx_last_beacon = iwl_mac_tx_last_beacon,
4056         .remain_on_channel = iwl_mac_remain_on_channel,
4057         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
4058 };
4059
4060 static void iwl_hw_detect(struct iwl_priv *priv)
4061 {
4062         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4063         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4064         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4065         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4066 }
4067
4068 static int iwl_set_hw_params(struct iwl_priv *priv)
4069 {
4070         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4071         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4072         if (priv->cfg->mod_params->amsdu_size_8K)
4073                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4074         else
4075                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4076
4077         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4078
4079         if (priv->cfg->mod_params->disable_11n)
4080                 priv->cfg->sku &= ~IWL_SKU_N;
4081
4082         /* Device-specific setup */
4083         return priv->cfg->ops->lib->set_hw_params(priv);
4084 }
4085
4086 static const u8 iwlagn_bss_ac_to_fifo[] = {
4087         IWL_TX_FIFO_VO,
4088         IWL_TX_FIFO_VI,
4089         IWL_TX_FIFO_BE,
4090         IWL_TX_FIFO_BK,
4091 };
4092
4093 static const u8 iwlagn_bss_ac_to_queue[] = {
4094         0, 1, 2, 3,
4095 };
4096
4097 static const u8 iwlagn_pan_ac_to_fifo[] = {
4098         IWL_TX_FIFO_VO_IPAN,
4099         IWL_TX_FIFO_VI_IPAN,
4100         IWL_TX_FIFO_BE_IPAN,
4101         IWL_TX_FIFO_BK_IPAN,
4102 };
4103
4104 static const u8 iwlagn_pan_ac_to_queue[] = {
4105         7, 6, 5, 4,
4106 };
4107
4108 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4109 {
4110         int err = 0, i;
4111         struct iwl_priv *priv;
4112         struct ieee80211_hw *hw;
4113         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4114         unsigned long flags;
4115         u16 pci_cmd, num_mac;
4116
4117         /************************
4118          * 1. Allocating HW data
4119          ************************/
4120
4121         /* Disabling hardware scan means that mac80211 will perform scans
4122          * "the hard way", rather than using device's scan. */
4123         if (cfg->mod_params->disable_hw_scan) {
4124                 dev_printk(KERN_DEBUG, &(pdev->dev),
4125                         "sw scan support is deprecated\n");
4126                 iwlagn_hw_ops.hw_scan = NULL;
4127         }
4128
4129         hw = iwl_alloc_all(cfg);
4130         if (!hw) {
4131                 err = -ENOMEM;
4132                 goto out;
4133         }
4134         priv = hw->priv;
4135         /* At this point both hw and priv are allocated. */
4136
4137         /*
4138          * The default context is always valid,
4139          * more may be discovered when firmware
4140          * is loaded.
4141          */
4142         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4143
4144         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4145                 priv->contexts[i].ctxid = i;
4146
4147         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4148         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4149         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4150         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4151         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4152         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4153         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4154         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4155         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4156         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4157         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4158                 BIT(NL80211_IFTYPE_ADHOC);
4159         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4160                 BIT(NL80211_IFTYPE_STATION);
4161         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4162         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4163         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4164         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4165
4166         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4167         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4168         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4169         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4170         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4171         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4172         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4173         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4174         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4175         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4176         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4177         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4178                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4179 #ifdef CONFIG_IWL_P2P
4180         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
4181                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
4182 #endif
4183         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4184         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4185         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4186
4187         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4188
4189         SET_IEEE80211_DEV(hw, &pdev->dev);
4190
4191         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4192         priv->cfg = cfg;
4193         priv->pci_dev = pdev;
4194         priv->inta_mask = CSR_INI_SET_MASK;
4195
4196         /* is antenna coupling more than 35dB ? */
4197         priv->bt_ant_couple_ok =
4198                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4199                 true : false;
4200
4201         /* enable/disable bt channel inhibition */
4202         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4203         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4204                        (priv->bt_ch_announce) ? "On" : "Off");
4205
4206         if (iwl_alloc_traffic_mem(priv))
4207                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4208
4209         /**************************
4210          * 2. Initializing PCI bus
4211          **************************/
4212         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4213                                 PCIE_LINK_STATE_CLKPM);
4214
4215         if (pci_enable_device(pdev)) {
4216                 err = -ENODEV;
4217                 goto out_ieee80211_free_hw;
4218         }
4219
4220         pci_set_master(pdev);
4221
4222         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4223         if (!err)
4224                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4225         if (err) {
4226                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4227                 if (!err)
4228                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4229                 /* both attempts failed: */
4230                 if (err) {
4231                         IWL_WARN(priv, "No suitable DMA available.\n");
4232                         goto out_pci_disable_device;
4233                 }
4234         }
4235
4236         err = pci_request_regions(pdev, DRV_NAME);
4237         if (err)
4238                 goto out_pci_disable_device;
4239
4240         pci_set_drvdata(pdev, priv);
4241
4242
4243         /***********************
4244          * 3. Read REV register
4245          ***********************/
4246         priv->hw_base = pci_iomap(pdev, 0, 0);
4247         if (!priv->hw_base) {
4248                 err = -ENODEV;
4249                 goto out_pci_release_regions;
4250         }
4251
4252         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4253                 (unsigned long long) pci_resource_len(pdev, 0));
4254         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4255
4256         /* these spin locks will be used in apm_ops.init and EEPROM access
4257          * we should init now
4258          */
4259         spin_lock_init(&priv->reg_lock);
4260         spin_lock_init(&priv->lock);
4261
4262         /*
4263          * stop and reset the on-board processor just in case it is in a
4264          * strange state ... like being left stranded by a primary kernel
4265          * and this is now the kdump kernel trying to start up
4266          */
4267         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4268
4269         iwl_hw_detect(priv);
4270         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4271                 priv->cfg->name, priv->hw_rev);
4272
4273         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4274          * PCI Tx retries from interfering with C3 CPU state */
4275         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4276
4277         iwl_prepare_card_hw(priv);
4278         if (!priv->hw_ready) {
4279                 IWL_WARN(priv, "Failed, HW not ready\n");
4280                 goto out_iounmap;
4281         }
4282
4283         /*****************
4284          * 4. Read EEPROM
4285          *****************/
4286         /* Read the EEPROM */
4287         err = iwl_eeprom_init(priv);
4288         if (err) {
4289                 IWL_ERR(priv, "Unable to init EEPROM\n");
4290                 goto out_iounmap;
4291         }
4292         err = iwl_eeprom_check_version(priv);
4293         if (err)
4294                 goto out_free_eeprom;
4295
4296         err = iwl_eeprom_check_sku(priv);
4297         if (err)
4298                 goto out_free_eeprom;
4299
4300         /* extract MAC Address */
4301         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4302         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4303         priv->hw->wiphy->addresses = priv->addresses;
4304         priv->hw->wiphy->n_addresses = 1;
4305         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4306         if (num_mac > 1) {
4307                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4308                        ETH_ALEN);
4309                 priv->addresses[1].addr[5]++;
4310                 priv->hw->wiphy->n_addresses++;
4311         }
4312
4313         /************************
4314          * 5. Setup HW constants
4315          ************************/
4316         if (iwl_set_hw_params(priv)) {
4317                 IWL_ERR(priv, "failed to set hw parameters\n");
4318                 goto out_free_eeprom;
4319         }
4320
4321         /*******************
4322          * 6. Setup priv
4323          *******************/
4324
4325         err = iwl_init_drv(priv);
4326         if (err)
4327                 goto out_free_eeprom;
4328         /* At this point both hw and priv are initialized. */
4329
4330         /********************
4331          * 7. Setup services
4332          ********************/
4333         spin_lock_irqsave(&priv->lock, flags);
4334         iwl_disable_interrupts(priv);
4335         spin_unlock_irqrestore(&priv->lock, flags);
4336
4337         pci_enable_msi(priv->pci_dev);
4338
4339         if (priv->cfg->ops->lib->isr_ops.alloc)
4340                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4341
4342         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4343                           IRQF_SHARED, DRV_NAME, priv);
4344         if (err) {
4345                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4346                 goto out_disable_msi;
4347         }
4348
4349         iwl_setup_deferred_work(priv);
4350         iwl_setup_rx_handlers(priv);
4351
4352         /*********************************************
4353          * 8. Enable interrupts and read RFKILL state
4354          *********************************************/
4355
4356         /* enable rfkill interrupt: hw bug w/a */
4357         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4358         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4359                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4360                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4361         }
4362
4363         iwl_enable_rfkill_int(priv);
4364
4365         /* If platform's RF_KILL switch is NOT set to KILL */
4366         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4367                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4368         else
4369                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4370
4371         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4372                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4373
4374         iwl_power_initialize(priv);
4375         iwl_tt_initialize(priv);
4376
4377         init_completion(&priv->_agn.firmware_loading_complete);
4378
4379         err = iwl_request_firmware(priv, true);
4380         if (err)
4381                 goto out_destroy_workqueue;
4382
4383         return 0;
4384
4385  out_destroy_workqueue:
4386         destroy_workqueue(priv->workqueue);
4387         priv->workqueue = NULL;
4388         free_irq(priv->pci_dev->irq, priv);
4389         if (priv->cfg->ops->lib->isr_ops.free)
4390                 priv->cfg->ops->lib->isr_ops.free(priv);
4391  out_disable_msi:
4392         pci_disable_msi(priv->pci_dev);
4393         iwl_uninit_drv(priv);
4394  out_free_eeprom:
4395         iwl_eeprom_free(priv);
4396  out_iounmap:
4397         pci_iounmap(pdev, priv->hw_base);
4398  out_pci_release_regions:
4399         pci_set_drvdata(pdev, NULL);
4400         pci_release_regions(pdev);
4401  out_pci_disable_device:
4402         pci_disable_device(pdev);
4403  out_ieee80211_free_hw:
4404         iwl_free_traffic_mem(priv);
4405         ieee80211_free_hw(priv->hw);
4406  out:
4407         return err;
4408 }
4409
4410 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4411 {
4412         struct iwl_priv *priv = pci_get_drvdata(pdev);
4413         unsigned long flags;
4414
4415         if (!priv)
4416                 return;
4417
4418         wait_for_completion(&priv->_agn.firmware_loading_complete);
4419
4420         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4421
4422         iwl_dbgfs_unregister(priv);
4423         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4424
4425         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4426          * to be called and iwl_down since we are removing the device
4427          * we need to set STATUS_EXIT_PENDING bit.
4428          */
4429         set_bit(STATUS_EXIT_PENDING, &priv->status);
4430
4431         iwl_leds_exit(priv);
4432
4433         if (priv->mac80211_registered) {
4434                 ieee80211_unregister_hw(priv->hw);
4435                 priv->mac80211_registered = 0;
4436         } else {
4437                 iwl_down(priv);
4438         }
4439
4440         /*
4441          * Make sure device is reset to low power before unloading driver.
4442          * This may be redundant with iwl_down(), but there are paths to
4443          * run iwl_down() without calling apm_ops.stop(), and there are
4444          * paths to avoid running iwl_down() at all before leaving driver.
4445          * This (inexpensive) call *makes sure* device is reset.
4446          */
4447         iwl_apm_stop(priv);
4448
4449         iwl_tt_exit(priv);
4450
4451         /* make sure we flush any pending irq or
4452          * tasklet for the driver
4453          */
4454         spin_lock_irqsave(&priv->lock, flags);
4455         iwl_disable_interrupts(priv);
4456         spin_unlock_irqrestore(&priv->lock, flags);
4457
4458         iwl_synchronize_irq(priv);
4459
4460         iwl_dealloc_ucode_pci(priv);
4461
4462         if (priv->rxq.bd)
4463                 iwlagn_rx_queue_free(priv, &priv->rxq);
4464         iwlagn_hw_txq_ctx_free(priv);
4465
4466         iwl_eeprom_free(priv);
4467
4468
4469         /*netif_stop_queue(dev); */
4470         flush_workqueue(priv->workqueue);
4471
4472         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4473          * priv->workqueue... so we can't take down the workqueue
4474          * until now... */
4475         destroy_workqueue(priv->workqueue);
4476         priv->workqueue = NULL;
4477         iwl_free_traffic_mem(priv);
4478
4479         free_irq(priv->pci_dev->irq, priv);
4480         pci_disable_msi(priv->pci_dev);
4481         pci_iounmap(pdev, priv->hw_base);
4482         pci_release_regions(pdev);
4483         pci_disable_device(pdev);
4484         pci_set_drvdata(pdev, NULL);
4485
4486         iwl_uninit_drv(priv);
4487
4488         if (priv->cfg->ops->lib->isr_ops.free)
4489                 priv->cfg->ops->lib->isr_ops.free(priv);
4490
4491         dev_kfree_skb(priv->beacon_skb);
4492
4493         ieee80211_free_hw(priv->hw);
4494 }
4495
4496
4497 /*****************************************************************************
4498  *
4499  * driver and module entry point
4500  *
4501  *****************************************************************************/
4502
4503 /* Hardware specific file defines the PCI IDs table for that hardware module */
4504 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4505         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4506         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4507         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4508         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4509         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4510         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4511         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4512         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4513         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4514         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4515         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4516         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4517         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4518         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4519         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4520         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4521         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4522         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4523         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4524         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4525         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4526         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4527         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4528         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4529
4530 /* 5300 Series WiFi */
4531         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4532         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4533         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4534         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4535         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4536         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4537         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4538         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4539         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4540         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4541         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4542         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4543
4544 /* 5350 Series WiFi/WiMax */
4545         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4546         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4547         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4548
4549 /* 5150 Series Wifi/WiMax */
4550         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4551         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4552         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4553         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4554         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4555         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4556
4557         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4558         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4559         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4560         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4561
4562 /* 6x00 Series */
4563         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4564         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4565         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4566         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4567         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4568         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4569         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4570         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4571         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4572         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4573
4574 /* 6x05 Series */
4575         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4576         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4577         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4578         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4579         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4580         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4581         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4582
4583 /* 6x30 Series */
4584         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4585         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4586         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4587         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4588         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4589         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4590         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4591         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4592         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4593         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4594         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4595         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4596         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4597         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4598         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4599         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4600
4601 /* 6x50 WiFi/WiMax Series */
4602         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4603         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4604         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4605         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4606         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4607         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4608
4609 /* 6150 WiFi/WiMax Series */
4610         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4611         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4612         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4613         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4614         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4615         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4616
4617 /* 1000 Series WiFi */
4618         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4619         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4620         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4621         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4622         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4623         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4624         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4625         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4626         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4627         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4628         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4629         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4630
4631 /* 100 Series WiFi */
4632         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4633         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4634         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4635         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4636         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4637         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4638
4639 /* 130 Series WiFi */
4640         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4641         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4642         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4643         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4644         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4645         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4646
4647 /* 2x00 Series */
4648         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4649         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4650         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4651         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4652         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4653         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4654
4655 /* 2x30 Series */
4656         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4657         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4658         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4659         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4660         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4661         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4662
4663 /* 6x35 Series */
4664         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4665         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4666         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4667         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4668         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4669         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4670         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4671         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4672         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4673
4674 /* 200 Series */
4675         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4676         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4677         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4678         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4679         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4680         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4681
4682 /* 230 Series */
4683         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4684         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4685         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4686         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4687         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4688         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4689
4690         {0}
4691 };
4692 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4693
4694 static struct pci_driver iwl_driver = {
4695         .name = DRV_NAME,
4696         .id_table = iwl_hw_card_ids,
4697         .probe = iwl_pci_probe,
4698         .remove = __devexit_p(iwl_pci_remove),
4699         .driver.pm = IWL_PM_OPS,
4700 };
4701
4702 static int __init iwl_init(void)
4703 {
4704
4705         int ret;
4706         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4707         pr_info(DRV_COPYRIGHT "\n");
4708
4709         ret = iwlagn_rate_control_register();
4710         if (ret) {
4711                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4712                 return ret;
4713         }
4714
4715         ret = pci_register_driver(&iwl_driver);
4716         if (ret) {
4717                 pr_err("Unable to initialize PCI module\n");
4718                 goto error_register;
4719         }
4720
4721         return ret;
4722
4723 error_register:
4724         iwlagn_rate_control_unregister();
4725         return ret;
4726 }
4727
4728 static void __exit iwl_exit(void)
4729 {
4730         pci_unregister_driver(&iwl_driver);
4731         iwlagn_rate_control_unregister();
4732 }
4733
4734 module_exit(iwl_exit);
4735 module_init(iwl_init);
4736
4737 #ifdef CONFIG_IWLWIFI_DEBUG
4738 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4739 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4740 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4741 MODULE_PARM_DESC(debug, "debug output mask");
4742 #endif
4743
4744 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4745 MODULE_PARM_DESC(swcrypto50,
4746                  "using crypto in software (default 0 [hardware]) (deprecated)");
4747 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4748 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4749 module_param_named(queues_num50,
4750                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4751 MODULE_PARM_DESC(queues_num50,
4752                  "number of hw queues in 50xx series (deprecated)");
4753 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4754 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4755 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4756 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4757 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4758 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4759 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4760                    int, S_IRUGO);
4761 MODULE_PARM_DESC(amsdu_size_8K50,
4762                  "enable 8K amsdu size in 50XX series (deprecated)");
4763 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4764                    int, S_IRUGO);
4765 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4766 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4767 MODULE_PARM_DESC(fw_restart50,
4768                  "restart firmware in case of error (deprecated)");
4769 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4770 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4771 module_param_named(
4772         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4773 MODULE_PARM_DESC(disable_hw_scan,
4774                  "disable hardware scanning (default 0) (deprecated)");
4775
4776 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4777                    S_IRUGO);
4778 MODULE_PARM_DESC(ucode_alternative,
4779                  "specify ucode alternative to use from ucode file");
4780
4781 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4782 MODULE_PARM_DESC(antenna_coupling,
4783                  "specify antenna coupling in dB (defualt: 0 dB)");
4784
4785 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4786 MODULE_PARM_DESC(bt_ch_inhibition,
4787                  "Disable BT channel inhibition (default: enable)");
4788
4789 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4790 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4791
4792 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4793 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");