1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
48 #include <net/mac80211.h>
50 #include <asm/div64.h>
52 #define DRV_NAME "iwlagn"
54 #include "iwl-eeprom.h"
58 #include "iwl-helpers.h"
60 #include "iwl-agn-calib.h"
64 /******************************************************************************
68 ******************************************************************************/
71 * module name, copyright, version, etc.
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
75 #ifdef CONFIG_IWLWIFI_DEBUG
81 #define DRV_VERSION IWLWIFI_VERSION VD
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
89 static int iwlagn_ant_coupling;
90 static bool iwlagn_bt_ch_announce = 1;
92 void iwl_update_chain_flags(struct iwl_priv *priv)
94 struct iwl_rxon_context *ctx;
96 if (priv->cfg->ops->hcmd->set_rxon_chain) {
97 for_each_context(priv, ctx) {
98 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
99 if (ctx->active.rx_chain != ctx->staging.rx_chain)
100 iwlcore_commit_rxon(priv, ctx);
105 static void iwl_clear_free_frames(struct iwl_priv *priv)
107 struct list_head *element;
109 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
112 while (!list_empty(&priv->free_frames)) {
113 element = priv->free_frames.next;
115 kfree(list_entry(element, struct iwl_frame, list));
116 priv->frames_count--;
119 if (priv->frames_count) {
120 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
122 priv->frames_count = 0;
126 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
128 struct iwl_frame *frame;
129 struct list_head *element;
130 if (list_empty(&priv->free_frames)) {
131 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
133 IWL_ERR(priv, "Could not allocate frame!\n");
137 priv->frames_count++;
141 element = priv->free_frames.next;
143 return list_entry(element, struct iwl_frame, list);
146 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
148 memset(frame, 0, sizeof(*frame));
149 list_add(&frame->list, &priv->free_frames);
152 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
153 struct ieee80211_hdr *hdr,
156 lockdep_assert_held(&priv->mutex);
158 if (!priv->beacon_skb)
161 if (priv->beacon_skb->len > left)
164 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
166 return priv->beacon_skb->len;
169 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
170 static void iwl_set_beacon_tim(struct iwl_priv *priv,
171 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
172 u8 *beacon, u32 frame_size)
175 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
178 * The index is relative to frame start but we start looking at the
179 * variable-length part of the beacon.
181 tim_idx = mgmt->u.beacon.variable - beacon;
183 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
184 while ((tim_idx < (frame_size - 2)) &&
185 (beacon[tim_idx] != WLAN_EID_TIM))
186 tim_idx += beacon[tim_idx+1] + 2;
188 /* If TIM field was found, set variables */
189 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
190 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
191 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
193 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
196 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
197 struct iwl_frame *frame)
199 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
204 * We have to set up the TX command, the TX Beacon command, and the
208 lockdep_assert_held(&priv->mutex);
210 if (!priv->beacon_ctx) {
211 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
215 /* Initialize memory */
216 tx_beacon_cmd = &frame->u.beacon;
217 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
219 /* Set up TX beacon contents */
220 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
221 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
222 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
227 /* Set up TX command fields */
228 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
229 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
230 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
231 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
232 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
234 /* Set up TX beacon command fields */
235 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
238 /* Set up packet rate and flags */
239 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
240 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
241 priv->hw_params.valid_tx_ant);
242 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
243 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
244 rate_flags |= RATE_MCS_CCK_MSK;
245 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
248 return sizeof(*tx_beacon_cmd) + frame_size;
251 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
253 struct iwl_frame *frame;
254 unsigned int frame_size;
256 struct iwl_host_cmd cmd = {
257 .id = REPLY_TX_BEACON,
258 .flags = CMD_SIZE_HUGE,
261 frame = iwl_get_free_frame(priv);
263 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
268 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
270 IWL_ERR(priv, "Error configuring the beacon command\n");
271 iwl_free_frame(priv, frame);
275 cmd.len = frame_size;
276 cmd.data = &frame->u.cmd[0];
278 rc = iwl_send_cmd_sync(priv, &cmd);
280 iwl_free_frame(priv, frame);
285 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
287 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
289 dma_addr_t addr = get_unaligned_le32(&tb->lo);
290 if (sizeof(dma_addr_t) > sizeof(u32))
292 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
297 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
299 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
301 return le16_to_cpu(tb->hi_n_len) >> 4;
304 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
305 dma_addr_t addr, u16 len)
307 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
308 u16 hi_n_len = len << 4;
310 put_unaligned_le32(addr, &tb->lo);
311 if (sizeof(dma_addr_t) > sizeof(u32))
312 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
314 tb->hi_n_len = cpu_to_le16(hi_n_len);
316 tfd->num_tbs = idx + 1;
319 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
321 return tfd->num_tbs & 0x1f;
325 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
326 * @priv - driver private data
329 * Does NOT advance any TFD circular buffer read/write indexes
330 * Does NOT free the TFD itself (which is within circular buffer)
332 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
334 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
336 struct pci_dev *dev = priv->pci_dev;
337 int index = txq->q.read_ptr;
341 tfd = &tfd_tmp[index];
343 /* Sanity check on number of chunks */
344 num_tbs = iwl_tfd_get_num_tbs(tfd);
346 if (num_tbs >= IWL_NUM_OF_TBS) {
347 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
348 /* @todo issue fatal error, it is quite serious situation */
354 pci_unmap_single(dev,
355 dma_unmap_addr(&txq->meta[index], mapping),
356 dma_unmap_len(&txq->meta[index], len),
357 PCI_DMA_BIDIRECTIONAL);
359 /* Unmap chunks, if any. */
360 for (i = 1; i < num_tbs; i++)
361 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
362 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
368 skb = txq->txb[txq->q.read_ptr].skb;
370 /* can be called from irqs-disabled context */
372 dev_kfree_skb_any(skb);
373 txq->txb[txq->q.read_ptr].skb = NULL;
378 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
379 struct iwl_tx_queue *txq,
380 dma_addr_t addr, u16 len,
384 struct iwl_tfd *tfd, *tfd_tmp;
388 tfd_tmp = (struct iwl_tfd *)txq->tfds;
389 tfd = &tfd_tmp[q->write_ptr];
392 memset(tfd, 0, sizeof(*tfd));
394 num_tbs = iwl_tfd_get_num_tbs(tfd);
396 /* Each TFD can point to a maximum 20 Tx buffers */
397 if (num_tbs >= IWL_NUM_OF_TBS) {
398 IWL_ERR(priv, "Error can not send more than %d chunks\n",
403 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
406 if (unlikely(addr & ~IWL_TX_DMA_MASK))
407 IWL_ERR(priv, "Unaligned address = %llx\n",
408 (unsigned long long)addr);
410 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
416 * Tell nic where to find circular buffer of Tx Frame Descriptors for
417 * given Tx queue, and enable the DMA channel used for that queue.
419 * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
420 * channels supported in hardware.
422 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
423 struct iwl_tx_queue *txq)
425 int txq_id = txq->q.id;
427 /* Circular buffer (TFD queue in DRAM) physical base address */
428 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
429 txq->q.dma_addr >> 8);
434 static void iwl_bg_beacon_update(struct work_struct *work)
436 struct iwl_priv *priv =
437 container_of(work, struct iwl_priv, beacon_update);
438 struct sk_buff *beacon;
440 mutex_lock(&priv->mutex);
441 if (!priv->beacon_ctx) {
442 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
446 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
448 * The ucode will send beacon notifications even in
449 * IBSS mode, but we don't want to process them. But
450 * we need to defer the type check to here due to
451 * requiring locking around the beacon_ctx access.
456 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
457 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
459 IWL_ERR(priv, "update beacon failed -- keeping old\n");
463 /* new beacon skb is allocated every time; dispose previous.*/
464 dev_kfree_skb(priv->beacon_skb);
466 priv->beacon_skb = beacon;
468 iwlagn_send_beacon_cmd(priv);
470 mutex_unlock(&priv->mutex);
473 static void iwl_bg_bt_runtime_config(struct work_struct *work)
475 struct iwl_priv *priv =
476 container_of(work, struct iwl_priv, bt_runtime_config);
478 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
481 /* dont send host command if rf-kill is on */
482 if (!iwl_is_ready_rf(priv))
484 priv->cfg->ops->hcmd->send_bt_config(priv);
487 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
489 struct iwl_priv *priv =
490 container_of(work, struct iwl_priv, bt_full_concurrency);
491 struct iwl_rxon_context *ctx;
493 mutex_lock(&priv->mutex);
495 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
498 /* dont send host command if rf-kill is on */
499 if (!iwl_is_ready_rf(priv))
502 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
503 priv->bt_full_concurrent ?
504 "full concurrency" : "3-wire");
507 * LQ & RXON updated cmds must be sent before BT Config cmd
508 * to avoid 3-wire collisions
510 for_each_context(priv, ctx) {
511 if (priv->cfg->ops->hcmd->set_rxon_chain)
512 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
513 iwlcore_commit_rxon(priv, ctx);
516 priv->cfg->ops->hcmd->send_bt_config(priv);
518 mutex_unlock(&priv->mutex);
522 * iwl_bg_statistics_periodic - Timer callback to queue statistics
524 * This callback is provided in order to send a statistics request.
526 * This timer function is continually reset to execute within
527 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
528 * was received. We need to ensure we receive the statistics in order
529 * to update the temperature used for calibrating the TXPOWER.
531 static void iwl_bg_statistics_periodic(unsigned long data)
533 struct iwl_priv *priv = (struct iwl_priv *)data;
535 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
538 /* dont send host command if rf-kill is on */
539 if (!iwl_is_ready_rf(priv))
542 iwl_send_statistics_request(priv, CMD_ASYNC, false);
546 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
547 u32 start_idx, u32 num_events,
551 u32 ptr; /* SRAM byte address of log data */
552 u32 ev, time, data; /* event log data */
553 unsigned long reg_flags;
556 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
558 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
560 /* Make sure device is powered up for SRAM reads */
561 spin_lock_irqsave(&priv->reg_lock, reg_flags);
562 if (iwl_grab_nic_access(priv)) {
563 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
567 /* Set starting address; reads will auto-increment */
568 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
572 * "time" is actually "data" for mode 0 (no timestamp).
573 * place event id # at far right for easier visual parsing.
575 for (i = 0; i < num_events; i++) {
576 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
577 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
579 trace_iwlwifi_dev_ucode_cont_event(priv,
582 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
583 trace_iwlwifi_dev_ucode_cont_event(priv,
587 /* Allow device to power down */
588 iwl_release_nic_access(priv);
589 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
592 static void iwl_continuous_event_trace(struct iwl_priv *priv)
594 u32 capacity; /* event log capacity in # entries */
595 u32 base; /* SRAM byte address of event log header */
596 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
597 u32 num_wraps; /* # times uCode wrapped to top of log */
598 u32 next_entry; /* index of next entry to be written by uCode */
600 base = priv->device_pointers.error_event_table;
601 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
602 capacity = iwl_read_targ_mem(priv, base);
603 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
604 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
605 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
609 if (num_wraps == priv->event_log.num_wraps) {
610 iwl_print_cont_event_trace(priv,
611 base, priv->event_log.next_entry,
612 next_entry - priv->event_log.next_entry,
614 priv->event_log.non_wraps_count++;
616 if ((num_wraps - priv->event_log.num_wraps) > 1)
617 priv->event_log.wraps_more_count++;
619 priv->event_log.wraps_once_count++;
620 trace_iwlwifi_dev_ucode_wrap_event(priv,
621 num_wraps - priv->event_log.num_wraps,
622 next_entry, priv->event_log.next_entry);
623 if (next_entry < priv->event_log.next_entry) {
624 iwl_print_cont_event_trace(priv, base,
625 priv->event_log.next_entry,
626 capacity - priv->event_log.next_entry,
629 iwl_print_cont_event_trace(priv, base, 0,
632 iwl_print_cont_event_trace(priv, base,
633 next_entry, capacity - next_entry,
636 iwl_print_cont_event_trace(priv, base, 0,
640 priv->event_log.num_wraps = num_wraps;
641 priv->event_log.next_entry = next_entry;
645 * iwl_bg_ucode_trace - Timer callback to log ucode event
647 * The timer is continually set to execute every
648 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
649 * this function is to perform continuous uCode event logging operation
652 static void iwl_bg_ucode_trace(unsigned long data)
654 struct iwl_priv *priv = (struct iwl_priv *)data;
656 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
659 if (priv->event_log.ucode_trace) {
660 iwl_continuous_event_trace(priv);
661 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
662 mod_timer(&priv->ucode_trace,
663 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
667 static void iwl_bg_tx_flush(struct work_struct *work)
669 struct iwl_priv *priv =
670 container_of(work, struct iwl_priv, tx_flush);
672 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
675 /* do nothing if rf-kill is on */
676 if (!iwl_is_ready_rf(priv))
679 if (priv->cfg->ops->lib->txfifo_flush) {
680 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
681 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
686 * iwl_rx_handle - Main entry function for receiving responses from uCode
688 * Uses the priv->rx_handlers callback function array to invoke
689 * the appropriate handlers, including command responses,
690 * frame-received notifications, and other notifications.
692 static void iwl_rx_handle(struct iwl_priv *priv)
694 struct iwl_rx_mem_buffer *rxb;
695 struct iwl_rx_packet *pkt;
696 struct iwl_rx_queue *rxq = &priv->rxq;
704 /* uCode's read index (stored in shared DRAM) indicates the last Rx
705 * buffer that the driver may process (last buffer filled by ucode). */
706 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
709 /* Rx interrupt, but nothing sent from uCode */
711 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
713 /* calculate total frames need to be restock after handling RX */
714 total_empty = r - rxq->write_actual;
716 total_empty += RX_QUEUE_SIZE;
718 if (total_empty > (RX_QUEUE_SIZE / 2))
726 /* If an RXB doesn't have a Rx queue slot associated with it,
727 * then a bug has been introduced in the queue refilling
728 * routines -- catch it here */
729 if (WARN_ON(rxb == NULL)) {
730 i = (i + 1) & RX_QUEUE_MASK;
734 rxq->queue[i] = NULL;
736 pci_unmap_page(priv->pci_dev, rxb->page_dma,
737 PAGE_SIZE << priv->hw_params.rx_page_order,
741 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
742 len += sizeof(u32); /* account for status word */
743 trace_iwlwifi_dev_rx(priv, pkt, len);
745 /* Reclaim a command buffer only if this packet is a response
746 * to a (driver-originated) command.
747 * If the packet (e.g. Rx frame) originated from uCode,
748 * there is no command buffer to reclaim.
749 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
750 * but apparently a few don't get set; catch them here. */
751 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
752 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
753 (pkt->hdr.cmd != REPLY_RX) &&
754 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
755 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
756 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
757 (pkt->hdr.cmd != REPLY_TX);
760 * Do the notification wait before RX handlers so
761 * even if the RX handler consumes the RXB we have
762 * access to it in the notification wait entry.
764 if (!list_empty(&priv->_agn.notif_waits)) {
765 struct iwl_notification_wait *w;
767 spin_lock(&priv->_agn.notif_wait_lock);
768 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
769 if (w->cmd == pkt->hdr.cmd) {
775 spin_unlock(&priv->_agn.notif_wait_lock);
777 wake_up_all(&priv->_agn.notif_waitq);
780 /* Based on type of command response or notification,
781 * handle those that need handling via function in
782 * rx_handlers table. See iwl_setup_rx_handlers() */
783 if (priv->rx_handlers[pkt->hdr.cmd]) {
784 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
785 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
786 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
787 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
789 /* No handling needed */
791 "r %d i %d No handler needed for %s, 0x%02x\n",
792 r, i, get_cmd_string(pkt->hdr.cmd),
797 * XXX: After here, we should always check rxb->page
798 * against NULL before touching it or its virtual
799 * memory (pkt). Because some rx_handler might have
800 * already taken or freed the pages.
804 /* Invoke any callbacks, transfer the buffer to caller,
805 * and fire off the (possibly) blocking iwl_send_cmd()
806 * as we reclaim the driver command queue */
808 iwl_tx_cmd_complete(priv, rxb);
810 IWL_WARN(priv, "Claim null rxb?\n");
813 /* Reuse the page if possible. For notification packets and
814 * SKBs that fail to Rx correctly, add them back into the
815 * rx_free list for reuse later. */
816 spin_lock_irqsave(&rxq->lock, flags);
817 if (rxb->page != NULL) {
818 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
819 0, PAGE_SIZE << priv->hw_params.rx_page_order,
821 list_add_tail(&rxb->list, &rxq->rx_free);
824 list_add_tail(&rxb->list, &rxq->rx_used);
826 spin_unlock_irqrestore(&rxq->lock, flags);
828 i = (i + 1) & RX_QUEUE_MASK;
829 /* If there are a lot of unused frames,
830 * restock the Rx queue so ucode wont assert. */
835 iwlagn_rx_replenish_now(priv);
841 /* Backtrack one entry */
844 iwlagn_rx_replenish_now(priv);
846 iwlagn_rx_queue_restock(priv);
849 /* call this function to flush any scheduled tasklet */
850 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
852 /* wait to make sure we flush pending tasklet*/
853 synchronize_irq(priv->pci_dev->irq);
854 tasklet_kill(&priv->irq_tasklet);
857 /* tasklet for iwlagn interrupt */
858 static void iwl_irq_tasklet(struct iwl_priv *priv)
864 #ifdef CONFIG_IWLWIFI_DEBUG
868 spin_lock_irqsave(&priv->lock, flags);
870 /* Ack/clear/reset pending uCode interrupts.
871 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
873 /* There is a hardware bug in the interrupt mask function that some
874 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
875 * they are disabled in the CSR_INT_MASK register. Furthermore the
876 * ICT interrupt handling mechanism has another bug that might cause
877 * these unmasked interrupts fail to be detected. We workaround the
878 * hardware bugs here by ACKing all the possible interrupts so that
879 * interrupt coalescing can still be achieved.
881 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
883 inta = priv->_agn.inta;
885 #ifdef CONFIG_IWLWIFI_DEBUG
886 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
888 inta_mask = iwl_read32(priv, CSR_INT_MASK);
889 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
894 spin_unlock_irqrestore(&priv->lock, flags);
896 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
899 /* Now service all interrupt bits discovered above. */
900 if (inta & CSR_INT_BIT_HW_ERR) {
901 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
903 /* Tell the device to stop sending interrupts */
904 iwl_disable_interrupts(priv);
906 priv->isr_stats.hw++;
907 iwl_irq_handle_error(priv);
909 handled |= CSR_INT_BIT_HW_ERR;
914 #ifdef CONFIG_IWLWIFI_DEBUG
915 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
916 /* NIC fires this, but we don't use it, redundant with WAKEUP */
917 if (inta & CSR_INT_BIT_SCD) {
918 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
919 "the frame/frames.\n");
920 priv->isr_stats.sch++;
923 /* Alive notification via Rx interrupt will do the real work */
924 if (inta & CSR_INT_BIT_ALIVE) {
925 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
926 priv->isr_stats.alive++;
930 /* Safely ignore these bits for debug checks below */
931 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
933 /* HW RF KILL switch toggled */
934 if (inta & CSR_INT_BIT_RF_KILL) {
936 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
937 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
940 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
941 hw_rf_kill ? "disable radio" : "enable radio");
943 priv->isr_stats.rfkill++;
945 /* driver only loads ucode once setting the interface up.
946 * the driver allows loading the ucode even if the radio
947 * is killed. Hence update the killswitch state here. The
948 * rfkill handler will care about restarting if needed.
950 if (!test_bit(STATUS_ALIVE, &priv->status)) {
952 set_bit(STATUS_RF_KILL_HW, &priv->status);
954 clear_bit(STATUS_RF_KILL_HW, &priv->status);
955 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
958 handled |= CSR_INT_BIT_RF_KILL;
961 /* Chip got too hot and stopped itself */
962 if (inta & CSR_INT_BIT_CT_KILL) {
963 IWL_ERR(priv, "Microcode CT kill error detected.\n");
964 priv->isr_stats.ctkill++;
965 handled |= CSR_INT_BIT_CT_KILL;
968 /* Error detected by uCode */
969 if (inta & CSR_INT_BIT_SW_ERR) {
970 IWL_ERR(priv, "Microcode SW error detected. "
971 " Restarting 0x%X.\n", inta);
972 priv->isr_stats.sw++;
973 iwl_irq_handle_error(priv);
974 handled |= CSR_INT_BIT_SW_ERR;
977 /* uCode wakes up after power-down sleep */
978 if (inta & CSR_INT_BIT_WAKEUP) {
979 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
980 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
981 for (i = 0; i < priv->hw_params.max_txq_num; i++)
982 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
984 priv->isr_stats.wakeup++;
986 handled |= CSR_INT_BIT_WAKEUP;
989 /* All uCode command responses, including Tx command responses,
990 * Rx "responses" (frame-received notification), and other
991 * notifications from uCode come through here*/
992 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
993 CSR_INT_BIT_RX_PERIODIC)) {
994 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
995 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
996 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
997 iwl_write32(priv, CSR_FH_INT_STATUS,
1000 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1001 handled |= CSR_INT_BIT_RX_PERIODIC;
1002 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1004 /* Sending RX interrupt require many steps to be done in the
1006 * 1- write interrupt to current index in ICT table.
1008 * 3- update RX shared data to indicate last write index.
1009 * 4- send interrupt.
1010 * This could lead to RX race, driver could receive RX interrupt
1011 * but the shared data changes does not reflect this;
1012 * periodic interrupt will detect any dangling Rx activity.
1015 /* Disable periodic interrupt; we use it as just a one-shot. */
1016 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1017 CSR_INT_PERIODIC_DIS);
1018 iwl_rx_handle(priv);
1021 * Enable periodic interrupt in 8 msec only if we received
1022 * real RX interrupt (instead of just periodic int), to catch
1023 * any dangling Rx interrupt. If it was just the periodic
1024 * interrupt, there was no dangling Rx activity, and no need
1025 * to extend the periodic interrupt; one-shot is enough.
1027 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1028 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1029 CSR_INT_PERIODIC_ENA);
1031 priv->isr_stats.rx++;
1034 /* This "Tx" DMA channel is used only for loading uCode */
1035 if (inta & CSR_INT_BIT_FH_TX) {
1036 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1037 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1038 priv->isr_stats.tx++;
1039 handled |= CSR_INT_BIT_FH_TX;
1040 /* Wake up uCode load routine, now that load is complete */
1041 priv->ucode_write_complete = 1;
1042 wake_up_interruptible(&priv->wait_command_queue);
1045 if (inta & ~handled) {
1046 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1047 priv->isr_stats.unhandled++;
1050 if (inta & ~(priv->inta_mask)) {
1051 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1052 inta & ~priv->inta_mask);
1055 /* Re-enable all interrupts */
1056 /* only Re-enable if disabled by irq */
1057 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1058 iwl_enable_interrupts(priv);
1059 /* Re-enable RF_KILL if it occurred */
1060 else if (handled & CSR_INT_BIT_RF_KILL)
1061 iwl_enable_rfkill_int(priv);
1064 /*****************************************************************************
1068 *****************************************************************************/
1070 #ifdef CONFIG_IWLWIFI_DEBUG
1073 * The following adds a new attribute to the sysfs representation
1074 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1075 * used for controlling the debug level.
1077 * See the level definitions in iwl for details.
1079 * The debug_level being managed using sysfs below is a per device debug
1080 * level that is used instead of the global debug level if it (the per
1081 * device debug level) is set.
1083 static ssize_t show_debug_level(struct device *d,
1084 struct device_attribute *attr, char *buf)
1086 struct iwl_priv *priv = dev_get_drvdata(d);
1087 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1089 static ssize_t store_debug_level(struct device *d,
1090 struct device_attribute *attr,
1091 const char *buf, size_t count)
1093 struct iwl_priv *priv = dev_get_drvdata(d);
1097 ret = strict_strtoul(buf, 0, &val);
1099 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1101 priv->debug_level = val;
1102 if (iwl_alloc_traffic_mem(priv))
1104 "Not enough memory to generate traffic log\n");
1106 return strnlen(buf, count);
1109 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1110 show_debug_level, store_debug_level);
1113 #endif /* CONFIG_IWLWIFI_DEBUG */
1116 static ssize_t show_temperature(struct device *d,
1117 struct device_attribute *attr, char *buf)
1119 struct iwl_priv *priv = dev_get_drvdata(d);
1121 if (!iwl_is_alive(priv))
1124 return sprintf(buf, "%d\n", priv->temperature);
1127 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1129 static ssize_t show_tx_power(struct device *d,
1130 struct device_attribute *attr, char *buf)
1132 struct iwl_priv *priv = dev_get_drvdata(d);
1134 if (!iwl_is_ready_rf(priv))
1135 return sprintf(buf, "off\n");
1137 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1140 static ssize_t store_tx_power(struct device *d,
1141 struct device_attribute *attr,
1142 const char *buf, size_t count)
1144 struct iwl_priv *priv = dev_get_drvdata(d);
1148 ret = strict_strtoul(buf, 10, &val);
1150 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1152 ret = iwl_set_tx_power(priv, val, false);
1154 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1162 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1164 static struct attribute *iwl_sysfs_entries[] = {
1165 &dev_attr_temperature.attr,
1166 &dev_attr_tx_power.attr,
1167 #ifdef CONFIG_IWLWIFI_DEBUG
1168 &dev_attr_debug_level.attr,
1173 static struct attribute_group iwl_attribute_group = {
1174 .name = NULL, /* put in device directory */
1175 .attrs = iwl_sysfs_entries,
1178 /******************************************************************************
1180 * uCode download functions
1182 ******************************************************************************/
1184 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1186 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1187 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1188 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1189 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1192 static void iwl_nic_start(struct iwl_priv *priv)
1194 /* Remove all resets to allow NIC to operate */
1195 iwl_write32(priv, CSR_RESET, 0);
1198 struct iwlagn_ucode_capabilities {
1199 u32 max_probe_length;
1200 u32 standard_phy_calibration_size;
1204 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1205 static int iwl_mac_setup_register(struct iwl_priv *priv,
1206 struct iwlagn_ucode_capabilities *capa);
1208 #define UCODE_EXPERIMENTAL_INDEX 100
1209 #define UCODE_EXPERIMENTAL_TAG "exp"
1211 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1213 const char *name_pre = priv->cfg->fw_name_pre;
1217 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1218 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1219 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1220 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1222 priv->fw_index = priv->cfg->ucode_api_max;
1223 sprintf(tag, "%d", priv->fw_index);
1226 sprintf(tag, "%d", priv->fw_index);
1229 if (priv->fw_index < priv->cfg->ucode_api_min) {
1230 IWL_ERR(priv, "no suitable firmware found!\n");
1234 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1236 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1237 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1238 ? "EXPERIMENTAL " : "",
1239 priv->firmware_name);
1241 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1242 &priv->pci_dev->dev, GFP_KERNEL, priv,
1243 iwl_ucode_callback);
1246 struct iwlagn_firmware_pieces {
1247 const void *inst, *data, *init, *init_data;
1248 size_t inst_size, data_size, init_size, init_data_size;
1252 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1253 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1256 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1257 const struct firmware *ucode_raw,
1258 struct iwlagn_firmware_pieces *pieces)
1260 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1261 u32 api_ver, hdr_size;
1264 priv->ucode_ver = le32_to_cpu(ucode->ver);
1265 api_ver = IWL_UCODE_API(priv->ucode_ver);
1270 if (ucode_raw->size < hdr_size) {
1271 IWL_ERR(priv, "File size too small!\n");
1274 pieces->build = le32_to_cpu(ucode->u.v2.build);
1275 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1276 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1277 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1278 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1279 src = ucode->u.v2.data;
1285 if (ucode_raw->size < hdr_size) {
1286 IWL_ERR(priv, "File size too small!\n");
1290 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1291 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1292 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1293 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1294 src = ucode->u.v1.data;
1298 /* Verify size of file vs. image size info in file's header */
1299 if (ucode_raw->size != hdr_size + pieces->inst_size +
1300 pieces->data_size + pieces->init_size +
1301 pieces->init_data_size) {
1304 "uCode file size %d does not match expected size\n",
1305 (int)ucode_raw->size);
1310 src += pieces->inst_size;
1312 src += pieces->data_size;
1314 src += pieces->init_size;
1315 pieces->init_data = src;
1316 src += pieces->init_data_size;
1321 static int iwlagn_wanted_ucode_alternative = 1;
1323 static int iwlagn_load_firmware(struct iwl_priv *priv,
1324 const struct firmware *ucode_raw,
1325 struct iwlagn_firmware_pieces *pieces,
1326 struct iwlagn_ucode_capabilities *capa)
1328 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1329 struct iwl_ucode_tlv *tlv;
1330 size_t len = ucode_raw->size;
1332 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1335 enum iwl_ucode_tlv_type tlv_type;
1338 if (len < sizeof(*ucode)) {
1339 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1343 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1344 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1345 le32_to_cpu(ucode->magic));
1350 * Check which alternatives are present, and "downgrade"
1351 * when the chosen alternative is not present, warning
1352 * the user when that happens. Some files may not have
1353 * any alternatives, so don't warn in that case.
1355 alternatives = le64_to_cpu(ucode->alternatives);
1356 tmp = wanted_alternative;
1357 if (wanted_alternative > 63)
1358 wanted_alternative = 63;
1359 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1360 wanted_alternative--;
1361 if (wanted_alternative && wanted_alternative != tmp)
1363 "uCode alternative %d not available, choosing %d\n",
1364 tmp, wanted_alternative);
1366 priv->ucode_ver = le32_to_cpu(ucode->ver);
1367 pieces->build = le32_to_cpu(ucode->build);
1370 len -= sizeof(*ucode);
1372 while (len >= sizeof(*tlv)) {
1375 len -= sizeof(*tlv);
1378 tlv_len = le32_to_cpu(tlv->length);
1379 tlv_type = le16_to_cpu(tlv->type);
1380 tlv_alt = le16_to_cpu(tlv->alternative);
1381 tlv_data = tlv->data;
1383 if (len < tlv_len) {
1384 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1388 len -= ALIGN(tlv_len, 4);
1389 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1392 * Alternative 0 is always valid.
1394 * Skip alternative TLVs that are not selected.
1396 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1400 case IWL_UCODE_TLV_INST:
1401 pieces->inst = tlv_data;
1402 pieces->inst_size = tlv_len;
1404 case IWL_UCODE_TLV_DATA:
1405 pieces->data = tlv_data;
1406 pieces->data_size = tlv_len;
1408 case IWL_UCODE_TLV_INIT:
1409 pieces->init = tlv_data;
1410 pieces->init_size = tlv_len;
1412 case IWL_UCODE_TLV_INIT_DATA:
1413 pieces->init_data = tlv_data;
1414 pieces->init_data_size = tlv_len;
1416 case IWL_UCODE_TLV_BOOT:
1417 IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1419 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1420 if (tlv_len != sizeof(u32))
1421 goto invalid_tlv_len;
1422 capa->max_probe_length =
1423 le32_to_cpup((__le32 *)tlv_data);
1425 case IWL_UCODE_TLV_PAN:
1427 goto invalid_tlv_len;
1428 capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1430 case IWL_UCODE_TLV_FLAGS:
1431 /* must be at least one u32 */
1432 if (tlv_len < sizeof(u32))
1433 goto invalid_tlv_len;
1434 /* and a proper number of u32s */
1435 if (tlv_len % sizeof(u32))
1436 goto invalid_tlv_len;
1438 * This driver only reads the first u32 as
1439 * right now no more features are defined,
1440 * if that changes then either the driver
1441 * will not work with the new firmware, or
1442 * it'll not take advantage of new features.
1444 capa->flags = le32_to_cpup((__le32 *)tlv_data);
1446 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1447 if (tlv_len != sizeof(u32))
1448 goto invalid_tlv_len;
1449 pieces->init_evtlog_ptr =
1450 le32_to_cpup((__le32 *)tlv_data);
1452 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1453 if (tlv_len != sizeof(u32))
1454 goto invalid_tlv_len;
1455 pieces->init_evtlog_size =
1456 le32_to_cpup((__le32 *)tlv_data);
1458 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1459 if (tlv_len != sizeof(u32))
1460 goto invalid_tlv_len;
1461 pieces->init_errlog_ptr =
1462 le32_to_cpup((__le32 *)tlv_data);
1464 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1465 if (tlv_len != sizeof(u32))
1466 goto invalid_tlv_len;
1467 pieces->inst_evtlog_ptr =
1468 le32_to_cpup((__le32 *)tlv_data);
1470 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1471 if (tlv_len != sizeof(u32))
1472 goto invalid_tlv_len;
1473 pieces->inst_evtlog_size =
1474 le32_to_cpup((__le32 *)tlv_data);
1476 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1477 if (tlv_len != sizeof(u32))
1478 goto invalid_tlv_len;
1479 pieces->inst_errlog_ptr =
1480 le32_to_cpup((__le32 *)tlv_data);
1482 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1484 goto invalid_tlv_len;
1485 priv->enhance_sensitivity_table = true;
1487 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1488 if (tlv_len != sizeof(u32))
1489 goto invalid_tlv_len;
1490 capa->standard_phy_calibration_size =
1491 le32_to_cpup((__le32 *)tlv_data);
1494 IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
1500 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1501 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1508 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1509 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1515 * iwl_ucode_callback - callback when firmware was loaded
1517 * If loaded successfully, copies the firmware into buffers
1518 * for the card to fetch (via DMA).
1520 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1522 struct iwl_priv *priv = context;
1523 struct iwl_ucode_header *ucode;
1525 struct iwlagn_firmware_pieces pieces;
1526 const unsigned int api_max = priv->cfg->ucode_api_max;
1527 const unsigned int api_min = priv->cfg->ucode_api_min;
1531 struct iwlagn_ucode_capabilities ucode_capa = {
1532 .max_probe_length = 200,
1533 .standard_phy_calibration_size =
1534 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1537 memset(&pieces, 0, sizeof(pieces));
1540 if (priv->fw_index <= priv->cfg->ucode_api_max)
1542 "request for firmware file '%s' failed.\n",
1543 priv->firmware_name);
1547 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1548 priv->firmware_name, ucode_raw->size);
1550 /* Make sure that we got at least the API version number */
1551 if (ucode_raw->size < 4) {
1552 IWL_ERR(priv, "File size way too small!\n");
1556 /* Data from ucode file: header followed by uCode images */
1557 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1560 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1562 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1568 api_ver = IWL_UCODE_API(priv->ucode_ver);
1569 build = pieces.build;
1572 * api_ver should match the api version forming part of the
1573 * firmware filename ... but we don't check for that and only rely
1574 * on the API version read from firmware header from here on forward
1576 /* no api version check required for experimental uCode */
1577 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1578 if (api_ver < api_min || api_ver > api_max) {
1580 "Driver unable to support your firmware API. "
1581 "Driver supports v%u, firmware is v%u.\n",
1586 if (api_ver != api_max)
1588 "Firmware has old API version. Expected v%u, "
1589 "got v%u. New firmware can be obtained "
1590 "from http://www.intellinuxwireless.org.\n",
1595 sprintf(buildstr, " build %u%s", build,
1596 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1601 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1602 IWL_UCODE_MAJOR(priv->ucode_ver),
1603 IWL_UCODE_MINOR(priv->ucode_ver),
1604 IWL_UCODE_API(priv->ucode_ver),
1605 IWL_UCODE_SERIAL(priv->ucode_ver),
1608 snprintf(priv->hw->wiphy->fw_version,
1609 sizeof(priv->hw->wiphy->fw_version),
1611 IWL_UCODE_MAJOR(priv->ucode_ver),
1612 IWL_UCODE_MINOR(priv->ucode_ver),
1613 IWL_UCODE_API(priv->ucode_ver),
1614 IWL_UCODE_SERIAL(priv->ucode_ver),
1618 * For any of the failures below (before allocating pci memory)
1619 * we will try to load a version with a smaller API -- maybe the
1620 * user just got a corrupted version of the latest API.
1623 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1625 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1627 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1629 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1631 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1632 pieces.init_data_size);
1634 /* Verify that uCode images will fit in card's SRAM */
1635 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1636 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1641 if (pieces.data_size > priv->hw_params.max_data_size) {
1642 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1647 if (pieces.init_size > priv->hw_params.max_inst_size) {
1648 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1653 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1654 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1655 pieces.init_data_size);
1659 /* Allocate ucode buffers for card's bus-master loading ... */
1661 /* Runtime instructions and 2 copies of data:
1662 * 1) unmodified from disk
1663 * 2) backup cache for save/restore during power-downs */
1664 priv->ucode_code.len = pieces.inst_size;
1665 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1667 priv->ucode_data.len = pieces.data_size;
1668 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1670 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr)
1673 /* Initialization instructions and data */
1674 if (pieces.init_size && pieces.init_data_size) {
1675 priv->ucode_init.len = pieces.init_size;
1676 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1678 priv->ucode_init_data.len = pieces.init_data_size;
1679 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1681 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1685 /* Now that we can no longer fail, copy information */
1688 * The (size - 16) / 12 formula is based on the information recorded
1689 * for each event, which is of mode 1 (including timestamp) for all
1690 * new microcodes that include this information.
1692 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1693 if (pieces.init_evtlog_size)
1694 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1696 priv->_agn.init_evtlog_size =
1697 priv->cfg->base_params->max_event_log_size;
1698 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1699 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1700 if (pieces.inst_evtlog_size)
1701 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1703 priv->_agn.inst_evtlog_size =
1704 priv->cfg->base_params->max_event_log_size;
1705 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1707 if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
1708 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1709 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1711 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1713 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1714 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1716 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1718 /* Copy images into buffers for card's bus-master reads ... */
1720 /* Runtime instructions (first block of data in file) */
1721 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1723 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1725 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1726 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1730 * NOTE: Copy into backup buffer will be done in iwl_up()
1732 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1734 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1736 /* Initialization instructions */
1737 if (pieces.init_size) {
1738 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1740 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1743 /* Initialization data */
1744 if (pieces.init_data_size) {
1745 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1746 pieces.init_data_size);
1747 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1748 pieces.init_data_size);
1752 * figure out the offset of chain noise reset and gain commands
1753 * base on the size of standard phy calibration commands table size
1755 if (ucode_capa.standard_phy_calibration_size >
1756 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1757 ucode_capa.standard_phy_calibration_size =
1758 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1760 priv->_agn.phy_calib_chain_noise_reset_cmd =
1761 ucode_capa.standard_phy_calibration_size;
1762 priv->_agn.phy_calib_chain_noise_gain_cmd =
1763 ucode_capa.standard_phy_calibration_size + 1;
1765 /**************************************************
1766 * This is still part of probe() in a sense...
1768 * 9. Setup and register with mac80211 and debugfs
1769 **************************************************/
1770 err = iwl_mac_setup_register(priv, &ucode_capa);
1774 err = iwl_dbgfs_register(priv, DRV_NAME);
1776 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1778 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1779 &iwl_attribute_group);
1781 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1785 /* We have our copies now, allow OS release its copies */
1786 release_firmware(ucode_raw);
1787 complete(&priv->_agn.firmware_loading_complete);
1791 /* try next, if any */
1792 if (iwl_request_firmware(priv, false))
1794 release_firmware(ucode_raw);
1798 IWL_ERR(priv, "failed to allocate pci memory\n");
1799 iwl_dealloc_ucode_pci(priv);
1801 complete(&priv->_agn.firmware_loading_complete);
1802 device_release_driver(&priv->pci_dev->dev);
1803 release_firmware(ucode_raw);
1806 static const char *desc_lookup_text[] = {
1811 "NMI_INTERRUPT_WDG",
1815 "HW_ERROR_TUNE_LOCK",
1816 "HW_ERROR_TEMPERATURE",
1817 "ILLEGAL_CHAN_FREQ",
1820 "NMI_INTERRUPT_HOST",
1821 "NMI_INTERRUPT_ACTION_PT",
1822 "NMI_INTERRUPT_UNKNOWN",
1823 "UCODE_VERSION_MISMATCH",
1824 "HW_ERROR_ABS_LOCK",
1825 "HW_ERROR_CAL_LOCK_FAIL",
1826 "NMI_INTERRUPT_INST_ACTION_PT",
1827 "NMI_INTERRUPT_DATA_ACTION_PT",
1829 "NMI_INTERRUPT_TRM",
1830 "NMI_INTERRUPT_BREAK_POINT"
1837 static struct { char *name; u8 num; } advanced_lookup[] = {
1838 { "NMI_INTERRUPT_WDG", 0x34 },
1839 { "SYSASSERT", 0x35 },
1840 { "UCODE_VERSION_MISMATCH", 0x37 },
1841 { "BAD_COMMAND", 0x38 },
1842 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1843 { "FATAL_ERROR", 0x3D },
1844 { "NMI_TRM_HW_ERR", 0x46 },
1845 { "NMI_INTERRUPT_TRM", 0x4C },
1846 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1847 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1848 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1849 { "NMI_INTERRUPT_HOST", 0x66 },
1850 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1851 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1852 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1853 { "ADVANCED_SYSASSERT", 0 },
1856 static const char *desc_lookup(u32 num)
1859 int max = ARRAY_SIZE(desc_lookup_text);
1862 return desc_lookup_text[num];
1864 max = ARRAY_SIZE(advanced_lookup) - 1;
1865 for (i = 0; i < max; i++) {
1866 if (advanced_lookup[i].num == num)
1869 return advanced_lookup[i].name;
1872 #define ERROR_START_OFFSET (1 * sizeof(u32))
1873 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1875 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1878 u32 desc, time, count, base, data1;
1879 u32 blink1, blink2, ilink1, ilink2;
1882 base = priv->device_pointers.error_event_table;
1883 if (priv->ucode_type == UCODE_INIT) {
1885 base = priv->_agn.init_errlog_ptr;
1888 base = priv->_agn.inst_errlog_ptr;
1891 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1893 "Not valid error log pointer 0x%08X for %s uCode\n",
1894 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1898 count = iwl_read_targ_mem(priv, base);
1900 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1901 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1902 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1903 priv->status, count);
1906 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1907 priv->isr_stats.err_code = desc;
1908 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1909 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1910 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1911 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1912 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1913 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1914 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1915 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1916 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1917 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1919 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1920 blink1, blink2, ilink1, ilink2);
1922 IWL_ERR(priv, "Desc Time "
1923 "data1 data2 line\n");
1924 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1925 desc_lookup(desc), desc, time, data1, data2, line);
1926 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1927 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1928 pc, blink1, blink2, ilink1, ilink2, hcmd);
1931 #define EVENT_START_OFFSET (4 * sizeof(u32))
1934 * iwl_print_event_log - Dump error event log to syslog
1937 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1938 u32 num_events, u32 mode,
1939 int pos, char **buf, size_t bufsz)
1942 u32 base; /* SRAM byte address of event log header */
1943 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1944 u32 ptr; /* SRAM byte address of log data */
1945 u32 ev, time, data; /* event log data */
1946 unsigned long reg_flags;
1948 if (num_events == 0)
1951 base = priv->device_pointers.log_event_table;
1952 if (priv->ucode_type == UCODE_INIT) {
1954 base = priv->_agn.init_evtlog_ptr;
1957 base = priv->_agn.inst_evtlog_ptr;
1961 event_size = 2 * sizeof(u32);
1963 event_size = 3 * sizeof(u32);
1965 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1967 /* Make sure device is powered up for SRAM reads */
1968 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1969 iwl_grab_nic_access(priv);
1971 /* Set starting address; reads will auto-increment */
1972 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
1975 /* "time" is actually "data" for mode 0 (no timestamp).
1976 * place event id # at far right for easier visual parsing. */
1977 for (i = 0; i < num_events; i++) {
1978 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1979 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1983 pos += scnprintf(*buf + pos, bufsz - pos,
1984 "EVT_LOG:0x%08x:%04u\n",
1987 trace_iwlwifi_dev_ucode_event(priv, 0,
1989 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1993 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1995 pos += scnprintf(*buf + pos, bufsz - pos,
1996 "EVT_LOGT:%010u:0x%08x:%04u\n",
1999 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2001 trace_iwlwifi_dev_ucode_event(priv, time,
2007 /* Allow device to power down */
2008 iwl_release_nic_access(priv);
2009 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2014 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2016 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2017 u32 num_wraps, u32 next_entry,
2019 int pos, char **buf, size_t bufsz)
2022 * display the newest DEFAULT_LOG_ENTRIES entries
2023 * i.e the entries just before the next ont that uCode would fill.
2026 if (next_entry < size) {
2027 pos = iwl_print_event_log(priv,
2028 capacity - (size - next_entry),
2029 size - next_entry, mode,
2031 pos = iwl_print_event_log(priv, 0,
2035 pos = iwl_print_event_log(priv, next_entry - size,
2036 size, mode, pos, buf, bufsz);
2038 if (next_entry < size) {
2039 pos = iwl_print_event_log(priv, 0, next_entry,
2040 mode, pos, buf, bufsz);
2042 pos = iwl_print_event_log(priv, next_entry - size,
2043 size, mode, pos, buf, bufsz);
2049 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2051 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2052 char **buf, bool display)
2054 u32 base; /* SRAM byte address of event log header */
2055 u32 capacity; /* event log capacity in # entries */
2056 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2057 u32 num_wraps; /* # times uCode wrapped to top of log */
2058 u32 next_entry; /* index of next entry to be written by uCode */
2059 u32 size; /* # entries that we'll print */
2064 base = priv->device_pointers.log_event_table;
2065 if (priv->ucode_type == UCODE_INIT) {
2066 logsize = priv->_agn.init_evtlog_size;
2068 base = priv->_agn.init_evtlog_ptr;
2070 logsize = priv->_agn.inst_evtlog_size;
2072 base = priv->_agn.inst_evtlog_ptr;
2075 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2077 "Invalid event log pointer 0x%08X for %s uCode\n",
2078 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2082 /* event log header */
2083 capacity = iwl_read_targ_mem(priv, base);
2084 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2085 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2086 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2088 if (capacity > logsize) {
2089 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2094 if (next_entry > logsize) {
2095 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2096 next_entry, logsize);
2097 next_entry = logsize;
2100 size = num_wraps ? capacity : next_entry;
2102 /* bail out if nothing in log */
2104 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2108 /* enable/disable bt channel inhibition */
2109 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2111 #ifdef CONFIG_IWLWIFI_DEBUG
2112 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2113 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2114 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2116 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2117 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2119 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2122 #ifdef CONFIG_IWLWIFI_DEBUG
2125 bufsz = capacity * 48;
2128 *buf = kmalloc(bufsz, GFP_KERNEL);
2132 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2134 * if uCode has wrapped back to top of log,
2135 * start at the oldest entry,
2136 * i.e the next one that uCode would fill.
2139 pos = iwl_print_event_log(priv, next_entry,
2140 capacity - next_entry, mode,
2142 /* (then/else) start at top of log */
2143 pos = iwl_print_event_log(priv, 0,
2144 next_entry, mode, pos, buf, bufsz);
2146 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2147 next_entry, size, mode,
2150 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2151 next_entry, size, mode,
2157 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2159 struct iwl_ct_kill_config cmd;
2160 struct iwl_ct_kill_throttling_config adv_cmd;
2161 unsigned long flags;
2164 spin_lock_irqsave(&priv->lock, flags);
2165 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2166 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2167 spin_unlock_irqrestore(&priv->lock, flags);
2168 priv->thermal_throttle.ct_kill_toggle = false;
2170 if (priv->cfg->base_params->support_ct_kill_exit) {
2171 adv_cmd.critical_temperature_enter =
2172 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2173 adv_cmd.critical_temperature_exit =
2174 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2176 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2177 sizeof(adv_cmd), &adv_cmd);
2179 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2181 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2183 "critical temperature enter is %d,"
2185 priv->hw_params.ct_kill_threshold,
2186 priv->hw_params.ct_kill_exit_threshold);
2188 cmd.critical_temperature_R =
2189 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2191 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2194 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2196 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2198 "critical temperature is %d\n",
2199 priv->hw_params.ct_kill_threshold);
2203 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2205 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2206 struct iwl_host_cmd cmd = {
2207 .id = CALIBRATION_CFG_CMD,
2208 .len = sizeof(struct iwl_calib_cfg_cmd),
2209 .data = &calib_cfg_cmd,
2212 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2213 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2214 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2216 return iwl_send_cmd(priv, &cmd);
2221 * iwl_alive_start - called after REPLY_ALIVE notification received
2222 * from protocol/runtime uCode (initialization uCode's
2223 * Alive gets handled by iwl_init_alive_start()).
2225 static void iwl_alive_start(struct iwl_priv *priv)
2228 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2230 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2232 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2233 * This is a paranoid check, because we would not have gotten the
2234 * "runtime" alive if code weren't properly loaded. */
2235 if (iwl_verify_ucode(priv, &priv->ucode_code)) {
2236 /* Runtime instruction load was bad;
2237 * take it all the way back down so we can try again */
2238 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2242 ret = iwlagn_alive_notify(priv);
2245 "Could not complete ALIVE transition [ntf]: %d\n", ret);
2250 /* After the ALIVE response, we can send host commands to the uCode */
2251 set_bit(STATUS_ALIVE, &priv->status);
2253 /* Enable watchdog to monitor the driver tx queues */
2254 iwl_setup_watchdog(priv);
2256 if (iwl_is_rfkill(priv))
2259 /* download priority table before any calibration request */
2260 if (priv->cfg->bt_params &&
2261 priv->cfg->bt_params->advanced_bt_coexist) {
2262 /* Configure Bluetooth device coexistence support */
2263 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2264 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2265 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2266 priv->cfg->ops->hcmd->send_bt_config(priv);
2267 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2268 iwlagn_send_prio_tbl(priv);
2270 /* FIXME: w/a to force change uCode BT state machine */
2271 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2272 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2273 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2274 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2276 if (priv->hw_params.calib_rt_cfg)
2277 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2279 ieee80211_wake_queues(priv->hw);
2281 priv->active_rate = IWL_RATES_MASK;
2283 /* Configure Tx antenna selection based on H/W config */
2284 if (priv->cfg->ops->hcmd->set_tx_ant)
2285 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2287 if (iwl_is_associated_ctx(ctx)) {
2288 struct iwl_rxon_cmd *active_rxon =
2289 (struct iwl_rxon_cmd *)&ctx->active;
2290 /* apply any changes in staging */
2291 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2292 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2294 struct iwl_rxon_context *tmp;
2295 /* Initialize our rx_config data */
2296 for_each_context(priv, tmp)
2297 iwl_connection_init_rx_config(priv, tmp);
2299 if (priv->cfg->ops->hcmd->set_rxon_chain)
2300 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2303 if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2304 !priv->cfg->bt_params->advanced_bt_coexist)) {
2306 * default is 2-wire BT coexexistence support
2308 priv->cfg->ops->hcmd->send_bt_config(priv);
2311 iwl_reset_run_time_calib(priv);
2313 set_bit(STATUS_READY, &priv->status);
2315 /* Configure the adapter for unassociated operation */
2316 iwlcore_commit_rxon(priv, ctx);
2318 /* At this point, the NIC is initialized and operational */
2319 iwl_rf_kill_ct_config(priv);
2321 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2322 wake_up_interruptible(&priv->wait_command_queue);
2324 iwl_power_update_mode(priv, true);
2325 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2331 queue_work(priv->workqueue, &priv->restart);
2334 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2336 static void __iwl_down(struct iwl_priv *priv)
2338 unsigned long flags;
2341 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2343 iwl_scan_cancel_timeout(priv, 200);
2345 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2347 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2348 * to prevent rearm timer */
2349 del_timer_sync(&priv->watchdog);
2351 iwl_clear_ucode_stations(priv, NULL);
2352 iwl_dealloc_bcast_stations(priv);
2353 iwl_clear_driver_stations(priv);
2355 /* reset BT coex data */
2356 priv->bt_status = 0;
2357 if (priv->cfg->bt_params)
2358 priv->bt_traffic_load =
2359 priv->cfg->bt_params->bt_init_traffic_load;
2361 priv->bt_traffic_load = 0;
2362 priv->bt_full_concurrent = false;
2363 priv->bt_ci_compliance = 0;
2365 /* Wipe out the EXIT_PENDING status bit if we are not actually
2366 * exiting the module */
2368 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2370 /* stop and reset the on-board processor */
2371 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2373 /* tell the device to stop sending interrupts */
2374 spin_lock_irqsave(&priv->lock, flags);
2375 iwl_disable_interrupts(priv);
2376 spin_unlock_irqrestore(&priv->lock, flags);
2377 iwl_synchronize_irq(priv);
2379 if (priv->mac80211_registered)
2380 ieee80211_stop_queues(priv->hw);
2382 /* If we have not previously called iwl_init() then
2383 * clear all bits but the RF Kill bit and return */
2384 if (!iwl_is_init(priv)) {
2385 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2387 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2388 STATUS_GEO_CONFIGURED |
2389 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2390 STATUS_EXIT_PENDING;
2394 /* ...otherwise clear out all the status bits but the RF Kill
2395 * bit and continue taking the NIC down. */
2396 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2398 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2399 STATUS_GEO_CONFIGURED |
2400 test_bit(STATUS_FW_ERROR, &priv->status) <<
2402 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2403 STATUS_EXIT_PENDING;
2405 /* device going down, Stop using ICT table */
2406 iwl_disable_ict(priv);
2408 iwlagn_txq_ctx_stop(priv);
2409 iwlagn_rxq_stop(priv);
2411 /* Power-down device's busmaster DMA clocks */
2412 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2415 /* Make sure (redundant) we've released our request to stay awake */
2416 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2418 /* Stop the device, and put it in low power state */
2422 dev_kfree_skb(priv->beacon_skb);
2423 priv->beacon_skb = NULL;
2425 /* clear out any free frames */
2426 iwl_clear_free_frames(priv);
2429 static void iwl_down(struct iwl_priv *priv)
2431 mutex_lock(&priv->mutex);
2433 mutex_unlock(&priv->mutex);
2435 iwl_cancel_deferred_work(priv);
2438 #define HW_READY_TIMEOUT (50)
2440 static int iwl_set_hw_ready(struct iwl_priv *priv)
2444 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2445 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2447 /* See if we got it */
2448 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2449 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2450 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2452 if (ret != -ETIMEDOUT)
2453 priv->hw_ready = true;
2455 priv->hw_ready = false;
2457 IWL_DEBUG_INFO(priv, "hardware %s\n",
2458 (priv->hw_ready == 1) ? "ready" : "not ready");
2462 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2466 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2468 ret = iwl_set_hw_ready(priv);
2472 /* If HW is not ready, prepare the conditions to check again */
2473 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2474 CSR_HW_IF_CONFIG_REG_PREPARE);
2476 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2477 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2478 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2480 /* HW should be ready by now, check again. */
2481 if (ret != -ETIMEDOUT)
2482 iwl_set_hw_ready(priv);
2487 #define MAX_HW_RESTARTS 5
2489 static int __iwl_up(struct iwl_priv *priv)
2491 struct iwl_rxon_context *ctx;
2495 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2496 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2500 for_each_context(priv, ctx) {
2501 ret = iwlagn_alloc_bcast_station(priv, ctx);
2503 iwl_dealloc_bcast_stations(priv);
2508 iwl_prepare_card_hw(priv);
2510 if (!priv->hw_ready) {
2511 IWL_WARN(priv, "Exit HW not ready\n");
2515 /* If platform's RF_KILL switch is NOT set to KILL */
2516 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2517 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2519 set_bit(STATUS_RF_KILL_HW, &priv->status);
2521 if (iwl_is_rfkill(priv)) {
2522 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2524 iwl_enable_interrupts(priv);
2525 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2529 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2531 ret = iwlagn_hw_nic_init(priv);
2533 IWL_ERR(priv, "Unable to init nic\n");
2537 /* make sure rfkill handshake bits are cleared */
2538 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2539 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2540 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2542 /* clear (again), then enable host interrupts */
2543 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2544 iwl_enable_interrupts(priv);
2546 /* really make sure rfkill handshake bits are cleared */
2547 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2548 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2550 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2552 /* load bootstrap state machine,
2553 * load bootstrap program into processor's memory,
2554 * prepare to load the "initialize" uCode */
2555 ret = iwlagn_load_ucode(priv);
2558 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2563 /* start card; "initialize" will load runtime ucode */
2564 iwl_nic_start(priv);
2566 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2571 set_bit(STATUS_EXIT_PENDING, &priv->status);
2573 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2575 /* tried to restart and config the device for as long as our
2576 * patience could withstand */
2577 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2582 /*****************************************************************************
2584 * Workqueue callbacks
2586 *****************************************************************************/
2588 static void iwl_bg_init_alive_start(struct work_struct *data)
2590 struct iwl_priv *priv =
2591 container_of(data, struct iwl_priv, init_alive_start.work);
2593 mutex_lock(&priv->mutex);
2595 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2596 mutex_unlock(&priv->mutex);
2600 iwlagn_init_alive_start(priv);
2601 mutex_unlock(&priv->mutex);
2604 static void iwl_bg_alive_start(struct work_struct *data)
2606 struct iwl_priv *priv =
2607 container_of(data, struct iwl_priv, alive_start.work);
2609 mutex_lock(&priv->mutex);
2610 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2613 /* enable dram interrupt */
2614 iwl_reset_ict(priv);
2616 iwl_alive_start(priv);
2618 mutex_unlock(&priv->mutex);
2621 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2623 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2624 run_time_calib_work);
2626 mutex_lock(&priv->mutex);
2628 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2629 test_bit(STATUS_SCANNING, &priv->status)) {
2630 mutex_unlock(&priv->mutex);
2634 if (priv->start_calib) {
2635 iwl_chain_noise_calibration(priv);
2636 iwl_sensitivity_calibration(priv);
2639 mutex_unlock(&priv->mutex);
2642 static void iwl_bg_restart(struct work_struct *data)
2644 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2646 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2649 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2650 struct iwl_rxon_context *ctx;
2651 bool bt_full_concurrent;
2652 u8 bt_ci_compliance;
2656 mutex_lock(&priv->mutex);
2657 for_each_context(priv, ctx)
2662 * __iwl_down() will clear the BT status variables,
2663 * which is correct, but when we restart we really
2664 * want to keep them so restore them afterwards.
2666 * The restart process will later pick them up and
2667 * re-configure the hw when we reconfigure the BT
2670 bt_full_concurrent = priv->bt_full_concurrent;
2671 bt_ci_compliance = priv->bt_ci_compliance;
2672 bt_load = priv->bt_traffic_load;
2673 bt_status = priv->bt_status;
2677 priv->bt_full_concurrent = bt_full_concurrent;
2678 priv->bt_ci_compliance = bt_ci_compliance;
2679 priv->bt_traffic_load = bt_load;
2680 priv->bt_status = bt_status;
2682 mutex_unlock(&priv->mutex);
2683 iwl_cancel_deferred_work(priv);
2684 ieee80211_restart_hw(priv->hw);
2688 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2691 mutex_lock(&priv->mutex);
2693 mutex_unlock(&priv->mutex);
2697 static void iwl_bg_rx_replenish(struct work_struct *data)
2699 struct iwl_priv *priv =
2700 container_of(data, struct iwl_priv, rx_replenish);
2702 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2705 mutex_lock(&priv->mutex);
2706 iwlagn_rx_replenish(priv);
2707 mutex_unlock(&priv->mutex);
2710 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2711 struct ieee80211_channel *chan,
2712 enum nl80211_channel_type channel_type,
2715 struct iwl_priv *priv = hw->priv;
2718 /* Not supported if we don't have PAN */
2719 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2724 /* Not supported on pre-P2P firmware */
2725 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2726 BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2731 mutex_lock(&priv->mutex);
2733 if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2735 * If the PAN context is free, use the normal
2736 * way of doing remain-on-channel offload + TX.
2742 /* TODO: queue up if scanning? */
2743 if (test_bit(STATUS_SCANNING, &priv->status) ||
2744 priv->_agn.offchan_tx_skb) {
2750 * max_scan_ie_len doesn't include the blank SSID or the header,
2751 * so need to add that again here.
2753 if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2758 priv->_agn.offchan_tx_skb = skb;
2759 priv->_agn.offchan_tx_timeout = wait;
2760 priv->_agn.offchan_tx_chan = chan;
2762 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2763 IWL_SCAN_OFFCH_TX, chan->band);
2765 priv->_agn.offchan_tx_skb = NULL;
2767 mutex_unlock(&priv->mutex);
2775 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2777 struct iwl_priv *priv = hw->priv;
2780 mutex_lock(&priv->mutex);
2782 if (!priv->_agn.offchan_tx_skb) {
2787 priv->_agn.offchan_tx_skb = NULL;
2789 ret = iwl_scan_cancel_timeout(priv, 200);
2793 mutex_unlock(&priv->mutex);
2798 /*****************************************************************************
2800 * mac80211 entry point functions
2802 *****************************************************************************/
2804 #define UCODE_READY_TIMEOUT (4 * HZ)
2807 * Not a mac80211 entry point function, but it fits in with all the
2808 * other mac80211 functions grouped here.
2810 static int iwl_mac_setup_register(struct iwl_priv *priv,
2811 struct iwlagn_ucode_capabilities *capa)
2814 struct ieee80211_hw *hw = priv->hw;
2815 struct iwl_rxon_context *ctx;
2817 hw->rate_control_algorithm = "iwl-agn-rs";
2819 /* Tell mac80211 our characteristics */
2820 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2821 IEEE80211_HW_AMPDU_AGGREGATION |
2822 IEEE80211_HW_NEED_DTIM_PERIOD |
2823 IEEE80211_HW_SPECTRUM_MGMT |
2824 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2826 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2828 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2829 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2831 if (priv->cfg->sku & IWL_SKU_N)
2832 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2833 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2835 if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2836 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2838 hw->sta_data_size = sizeof(struct iwl_station_priv);
2839 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2841 for_each_context(priv, ctx) {
2842 hw->wiphy->interface_modes |= ctx->interface_modes;
2843 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2846 hw->wiphy->max_remain_on_channel_duration = 1000;
2848 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2849 WIPHY_FLAG_DISABLE_BEACON_HINTS |
2850 WIPHY_FLAG_IBSS_RSN;
2853 * For now, disable PS by default because it affects
2854 * RX performance significantly.
2856 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2858 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2859 /* we create the 802.11 header and a zero-length SSID element */
2860 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2862 /* Default value; 4 EDCA QOS priorities */
2865 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2867 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2868 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2869 &priv->bands[IEEE80211_BAND_2GHZ];
2870 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2871 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2872 &priv->bands[IEEE80211_BAND_5GHZ];
2874 iwl_leds_init(priv);
2876 ret = ieee80211_register_hw(priv->hw);
2878 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2881 priv->mac80211_registered = 1;
2887 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2889 struct iwl_priv *priv = hw->priv;
2892 IWL_DEBUG_MAC80211(priv, "enter\n");
2894 /* we should be verifying the device is ready to be opened */
2895 mutex_lock(&priv->mutex);
2896 ret = __iwl_up(priv);
2897 mutex_unlock(&priv->mutex);
2902 if (iwl_is_rfkill(priv))
2905 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2907 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2908 * mac80211 will not be run successfully. */
2909 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2910 test_bit(STATUS_READY, &priv->status),
2911 UCODE_READY_TIMEOUT);
2913 if (!test_bit(STATUS_READY, &priv->status)) {
2914 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2915 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2920 iwlagn_led_enable(priv);
2924 IWL_DEBUG_MAC80211(priv, "leave\n");
2928 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2930 struct iwl_priv *priv = hw->priv;
2932 IWL_DEBUG_MAC80211(priv, "enter\n");
2941 flush_workqueue(priv->workqueue);
2943 /* User space software may expect getting rfkill changes
2944 * even if interface is down */
2945 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2946 iwl_enable_rfkill_int(priv);
2948 IWL_DEBUG_MAC80211(priv, "leave\n");
2951 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2953 struct iwl_priv *priv = hw->priv;
2955 IWL_DEBUG_MACDUMP(priv, "enter\n");
2957 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2958 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2960 if (iwlagn_tx_skb(priv, skb))
2961 dev_kfree_skb_any(skb);
2963 IWL_DEBUG_MACDUMP(priv, "leave\n");
2966 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2967 struct ieee80211_vif *vif,
2968 struct ieee80211_key_conf *keyconf,
2969 struct ieee80211_sta *sta,
2970 u32 iv32, u16 *phase1key)
2972 struct iwl_priv *priv = hw->priv;
2973 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2975 IWL_DEBUG_MAC80211(priv, "enter\n");
2977 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2980 IWL_DEBUG_MAC80211(priv, "leave\n");
2983 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2984 struct ieee80211_vif *vif,
2985 struct ieee80211_sta *sta,
2986 struct ieee80211_key_conf *key)
2988 struct iwl_priv *priv = hw->priv;
2989 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2990 struct iwl_rxon_context *ctx = vif_priv->ctx;
2993 bool is_default_wep_key = false;
2995 IWL_DEBUG_MAC80211(priv, "enter\n");
2997 if (priv->cfg->mod_params->sw_crypto) {
2998 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3003 * To support IBSS RSN, don't program group keys in IBSS, the
3004 * hardware will then not attempt to decrypt the frames.
3006 if (vif->type == NL80211_IFTYPE_ADHOC &&
3007 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3010 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3011 if (sta_id == IWL_INVALID_STATION)
3014 mutex_lock(&priv->mutex);
3015 iwl_scan_cancel_timeout(priv, 100);
3018 * If we are getting WEP group key and we didn't receive any key mapping
3019 * so far, we are in legacy wep mode (group key only), otherwise we are
3021 * In legacy wep mode, we use another host command to the uCode.
3023 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3024 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3027 is_default_wep_key = !ctx->key_mapping_keys;
3029 is_default_wep_key =
3030 (key->hw_key_idx == HW_KEY_DEFAULT);
3035 if (is_default_wep_key)
3036 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3038 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3041 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3044 if (is_default_wep_key)
3045 ret = iwl_remove_default_wep_key(priv, ctx, key);
3047 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3049 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3055 mutex_unlock(&priv->mutex);
3056 IWL_DEBUG_MAC80211(priv, "leave\n");
3061 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3062 struct ieee80211_vif *vif,
3063 enum ieee80211_ampdu_mlme_action action,
3064 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3067 struct iwl_priv *priv = hw->priv;
3069 struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3071 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3074 if (!(priv->cfg->sku & IWL_SKU_N))
3077 mutex_lock(&priv->mutex);
3080 case IEEE80211_AMPDU_RX_START:
3081 IWL_DEBUG_HT(priv, "start Rx\n");
3082 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3084 case IEEE80211_AMPDU_RX_STOP:
3085 IWL_DEBUG_HT(priv, "stop Rx\n");
3086 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3087 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3090 case IEEE80211_AMPDU_TX_START:
3091 IWL_DEBUG_HT(priv, "start Tx\n");
3092 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3094 priv->_agn.agg_tids_count++;
3095 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3096 priv->_agn.agg_tids_count);
3099 case IEEE80211_AMPDU_TX_STOP:
3100 IWL_DEBUG_HT(priv, "stop Tx\n");
3101 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3102 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3103 priv->_agn.agg_tids_count--;
3104 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3105 priv->_agn.agg_tids_count);
3107 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3109 if (priv->cfg->ht_params &&
3110 priv->cfg->ht_params->use_rts_for_aggregation) {
3111 struct iwl_station_priv *sta_priv =
3112 (void *) sta->drv_priv;
3114 * switch off RTS/CTS if it was previously enabled
3117 sta_priv->lq_sta.lq.general_params.flags &=
3118 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3119 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3120 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3123 case IEEE80211_AMPDU_TX_OPERATIONAL:
3124 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
3126 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
3129 * If the limit is 0, then it wasn't initialised yet,
3130 * use the default. We can do that since we take the
3131 * minimum below, and we don't want to go above our
3132 * default due to hardware restrictions.
3134 if (sta_priv->max_agg_bufsize == 0)
3135 sta_priv->max_agg_bufsize =
3136 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3139 * Even though in theory the peer could have different
3140 * aggregation reorder buffer sizes for different sessions,
3141 * our ucode doesn't allow for that and has a global limit
3142 * for each station. Therefore, use the minimum of all the
3143 * aggregation sessions and our default value.
3145 sta_priv->max_agg_bufsize =
3146 min(sta_priv->max_agg_bufsize, buf_size);
3148 if (priv->cfg->ht_params &&
3149 priv->cfg->ht_params->use_rts_for_aggregation) {
3151 * switch to RTS/CTS if it is the prefer protection
3152 * method for HT traffic
3155 sta_priv->lq_sta.lq.general_params.flags |=
3156 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3159 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3160 sta_priv->max_agg_bufsize;
3162 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3163 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3167 mutex_unlock(&priv->mutex);
3172 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3173 struct ieee80211_vif *vif,
3174 struct ieee80211_sta *sta)
3176 struct iwl_priv *priv = hw->priv;
3177 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3178 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3179 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3183 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3185 mutex_lock(&priv->mutex);
3186 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3188 sta_priv->common.sta_id = IWL_INVALID_STATION;
3190 atomic_set(&sta_priv->pending_frames, 0);
3191 if (vif->type == NL80211_IFTYPE_AP)
3192 sta_priv->client = true;
3194 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3195 is_ap, sta, &sta_id);
3197 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3199 /* Should we return success if return code is EEXIST ? */
3200 mutex_unlock(&priv->mutex);
3204 sta_priv->common.sta_id = sta_id;
3206 /* Initialize rate scaling */
3207 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3209 iwl_rs_rate_init(priv, sta, sta_id);
3210 mutex_unlock(&priv->mutex);
3215 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3216 struct ieee80211_channel_switch *ch_switch)
3218 struct iwl_priv *priv = hw->priv;
3219 const struct iwl_channel_info *ch_info;
3220 struct ieee80211_conf *conf = &hw->conf;
3221 struct ieee80211_channel *channel = ch_switch->channel;
3222 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3225 * When we add support for multiple interfaces, we need to
3226 * revisit this. The channel switch command in the device
3227 * only affects the BSS context, but what does that really
3228 * mean? And what if we get a CSA on the second interface?
3229 * This needs a lot of work.
3231 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3233 unsigned long flags = 0;
3235 IWL_DEBUG_MAC80211(priv, "enter\n");
3237 mutex_lock(&priv->mutex);
3239 if (iwl_is_rfkill(priv))
3242 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3243 test_bit(STATUS_SCANNING, &priv->status))
3246 if (!iwl_is_associated_ctx(ctx))
3249 /* channel switch in progress */
3250 if (priv->switch_rxon.switch_in_progress == true)
3253 if (priv->cfg->ops->lib->set_channel_switch) {
3255 ch = channel->hw_value;
3256 if (le16_to_cpu(ctx->active.channel) != ch) {
3257 ch_info = iwl_get_channel_info(priv,
3260 if (!is_channel_valid(ch_info)) {
3261 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3264 spin_lock_irqsave(&priv->lock, flags);
3266 priv->current_ht_config.smps = conf->smps_mode;
3268 /* Configure HT40 channels */
3269 ctx->ht.enabled = conf_is_ht(conf);
3270 if (ctx->ht.enabled) {
3271 if (conf_is_ht40_minus(conf)) {
3272 ctx->ht.extension_chan_offset =
3273 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3274 ctx->ht.is_40mhz = true;
3275 } else if (conf_is_ht40_plus(conf)) {
3276 ctx->ht.extension_chan_offset =
3277 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3278 ctx->ht.is_40mhz = true;
3280 ctx->ht.extension_chan_offset =
3281 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3282 ctx->ht.is_40mhz = false;
3285 ctx->ht.is_40mhz = false;
3287 if ((le16_to_cpu(ctx->staging.channel) != ch))
3288 ctx->staging.flags = 0;
3290 iwl_set_rxon_channel(priv, channel, ctx);
3291 iwl_set_rxon_ht(priv, ht_conf);
3292 iwl_set_flags_for_band(priv, ctx, channel->band,
3294 spin_unlock_irqrestore(&priv->lock, flags);
3298 * at this point, staging_rxon has the
3299 * configuration for channel switch
3301 if (priv->cfg->ops->lib->set_channel_switch(priv,
3303 priv->switch_rxon.switch_in_progress = false;
3307 mutex_unlock(&priv->mutex);
3308 if (!priv->switch_rxon.switch_in_progress)
3309 ieee80211_chswitch_done(ctx->vif, false);
3310 IWL_DEBUG_MAC80211(priv, "leave\n");
3313 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3314 unsigned int changed_flags,
3315 unsigned int *total_flags,
3318 struct iwl_priv *priv = hw->priv;
3319 __le32 filter_or = 0, filter_nand = 0;
3320 struct iwl_rxon_context *ctx;
3322 #define CHK(test, flag) do { \
3323 if (*total_flags & (test)) \
3324 filter_or |= (flag); \
3326 filter_nand |= (flag); \
3329 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3330 changed_flags, *total_flags);
3332 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3333 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3334 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3335 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3339 mutex_lock(&priv->mutex);
3341 for_each_context(priv, ctx) {
3342 ctx->staging.filter_flags &= ~filter_nand;
3343 ctx->staging.filter_flags |= filter_or;
3346 * Not committing directly because hardware can perform a scan,
3347 * but we'll eventually commit the filter flags change anyway.
3351 mutex_unlock(&priv->mutex);
3354 * Receiving all multicast frames is always enabled by the
3355 * default flags setup in iwl_connection_init_rx_config()
3356 * since we currently do not support programming multicast
3357 * filters into the device.
3359 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3360 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3363 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3365 struct iwl_priv *priv = hw->priv;
3367 mutex_lock(&priv->mutex);
3368 IWL_DEBUG_MAC80211(priv, "enter\n");
3370 /* do not support "flush" */
3371 if (!priv->cfg->ops->lib->txfifo_flush)
3374 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3375 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3378 if (iwl_is_rfkill(priv)) {
3379 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3384 * mac80211 will not push any more frames for transmit
3385 * until the flush is completed
3388 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3389 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3390 IWL_ERR(priv, "flush request fail\n");
3394 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3395 iwlagn_wait_tx_queue_empty(priv);
3397 mutex_unlock(&priv->mutex);
3398 IWL_DEBUG_MAC80211(priv, "leave\n");
3401 static void iwlagn_disable_roc(struct iwl_priv *priv)
3403 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3404 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3406 lockdep_assert_held(&priv->mutex);
3408 if (!ctx->is_active)
3411 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3412 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3413 iwl_set_rxon_channel(priv, chan, ctx);
3414 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3416 priv->_agn.hw_roc_channel = NULL;
3418 iwlcore_commit_rxon(priv, ctx);
3420 ctx->is_active = false;
3423 static void iwlagn_bg_roc_done(struct work_struct *work)
3425 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3426 _agn.hw_roc_work.work);
3428 mutex_lock(&priv->mutex);
3429 ieee80211_remain_on_channel_expired(priv->hw);
3430 iwlagn_disable_roc(priv);
3431 mutex_unlock(&priv->mutex);
3434 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3435 struct ieee80211_channel *channel,
3436 enum nl80211_channel_type channel_type,
3439 struct iwl_priv *priv = hw->priv;
3442 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3445 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3446 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3449 mutex_lock(&priv->mutex);
3451 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3452 test_bit(STATUS_SCAN_HW, &priv->status)) {
3457 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3458 priv->_agn.hw_roc_channel = channel;
3459 priv->_agn.hw_roc_chantype = channel_type;
3460 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3461 iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3462 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3463 msecs_to_jiffies(duration + 20));
3465 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3466 ieee80211_ready_on_channel(priv->hw);
3469 mutex_unlock(&priv->mutex);
3474 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3476 struct iwl_priv *priv = hw->priv;
3478 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3481 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3483 mutex_lock(&priv->mutex);
3484 iwlagn_disable_roc(priv);
3485 mutex_unlock(&priv->mutex);
3490 /*****************************************************************************
3492 * driver setup and teardown
3494 *****************************************************************************/
3496 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3498 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3500 init_waitqueue_head(&priv->wait_command_queue);
3502 INIT_WORK(&priv->restart, iwl_bg_restart);
3503 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3504 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3505 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3506 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3507 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3508 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3509 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3510 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3511 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3513 iwl_setup_scan_deferred_work(priv);
3515 if (priv->cfg->ops->lib->setup_deferred_work)
3516 priv->cfg->ops->lib->setup_deferred_work(priv);
3518 init_timer(&priv->statistics_periodic);
3519 priv->statistics_periodic.data = (unsigned long)priv;
3520 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3522 init_timer(&priv->ucode_trace);
3523 priv->ucode_trace.data = (unsigned long)priv;
3524 priv->ucode_trace.function = iwl_bg_ucode_trace;
3526 init_timer(&priv->watchdog);
3527 priv->watchdog.data = (unsigned long)priv;
3528 priv->watchdog.function = iwl_bg_watchdog;
3530 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3531 iwl_irq_tasklet, (unsigned long)priv);
3534 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3536 if (priv->cfg->ops->lib->cancel_deferred_work)
3537 priv->cfg->ops->lib->cancel_deferred_work(priv);
3539 cancel_delayed_work_sync(&priv->init_alive_start);
3540 cancel_delayed_work(&priv->alive_start);
3541 cancel_work_sync(&priv->run_time_calib_work);
3542 cancel_work_sync(&priv->beacon_update);
3544 iwl_cancel_scan_deferred_work(priv);
3546 cancel_work_sync(&priv->bt_full_concurrency);
3547 cancel_work_sync(&priv->bt_runtime_config);
3549 del_timer_sync(&priv->statistics_periodic);
3550 del_timer_sync(&priv->ucode_trace);
3553 static void iwl_init_hw_rates(struct iwl_priv *priv,
3554 struct ieee80211_rate *rates)
3558 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3559 rates[i].bitrate = iwl_rates[i].ieee * 5;
3560 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3561 rates[i].hw_value_short = i;
3563 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3565 * If CCK != 1M then set short preamble rate flag.
3568 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3569 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3574 static int iwl_init_drv(struct iwl_priv *priv)
3578 spin_lock_init(&priv->sta_lock);
3579 spin_lock_init(&priv->hcmd_lock);
3581 INIT_LIST_HEAD(&priv->free_frames);
3583 mutex_init(&priv->mutex);
3585 priv->ieee_channels = NULL;
3586 priv->ieee_rates = NULL;
3587 priv->band = IEEE80211_BAND_2GHZ;
3589 priv->iw_mode = NL80211_IFTYPE_STATION;
3590 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3591 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3592 priv->_agn.agg_tids_count = 0;
3594 /* initialize force reset */
3595 priv->force_reset[IWL_RF_RESET].reset_duration =
3596 IWL_DELAY_NEXT_FORCE_RF_RESET;
3597 priv->force_reset[IWL_FW_RESET].reset_duration =
3598 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3600 priv->rx_statistics_jiffies = jiffies;
3602 /* Choose which receivers/antennas to use */
3603 if (priv->cfg->ops->hcmd->set_rxon_chain)
3604 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3605 &priv->contexts[IWL_RXON_CTX_BSS]);
3607 iwl_init_scan_params(priv);
3610 if (priv->cfg->bt_params &&
3611 priv->cfg->bt_params->advanced_bt_coexist) {
3612 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3613 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3614 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3615 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3616 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3617 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3620 /* Set the tx_power_user_lmt to the lowest power level
3621 * this value will get overwritten by channel max power avg
3623 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3624 priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3626 ret = iwl_init_channel_map(priv);
3628 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3632 ret = iwlcore_init_geos(priv);
3634 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3635 goto err_free_channel_map;
3637 iwl_init_hw_rates(priv, priv->ieee_rates);
3641 err_free_channel_map:
3642 iwl_free_channel_map(priv);
3647 static void iwl_uninit_drv(struct iwl_priv *priv)
3649 iwl_calib_free_results(priv);
3650 iwlcore_free_geos(priv);
3651 iwl_free_channel_map(priv);
3652 kfree(priv->scan_cmd);
3655 struct ieee80211_ops iwlagn_hw_ops = {
3656 .tx = iwlagn_mac_tx,
3657 .start = iwlagn_mac_start,
3658 .stop = iwlagn_mac_stop,
3659 .add_interface = iwl_mac_add_interface,
3660 .remove_interface = iwl_mac_remove_interface,
3661 .change_interface = iwl_mac_change_interface,
3662 .config = iwlagn_mac_config,
3663 .configure_filter = iwlagn_configure_filter,
3664 .set_key = iwlagn_mac_set_key,
3665 .update_tkip_key = iwlagn_mac_update_tkip_key,
3666 .conf_tx = iwl_mac_conf_tx,
3667 .bss_info_changed = iwlagn_bss_info_changed,
3668 .ampdu_action = iwlagn_mac_ampdu_action,
3669 .hw_scan = iwl_mac_hw_scan,
3670 .sta_notify = iwlagn_mac_sta_notify,
3671 .sta_add = iwlagn_mac_sta_add,
3672 .sta_remove = iwl_mac_sta_remove,
3673 .channel_switch = iwlagn_mac_channel_switch,
3674 .flush = iwlagn_mac_flush,
3675 .tx_last_beacon = iwl_mac_tx_last_beacon,
3676 .remain_on_channel = iwl_mac_remain_on_channel,
3677 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3678 .offchannel_tx = iwl_mac_offchannel_tx,
3679 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3682 static u32 iwl_hw_detect(struct iwl_priv *priv)
3686 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3687 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
3688 return iwl_read32(priv, CSR_HW_REV);
3691 static int iwl_set_hw_params(struct iwl_priv *priv)
3693 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3694 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3695 if (priv->cfg->mod_params->amsdu_size_8K)
3696 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3698 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3700 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3702 if (priv->cfg->mod_params->disable_11n)
3703 priv->cfg->sku &= ~IWL_SKU_N;
3705 /* Device-specific setup */
3706 return priv->cfg->ops->lib->set_hw_params(priv);
3709 static const u8 iwlagn_bss_ac_to_fifo[] = {
3716 static const u8 iwlagn_bss_ac_to_queue[] = {
3720 static const u8 iwlagn_pan_ac_to_fifo[] = {
3721 IWL_TX_FIFO_VO_IPAN,
3722 IWL_TX_FIFO_VI_IPAN,
3723 IWL_TX_FIFO_BE_IPAN,
3724 IWL_TX_FIFO_BK_IPAN,
3727 static const u8 iwlagn_pan_ac_to_queue[] = {
3731 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3734 struct iwl_priv *priv;
3735 struct ieee80211_hw *hw;
3736 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3737 unsigned long flags;
3738 u16 pci_cmd, num_mac;
3741 /************************
3742 * 1. Allocating HW data
3743 ************************/
3745 hw = iwl_alloc_all(cfg);
3751 /* At this point both hw and priv are allocated. */
3754 * The default context is always valid,
3755 * more may be discovered when firmware
3758 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3760 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3761 priv->contexts[i].ctxid = i;
3763 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3764 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3765 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3766 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3767 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3768 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3769 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3770 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3771 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3772 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3773 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3774 BIT(NL80211_IFTYPE_ADHOC);
3775 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3776 BIT(NL80211_IFTYPE_STATION);
3777 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3778 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3779 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3780 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3782 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3783 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3784 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3785 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3786 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3787 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3788 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3789 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3790 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3791 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3792 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3793 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3794 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3795 #ifdef CONFIG_IWL_P2P
3796 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3797 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3799 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3800 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3801 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3803 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3805 SET_IEEE80211_DEV(hw, &pdev->dev);
3807 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3809 priv->pci_dev = pdev;
3810 priv->inta_mask = CSR_INI_SET_MASK;
3812 /* is antenna coupling more than 35dB ? */
3813 priv->bt_ant_couple_ok =
3814 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3817 /* enable/disable bt channel inhibition */
3818 priv->bt_ch_announce = iwlagn_bt_ch_announce;
3819 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3820 (priv->bt_ch_announce) ? "On" : "Off");
3822 if (iwl_alloc_traffic_mem(priv))
3823 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3825 /**************************
3826 * 2. Initializing PCI bus
3827 **************************/
3828 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3829 PCIE_LINK_STATE_CLKPM);
3831 if (pci_enable_device(pdev)) {
3833 goto out_ieee80211_free_hw;
3836 pci_set_master(pdev);
3838 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3840 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3842 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3844 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3845 /* both attempts failed: */
3847 IWL_WARN(priv, "No suitable DMA available.\n");
3848 goto out_pci_disable_device;
3852 err = pci_request_regions(pdev, DRV_NAME);
3854 goto out_pci_disable_device;
3856 pci_set_drvdata(pdev, priv);
3859 /***********************
3860 * 3. Read REV register
3861 ***********************/
3862 priv->hw_base = pci_iomap(pdev, 0, 0);
3863 if (!priv->hw_base) {
3865 goto out_pci_release_regions;
3868 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3869 (unsigned long long) pci_resource_len(pdev, 0));
3870 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3872 /* these spin locks will be used in apm_ops.init and EEPROM access
3873 * we should init now
3875 spin_lock_init(&priv->reg_lock);
3876 spin_lock_init(&priv->lock);
3879 * stop and reset the on-board processor just in case it is in a
3880 * strange state ... like being left stranded by a primary kernel
3881 * and this is now the kdump kernel trying to start up
3883 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3885 hw_rev = iwl_hw_detect(priv);
3886 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3887 priv->cfg->name, hw_rev);
3889 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3890 * PCI Tx retries from interfering with C3 CPU state */
3891 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3893 iwl_prepare_card_hw(priv);
3894 if (!priv->hw_ready) {
3895 IWL_WARN(priv, "Failed, HW not ready\n");
3902 /* Read the EEPROM */
3903 err = iwl_eeprom_init(priv, hw_rev);
3905 IWL_ERR(priv, "Unable to init EEPROM\n");
3908 err = iwl_eeprom_check_version(priv);
3910 goto out_free_eeprom;
3912 err = iwl_eeprom_check_sku(priv);
3914 goto out_free_eeprom;
3916 /* extract MAC Address */
3917 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3918 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3919 priv->hw->wiphy->addresses = priv->addresses;
3920 priv->hw->wiphy->n_addresses = 1;
3921 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3923 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3925 priv->addresses[1].addr[5]++;
3926 priv->hw->wiphy->n_addresses++;
3929 /************************
3930 * 5. Setup HW constants
3931 ************************/
3932 if (iwl_set_hw_params(priv)) {
3933 IWL_ERR(priv, "failed to set hw parameters\n");
3934 goto out_free_eeprom;
3937 /*******************
3939 *******************/
3941 err = iwl_init_drv(priv);
3943 goto out_free_eeprom;
3944 /* At this point both hw and priv are initialized. */
3946 /********************
3948 ********************/
3949 spin_lock_irqsave(&priv->lock, flags);
3950 iwl_disable_interrupts(priv);
3951 spin_unlock_irqrestore(&priv->lock, flags);
3953 pci_enable_msi(priv->pci_dev);
3955 iwl_alloc_isr_ict(priv);
3957 err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
3958 IRQF_SHARED, DRV_NAME, priv);
3960 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3961 goto out_disable_msi;
3964 iwl_setup_deferred_work(priv);
3965 iwl_setup_rx_handlers(priv);
3967 /*********************************************
3968 * 8. Enable interrupts and read RFKILL state
3969 *********************************************/
3971 /* enable rfkill interrupt: hw bug w/a */
3972 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3973 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3974 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3975 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3978 iwl_enable_rfkill_int(priv);
3980 /* If platform's RF_KILL switch is NOT set to KILL */
3981 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3982 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3984 set_bit(STATUS_RF_KILL_HW, &priv->status);
3986 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3987 test_bit(STATUS_RF_KILL_HW, &priv->status));
3989 iwl_power_initialize(priv);
3990 iwl_tt_initialize(priv);
3992 init_completion(&priv->_agn.firmware_loading_complete);
3994 err = iwl_request_firmware(priv, true);
3996 goto out_destroy_workqueue;
4000 out_destroy_workqueue:
4001 destroy_workqueue(priv->workqueue);
4002 priv->workqueue = NULL;
4003 free_irq(priv->pci_dev->irq, priv);
4004 iwl_free_isr_ict(priv);
4006 pci_disable_msi(priv->pci_dev);
4007 iwl_uninit_drv(priv);
4009 iwl_eeprom_free(priv);
4011 pci_iounmap(pdev, priv->hw_base);
4012 out_pci_release_regions:
4013 pci_set_drvdata(pdev, NULL);
4014 pci_release_regions(pdev);
4015 out_pci_disable_device:
4016 pci_disable_device(pdev);
4017 out_ieee80211_free_hw:
4018 iwl_free_traffic_mem(priv);
4019 ieee80211_free_hw(priv->hw);
4024 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4026 struct iwl_priv *priv = pci_get_drvdata(pdev);
4027 unsigned long flags;
4032 wait_for_completion(&priv->_agn.firmware_loading_complete);
4034 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4036 iwl_dbgfs_unregister(priv);
4037 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4039 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4040 * to be called and iwl_down since we are removing the device
4041 * we need to set STATUS_EXIT_PENDING bit.
4043 set_bit(STATUS_EXIT_PENDING, &priv->status);
4045 iwl_leds_exit(priv);
4047 if (priv->mac80211_registered) {
4048 ieee80211_unregister_hw(priv->hw);
4049 priv->mac80211_registered = 0;
4055 * Make sure device is reset to low power before unloading driver.
4056 * This may be redundant with iwl_down(), but there are paths to
4057 * run iwl_down() without calling apm_ops.stop(), and there are
4058 * paths to avoid running iwl_down() at all before leaving driver.
4059 * This (inexpensive) call *makes sure* device is reset.
4065 /* make sure we flush any pending irq or
4066 * tasklet for the driver
4068 spin_lock_irqsave(&priv->lock, flags);
4069 iwl_disable_interrupts(priv);
4070 spin_unlock_irqrestore(&priv->lock, flags);
4072 iwl_synchronize_irq(priv);
4074 iwl_dealloc_ucode_pci(priv);
4077 iwlagn_rx_queue_free(priv, &priv->rxq);
4078 iwlagn_hw_txq_ctx_free(priv);
4080 iwl_eeprom_free(priv);
4083 /*netif_stop_queue(dev); */
4084 flush_workqueue(priv->workqueue);
4086 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4087 * priv->workqueue... so we can't take down the workqueue
4089 destroy_workqueue(priv->workqueue);
4090 priv->workqueue = NULL;
4091 iwl_free_traffic_mem(priv);
4093 free_irq(priv->pci_dev->irq, priv);
4094 pci_disable_msi(priv->pci_dev);
4095 pci_iounmap(pdev, priv->hw_base);
4096 pci_release_regions(pdev);
4097 pci_disable_device(pdev);
4098 pci_set_drvdata(pdev, NULL);
4100 iwl_uninit_drv(priv);
4102 iwl_free_isr_ict(priv);
4104 dev_kfree_skb(priv->beacon_skb);
4106 ieee80211_free_hw(priv->hw);
4110 /*****************************************************************************
4112 * driver and module entry point
4114 *****************************************************************************/
4116 /* Hardware specific file defines the PCI IDs table for that hardware module */
4117 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4118 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4119 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4120 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4121 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4122 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4123 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4124 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4125 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4126 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4127 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4128 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4129 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4130 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4131 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4132 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4133 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4134 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4135 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4136 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4137 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4138 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4139 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4140 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4141 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4143 /* 5300 Series WiFi */
4144 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4145 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4146 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4147 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4148 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4149 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4150 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4151 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4152 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4153 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4154 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4155 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4157 /* 5350 Series WiFi/WiMax */
4158 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4159 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4160 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4162 /* 5150 Series Wifi/WiMax */
4163 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4164 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4165 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4166 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4167 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4168 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4170 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4171 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4172 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4173 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4176 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4177 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4178 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4179 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4180 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4181 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4182 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4183 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4184 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4185 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4188 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4189 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4190 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4191 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4192 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4193 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4194 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4197 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4198 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4199 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4200 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4201 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4202 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4203 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4204 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4205 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4206 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4207 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4208 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4209 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4210 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4211 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4212 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4214 /* 6x50 WiFi/WiMax Series */
4215 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4216 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4217 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4218 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4219 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4220 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4222 /* 6150 WiFi/WiMax Series */
4223 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4224 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4225 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4226 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4227 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4228 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4230 /* 1000 Series WiFi */
4231 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4232 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4233 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4234 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4235 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4236 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4237 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4238 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4239 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4240 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4241 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4242 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4244 /* 100 Series WiFi */
4245 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4246 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4247 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4248 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4249 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4250 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4252 /* 130 Series WiFi */
4253 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4254 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4255 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4256 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4257 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4258 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4261 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4262 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4263 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4264 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4265 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4266 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4269 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4270 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4271 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4272 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4273 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4274 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4277 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4278 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4279 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4280 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4281 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4282 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4283 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4284 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4285 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4288 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4289 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4290 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4291 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4292 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4293 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4296 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4297 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4298 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4299 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4300 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4301 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4305 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4307 static struct pci_driver iwl_driver = {
4309 .id_table = iwl_hw_card_ids,
4310 .probe = iwl_pci_probe,
4311 .remove = __devexit_p(iwl_pci_remove),
4312 .driver.pm = IWL_PM_OPS,
4315 static int __init iwl_init(void)
4319 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4320 pr_info(DRV_COPYRIGHT "\n");
4322 ret = iwlagn_rate_control_register();
4324 pr_err("Unable to register rate control algorithm: %d\n", ret);
4328 ret = pci_register_driver(&iwl_driver);
4330 pr_err("Unable to initialize PCI module\n");
4331 goto error_register;
4337 iwlagn_rate_control_unregister();
4341 static void __exit iwl_exit(void)
4343 pci_unregister_driver(&iwl_driver);
4344 iwlagn_rate_control_unregister();
4347 module_exit(iwl_exit);
4348 module_init(iwl_init);
4350 #ifdef CONFIG_IWLWIFI_DEBUG
4351 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4352 MODULE_PARM_DESC(debug, "debug output mask");
4355 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4356 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4357 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4358 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4359 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4360 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4361 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4363 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4364 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4365 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4367 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4369 MODULE_PARM_DESC(ucode_alternative,
4370 "specify ucode alternative to use from ucode file");
4372 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4373 MODULE_PARM_DESC(antenna_coupling,
4374 "specify antenna coupling in dB (defualt: 0 dB)");
4376 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4377 MODULE_PARM_DESC(bt_ch_inhibition,
4378 "Disable BT channel inhibition (default: enable)");
4380 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4381 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4383 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4384 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");