1 /******************************************************************************
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
39 #include "iwl-helpers.h"
40 #include "iwl-agn-hw.h"
44 * mac80211 queues, ACs, hardware queues, FIFOs.
46 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
48 * Mac80211 uses the following numbers, which we get as from it
49 * by way of skb_get_queue_mapping(skb):
57 * Regular (not A-MPDU) frames are put into hardware queues corresponding
58 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
59 * own queue per aggregation session (RA/TID combination), such queues are
60 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
61 * order to map frames to the right queue, we also need an AC->hw queue
62 * mapping. This is implemented here.
64 * Due to the way hw queues are set up (by the hw specific modules like
65 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
69 static const u8 tid_to_ac[] = {
70 /* this matches the mac80211 numbers */
71 2, 3, 3, 2, 1, 1, 0, 0
74 static const u8 ac_to_fifo[] = {
81 static inline int get_fifo_from_ac(u8 ac)
83 return ac_to_fifo[ac];
86 static inline int get_ac_from_tid(u16 tid)
88 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
89 return tid_to_ac[tid];
91 /* no support for TIDs 8-15 yet */
95 static inline int get_fifo_from_tid(u16 tid)
97 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
98 return get_fifo_from_ac(tid_to_ac[tid]);
100 /* no support for TIDs 8-15 yet */
105 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
107 void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
108 struct iwl_tx_queue *txq,
111 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
112 int write_ptr = txq->q.write_ptr;
113 int txq_id = txq->q.id;
116 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
119 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
121 if (txq_id != IWL_CMD_QUEUE_NUM) {
122 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
123 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
125 switch (sec_ctl & TX_CMD_SEC_MSK) {
129 case TX_CMD_SEC_TKIP:
133 len += WEP_IV_LEN + WEP_ICV_LEN;
138 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
140 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
142 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
144 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
147 void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
148 struct iwl_tx_queue *txq)
150 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
151 int txq_id = txq->q.id;
152 int read_ptr = txq->q.read_ptr;
156 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
158 if (txq_id != IWL_CMD_QUEUE_NUM)
159 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
161 bc_ent = cpu_to_le16(1 | (sta_id << 12));
162 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
164 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
166 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
169 static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
176 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
178 tbl_dw_addr = priv->scd_base_addr +
179 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
181 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
184 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
186 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
188 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
193 static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
195 /* Simply stop the queue, but don't change any configuration;
196 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
198 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
199 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
200 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
203 void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
204 int txq_id, u32 index)
206 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
207 (index & 0xff) | (txq_id << 8));
208 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index);
211 void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
212 struct iwl_tx_queue *txq,
213 int tx_fifo_id, int scd_retry)
215 int txq_id = txq->q.id;
216 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
218 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
219 (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
220 (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) |
221 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) |
222 IWLAGN_SCD_QUEUE_STTS_REG_MSK);
224 txq->sched_retry = scd_retry;
226 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
227 active ? "Activate" : "Deactivate",
228 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
231 int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
232 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
237 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
238 (IWLAGN_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
241 "queue number out of range: %d, must be %d to %d\n",
242 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
243 IWLAGN_FIRST_AMPDU_QUEUE +
244 priv->cfg->num_of_ampdu_queues - 1);
248 ra_tid = BUILD_RAxTID(sta_id, tid);
250 /* Modify device's station table to Tx this TID */
251 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
253 spin_lock_irqsave(&priv->lock, flags);
255 /* Stop this Tx queue before configuring it */
256 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
258 /* Map receiver-address / traffic-ID to this queue */
259 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
261 /* Set this queue as a chain-building queue */
262 iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id));
264 /* enable aggregations for the queue */
265 iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id));
267 /* Place first TFD at index corresponding to start sequence number.
268 * Assumes that ssn_idx is valid (!= 0xFFF) */
269 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
270 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
271 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
273 /* Set up Tx window size and frame limit for this queue */
274 iwl_write_targ_mem(priv, priv->scd_base_addr +
275 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
278 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
279 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
281 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
282 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
284 iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
286 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
287 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
289 spin_unlock_irqrestore(&priv->lock, flags);
294 int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
295 u16 ssn_idx, u8 tx_fifo)
297 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
298 (IWLAGN_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
301 "queue number out of range: %d, must be %d to %d\n",
302 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
303 IWLAGN_FIRST_AMPDU_QUEUE +
304 priv->cfg->num_of_ampdu_queues - 1);
308 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
310 iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id));
312 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
313 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
314 /* supposes that ssn_idx is valid (!= 0xFFF) */
315 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
317 iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
318 iwl_txq_ctx_deactivate(priv, txq_id);
319 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
325 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
326 * must be called under priv->lock and mac access
328 void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
330 iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask);
333 static inline int get_queue_from_ac(u16 ac)
339 * handle build REPLY_TX command notification.
341 static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
342 struct iwl_tx_cmd *tx_cmd,
343 struct ieee80211_tx_info *info,
344 struct ieee80211_hdr *hdr,
347 __le16 fc = hdr->frame_control;
348 __le32 tx_flags = tx_cmd->tx_flags;
350 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
351 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
352 tx_flags |= TX_CMD_FLG_ACK_MSK;
353 if (ieee80211_is_mgmt(fc))
354 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
355 if (ieee80211_is_probe_resp(fc) &&
356 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
357 tx_flags |= TX_CMD_FLG_TSF_MSK;
359 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
360 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
363 if (ieee80211_is_back_req(fc))
364 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
367 tx_cmd->sta_id = std_id;
368 if (ieee80211_has_morefrags(fc))
369 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
371 if (ieee80211_is_data_qos(fc)) {
372 u8 *qc = ieee80211_get_qos_ctl(hdr);
373 tx_cmd->tid_tspec = qc[0] & 0xf;
374 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
376 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
379 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
381 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
382 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
384 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
385 if (ieee80211_is_mgmt(fc)) {
386 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
387 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
389 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
391 tx_cmd->timeout.pm_frame_timeout = 0;
394 tx_cmd->driver_txop = 0;
395 tx_cmd->tx_flags = tx_flags;
396 tx_cmd->next_frame_len = 0;
399 #define RTS_DFAULT_RETRY_LIMIT 60
401 static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv,
402 struct iwl_tx_cmd *tx_cmd,
403 struct ieee80211_tx_info *info,
412 /* Set retry limit on DATA packets and Probe Responses*/
413 if (ieee80211_is_probe_resp(fc))
414 data_retry_limit = 3;
416 data_retry_limit = IWLAGN_DEFAULT_TX_RETRY;
417 tx_cmd->data_retry_limit = data_retry_limit;
419 /* Set retry limit on RTS packets */
420 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
421 if (data_retry_limit < rts_retry_limit)
422 rts_retry_limit = data_retry_limit;
423 tx_cmd->rts_retry_limit = rts_retry_limit;
425 /* DATA packets will use the uCode station table for rate/antenna
427 if (ieee80211_is_data(fc)) {
428 tx_cmd->initial_rate_index = 0;
429 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
434 * If the current TX rate stored in mac80211 has the MCS bit set, it's
435 * not really a TX rate. Thus, we use the lowest supported rate for
436 * this band. Also use the lowest supported rate if the stored rate
439 rate_idx = info->control.rates[0].idx;
440 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
441 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
442 rate_idx = rate_lowest_index(&priv->bands[info->band],
444 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
445 if (info->band == IEEE80211_BAND_5GHZ)
446 rate_idx += IWL_FIRST_OFDM_RATE;
447 /* Get PLCP rate for tx_cmd->rate_n_flags */
448 rate_plcp = iwl_rates[rate_idx].plcp;
449 /* Zero out flags for this packet */
452 /* Set CCK flag as needed */
453 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
454 rate_flags |= RATE_MCS_CCK_MSK;
456 /* Set up RTS and CTS flags for certain packets */
457 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
458 case cpu_to_le16(IEEE80211_STYPE_AUTH):
459 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
460 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
461 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
462 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
463 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
464 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
471 /* Set up antennas */
472 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
473 priv->hw_params.valid_tx_ant);
474 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
476 /* Set the rate in the TX cmd */
477 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
480 static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
481 struct ieee80211_tx_info *info,
482 struct iwl_tx_cmd *tx_cmd,
483 struct sk_buff *skb_frag,
486 struct ieee80211_key_conf *keyconf = info->control.hw_key;
488 switch (keyconf->alg) {
490 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
491 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
492 if (info->flags & IEEE80211_TX_CTL_AMPDU)
493 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
494 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
498 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
499 ieee80211_get_tkip_key(keyconf, skb_frag,
500 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
501 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
505 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
506 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
508 if (keyconf->keylen == WEP_KEY_LEN_128)
509 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
511 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
513 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
514 "with key %d\n", keyconf->keyidx);
518 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
524 * start REPLY_TX command process
526 int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
528 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
529 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
530 struct ieee80211_sta *sta = info->control.sta;
531 struct iwl_station_priv *sta_priv = NULL;
532 struct iwl_tx_queue *txq;
534 struct iwl_device_cmd *out_cmd;
535 struct iwl_cmd_meta *out_meta;
536 struct iwl_tx_cmd *tx_cmd;
538 dma_addr_t phys_addr;
539 dma_addr_t txcmd_phys;
540 dma_addr_t scratch_phys;
541 u16 len, len_org, firstlen, secondlen;
546 u8 wait_write_ptr = 0;
551 spin_lock_irqsave(&priv->lock, flags);
552 if (iwl_is_rfkill(priv)) {
553 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
557 fc = hdr->frame_control;
559 #ifdef CONFIG_IWLWIFI_DEBUG
560 if (ieee80211_is_auth(fc))
561 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
562 else if (ieee80211_is_assoc_req(fc))
563 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
564 else if (ieee80211_is_reassoc_req(fc))
565 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
568 hdr_len = ieee80211_hdrlen(fc);
570 /* Find index into station table for destination station */
571 sta_id = iwl_sta_id_or_broadcast(priv, info->control.sta);
572 if (sta_id == IWL_INVALID_STATION) {
573 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
578 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
581 sta_priv = (void *)sta->drv_priv;
583 if (sta_priv && sta_id != priv->hw_params.bcast_sta_id &&
585 WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
587 * This sends an asynchronous command to the device,
588 * but we can rely on it being processed before the
589 * next frame is processed -- and the next frame to
590 * this station is the one that will consume this
592 * For now set the counter to just 1 since we do not
595 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
598 txq_id = get_queue_from_ac(skb_get_queue_mapping(skb));
600 /* irqs already disabled/saved above when locking priv->lock */
601 spin_lock(&priv->sta_lock);
603 if (ieee80211_is_data_qos(fc)) {
604 qc = ieee80211_get_qos_ctl(hdr);
605 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
606 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
607 spin_unlock(&priv->sta_lock);
610 seq_number = priv->stations[sta_id].tid[tid].seq_number;
611 seq_number &= IEEE80211_SCTL_SEQ;
612 hdr->seq_ctrl = hdr->seq_ctrl &
613 cpu_to_le16(IEEE80211_SCTL_FRAG);
614 hdr->seq_ctrl |= cpu_to_le16(seq_number);
616 /* aggregation is on for this <sta,tid> */
617 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
618 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
619 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
623 txq = &priv->txq[txq_id];
624 swq_id = txq->swq_id;
627 if (unlikely(iwl_queue_space(q) < q->high_mark)) {
628 spin_unlock(&priv->sta_lock);
632 if (ieee80211_is_data_qos(fc)) {
633 priv->stations[sta_id].tid[tid].tfds_in_queue++;
634 if (!ieee80211_has_morefrags(fc))
635 priv->stations[sta_id].tid[tid].seq_number = seq_number;
638 spin_unlock(&priv->sta_lock);
640 /* Set up driver data for this TFD */
641 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
642 txq->txb[q->write_ptr].skb = skb;
644 /* Set up first empty entry in queue's array of Tx/cmd buffers */
645 out_cmd = txq->cmd[q->write_ptr];
646 out_meta = &txq->meta[q->write_ptr];
647 tx_cmd = &out_cmd->cmd.tx;
648 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
649 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
652 * Set up the Tx-command (not MAC!) header.
653 * Store the chosen Tx queue and TFD index within the sequence field;
654 * after Tx, uCode's Tx response will return this value so driver can
655 * locate the frame within the tx queue and do post-tx processing.
657 out_cmd->hdr.cmd = REPLY_TX;
658 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
659 INDEX_TO_SEQ(q->write_ptr)));
661 /* Copy MAC header from skb into command buffer */
662 memcpy(tx_cmd->hdr, hdr, hdr_len);
665 /* Total # bytes to be transmitted */
667 tx_cmd->len = cpu_to_le16(len);
669 if (info->control.hw_key)
670 iwlagn_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
672 /* TODO need this for burst mode later on */
673 iwlagn_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
674 iwl_dbg_log_tx_data_frame(priv, len, hdr);
676 iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc);
678 iwl_update_stats(priv, true, fc, len);
680 * Use the first empty entry in this queue's command buffer array
681 * to contain the Tx command and MAC header concatenated together
682 * (payload data will be in another buffer).
683 * Size of this varies, due to varying MAC header length.
684 * If end is not dword aligned, we'll have 2 extra bytes at the end
685 * of the MAC header (device reads on dword boundaries).
686 * We'll tell device about this padding later.
688 len = sizeof(struct iwl_tx_cmd) +
689 sizeof(struct iwl_cmd_header) + hdr_len;
692 firstlen = len = (len + 3) & ~3;
699 /* Tell NIC about any 2-byte padding after MAC header */
701 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
703 /* Physical address of this Tx command's header (not MAC header!),
704 * within command buffer array. */
705 txcmd_phys = pci_map_single(priv->pci_dev,
707 PCI_DMA_BIDIRECTIONAL);
708 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
709 dma_unmap_len_set(out_meta, len, len);
710 /* Add buffer containing Tx command and MAC(!) header to TFD's
712 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
713 txcmd_phys, len, 1, 0);
715 if (!ieee80211_has_morefrags(hdr->frame_control)) {
716 txq->need_update = 1;
719 txq->need_update = 0;
722 /* Set up TFD's 2nd entry to point directly to remainder of skb,
723 * if any (802.11 null frames have no payload). */
724 secondlen = len = skb->len - hdr_len;
726 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
727 len, PCI_DMA_TODEVICE);
728 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
733 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
734 offsetof(struct iwl_tx_cmd, scratch);
736 len = sizeof(struct iwl_tx_cmd) +
737 sizeof(struct iwl_cmd_header) + hdr_len;
738 /* take back ownership of DMA buffer to enable update */
739 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
740 len, PCI_DMA_BIDIRECTIONAL);
741 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
742 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
744 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
745 le16_to_cpu(out_cmd->hdr.sequence));
746 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
747 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
748 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
750 /* Set up entry for this TFD in Tx byte-count array */
751 if (info->flags & IEEE80211_TX_CTL_AMPDU)
752 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
753 le16_to_cpu(tx_cmd->len));
755 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
756 len, PCI_DMA_BIDIRECTIONAL);
758 trace_iwlwifi_dev_tx(priv,
759 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
760 sizeof(struct iwl_tfd),
761 &out_cmd->hdr, firstlen,
762 skb->data + hdr_len, secondlen);
764 /* Tell device the write index *just past* this latest filled TFD */
765 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
766 iwl_txq_update_write_ptr(priv, txq);
767 spin_unlock_irqrestore(&priv->lock, flags);
770 * At this point the frame is "transmitted" successfully
771 * and we will get a TX status notification eventually,
772 * regardless of the value of ret. "ret" only indicates
773 * whether or not we should update the write pointer.
776 /* avoid atomic ops if it isn't an associated client */
777 if (sta_priv && sta_priv->client)
778 atomic_inc(&sta_priv->pending_frames);
780 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
781 if (wait_write_ptr) {
782 spin_lock_irqsave(&priv->lock, flags);
783 txq->need_update = 1;
784 iwl_txq_update_write_ptr(priv, txq);
785 spin_unlock_irqrestore(&priv->lock, flags);
787 iwl_stop_queue(priv, txq->swq_id);
794 spin_unlock_irqrestore(&priv->lock, flags);
798 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
799 struct iwl_dma_ptr *ptr, size_t size)
801 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
809 static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
810 struct iwl_dma_ptr *ptr)
812 if (unlikely(!ptr->addr))
815 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
816 memset(ptr, 0, sizeof(*ptr));
820 * iwlagn_hw_txq_ctx_free - Free TXQ Context
822 * Destroy all TX DMA queues and structures
824 void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv)
830 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
831 if (txq_id == IWL_CMD_QUEUE_NUM)
832 iwl_cmd_queue_free(priv);
834 iwl_tx_queue_free(priv, txq_id);
836 iwlagn_free_dma_ptr(priv, &priv->kw);
838 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
840 /* free tx queue structure */
841 iwl_free_txq_mem(priv);
845 * iwlagn_txq_ctx_alloc - allocate TX queue context
846 * Allocate all Tx DMA structures and initialize them
851 int iwlagn_txq_ctx_alloc(struct iwl_priv *priv)
854 int txq_id, slots_num;
857 /* Free all tx/cmd queues and keep-warm buffer */
858 iwlagn_hw_txq_ctx_free(priv);
860 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
861 priv->hw_params.scd_bc_tbls_size);
863 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
866 /* Alloc keep-warm buffer */
867 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
869 IWL_ERR(priv, "Keep Warm allocation failed\n");
873 /* allocate tx queue structure */
874 ret = iwl_alloc_txq_mem(priv);
878 spin_lock_irqsave(&priv->lock, flags);
880 /* Turn off all Tx DMA fifos */
881 priv->cfg->ops->lib->txq_set_sched(priv, 0);
883 /* Tell NIC where to find the "keep warm" buffer */
884 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
886 spin_unlock_irqrestore(&priv->lock, flags);
888 /* Alloc and init all Tx queues, including the command queue (#4) */
889 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
890 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
891 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
892 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
895 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
903 iwlagn_hw_txq_ctx_free(priv);
904 iwlagn_free_dma_ptr(priv, &priv->kw);
906 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
911 void iwlagn_txq_ctx_reset(struct iwl_priv *priv)
913 int txq_id, slots_num;
916 spin_lock_irqsave(&priv->lock, flags);
918 /* Turn off all Tx DMA fifos */
919 priv->cfg->ops->lib->txq_set_sched(priv, 0);
921 /* Tell NIC where to find the "keep warm" buffer */
922 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
924 spin_unlock_irqrestore(&priv->lock, flags);
926 /* Alloc and init all Tx queues, including the command queue (#4) */
927 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
928 slots_num = txq_id == IWL_CMD_QUEUE_NUM ?
929 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
930 iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id);
935 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
937 void iwlagn_txq_ctx_stop(struct iwl_priv *priv)
942 /* Turn off all Tx DMA fifos */
943 spin_lock_irqsave(&priv->lock, flags);
945 priv->cfg->ops->lib->txq_set_sched(priv, 0);
947 /* Stop each Tx DMA channel, and wait for it to be idle */
948 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
949 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
950 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
951 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
954 spin_unlock_irqrestore(&priv->lock, flags);
958 * Find first available (lowest unused) Tx Queue, mark it "active".
959 * Called only when finding queue for aggregation.
960 * Should never return anything < 7, because they should already
961 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
963 static int iwlagn_txq_ctx_activate_free(struct iwl_priv *priv)
967 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
968 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
973 int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
974 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
981 struct iwl_tid_data *tid_data;
983 tx_fifo = get_fifo_from_tid(tid);
984 if (unlikely(tx_fifo < 0))
987 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
988 __func__, sta->addr, tid);
990 sta_id = iwl_sta_id(sta);
991 if (sta_id == IWL_INVALID_STATION) {
992 IWL_ERR(priv, "Start AGG on invalid station\n");
995 if (unlikely(tid >= MAX_TID_COUNT))
998 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
999 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1003 txq_id = iwlagn_txq_ctx_activate_free(priv);
1005 IWL_ERR(priv, "No free aggregation queue available\n");
1009 spin_lock_irqsave(&priv->sta_lock, flags);
1010 tid_data = &priv->stations[sta_id].tid[tid];
1011 *ssn = SEQ_TO_SN(tid_data->seq_number);
1012 tid_data->agg.txq_id = txq_id;
1013 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(get_ac_from_tid(tid), txq_id);
1014 spin_unlock_irqrestore(&priv->sta_lock, flags);
1016 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1021 spin_lock_irqsave(&priv->sta_lock, flags);
1022 tid_data = &priv->stations[sta_id].tid[tid];
1023 if (tid_data->tfds_in_queue == 0) {
1024 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1025 tid_data->agg.state = IWL_AGG_ON;
1026 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1028 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1029 tid_data->tfds_in_queue);
1030 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1032 spin_unlock_irqrestore(&priv->sta_lock, flags);
1036 int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
1037 struct ieee80211_sta *sta, u16 tid)
1039 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1040 struct iwl_tid_data *tid_data;
1041 int write_ptr, read_ptr;
1042 unsigned long flags;
1044 tx_fifo_id = get_fifo_from_tid(tid);
1045 if (unlikely(tx_fifo_id < 0))
1048 sta_id = iwl_sta_id(sta);
1050 if (sta_id == IWL_INVALID_STATION) {
1051 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1055 spin_lock_irqsave(&priv->sta_lock, flags);
1057 if (priv->stations[sta_id].tid[tid].agg.state ==
1058 IWL_EMPTYING_HW_QUEUE_ADDBA) {
1059 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1060 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1061 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1062 spin_unlock_irqrestore(&priv->sta_lock, flags);
1066 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1067 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1069 tid_data = &priv->stations[sta_id].tid[tid];
1070 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1071 txq_id = tid_data->agg.txq_id;
1072 write_ptr = priv->txq[txq_id].q.write_ptr;
1073 read_ptr = priv->txq[txq_id].q.read_ptr;
1075 /* The queue is not empty */
1076 if (write_ptr != read_ptr) {
1077 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1078 priv->stations[sta_id].tid[tid].agg.state =
1079 IWL_EMPTYING_HW_QUEUE_DELBA;
1080 spin_unlock_irqrestore(&priv->sta_lock, flags);
1084 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1085 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1087 /* do not restore/save irqs */
1088 spin_unlock(&priv->sta_lock);
1089 spin_lock(&priv->lock);
1092 * the only reason this call can fail is queue number out of range,
1093 * which can happen if uCode is reloaded and all the station
1094 * information are lost. if it is outside the range, there is no need
1095 * to deactivate the uCode queue, just return "success" to allow
1096 * mac80211 to clean up it own data.
1098 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1100 spin_unlock_irqrestore(&priv->lock, flags);
1102 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1107 int iwlagn_txq_check_empty(struct iwl_priv *priv,
1108 int sta_id, u8 tid, int txq_id)
1110 struct iwl_queue *q = &priv->txq[txq_id].q;
1111 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1112 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1114 WARN_ON(!spin_is_locked(&priv->sta_lock));
1116 switch (priv->stations[sta_id].tid[tid].agg.state) {
1117 case IWL_EMPTYING_HW_QUEUE_DELBA:
1118 /* We are reclaiming the last packet of the */
1119 /* aggregated HW queue */
1120 if ((txq_id == tid_data->agg.txq_id) &&
1121 (q->read_ptr == q->write_ptr)) {
1122 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1123 int tx_fifo = get_fifo_from_tid(tid);
1124 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1125 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1127 tid_data->agg.state = IWL_AGG_OFF;
1128 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1131 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1132 /* We are reclaiming the last packet of the queue */
1133 if (tid_data->tfds_in_queue == 0) {
1134 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1135 tid_data->agg.state = IWL_AGG_ON;
1136 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1144 static void iwlagn_tx_status(struct iwl_priv *priv, struct sk_buff *skb)
1146 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1147 struct ieee80211_sta *sta;
1148 struct iwl_station_priv *sta_priv;
1150 sta = ieee80211_find_sta(priv->vif, hdr->addr1);
1152 sta_priv = (void *)sta->drv_priv;
1153 /* avoid atomic ops if this isn't a client */
1154 if (sta_priv->client &&
1155 atomic_dec_return(&sta_priv->pending_frames) == 0)
1156 ieee80211_sta_block_awake(priv->hw, sta, false);
1159 ieee80211_tx_status_irqsafe(priv->hw, skb);
1162 int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1164 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1165 struct iwl_queue *q = &txq->q;
1166 struct iwl_tx_info *tx_info;
1168 struct ieee80211_hdr *hdr;
1170 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1171 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1172 "is out of range [0-%d] %d %d.\n", txq_id,
1173 index, q->n_bd, q->write_ptr, q->read_ptr);
1177 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1178 q->read_ptr != index;
1179 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1181 tx_info = &txq->txb[txq->q.read_ptr];
1182 iwlagn_tx_status(priv, tx_info->skb);
1184 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1185 if (hdr && ieee80211_is_data_qos(hdr->frame_control))
1187 tx_info->skb = NULL;
1189 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1190 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1192 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1198 * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack
1200 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1201 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1203 static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1204 struct iwl_ht_agg *agg,
1205 struct iwl_compressed_ba_resp *ba_resp)
1209 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1210 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1213 struct ieee80211_tx_info *info;
1215 if (unlikely(!agg->wait_for_ba)) {
1216 IWL_ERR(priv, "Received BA when not expected\n");
1220 /* Mark that the expected block-ack response arrived */
1221 agg->wait_for_ba = 0;
1222 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1224 /* Calculate shift to align block-ack bits with our Tx window bits */
1225 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1226 if (sh < 0) /* tbw something is wrong with indices */
1229 /* don't use 64-bit values for now */
1230 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1232 if (agg->frame_count > (64 - sh)) {
1233 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1237 /* check for success or failure according to the
1238 * transmitted bitmap and block-ack bitmap */
1239 bitmap &= agg->bitmap;
1241 /* For each frame attempted in aggregation,
1242 * update driver's record of tx frame's status. */
1243 for (i = 0; i < agg->frame_count ; i++) {
1244 ack = bitmap & (1ULL << i);
1246 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1247 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1248 agg->start_idx + i);
1251 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb);
1252 memset(&info->status, 0, sizeof(info->status));
1253 info->flags |= IEEE80211_TX_STAT_ACK;
1254 info->flags |= IEEE80211_TX_STAT_AMPDU;
1255 info->status.ampdu_ack_len = successes;
1256 info->status.ampdu_len = agg->frame_count;
1257 iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1259 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1265 * translate ucode response to mac80211 tx status control values
1267 void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
1268 struct ieee80211_tx_info *info)
1270 struct ieee80211_tx_rate *r = &info->control.rates[0];
1272 info->antenna_sel_tx =
1273 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
1274 if (rate_n_flags & RATE_MCS_HT_MSK)
1275 r->flags |= IEEE80211_TX_RC_MCS;
1276 if (rate_n_flags & RATE_MCS_GF_MSK)
1277 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
1278 if (rate_n_flags & RATE_MCS_HT40_MSK)
1279 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
1280 if (rate_n_flags & RATE_MCS_DUP_MSK)
1281 r->flags |= IEEE80211_TX_RC_DUP_DATA;
1282 if (rate_n_flags & RATE_MCS_SGI_MSK)
1283 r->flags |= IEEE80211_TX_RC_SHORT_GI;
1284 r->idx = iwlagn_hwrate_to_mac80211_idx(rate_n_flags, info->band);
1288 * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1290 * Handles block-acknowledge notification from device, which reports success
1291 * of frames sent via aggregation.
1293 void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
1294 struct iwl_rx_mem_buffer *rxb)
1296 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1297 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1298 struct iwl_tx_queue *txq = NULL;
1299 struct iwl_ht_agg *agg;
1303 unsigned long flags;
1305 /* "flow" corresponds to Tx queue */
1306 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1308 /* "ssn" is start of block-ack Tx window, corresponds to index
1309 * (in Tx queue's circular buffer) of first TFD/frame in window */
1310 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1312 if (scd_flow >= priv->hw_params.max_txq_num) {
1314 "BUG_ON scd_flow is bigger than number of queues\n");
1318 txq = &priv->txq[scd_flow];
1319 sta_id = ba_resp->sta_id;
1321 agg = &priv->stations[sta_id].tid[tid].agg;
1323 /* Find index just before block-ack window */
1324 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1326 spin_lock_irqsave(&priv->sta_lock, flags);
1328 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1331 (u8 *) &ba_resp->sta_addr_lo32,
1333 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1334 "%d, scd_ssn = %d\n",
1337 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1340 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx\n",
1342 (unsigned long long)agg->bitmap);
1344 /* Update driver's record of ACK vs. not for each frame in window */
1345 iwlagn_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1347 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1348 * block-ack window (we assume that they've been successfully
1349 * transmitted ... if not, it's too late anyway). */
1350 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1351 /* calculate mac80211 ampdu sw queue to wake */
1352 int freed = iwlagn_tx_queue_reclaim(priv, scd_flow, index);
1353 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1355 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1356 priv->mac80211_registered &&
1357 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1358 iwl_wake_queue(priv, txq->swq_id);
1360 iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow);
1363 spin_unlock_irqrestore(&priv->sta_lock, flags);