drivers/net/wireless/iwlwifi/iwl-agn-lib.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/sched.h>
  34
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-helpers.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-agn.h"
  41 #include "iwl-sta.h"
  42
  43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
  44 {
  45         return le32_to_cpup((__le32 *)&tx_resp->status +
  46                             tx_resp->frame_count) & MAX_SN;
  47 }
  48
  49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
  50 {
  51         status &= TX_STATUS_MSK;
  52
  53         switch (status) {
  54         case TX_STATUS_POSTPONE_DELAY:
  55                 priv->_agn.reply_tx_stats.pp_delay++;
  56                 break;
  57         case TX_STATUS_POSTPONE_FEW_BYTES:
  58                 priv->_agn.reply_tx_stats.pp_few_bytes++;
  59                 break;
  60         case TX_STATUS_POSTPONE_BT_PRIO:
  61                 priv->_agn.reply_tx_stats.pp_bt_prio++;
  62                 break;
  63         case TX_STATUS_POSTPONE_QUIET_PERIOD:
  64                 priv->_agn.reply_tx_stats.pp_quiet_period++;
  65                 break;
  66         case TX_STATUS_POSTPONE_CALC_TTAK:
  67                 priv->_agn.reply_tx_stats.pp_calc_ttak++;
  68                 break;
  69         case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
  70                 priv->_agn.reply_tx_stats.int_crossed_retry++;
  71                 break;
  72         case TX_STATUS_FAIL_SHORT_LIMIT:
  73                 priv->_agn.reply_tx_stats.short_limit++;
  74                 break;
  75         case TX_STATUS_FAIL_LONG_LIMIT:
  76                 priv->_agn.reply_tx_stats.long_limit++;
  77                 break;
  78         case TX_STATUS_FAIL_FIFO_UNDERRUN:
  79                 priv->_agn.reply_tx_stats.fifo_underrun++;
  80                 break;
  81         case TX_STATUS_FAIL_DRAIN_FLOW:
  82                 priv->_agn.reply_tx_stats.drain_flow++;
  83                 break;
  84         case TX_STATUS_FAIL_RFKILL_FLUSH:
  85                 priv->_agn.reply_tx_stats.rfkill_flush++;
  86                 break;
  87         case TX_STATUS_FAIL_LIFE_EXPIRE:
  88                 priv->_agn.reply_tx_stats.life_expire++;
  89                 break;
  90         case TX_STATUS_FAIL_DEST_PS:
  91                 priv->_agn.reply_tx_stats.dest_ps++;
  92                 break;
  93         case TX_STATUS_FAIL_HOST_ABORTED:
  94                 priv->_agn.reply_tx_stats.host_abort++;
  95                 break;
  96         case TX_STATUS_FAIL_BT_RETRY:
  97                 priv->_agn.reply_tx_stats.bt_retry++;
  98                 break;
  99         case TX_STATUS_FAIL_STA_INVALID:
 100                 priv->_agn.reply_tx_stats.sta_invalid++;
 101                 break;
 102         case TX_STATUS_FAIL_FRAG_DROPPED:
 103                 priv->_agn.reply_tx_stats.frag_drop++;
 104                 break;
 105         case TX_STATUS_FAIL_TID_DISABLE:
 106                 priv->_agn.reply_tx_stats.tid_disable++;
 107                 break;
 108         case TX_STATUS_FAIL_FIFO_FLUSHED:
 109                 priv->_agn.reply_tx_stats.fifo_flush++;
 110                 break;
 111         case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
 112                 priv->_agn.reply_tx_stats.insuff_cf_poll++;
 113                 break;
 114         case TX_STATUS_FAIL_PASSIVE_NO_RX:
 115                 priv->_agn.reply_tx_stats.fail_hw_drop++;
 116                 break;
 117         case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
 118                 priv->_agn.reply_tx_stats.sta_color_mismatch++;
 119                 break;
 120         default:
 121                 priv->_agn.reply_tx_stats.unknown++;
 122                 break;
 123         }
 124 }
 125
 126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
 127 {
 128         status &= AGG_TX_STATUS_MSK;
 129
 130         switch (status) {
 131         case AGG_TX_STATE_UNDERRUN_MSK:
 132                 priv->_agn.reply_agg_tx_stats.underrun++;
 133                 break;
 134         case AGG_TX_STATE_BT_PRIO_MSK:
 135                 priv->_agn.reply_agg_tx_stats.bt_prio++;
 136                 break;
 137         case AGG_TX_STATE_FEW_BYTES_MSK:
 138                 priv->_agn.reply_agg_tx_stats.few_bytes++;
 139                 break;
 140         case AGG_TX_STATE_ABORT_MSK:
 141                 priv->_agn.reply_agg_tx_stats.abort++;
 142                 break;
 143         case AGG_TX_STATE_LAST_SENT_TTL_MSK:
 144                 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
 145                 break;
 146         case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
 147                 priv->_agn.reply_agg_tx_stats.last_sent_try++;
 148                 break;
 149         case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
 150                 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
 151                 break;
 152         case AGG_TX_STATE_SCD_QUERY_MSK:
 153                 priv->_agn.reply_agg_tx_stats.scd_query++;
 154                 break;
 155         case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
 156                 priv->_agn.reply_agg_tx_stats.bad_crc32++;
 157                 break;
 158         case AGG_TX_STATE_RESPONSE_MSK:
 159                 priv->_agn.reply_agg_tx_stats.response++;
 160                 break;
 161         case AGG_TX_STATE_DUMP_TX_MSK:
 162                 priv->_agn.reply_agg_tx_stats.dump_tx++;
 163                 break;
 164         case AGG_TX_STATE_DELAY_TX_MSK:
 165                 priv->_agn.reply_agg_tx_stats.delay_tx++;
 166                 break;
 167         default:
 168                 priv->_agn.reply_agg_tx_stats.unknown++;
 169                 break;
 170         }
 171 }
 172
 173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
 174                                  struct ieee80211_tx_info *info,
 175                                  struct iwl_rxon_context *ctx,
 176                                  struct iwlagn_tx_resp *tx_resp,
 177                                  int txq_id, bool is_agg)
 178 {
 179         u16  status = le16_to_cpu(tx_resp->status.status);
 180
 181         info->status.rates[0].count = tx_resp->failure_frame + 1;
 182         if (is_agg)
 183                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 184         info->flags |= iwl_tx_status_to_mac80211(status);
 185         iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
 186                                     info);
 187         if (!iwl_is_tx_success(status))
 188                 iwlagn_count_tx_err_status(priv, status);
 189
 190         if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&
 191             iwl_is_associated_ctx(ctx) && ctx->vif &&
 192             ctx->vif->type == NL80211_IFTYPE_STATION) {
 193                 ctx->last_tx_rejected = true;
 194                 iwl_stop_queue(priv, &priv->txq[txq_id]);
 195         }
 196
 197         IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
 198                            "0x%x retries %d\n",
 199                            txq_id,
 200                            iwl_get_tx_fail_reason(status), status,
 201                            le32_to_cpu(tx_resp->rate_n_flags),
 202                            tx_resp->failure_frame);
 203 }
 204
 205 #ifdef CONFIG_IWLWIFI_DEBUG
 206 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
 207
 208 const char *iwl_get_agg_tx_fail_reason(u16 status)
 209 {
 210         status &= AGG_TX_STATUS_MSK;
 211         switch (status) {
 212         case AGG_TX_STATE_TRANSMITTED:
 213                 return "SUCCESS";
 214                 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
 215                 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
 216                 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
 217                 AGG_TX_STATE_FAIL(ABORT_MSK);
 218                 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
 219                 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
 220                 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
 221                 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
 222                 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
 223                 AGG_TX_STATE_FAIL(RESPONSE_MSK);
 224                 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
 225                 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
 226         }
 227
 228         return "UNKNOWN";
 229 }
 230 #endif /* CONFIG_IWLWIFI_DEBUG */
 231
 232 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
 233                                       struct iwl_ht_agg *agg,
 234                                       struct iwlagn_tx_resp *tx_resp,
 235                                       int txq_id, u16 start_idx)
 236 {
 237         u16 status;
 238         struct agg_tx_status *frame_status = &tx_resp->status;
 239         struct ieee80211_hdr *hdr = NULL;
 240         int i, sh, idx;
 241         u16 seq;
 242
 243         if (agg->wait_for_ba)
 244                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 245
 246         agg->frame_count = tx_resp->frame_count;
 247         agg->start_idx = start_idx;
 248         agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 249         agg->bitmap = 0;
 250
 251         /* # frames attempted by Tx command */
 252         if (agg->frame_count == 1) {
 253                 struct iwl_tx_info *txb;
 254
 255                 /* Only one frame was attempted; no block-ack will arrive */
 256                 idx = start_idx;
 257
 258                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 259                                    agg->frame_count, agg->start_idx, idx);
 260                 txb = &priv->txq[txq_id].txb[idx];
 261                 iwlagn_set_tx_status(priv, IEEE80211_SKB_CB(txb->skb),
 262                                      txb->ctx, tx_resp, txq_id, true);
 263                 agg->wait_for_ba = 0;
 264         } else {
 265                 /* Two or more frames were attempted; expect block-ack */
 266                 u64 bitmap = 0;
 267
 268                 /*
 269                  * Start is the lowest frame sent. It may not be the first
 270                  * frame in the batch; we figure this out dynamically during
 271                  * the following loop.
 272                  */
 273                 int start = agg->start_idx;
 274
 275                 /* Construct bit-map of pending frames within Tx window */
 276                 for (i = 0; i < agg->frame_count; i++) {
 277                         u16 sc;
 278                         status = le16_to_cpu(frame_status[i].status);
 279                         seq  = le16_to_cpu(frame_status[i].sequence);
 280                         idx = SEQ_TO_INDEX(seq);
 281                         txq_id = SEQ_TO_QUEUE(seq);
 282
 283                         if (status & AGG_TX_STATUS_MSK)
 284                                 iwlagn_count_agg_tx_err_status(priv, status);
 285
 286                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
 287                                       AGG_TX_STATE_ABORT_MSK))
 288                                 continue;
 289
 290                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
 291                                            agg->frame_count, txq_id, idx);
 292                         IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
 293                                            "try-count (0x%08x)\n",
 294                                            iwl_get_agg_tx_fail_reason(status),
 295                                            status & AGG_TX_STATUS_MSK,
 296                                            status & AGG_TX_TRY_MSK);
 297
 298                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
 299                         if (!hdr) {
 300                                 IWL_ERR(priv,
 301                                         "BUG_ON idx doesn't point to valid skb"
 302                                         " idx=%d, txq_id=%d\n", idx, txq_id);
 303                                 return -1;
 304                         }
 305
 306                         sc = le16_to_cpu(hdr->seq_ctrl);
 307                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
 308                                 IWL_ERR(priv,
 309                                         "BUG_ON idx doesn't match seq control"
 310                                         " idx=%d, seq_idx=%d, seq=%d\n",
 311                                           idx, SEQ_TO_SN(sc),
 312                                           hdr->seq_ctrl);
 313                                 return -1;
 314                         }
 315
 316                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
 317                                            i, idx, SEQ_TO_SN(sc));
 318
 319                         /*
 320                          * sh -> how many frames ahead of the starting frame is
 321                          * the current one?
 322                          *
 323                          * Note that all frames sent in the batch must be in a
 324                          * 64-frame window, so this number should be in [0,63].
 325                          * If outside of this window, then we've found a new
 326                          * "first" frame in the batch and need to change start.
 327                          */
 328                         sh = idx - start;
 329
 330                         /*
 331                          * If >= 64, out of window. start must be at the front
 332                          * of the circular buffer, idx must be near the end of
 333                          * the buffer, and idx is the new "first" frame. Shift
 334                          * the indices around.
 335                          */
 336                         if (sh >= 64) {
 337                                 /* Shift bitmap by start - idx, wrapped */
 338                                 sh = 0x100 - idx + start;
 339                                 bitmap = bitmap << sh;
 340                                 /* Now idx is the new start so sh = 0 */
 341                                 sh = 0;
 342                                 start = idx;
 343                         /*
 344                          * If <= -64 then wraps the 256-pkt circular buffer
 345                          * (e.g., start = 255 and idx = 0, sh should be 1)
 346                          */
 347                         } else if (sh <= -64) {
 348                                 sh  = 0x100 - start + idx;
 349                         /*
 350                          * If < 0 but > -64, out of window. idx is before start
 351                          * but not wrapped. Shift the indices around.
 352                          */
 353                         } else if (sh < 0) {
 354                                 /* Shift by how far start is ahead of idx */
 355                                 sh = start - idx;
 356                                 bitmap = bitmap << sh;
 357                                 /* Now idx is the new start so sh = 0 */
 358                                 start = idx;
 359                                 sh = 0;
 360                         }
 361                         /* Sequence number start + sh was sent in this batch */
 362                         bitmap |= 1ULL << sh;
 363                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
 364                                            start, (unsigned long long)bitmap);
 365                 }
 366
 367                 /*
 368                  * Store the bitmap and possibly the new start, if we wrapped
 369                  * the buffer above
 370                  */
 371                 agg->bitmap = bitmap;
 372                 agg->start_idx = start;
 373                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
 374                                    agg->frame_count, agg->start_idx,
 375                                    (unsigned long long)agg->bitmap);
 376
 377                 if (bitmap)
 378                         agg->wait_for_ba = 1;
 379         }
 380         return 0;
 381 }
 382
 383 void iwl_check_abort_status(struct iwl_priv *priv,
 384                             u8 frame_count, u32 status)
 385 {
 386         if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
 387                 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
 388                 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 389                         queue_work(priv->workqueue, &priv->tx_flush);
 390         }
 391 }
 392
 393 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
 394                                 struct iwl_rx_mem_buffer *rxb)
 395 {
 396         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 397         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 398         int txq_id = SEQ_TO_QUEUE(sequence);
 399         int index = SEQ_TO_INDEX(sequence);
 400         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 401         struct ieee80211_tx_info *info;
 402         struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 403         struct iwl_tx_info *txb;
 404         u32 status = le16_to_cpu(tx_resp->status.status);
 405         int tid;
 406         int sta_id;
 407         int freed;
 408         unsigned long flags;
 409
 410         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 411                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 412                           "is out of range [0-%d] %d %d\n", txq_id,
 413                           index, txq->q.n_bd, txq->q.write_ptr,
 414                           txq->q.read_ptr);
 415                 return;
 416         }
 417
 418         txq->time_stamp = jiffies;
 419         txb = &txq->txb[txq->q.read_ptr];
 420         info = IEEE80211_SKB_CB(txb->skb);
 421         memset(&info->status, 0, sizeof(info->status));
 422
 423         tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
 424                 IWLAGN_TX_RES_TID_POS;
 425         sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
 426                 IWLAGN_TX_RES_RA_POS;
 427
 428         spin_lock_irqsave(&priv->sta_lock, flags);
 429         if (txq->sched_retry) {
 430                 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
 431                 struct iwl_ht_agg *agg;
 432
 433                 agg = &priv->stations[sta_id].tid[tid].agg;
 434                 /*
 435                  * If the BT kill count is non-zero, we'll get this
 436                  * notification again.
 437                  */
 438                 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
 439                     priv->cfg->bt_params &&
 440                     priv->cfg->bt_params->advanced_bt_coexist) {
 441                         IWL_WARN(priv, "receive reply tx with bt_kill\n");
 442                 }
 443                 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
 444
 445                 /* check if BAR is needed */
 446                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
 447                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
 448
 449                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
 450                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
 451                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
 452                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
 453                                         scd_ssn , index, txq_id, txq->swq_id);
 454
 455                         freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 456                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 457
 458                         if (priv->mac80211_registered &&
 459                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
 460                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
 461                                 iwl_wake_queue(priv, txq);
 462                 }
 463         } else {
 464                 iwlagn_set_tx_status(priv, info, txb->ctx, tx_resp,
 465                                      txq_id, false);
 466                 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 467                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 468
 469                 if (priv->mac80211_registered &&
 470                     iwl_queue_space(&txq->q) > txq->q.low_mark &&
 471                     status != TX_STATUS_FAIL_PASSIVE_NO_RX)
 472                         iwl_wake_queue(priv, txq);
 473         }
 474
 475         iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
 476
 477         iwl_check_abort_status(priv, tx_resp->frame_count, status);
 478         spin_unlock_irqrestore(&priv->sta_lock, flags);
 479 }
 480
 481 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
 482 {
 483         /* init calibration handlers */
 484         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
 485                                         iwlagn_rx_calib_result;
 486         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
 487                                         iwlagn_rx_calib_complete;
 488         priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
 489
 490         /* set up notification wait support */
 491         spin_lock_init(&priv->_agn.notif_wait_lock);
 492         INIT_LIST_HEAD(&priv->_agn.notif_waits);
 493         init_waitqueue_head(&priv->_agn.notif_waitq);
 494 }
 495
 496 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
 497 {
 498         /*
 499          * nothing need to be done here anymore
 500          * still keep for future use if needed
 501          */
 502 }
 503
 504 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
 505 {
 506         return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
 507                 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
 508 }
 509
 510 int iwlagn_send_tx_power(struct iwl_priv *priv)
 511 {
 512         struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
 513         u8 tx_ant_cfg_cmd;
 514
 515         if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
 516                       "TX Power requested while scanning!\n"))
 517                 return -EAGAIN;
 518
 519         /* half dBm need to multiply */
 520         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
 521
 522         if (priv->tx_power_lmt_in_half_dbm &&
 523             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
 524                 /*
 525                  * For the newer devices which using enhanced/extend tx power
 526                  * table in EEPROM, the format is in half dBm. driver need to
 527                  * convert to dBm format before report to mac80211.
 528                  * By doing so, there is a possibility of 1/2 dBm resolution
 529                  * lost. driver will perform "round-up" operation before
 530                  * reporting, but it will cause 1/2 dBm tx power over the
 531                  * regulatory limit. Perform the checking here, if the
 532                  * "tx_power_user_lmt" is higher than EEPROM value (in
 533                  * half-dBm format), lower the tx power based on EEPROM
 534                  */
 535                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
 536         }
 537         tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
 538         tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
 539
 540         if (IWL_UCODE_API(priv->ucode_ver) == 1)
 541                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
 542         else
 543                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
 544
 545         return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
 546                                 &tx_power_cmd);
 547 }
 548
 549 void iwlagn_temperature(struct iwl_priv *priv)
 550 {
 551         /* store temperature from correct statistics (in Celsius) */
 552         priv->temperature = le32_to_cpu((iwl_bt_statistics(priv)) ?
 553                 priv->_agn.statistics_bt.general.common.temperature :
 554                 priv->_agn.statistics.general.common.temperature);
 555         iwl_tt_handler(priv);
 556 }
 557
 558 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
 559 {
 560         struct iwl_eeprom_calib_hdr {
 561                 u8 version;
 562                 u8 pa_type;
 563                 u16 voltage;
 564         } *hdr;
 565
 566         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 567                                                         EEPROM_CALIB_ALL);
 568         return hdr->version;
 569
 570 }
 571
 572 /*
 573  * EEPROM
 574  */
 575 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 576 {
 577         u16 offset = 0;
 578
 579         if ((address & INDIRECT_ADDRESS) == 0)
 580                 return address;
 581
 582         switch (address & INDIRECT_TYPE_MSK) {
 583         case INDIRECT_HOST:
 584                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
 585                 break;
 586         case INDIRECT_GENERAL:
 587                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
 588                 break;
 589         case INDIRECT_REGULATORY:
 590                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
 591                 break;
 592         case INDIRECT_TXP_LIMIT:
 593                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
 594                 break;
 595         case INDIRECT_TXP_LIMIT_SIZE:
 596                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
 597                 break;
 598         case INDIRECT_CALIBRATION:
 599                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
 600                 break;
 601         case INDIRECT_PROCESS_ADJST:
 602                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
 603                 break;
 604         case INDIRECT_OTHERS:
 605                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
 606                 break;
 607         default:
 608                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 609                 address & INDIRECT_TYPE_MSK);
 610                 break;
 611         }
 612
 613         /* translate the offset from words to byte */
 614         return (address & ADDRESS_MSK) + (offset << 1);
 615 }
 616
 617 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
 618                                            size_t offset)
 619 {
 620         u32 address = eeprom_indirect_address(priv, offset);
 621         BUG_ON(address >= priv->cfg->base_params->eeprom_size);
 622         return &priv->eeprom[address];
 623 }
 624
 625 struct iwl_mod_params iwlagn_mod_params = {
 626         .amsdu_size_8K = 1,
 627         .restart_fw = 1,
 628         .plcp_check = true,
 629         /* the rest are 0 by default */
 630 };
 631
 632 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 633 {
 634         unsigned long flags;
 635         int i;
 636         spin_lock_irqsave(&rxq->lock, flags);
 637         INIT_LIST_HEAD(&rxq->rx_free);
 638         INIT_LIST_HEAD(&rxq->rx_used);
 639         /* Fill the rx_used queue with _all_ of the Rx buffers */
 640         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 641                 /* In the reset function, these buffers may have been allocated
 642                  * to an SKB, so we need to unmap and free potential storage */
 643                 if (rxq->pool[i].page != NULL) {
 644                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 645                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 646                                 PCI_DMA_FROMDEVICE);
 647                         __iwl_free_pages(priv, rxq->pool[i].page);
 648                         rxq->pool[i].page = NULL;
 649                 }
 650                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 651         }
 652
 653         for (i = 0; i < RX_QUEUE_SIZE; i++)
 654                 rxq->queue[i] = NULL;
 655
 656         /* Set us so that we have processed and used all buffers, but have
 657          * not restocked the Rx queue with fresh buffers */
 658         rxq->read = rxq->write = 0;
 659         rxq->write_actual = 0;
 660         rxq->free_count = 0;
 661         spin_unlock_irqrestore(&rxq->lock, flags);
 662 }
 663
 664 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 665 {
 666         u32 rb_size;
 667         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 668         u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
 669
 670         rb_timeout = RX_RB_TIMEOUT;
 671
 672         if (priv->cfg->mod_params->amsdu_size_8K)
 673                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 674         else
 675                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 676
 677         /* Stop Rx DMA */
 678         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 679
 680         /* Reset driver's Rx queue write index */
 681         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 682
 683         /* Tell device where to find RBD circular buffer in DRAM */
 684         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 685                            (u32)(rxq->bd_dma >> 8));
 686
 687         /* Tell device where in DRAM to update its Rx status */
 688         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 689                            rxq->rb_stts_dma >> 4);
 690
 691         /* Enable Rx DMA
 692          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 693          *      the credit mechanism in 5000 HW RX FIFO
 694          * Direct rx interrupts to hosts
 695          * Rx buffer size 4 or 8k
 696          * RB timeout 0x10
 697          * 256 RBDs
 698          */
 699         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 700                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 701                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 702                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 703                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 704                            rb_size|
 705                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 706                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 707
 708         /* Set interrupt coalescing timer to default (2048 usecs) */
 709         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 710
 711         return 0;
 712 }
 713
 714 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
 715 {
 716 /*
 717  * (for documentation purposes)
 718  * to set power to V_AUX, do:
 719
 720                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 721                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 722                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 723                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 724  */
 725
 726         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 727                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 728                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 729 }
 730
 731 int iwlagn_hw_nic_init(struct iwl_priv *priv)
 732 {
 733         unsigned long flags;
 734         struct iwl_rx_queue *rxq = &priv->rxq;
 735         int ret;
 736
 737         /* nic_init */
 738         spin_lock_irqsave(&priv->lock, flags);
 739         priv->cfg->ops->lib->apm_ops.init(priv);
 740
 741         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 742         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 743
 744         spin_unlock_irqrestore(&priv->lock, flags);
 745
 746         iwlagn_set_pwr_vmain(priv);
 747
 748         priv->cfg->ops->lib->apm_ops.config(priv);
 749
 750         /* Allocate the RX queue, or reset if it is already allocated */
 751         if (!rxq->bd) {
 752                 ret = iwl_rx_queue_alloc(priv);
 753                 if (ret) {
 754                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
 755                         return -ENOMEM;
 756                 }
 757         } else
 758                 iwlagn_rx_queue_reset(priv, rxq);
 759
 760         iwlagn_rx_replenish(priv);
 761
 762         iwlagn_rx_init(priv, rxq);
 763
 764         spin_lock_irqsave(&priv->lock, flags);
 765
 766         rxq->need_update = 1;
 767         iwl_rx_queue_update_write_ptr(priv, rxq);
 768
 769         spin_unlock_irqrestore(&priv->lock, flags);
 770
 771         /* Allocate or reset and init all Tx and Command queues */
 772         if (!priv->txq) {
 773                 ret = iwlagn_txq_ctx_alloc(priv);
 774                 if (ret)
 775                         return ret;
 776         } else
 777                 iwlagn_txq_ctx_reset(priv);
 778
 779         if (priv->cfg->base_params->shadow_reg_enable) {
 780                 /* enable shadow regs in HW */
 781                 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
 782                         0x800FFFFF);
 783         }
 784
 785         set_bit(STATUS_INIT, &priv->status);
 786
 787         return 0;
 788 }
 789
 790 /**
 791  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 792  */
 793 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
 794                                           dma_addr_t dma_addr)
 795 {
 796         return cpu_to_le32((u32)(dma_addr >> 8));
 797 }
 798
 799 /**
 800  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 801  *
 802  * If there are slots in the RX queue that need to be restocked,
 803  * and we have free pre-allocated buffers, fill the ranks as much
 804  * as we can, pulling from rx_free.
 805  *
 806  * This moves the 'write' index forward to catch up with 'processed', and
 807  * also updates the memory address in the firmware to reference the new
 808  * target buffer.
 809  */
 810 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
 811 {
 812         struct iwl_rx_queue *rxq = &priv->rxq;
 813         struct list_head *element;
 814         struct iwl_rx_mem_buffer *rxb;
 815         unsigned long flags;
 816
 817         spin_lock_irqsave(&rxq->lock, flags);
 818         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 819                 /* The overwritten rxb must be a used one */
 820                 rxb = rxq->queue[rxq->write];
 821                 BUG_ON(rxb && rxb->page);
 822
 823                 /* Get next free Rx buffer, remove from free list */
 824                 element = rxq->rx_free.next;
 825                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 826                 list_del(element);
 827
 828                 /* Point to Rx buffer via next RBD in circular buffer */
 829                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
 830                                                               rxb->page_dma);
 831                 rxq->queue[rxq->write] = rxb;
 832                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 833                 rxq->free_count--;
 834         }
 835         spin_unlock_irqrestore(&rxq->lock, flags);
 836         /* If the pre-allocated buffer pool is dropping low, schedule to
 837          * refill it */
 838         if (rxq->free_count <= RX_LOW_WATERMARK)
 839                 queue_work(priv->workqueue, &priv->rx_replenish);
 840
 841
 842         /* If we've added more space for the firmware to place data, tell it.
 843          * Increment device's write pointer in multiples of 8. */
 844         if (rxq->write_actual != (rxq->write & ~0x7)) {
 845                 spin_lock_irqsave(&rxq->lock, flags);
 846                 rxq->need_update = 1;
 847                 spin_unlock_irqrestore(&rxq->lock, flags);
 848                 iwl_rx_queue_update_write_ptr(priv, rxq);
 849         }
 850 }
 851
 852 /**
 853  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 854  *
 855  * When moving to rx_free an SKB is allocated for the slot.
 856  *
 857  * Also restock the Rx queue via iwl_rx_queue_restock.
 858  * This is called as a scheduled work item (except for during initialization)
 859  */
 860 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
 861 {
 862         struct iwl_rx_queue *rxq = &priv->rxq;
 863         struct list_head *element;
 864         struct iwl_rx_mem_buffer *rxb;
 865         struct page *page;
 866         unsigned long flags;
 867         gfp_t gfp_mask = priority;
 868
 869         while (1) {
 870                 spin_lock_irqsave(&rxq->lock, flags);
 871                 if (list_empty(&rxq->rx_used)) {
 872                         spin_unlock_irqrestore(&rxq->lock, flags);
 873                         return;
 874                 }
 875                 spin_unlock_irqrestore(&rxq->lock, flags);
 876
 877                 if (rxq->free_count > RX_LOW_WATERMARK)
 878                         gfp_mask |= __GFP_NOWARN;
 879
 880                 if (priv->hw_params.rx_page_order > 0)
 881                         gfp_mask |= __GFP_COMP;
 882
 883                 /* Alloc a new receive buffer */
 884                 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
 885                 if (!page) {
 886                         if (net_ratelimit())
 887                                 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
 888                                                "order: %d\n",
 889                                                priv->hw_params.rx_page_order);
 890
 891                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 892                             net_ratelimit())
 893                                 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
 894                                          priority == GFP_ATOMIC ?  "GFP_ATOMIC" : "GFP_KERNEL",
 895                                          rxq->free_count);
 896                         /* We don't reschedule replenish work here -- we will
 897                          * call the restock method and if it still needs
 898                          * more buffers it will schedule replenish */
 899                         return;
 900                 }
 901
 902                 spin_lock_irqsave(&rxq->lock, flags);
 903
 904                 if (list_empty(&rxq->rx_used)) {
 905                         spin_unlock_irqrestore(&rxq->lock, flags);
 906                         __free_pages(page, priv->hw_params.rx_page_order);
 907                         return;
 908                 }
 909                 element = rxq->rx_used.next;
 910                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 911                 list_del(element);
 912
 913                 spin_unlock_irqrestore(&rxq->lock, flags);
 914
 915                 BUG_ON(rxb->page);
 916                 rxb->page = page;
 917                 /* Get physical address of the RB */
 918                 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
 919                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 920                                 PCI_DMA_FROMDEVICE);
 921                 /* dma address must be no more than 36 bits */
 922                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 923                 /* and also 256 byte aligned! */
 924                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 925
 926                 spin_lock_irqsave(&rxq->lock, flags);
 927
 928                 list_add_tail(&rxb->list, &rxq->rx_free);
 929                 rxq->free_count++;
 930
 931                 spin_unlock_irqrestore(&rxq->lock, flags);
 932         }
 933 }
 934
 935 void iwlagn_rx_replenish(struct iwl_priv *priv)
 936 {
 937         unsigned long flags;
 938
 939         iwlagn_rx_allocate(priv, GFP_KERNEL);
 940
 941         spin_lock_irqsave(&priv->lock, flags);
 942         iwlagn_rx_queue_restock(priv);
 943         spin_unlock_irqrestore(&priv->lock, flags);
 944 }
 945
 946 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
 947 {
 948         iwlagn_rx_allocate(priv, GFP_ATOMIC);
 949
 950         iwlagn_rx_queue_restock(priv);
 951 }
 952
 953 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
 954  * If an SKB has been detached, the POOL needs to have its SKB set to NULL
 955  * This free routine walks the list of POOL entries and if SKB is set to
 956  * non NULL it is unmapped and freed
 957  */
 958 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 959 {
 960         int i;
 961         for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
 962                 if (rxq->pool[i].page != NULL) {
 963                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 964                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 965                                 PCI_DMA_FROMDEVICE);
 966                         __iwl_free_pages(priv, rxq->pool[i].page);
 967                         rxq->pool[i].page = NULL;
 968                 }
 969         }
 970
 971         dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
 972                           rxq->bd_dma);
 973         dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
 974                           rxq->rb_stts, rxq->rb_stts_dma);
 975         rxq->bd = NULL;
 976         rxq->rb_stts  = NULL;
 977 }
 978
 979 int iwlagn_rxq_stop(struct iwl_priv *priv)
 980 {
 981
 982         /* stop Rx DMA */
 983         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 984         iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
 985                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 986
 987         return 0;
 988 }
 989
 990 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
 991 {
 992         int idx = 0;
 993         int band_offset = 0;
 994
 995         /* HT rate format: mac80211 wants an MCS number, which is just LSB */
 996         if (rate_n_flags & RATE_MCS_HT_MSK) {
 997                 idx = (rate_n_flags & 0xff);
 998                 return idx;
 999         /* Legacy rate format, search for match in table */
1000         } else {
1001                 if (band == IEEE80211_BAND_5GHZ)
1002                         band_offset = IWL_FIRST_OFDM_RATE;
1003                 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
1004                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
1005                                 return idx - band_offset;
1006         }
1007
1008         return -1;
1009 }
1010
1011 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1012                                            struct ieee80211_vif *vif,
1013                                            enum ieee80211_band band,
1014                                            struct iwl_scan_channel *scan_ch)
1015 {
1016         const struct ieee80211_supported_band *sband;
1017         u16 passive_dwell = 0;
1018         u16 active_dwell = 0;
1019         int added = 0;
1020         u16 channel = 0;
1021
1022         sband = iwl_get_hw_mode(priv, band);
1023         if (!sband) {
1024                 IWL_ERR(priv, "invalid band\n");
1025                 return added;
1026         }
1027
1028         active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1029         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1030
1031         if (passive_dwell <= active_dwell)
1032                 passive_dwell = active_dwell + 1;
1033
1034         channel = iwl_get_single_channel_number(priv, band);
1035         if (channel) {
1036                 scan_ch->channel = cpu_to_le16(channel);
1037                 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1038                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1039                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1040                 /* Set txpower levels to defaults */
1041                 scan_ch->dsp_atten = 110;
1042                 if (band == IEEE80211_BAND_5GHZ)
1043                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1044                 else
1045                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1046                 added++;
1047         } else
1048                 IWL_ERR(priv, "no valid channel found\n");
1049         return added;
1050 }
1051
1052 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1053                                      struct ieee80211_vif *vif,
1054                                      enum ieee80211_band band,
1055                                      u8 is_active, u8 n_probes,
1056                                      struct iwl_scan_channel *scan_ch)
1057 {
1058         struct ieee80211_channel *chan;
1059         const struct ieee80211_supported_band *sband;
1060         const struct iwl_channel_info *ch_info;
1061         u16 passive_dwell = 0;
1062         u16 active_dwell = 0;
1063         int added, i;
1064         u16 channel;
1065
1066         sband = iwl_get_hw_mode(priv, band);
1067         if (!sband)
1068                 return 0;
1069
1070         active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1071         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1072
1073         if (passive_dwell <= active_dwell)
1074                 passive_dwell = active_dwell + 1;
1075
1076         for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1077                 chan = priv->scan_request->channels[i];
1078
1079                 if (chan->band != band)
1080                         continue;
1081
1082                 channel = chan->hw_value;
1083                 scan_ch->channel = cpu_to_le16(channel);
1084
1085                 ch_info = iwl_get_channel_info(priv, band, channel);
1086                 if (!is_channel_valid(ch_info)) {
1087                         IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1088                                         channel);
1089                         continue;
1090                 }
1091
1092                 if (!is_active || is_channel_passive(ch_info) ||
1093                     (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1094                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1095                 else
1096                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1097
1098                 if (n_probes)
1099                         scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1100
1101                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1102                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1103
1104                 /* Set txpower levels to defaults */
1105                 scan_ch->dsp_atten = 110;
1106
1107                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1108                  * power level:
1109                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1110                  */
1111                 if (band == IEEE80211_BAND_5GHZ)
1112                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1113                 else
1114                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1115
1116                 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1117                                channel, le32_to_cpu(scan_ch->type),
1118                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1119                                 "ACTIVE" : "PASSIVE",
1120                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1121                                active_dwell : passive_dwell);
1122
1123                 scan_ch++;
1124                 added++;
1125         }
1126
1127         IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1128         return added;
1129 }
1130
1131 static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen)
1132 {
1133         struct sk_buff *skb = priv->_agn.offchan_tx_skb;
1134
1135         if (skb->len < maxlen)
1136                 maxlen = skb->len;
1137
1138         memcpy(data, skb->data, maxlen);
1139
1140         return maxlen;
1141 }
1142
1143 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1144 {
1145         struct iwl_host_cmd cmd = {
1146                 .id = REPLY_SCAN_CMD,
1147                 .len = sizeof(struct iwl_scan_cmd),
1148                 .flags = CMD_SIZE_HUGE,
1149         };
1150         struct iwl_scan_cmd *scan;
1151         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1152         u32 rate_flags = 0;
1153         u16 cmd_len;
1154         u16 rx_chain = 0;
1155         enum ieee80211_band band;
1156         u8 n_probes = 0;
1157         u8 rx_ant = priv->hw_params.valid_rx_ant;
1158         u8 rate;
1159         bool is_active = false;
1160         int  chan_mod;
1161         u8 active_chains;
1162         u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1163         int ret;
1164
1165         lockdep_assert_held(&priv->mutex);
1166
1167         if (vif)
1168                 ctx = iwl_rxon_ctx_from_vif(vif);
1169
1170         if (!priv->scan_cmd) {
1171                 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1172                                          IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1173                 if (!priv->scan_cmd) {
1174                         IWL_DEBUG_SCAN(priv,
1175                                        "fail to allocate memory for scan\n");
1176                         return -ENOMEM;
1177                 }
1178         }
1179         scan = priv->scan_cmd;
1180         memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1181
1182         scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1183         scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1184
1185         if (priv->scan_type != IWL_SCAN_OFFCH_TX &&
1186             iwl_is_any_associated(priv)) {
1187                 u16 interval = 0;
1188                 u32 extra;
1189                 u32 suspend_time = 100;
1190                 u32 scan_suspend_time = 100;
1191
1192                 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1193                 switch (priv->scan_type) {
1194                 case IWL_SCAN_OFFCH_TX:
1195                         WARN_ON(1);
1196                         break;
1197                 case IWL_SCAN_RADIO_RESET:
1198                         interval = 0;
1199                         break;
1200                 case IWL_SCAN_NORMAL:
1201                         interval = vif->bss_conf.beacon_int;
1202                         break;
1203                 }
1204
1205                 scan->suspend_time = 0;
1206                 scan->max_out_time = cpu_to_le32(200 * 1024);
1207                 if (!interval)
1208                         interval = suspend_time;
1209
1210                 extra = (suspend_time / interval) << 22;
1211                 scan_suspend_time = (extra |
1212                     ((suspend_time % interval) * 1024));
1213                 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1214                 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1215                                scan_suspend_time, interval);
1216         } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) {
1217                 scan->suspend_time = 0;
1218                 scan->max_out_time =
1219                         cpu_to_le32(1024 * priv->_agn.offchan_tx_timeout);
1220         }
1221
1222         switch (priv->scan_type) {
1223         case IWL_SCAN_RADIO_RESET:
1224                 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1225                 break;
1226         case IWL_SCAN_NORMAL:
1227                 if (priv->scan_request->n_ssids) {
1228                         int i, p = 0;
1229                         IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1230                         for (i = 0; i < priv->scan_request->n_ssids; i++) {
1231                                 /* always does wildcard anyway */
1232                                 if (!priv->scan_request->ssids[i].ssid_len)
1233                                         continue;
1234                                 scan->direct_scan[p].id = WLAN_EID_SSID;
1235                                 scan->direct_scan[p].len =
1236                                         priv->scan_request->ssids[i].ssid_len;
1237                                 memcpy(scan->direct_scan[p].ssid,
1238                                        priv->scan_request->ssids[i].ssid,
1239                                        priv->scan_request->ssids[i].ssid_len);
1240                                 n_probes++;
1241                                 p++;
1242                         }
1243                         is_active = true;
1244                 } else
1245                         IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1246                 break;
1247         case IWL_SCAN_OFFCH_TX:
1248                 IWL_DEBUG_SCAN(priv, "Start offchannel TX scan.\n");
1249                 break;
1250         }
1251
1252         scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1253         scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1254         scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1255
1256         switch (priv->scan_band) {
1257         case IEEE80211_BAND_2GHZ:
1258                 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1259                 chan_mod = le32_to_cpu(
1260                         priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1261                                                 RXON_FLG_CHANNEL_MODE_MSK)
1262                                        >> RXON_FLG_CHANNEL_MODE_POS;
1263                 if (chan_mod == CHANNEL_MODE_PURE_40) {
1264                         rate = IWL_RATE_6M_PLCP;
1265                 } else {
1266                         rate = IWL_RATE_1M_PLCP;
1267                         rate_flags = RATE_MCS_CCK_MSK;
1268                 }
1269                 /*
1270                  * Internal scans are passive, so we can indiscriminately set
1271                  * the BT ignore flag on 2.4 GHz since it applies to TX only.
1272                  */
1273                 if (priv->cfg->bt_params &&
1274                     priv->cfg->bt_params->advanced_bt_coexist)
1275                         scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1276                 break;
1277         case IEEE80211_BAND_5GHZ:
1278                 rate = IWL_RATE_6M_PLCP;
1279                 break;
1280         default:
1281                 IWL_WARN(priv, "Invalid scan band\n");
1282                 return -EIO;
1283         }
1284
1285         /*
1286          * If active scanning is requested but a certain channel is
1287          * marked passive, we can do active scanning if we detect
1288          * transmissions.
1289          *
1290          * There is an issue with some firmware versions that triggers
1291          * a sysassert on a "good CRC threshold" of zero (== disabled),
1292          * on a radar channel even though this means that we should NOT
1293          * send probes.
1294          *
1295          * The "good CRC threshold" is the number of frames that we
1296          * need to receive during our dwell time on a channel before
1297          * sending out probes -- setting this to a huge value will
1298          * mean we never reach it, but at the same time work around
1299          * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1300          * here instead of IWL_GOOD_CRC_TH_DISABLED.
1301          */
1302         scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1303                                         IWL_GOOD_CRC_TH_NEVER;
1304
1305         band = priv->scan_band;
1306
1307         if (priv->cfg->scan_rx_antennas[band])
1308                 rx_ant = priv->cfg->scan_rx_antennas[band];
1309
1310         if (band == IEEE80211_BAND_2GHZ &&
1311             priv->cfg->bt_params &&
1312             priv->cfg->bt_params->advanced_bt_coexist) {
1313                 /* transmit 2.4 GHz probes only on first antenna */
1314                 scan_tx_antennas = first_antenna(scan_tx_antennas);
1315         }
1316
1317         priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1318                                                     scan_tx_antennas);
1319         rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1320         scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1321
1322         /* In power save mode use one chain, otherwise use all chains */
1323         if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1324                 /* rx_ant has been set to all valid chains previously */
1325                 active_chains = rx_ant &
1326                                 ((u8)(priv->chain_noise_data.active_chains));
1327                 if (!active_chains)
1328                         active_chains = rx_ant;
1329
1330                 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1331                                 priv->chain_noise_data.active_chains);
1332
1333                 rx_ant = first_antenna(active_chains);
1334         }
1335         if (priv->cfg->bt_params &&
1336             priv->cfg->bt_params->advanced_bt_coexist &&
1337             priv->bt_full_concurrent) {
1338                 /* operated as 1x1 in full concurrency mode */
1339                 rx_ant = first_antenna(rx_ant);
1340         }
1341
1342         /* MIMO is not used here, but value is required */
1343         rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1344         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1345         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1346         rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1347         scan->rx_chain = cpu_to_le16(rx_chain);
1348         switch (priv->scan_type) {
1349         case IWL_SCAN_NORMAL:
1350                 cmd_len = iwl_fill_probe_req(priv,
1351                                         (struct ieee80211_mgmt *)scan->data,
1352                                         vif->addr,
1353                                         priv->scan_request->ie,
1354                                         priv->scan_request->ie_len,
1355                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1356                 break;
1357         case IWL_SCAN_RADIO_RESET:
1358                 /* use bcast addr, will not be transmitted but must be valid */
1359                 cmd_len = iwl_fill_probe_req(priv,
1360                                         (struct ieee80211_mgmt *)scan->data,
1361                                         iwl_bcast_addr, NULL, 0,
1362                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1363                 break;
1364         case IWL_SCAN_OFFCH_TX:
1365                 cmd_len = iwl_fill_offch_tx(priv, scan->data,
1366                                             IWL_MAX_SCAN_SIZE
1367                                              - sizeof(*scan)
1368                                              - sizeof(struct iwl_scan_channel));
1369                 scan->scan_flags |= IWL_SCAN_FLAGS_ACTION_FRAME_TX;
1370                 break;
1371         default:
1372                 BUG();
1373         }
1374         scan->tx_cmd.len = cpu_to_le16(cmd_len);
1375
1376         scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1377                                RXON_FILTER_BCON_AWARE_MSK);
1378
1379         switch (priv->scan_type) {
1380         case IWL_SCAN_RADIO_RESET:
1381                 scan->channel_count =
1382                         iwl_get_single_channel_for_scan(priv, vif, band,
1383                                 (void *)&scan->data[cmd_len]);
1384                 break;
1385         case IWL_SCAN_NORMAL:
1386                 scan->channel_count =
1387                         iwl_get_channels_for_scan(priv, vif, band,
1388                                 is_active, n_probes,
1389                                 (void *)&scan->data[cmd_len]);
1390                 break;
1391         case IWL_SCAN_OFFCH_TX: {
1392                 struct iwl_scan_channel *scan_ch;
1393
1394                 scan->channel_count = 1;
1395
1396                 scan_ch = (void *)&scan->data[cmd_len];
1397                 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1398                 scan_ch->channel =
1399                         cpu_to_le16(priv->_agn.offchan_tx_chan->hw_value);
1400                 scan_ch->active_dwell =
1401                         cpu_to_le16(priv->_agn.offchan_tx_timeout);
1402                 scan_ch->passive_dwell = 0;
1403
1404                 /* Set txpower levels to defaults */
1405                 scan_ch->dsp_atten = 110;
1406
1407                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1408                  * power level:
1409                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1410                  */
1411                 if (priv->_agn.offchan_tx_chan->band == IEEE80211_BAND_5GHZ)
1412                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1413                 else
1414                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1415                 }
1416                 break;
1417         }
1418
1419         if (scan->channel_count == 0) {
1420                 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1421                 return -EIO;
1422         }
1423
1424         cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1425             scan->channel_count * sizeof(struct iwl_scan_channel);
1426         cmd.data = scan;
1427         scan->len = cpu_to_le16(cmd.len);
1428
1429         /* set scan bit here for PAN params */
1430         set_bit(STATUS_SCAN_HW, &priv->status);
1431
1432         if (priv->cfg->ops->hcmd->set_pan_params) {
1433                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1434                 if (ret)
1435                         return ret;
1436         }
1437
1438         ret = iwl_send_cmd_sync(priv, &cmd);
1439         if (ret) {
1440                 clear_bit(STATUS_SCAN_HW, &priv->status);
1441                 if (priv->cfg->ops->hcmd->set_pan_params)
1442                         priv->cfg->ops->hcmd->set_pan_params(priv);
1443         }
1444
1445         return ret;
1446 }
1447
1448 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1449                                struct ieee80211_vif *vif, bool add)
1450 {
1451         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1452
1453         if (add)
1454                 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1455                                                 vif->bss_conf.bssid,
1456                                                 &vif_priv->ibss_bssid_sta_id);
1457         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1458                                   vif->bss_conf.bssid);
1459 }
1460
1461 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1462                             int sta_id, int tid, int freed)
1463 {
1464         lockdep_assert_held(&priv->sta_lock);
1465
1466         if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1467                 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1468         else {
1469                 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1470                         priv->stations[sta_id].tid[tid].tfds_in_queue,
1471                         freed);
1472                 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1473         }
1474 }
1475
1476 #define IWL_FLUSH_WAIT_MS       2000
1477
1478 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1479 {
1480         struct iwl_tx_queue *txq;
1481         struct iwl_queue *q;
1482         int cnt;
1483         unsigned long now = jiffies;
1484         int ret = 0;
1485
1486         /* waiting for all the tx frames complete might take a while */
1487         for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1488                 if (cnt == priv->cmd_queue)
1489                         continue;
1490                 txq = &priv->txq[cnt];
1491                 q = &txq->q;
1492                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1493                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1494                                 msleep(1);
1495
1496                 if (q->read_ptr != q->write_ptr) {
1497                         IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1498                         ret = -ETIMEDOUT;
1499                         break;
1500                 }
1501         }
1502         return ret;
1503 }
1504
1505 #define IWL_TX_QUEUE_MSK        0xfffff
1506
1507 /**
1508  * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1509  *
1510  * pre-requirements:
1511  *  1. acquire mutex before calling
1512  *  2. make sure rf is on and not in exit state
1513  */
1514 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1515 {
1516         struct iwl_txfifo_flush_cmd flush_cmd;
1517         struct iwl_host_cmd cmd = {
1518                 .id = REPLY_TXFIFO_FLUSH,
1519                 .len = sizeof(struct iwl_txfifo_flush_cmd),
1520                 .flags = CMD_SYNC,
1521                 .data = &flush_cmd,
1522         };
1523
1524         might_sleep();
1525
1526         memset(&flush_cmd, 0, sizeof(flush_cmd));
1527         flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1528                                  IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1529         if (priv->cfg->sku & IWL_SKU_N)
1530                 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1531
1532         IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1533                        flush_cmd.fifo_control);
1534         flush_cmd.flush_control = cpu_to_le16(flush_control);
1535
1536         return iwl_send_cmd(priv, &cmd);
1537 }
1538
1539 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1540 {
1541         mutex_lock(&priv->mutex);
1542         ieee80211_stop_queues(priv->hw);
1543         if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1544                 IWL_ERR(priv, "flush request fail\n");
1545                 goto done;
1546         }
1547         IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1548         iwlagn_wait_tx_queue_empty(priv);
1549 done:
1550         ieee80211_wake_queues(priv->hw);
1551         mutex_unlock(&priv->mutex);
1552 }
1553
1554 /*
1555  * BT coex
1556  */
1557 /*
1558  * Macros to access the lookup table.
1559  *
1560  * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1561 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1562  *
1563  * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1564  *
1565  * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1566  * one after another in 32-bit registers, and "registers" 0 through 7 contain
1567  * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1568  *
1569  * These macros encode that format.
1570  */
1571 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1572                   wifi_txrx, wifi_sh_ant_req) \
1573         (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1574         (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1575
1576 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1577         lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1578 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1579                                  wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1580         (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1581                                    bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1582                                    wifi_sh_ant_req))))
1583 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1584                                 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1585         LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1586                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1587                                wifi_sh_ant_req))
1588 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1589                                   wifi_req, wifi_prio, wifi_txrx, \
1590                                   wifi_sh_ant_req) \
1591         LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1592                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1593                                wifi_sh_ant_req))
1594
1595 #define LUT_WLAN_KILL_OP(lut, op, val) \
1596         lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1597 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1598                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1599         (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1600                              wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1601 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1602                           wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1603         LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1604                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1605 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1606                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1607         LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1608                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1609
1610 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1611         lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1612 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1613                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1614         (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1615                               wifi_req, wifi_prio, wifi_txrx, \
1616                               wifi_sh_ant_req))))
1617 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1618                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1619         LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1620                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1621 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1622                              wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1623         LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1624                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1625
1626 static const __le32 iwlagn_def_3w_lookup[12] = {
1627         cpu_to_le32(0xaaaaaaaa),
1628         cpu_to_le32(0xaaaaaaaa),
1629         cpu_to_le32(0xaeaaaaaa),
1630         cpu_to_le32(0xaaaaaaaa),
1631         cpu_to_le32(0xcc00ff28),
1632         cpu_to_le32(0x0000aaaa),
1633         cpu_to_le32(0xcc00aaaa),
1634         cpu_to_le32(0x0000aaaa),
1635         cpu_to_le32(0xc0004000),
1636         cpu_to_le32(0x00004000),
1637         cpu_to_le32(0xf0005000),
1638         cpu_to_le32(0xf0005000),
1639 };
1640
1641 static const __le32 iwlagn_concurrent_lookup[12] = {
1642         cpu_to_le32(0xaaaaaaaa),
1643         cpu_to_le32(0xaaaaaaaa),
1644         cpu_to_le32(0xaaaaaaaa),
1645         cpu_to_le32(0xaaaaaaaa),
1646         cpu_to_le32(0xaaaaaaaa),
1647         cpu_to_le32(0xaaaaaaaa),
1648         cpu_to_le32(0xaaaaaaaa),
1649         cpu_to_le32(0xaaaaaaaa),
1650         cpu_to_le32(0x00000000),
1651         cpu_to_le32(0x00000000),
1652         cpu_to_le32(0x00000000),
1653         cpu_to_le32(0x00000000),
1654 };
1655
1656 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1657 {
1658         struct iwl_basic_bt_cmd basic = {
1659                 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1660                 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1661                 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1662                 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1663         };
1664         struct iwl6000_bt_cmd bt_cmd_6000;
1665         struct iwl2000_bt_cmd bt_cmd_2000;
1666         int ret;
1667
1668         BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1669                         sizeof(basic.bt3_lookup_table));
1670
1671         if (priv->cfg->bt_params) {
1672                 if (priv->cfg->bt_params->bt_session_2) {
1673                         bt_cmd_2000.prio_boost = cpu_to_le32(
1674                                 priv->cfg->bt_params->bt_prio_boost);
1675                         bt_cmd_2000.tx_prio_boost = 0;
1676                         bt_cmd_2000.rx_prio_boost = 0;
1677                 } else {
1678                         bt_cmd_6000.prio_boost =
1679                                 priv->cfg->bt_params->bt_prio_boost;
1680                         bt_cmd_6000.tx_prio_boost = 0;
1681                         bt_cmd_6000.rx_prio_boost = 0;
1682                 }
1683         } else {
1684                 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1685                 return;
1686         }
1687
1688         basic.kill_ack_mask = priv->kill_ack_mask;
1689         basic.kill_cts_mask = priv->kill_cts_mask;
1690         basic.valid = priv->bt_valid;
1691
1692         /*
1693          * Configure BT coex mode to "no coexistence" when the
1694          * user disabled BT coexistence, we have no interface
1695          * (might be in monitor mode), or the interface is in
1696          * IBSS mode (no proper uCode support for coex then).
1697          */
1698         if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1699                 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1700         } else {
1701                 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1702                                         IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1703                 if (priv->cfg->bt_params &&
1704                     priv->cfg->bt_params->bt_sco_disable)
1705                         basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1706
1707                 if (priv->bt_ch_announce)
1708                         basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1709                 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", basic.flags);
1710         }
1711         priv->bt_enable_flag = basic.flags;
1712         if (priv->bt_full_concurrent)
1713                 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1714                         sizeof(iwlagn_concurrent_lookup));
1715         else
1716                 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1717                         sizeof(iwlagn_def_3w_lookup));
1718
1719         IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1720                        basic.flags ? "active" : "disabled",
1721                        priv->bt_full_concurrent ?
1722                        "full concurrency" : "3-wire");
1723
1724         if (priv->cfg->bt_params->bt_session_2) {
1725                 memcpy(&bt_cmd_2000.basic, &basic,
1726                         sizeof(basic));
1727                 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1728                         sizeof(bt_cmd_2000), &bt_cmd_2000);
1729         } else {
1730                 memcpy(&bt_cmd_6000.basic, &basic,
1731                         sizeof(basic));
1732                 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1733                         sizeof(bt_cmd_6000), &bt_cmd_6000);
1734         }
1735         if (ret)
1736                 IWL_ERR(priv, "failed to send BT Coex Config\n");
1737
1738 }
1739
1740 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1741 {
1742         struct iwl_priv *priv =
1743                 container_of(work, struct iwl_priv, bt_traffic_change_work);
1744         struct iwl_rxon_context *ctx;
1745         int smps_request = -1;
1746
1747         if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1748                 /* bt coex disabled */
1749                 return;
1750         }
1751
1752         /*
1753          * Note: bt_traffic_load can be overridden by scan complete and
1754          * coex profile notifications. Ignore that since only bad consequence
1755          * can be not matching debug print with actual state.
1756          */
1757         IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1758                        priv->bt_traffic_load);
1759
1760         switch (priv->bt_traffic_load) {
1761         case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1762                 if (priv->bt_status)
1763                         smps_request = IEEE80211_SMPS_DYNAMIC;
1764                 else
1765                         smps_request = IEEE80211_SMPS_AUTOMATIC;
1766                 break;
1767         case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1768                 smps_request = IEEE80211_SMPS_DYNAMIC;
1769                 break;
1770         case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1771         case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1772                 smps_request = IEEE80211_SMPS_STATIC;
1773                 break;
1774         default:
1775                 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1776                         priv->bt_traffic_load);
1777                 break;
1778         }
1779
1780         mutex_lock(&priv->mutex);
1781
1782         /*
1783          * We can not send command to firmware while scanning. When the scan
1784          * complete we will schedule this work again. We do check with mutex
1785          * locked to prevent new scan request to arrive. We do not check
1786          * STATUS_SCANNING to avoid race when queue_work two times from
1787          * different notifications, but quit and not perform any work at all.
1788          */
1789         if (test_bit(STATUS_SCAN_HW, &priv->status))
1790                 goto out;
1791
1792         if (priv->cfg->ops->lib->update_chain_flags)
1793                 priv->cfg->ops->lib->update_chain_flags(priv);
1794
1795         if (smps_request != -1) {
1796                 for_each_context(priv, ctx) {
1797                         if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1798                                 ieee80211_request_smps(ctx->vif, smps_request);
1799                 }
1800         }
1801 out:
1802         mutex_unlock(&priv->mutex);
1803 }
1804
1805 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1806                                 struct iwl_bt_uart_msg *uart_msg)
1807 {
1808         IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1809                         "Update Req = 0x%X",
1810                 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1811                         BT_UART_MSG_FRAME1MSGTYPE_POS,
1812                 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1813                         BT_UART_MSG_FRAME1SSN_POS,
1814                 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1815                         BT_UART_MSG_FRAME1UPDATEREQ_POS);
1816
1817         IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1818                         "Chl_SeqN = 0x%X, In band = 0x%X",
1819                 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1820                         BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1821                 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1822                         BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1823                 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1824                         BT_UART_MSG_FRAME2CHLSEQN_POS,
1825                 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1826                         BT_UART_MSG_FRAME2INBAND_POS);
1827
1828         IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1829                         "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1830                 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1831                         BT_UART_MSG_FRAME3SCOESCO_POS,
1832                 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1833                         BT_UART_MSG_FRAME3SNIFF_POS,
1834                 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1835                         BT_UART_MSG_FRAME3A2DP_POS,
1836                 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1837                         BT_UART_MSG_FRAME3ACL_POS,
1838                 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1839                         BT_UART_MSG_FRAME3MASTER_POS,
1840                 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1841                         BT_UART_MSG_FRAME3OBEX_POS);
1842
1843         IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1844                 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1845                         BT_UART_MSG_FRAME4IDLEDURATION_POS);
1846
1847         IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1848                         "eSCO Retransmissions = 0x%X",
1849                 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1850                         BT_UART_MSG_FRAME5TXACTIVITY_POS,
1851                 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1852                         BT_UART_MSG_FRAME5RXACTIVITY_POS,
1853                 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1854                         BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1855
1856         IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1857                 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1858                         BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1859                 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1860                         BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1861
1862         IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Page = "
1863                         "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1864                 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1865                         BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1866                 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
1867                         BT_UART_MSG_FRAME7PAGE_POS,
1868                 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
1869                         BT_UART_MSG_FRAME7INQUIRY_POS,
1870                 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1871                         BT_UART_MSG_FRAME7CONNECTABLE_POS);
1872 }
1873
1874 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
1875                                 struct iwl_bt_uart_msg *uart_msg)
1876 {
1877         u8 kill_msk;
1878         static const __le32 bt_kill_ack_msg[2] = {
1879                 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
1880                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1881         static const __le32 bt_kill_cts_msg[2] = {
1882                 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
1883                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1884
1885         kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
1886                 ? 1 : 0;
1887         if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
1888             priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
1889                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1890                 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
1891                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
1892                 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
1893
1894                 /* schedule to send runtime bt_config */
1895                 queue_work(priv->workqueue, &priv->bt_runtime_config);
1896         }
1897 }
1898
1899 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1900                                              struct iwl_rx_mem_buffer *rxb)
1901 {
1902         unsigned long flags;
1903         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1904         struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1905         struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1906
1907         if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1908                 /* bt coex disabled */
1909                 return;
1910         }
1911
1912         IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1913         IWL_DEBUG_NOTIF(priv, "    status: %d\n", coex->bt_status);
1914         IWL_DEBUG_NOTIF(priv, "    traffic load: %d\n", coex->bt_traffic_load);
1915         IWL_DEBUG_NOTIF(priv, "    CI compliance: %d\n",
1916                         coex->bt_ci_compliance);
1917         iwlagn_print_uartmsg(priv, uart_msg);
1918
1919         priv->last_bt_traffic_load = priv->bt_traffic_load;
1920         if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1921                 if (priv->bt_status != coex->bt_status ||
1922                     priv->last_bt_traffic_load != coex->bt_traffic_load) {
1923                         if (coex->bt_status) {
1924                                 /* BT on */
1925                                 if (!priv->bt_ch_announce)
1926                                         priv->bt_traffic_load =
1927                                                 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1928                                 else
1929                                         priv->bt_traffic_load =
1930                                                 coex->bt_traffic_load;
1931                         } else {
1932                                 /* BT off */
1933                                 priv->bt_traffic_load =
1934                                         IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1935                         }
1936                         priv->bt_status = coex->bt_status;
1937                         queue_work(priv->workqueue,
1938                                    &priv->bt_traffic_change_work);
1939                 }
1940         }
1941
1942         iwlagn_set_kill_msk(priv, uart_msg);
1943
1944         /* FIXME: based on notification, adjust the prio_boost */
1945
1946         spin_lock_irqsave(&priv->lock, flags);
1947         priv->bt_ci_compliance = coex->bt_ci_compliance;
1948         spin_unlock_irqrestore(&priv->lock, flags);
1949 }
1950
1951 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1952 {
1953         iwlagn_rx_handler_setup(priv);
1954         priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1955                 iwlagn_bt_coex_profile_notif;
1956 }
1957
1958 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1959 {
1960         iwlagn_setup_deferred_work(priv);
1961
1962         INIT_WORK(&priv->bt_traffic_change_work,
1963                   iwlagn_bt_traffic_change_work);
1964 }
1965
1966 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1967 {
1968         cancel_work_sync(&priv->bt_traffic_change_work);
1969 }
1970
1971 static bool is_single_rx_stream(struct iwl_priv *priv)
1972 {
1973         return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1974                priv->current_ht_config.single_chain_sufficient;
1975 }
1976
1977 #define IWL_NUM_RX_CHAINS_MULTIPLE      3
1978 #define IWL_NUM_RX_CHAINS_SINGLE        2
1979 #define IWL_NUM_IDLE_CHAINS_DUAL        2
1980 #define IWL_NUM_IDLE_CHAINS_SINGLE      1
1981
1982 /*
1983  * Determine how many receiver/antenna chains to use.
1984  *
1985  * More provides better reception via diversity.  Fewer saves power
1986  * at the expense of throughput, but only when not in powersave to
1987  * start with.
1988  *
1989  * MIMO (dual stream) requires at least 2, but works better with 3.
1990  * This does not determine *which* chains to use, just how many.
1991  */
1992 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
1993 {
1994         if (priv->cfg->bt_params &&
1995             priv->cfg->bt_params->advanced_bt_coexist &&
1996             (priv->bt_full_concurrent ||
1997              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
1998                 /*
1999                  * only use chain 'A' in bt high traffic load or
2000                  * full concurrency mode
2001                  */
2002                 return IWL_NUM_RX_CHAINS_SINGLE;
2003         }
2004         /* # of Rx chains to use when expecting MIMO. */
2005         if (is_single_rx_stream(priv))
2006                 return IWL_NUM_RX_CHAINS_SINGLE;
2007         else
2008                 return IWL_NUM_RX_CHAINS_MULTIPLE;
2009 }
2010
2011 /*
2012  * When we are in power saving mode, unless device support spatial
2013  * multiplexing power save, use the active count for rx chain count.
2014  */
2015 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2016 {
2017         /* # Rx chains when idling, depending on SMPS mode */
2018         switch (priv->current_ht_config.smps) {
2019         case IEEE80211_SMPS_STATIC:
2020         case IEEE80211_SMPS_DYNAMIC:
2021                 return IWL_NUM_IDLE_CHAINS_SINGLE;
2022         case IEEE80211_SMPS_OFF:
2023                 return active_cnt;
2024         default:
2025                 WARN(1, "invalid SMPS mode %d",
2026                      priv->current_ht_config.smps);
2027                 return active_cnt;
2028         }
2029 }
2030
2031 /* up to 4 chains */
2032 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2033 {
2034         u8 res;
2035         res = (chain_bitmap & BIT(0)) >> 0;
2036         res += (chain_bitmap & BIT(1)) >> 1;
2037         res += (chain_bitmap & BIT(2)) >> 2;
2038         res += (chain_bitmap & BIT(3)) >> 3;
2039         return res;
2040 }
2041
2042 /**
2043  * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2044  *
2045  * Selects how many and which Rx receivers/antennas/chains to use.
2046  * This should not be used for scan command ... it puts data in wrong place.
2047  */
2048 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2049 {
2050         bool is_single = is_single_rx_stream(priv);
2051         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2052         u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2053         u32 active_chains;
2054         u16 rx_chain;
2055
2056         /* Tell uCode which antennas are actually connected.
2057          * Before first association, we assume all antennas are connected.
2058          * Just after first association, iwl_chain_noise_calibration()
2059          *    checks which antennas actually *are* connected. */
2060         if (priv->chain_noise_data.active_chains)
2061                 active_chains = priv->chain_noise_data.active_chains;
2062         else
2063                 active_chains = priv->hw_params.valid_rx_ant;
2064
2065         if (priv->cfg->bt_params &&
2066             priv->cfg->bt_params->advanced_bt_coexist &&
2067             (priv->bt_full_concurrent ||
2068              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2069                 /*
2070                  * only use chain 'A' in bt high traffic load or
2071                  * full concurrency mode
2072                  */
2073                 active_chains = first_antenna(active_chains);
2074         }
2075
2076         rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2077
2078         /* How many receivers should we use? */
2079         active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2080         idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2081
2082
2083         /* correct rx chain count according hw settings
2084          * and chain noise calibration
2085          */
2086         valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2087         if (valid_rx_cnt < active_rx_cnt)
2088                 active_rx_cnt = valid_rx_cnt;
2089
2090         if (valid_rx_cnt < idle_rx_cnt)
2091                 idle_rx_cnt = valid_rx_cnt;
2092
2093         rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2094         rx_chain |= idle_rx_cnt  << RXON_RX_CHAIN_CNT_POS;
2095
2096         ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2097
2098         if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2099                 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2100         else
2101                 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2102
2103         IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2104                         ctx->staging.rx_chain,
2105                         active_rx_cnt, idle_rx_cnt);
2106
2107         WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2108                 active_rx_cnt < idle_rx_cnt);
2109 }
2110
2111 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2112 {
2113         int i;
2114         u8 ind = ant;
2115
2116         if (priv->band == IEEE80211_BAND_2GHZ &&
2117             priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2118                 return 0;
2119
2120         for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2121                 ind = (ind + 1) < RATE_ANT_NUM ?  ind + 1 : 0;
2122                 if (valid & BIT(ind))
2123                         return ind;
2124         }
2125         return ant;
2126 }
2127
2128 static const char *get_csr_string(int cmd)
2129 {
2130         switch (cmd) {
2131         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2132         IWL_CMD(CSR_INT_COALESCING);
2133         IWL_CMD(CSR_INT);
2134         IWL_CMD(CSR_INT_MASK);
2135         IWL_CMD(CSR_FH_INT_STATUS);
2136         IWL_CMD(CSR_GPIO_IN);
2137         IWL_CMD(CSR_RESET);
2138         IWL_CMD(CSR_GP_CNTRL);
2139         IWL_CMD(CSR_HW_REV);
2140         IWL_CMD(CSR_EEPROM_REG);
2141         IWL_CMD(CSR_EEPROM_GP);
2142         IWL_CMD(CSR_OTP_GP_REG);
2143         IWL_CMD(CSR_GIO_REG);
2144         IWL_CMD(CSR_GP_UCODE_REG);
2145         IWL_CMD(CSR_GP_DRIVER_REG);
2146         IWL_CMD(CSR_UCODE_DRV_GP1);
2147         IWL_CMD(CSR_UCODE_DRV_GP2);
2148         IWL_CMD(CSR_LED_REG);
2149         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2150         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2151         IWL_CMD(CSR_ANA_PLL_CFG);
2152         IWL_CMD(CSR_HW_REV_WA_REG);
2153         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2154         default:
2155                 return "UNKNOWN";
2156         }
2157 }
2158
2159 void iwl_dump_csr(struct iwl_priv *priv)
2160 {
2161         int i;
2162         static const u32 csr_tbl[] = {
2163                 CSR_HW_IF_CONFIG_REG,
2164                 CSR_INT_COALESCING,
2165                 CSR_INT,
2166                 CSR_INT_MASK,
2167                 CSR_FH_INT_STATUS,
2168                 CSR_GPIO_IN,
2169                 CSR_RESET,
2170                 CSR_GP_CNTRL,
2171                 CSR_HW_REV,
2172                 CSR_EEPROM_REG,
2173                 CSR_EEPROM_GP,
2174                 CSR_OTP_GP_REG,
2175                 CSR_GIO_REG,
2176                 CSR_GP_UCODE_REG,
2177                 CSR_GP_DRIVER_REG,
2178                 CSR_UCODE_DRV_GP1,
2179                 CSR_UCODE_DRV_GP2,
2180                 CSR_LED_REG,
2181                 CSR_DRAM_INT_TBL_REG,
2182                 CSR_GIO_CHICKEN_BITS,
2183                 CSR_ANA_PLL_CFG,
2184                 CSR_HW_REV_WA_REG,
2185                 CSR_DBG_HPET_MEM_REG
2186         };
2187         IWL_ERR(priv, "CSR values:\n");
2188         IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2189                 "CSR_INT_PERIODIC_REG)\n");
2190         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2191                 IWL_ERR(priv, "  %25s: 0X%08x\n",
2192                         get_csr_string(csr_tbl[i]),
2193                         iwl_read32(priv, csr_tbl[i]));
2194         }
2195 }
2196
2197 static const char *get_fh_string(int cmd)
2198 {
2199         switch (cmd) {
2200         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2201         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2202         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2203         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2204         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2205         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2206         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2207         IWL_CMD(FH_TSSR_TX_STATUS_REG);
2208         IWL_CMD(FH_TSSR_TX_ERROR_REG);
2209         default:
2210                 return "UNKNOWN";
2211         }
2212 }
2213
2214 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2215 {
2216         int i;
2217 #ifdef CONFIG_IWLWIFI_DEBUG
2218         int pos = 0;
2219         size_t bufsz = 0;
2220 #endif
2221         static const u32 fh_tbl[] = {
2222                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2223                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2224                 FH_RSCSR_CHNL0_WPTR,
2225                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2226                 FH_MEM_RSSR_SHARED_CTRL_REG,
2227                 FH_MEM_RSSR_RX_STATUS_REG,
2228                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2229                 FH_TSSR_TX_STATUS_REG,
2230                 FH_TSSR_TX_ERROR_REG
2231         };
2232 #ifdef CONFIG_IWLWIFI_DEBUG
2233         if (display) {
2234                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2235                 *buf = kmalloc(bufsz, GFP_KERNEL);
2236                 if (!*buf)
2237                         return -ENOMEM;
2238                 pos += scnprintf(*buf + pos, bufsz - pos,
2239                                 "FH register values:\n");
2240                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2241                         pos += scnprintf(*buf + pos, bufsz - pos,
2242                                 "  %34s: 0X%08x\n",
2243                                 get_fh_string(fh_tbl[i]),
2244                                 iwl_read_direct32(priv, fh_tbl[i]));
2245                 }
2246                 return pos;
2247         }
2248 #endif
2249         IWL_ERR(priv, "FH register values:\n");
2250         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
2251                 IWL_ERR(priv, "  %34s: 0X%08x\n",
2252                         get_fh_string(fh_tbl[i]),
2253                         iwl_read_direct32(priv, fh_tbl[i]));
2254         }
2255         return 0;
2256 }
2257
2258 /* notification wait support */
2259 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2260                                    struct iwl_notification_wait *wait_entry,
2261                                    void (*fn)(struct iwl_priv *priv,
2262                                               struct iwl_rx_packet *pkt),
2263                                    u8 cmd)
2264 {
2265         wait_entry->fn = fn;
2266         wait_entry->cmd = cmd;
2267         wait_entry->triggered = false;
2268
2269         spin_lock_bh(&priv->_agn.notif_wait_lock);
2270         list_add(&wait_entry->list, &priv->_agn.notif_waits);
2271         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2272 }
2273
2274 signed long iwlagn_wait_notification(struct iwl_priv *priv,
2275                                      struct iwl_notification_wait *wait_entry,
2276                                      unsigned long timeout)
2277 {
2278         int ret;
2279
2280         ret = wait_event_timeout(priv->_agn.notif_waitq,
2281                                  wait_entry->triggered,
2282                                  timeout);
2283
2284         spin_lock_bh(&priv->_agn.notif_wait_lock);
2285         list_del(&wait_entry->list);
2286         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2287
2288         return ret;
2289 }
2290
2291 void iwlagn_remove_notification(struct iwl_priv *priv,
2292                                 struct iwl_notification_wait *wait_entry)
2293 {
2294         spin_lock_bh(&priv->_agn.notif_wait_lock);
2295         list_del(&wait_entry->list);
2296         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2297 }