drivers/net/wireless/iwlwifi/iwl-agn-lib.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/sched.h>
  34
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-helpers.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-agn.h"
  41 #include "iwl-sta.h"
  42
  43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
  44 {
  45         return le32_to_cpup((__le32 *)&tx_resp->status +
  46                             tx_resp->frame_count) & MAX_SN;
  47 }
  48
  49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
  50 {
  51         status &= TX_STATUS_MSK;
  52
  53         switch (status) {
  54         case TX_STATUS_POSTPONE_DELAY:
  55                 priv->_agn.reply_tx_stats.pp_delay++;
  56                 break;
  57         case TX_STATUS_POSTPONE_FEW_BYTES:
  58                 priv->_agn.reply_tx_stats.pp_few_bytes++;
  59                 break;
  60         case TX_STATUS_POSTPONE_BT_PRIO:
  61                 priv->_agn.reply_tx_stats.pp_bt_prio++;
  62                 break;
  63         case TX_STATUS_POSTPONE_QUIET_PERIOD:
  64                 priv->_agn.reply_tx_stats.pp_quiet_period++;
  65                 break;
  66         case TX_STATUS_POSTPONE_CALC_TTAK:
  67                 priv->_agn.reply_tx_stats.pp_calc_ttak++;
  68                 break;
  69         case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
  70                 priv->_agn.reply_tx_stats.int_crossed_retry++;
  71                 break;
  72         case TX_STATUS_FAIL_SHORT_LIMIT:
  73                 priv->_agn.reply_tx_stats.short_limit++;
  74                 break;
  75         case TX_STATUS_FAIL_LONG_LIMIT:
  76                 priv->_agn.reply_tx_stats.long_limit++;
  77                 break;
  78         case TX_STATUS_FAIL_FIFO_UNDERRUN:
  79                 priv->_agn.reply_tx_stats.fifo_underrun++;
  80                 break;
  81         case TX_STATUS_FAIL_DRAIN_FLOW:
  82                 priv->_agn.reply_tx_stats.drain_flow++;
  83                 break;
  84         case TX_STATUS_FAIL_RFKILL_FLUSH:
  85                 priv->_agn.reply_tx_stats.rfkill_flush++;
  86                 break;
  87         case TX_STATUS_FAIL_LIFE_EXPIRE:
  88                 priv->_agn.reply_tx_stats.life_expire++;
  89                 break;
  90         case TX_STATUS_FAIL_DEST_PS:
  91                 priv->_agn.reply_tx_stats.dest_ps++;
  92                 break;
  93         case TX_STATUS_FAIL_HOST_ABORTED:
  94                 priv->_agn.reply_tx_stats.host_abort++;
  95                 break;
  96         case TX_STATUS_FAIL_BT_RETRY:
  97                 priv->_agn.reply_tx_stats.bt_retry++;
  98                 break;
  99         case TX_STATUS_FAIL_STA_INVALID:
 100                 priv->_agn.reply_tx_stats.sta_invalid++;
 101                 break;
 102         case TX_STATUS_FAIL_FRAG_DROPPED:
 103                 priv->_agn.reply_tx_stats.frag_drop++;
 104                 break;
 105         case TX_STATUS_FAIL_TID_DISABLE:
 106                 priv->_agn.reply_tx_stats.tid_disable++;
 107                 break;
 108         case TX_STATUS_FAIL_FIFO_FLUSHED:
 109                 priv->_agn.reply_tx_stats.fifo_flush++;
 110                 break;
 111         case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
 112                 priv->_agn.reply_tx_stats.insuff_cf_poll++;
 113                 break;
 114         case TX_STATUS_FAIL_PASSIVE_NO_RX:
 115                 priv->_agn.reply_tx_stats.fail_hw_drop++;
 116                 break;
 117         case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
 118                 priv->_agn.reply_tx_stats.sta_color_mismatch++;
 119                 break;
 120         default:
 121                 priv->_agn.reply_tx_stats.unknown++;
 122                 break;
 123         }
 124 }
 125
 126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
 127 {
 128         status &= AGG_TX_STATUS_MSK;
 129
 130         switch (status) {
 131         case AGG_TX_STATE_UNDERRUN_MSK:
 132                 priv->_agn.reply_agg_tx_stats.underrun++;
 133                 break;
 134         case AGG_TX_STATE_BT_PRIO_MSK:
 135                 priv->_agn.reply_agg_tx_stats.bt_prio++;
 136                 break;
 137         case AGG_TX_STATE_FEW_BYTES_MSK:
 138                 priv->_agn.reply_agg_tx_stats.few_bytes++;
 139                 break;
 140         case AGG_TX_STATE_ABORT_MSK:
 141                 priv->_agn.reply_agg_tx_stats.abort++;
 142                 break;
 143         case AGG_TX_STATE_LAST_SENT_TTL_MSK:
 144                 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
 145                 break;
 146         case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
 147                 priv->_agn.reply_agg_tx_stats.last_sent_try++;
 148                 break;
 149         case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
 150                 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
 151                 break;
 152         case AGG_TX_STATE_SCD_QUERY_MSK:
 153                 priv->_agn.reply_agg_tx_stats.scd_query++;
 154                 break;
 155         case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
 156                 priv->_agn.reply_agg_tx_stats.bad_crc32++;
 157                 break;
 158         case AGG_TX_STATE_RESPONSE_MSK:
 159                 priv->_agn.reply_agg_tx_stats.response++;
 160                 break;
 161         case AGG_TX_STATE_DUMP_TX_MSK:
 162                 priv->_agn.reply_agg_tx_stats.dump_tx++;
 163                 break;
 164         case AGG_TX_STATE_DELAY_TX_MSK:
 165                 priv->_agn.reply_agg_tx_stats.delay_tx++;
 166                 break;
 167         default:
 168                 priv->_agn.reply_agg_tx_stats.unknown++;
 169                 break;
 170         }
 171 }
 172
 173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
 174                                  struct ieee80211_tx_info *info,
 175                                  struct iwl_rxon_context *ctx,
 176                                  struct iwlagn_tx_resp *tx_resp,
 177                                  int txq_id, bool is_agg)
 178 {
 179         u16  status = le16_to_cpu(tx_resp->status.status);
 180
 181         info->status.rates[0].count = tx_resp->failure_frame + 1;
 182         if (is_agg)
 183                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 184         info->flags |= iwl_tx_status_to_mac80211(status);
 185         iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
 186                                     info);
 187         if (!iwl_is_tx_success(status))
 188                 iwlagn_count_tx_err_status(priv, status);
 189
 190         if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&
 191             iwl_is_associated_ctx(ctx) && ctx->vif &&
 192             ctx->vif->type == NL80211_IFTYPE_STATION) {
 193                 ctx->last_tx_rejected = true;
 194                 iwl_stop_queue(priv, &priv->txq[txq_id]);
 195         }
 196
 197         IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
 198                            "0x%x retries %d\n",
 199                            txq_id,
 200                            iwl_get_tx_fail_reason(status), status,
 201                            le32_to_cpu(tx_resp->rate_n_flags),
 202                            tx_resp->failure_frame);
 203 }
 204
 205 #ifdef CONFIG_IWLWIFI_DEBUG
 206 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
 207
 208 const char *iwl_get_agg_tx_fail_reason(u16 status)
 209 {
 210         status &= AGG_TX_STATUS_MSK;
 211         switch (status) {
 212         case AGG_TX_STATE_TRANSMITTED:
 213                 return "SUCCESS";
 214                 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
 215                 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
 216                 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
 217                 AGG_TX_STATE_FAIL(ABORT_MSK);
 218                 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
 219                 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
 220                 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
 221                 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
 222                 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
 223                 AGG_TX_STATE_FAIL(RESPONSE_MSK);
 224                 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
 225                 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
 226         }
 227
 228         return "UNKNOWN";
 229 }
 230 #endif /* CONFIG_IWLWIFI_DEBUG */
 231
 232 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
 233                                       struct iwl_ht_agg *agg,
 234                                       struct iwlagn_tx_resp *tx_resp,
 235                                       int txq_id, u16 start_idx)
 236 {
 237         u16 status;
 238         struct agg_tx_status *frame_status = &tx_resp->status;
 239         struct ieee80211_hdr *hdr = NULL;
 240         int i, sh, idx;
 241         u16 seq;
 242
 243         if (agg->wait_for_ba)
 244                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 245
 246         agg->frame_count = tx_resp->frame_count;
 247         agg->start_idx = start_idx;
 248         agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 249         agg->bitmap = 0;
 250
 251         /* # frames attempted by Tx command */
 252         if (agg->frame_count == 1) {
 253                 struct iwl_tx_info *txb;
 254
 255                 /* Only one frame was attempted; no block-ack will arrive */
 256                 idx = start_idx;
 257
 258                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 259                                    agg->frame_count, agg->start_idx, idx);
 260                 txb = &priv->txq[txq_id].txb[idx];
 261                 iwlagn_set_tx_status(priv, IEEE80211_SKB_CB(txb->skb),
 262                                      txb->ctx, tx_resp, txq_id, true);
 263                 agg->wait_for_ba = 0;
 264         } else {
 265                 /* Two or more frames were attempted; expect block-ack */
 266                 u64 bitmap = 0;
 267
 268                 /*
 269                  * Start is the lowest frame sent. It may not be the first
 270                  * frame in the batch; we figure this out dynamically during
 271                  * the following loop.
 272                  */
 273                 int start = agg->start_idx;
 274
 275                 /* Construct bit-map of pending frames within Tx window */
 276                 for (i = 0; i < agg->frame_count; i++) {
 277                         u16 sc;
 278                         status = le16_to_cpu(frame_status[i].status);
 279                         seq  = le16_to_cpu(frame_status[i].sequence);
 280                         idx = SEQ_TO_INDEX(seq);
 281                         txq_id = SEQ_TO_QUEUE(seq);
 282
 283                         if (status & AGG_TX_STATUS_MSK)
 284                                 iwlagn_count_agg_tx_err_status(priv, status);
 285
 286                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
 287                                       AGG_TX_STATE_ABORT_MSK))
 288                                 continue;
 289
 290                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
 291                                            agg->frame_count, txq_id, idx);
 292                         IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
 293                                            "try-count (0x%08x)\n",
 294                                            iwl_get_agg_tx_fail_reason(status),
 295                                            status & AGG_TX_STATUS_MSK,
 296                                            status & AGG_TX_TRY_MSK);
 297
 298                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
 299                         if (!hdr) {
 300                                 IWL_ERR(priv,
 301                                         "BUG_ON idx doesn't point to valid skb"
 302                                         " idx=%d, txq_id=%d\n", idx, txq_id);
 303                                 return -1;
 304                         }
 305
 306                         sc = le16_to_cpu(hdr->seq_ctrl);
 307                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
 308                                 IWL_ERR(priv,
 309                                         "BUG_ON idx doesn't match seq control"
 310                                         " idx=%d, seq_idx=%d, seq=%d\n",
 311                                           idx, SEQ_TO_SN(sc),
 312                                           hdr->seq_ctrl);
 313                                 return -1;
 314                         }
 315
 316                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
 317                                            i, idx, SEQ_TO_SN(sc));
 318
 319                         /*
 320                          * sh -> how many frames ahead of the starting frame is
 321                          * the current one?
 322                          *
 323                          * Note that all frames sent in the batch must be in a
 324                          * 64-frame window, so this number should be in [0,63].
 325                          * If outside of this window, then we've found a new
 326                          * "first" frame in the batch and need to change start.
 327                          */
 328                         sh = idx - start;
 329
 330                         /*
 331                          * If >= 64, out of window. start must be at the front
 332                          * of the circular buffer, idx must be near the end of
 333                          * the buffer, and idx is the new "first" frame. Shift
 334                          * the indices around.
 335                          */
 336                         if (sh >= 64) {
 337                                 /* Shift bitmap by start - idx, wrapped */
 338                                 sh = 0x100 - idx + start;
 339                                 bitmap = bitmap << sh;
 340                                 /* Now idx is the new start so sh = 0 */
 341                                 sh = 0;
 342                                 start = idx;
 343                         /*
 344                          * If <= -64 then wraps the 256-pkt circular buffer
 345                          * (e.g., start = 255 and idx = 0, sh should be 1)
 346                          */
 347                         } else if (sh <= -64) {
 348                                 sh  = 0x100 - start + idx;
 349                         /*
 350                          * If < 0 but > -64, out of window. idx is before start
 351                          * but not wrapped. Shift the indices around.
 352                          */
 353                         } else if (sh < 0) {
 354                                 /* Shift by how far start is ahead of idx */
 355                                 sh = start - idx;
 356                                 bitmap = bitmap << sh;
 357                                 /* Now idx is the new start so sh = 0 */
 358                                 start = idx;
 359                                 sh = 0;
 360                         }
 361                         /* Sequence number start + sh was sent in this batch */
 362                         bitmap |= 1ULL << sh;
 363                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
 364                                            start, (unsigned long long)bitmap);
 365                 }
 366
 367                 /*
 368                  * Store the bitmap and possibly the new start, if we wrapped
 369                  * the buffer above
 370                  */
 371                 agg->bitmap = bitmap;
 372                 agg->start_idx = start;
 373                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
 374                                    agg->frame_count, agg->start_idx,
 375                                    (unsigned long long)agg->bitmap);
 376
 377                 if (bitmap)
 378                         agg->wait_for_ba = 1;
 379         }
 380         return 0;
 381 }
 382
 383 void iwl_check_abort_status(struct iwl_priv *priv,
 384                             u8 frame_count, u32 status)
 385 {
 386         if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
 387                 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
 388                 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 389                         queue_work(priv->workqueue, &priv->tx_flush);
 390         }
 391 }
 392
 393 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
 394                                 struct iwl_rx_mem_buffer *rxb)
 395 {
 396         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 397         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 398         int txq_id = SEQ_TO_QUEUE(sequence);
 399         int index = SEQ_TO_INDEX(sequence);
 400         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 401         struct ieee80211_tx_info *info;
 402         struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 403         struct iwl_tx_info *txb;
 404         u32 status = le16_to_cpu(tx_resp->status.status);
 405         int tid;
 406         int sta_id;
 407         int freed;
 408         unsigned long flags;
 409
 410         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 411                 IWL_ERR(priv, "%s: Read index for DMA queue txq_id (%d) "
 412                           "index %d is out of range [0-%d] %d %d\n", __func__,
 413                           txq_id, index, txq->q.n_bd, txq->q.write_ptr,
 414                           txq->q.read_ptr);
 415                 return;
 416         }
 417
 418         txq->time_stamp = jiffies;
 419         txb = &txq->txb[txq->q.read_ptr];
 420         info = IEEE80211_SKB_CB(txb->skb);
 421         memset(&info->status, 0, sizeof(info->status));
 422
 423         tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
 424                 IWLAGN_TX_RES_TID_POS;
 425         sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
 426                 IWLAGN_TX_RES_RA_POS;
 427
 428         spin_lock_irqsave(&priv->sta_lock, flags);
 429         if (txq->sched_retry) {
 430                 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
 431                 struct iwl_ht_agg *agg;
 432
 433                 agg = &priv->stations[sta_id].tid[tid].agg;
 434                 /*
 435                  * If the BT kill count is non-zero, we'll get this
 436                  * notification again.
 437                  */
 438                 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
 439                     priv->cfg->bt_params &&
 440                     priv->cfg->bt_params->advanced_bt_coexist) {
 441                         IWL_DEBUG_COEX(priv, "receive reply tx with bt_kill\n");
 442                 }
 443                 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
 444
 445                 /* check if BAR is needed */
 446                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
 447                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
 448
 449                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
 450                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
 451                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
 452                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
 453                                         scd_ssn , index, txq_id, txq->swq_id);
 454
 455                         freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 456                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 457
 458                         if (priv->mac80211_registered &&
 459                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
 460                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
 461                                 iwl_wake_queue(priv, txq);
 462                 }
 463         } else {
 464                 iwlagn_set_tx_status(priv, info, txb->ctx, tx_resp,
 465                                      txq_id, false);
 466                 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 467                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 468
 469                 if (priv->mac80211_registered &&
 470                     iwl_queue_space(&txq->q) > txq->q.low_mark &&
 471                     status != TX_STATUS_FAIL_PASSIVE_NO_RX)
 472                         iwl_wake_queue(priv, txq);
 473         }
 474
 475         iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
 476
 477         iwl_check_abort_status(priv, tx_resp->frame_count, status);
 478         spin_unlock_irqrestore(&priv->sta_lock, flags);
 479 }
 480
 481 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
 482 {
 483         /* init calibration handlers */
 484         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
 485                                         iwlagn_rx_calib_result;
 486         priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
 487
 488         /* set up notification wait support */
 489         spin_lock_init(&priv->_agn.notif_wait_lock);
 490         INIT_LIST_HEAD(&priv->_agn.notif_waits);
 491         init_waitqueue_head(&priv->_agn.notif_waitq);
 492 }
 493
 494 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
 495 {
 496         /*
 497          * nothing need to be done here anymore
 498          * still keep for future use if needed
 499          */
 500 }
 501
 502 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
 503 {
 504         return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
 505                 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
 506 }
 507
 508 int iwlagn_send_tx_power(struct iwl_priv *priv)
 509 {
 510         struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
 511         u8 tx_ant_cfg_cmd;
 512
 513         if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
 514                       "TX Power requested while scanning!\n"))
 515                 return -EAGAIN;
 516
 517         /* half dBm need to multiply */
 518         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
 519
 520         if (priv->tx_power_lmt_in_half_dbm &&
 521             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
 522                 /*
 523                  * For the newer devices which using enhanced/extend tx power
 524                  * table in EEPROM, the format is in half dBm. driver need to
 525                  * convert to dBm format before report to mac80211.
 526                  * By doing so, there is a possibility of 1/2 dBm resolution
 527                  * lost. driver will perform "round-up" operation before
 528                  * reporting, but it will cause 1/2 dBm tx power over the
 529                  * regulatory limit. Perform the checking here, if the
 530                  * "tx_power_user_lmt" is higher than EEPROM value (in
 531                  * half-dBm format), lower the tx power based on EEPROM
 532                  */
 533                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
 534         }
 535         tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
 536         tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
 537
 538         if (IWL_UCODE_API(priv->ucode_ver) == 1)
 539                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
 540         else
 541                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
 542
 543         return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
 544                                 &tx_power_cmd);
 545 }
 546
 547 void iwlagn_temperature(struct iwl_priv *priv)
 548 {
 549         /* store temperature from correct statistics (in Celsius) */
 550         priv->temperature = le32_to_cpu(priv->statistics.common.temperature);
 551         iwl_tt_handler(priv);
 552 }
 553
 554 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
 555 {
 556         struct iwl_eeprom_calib_hdr {
 557                 u8 version;
 558                 u8 pa_type;
 559                 u16 voltage;
 560         } *hdr;
 561
 562         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 563                                                         EEPROM_CALIB_ALL);
 564         return hdr->version;
 565
 566 }
 567
 568 /*
 569  * EEPROM
 570  */
 571 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 572 {
 573         u16 offset = 0;
 574
 575         if ((address & INDIRECT_ADDRESS) == 0)
 576                 return address;
 577
 578         switch (address & INDIRECT_TYPE_MSK) {
 579         case INDIRECT_HOST:
 580                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
 581                 break;
 582         case INDIRECT_GENERAL:
 583                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
 584                 break;
 585         case INDIRECT_REGULATORY:
 586                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
 587                 break;
 588         case INDIRECT_TXP_LIMIT:
 589                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
 590                 break;
 591         case INDIRECT_TXP_LIMIT_SIZE:
 592                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
 593                 break;
 594         case INDIRECT_CALIBRATION:
 595                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
 596                 break;
 597         case INDIRECT_PROCESS_ADJST:
 598                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
 599                 break;
 600         case INDIRECT_OTHERS:
 601                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
 602                 break;
 603         default:
 604                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 605                 address & INDIRECT_TYPE_MSK);
 606                 break;
 607         }
 608
 609         /* translate the offset from words to byte */
 610         return (address & ADDRESS_MSK) + (offset << 1);
 611 }
 612
 613 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
 614                                            size_t offset)
 615 {
 616         u32 address = eeprom_indirect_address(priv, offset);
 617         BUG_ON(address >= priv->cfg->base_params->eeprom_size);
 618         return &priv->eeprom[address];
 619 }
 620
 621 struct iwl_mod_params iwlagn_mod_params = {
 622         .amsdu_size_8K = 1,
 623         .restart_fw = 1,
 624         .plcp_check = true,
 625         .bt_coex_active = true,
 626         .no_sleep_autoadjust = true,
 627         /* the rest are 0 by default */
 628 };
 629
 630 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 631 {
 632         unsigned long flags;
 633         int i;
 634         spin_lock_irqsave(&rxq->lock, flags);
 635         INIT_LIST_HEAD(&rxq->rx_free);
 636         INIT_LIST_HEAD(&rxq->rx_used);
 637         /* Fill the rx_used queue with _all_ of the Rx buffers */
 638         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 639                 /* In the reset function, these buffers may have been allocated
 640                  * to an SKB, so we need to unmap and free potential storage */
 641                 if (rxq->pool[i].page != NULL) {
 642                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 643                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 644                                 PCI_DMA_FROMDEVICE);
 645                         __iwl_free_pages(priv, rxq->pool[i].page);
 646                         rxq->pool[i].page = NULL;
 647                 }
 648                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 649         }
 650
 651         for (i = 0; i < RX_QUEUE_SIZE; i++)
 652                 rxq->queue[i] = NULL;
 653
 654         /* Set us so that we have processed and used all buffers, but have
 655          * not restocked the Rx queue with fresh buffers */
 656         rxq->read = rxq->write = 0;
 657         rxq->write_actual = 0;
 658         rxq->free_count = 0;
 659         spin_unlock_irqrestore(&rxq->lock, flags);
 660 }
 661
 662 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 663 {
 664         u32 rb_size;
 665         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 666         u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
 667
 668         rb_timeout = RX_RB_TIMEOUT;
 669
 670         if (iwlagn_mod_params.amsdu_size_8K)
 671                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 672         else
 673                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 674
 675         /* Stop Rx DMA */
 676         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 677
 678         /* Reset driver's Rx queue write index */
 679         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 680
 681         /* Tell device where to find RBD circular buffer in DRAM */
 682         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 683                            (u32)(rxq->bd_dma >> 8));
 684
 685         /* Tell device where in DRAM to update its Rx status */
 686         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 687                            rxq->rb_stts_dma >> 4);
 688
 689         /* Enable Rx DMA
 690          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 691          *      the credit mechanism in 5000 HW RX FIFO
 692          * Direct rx interrupts to hosts
 693          * Rx buffer size 4 or 8k
 694          * RB timeout 0x10
 695          * 256 RBDs
 696          */
 697         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 698                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 699                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 700                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 701                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 702                            rb_size|
 703                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 704                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 705
 706         /* Set interrupt coalescing timer to default (2048 usecs) */
 707         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 708
 709         return 0;
 710 }
 711
 712 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
 713 {
 714 /*
 715  * (for documentation purposes)
 716  * to set power to V_AUX, do:
 717
 718                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 719                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 720                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 721                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 722  */
 723
 724         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 725                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 726                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 727 }
 728
 729 int iwlagn_hw_nic_init(struct iwl_priv *priv)
 730 {
 731         unsigned long flags;
 732         struct iwl_rx_queue *rxq = &priv->rxq;
 733         int ret;
 734
 735         /* nic_init */
 736         spin_lock_irqsave(&priv->lock, flags);
 737         priv->cfg->ops->lib->apm_ops.init(priv);
 738
 739         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 740         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 741
 742         spin_unlock_irqrestore(&priv->lock, flags);
 743
 744         iwlagn_set_pwr_vmain(priv);
 745
 746         priv->cfg->ops->lib->apm_ops.config(priv);
 747
 748         /* Allocate the RX queue, or reset if it is already allocated */
 749         if (!rxq->bd) {
 750                 ret = iwl_rx_queue_alloc(priv);
 751                 if (ret) {
 752                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
 753                         return -ENOMEM;
 754                 }
 755         } else
 756                 iwlagn_rx_queue_reset(priv, rxq);
 757
 758         iwlagn_rx_replenish(priv);
 759
 760         iwlagn_rx_init(priv, rxq);
 761
 762         spin_lock_irqsave(&priv->lock, flags);
 763
 764         rxq->need_update = 1;
 765         iwl_rx_queue_update_write_ptr(priv, rxq);
 766
 767         spin_unlock_irqrestore(&priv->lock, flags);
 768
 769         /* Allocate or reset and init all Tx and Command queues */
 770         if (!priv->txq) {
 771                 ret = iwlagn_txq_ctx_alloc(priv);
 772                 if (ret)
 773                         return ret;
 774         } else
 775                 iwlagn_txq_ctx_reset(priv);
 776
 777         if (priv->cfg->base_params->shadow_reg_enable) {
 778                 /* enable shadow regs in HW */
 779                 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
 780                         0x800FFFFF);
 781         }
 782
 783         set_bit(STATUS_INIT, &priv->status);
 784
 785         return 0;
 786 }
 787
 788 /**
 789  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 790  */
 791 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
 792                                           dma_addr_t dma_addr)
 793 {
 794         return cpu_to_le32((u32)(dma_addr >> 8));
 795 }
 796
 797 /**
 798  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 799  *
 800  * If there are slots in the RX queue that need to be restocked,
 801  * and we have free pre-allocated buffers, fill the ranks as much
 802  * as we can, pulling from rx_free.
 803  *
 804  * This moves the 'write' index forward to catch up with 'processed', and
 805  * also updates the memory address in the firmware to reference the new
 806  * target buffer.
 807  */
 808 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
 809 {
 810         struct iwl_rx_queue *rxq = &priv->rxq;
 811         struct list_head *element;
 812         struct iwl_rx_mem_buffer *rxb;
 813         unsigned long flags;
 814
 815         spin_lock_irqsave(&rxq->lock, flags);
 816         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 817                 /* The overwritten rxb must be a used one */
 818                 rxb = rxq->queue[rxq->write];
 819                 BUG_ON(rxb && rxb->page);
 820
 821                 /* Get next free Rx buffer, remove from free list */
 822                 element = rxq->rx_free.next;
 823                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 824                 list_del(element);
 825
 826                 /* Point to Rx buffer via next RBD in circular buffer */
 827                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
 828                                                               rxb->page_dma);
 829                 rxq->queue[rxq->write] = rxb;
 830                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 831                 rxq->free_count--;
 832         }
 833         spin_unlock_irqrestore(&rxq->lock, flags);
 834         /* If the pre-allocated buffer pool is dropping low, schedule to
 835          * refill it */
 836         if (rxq->free_count <= RX_LOW_WATERMARK)
 837                 queue_work(priv->workqueue, &priv->rx_replenish);
 838
 839
 840         /* If we've added more space for the firmware to place data, tell it.
 841          * Increment device's write pointer in multiples of 8. */
 842         if (rxq->write_actual != (rxq->write & ~0x7)) {
 843                 spin_lock_irqsave(&rxq->lock, flags);
 844                 rxq->need_update = 1;
 845                 spin_unlock_irqrestore(&rxq->lock, flags);
 846                 iwl_rx_queue_update_write_ptr(priv, rxq);
 847         }
 848 }
 849
 850 /**
 851  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 852  *
 853  * When moving to rx_free an SKB is allocated for the slot.
 854  *
 855  * Also restock the Rx queue via iwl_rx_queue_restock.
 856  * This is called as a scheduled work item (except for during initialization)
 857  */
 858 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
 859 {
 860         struct iwl_rx_queue *rxq = &priv->rxq;
 861         struct list_head *element;
 862         struct iwl_rx_mem_buffer *rxb;
 863         struct page *page;
 864         unsigned long flags;
 865         gfp_t gfp_mask = priority;
 866
 867         while (1) {
 868                 spin_lock_irqsave(&rxq->lock, flags);
 869                 if (list_empty(&rxq->rx_used)) {
 870                         spin_unlock_irqrestore(&rxq->lock, flags);
 871                         return;
 872                 }
 873                 spin_unlock_irqrestore(&rxq->lock, flags);
 874
 875                 if (rxq->free_count > RX_LOW_WATERMARK)
 876                         gfp_mask |= __GFP_NOWARN;
 877
 878                 if (priv->hw_params.rx_page_order > 0)
 879                         gfp_mask |= __GFP_COMP;
 880
 881                 /* Alloc a new receive buffer */
 882                 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
 883                 if (!page) {
 884                         if (net_ratelimit())
 885                                 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
 886                                                "order: %d\n",
 887                                                priv->hw_params.rx_page_order);
 888
 889                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 890                             net_ratelimit())
 891                                 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
 892                                          priority == GFP_ATOMIC ?  "GFP_ATOMIC" : "GFP_KERNEL",
 893                                          rxq->free_count);
 894                         /* We don't reschedule replenish work here -- we will
 895                          * call the restock method and if it still needs
 896                          * more buffers it will schedule replenish */
 897                         return;
 898                 }
 899
 900                 spin_lock_irqsave(&rxq->lock, flags);
 901
 902                 if (list_empty(&rxq->rx_used)) {
 903                         spin_unlock_irqrestore(&rxq->lock, flags);
 904                         __free_pages(page, priv->hw_params.rx_page_order);
 905                         return;
 906                 }
 907                 element = rxq->rx_used.next;
 908                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 909                 list_del(element);
 910
 911                 spin_unlock_irqrestore(&rxq->lock, flags);
 912
 913                 BUG_ON(rxb->page);
 914                 rxb->page = page;
 915                 /* Get physical address of the RB */
 916                 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
 917                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 918                                 PCI_DMA_FROMDEVICE);
 919                 /* dma address must be no more than 36 bits */
 920                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 921                 /* and also 256 byte aligned! */
 922                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 923
 924                 spin_lock_irqsave(&rxq->lock, flags);
 925
 926                 list_add_tail(&rxb->list, &rxq->rx_free);
 927                 rxq->free_count++;
 928
 929                 spin_unlock_irqrestore(&rxq->lock, flags);
 930         }
 931 }
 932
 933 void iwlagn_rx_replenish(struct iwl_priv *priv)
 934 {
 935         unsigned long flags;
 936
 937         iwlagn_rx_allocate(priv, GFP_KERNEL);
 938
 939         spin_lock_irqsave(&priv->lock, flags);
 940         iwlagn_rx_queue_restock(priv);
 941         spin_unlock_irqrestore(&priv->lock, flags);
 942 }
 943
 944 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
 945 {
 946         iwlagn_rx_allocate(priv, GFP_ATOMIC);
 947
 948         iwlagn_rx_queue_restock(priv);
 949 }
 950
 951 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
 952  * If an SKB has been detached, the POOL needs to have its SKB set to NULL
 953  * This free routine walks the list of POOL entries and if SKB is set to
 954  * non NULL it is unmapped and freed
 955  */
 956 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 957 {
 958         int i;
 959         for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
 960                 if (rxq->pool[i].page != NULL) {
 961                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 962                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 963                                 PCI_DMA_FROMDEVICE);
 964                         __iwl_free_pages(priv, rxq->pool[i].page);
 965                         rxq->pool[i].page = NULL;
 966                 }
 967         }
 968
 969         dma_free_coherent(priv->bus.dev, 4 * RX_QUEUE_SIZE,
 970                           rxq->bd, rxq->bd_dma);
 971         dma_free_coherent(priv->bus.dev,
 972                           sizeof(struct iwl_rb_status),
 973                           rxq->rb_stts, rxq->rb_stts_dma);
 974         rxq->bd = NULL;
 975         rxq->rb_stts  = NULL;
 976 }
 977
 978 int iwlagn_rxq_stop(struct iwl_priv *priv)
 979 {
 980
 981         /* stop Rx DMA */
 982         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 983         iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
 984                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 985
 986         return 0;
 987 }
 988
 989 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
 990 {
 991         int idx = 0;
 992         int band_offset = 0;
 993
 994         /* HT rate format: mac80211 wants an MCS number, which is just LSB */
 995         if (rate_n_flags & RATE_MCS_HT_MSK) {
 996                 idx = (rate_n_flags & 0xff);
 997                 return idx;
 998         /* Legacy rate format, search for match in table */
 999         } else {
1000                 if (band == IEEE80211_BAND_5GHZ)
1001                         band_offset = IWL_FIRST_OFDM_RATE;
1002                 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
1003                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
1004                                 return idx - band_offset;
1005         }
1006
1007         return -1;
1008 }
1009
1010 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1011                                            struct ieee80211_vif *vif,
1012                                            enum ieee80211_band band,
1013                                            struct iwl_scan_channel *scan_ch)
1014 {
1015         const struct ieee80211_supported_band *sband;
1016         u16 passive_dwell = 0;
1017         u16 active_dwell = 0;
1018         int added = 0;
1019         u16 channel = 0;
1020
1021         sband = iwl_get_hw_mode(priv, band);
1022         if (!sband) {
1023                 IWL_ERR(priv, "invalid band\n");
1024                 return added;
1025         }
1026
1027         active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1028         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1029
1030         if (passive_dwell <= active_dwell)
1031                 passive_dwell = active_dwell + 1;
1032
1033         channel = iwl_get_single_channel_number(priv, band);
1034         if (channel) {
1035                 scan_ch->channel = cpu_to_le16(channel);
1036                 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1037                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1038                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1039                 /* Set txpower levels to defaults */
1040                 scan_ch->dsp_atten = 110;
1041                 if (band == IEEE80211_BAND_5GHZ)
1042                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1043                 else
1044                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1045                 added++;
1046         } else
1047                 IWL_ERR(priv, "no valid channel found\n");
1048         return added;
1049 }
1050
1051 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1052                                      struct ieee80211_vif *vif,
1053                                      enum ieee80211_band band,
1054                                      u8 is_active, u8 n_probes,
1055                                      struct iwl_scan_channel *scan_ch)
1056 {
1057         struct ieee80211_channel *chan;
1058         const struct ieee80211_supported_band *sband;
1059         const struct iwl_channel_info *ch_info;
1060         u16 passive_dwell = 0;
1061         u16 active_dwell = 0;
1062         int added, i;
1063         u16 channel;
1064
1065         sband = iwl_get_hw_mode(priv, band);
1066         if (!sband)
1067                 return 0;
1068
1069         active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1070         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1071
1072         if (passive_dwell <= active_dwell)
1073                 passive_dwell = active_dwell + 1;
1074
1075         for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1076                 chan = priv->scan_request->channels[i];
1077
1078                 if (chan->band != band)
1079                         continue;
1080
1081                 channel = chan->hw_value;
1082                 scan_ch->channel = cpu_to_le16(channel);
1083
1084                 ch_info = iwl_get_channel_info(priv, band, channel);
1085                 if (!is_channel_valid(ch_info)) {
1086                         IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1087                                         channel);
1088                         continue;
1089                 }
1090
1091                 if (!is_active || is_channel_passive(ch_info) ||
1092                     (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1093                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1094                 else
1095                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1096
1097                 if (n_probes)
1098                         scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1099
1100                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1101                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1102
1103                 /* Set txpower levels to defaults */
1104                 scan_ch->dsp_atten = 110;
1105
1106                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1107                  * power level:
1108                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1109                  */
1110                 if (band == IEEE80211_BAND_5GHZ)
1111                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1112                 else
1113                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1114
1115                 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1116                                channel, le32_to_cpu(scan_ch->type),
1117                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1118                                 "ACTIVE" : "PASSIVE",
1119                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1120                                active_dwell : passive_dwell);
1121
1122                 scan_ch++;
1123                 added++;
1124         }
1125
1126         IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1127         return added;
1128 }
1129
1130 static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen)
1131 {
1132         struct sk_buff *skb = priv->_agn.offchan_tx_skb;
1133
1134         if (skb->len < maxlen)
1135                 maxlen = skb->len;
1136
1137         memcpy(data, skb->data, maxlen);
1138
1139         return maxlen;
1140 }
1141
1142 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1143 {
1144         struct iwl_host_cmd cmd = {
1145                 .id = REPLY_SCAN_CMD,
1146                 .len = { sizeof(struct iwl_scan_cmd), },
1147         };
1148         struct iwl_scan_cmd *scan;
1149         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1150         u32 rate_flags = 0;
1151         u16 cmd_len;
1152         u16 rx_chain = 0;
1153         enum ieee80211_band band;
1154         u8 n_probes = 0;
1155         u8 rx_ant = priv->hw_params.valid_rx_ant;
1156         u8 rate;
1157         bool is_active = false;
1158         int  chan_mod;
1159         u8 active_chains;
1160         u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1161         int ret;
1162
1163         lockdep_assert_held(&priv->mutex);
1164
1165         if (vif)
1166                 ctx = iwl_rxon_ctx_from_vif(vif);
1167
1168         if (!priv->scan_cmd) {
1169                 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1170                                          IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1171                 if (!priv->scan_cmd) {
1172                         IWL_DEBUG_SCAN(priv,
1173                                        "fail to allocate memory for scan\n");
1174                         return -ENOMEM;
1175                 }
1176         }
1177         scan = priv->scan_cmd;
1178         memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1179
1180         scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1181         scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1182
1183         if (priv->scan_type != IWL_SCAN_OFFCH_TX &&
1184             iwl_is_any_associated(priv)) {
1185                 u16 interval = 0;
1186                 u32 extra;
1187                 u32 suspend_time = 100;
1188                 u32 scan_suspend_time = 100;
1189
1190                 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1191                 switch (priv->scan_type) {
1192                 case IWL_SCAN_OFFCH_TX:
1193                         WARN_ON(1);
1194                         break;
1195                 case IWL_SCAN_RADIO_RESET:
1196                         interval = 0;
1197                         break;
1198                 case IWL_SCAN_NORMAL:
1199                         interval = vif->bss_conf.beacon_int;
1200                         break;
1201                 }
1202
1203                 scan->suspend_time = 0;
1204                 scan->max_out_time = cpu_to_le32(200 * 1024);
1205                 if (!interval)
1206                         interval = suspend_time;
1207
1208                 extra = (suspend_time / interval) << 22;
1209                 scan_suspend_time = (extra |
1210                     ((suspend_time % interval) * 1024));
1211                 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1212                 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1213                                scan_suspend_time, interval);
1214         } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) {
1215                 scan->suspend_time = 0;
1216                 scan->max_out_time =
1217                         cpu_to_le32(1024 * priv->_agn.offchan_tx_timeout);
1218         }
1219
1220         switch (priv->scan_type) {
1221         case IWL_SCAN_RADIO_RESET:
1222                 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1223                 break;
1224         case IWL_SCAN_NORMAL:
1225                 if (priv->scan_request->n_ssids) {
1226                         int i, p = 0;
1227                         IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1228                         for (i = 0; i < priv->scan_request->n_ssids; i++) {
1229                                 /* always does wildcard anyway */
1230                                 if (!priv->scan_request->ssids[i].ssid_len)
1231                                         continue;
1232                                 scan->direct_scan[p].id = WLAN_EID_SSID;
1233                                 scan->direct_scan[p].len =
1234                                         priv->scan_request->ssids[i].ssid_len;
1235                                 memcpy(scan->direct_scan[p].ssid,
1236                                        priv->scan_request->ssids[i].ssid,
1237                                        priv->scan_request->ssids[i].ssid_len);
1238                                 n_probes++;
1239                                 p++;
1240                         }
1241                         is_active = true;
1242                 } else
1243                         IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1244                 break;
1245         case IWL_SCAN_OFFCH_TX:
1246                 IWL_DEBUG_SCAN(priv, "Start offchannel TX scan.\n");
1247                 break;
1248         }
1249
1250         scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1251         scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1252         scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1253
1254         switch (priv->scan_band) {
1255         case IEEE80211_BAND_2GHZ:
1256                 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1257                 chan_mod = le32_to_cpu(
1258                         priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1259                                                 RXON_FLG_CHANNEL_MODE_MSK)
1260                                        >> RXON_FLG_CHANNEL_MODE_POS;
1261                 if (chan_mod == CHANNEL_MODE_PURE_40) {
1262                         rate = IWL_RATE_6M_PLCP;
1263                 } else {
1264                         rate = IWL_RATE_1M_PLCP;
1265                         rate_flags = RATE_MCS_CCK_MSK;
1266                 }
1267                 /*
1268                  * Internal scans are passive, so we can indiscriminately set
1269                  * the BT ignore flag on 2.4 GHz since it applies to TX only.
1270                  */
1271                 if (priv->cfg->bt_params &&
1272                     priv->cfg->bt_params->advanced_bt_coexist)
1273                         scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1274                 break;
1275         case IEEE80211_BAND_5GHZ:
1276                 rate = IWL_RATE_6M_PLCP;
1277                 break;
1278         default:
1279                 IWL_WARN(priv, "Invalid scan band\n");
1280                 return -EIO;
1281         }
1282
1283         /*
1284          * If active scanning is requested but a certain channel is
1285          * marked passive, we can do active scanning if we detect
1286          * transmissions.
1287          *
1288          * There is an issue with some firmware versions that triggers
1289          * a sysassert on a "good CRC threshold" of zero (== disabled),
1290          * on a radar channel even though this means that we should NOT
1291          * send probes.
1292          *
1293          * The "good CRC threshold" is the number of frames that we
1294          * need to receive during our dwell time on a channel before
1295          * sending out probes -- setting this to a huge value will
1296          * mean we never reach it, but at the same time work around
1297          * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1298          * here instead of IWL_GOOD_CRC_TH_DISABLED.
1299          *
1300          * This was fixed in later versions along with some other
1301          * scan changes, and the threshold behaves as a flag in those
1302          * versions.
1303          */
1304         if (priv->new_scan_threshold_behaviour)
1305                 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1306                                                 IWL_GOOD_CRC_TH_DISABLED;
1307         else
1308                 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1309                                                 IWL_GOOD_CRC_TH_NEVER;
1310
1311         band = priv->scan_band;
1312
1313         if (priv->cfg->scan_rx_antennas[band])
1314                 rx_ant = priv->cfg->scan_rx_antennas[band];
1315
1316         if (band == IEEE80211_BAND_2GHZ &&
1317             priv->cfg->bt_params &&
1318             priv->cfg->bt_params->advanced_bt_coexist) {
1319                 /* transmit 2.4 GHz probes only on first antenna */
1320                 scan_tx_antennas = first_antenna(scan_tx_antennas);
1321         }
1322
1323         priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1324                                                     scan_tx_antennas);
1325         rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1326         scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1327
1328         /* In power save mode use one chain, otherwise use all chains */
1329         if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1330                 /* rx_ant has been set to all valid chains previously */
1331                 active_chains = rx_ant &
1332                                 ((u8)(priv->chain_noise_data.active_chains));
1333                 if (!active_chains)
1334                         active_chains = rx_ant;
1335
1336                 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1337                                 priv->chain_noise_data.active_chains);
1338
1339                 rx_ant = first_antenna(active_chains);
1340         }
1341         if (priv->cfg->bt_params &&
1342             priv->cfg->bt_params->advanced_bt_coexist &&
1343             priv->bt_full_concurrent) {
1344                 /* operated as 1x1 in full concurrency mode */
1345                 rx_ant = first_antenna(rx_ant);
1346         }
1347
1348         /* MIMO is not used here, but value is required */
1349         rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1350         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1351         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1352         rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1353         scan->rx_chain = cpu_to_le16(rx_chain);
1354         switch (priv->scan_type) {
1355         case IWL_SCAN_NORMAL:
1356                 cmd_len = iwl_fill_probe_req(priv,
1357                                         (struct ieee80211_mgmt *)scan->data,
1358                                         vif->addr,
1359                                         priv->scan_request->ie,
1360                                         priv->scan_request->ie_len,
1361                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1362                 break;
1363         case IWL_SCAN_RADIO_RESET:
1364                 /* use bcast addr, will not be transmitted but must be valid */
1365                 cmd_len = iwl_fill_probe_req(priv,
1366                                         (struct ieee80211_mgmt *)scan->data,
1367                                         iwl_bcast_addr, NULL, 0,
1368                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1369                 break;
1370         case IWL_SCAN_OFFCH_TX:
1371                 cmd_len = iwl_fill_offch_tx(priv, scan->data,
1372                                             IWL_MAX_SCAN_SIZE
1373                                              - sizeof(*scan)
1374                                              - sizeof(struct iwl_scan_channel));
1375                 scan->scan_flags |= IWL_SCAN_FLAGS_ACTION_FRAME_TX;
1376                 break;
1377         default:
1378                 BUG();
1379         }
1380         scan->tx_cmd.len = cpu_to_le16(cmd_len);
1381
1382         scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1383                                RXON_FILTER_BCON_AWARE_MSK);
1384
1385         switch (priv->scan_type) {
1386         case IWL_SCAN_RADIO_RESET:
1387                 scan->channel_count =
1388                         iwl_get_single_channel_for_scan(priv, vif, band,
1389                                 (void *)&scan->data[cmd_len]);
1390                 break;
1391         case IWL_SCAN_NORMAL:
1392                 scan->channel_count =
1393                         iwl_get_channels_for_scan(priv, vif, band,
1394                                 is_active, n_probes,
1395                                 (void *)&scan->data[cmd_len]);
1396                 break;
1397         case IWL_SCAN_OFFCH_TX: {
1398                 struct iwl_scan_channel *scan_ch;
1399
1400                 scan->channel_count = 1;
1401
1402                 scan_ch = (void *)&scan->data[cmd_len];
1403                 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1404                 scan_ch->channel =
1405                         cpu_to_le16(priv->_agn.offchan_tx_chan->hw_value);
1406                 scan_ch->active_dwell =
1407                         cpu_to_le16(priv->_agn.offchan_tx_timeout);
1408                 scan_ch->passive_dwell = 0;
1409
1410                 /* Set txpower levels to defaults */
1411                 scan_ch->dsp_atten = 110;
1412
1413                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1414                  * power level:
1415                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1416                  */
1417                 if (priv->_agn.offchan_tx_chan->band == IEEE80211_BAND_5GHZ)
1418                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1419                 else
1420                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1421                 }
1422                 break;
1423         }
1424
1425         if (scan->channel_count == 0) {
1426                 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1427                 return -EIO;
1428         }
1429
1430         cmd.len[0] += le16_to_cpu(scan->tx_cmd.len) +
1431             scan->channel_count * sizeof(struct iwl_scan_channel);
1432         cmd.data[0] = scan;
1433         cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
1434         scan->len = cpu_to_le16(cmd.len[0]);
1435
1436         /* set scan bit here for PAN params */
1437         set_bit(STATUS_SCAN_HW, &priv->status);
1438
1439         if (priv->cfg->ops->hcmd->set_pan_params) {
1440                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1441                 if (ret)
1442                         return ret;
1443         }
1444
1445         ret = iwl_send_cmd_sync(priv, &cmd);
1446         if (ret) {
1447                 clear_bit(STATUS_SCAN_HW, &priv->status);
1448                 if (priv->cfg->ops->hcmd->set_pan_params)
1449                         priv->cfg->ops->hcmd->set_pan_params(priv);
1450         }
1451
1452         return ret;
1453 }
1454
1455 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1456                                struct ieee80211_vif *vif, bool add)
1457 {
1458         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1459
1460         if (add)
1461                 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1462                                                 vif->bss_conf.bssid,
1463                                                 &vif_priv->ibss_bssid_sta_id);
1464         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1465                                   vif->bss_conf.bssid);
1466 }
1467
1468 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1469                             int sta_id, int tid, int freed)
1470 {
1471         lockdep_assert_held(&priv->sta_lock);
1472
1473         if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1474                 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1475         else {
1476                 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1477                         priv->stations[sta_id].tid[tid].tfds_in_queue,
1478                         freed);
1479                 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1480         }
1481 }
1482
1483 #define IWL_FLUSH_WAIT_MS       2000
1484
1485 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1486 {
1487         struct iwl_tx_queue *txq;
1488         struct iwl_queue *q;
1489         int cnt;
1490         unsigned long now = jiffies;
1491         int ret = 0;
1492
1493         /* waiting for all the tx frames complete might take a while */
1494         for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1495                 if (cnt == priv->cmd_queue)
1496                         continue;
1497                 txq = &priv->txq[cnt];
1498                 q = &txq->q;
1499                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1500                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1501                                 msleep(1);
1502
1503                 if (q->read_ptr != q->write_ptr) {
1504                         IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1505                         ret = -ETIMEDOUT;
1506                         break;
1507                 }
1508         }
1509         return ret;
1510 }
1511
1512 #define IWL_TX_QUEUE_MSK        0xfffff
1513
1514 /**
1515  * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1516  *
1517  * pre-requirements:
1518  *  1. acquire mutex before calling
1519  *  2. make sure rf is on and not in exit state
1520  */
1521 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1522 {
1523         struct iwl_txfifo_flush_cmd flush_cmd;
1524         struct iwl_host_cmd cmd = {
1525                 .id = REPLY_TXFIFO_FLUSH,
1526                 .len = { sizeof(struct iwl_txfifo_flush_cmd), },
1527                 .flags = CMD_SYNC,
1528                 .data = { &flush_cmd, },
1529         };
1530
1531         might_sleep();
1532
1533         memset(&flush_cmd, 0, sizeof(flush_cmd));
1534         if (flush_control & BIT(IWL_RXON_CTX_BSS))
1535                 flush_cmd.fifo_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK |
1536                                  IWL_SCD_BE_MSK | IWL_SCD_BK_MSK |
1537                                  IWL_SCD_MGMT_MSK;
1538         if ((flush_control & BIT(IWL_RXON_CTX_PAN)) &&
1539             (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)))
1540                 flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK |
1541                                 IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK |
1542                                 IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK |
1543                                 IWL_PAN_SCD_MULTICAST_MSK;
1544
1545         if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
1546                 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1547
1548         IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1549                        flush_cmd.fifo_control);
1550         flush_cmd.flush_control = cpu_to_le16(flush_control);
1551
1552         return iwl_send_cmd(priv, &cmd);
1553 }
1554
1555 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1556 {
1557         mutex_lock(&priv->mutex);
1558         ieee80211_stop_queues(priv->hw);
1559         if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) {
1560                 IWL_ERR(priv, "flush request fail\n");
1561                 goto done;
1562         }
1563         IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1564         iwlagn_wait_tx_queue_empty(priv);
1565 done:
1566         ieee80211_wake_queues(priv->hw);
1567         mutex_unlock(&priv->mutex);
1568 }
1569
1570 /*
1571  * BT coex
1572  */
1573 /*
1574  * Macros to access the lookup table.
1575  *
1576  * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1577 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1578  *
1579  * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1580  *
1581  * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1582  * one after another in 32-bit registers, and "registers" 0 through 7 contain
1583  * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1584  *
1585  * These macros encode that format.
1586  */
1587 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1588                   wifi_txrx, wifi_sh_ant_req) \
1589         (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1590         (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1591
1592 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1593         lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1594 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1595                                  wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1596         (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1597                                    bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1598                                    wifi_sh_ant_req))))
1599 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1600                                 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1601         LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1602                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1603                                wifi_sh_ant_req))
1604 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1605                                   wifi_req, wifi_prio, wifi_txrx, \
1606                                   wifi_sh_ant_req) \
1607         LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1608                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1609                                wifi_sh_ant_req))
1610
1611 #define LUT_WLAN_KILL_OP(lut, op, val) \
1612         lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1613 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1614                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1615         (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1616                              wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1617 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1618                           wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1619         LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1620                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1621 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1622                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1623         LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1624                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1625
1626 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1627         lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1628 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1629                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1630         (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1631                               wifi_req, wifi_prio, wifi_txrx, \
1632                               wifi_sh_ant_req))))
1633 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1634                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1635         LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1636                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1637 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1638                              wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1639         LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1640                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1641
1642 static const __le32 iwlagn_def_3w_lookup[12] = {
1643         cpu_to_le32(0xaaaaaaaa),
1644         cpu_to_le32(0xaaaaaaaa),
1645         cpu_to_le32(0xaeaaaaaa),
1646         cpu_to_le32(0xaaaaaaaa),
1647         cpu_to_le32(0xcc00ff28),
1648         cpu_to_le32(0x0000aaaa),
1649         cpu_to_le32(0xcc00aaaa),
1650         cpu_to_le32(0x0000aaaa),
1651         cpu_to_le32(0xc0004000),
1652         cpu_to_le32(0x00004000),
1653         cpu_to_le32(0xf0005000),
1654         cpu_to_le32(0xf0005000),
1655 };
1656
1657 static const __le32 iwlagn_concurrent_lookup[12] = {
1658         cpu_to_le32(0xaaaaaaaa),
1659         cpu_to_le32(0xaaaaaaaa),
1660         cpu_to_le32(0xaaaaaaaa),
1661         cpu_to_le32(0xaaaaaaaa),
1662         cpu_to_le32(0xaaaaaaaa),
1663         cpu_to_le32(0xaaaaaaaa),
1664         cpu_to_le32(0xaaaaaaaa),
1665         cpu_to_le32(0xaaaaaaaa),
1666         cpu_to_le32(0x00000000),
1667         cpu_to_le32(0x00000000),
1668         cpu_to_le32(0x00000000),
1669         cpu_to_le32(0x00000000),
1670 };
1671
1672 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1673 {
1674         struct iwl_basic_bt_cmd basic = {
1675                 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1676                 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1677                 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1678                 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1679         };
1680         struct iwl6000_bt_cmd bt_cmd_6000;
1681         struct iwl2000_bt_cmd bt_cmd_2000;
1682         int ret;
1683
1684         BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1685                         sizeof(basic.bt3_lookup_table));
1686
1687         if (priv->cfg->bt_params) {
1688                 if (priv->cfg->bt_params->bt_session_2) {
1689                         bt_cmd_2000.prio_boost = cpu_to_le32(
1690                                 priv->cfg->bt_params->bt_prio_boost);
1691                         bt_cmd_2000.tx_prio_boost = 0;
1692                         bt_cmd_2000.rx_prio_boost = 0;
1693                 } else {
1694                         bt_cmd_6000.prio_boost =
1695                                 priv->cfg->bt_params->bt_prio_boost;
1696                         bt_cmd_6000.tx_prio_boost = 0;
1697                         bt_cmd_6000.rx_prio_boost = 0;
1698                 }
1699         } else {
1700                 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1701                 return;
1702         }
1703
1704         basic.kill_ack_mask = priv->kill_ack_mask;
1705         basic.kill_cts_mask = priv->kill_cts_mask;
1706         basic.valid = priv->bt_valid;
1707
1708         /*
1709          * Configure BT coex mode to "no coexistence" when the
1710          * user disabled BT coexistence, we have no interface
1711          * (might be in monitor mode), or the interface is in
1712          * IBSS mode (no proper uCode support for coex then).
1713          */
1714         if (!iwlagn_mod_params.bt_coex_active ||
1715             priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1716                 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1717         } else {
1718                 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1719                                         IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1720                 if (priv->cfg->bt_params &&
1721                     priv->cfg->bt_params->bt_sco_disable)
1722                         basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1723
1724                 if (priv->bt_ch_announce)
1725                         basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1726                 IWL_DEBUG_COEX(priv, "BT coex flag: 0X%x\n", basic.flags);
1727         }
1728         priv->bt_enable_flag = basic.flags;
1729         if (priv->bt_full_concurrent)
1730                 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1731                         sizeof(iwlagn_concurrent_lookup));
1732         else
1733                 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1734                         sizeof(iwlagn_def_3w_lookup));
1735
1736         IWL_DEBUG_COEX(priv, "BT coex %s in %s mode\n",
1737                        basic.flags ? "active" : "disabled",
1738                        priv->bt_full_concurrent ?
1739                        "full concurrency" : "3-wire");
1740
1741         if (priv->cfg->bt_params->bt_session_2) {
1742                 memcpy(&bt_cmd_2000.basic, &basic,
1743                         sizeof(basic));
1744                 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1745                         sizeof(bt_cmd_2000), &bt_cmd_2000);
1746         } else {
1747                 memcpy(&bt_cmd_6000.basic, &basic,
1748                         sizeof(basic));
1749                 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1750                         sizeof(bt_cmd_6000), &bt_cmd_6000);
1751         }
1752         if (ret)
1753                 IWL_ERR(priv, "failed to send BT Coex Config\n");
1754
1755 }
1756
1757 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1758 {
1759         struct iwl_priv *priv =
1760                 container_of(work, struct iwl_priv, bt_traffic_change_work);
1761         struct iwl_rxon_context *ctx;
1762         int smps_request = -1;
1763
1764         if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1765                 /* bt coex disabled */
1766                 return;
1767         }
1768
1769         /*
1770          * Note: bt_traffic_load can be overridden by scan complete and
1771          * coex profile notifications. Ignore that since only bad consequence
1772          * can be not matching debug print with actual state.
1773          */
1774         IWL_DEBUG_COEX(priv, "BT traffic load changes: %d\n",
1775                        priv->bt_traffic_load);
1776
1777         switch (priv->bt_traffic_load) {
1778         case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1779                 if (priv->bt_status)
1780                         smps_request = IEEE80211_SMPS_DYNAMIC;
1781                 else
1782                         smps_request = IEEE80211_SMPS_AUTOMATIC;
1783                 break;
1784         case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1785                 smps_request = IEEE80211_SMPS_DYNAMIC;
1786                 break;
1787         case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1788         case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1789                 smps_request = IEEE80211_SMPS_STATIC;
1790                 break;
1791         default:
1792                 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1793                         priv->bt_traffic_load);
1794                 break;
1795         }
1796
1797         mutex_lock(&priv->mutex);
1798
1799         /*
1800          * We can not send command to firmware while scanning. When the scan
1801          * complete we will schedule this work again. We do check with mutex
1802          * locked to prevent new scan request to arrive. We do not check
1803          * STATUS_SCANNING to avoid race when queue_work two times from
1804          * different notifications, but quit and not perform any work at all.
1805          */
1806         if (test_bit(STATUS_SCAN_HW, &priv->status))
1807                 goto out;
1808
1809         if (priv->cfg->ops->lib->update_chain_flags)
1810                 priv->cfg->ops->lib->update_chain_flags(priv);
1811
1812         if (smps_request != -1) {
1813                 priv->current_ht_config.smps = smps_request;
1814                 for_each_context(priv, ctx) {
1815                         if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1816                                 ieee80211_request_smps(ctx->vif, smps_request);
1817                 }
1818         }
1819 out:
1820         mutex_unlock(&priv->mutex);
1821 }
1822
1823 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1824                                 struct iwl_bt_uart_msg *uart_msg)
1825 {
1826         IWL_DEBUG_COEX(priv, "Message Type = 0x%X, SSN = 0x%X, "
1827                         "Update Req = 0x%X",
1828                 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1829                         BT_UART_MSG_FRAME1MSGTYPE_POS,
1830                 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1831                         BT_UART_MSG_FRAME1SSN_POS,
1832                 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1833                         BT_UART_MSG_FRAME1UPDATEREQ_POS);
1834
1835         IWL_DEBUG_COEX(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1836                         "Chl_SeqN = 0x%X, In band = 0x%X",
1837                 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1838                         BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1839                 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1840                         BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1841                 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1842                         BT_UART_MSG_FRAME2CHLSEQN_POS,
1843                 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1844                         BT_UART_MSG_FRAME2INBAND_POS);
1845
1846         IWL_DEBUG_COEX(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1847                         "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1848                 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1849                         BT_UART_MSG_FRAME3SCOESCO_POS,
1850                 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1851                         BT_UART_MSG_FRAME3SNIFF_POS,
1852                 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1853                         BT_UART_MSG_FRAME3A2DP_POS,
1854                 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1855                         BT_UART_MSG_FRAME3ACL_POS,
1856                 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1857                         BT_UART_MSG_FRAME3MASTER_POS,
1858                 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1859                         BT_UART_MSG_FRAME3OBEX_POS);
1860
1861         IWL_DEBUG_COEX(priv, "Idle duration = 0x%X",
1862                 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1863                         BT_UART_MSG_FRAME4IDLEDURATION_POS);
1864
1865         IWL_DEBUG_COEX(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1866                         "eSCO Retransmissions = 0x%X",
1867                 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1868                         BT_UART_MSG_FRAME5TXACTIVITY_POS,
1869                 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1870                         BT_UART_MSG_FRAME5RXACTIVITY_POS,
1871                 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1872                         BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1873
1874         IWL_DEBUG_COEX(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1875                 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1876                         BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1877                 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1878                         BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1879
1880         IWL_DEBUG_COEX(priv, "Sniff Activity = 0x%X, Page = "
1881                         "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1882                 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1883                         BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1884                 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
1885                         BT_UART_MSG_FRAME7PAGE_POS,
1886                 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
1887                         BT_UART_MSG_FRAME7INQUIRY_POS,
1888                 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1889                         BT_UART_MSG_FRAME7CONNECTABLE_POS);
1890 }
1891
1892 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
1893                                 struct iwl_bt_uart_msg *uart_msg)
1894 {
1895         u8 kill_msk;
1896         static const __le32 bt_kill_ack_msg[2] = {
1897                 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
1898                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1899         static const __le32 bt_kill_cts_msg[2] = {
1900                 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
1901                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1902
1903         kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
1904                 ? 1 : 0;
1905         if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
1906             priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
1907                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1908                 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
1909                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
1910                 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
1911
1912                 /* schedule to send runtime bt_config */
1913                 queue_work(priv->workqueue, &priv->bt_runtime_config);
1914         }
1915 }
1916
1917 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1918                                              struct iwl_rx_mem_buffer *rxb)
1919 {
1920         unsigned long flags;
1921         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1922         struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1923         struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1924
1925         if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1926                 /* bt coex disabled */
1927                 return;
1928         }
1929
1930         IWL_DEBUG_COEX(priv, "BT Coex notification:\n");
1931         IWL_DEBUG_COEX(priv, "    status: %d\n", coex->bt_status);
1932         IWL_DEBUG_COEX(priv, "    traffic load: %d\n", coex->bt_traffic_load);
1933         IWL_DEBUG_COEX(priv, "    CI compliance: %d\n",
1934                         coex->bt_ci_compliance);
1935         iwlagn_print_uartmsg(priv, uart_msg);
1936
1937         priv->last_bt_traffic_load = priv->bt_traffic_load;
1938         if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1939                 if (priv->bt_status != coex->bt_status ||
1940                     priv->last_bt_traffic_load != coex->bt_traffic_load) {
1941                         if (coex->bt_status) {
1942                                 /* BT on */
1943                                 if (!priv->bt_ch_announce)
1944                                         priv->bt_traffic_load =
1945                                                 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1946                                 else
1947                                         priv->bt_traffic_load =
1948                                                 coex->bt_traffic_load;
1949                         } else {
1950                                 /* BT off */
1951                                 priv->bt_traffic_load =
1952                                         IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1953                         }
1954                         priv->bt_status = coex->bt_status;
1955                         queue_work(priv->workqueue,
1956                                    &priv->bt_traffic_change_work);
1957                 }
1958         }
1959
1960         iwlagn_set_kill_msk(priv, uart_msg);
1961
1962         /* FIXME: based on notification, adjust the prio_boost */
1963
1964         spin_lock_irqsave(&priv->lock, flags);
1965         priv->bt_ci_compliance = coex->bt_ci_compliance;
1966         spin_unlock_irqrestore(&priv->lock, flags);
1967 }
1968
1969 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1970 {
1971         iwlagn_rx_handler_setup(priv);
1972         priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1973                 iwlagn_bt_coex_profile_notif;
1974 }
1975
1976 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1977 {
1978         iwlagn_setup_deferred_work(priv);
1979
1980         INIT_WORK(&priv->bt_traffic_change_work,
1981                   iwlagn_bt_traffic_change_work);
1982 }
1983
1984 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1985 {
1986         cancel_work_sync(&priv->bt_traffic_change_work);
1987 }
1988
1989 static bool is_single_rx_stream(struct iwl_priv *priv)
1990 {
1991         return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1992                priv->current_ht_config.single_chain_sufficient;
1993 }
1994
1995 #define IWL_NUM_RX_CHAINS_MULTIPLE      3
1996 #define IWL_NUM_RX_CHAINS_SINGLE        2
1997 #define IWL_NUM_IDLE_CHAINS_DUAL        2
1998 #define IWL_NUM_IDLE_CHAINS_SINGLE      1
1999
2000 /*
2001  * Determine how many receiver/antenna chains to use.
2002  *
2003  * More provides better reception via diversity.  Fewer saves power
2004  * at the expense of throughput, but only when not in powersave to
2005  * start with.
2006  *
2007  * MIMO (dual stream) requires at least 2, but works better with 3.
2008  * This does not determine *which* chains to use, just how many.
2009  */
2010 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2011 {
2012         if (priv->cfg->bt_params &&
2013             priv->cfg->bt_params->advanced_bt_coexist &&
2014             (priv->bt_full_concurrent ||
2015              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2016                 /*
2017                  * only use chain 'A' in bt high traffic load or
2018                  * full concurrency mode
2019                  */
2020                 return IWL_NUM_RX_CHAINS_SINGLE;
2021         }
2022         /* # of Rx chains to use when expecting MIMO. */
2023         if (is_single_rx_stream(priv))
2024                 return IWL_NUM_RX_CHAINS_SINGLE;
2025         else
2026                 return IWL_NUM_RX_CHAINS_MULTIPLE;
2027 }
2028
2029 /*
2030  * When we are in power saving mode, unless device support spatial
2031  * multiplexing power save, use the active count for rx chain count.
2032  */
2033 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2034 {
2035         /* # Rx chains when idling, depending on SMPS mode */
2036         switch (priv->current_ht_config.smps) {
2037         case IEEE80211_SMPS_STATIC:
2038         case IEEE80211_SMPS_DYNAMIC:
2039                 return IWL_NUM_IDLE_CHAINS_SINGLE;
2040         case IEEE80211_SMPS_OFF:
2041                 return active_cnt;
2042         default:
2043                 WARN(1, "invalid SMPS mode %d",
2044                      priv->current_ht_config.smps);
2045                 return active_cnt;
2046         }
2047 }
2048
2049 /* up to 4 chains */
2050 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2051 {
2052         u8 res;
2053         res = (chain_bitmap & BIT(0)) >> 0;
2054         res += (chain_bitmap & BIT(1)) >> 1;
2055         res += (chain_bitmap & BIT(2)) >> 2;
2056         res += (chain_bitmap & BIT(3)) >> 3;
2057         return res;
2058 }
2059
2060 /**
2061  * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2062  *
2063  * Selects how many and which Rx receivers/antennas/chains to use.
2064  * This should not be used for scan command ... it puts data in wrong place.
2065  */
2066 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2067 {
2068         bool is_single = is_single_rx_stream(priv);
2069         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2070         u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2071         u32 active_chains;
2072         u16 rx_chain;
2073
2074         /* Tell uCode which antennas are actually connected.
2075          * Before first association, we assume all antennas are connected.
2076          * Just after first association, iwl_chain_noise_calibration()
2077          *    checks which antennas actually *are* connected. */
2078         if (priv->chain_noise_data.active_chains)
2079                 active_chains = priv->chain_noise_data.active_chains;
2080         else
2081                 active_chains = priv->hw_params.valid_rx_ant;
2082
2083         if (priv->cfg->bt_params &&
2084             priv->cfg->bt_params->advanced_bt_coexist &&
2085             (priv->bt_full_concurrent ||
2086              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2087                 /*
2088                  * only use chain 'A' in bt high traffic load or
2089                  * full concurrency mode
2090                  */
2091                 active_chains = first_antenna(active_chains);
2092         }
2093
2094         rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2095
2096         /* How many receivers should we use? */
2097         active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2098         idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2099
2100
2101         /* correct rx chain count according hw settings
2102          * and chain noise calibration
2103          */
2104         valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2105         if (valid_rx_cnt < active_rx_cnt)
2106                 active_rx_cnt = valid_rx_cnt;
2107
2108         if (valid_rx_cnt < idle_rx_cnt)
2109                 idle_rx_cnt = valid_rx_cnt;
2110
2111         rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2112         rx_chain |= idle_rx_cnt  << RXON_RX_CHAIN_CNT_POS;
2113
2114         ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2115
2116         if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2117                 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2118         else
2119                 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2120
2121         IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2122                         ctx->staging.rx_chain,
2123                         active_rx_cnt, idle_rx_cnt);
2124
2125         WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2126                 active_rx_cnt < idle_rx_cnt);
2127 }
2128
2129 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2130 {
2131         int i;
2132         u8 ind = ant;
2133
2134         if (priv->band == IEEE80211_BAND_2GHZ &&
2135             priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2136                 return 0;
2137
2138         for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2139                 ind = (ind + 1) < RATE_ANT_NUM ?  ind + 1 : 0;
2140                 if (valid & BIT(ind))
2141                         return ind;
2142         }
2143         return ant;
2144 }
2145
2146 static const char *get_csr_string(int cmd)
2147 {
2148         switch (cmd) {
2149         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2150         IWL_CMD(CSR_INT_COALESCING);
2151         IWL_CMD(CSR_INT);
2152         IWL_CMD(CSR_INT_MASK);
2153         IWL_CMD(CSR_FH_INT_STATUS);
2154         IWL_CMD(CSR_GPIO_IN);
2155         IWL_CMD(CSR_RESET);
2156         IWL_CMD(CSR_GP_CNTRL);
2157         IWL_CMD(CSR_HW_REV);
2158         IWL_CMD(CSR_EEPROM_REG);
2159         IWL_CMD(CSR_EEPROM_GP);
2160         IWL_CMD(CSR_OTP_GP_REG);
2161         IWL_CMD(CSR_GIO_REG);
2162         IWL_CMD(CSR_GP_UCODE_REG);
2163         IWL_CMD(CSR_GP_DRIVER_REG);
2164         IWL_CMD(CSR_UCODE_DRV_GP1);
2165         IWL_CMD(CSR_UCODE_DRV_GP2);
2166         IWL_CMD(CSR_LED_REG);
2167         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2168         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2169         IWL_CMD(CSR_ANA_PLL_CFG);
2170         IWL_CMD(CSR_HW_REV_WA_REG);
2171         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2172         default:
2173                 return "UNKNOWN";
2174         }
2175 }
2176
2177 void iwl_dump_csr(struct iwl_priv *priv)
2178 {
2179         int i;
2180         static const u32 csr_tbl[] = {
2181                 CSR_HW_IF_CONFIG_REG,
2182                 CSR_INT_COALESCING,
2183                 CSR_INT,
2184                 CSR_INT_MASK,
2185                 CSR_FH_INT_STATUS,
2186                 CSR_GPIO_IN,
2187                 CSR_RESET,
2188                 CSR_GP_CNTRL,
2189                 CSR_HW_REV,
2190                 CSR_EEPROM_REG,
2191                 CSR_EEPROM_GP,
2192                 CSR_OTP_GP_REG,
2193                 CSR_GIO_REG,
2194                 CSR_GP_UCODE_REG,
2195                 CSR_GP_DRIVER_REG,
2196                 CSR_UCODE_DRV_GP1,
2197                 CSR_UCODE_DRV_GP2,
2198                 CSR_LED_REG,
2199                 CSR_DRAM_INT_TBL_REG,
2200                 CSR_GIO_CHICKEN_BITS,
2201                 CSR_ANA_PLL_CFG,
2202                 CSR_HW_REV_WA_REG,
2203                 CSR_DBG_HPET_MEM_REG
2204         };
2205         IWL_ERR(priv, "CSR values:\n");
2206         IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2207                 "CSR_INT_PERIODIC_REG)\n");
2208         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2209                 IWL_ERR(priv, "  %25s: 0X%08x\n",
2210                         get_csr_string(csr_tbl[i]),
2211                         iwl_read32(priv, csr_tbl[i]));
2212         }
2213 }
2214
2215 static const char *get_fh_string(int cmd)
2216 {
2217         switch (cmd) {
2218         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2219         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2220         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2221         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2222         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2223         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2224         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2225         IWL_CMD(FH_TSSR_TX_STATUS_REG);
2226         IWL_CMD(FH_TSSR_TX_ERROR_REG);
2227         default:
2228                 return "UNKNOWN";
2229         }
2230 }
2231
2232 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2233 {
2234         int i;
2235 #ifdef CONFIG_IWLWIFI_DEBUG
2236         int pos = 0;
2237         size_t bufsz = 0;
2238 #endif
2239         static const u32 fh_tbl[] = {
2240                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2241                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2242                 FH_RSCSR_CHNL0_WPTR,
2243                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2244                 FH_MEM_RSSR_SHARED_CTRL_REG,
2245                 FH_MEM_RSSR_RX_STATUS_REG,
2246                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2247                 FH_TSSR_TX_STATUS_REG,
2248                 FH_TSSR_TX_ERROR_REG
2249         };
2250 #ifdef CONFIG_IWLWIFI_DEBUG
2251         if (display) {
2252                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2253                 *buf = kmalloc(bufsz, GFP_KERNEL);
2254                 if (!*buf)
2255                         return -ENOMEM;
2256                 pos += scnprintf(*buf + pos, bufsz - pos,
2257                                 "FH register values:\n");
2258                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2259                         pos += scnprintf(*buf + pos, bufsz - pos,
2260                                 "  %34s: 0X%08x\n",
2261                                 get_fh_string(fh_tbl[i]),
2262                                 iwl_read_direct32(priv, fh_tbl[i]));
2263                 }
2264                 return pos;
2265         }
2266 #endif
2267         IWL_ERR(priv, "FH register values:\n");
2268         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
2269                 IWL_ERR(priv, "  %34s: 0X%08x\n",
2270                         get_fh_string(fh_tbl[i]),
2271                         iwl_read_direct32(priv, fh_tbl[i]));
2272         }
2273         return 0;
2274 }
2275
2276 /* notification wait support */
2277 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2278                                    struct iwl_notification_wait *wait_entry,
2279                                    u8 cmd,
2280                                    void (*fn)(struct iwl_priv *priv,
2281                                               struct iwl_rx_packet *pkt,
2282                                               void *data),
2283                                    void *fn_data)
2284 {
2285         wait_entry->fn = fn;
2286         wait_entry->fn_data = fn_data;
2287         wait_entry->cmd = cmd;
2288         wait_entry->triggered = false;
2289         wait_entry->aborted = false;
2290
2291         spin_lock_bh(&priv->_agn.notif_wait_lock);
2292         list_add(&wait_entry->list, &priv->_agn.notif_waits);
2293         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2294 }
2295
2296 int iwlagn_wait_notification(struct iwl_priv *priv,
2297                              struct iwl_notification_wait *wait_entry,
2298                              unsigned long timeout)
2299 {
2300         int ret;
2301
2302         ret = wait_event_timeout(priv->_agn.notif_waitq,
2303                                  wait_entry->triggered || wait_entry->aborted,
2304                                  timeout);
2305
2306         spin_lock_bh(&priv->_agn.notif_wait_lock);
2307         list_del(&wait_entry->list);
2308         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2309
2310         if (wait_entry->aborted)
2311                 return -EIO;
2312
2313         /* return value is always >= 0 */
2314         if (ret <= 0)
2315                 return -ETIMEDOUT;
2316         return 0;
2317 }
2318
2319 void iwlagn_remove_notification(struct iwl_priv *priv,
2320                                 struct iwl_notification_wait *wait_entry)
2321 {
2322         spin_lock_bh(&priv->_agn.notif_wait_lock);
2323         list_del(&wait_entry->list);
2324         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2325 }
2326
2327 int iwlagn_start_device(struct iwl_priv *priv)
2328 {
2329         int ret;
2330
2331         if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
2332              iwl_prepare_card_hw(priv)) {
2333                 IWL_WARN(priv, "Exit HW not ready\n");
2334                 return -EIO;
2335         }
2336
2337         /* If platform's RF_KILL switch is NOT set to KILL */
2338         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2339                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2340         else
2341                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2342
2343         if (iwl_is_rfkill(priv)) {
2344                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2345                 iwl_enable_interrupts(priv);
2346                 return -ERFKILL;
2347         }
2348
2349         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2350
2351         ret = iwlagn_hw_nic_init(priv);
2352         if (ret) {
2353                 IWL_ERR(priv, "Unable to init nic\n");
2354                 return ret;
2355         }
2356
2357         /* make sure rfkill handshake bits are cleared */
2358         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2359         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2360                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2361
2362         /* clear (again), then enable host interrupts */
2363         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2364         iwl_enable_interrupts(priv);
2365
2366         /* really make sure rfkill handshake bits are cleared */
2367         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2368         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2369
2370         return 0;
2371 }
2372
2373 void iwlagn_stop_device(struct iwl_priv *priv)
2374 {
2375         unsigned long flags;
2376
2377         /* stop and reset the on-board processor */
2378         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2379
2380         /* tell the device to stop sending interrupts */
2381         spin_lock_irqsave(&priv->lock, flags);
2382         iwl_disable_interrupts(priv);
2383         spin_unlock_irqrestore(&priv->lock, flags);
2384         iwl_synchronize_irq(priv);
2385
2386         /* device going down, Stop using ICT table */
2387         iwl_disable_ict(priv);
2388
2389         /*
2390          * If a HW restart happens during firmware loading,
2391          * then the firmware loading might call this function
2392          * and later it might be called again due to the
2393          * restart. So don't process again if the device is
2394          * already dead.
2395          */
2396         if (test_bit(STATUS_DEVICE_ENABLED, &priv->status)) {
2397                 iwlagn_txq_ctx_stop(priv);
2398                 iwlagn_rxq_stop(priv);
2399
2400                 /* Power-down device's busmaster DMA clocks */
2401                 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2402                 udelay(5);
2403         }
2404
2405         /* Make sure (redundant) we've released our request to stay awake */
2406         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2407
2408         /* Stop the device, and put it in low power state */
2409         iwl_apm_stop(priv);
2410 }