drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/wireless.h>
  35 #include <net/mac80211.h>
  36 #include <linux/etherdevice.h>
  37 #include <asm/unaligned.h>
  38
  39 #include "iwl-eeprom.h"
  40 #include "iwl-dev.h"
  41 #include "iwl-core.h"
  42 #include "iwl-io.h"
  43 #include "iwl-sta.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46
  47 #define IWL5000_UCODE_API  "-1"
  48
  49 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  50         IWL_TX_FIFO_AC3,
  51         IWL_TX_FIFO_AC2,
  52         IWL_TX_FIFO_AC1,
  53         IWL_TX_FIFO_AC0,
  54         IWL50_CMD_FIFO_NUM,
  55         IWL_TX_FIFO_HCCA_1,
  56         IWL_TX_FIFO_HCCA_2
  57 };
  58
  59 /* FIXME: same implementation as 4965 */
  60 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  61 {
  62         int ret = 0;
  63         unsigned long flags;
  64
  65         spin_lock_irqsave(&priv->lock, flags);
  66
  67         /* set stop master bit */
  68         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  69
  70         ret = iwl_poll_bit(priv, CSR_RESET,
  71                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
  72                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  73         if (ret < 0)
  74                 goto out;
  75
  76 out:
  77         spin_unlock_irqrestore(&priv->lock, flags);
  78         IWL_DEBUG_INFO("stop master\n");
  79
  80         return ret;
  81 }
  82
  83
  84 static int iwl5000_apm_init(struct iwl_priv *priv)
  85 {
  86         int ret = 0;
  87
  88         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  89                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  90
  91         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
  92         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  93                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  94
  95         /* Set FH wait treshold to maximum (HW error during stress W/A) */
  96         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  97
  98         /* enable HAP INTA to move device L1a -> L0s */
  99         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 100                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 101
 102         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 103
 104         /* set "initialization complete" bit to move adapter
 105          * D0U* --> D0A* state */
 106         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 107
 108         /* wait for clock stabilization */
 109         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 110                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 111                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 112         if (ret < 0) {
 113                 IWL_DEBUG_INFO("Failed to init the card\n");
 114                 return ret;
 115         }
 116
 117         ret = iwl_grab_nic_access(priv);
 118         if (ret)
 119                 return ret;
 120
 121         /* enable DMA */
 122         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 123
 124         udelay(20);
 125
 126         /* disable L1-Active */
 127         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 128                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 129
 130         iwl_release_nic_access(priv);
 131
 132         return ret;
 133 }
 134
 135 /* FIXME: this is indentical to 4965 */
 136 static void iwl5000_apm_stop(struct iwl_priv *priv)
 137 {
 138         unsigned long flags;
 139
 140         iwl5000_apm_stop_master(priv);
 141
 142         spin_lock_irqsave(&priv->lock, flags);
 143
 144         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 145
 146         udelay(10);
 147
 148         /* clear "init complete"  move adapter D0A* --> D0U state */
 149         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 150
 151         spin_unlock_irqrestore(&priv->lock, flags);
 152 }
 153
 154
 155 static int iwl5000_apm_reset(struct iwl_priv *priv)
 156 {
 157         int ret = 0;
 158         unsigned long flags;
 159
 160         iwl5000_apm_stop_master(priv);
 161
 162         spin_lock_irqsave(&priv->lock, flags);
 163
 164         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 165
 166         udelay(10);
 167
 168
 169         /* FIXME: put here L1A -L0S w/a */
 170
 171         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 172
 173         /* set "initialization complete" bit to move adapter
 174          * D0U* --> D0A* state */
 175         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 176
 177         /* wait for clock stabilization */
 178         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 179                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 180                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 181         if (ret < 0) {
 182                 IWL_DEBUG_INFO("Failed to init the card\n");
 183                 goto out;
 184         }
 185
 186         ret = iwl_grab_nic_access(priv);
 187         if (ret)
 188                 goto out;
 189
 190         /* enable DMA */
 191         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 192
 193         udelay(20);
 194
 195         /* disable L1-Active */
 196         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 197                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 198
 199         iwl_release_nic_access(priv);
 200
 201 out:
 202         spin_unlock_irqrestore(&priv->lock, flags);
 203
 204         return ret;
 205 }
 206
 207
 208 static void iwl5000_nic_config(struct iwl_priv *priv)
 209 {
 210         unsigned long flags;
 211         u16 radio_cfg;
 212         u16 link;
 213
 214         spin_lock_irqsave(&priv->lock, flags);
 215
 216         pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
 217
 218         /* L1 is enabled by BIOS */
 219         if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
 220                 /* diable L0S disabled L1A enabled */
 221                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 222         else
 223                 /* L0S enabled L1A disabled */
 224                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 225
 226         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 227
 228         /* write radio config values to register */
 229         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 230                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 231                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 232                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 233                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 234
 235         /* set CSR_HW_CONFIG_REG for uCode use */
 236         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 237                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 238                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 239
 240         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 241          * (PCIe power is lost before PERST# is asserted),
 242          * causing ME FW to lose ownership and not being able to obtain it back.
 243          */
 244         iwl_grab_nic_access(priv);
 245         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 246                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 247                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 248         iwl_release_nic_access(priv);
 249
 250         spin_unlock_irqrestore(&priv->lock, flags);
 251 }
 252
 253
 254
 255 /*
 256  * EEPROM
 257  */
 258 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 259 {
 260         u16 offset = 0;
 261
 262         if ((address & INDIRECT_ADDRESS) == 0)
 263                 return address;
 264
 265         switch (address & INDIRECT_TYPE_MSK) {
 266         case INDIRECT_HOST:
 267                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 268                 break;
 269         case INDIRECT_GENERAL:
 270                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 271                 break;
 272         case INDIRECT_REGULATORY:
 273                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 274                 break;
 275         case INDIRECT_CALIBRATION:
 276                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 277                 break;
 278         case INDIRECT_PROCESS_ADJST:
 279                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 280                 break;
 281         case INDIRECT_OTHERS:
 282                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 283                 break;
 284         default:
 285                 IWL_ERROR("illegal indirect type: 0x%X\n",
 286                 address & INDIRECT_TYPE_MSK);
 287                 break;
 288         }
 289
 290         /* translate the offset from words to byte */
 291         return (address & ADDRESS_MSK) + (offset << 1);
 292 }
 293
 294 static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
 295 {
 296         u16 eeprom_ver;
 297         struct iwl_eeprom_calib_hdr {
 298                 u8 version;
 299                 u8 pa_type;
 300                 u16 voltage;
 301         } *hdr;
 302
 303         eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
 304
 305         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 306                                                         EEPROM_5000_CALIB_ALL);
 307
 308         if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
 309             hdr->version < EEPROM_5000_TX_POWER_VERSION)
 310                 goto err;
 311
 312         return 0;
 313 err:
 314         IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
 315                   eeprom_ver, EEPROM_5000_EEPROM_VERSION,
 316                   hdr->version, EEPROM_5000_TX_POWER_VERSION);
 317         return -EINVAL;
 318
 319 }
 320
 321 static void iwl5000_gain_computation(struct iwl_priv *priv,
 322                 u32 average_noise[NUM_RX_CHAINS],
 323                 u16 min_average_noise_antenna_i,
 324                 u32 min_average_noise)
 325 {
 326         int i;
 327         s32 delta_g;
 328         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 329
 330         /* Find Gain Code for the antennas B and C */
 331         for (i = 1; i < NUM_RX_CHAINS; i++) {
 332                 if ((data->disconn_array[i])) {
 333                         data->delta_gain_code[i] = 0;
 334                         continue;
 335                 }
 336                 delta_g = (1000 * ((s32)average_noise[0] -
 337                         (s32)average_noise[i])) / 1500;
 338                 /* bound gain by 2 bits value max, 3rd bit is sign */
 339                 data->delta_gain_code[i] =
 340                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 341
 342                 if (delta_g < 0)
 343                         /* set negative sign */
 344                         data->delta_gain_code[i] |= (1 << 2);
 345         }
 346
 347         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
 348                         data->delta_gain_code[1], data->delta_gain_code[2]);
 349
 350         if (!data->radio_write) {
 351                 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
 352                 memset(&cmd, 0, sizeof(cmd));
 353
 354                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 355                 cmd.delta_gain_1 = data->delta_gain_code[1];
 356                 cmd.delta_gain_2 = data->delta_gain_code[2];
 357                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 358                         sizeof(cmd), &cmd, NULL);
 359
 360                 data->radio_write = 1;
 361                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 362         }
 363
 364         data->chain_noise_a = 0;
 365         data->chain_noise_b = 0;
 366         data->chain_noise_c = 0;
 367         data->chain_signal_a = 0;
 368         data->chain_signal_b = 0;
 369         data->chain_signal_c = 0;
 370         data->beacon_count = 0;
 371 }
 372
 373 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 374 {
 375         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 376
 377         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 378                 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
 379
 380                 memset(&cmd, 0, sizeof(cmd));
 381                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 382                 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 383                         sizeof(cmd), &cmd))
 384                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
 385                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 386                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 387         }
 388 }
 389
 390 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 391                         __le32 *tx_flags)
 392 {
 393         if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) ||
 394             (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT))
 395                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 396         else
 397                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 398 }
 399
 400 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 401         .min_nrg_cck = 95,
 402         .max_nrg_cck = 0,
 403         .auto_corr_min_ofdm = 90,
 404         .auto_corr_min_ofdm_mrc = 170,
 405         .auto_corr_min_ofdm_x1 = 120,
 406         .auto_corr_min_ofdm_mrc_x1 = 240,
 407
 408         .auto_corr_max_ofdm = 120,
 409         .auto_corr_max_ofdm_mrc = 210,
 410         .auto_corr_max_ofdm_x1 = 155,
 411         .auto_corr_max_ofdm_mrc_x1 = 290,
 412
 413         .auto_corr_min_cck = 125,
 414         .auto_corr_max_cck = 200,
 415         .auto_corr_min_cck_mrc = 170,
 416         .auto_corr_max_cck_mrc = 400,
 417         .nrg_th_cck = 95,
 418         .nrg_th_ofdm = 95,
 419 };
 420
 421 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 422                                            size_t offset)
 423 {
 424         u32 address = eeprom_indirect_address(priv, offset);
 425         BUG_ON(address >= priv->cfg->eeprom_size);
 426         return &priv->eeprom[address];
 427 }
 428
 429 /*
 430  *  Calibration
 431  */
 432 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 433 {
 434         u8 data[sizeof(struct iwl5000_calib_hdr) +
 435                 sizeof(struct iwl_cal_xtal_freq)];
 436         struct iwl5000_calib_cmd *cmd = (struct iwl5000_calib_cmd *)data;
 437         struct iwl_cal_xtal_freq *xtal = (struct iwl_cal_xtal_freq *)cmd->data;
 438         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 439
 440         cmd->hdr.op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 441         xtal->cap_pin1 = (u8)xtal_calib[0];
 442         xtal->cap_pin2 = (u8)xtal_calib[1];
 443         return iwl_calib_set(&priv->calib_results[IWL5000_CALIB_XTAL],
 444                              data, sizeof(data));
 445 }
 446
 447 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 448 {
 449         struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
 450         struct iwl_host_cmd cmd = {
 451                 .id = CALIBRATION_CFG_CMD,
 452                 .len = sizeof(struct iwl5000_calib_cfg_cmd),
 453                 .data = &calib_cfg_cmd,
 454         };
 455
 456         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 457         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 458         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 459         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 460         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 461
 462         return iwl_send_cmd(priv, &cmd);
 463 }
 464
 465 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 466                              struct iwl_rx_mem_buffer *rxb)
 467 {
 468         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 469         struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
 470         int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
 471         int index;
 472
 473         /* reduce the size of the length field itself */
 474         len -= 4;
 475
 476         /* Define the order in which the results will be sent to the runtime
 477          * uCode. iwl_send_calib_results sends them in a row according to their
 478          * index. We sort them here */
 479         switch (hdr->op_code) {
 480         case IWL5000_PHY_CALIBRATE_LO_CMD:
 481                 index = IWL5000_CALIB_LO;
 482                 break;
 483         case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
 484                 index = IWL5000_CALIB_TX_IQ;
 485                 break;
 486         case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 487                 index = IWL5000_CALIB_TX_IQ_PERD;
 488                 break;
 489         default:
 490                 IWL_ERROR("Unknown calibration notification %d\n",
 491                           hdr->op_code);
 492                 return;
 493         }
 494         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 495 }
 496
 497 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 498                                struct iwl_rx_mem_buffer *rxb)
 499 {
 500         IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
 501         queue_work(priv->workqueue, &priv->restart);
 502 }
 503
 504 /*
 505  * ucode
 506  */
 507 static int iwl5000_load_section(struct iwl_priv *priv,
 508                                 struct fw_desc *image,
 509                                 u32 dst_addr)
 510 {
 511         int ret = 0;
 512         unsigned long flags;
 513
 514         dma_addr_t phy_addr = image->p_addr;
 515         u32 byte_cnt = image->len;
 516
 517         spin_lock_irqsave(&priv->lock, flags);
 518         ret = iwl_grab_nic_access(priv);
 519         if (ret) {
 520                 spin_unlock_irqrestore(&priv->lock, flags);
 521                 return ret;
 522         }
 523
 524         iwl_write_direct32(priv,
 525                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 526                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 527
 528         iwl_write_direct32(priv,
 529                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 530
 531         iwl_write_direct32(priv,
 532                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 533                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 534
 535         iwl_write_direct32(priv,
 536                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 537                 (iwl_get_dma_hi_address(phy_addr)
 538                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 539
 540         iwl_write_direct32(priv,
 541                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 542                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 543                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 544                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 545
 546         iwl_write_direct32(priv,
 547                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 548                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 549                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
 550                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 551
 552         iwl_release_nic_access(priv);
 553         spin_unlock_irqrestore(&priv->lock, flags);
 554         return 0;
 555 }
 556
 557 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 558                 struct fw_desc *inst_image,
 559                 struct fw_desc *data_image)
 560 {
 561         int ret = 0;
 562
 563         ret = iwl5000_load_section(
 564                 priv, inst_image, RTC_INST_LOWER_BOUND);
 565         if (ret)
 566                 return ret;
 567
 568         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
 569         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 570                                 priv->ucode_write_complete, 5 * HZ);
 571         if (ret == -ERESTARTSYS) {
 572                 IWL_ERROR("Could not load the INST uCode section due "
 573                         "to interrupt\n");
 574                 return ret;
 575         }
 576         if (!ret) {
 577                 IWL_ERROR("Could not load the INST uCode section\n");
 578                 return -ETIMEDOUT;
 579         }
 580
 581         priv->ucode_write_complete = 0;
 582
 583         ret = iwl5000_load_section(
 584                 priv, data_image, RTC_DATA_LOWER_BOUND);
 585         if (ret)
 586                 return ret;
 587
 588         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
 589
 590         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 591                                 priv->ucode_write_complete, 5 * HZ);
 592         if (ret == -ERESTARTSYS) {
 593                 IWL_ERROR("Could not load the INST uCode section due "
 594                         "to interrupt\n");
 595                 return ret;
 596         } else if (!ret) {
 597                 IWL_ERROR("Could not load the DATA uCode section\n");
 598                 return -ETIMEDOUT;
 599         } else
 600                 ret = 0;
 601
 602         priv->ucode_write_complete = 0;
 603
 604         return ret;
 605 }
 606
 607 static int iwl5000_load_ucode(struct iwl_priv *priv)
 608 {
 609         int ret = 0;
 610
 611         /* check whether init ucode should be loaded, or rather runtime ucode */
 612         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 613                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
 614                 ret = iwl5000_load_given_ucode(priv,
 615                         &priv->ucode_init, &priv->ucode_init_data);
 616                 if (!ret) {
 617                         IWL_DEBUG_INFO("Init ucode load complete.\n");
 618                         priv->ucode_type = UCODE_INIT;
 619                 }
 620         } else {
 621                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
 622                         "Loading runtime ucode...\n");
 623                 ret = iwl5000_load_given_ucode(priv,
 624                         &priv->ucode_code, &priv->ucode_data);
 625                 if (!ret) {
 626                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
 627                         priv->ucode_type = UCODE_RT;
 628                 }
 629         }
 630
 631         return ret;
 632 }
 633
 634 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 635 {
 636         int ret = 0;
 637
 638         /* Check alive response for "valid" sign from uCode */
 639         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 640                 /* We had an error bringing up the hardware, so take it
 641                  * all the way back down so we can try again */
 642                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
 643                 goto restart;
 644         }
 645
 646         /* initialize uCode was loaded... verify inst image.
 647          * This is a paranoid check, because we would not have gotten the
 648          * "initialize" alive if code weren't properly loaded.  */
 649         if (iwl_verify_ucode(priv)) {
 650                 /* Runtime instruction load was bad;
 651                  * take it all the way back down so we can try again */
 652                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
 653                 goto restart;
 654         }
 655
 656         iwl_clear_stations_table(priv);
 657         ret = priv->cfg->ops->lib->alive_notify(priv);
 658         if (ret) {
 659                 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
 660                 goto restart;
 661         }
 662
 663         iwl5000_send_calib_cfg(priv);
 664         return;
 665
 666 restart:
 667         /* real restart (first load init_ucode) */
 668         queue_work(priv->workqueue, &priv->restart);
 669 }
 670
 671 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 672                                 int txq_id, u32 index)
 673 {
 674         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 675                         (index & 0xff) | (txq_id << 8));
 676         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 677 }
 678
 679 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 680                                         struct iwl_tx_queue *txq,
 681                                         int tx_fifo_id, int scd_retry)
 682 {
 683         int txq_id = txq->q.id;
 684         int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
 685
 686         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 687                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 688                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 689                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 690                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 691
 692         txq->sched_retry = scd_retry;
 693
 694         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
 695                        active ? "Activate" : "Deactivate",
 696                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 697 }
 698
 699 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 700 {
 701         struct iwl_wimax_coex_cmd coex_cmd;
 702
 703         memset(&coex_cmd, 0, sizeof(coex_cmd));
 704
 705         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 706                                 sizeof(coex_cmd), &coex_cmd);
 707 }
 708
 709 static int iwl5000_alive_notify(struct iwl_priv *priv)
 710 {
 711         u32 a;
 712         int i = 0;
 713         unsigned long flags;
 714         int ret;
 715
 716         spin_lock_irqsave(&priv->lock, flags);
 717
 718         ret = iwl_grab_nic_access(priv);
 719         if (ret) {
 720                 spin_unlock_irqrestore(&priv->lock, flags);
 721                 return ret;
 722         }
 723
 724         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 725         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 726         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 727                 a += 4)
 728                 iwl_write_targ_mem(priv, a, 0);
 729         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 730                 a += 4)
 731                 iwl_write_targ_mem(priv, a, 0);
 732         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 733                 iwl_write_targ_mem(priv, a, 0);
 734
 735         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 736                 (priv->shared_phys +
 737                  offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
 738         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 739                 IWL50_SCD_QUEUECHAIN_SEL_ALL(
 740                         priv->hw_params.max_txq_num));
 741         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 742
 743         /* initiate the queues */
 744         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 745                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 746                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 747                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 748                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 749                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 750                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 751                                 sizeof(u32),
 752                                 ((SCD_WIN_SIZE <<
 753                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 754                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 755                                 ((SCD_FRAME_LIMIT <<
 756                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 757                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 758         }
 759
 760         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 761                         IWL_MASK(0, priv->hw_params.max_txq_num));
 762
 763         /* Activate all Tx DMA/FIFO channels */
 764         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 765
 766         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 767         /* map qos queues to fifos one-to-one */
 768         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 769                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 770                 iwl_txq_ctx_activate(priv, i);
 771                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 772         }
 773         /* TODO - need to initialize those FIFOs inside the loop above,
 774          * not only mark them as active */
 775         iwl_txq_ctx_activate(priv, 4);
 776         iwl_txq_ctx_activate(priv, 7);
 777         iwl_txq_ctx_activate(priv, 8);
 778         iwl_txq_ctx_activate(priv, 9);
 779
 780         iwl_release_nic_access(priv);
 781         spin_unlock_irqrestore(&priv->lock, flags);
 782
 783
 784         iwl5000_send_wimax_coex(priv);
 785
 786         iwl5000_set_Xtal_calib(priv);
 787         iwl_send_calib_results(priv);
 788
 789         return 0;
 790 }
 791
 792 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 793 {
 794         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 795             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 796                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
 797                           IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 798                 return -EINVAL;
 799         }
 800
 801         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 802         priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE;
 803         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 804         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 805         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 806         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 807         priv->hw_params.max_bsm_size = 0;
 808         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 809                                         BIT(IEEE80211_BAND_5GHZ);
 810         priv->hw_params.sens = &iwl5000_sensitivity;
 811
 812         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 813         case CSR_HW_REV_TYPE_5100:
 814         case CSR_HW_REV_TYPE_5150:
 815                 priv->hw_params.tx_chains_num = 1;
 816                 priv->hw_params.rx_chains_num = 2;
 817                 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
 818                 priv->hw_params.valid_tx_ant = ANT_A;
 819                 priv->hw_params.valid_rx_ant = ANT_AB;
 820                 break;
 821         case CSR_HW_REV_TYPE_5300:
 822         case CSR_HW_REV_TYPE_5350:
 823                 priv->hw_params.tx_chains_num = 3;
 824                 priv->hw_params.rx_chains_num = 3;
 825                 priv->hw_params.valid_tx_ant = ANT_ABC;
 826                 priv->hw_params.valid_rx_ant = ANT_ABC;
 827                 break;
 828         }
 829
 830         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 831         case CSR_HW_REV_TYPE_5100:
 832         case CSR_HW_REV_TYPE_5300:
 833         case CSR_HW_REV_TYPE_5350:
 834                 /* 5X00 and 5350 wants in Celsius */
 835                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 836                 break;
 837         case CSR_HW_REV_TYPE_5150:
 838                 /* 5150 wants in Kelvin */
 839                 priv->hw_params.ct_kill_threshold =
 840                                 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
 841                 break;
 842         }
 843
 844         /* Set initial calibration set */
 845         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 846         case CSR_HW_REV_TYPE_5100:
 847         case CSR_HW_REV_TYPE_5300:
 848         case CSR_HW_REV_TYPE_5350:
 849                 priv->hw_params.calib_init_cfg =
 850                         BIT(IWL5000_CALIB_XTAL)         |
 851                         BIT(IWL5000_CALIB_LO)           |
 852                         BIT(IWL5000_CALIB_TX_IQ)        |
 853                         BIT(IWL5000_CALIB_TX_IQ_PERD);
 854                 break;
 855         case CSR_HW_REV_TYPE_5150:
 856                 priv->hw_params.calib_init_cfg = 0;
 857                 break;
 858         }
 859
 860
 861         return 0;
 862 }
 863
 864 static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
 865 {
 866         priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
 867                                         sizeof(struct iwl5000_shared),
 868                                         &priv->shared_phys);
 869         if (!priv->shared_virt)
 870                 return -ENOMEM;
 871
 872         memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
 873
 874         priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
 875
 876         return 0;
 877 }
 878
 879 static void iwl5000_free_shared_mem(struct iwl_priv *priv)
 880 {
 881         if (priv->shared_virt)
 882                 pci_free_consistent(priv->pci_dev,
 883                                     sizeof(struct iwl5000_shared),
 884                                     priv->shared_virt,
 885                                     priv->shared_phys);
 886 }
 887
 888 static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
 889 {
 890         struct iwl5000_shared *s = priv->shared_virt;
 891         return le32_to_cpu(s->rb_closed) & 0xFFF;
 892 }
 893
 894 /**
 895  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 896  */
 897 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 898                                             struct iwl_tx_queue *txq,
 899                                             u16 byte_cnt)
 900 {
 901         struct iwl5000_shared *shared_data = priv->shared_virt;
 902         int txq_id = txq->q.id;
 903         u8 sec_ctl = 0;
 904         u8 sta = 0;
 905         int len;
 906
 907         len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 908
 909         if (txq_id != IWL_CMD_QUEUE_NUM) {
 910                 sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 911                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 912
 913                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 914                 case TX_CMD_SEC_CCM:
 915                         len += CCMP_MIC_LEN;
 916                         break;
 917                 case TX_CMD_SEC_TKIP:
 918                         len += TKIP_ICV_LEN;
 919                         break;
 920                 case TX_CMD_SEC_WEP:
 921                         len += WEP_IV_LEN + WEP_ICV_LEN;
 922                         break;
 923                 }
 924         }
 925
 926         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 927                        tfd_offset[txq->q.write_ptr], byte_cnt, len);
 928
 929         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 930                        tfd_offset[txq->q.write_ptr], sta_id, sta);
 931
 932         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
 933                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 934                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 935                         byte_cnt, len);
 936                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 937                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 938                         sta_id, sta);
 939         }
 940 }
 941
 942 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 943                                            struct iwl_tx_queue *txq)
 944 {
 945         int txq_id = txq->q.id;
 946         struct iwl5000_shared *shared_data = priv->shared_virt;
 947         u8 sta = 0;
 948
 949         if (txq_id != IWL_CMD_QUEUE_NUM)
 950                 sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id;
 951
 952         shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
 953                                         val = cpu_to_le16(1 | (sta << 12));
 954
 955         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
 956                 shared_data->queues_byte_cnt_tbls[txq_id].
 957                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
 958                                 val = cpu_to_le16(1 | (sta << 12));
 959         }
 960 }
 961
 962 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 963                                         u16 txq_id)
 964 {
 965         u32 tbl_dw_addr;
 966         u32 tbl_dw;
 967         u16 scd_q2ratid;
 968
 969         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 970
 971         tbl_dw_addr = priv->scd_base_addr +
 972                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 973
 974         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 975
 976         if (txq_id & 0x1)
 977                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 978         else
 979                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 980
 981         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 982
 983         return 0;
 984 }
 985 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 986 {
 987         /* Simply stop the queue, but don't change any configuration;
 988          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 989         iwl_write_prph(priv,
 990                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 991                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 992                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 993 }
 994
 995 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
 996                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
 997 {
 998         unsigned long flags;
 999         int ret;
1000         u16 ra_tid;
1001
1002         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1003             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1004                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1005                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1006                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1007                 return -EINVAL;
1008         }
1009
1010         ra_tid = BUILD_RAxTID(sta_id, tid);
1011
1012         /* Modify device's station table to Tx this TID */
1013         iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1014
1015         spin_lock_irqsave(&priv->lock, flags);
1016         ret = iwl_grab_nic_access(priv);
1017         if (ret) {
1018                 spin_unlock_irqrestore(&priv->lock, flags);
1019                 return ret;
1020         }
1021
1022         /* Stop this Tx queue before configuring it */
1023         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1024
1025         /* Map receiver-address / traffic-ID to this queue */
1026         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1027
1028         /* Set this queue as a chain-building queue */
1029         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1030
1031         /* enable aggregations for the queue */
1032         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1033
1034         /* Place first TFD at index corresponding to start sequence number.
1035          * Assumes that ssn_idx is valid (!= 0xFFF) */
1036         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1037         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1038         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1039
1040         /* Set up Tx window size and frame limit for this queue */
1041         iwl_write_targ_mem(priv, priv->scd_base_addr +
1042                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1043                         sizeof(u32),
1044                         ((SCD_WIN_SIZE <<
1045                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1046                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1047                         ((SCD_FRAME_LIMIT <<
1048                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1049                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1050
1051         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1052
1053         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1054         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1055
1056         iwl_release_nic_access(priv);
1057         spin_unlock_irqrestore(&priv->lock, flags);
1058
1059         return 0;
1060 }
1061
1062 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1063                                    u16 ssn_idx, u8 tx_fifo)
1064 {
1065         int ret;
1066
1067         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1068             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1069                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1070                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1071                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1072                 return -EINVAL;
1073         }
1074
1075         ret = iwl_grab_nic_access(priv);
1076         if (ret)
1077                 return ret;
1078
1079         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1080
1081         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1082
1083         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1084         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1085         /* supposes that ssn_idx is valid (!= 0xFFF) */
1086         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1087
1088         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1089         iwl_txq_ctx_deactivate(priv, txq_id);
1090         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1091
1092         iwl_release_nic_access(priv);
1093
1094         return 0;
1095 }
1096
1097 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1098 {
1099         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1100         memcpy(data, cmd, size);
1101         return size;
1102 }
1103
1104
1105 /*
1106  * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
1107  * must be called under priv->lock and mac access
1108  */
1109 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1110 {
1111         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1112 }
1113
1114
1115 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1116 {
1117         return le32_to_cpup((__le32 *)&tx_resp->status +
1118                             tx_resp->frame_count) & MAX_SN;
1119 }
1120
1121 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1122                                       struct iwl_ht_agg *agg,
1123                                       struct iwl5000_tx_resp *tx_resp,
1124                                       int txq_id, u16 start_idx)
1125 {
1126         u16 status;
1127         struct agg_tx_status *frame_status = &tx_resp->status;
1128         struct ieee80211_tx_info *info = NULL;
1129         struct ieee80211_hdr *hdr = NULL;
1130         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1131         int i, sh, idx;
1132         u16 seq;
1133
1134         if (agg->wait_for_ba)
1135                 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1136
1137         agg->frame_count = tx_resp->frame_count;
1138         agg->start_idx = start_idx;
1139         agg->rate_n_flags = rate_n_flags;
1140         agg->bitmap = 0;
1141
1142         /* # frames attempted by Tx command */
1143         if (agg->frame_count == 1) {
1144                 /* Only one frame was attempted; no block-ack will arrive */
1145                 status = le16_to_cpu(frame_status[0].status);
1146                 idx = start_idx;
1147
1148                 /* FIXME: code repetition */
1149                 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1150                                    agg->frame_count, agg->start_idx, idx);
1151
1152                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1153                 info->status.retry_count = tx_resp->failure_frame;
1154                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1155                 info->flags |= iwl_is_tx_success(status)?
1156                         IEEE80211_TX_STAT_ACK : 0;
1157                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1158
1159                 /* FIXME: code repetition end */
1160
1161                 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1162                                     status & 0xff, tx_resp->failure_frame);
1163                 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1164
1165                 agg->wait_for_ba = 0;
1166         } else {
1167                 /* Two or more frames were attempted; expect block-ack */
1168                 u64 bitmap = 0;
1169                 int start = agg->start_idx;
1170
1171                 /* Construct bit-map of pending frames within Tx window */
1172                 for (i = 0; i < agg->frame_count; i++) {
1173                         u16 sc;
1174                         status = le16_to_cpu(frame_status[i].status);
1175                         seq  = le16_to_cpu(frame_status[i].sequence);
1176                         idx = SEQ_TO_INDEX(seq);
1177                         txq_id = SEQ_TO_QUEUE(seq);
1178
1179                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1180                                       AGG_TX_STATE_ABORT_MSK))
1181                                 continue;
1182
1183                         IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1184                                            agg->frame_count, txq_id, idx);
1185
1186                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1187
1188                         sc = le16_to_cpu(hdr->seq_ctrl);
1189                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1190                                 IWL_ERROR("BUG_ON idx doesn't match seq control"
1191                                           " idx=%d, seq_idx=%d, seq=%d\n",
1192                                           idx, SEQ_TO_SN(sc),
1193                                           hdr->seq_ctrl);
1194                                 return -1;
1195                         }
1196
1197                         IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1198                                            i, idx, SEQ_TO_SN(sc));
1199
1200                         sh = idx - start;
1201                         if (sh > 64) {
1202                                 sh = (start - idx) + 0xff;
1203                                 bitmap = bitmap << sh;
1204                                 sh = 0;
1205                                 start = idx;
1206                         } else if (sh < -64)
1207                                 sh  = 0xff - (start - idx);
1208                         else if (sh < 0) {
1209                                 sh = start - idx;
1210                                 start = idx;
1211                                 bitmap = bitmap << sh;
1212                                 sh = 0;
1213                         }
1214                         bitmap |= 1ULL << sh;
1215                         IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1216                                            start, (unsigned long long)bitmap);
1217                 }
1218
1219                 agg->bitmap = bitmap;
1220                 agg->start_idx = start;
1221                 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1222                                    agg->frame_count, agg->start_idx,
1223                                    (unsigned long long)agg->bitmap);
1224
1225                 if (bitmap)
1226                         agg->wait_for_ba = 1;
1227         }
1228         return 0;
1229 }
1230
1231 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1232                                 struct iwl_rx_mem_buffer *rxb)
1233 {
1234         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1235         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1236         int txq_id = SEQ_TO_QUEUE(sequence);
1237         int index = SEQ_TO_INDEX(sequence);
1238         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1239         struct ieee80211_tx_info *info;
1240         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1241         u32  status = le16_to_cpu(tx_resp->status.status);
1242         int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
1243         struct ieee80211_hdr *hdr;
1244         u8 *qc = NULL;
1245
1246         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1247                 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1248                           "is out of range [0-%d] %d %d\n", txq_id,
1249                           index, txq->q.n_bd, txq->q.write_ptr,
1250                           txq->q.read_ptr);
1251                 return;
1252         }
1253
1254         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1255         memset(&info->status, 0, sizeof(info->status));
1256
1257         hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
1258         if (ieee80211_is_data_qos(hdr->frame_control)) {
1259                 qc = ieee80211_get_qos_ctl(hdr);
1260                 tid = qc[0] & 0xf;
1261         }
1262
1263         sta_id = iwl_get_ra_sta_id(priv, hdr);
1264         if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
1265                 IWL_ERROR("Station not known\n");
1266                 return;
1267         }
1268
1269         if (txq->sched_retry) {
1270                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1271                 struct iwl_ht_agg *agg = NULL;
1272
1273                 if (!qc)
1274                         return;
1275
1276                 agg = &priv->stations[sta_id].tid[tid].agg;
1277
1278                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1279
1280                 /* check if BAR is needed */
1281                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1282                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1283
1284                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1285                         int freed, ampdu_q;
1286                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1287                         IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1288                                            "%d index %d\n", scd_ssn , index);
1289                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1290                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1291
1292                         if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1293                             txq_id >= 0 && priv->mac80211_registered &&
1294                             agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
1295                                 /* calculate mac80211 ampdu sw queue to wake */
1296                                 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE +
1297                                           priv->hw->queues;
1298                                 if (agg->state == IWL_AGG_OFF)
1299                                         ieee80211_wake_queue(priv->hw, txq_id);
1300                                 else
1301                                         ieee80211_wake_queue(priv->hw, ampdu_q);
1302                         }
1303                         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1304                 }
1305         } else {
1306                 info->status.retry_count = tx_resp->failure_frame;
1307                 info->flags =
1308                         iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
1309                 iwl_hwrate_to_tx_control(priv,
1310                                         le32_to_cpu(tx_resp->rate_n_flags),
1311                                         info);
1312
1313                 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
1314                              "0x%x retries %d\n", txq_id,
1315                                 iwl_get_tx_fail_reason(status),
1316                                 status, le32_to_cpu(tx_resp->rate_n_flags),
1317                                 tx_resp->failure_frame);
1318
1319                 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
1320                 if (index != -1) {
1321                     int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1322                     if (tid != MAX_TID_COUNT)
1323                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1324                     if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1325                         (txq_id >= 0) && priv->mac80211_registered)
1326                         ieee80211_wake_queue(priv->hw, txq_id);
1327                     if (tid != MAX_TID_COUNT)
1328                         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1329                 }
1330         }
1331
1332         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1333                 IWL_ERROR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
1334 }
1335
1336 /* Currently 5000 is the supperset of everything */
1337 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1338 {
1339         return len;
1340 }
1341
1342 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1343 {
1344         /* in 5000 the tx power calibration is done in uCode */
1345         priv->disable_tx_power_cal = 1;
1346 }
1347
1348 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1349 {
1350         /* init calibration handlers */
1351         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1352                                         iwl5000_rx_calib_result;
1353         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1354                                         iwl5000_rx_calib_complete;
1355         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1356 }
1357
1358
1359 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1360 {
1361         return (addr >= RTC_DATA_LOWER_BOUND) &&
1362                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1363 }
1364
1365 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1366 {
1367         int ret = 0;
1368         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1369         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1370         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1371
1372         if ((rxon1->flags == rxon2->flags) &&
1373             (rxon1->filter_flags == rxon2->filter_flags) &&
1374             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1375             (rxon1->ofdm_ht_single_stream_basic_rates ==
1376              rxon2->ofdm_ht_single_stream_basic_rates) &&
1377             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1378              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1379             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1380              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1381             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1382             (rxon1->rx_chain == rxon2->rx_chain) &&
1383             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1384                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
1385                 return 0;
1386         }
1387
1388         rxon_assoc.flags = priv->staging_rxon.flags;
1389         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1390         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1391         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1392         rxon_assoc.reserved1 = 0;
1393         rxon_assoc.reserved2 = 0;
1394         rxon_assoc.reserved3 = 0;
1395         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1396             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1397         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1398             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1399         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1400         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1401                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1402         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1403
1404         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1405                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1406         if (ret)
1407                 return ret;
1408
1409         return ret;
1410 }
1411 static int  iwl5000_send_tx_power(struct iwl_priv *priv)
1412 {
1413         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1414
1415         /* half dBm need to multiply */
1416         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1417         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1418         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1419         return  iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1420                                        sizeof(tx_power_cmd), &tx_power_cmd,
1421                                        NULL);
1422 }
1423
1424 static void iwl5000_temperature(struct iwl_priv *priv)
1425 {
1426         /* store temperature from statistics (in Celsius) */
1427         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1428 }
1429
1430 /* Calc max signal level (dBm) among 3 possible receivers */
1431 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1432                              struct iwl_rx_phy_res *rx_resp)
1433 {
1434         /* data from PHY/DSP regarding signal strength, etc.,
1435          *   contents are always there, not configurable by host
1436          */
1437         struct iwl5000_non_cfg_phy *ncphy =
1438                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1439         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1440         u8 agc;
1441
1442         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1443         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1444
1445         /* Find max rssi among 3 possible receivers.
1446          * These values are measured by the digital signal processor (DSP).
1447          * They should stay fairly constant even as the signal strength varies,
1448          *   if the radio's automatic gain control (AGC) is working right.
1449          * AGC value (see below) will provide the "interesting" info.
1450          */
1451         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1452         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1453         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1454         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1455         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1456
1457         max_rssi = max_t(u32, rssi_a, rssi_b);
1458         max_rssi = max_t(u32, max_rssi, rssi_c);
1459
1460         IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1461                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1462
1463         /* dBm = max_rssi dB - agc dB - constant.
1464          * Higher AGC (higher radio gain) means lower signal. */
1465         return max_rssi - agc - IWL_RSSI_OFFSET;
1466 }
1467
1468 static struct iwl_hcmd_ops iwl5000_hcmd = {
1469         .rxon_assoc = iwl5000_send_rxon_assoc,
1470 };
1471
1472 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1473         .get_hcmd_size = iwl5000_get_hcmd_size,
1474         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1475         .gain_computation = iwl5000_gain_computation,
1476         .chain_noise_reset = iwl5000_chain_noise_reset,
1477         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1478         .calc_rssi = iwl5000_calc_rssi,
1479 };
1480
1481 static struct iwl_lib_ops iwl5000_lib = {
1482         .set_hw_params = iwl5000_hw_set_hw_params,
1483         .alloc_shared_mem = iwl5000_alloc_shared_mem,
1484         .free_shared_mem = iwl5000_free_shared_mem,
1485         .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
1486         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1487         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1488         .txq_set_sched = iwl5000_txq_set_sched,
1489         .txq_agg_enable = iwl5000_txq_agg_enable,
1490         .txq_agg_disable = iwl5000_txq_agg_disable,
1491         .rx_handler_setup = iwl5000_rx_handler_setup,
1492         .setup_deferred_work = iwl5000_setup_deferred_work,
1493         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1494         .load_ucode = iwl5000_load_ucode,
1495         .init_alive_start = iwl5000_init_alive_start,
1496         .alive_notify = iwl5000_alive_notify,
1497         .send_tx_power = iwl5000_send_tx_power,
1498         .temperature = iwl5000_temperature,
1499         .update_chain_flags = iwl4965_update_chain_flags,
1500         .apm_ops = {
1501                 .init = iwl5000_apm_init,
1502                 .reset = iwl5000_apm_reset,
1503                 .stop = iwl5000_apm_stop,
1504                 .config = iwl5000_nic_config,
1505                 .set_pwr_src = iwl4965_set_pwr_src,
1506         },
1507         .eeprom_ops = {
1508                 .regulatory_bands = {
1509                         EEPROM_5000_REG_BAND_1_CHANNELS,
1510                         EEPROM_5000_REG_BAND_2_CHANNELS,
1511                         EEPROM_5000_REG_BAND_3_CHANNELS,
1512                         EEPROM_5000_REG_BAND_4_CHANNELS,
1513                         EEPROM_5000_REG_BAND_5_CHANNELS,
1514                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1515                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1516                 },
1517                 .verify_signature  = iwlcore_eeprom_verify_signature,
1518                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1519                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1520                 .check_version  = iwl5000_eeprom_check_version,
1521                 .query_addr = iwl5000_eeprom_query_addr,
1522         },
1523 };
1524
1525 static struct iwl_ops iwl5000_ops = {
1526         .lib = &iwl5000_lib,
1527         .hcmd = &iwl5000_hcmd,
1528         .utils = &iwl5000_hcmd_utils,
1529 };
1530
1531 static struct iwl_mod_params iwl50_mod_params = {
1532         .num_of_queues = IWL50_NUM_QUEUES,
1533         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1534         .enable_qos = 1,
1535         .amsdu_size_8K = 1,
1536         .restart_fw = 1,
1537         /* the rest are 0 by default */
1538 };
1539
1540
1541 struct iwl_cfg iwl5300_agn_cfg = {
1542         .name = "5300AGN",
1543         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1544         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1545         .ops = &iwl5000_ops,
1546         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1547         .mod_params = &iwl50_mod_params,
1548 };
1549
1550 struct iwl_cfg iwl5100_bg_cfg = {
1551         .name = "5100BG",
1552         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1553         .sku = IWL_SKU_G,
1554         .ops = &iwl5000_ops,
1555         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1556         .mod_params = &iwl50_mod_params,
1557 };
1558
1559 struct iwl_cfg iwl5100_abg_cfg = {
1560         .name = "5100ABG",
1561         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1562         .sku = IWL_SKU_A|IWL_SKU_G,
1563         .ops = &iwl5000_ops,
1564         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1565         .mod_params = &iwl50_mod_params,
1566 };
1567
1568 struct iwl_cfg iwl5100_agn_cfg = {
1569         .name = "5100AGN",
1570         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1571         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1572         .ops = &iwl5000_ops,
1573         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1574         .mod_params = &iwl50_mod_params,
1575 };
1576
1577 struct iwl_cfg iwl5350_agn_cfg = {
1578         .name = "5350AGN",
1579         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1580         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1581         .ops = &iwl5000_ops,
1582         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1583         .mod_params = &iwl50_mod_params,
1584 };
1585
1586 MODULE_FIRMWARE("iwlwifi-5000" IWL5000_UCODE_API ".ucode");
1587
1588 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1589 MODULE_PARM_DESC(disable50,
1590                   "manually disable the 50XX radio (default 0 [radio on])");
1591 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1592 MODULE_PARM_DESC(swcrypto50,
1593                   "using software crypto engine (default 0 [hardware])\n");
1594 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1595 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1596 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1597 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1598 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1599 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1600 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1601 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1602 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1603 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1604 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1605 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");