drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/delay.h>
  34 #include <linux/sched.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/wireless.h>
  38 #include <linux/firmware.h>
  39 #include <linux/etherdevice.h>
  40 #include <asm/unaligned.h>
  41 #include <net/mac80211.h>
  42
  43 #include "iwl-fh.h"
  44 #include "iwl-3945-fh.h"
  45 #include "iwl-commands.h"
  46 #include "iwl-sta.h"
  47 #include "iwl-3945.h"
  48 #include "iwl-eeprom.h"
  49 #include "iwl-core.h"
  50 #include "iwl-helpers.h"
  51 #include "iwl-led.h"
  52 #include "iwl-3945-led.h"
  53 #include "iwl-3945-debugfs.h"
  54 #include "iwl-legacy.h"
  55
  56 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  57         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  58                                     IWL_RATE_##r##M_IEEE,   \
  59                                     IWL_RATE_##ip##M_INDEX, \
  60                                     IWL_RATE_##in##M_INDEX, \
  61                                     IWL_RATE_##rp##M_INDEX, \
  62                                     IWL_RATE_##rn##M_INDEX, \
  63                                     IWL_RATE_##pp##M_INDEX, \
  64                                     IWL_RATE_##np##M_INDEX, \
  65                                     IWL_RATE_##r##M_INDEX_TABLE, \
  66                                     IWL_RATE_##ip##M_INDEX_TABLE }
  67
  68 /*
  69  * Parameter order:
  70  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  71  *
  72  * If there isn't a valid next or previous rate then INV is used which
  73  * maps to IWL_RATE_INVALID
  74  *
  75  */
  76 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  77         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  78         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  79         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  80         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  81         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  82         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  83         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  84         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  85         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  86         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  87         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  88         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  89 };
  90
  91 static inline u8 iwl3945_get_prev_ieee_rate(u8 rate_index)
  92 {
  93         u8 rate = iwl3945_rates[rate_index].prev_ieee;
  94
  95         if (rate == IWL_RATE_INVALID)
  96                 rate = rate_index;
  97         return rate;
  98 }
  99
 100 /* 1 = enable the iwl3945_disable_events() function */
 101 #define IWL_EVT_DISABLE (0)
 102 #define IWL_EVT_DISABLE_SIZE (1532/32)
 103
 104 /**
 105  * iwl3945_disable_events - Disable selected events in uCode event log
 106  *
 107  * Disable an event by writing "1"s into "disable"
 108  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
 109  *   Default values of 0 enable uCode events to be logged.
 110  * Use for only special debugging.  This function is just a placeholder as-is,
 111  *   you'll need to provide the special bits! ...
 112  *   ... and set IWL_EVT_DISABLE to 1. */
 113 void iwl3945_disable_events(struct iwl_priv *priv)
 114 {
 115         int i;
 116         u32 base;               /* SRAM address of event log header */
 117         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 118         u32 array_size;         /* # of u32 entries in array */
 119         static const u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 120                 0x00000000,     /*   31 -    0  Event id numbers */
 121                 0x00000000,     /*   63 -   32 */
 122                 0x00000000,     /*   95 -   64 */
 123                 0x00000000,     /*  127 -   96 */
 124                 0x00000000,     /*  159 -  128 */
 125                 0x00000000,     /*  191 -  160 */
 126                 0x00000000,     /*  223 -  192 */
 127                 0x00000000,     /*  255 -  224 */
 128                 0x00000000,     /*  287 -  256 */
 129                 0x00000000,     /*  319 -  288 */
 130                 0x00000000,     /*  351 -  320 */
 131                 0x00000000,     /*  383 -  352 */
 132                 0x00000000,     /*  415 -  384 */
 133                 0x00000000,     /*  447 -  416 */
 134                 0x00000000,     /*  479 -  448 */
 135                 0x00000000,     /*  511 -  480 */
 136                 0x00000000,     /*  543 -  512 */
 137                 0x00000000,     /*  575 -  544 */
 138                 0x00000000,     /*  607 -  576 */
 139                 0x00000000,     /*  639 -  608 */
 140                 0x00000000,     /*  671 -  640 */
 141                 0x00000000,     /*  703 -  672 */
 142                 0x00000000,     /*  735 -  704 */
 143                 0x00000000,     /*  767 -  736 */
 144                 0x00000000,     /*  799 -  768 */
 145                 0x00000000,     /*  831 -  800 */
 146                 0x00000000,     /*  863 -  832 */
 147                 0x00000000,     /*  895 -  864 */
 148                 0x00000000,     /*  927 -  896 */
 149                 0x00000000,     /*  959 -  928 */
 150                 0x00000000,     /*  991 -  960 */
 151                 0x00000000,     /* 1023 -  992 */
 152                 0x00000000,     /* 1055 - 1024 */
 153                 0x00000000,     /* 1087 - 1056 */
 154                 0x00000000,     /* 1119 - 1088 */
 155                 0x00000000,     /* 1151 - 1120 */
 156                 0x00000000,     /* 1183 - 1152 */
 157                 0x00000000,     /* 1215 - 1184 */
 158                 0x00000000,     /* 1247 - 1216 */
 159                 0x00000000,     /* 1279 - 1248 */
 160                 0x00000000,     /* 1311 - 1280 */
 161                 0x00000000,     /* 1343 - 1312 */
 162                 0x00000000,     /* 1375 - 1344 */
 163                 0x00000000,     /* 1407 - 1376 */
 164                 0x00000000,     /* 1439 - 1408 */
 165                 0x00000000,     /* 1471 - 1440 */
 166                 0x00000000,     /* 1503 - 1472 */
 167         };
 168
 169         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 170         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 171                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 172                 return;
 173         }
 174
 175         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 176         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 177
 178         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 179                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 180                                disable_ptr);
 181                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 182                         iwl_write_targ_mem(priv,
 183                                            disable_ptr + (i * sizeof(u32)),
 184                                            evt_disable[i]);
 185
 186         } else {
 187                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 188                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 189                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 190                                disable_ptr, array_size);
 191         }
 192
 193 }
 194
 195 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 196 {
 197         int idx;
 198
 199         for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
 200                 if (iwl3945_rates[idx].plcp == plcp)
 201                         return idx;
 202         return -1;
 203 }
 204
 205 #ifdef CONFIG_IWLWIFI_DEBUG
 206 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
 207
 208 static const char *iwl3945_get_tx_fail_reason(u32 status)
 209 {
 210         switch (status & TX_STATUS_MSK) {
 211         case TX_3945_STATUS_SUCCESS:
 212                 return "SUCCESS";
 213                 TX_STATUS_ENTRY(SHORT_LIMIT);
 214                 TX_STATUS_ENTRY(LONG_LIMIT);
 215                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 216                 TX_STATUS_ENTRY(MGMNT_ABORT);
 217                 TX_STATUS_ENTRY(NEXT_FRAG);
 218                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 219                 TX_STATUS_ENTRY(DEST_PS);
 220                 TX_STATUS_ENTRY(ABORTED);
 221                 TX_STATUS_ENTRY(BT_RETRY);
 222                 TX_STATUS_ENTRY(STA_INVALID);
 223                 TX_STATUS_ENTRY(FRAG_DROPPED);
 224                 TX_STATUS_ENTRY(TID_DISABLE);
 225                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 226                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 227                 TX_STATUS_ENTRY(TX_LOCKED);
 228                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 229         }
 230
 231         return "UNKNOWN";
 232 }
 233 #else
 234 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 235 {
 236         return "";
 237 }
 238 #endif
 239
 240 /*
 241  * get ieee prev rate from rate scale table.
 242  * for A and B mode we need to overright prev
 243  * value
 244  */
 245 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 246 {
 247         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 248
 249         switch (priv->band) {
 250         case IEEE80211_BAND_5GHZ:
 251                 if (rate == IWL_RATE_12M_INDEX)
 252                         next_rate = IWL_RATE_9M_INDEX;
 253                 else if (rate == IWL_RATE_6M_INDEX)
 254                         next_rate = IWL_RATE_6M_INDEX;
 255                 break;
 256         case IEEE80211_BAND_2GHZ:
 257                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 258                     iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
 259                         if (rate == IWL_RATE_11M_INDEX)
 260                                 next_rate = IWL_RATE_5M_INDEX;
 261                 }
 262                 break;
 263
 264         default:
 265                 break;
 266         }
 267
 268         return next_rate;
 269 }
 270
 271
 272 /**
 273  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 274  *
 275  * When FW advances 'R' index, all entries between old and new 'R' index
 276  * need to be reclaimed. As result, some free space forms. If there is
 277  * enough free space (> low mark), wake the stack that feeds us.
 278  */
 279 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 280                                      int txq_id, int index)
 281 {
 282         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 283         struct iwl_queue *q = &txq->q;
 284         struct iwl_tx_info *tx_info;
 285
 286         BUG_ON(txq_id == IWL39_CMD_QUEUE_NUM);
 287
 288         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 289                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 290
 291                 tx_info = &txq->txb[txq->q.read_ptr];
 292                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
 293                 tx_info->skb = NULL;
 294                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 295         }
 296
 297         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 298                         (txq_id != IWL39_CMD_QUEUE_NUM) &&
 299                         priv->mac80211_registered)
 300                 iwl_wake_queue(priv, txq);
 301 }
 302
 303 /**
 304  * iwl3945_rx_reply_tx - Handle Tx response
 305  */
 306 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 307                                 struct iwl_rx_mem_buffer *rxb)
 308 {
 309         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 310         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 311         int txq_id = SEQ_TO_QUEUE(sequence);
 312         int index = SEQ_TO_INDEX(sequence);
 313         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 314         struct ieee80211_tx_info *info;
 315         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 316         u32  status = le32_to_cpu(tx_resp->status);
 317         int rate_idx;
 318         int fail;
 319
 320         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 321                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 322                           "is out of range [0-%d] %d %d\n", txq_id,
 323                           index, txq->q.n_bd, txq->q.write_ptr,
 324                           txq->q.read_ptr);
 325                 return;
 326         }
 327
 328         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
 329         ieee80211_tx_info_clear_status(info);
 330
 331         /* Fill the MRR chain with some info about on-chip retransmissions */
 332         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 333         if (info->band == IEEE80211_BAND_5GHZ)
 334                 rate_idx -= IWL_FIRST_OFDM_RATE;
 335
 336         fail = tx_resp->failure_frame;
 337
 338         info->status.rates[0].idx = rate_idx;
 339         info->status.rates[0].count = fail + 1; /* add final attempt */
 340
 341         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 342         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 343                                 IEEE80211_TX_STAT_ACK : 0;
 344
 345         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 346                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 347                         tx_resp->rate, tx_resp->failure_frame);
 348
 349         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 350         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 351
 352         if (status & TX_ABORT_REQUIRED_MSK)
 353                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 354 }
 355
 356
 357
 358 /*****************************************************************************
 359  *
 360  * Intel PRO/Wireless 3945ABG/BG Network Connection
 361  *
 362  *  RX handler implementations
 363  *
 364  *****************************************************************************/
 365 #ifdef CONFIG_IWLWIFI_DEBUGFS
 366 /*
 367  *  based on the assumption of all statistics counter are in DWORD
 368  *  FIXME: This function is for debugging, do not deal with
 369  *  the case of counters roll-over.
 370  */
 371 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
 372                                             __le32 *stats)
 373 {
 374         int i;
 375         __le32 *prev_stats;
 376         u32 *accum_stats;
 377         u32 *delta, *max_delta;
 378
 379         prev_stats = (__le32 *)&priv->_3945.statistics;
 380         accum_stats = (u32 *)&priv->_3945.accum_statistics;
 381         delta = (u32 *)&priv->_3945.delta_statistics;
 382         max_delta = (u32 *)&priv->_3945.max_delta;
 383
 384         for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
 385              i += sizeof(__le32), stats++, prev_stats++, delta++,
 386              max_delta++, accum_stats++) {
 387                 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
 388                         *delta = (le32_to_cpu(*stats) -
 389                                 le32_to_cpu(*prev_stats));
 390                         *accum_stats += *delta;
 391                         if (*delta > *max_delta)
 392                                 *max_delta = *delta;
 393                 }
 394         }
 395
 396         /* reset accumulative statistics for "no-counter" type statistics */
 397         priv->_3945.accum_statistics.general.temperature =
 398                 priv->_3945.statistics.general.temperature;
 399         priv->_3945.accum_statistics.general.ttl_timestamp =
 400                 priv->_3945.statistics.general.ttl_timestamp;
 401 }
 402 #endif
 403
 404 /**
 405  * iwl3945_good_plcp_health - checks for plcp error.
 406  *
 407  * When the plcp error is exceeding the thresholds, reset the radio
 408  * to improve the throughput.
 409  */
 410 static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
 411                                 struct iwl_rx_packet *pkt)
 412 {
 413         bool rc = true;
 414         struct iwl3945_notif_statistics current_stat;
 415         int combined_plcp_delta;
 416         unsigned int plcp_msec;
 417         unsigned long plcp_received_jiffies;
 418
 419         if (priv->cfg->base_params->plcp_delta_threshold ==
 420             IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
 421                 IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
 422                 return rc;
 423         }
 424         memcpy(&current_stat, pkt->u.raw, sizeof(struct
 425                         iwl3945_notif_statistics));
 426         /*
 427          * check for plcp_err and trigger radio reset if it exceeds
 428          * the plcp error threshold plcp_delta.
 429          */
 430         plcp_received_jiffies = jiffies;
 431         plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
 432                                         (long) priv->plcp_jiffies);
 433         priv->plcp_jiffies = plcp_received_jiffies;
 434         /*
 435          * check to make sure plcp_msec is not 0 to prevent division
 436          * by zero.
 437          */
 438         if (plcp_msec) {
 439                 combined_plcp_delta =
 440                         (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
 441                         le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
 442
 443                 if ((combined_plcp_delta > 0) &&
 444                         ((combined_plcp_delta * 100) / plcp_msec) >
 445                         priv->cfg->base_params->plcp_delta_threshold) {
 446                         /*
 447                          * if plcp_err exceed the threshold, the following
 448                          * data is printed in csv format:
 449                          *    Text: plcp_err exceeded %d,
 450                          *    Received ofdm.plcp_err,
 451                          *    Current ofdm.plcp_err,
 452                          *    combined_plcp_delta,
 453                          *    plcp_msec
 454                          */
 455                         IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
 456                                 "%u, %d, %u mSecs\n",
 457                                 priv->cfg->base_params->plcp_delta_threshold,
 458                                 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
 459                                 combined_plcp_delta, plcp_msec);
 460                         /*
 461                          * Reset the RF radio due to the high plcp
 462                          * error rate
 463                          */
 464                         rc = false;
 465                 }
 466         }
 467         return rc;
 468 }
 469
 470 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 471                 struct iwl_rx_mem_buffer *rxb)
 472 {
 473         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 474
 475         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 476                      (int)sizeof(struct iwl3945_notif_statistics),
 477                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 478 #ifdef CONFIG_IWLWIFI_DEBUGFS
 479         iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
 480 #endif
 481         iwl_recover_from_statistics(priv, pkt);
 482
 483         memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
 484 }
 485
 486 void iwl3945_reply_statistics(struct iwl_priv *priv,
 487                               struct iwl_rx_mem_buffer *rxb)
 488 {
 489         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 490         __le32 *flag = (__le32 *)&pkt->u.raw;
 491
 492         if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
 493 #ifdef CONFIG_IWLWIFI_DEBUGFS
 494                 memset(&priv->_3945.accum_statistics, 0,
 495                         sizeof(struct iwl3945_notif_statistics));
 496                 memset(&priv->_3945.delta_statistics, 0,
 497                         sizeof(struct iwl3945_notif_statistics));
 498                 memset(&priv->_3945.max_delta, 0,
 499                         sizeof(struct iwl3945_notif_statistics));
 500 #endif
 501                 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
 502         }
 503         iwl3945_hw_rx_statistics(priv, rxb);
 504 }
 505
 506
 507 /******************************************************************************
 508  *
 509  * Misc. internal state and helper functions
 510  *
 511  ******************************************************************************/
 512
 513 /* This is necessary only for a number of statistics, see the caller. */
 514 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 515                 struct ieee80211_hdr *header)
 516 {
 517         /* Filter incoming packets to determine if they are targeted toward
 518          * this network, discarding packets coming from ourselves */
 519         switch (priv->iw_mode) {
 520         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 521                 /* packets to our IBSS update information */
 522                 return !compare_ether_addr(header->addr3, priv->bssid);
 523         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 524                 /* packets to our IBSS update information */
 525                 return !compare_ether_addr(header->addr2, priv->bssid);
 526         default:
 527                 return 1;
 528         }
 529 }
 530
 531 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 532                                    struct iwl_rx_mem_buffer *rxb,
 533                                    struct ieee80211_rx_status *stats)
 534 {
 535         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 536         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 537         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 538         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 539         u16 len = le16_to_cpu(rx_hdr->len);
 540         struct sk_buff *skb;
 541         __le16 fc = hdr->frame_control;
 542
 543         /* We received data from the HW, so stop the watchdog */
 544         if (unlikely(len + IWL39_RX_FRAME_SIZE >
 545                      PAGE_SIZE << priv->hw_params.rx_page_order)) {
 546                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 547                 return;
 548         }
 549
 550         /* We only process data packets if the interface is open */
 551         if (unlikely(!priv->is_open)) {
 552                 IWL_DEBUG_DROP_LIMIT(priv,
 553                         "Dropping packet while interface is not open.\n");
 554                 return;
 555         }
 556
 557         skb = dev_alloc_skb(128);
 558         if (!skb) {
 559                 IWL_ERR(priv, "dev_alloc_skb failed\n");
 560                 return;
 561         }
 562
 563         if (!iwl3945_mod_params.sw_crypto)
 564                 iwl_set_decrypted_flag(priv,
 565                                        (struct ieee80211_hdr *)rxb_addr(rxb),
 566                                        le32_to_cpu(rx_end->status), stats);
 567
 568         skb_add_rx_frag(skb, 0, rxb->page,
 569                         (void *)rx_hdr->payload - (void *)pkt, len);
 570
 571         iwl_update_stats(priv, false, fc, len);
 572         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
 573
 574         ieee80211_rx(priv->hw, skb);
 575         priv->alloc_rxb_page--;
 576         rxb->page = NULL;
 577 }
 578
 579 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 580
 581 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 582                                 struct iwl_rx_mem_buffer *rxb)
 583 {
 584         struct ieee80211_hdr *header;
 585         struct ieee80211_rx_status rx_status;
 586         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 587         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 588         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 589         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 590         u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
 591         u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
 592         u8 network_packet;
 593
 594         rx_status.flag = 0;
 595         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 596         rx_status.freq =
 597                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 598         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 599                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 600
 601         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 602         if (rx_status.band == IEEE80211_BAND_5GHZ)
 603                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 604
 605         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
 606                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 607
 608         /* set the preamble flag if appropriate */
 609         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 610                 rx_status.flag |= RX_FLAG_SHORTPRE;
 611
 612         if ((unlikely(rx_stats->phy_count > 20))) {
 613                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 614                                 rx_stats->phy_count);
 615                 return;
 616         }
 617
 618         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 619             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 620                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 621                 return;
 622         }
 623
 624
 625
 626         /* Convert 3945's rssi indicator to dBm */
 627         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 628
 629         IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
 630                         rx_status.signal, rx_stats_sig_avg,
 631                         rx_stats_noise_diff);
 632
 633         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 634
 635         network_packet = iwl3945_is_network_packet(priv, header);
 636
 637         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
 638                               network_packet ? '*' : ' ',
 639                               le16_to_cpu(rx_hdr->channel),
 640                               rx_status.signal, rx_status.signal,
 641                               rx_status.rate_idx);
 642
 643         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 644
 645         if (network_packet) {
 646                 priv->_3945.last_beacon_time =
 647                         le32_to_cpu(rx_end->beacon_timestamp);
 648                 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
 649                 priv->_3945.last_rx_rssi = rx_status.signal;
 650         }
 651
 652         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 653 }
 654
 655 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 656                                      struct iwl_tx_queue *txq,
 657                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 658 {
 659         int count;
 660         struct iwl_queue *q;
 661         struct iwl3945_tfd *tfd, *tfd_tmp;
 662
 663         q = &txq->q;
 664         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 665         tfd = &tfd_tmp[q->write_ptr];
 666
 667         if (reset)
 668                 memset(tfd, 0, sizeof(*tfd));
 669
 670         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 671
 672         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 673                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 674                           NUM_TFD_CHUNKS);
 675                 return -EINVAL;
 676         }
 677
 678         tfd->tbs[count].addr = cpu_to_le32(addr);
 679         tfd->tbs[count].len = cpu_to_le32(len);
 680
 681         count++;
 682
 683         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 684                                          TFD_CTL_PAD_SET(pad));
 685
 686         return 0;
 687 }
 688
 689 /**
 690  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 691  *
 692  * Does NOT advance any indexes
 693  */
 694 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 695 {
 696         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 697         int index = txq->q.read_ptr;
 698         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 699         struct pci_dev *dev = priv->pci_dev;
 700         int i;
 701         int counter;
 702
 703         /* sanity check */
 704         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 705         if (counter > NUM_TFD_CHUNKS) {
 706                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 707                 /* @todo issue fatal error, it is quite serious situation */
 708                 return;
 709         }
 710
 711         /* Unmap tx_cmd */
 712         if (counter)
 713                 pci_unmap_single(dev,
 714                                 dma_unmap_addr(&txq->meta[index], mapping),
 715                                 dma_unmap_len(&txq->meta[index], len),
 716                                 PCI_DMA_TODEVICE);
 717
 718         /* unmap chunks if any */
 719
 720         for (i = 1; i < counter; i++)
 721                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 722                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 723
 724         /* free SKB */
 725         if (txq->txb) {
 726                 struct sk_buff *skb;
 727
 728                 skb = txq->txb[txq->q.read_ptr].skb;
 729
 730                 /* can be called from irqs-disabled context */
 731                 if (skb) {
 732                         dev_kfree_skb_any(skb);
 733                         txq->txb[txq->q.read_ptr].skb = NULL;
 734                 }
 735         }
 736 }
 737
 738 /**
 739  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 740  *
 741 */
 742 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 743                                   struct iwl_device_cmd *cmd,
 744                                   struct ieee80211_tx_info *info,
 745                                   struct ieee80211_hdr *hdr,
 746                                   int sta_id, int tx_id)
 747 {
 748         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 749         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
 750         u16 rate_mask;
 751         int rate;
 752         u8 rts_retry_limit;
 753         u8 data_retry_limit;
 754         __le32 tx_flags;
 755         __le16 fc = hdr->frame_control;
 756         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 757
 758         rate = iwl3945_rates[rate_index].plcp;
 759         tx_flags = tx_cmd->tx_flags;
 760
 761         /* We need to figure out how to get the sta->supp_rates while
 762          * in this running context */
 763         rate_mask = IWL_RATES_MASK;
 764
 765
 766         /* Set retry limit on DATA packets and Probe Responses*/
 767         if (ieee80211_is_probe_resp(fc))
 768                 data_retry_limit = 3;
 769         else
 770                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 771         tx_cmd->data_retry_limit = data_retry_limit;
 772
 773         if (tx_id >= IWL39_CMD_QUEUE_NUM)
 774                 rts_retry_limit = 3;
 775         else
 776                 rts_retry_limit = 7;
 777
 778         if (data_retry_limit < rts_retry_limit)
 779                 rts_retry_limit = data_retry_limit;
 780         tx_cmd->rts_retry_limit = rts_retry_limit;
 781
 782         tx_cmd->rate = rate;
 783         tx_cmd->tx_flags = tx_flags;
 784
 785         /* OFDM */
 786         tx_cmd->supp_rates[0] =
 787            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 788
 789         /* CCK */
 790         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
 791
 792         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 793                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 794                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
 795                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
 796 }
 797
 798 static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
 799 {
 800         unsigned long flags_spin;
 801         struct iwl_station_entry *station;
 802
 803         if (sta_id == IWL_INVALID_STATION)
 804                 return IWL_INVALID_STATION;
 805
 806         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 807         station = &priv->stations[sta_id];
 808
 809         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 810         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 811         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 812         iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
 813         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 814
 815         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 816                         sta_id, tx_rate);
 817         return sta_id;
 818 }
 819
 820 static void iwl3945_set_pwr_vmain(struct iwl_priv *priv)
 821 {
 822 /*
 823  * (for documentation purposes)
 824  * to set power to V_AUX, do
 825
 826                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 827                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 828                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 829                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 830
 831                         iwl_poll_bit(priv, CSR_GPIO_IN,
 832                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 833                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 834                 }
 835  */
 836
 837         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 838                         APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 839                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 840
 841         iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 842                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 843 }
 844
 845 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 846 {
 847         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
 848         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 849         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 850         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 851                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 852                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 853                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 854                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 855                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 856                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 857                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 858                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 859
 860         /* fake read to flush all prev I/O */
 861         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 862
 863         return 0;
 864 }
 865
 866 static int iwl3945_tx_reset(struct iwl_priv *priv)
 867 {
 868
 869         /* bypass mode */
 870         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 871
 872         /* RA 0 is active */
 873         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 874
 875         /* all 6 fifo are active */
 876         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 877
 878         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 879         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 880         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 881         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 882
 883         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 884                              priv->_3945.shared_phys);
 885
 886         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 887                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 888                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 889                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 890                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 891                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 892                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 893                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 894
 895
 896         return 0;
 897 }
 898
 899 /**
 900  * iwl3945_txq_ctx_reset - Reset TX queue context
 901  *
 902  * Destroys all DMA structures and initialize them again
 903  */
 904 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 905 {
 906         int rc;
 907         int txq_id, slots_num;
 908
 909         iwl3945_hw_txq_ctx_free(priv);
 910
 911         /* allocate tx queue structure */
 912         rc = iwl_alloc_txq_mem(priv);
 913         if (rc)
 914                 return rc;
 915
 916         /* Tx CMD queue */
 917         rc = iwl3945_tx_reset(priv);
 918         if (rc)
 919                 goto error;
 920
 921         /* Tx queue(s) */
 922         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 923                 slots_num = (txq_id == IWL39_CMD_QUEUE_NUM) ?
 924                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 925                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 926                                        txq_id);
 927                 if (rc) {
 928                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
 929                         goto error;
 930                 }
 931         }
 932
 933         return rc;
 934
 935  error:
 936         iwl3945_hw_txq_ctx_free(priv);
 937         return rc;
 938 }
 939
 940
 941 /*
 942  * Start up 3945's basic functionality after it has been reset
 943  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 944  * NOTE:  This does not load uCode nor start the embedded processor
 945  */
 946 static int iwl3945_apm_init(struct iwl_priv *priv)
 947 {
 948         int ret = iwl_apm_init(priv);
 949
 950         /* Clear APMG (NIC's internal power management) interrupts */
 951         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
 952         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
 953
 954         /* Reset radio chip */
 955         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 956         udelay(5);
 957         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 958
 959         return ret;
 960 }
 961
 962 static void iwl3945_nic_config(struct iwl_priv *priv)
 963 {
 964         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
 965         unsigned long flags;
 966         u8 rev_id = 0;
 967
 968         spin_lock_irqsave(&priv->lock, flags);
 969
 970         /* Determine HW type */
 971         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
 972
 973         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
 974
 975         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
 976                 IWL_DEBUG_INFO(priv, "RTP type\n");
 977         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
 978                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
 979                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 980                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
 981         } else {
 982                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
 983                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 984                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
 985         }
 986
 987         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
 988                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
 989                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 990                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
 991         } else
 992                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
 993
 994         if ((eeprom->board_revision & 0xF0) == 0xD0) {
 995                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
 996                                eeprom->board_revision);
 997                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 998                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
 999         } else {
1000                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1001                                eeprom->board_revision);
1002                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1003                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1004         }
1005
1006         if (eeprom->almgor_m_version <= 1) {
1007                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1008                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1009                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1010                                eeprom->almgor_m_version);
1011         } else {
1012                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1013                                eeprom->almgor_m_version);
1014                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1015                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1016         }
1017         spin_unlock_irqrestore(&priv->lock, flags);
1018
1019         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1020                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1021
1022         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1023                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1024 }
1025
1026 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1027 {
1028         int rc;
1029         unsigned long flags;
1030         struct iwl_rx_queue *rxq = &priv->rxq;
1031
1032         spin_lock_irqsave(&priv->lock, flags);
1033         priv->cfg->ops->lib->apm_ops.init(priv);
1034         spin_unlock_irqrestore(&priv->lock, flags);
1035
1036         iwl3945_set_pwr_vmain(priv);
1037
1038         priv->cfg->ops->lib->apm_ops.config(priv);
1039
1040         /* Allocate the RX queue, or reset if it is already allocated */
1041         if (!rxq->bd) {
1042                 rc = iwl_rx_queue_alloc(priv);
1043                 if (rc) {
1044                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1045                         return -ENOMEM;
1046                 }
1047         } else
1048                 iwl3945_rx_queue_reset(priv, rxq);
1049
1050         iwl3945_rx_replenish(priv);
1051
1052         iwl3945_rx_init(priv, rxq);
1053
1054
1055         /* Look at using this instead:
1056         rxq->need_update = 1;
1057         iwl_rx_queue_update_write_ptr(priv, rxq);
1058         */
1059
1060         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1061
1062         rc = iwl3945_txq_ctx_reset(priv);
1063         if (rc)
1064                 return rc;
1065
1066         set_bit(STATUS_INIT, &priv->status);
1067
1068         return 0;
1069 }
1070
1071 /**
1072  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1073  *
1074  * Destroy all TX DMA queues and structures
1075  */
1076 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1077 {
1078         int txq_id;
1079
1080         /* Tx queues */
1081         if (priv->txq)
1082                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1083                      txq_id++)
1084                         if (txq_id == IWL39_CMD_QUEUE_NUM)
1085                                 iwl_cmd_queue_free(priv);
1086                         else
1087                                 iwl_tx_queue_free(priv, txq_id);
1088
1089         /* free tx queue structure */
1090         iwl_free_txq_mem(priv);
1091 }
1092
1093 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1094 {
1095         int txq_id;
1096
1097         /* stop SCD */
1098         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1099         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1100
1101         /* reset TFD queues */
1102         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1103                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1104                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1105                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1106                                 1000);
1107         }
1108
1109         iwl3945_hw_txq_ctx_free(priv);
1110 }
1111
1112 /**
1113  * iwl3945_hw_reg_adjust_power_by_temp
1114  * return index delta into power gain settings table
1115 */
1116 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1117 {
1118         return (new_reading - old_reading) * (-11) / 100;
1119 }
1120
1121 /**
1122  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1123  */
1124 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1125 {
1126         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1127 }
1128
1129 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1130 {
1131         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1132 }
1133
1134 /**
1135  * iwl3945_hw_reg_txpower_get_temperature
1136  * get the current temperature by reading from NIC
1137 */
1138 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1139 {
1140         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1141         int temperature;
1142
1143         temperature = iwl3945_hw_get_temperature(priv);
1144
1145         /* driver's okay range is -260 to +25.
1146          *   human readable okay range is 0 to +285 */
1147         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1148
1149         /* handle insane temp reading */
1150         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1151                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1152
1153                 /* if really really hot(?),
1154                  *   substitute the 3rd band/group's temp measured at factory */
1155                 if (priv->last_temperature > 100)
1156                         temperature = eeprom->groups[2].temperature;
1157                 else /* else use most recent "sane" value from driver */
1158                         temperature = priv->last_temperature;
1159         }
1160
1161         return temperature;     /* raw, not "human readable" */
1162 }
1163
1164 /* Adjust Txpower only if temperature variance is greater than threshold.
1165  *
1166  * Both are lower than older versions' 9 degrees */
1167 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1168
1169 /**
1170  * is_temp_calib_needed - determines if new calibration is needed
1171  *
1172  * records new temperature in tx_mgr->temperature.
1173  * replaces tx_mgr->last_temperature *only* if calib needed
1174  *    (assumes caller will actually do the calibration!). */
1175 static int is_temp_calib_needed(struct iwl_priv *priv)
1176 {
1177         int temp_diff;
1178
1179         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1180         temp_diff = priv->temperature - priv->last_temperature;
1181
1182         /* get absolute value */
1183         if (temp_diff < 0) {
1184                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1185                 temp_diff = -temp_diff;
1186         } else if (temp_diff == 0)
1187                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1188         else
1189                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1190
1191         /* if we don't need calibration, *don't* update last_temperature */
1192         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1193                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1194                 return 0;
1195         }
1196
1197         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1198
1199         /* assume that caller will actually do calib ...
1200          *   update the "last temperature" value */
1201         priv->last_temperature = priv->temperature;
1202         return 1;
1203 }
1204
1205 #define IWL_MAX_GAIN_ENTRIES 78
1206 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1207 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1208
1209 /* radio and DSP power table, each step is 1/2 dB.
1210  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1211 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1212         {
1213          {251, 127},            /* 2.4 GHz, highest power */
1214          {251, 127},
1215          {251, 127},
1216          {251, 127},
1217          {251, 125},
1218          {251, 110},
1219          {251, 105},
1220          {251, 98},
1221          {187, 125},
1222          {187, 115},
1223          {187, 108},
1224          {187, 99},
1225          {243, 119},
1226          {243, 111},
1227          {243, 105},
1228          {243, 97},
1229          {243, 92},
1230          {211, 106},
1231          {211, 100},
1232          {179, 120},
1233          {179, 113},
1234          {179, 107},
1235          {147, 125},
1236          {147, 119},
1237          {147, 112},
1238          {147, 106},
1239          {147, 101},
1240          {147, 97},
1241          {147, 91},
1242          {115, 107},
1243          {235, 121},
1244          {235, 115},
1245          {235, 109},
1246          {203, 127},
1247          {203, 121},
1248          {203, 115},
1249          {203, 108},
1250          {203, 102},
1251          {203, 96},
1252          {203, 92},
1253          {171, 110},
1254          {171, 104},
1255          {171, 98},
1256          {139, 116},
1257          {227, 125},
1258          {227, 119},
1259          {227, 113},
1260          {227, 107},
1261          {227, 101},
1262          {227, 96},
1263          {195, 113},
1264          {195, 106},
1265          {195, 102},
1266          {195, 95},
1267          {163, 113},
1268          {163, 106},
1269          {163, 102},
1270          {163, 95},
1271          {131, 113},
1272          {131, 106},
1273          {131, 102},
1274          {131, 95},
1275          {99, 113},
1276          {99, 106},
1277          {99, 102},
1278          {99, 95},
1279          {67, 113},
1280          {67, 106},
1281          {67, 102},
1282          {67, 95},
1283          {35, 113},
1284          {35, 106},
1285          {35, 102},
1286          {35, 95},
1287          {3, 113},
1288          {3, 106},
1289          {3, 102},
1290          {3, 95} },             /* 2.4 GHz, lowest power */
1291         {
1292          {251, 127},            /* 5.x GHz, highest power */
1293          {251, 120},
1294          {251, 114},
1295          {219, 119},
1296          {219, 101},
1297          {187, 113},
1298          {187, 102},
1299          {155, 114},
1300          {155, 103},
1301          {123, 117},
1302          {123, 107},
1303          {123, 99},
1304          {123, 92},
1305          {91, 108},
1306          {59, 125},
1307          {59, 118},
1308          {59, 109},
1309          {59, 102},
1310          {59, 96},
1311          {59, 90},
1312          {27, 104},
1313          {27, 98},
1314          {27, 92},
1315          {115, 118},
1316          {115, 111},
1317          {115, 104},
1318          {83, 126},
1319          {83, 121},
1320          {83, 113},
1321          {83, 105},
1322          {83, 99},
1323          {51, 118},
1324          {51, 111},
1325          {51, 104},
1326          {51, 98},
1327          {19, 116},
1328          {19, 109},
1329          {19, 102},
1330          {19, 98},
1331          {19, 93},
1332          {171, 113},
1333          {171, 107},
1334          {171, 99},
1335          {139, 120},
1336          {139, 113},
1337          {139, 107},
1338          {139, 99},
1339          {107, 120},
1340          {107, 113},
1341          {107, 107},
1342          {107, 99},
1343          {75, 120},
1344          {75, 113},
1345          {75, 107},
1346          {75, 99},
1347          {43, 120},
1348          {43, 113},
1349          {43, 107},
1350          {43, 99},
1351          {11, 120},
1352          {11, 113},
1353          {11, 107},
1354          {11, 99},
1355          {131, 107},
1356          {131, 99},
1357          {99, 120},
1358          {99, 113},
1359          {99, 107},
1360          {99, 99},
1361          {67, 120},
1362          {67, 113},
1363          {67, 107},
1364          {67, 99},
1365          {35, 120},
1366          {35, 113},
1367          {35, 107},
1368          {35, 99},
1369          {3, 120} }             /* 5.x GHz, lowest power */
1370 };
1371
1372 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1373 {
1374         if (index < 0)
1375                 return 0;
1376         if (index >= IWL_MAX_GAIN_ENTRIES)
1377                 return IWL_MAX_GAIN_ENTRIES - 1;
1378         return (u8) index;
1379 }
1380
1381 /* Kick off thermal recalibration check every 60 seconds */
1382 #define REG_RECALIB_PERIOD (60)
1383
1384 /**
1385  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1386  *
1387  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1388  * or 6 Mbit (OFDM) rates.
1389  */
1390 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1391                                s32 rate_index, const s8 *clip_pwrs,
1392                                struct iwl_channel_info *ch_info,
1393                                int band_index)
1394 {
1395         struct iwl3945_scan_power_info *scan_power_info;
1396         s8 power;
1397         u8 power_index;
1398
1399         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1400
1401         /* use this channel group's 6Mbit clipping/saturation pwr,
1402          *   but cap at regulatory scan power restriction (set during init
1403          *   based on eeprom channel data) for this channel.  */
1404         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1405
1406         /* further limit to user's max power preference.
1407          * FIXME:  Other spectrum management power limitations do not
1408          *   seem to apply?? */
1409         power = min(power, priv->tx_power_user_lmt);
1410         scan_power_info->requested_power = power;
1411
1412         /* find difference between new scan *power* and current "normal"
1413          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1414          *   current "normal" temperature-compensated Tx power *index* for
1415          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1416          *   *index*. */
1417         power_index = ch_info->power_info[rate_index].power_table_index
1418             - (power - ch_info->power_info
1419                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1420
1421         /* store reference index that we use when adjusting *all* scan
1422          *   powers.  So we can accommodate user (all channel) or spectrum
1423          *   management (single channel) power changes "between" temperature
1424          *   feedback compensation procedures.
1425          * don't force fit this reference index into gain table; it may be a
1426          *   negative number.  This will help avoid errors when we're at
1427          *   the lower bounds (highest gains, for warmest temperatures)
1428          *   of the table. */
1429
1430         /* don't exceed table bounds for "real" setting */
1431         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1432
1433         scan_power_info->power_table_index = power_index;
1434         scan_power_info->tpc.tx_gain =
1435             power_gain_table[band_index][power_index].tx_gain;
1436         scan_power_info->tpc.dsp_atten =
1437             power_gain_table[band_index][power_index].dsp_atten;
1438 }
1439
1440 /**
1441  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1442  *
1443  * Configures power settings for all rates for the current channel,
1444  * using values from channel info struct, and send to NIC
1445  */
1446 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1447 {
1448         int rate_idx, i;
1449         const struct iwl_channel_info *ch_info = NULL;
1450         struct iwl3945_txpowertable_cmd txpower = {
1451                 .channel = priv->contexts[IWL_RXON_CTX_BSS].active.channel,
1452         };
1453         u16 chan;
1454
1455         if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
1456                       "TX Power requested while scanning!\n"))
1457                 return -EAGAIN;
1458
1459         chan = le16_to_cpu(priv->contexts[IWL_RXON_CTX_BSS].active.channel);
1460
1461         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1462         ch_info = iwl_get_channel_info(priv, priv->band, chan);
1463         if (!ch_info) {
1464                 IWL_ERR(priv,
1465                         "Failed to get channel info for channel %d [%d]\n",
1466                         chan, priv->band);
1467                 return -EINVAL;
1468         }
1469
1470         if (!is_channel_valid(ch_info)) {
1471                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1472                                 "non-Tx channel.\n");
1473                 return 0;
1474         }
1475
1476         /* fill cmd with power settings for all rates for current channel */
1477         /* Fill OFDM rate */
1478         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1479              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1480
1481                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1482                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1483
1484                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1485                                 le16_to_cpu(txpower.channel),
1486                                 txpower.band,
1487                                 txpower.power[i].tpc.tx_gain,
1488                                 txpower.power[i].tpc.dsp_atten,
1489                                 txpower.power[i].rate);
1490         }
1491         /* Fill CCK rates */
1492         for (rate_idx = IWL_FIRST_CCK_RATE;
1493              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1494                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1495                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1496
1497                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1498                                 le16_to_cpu(txpower.channel),
1499                                 txpower.band,
1500                                 txpower.power[i].tpc.tx_gain,
1501                                 txpower.power[i].tpc.dsp_atten,
1502                                 txpower.power[i].rate);
1503         }
1504
1505         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1506                                 sizeof(struct iwl3945_txpowertable_cmd),
1507                                 &txpower);
1508
1509 }
1510
1511 /**
1512  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1513  * @ch_info: Channel to update.  Uses power_info.requested_power.
1514  *
1515  * Replace requested_power and base_power_index ch_info fields for
1516  * one channel.
1517  *
1518  * Called if user or spectrum management changes power preferences.
1519  * Takes into account h/w and modulation limitations (clip power).
1520  *
1521  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1522  *
1523  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1524  *       properly fill out the scan powers, and actual h/w gain settings,
1525  *       and send changes to NIC
1526  */
1527 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1528                              struct iwl_channel_info *ch_info)
1529 {
1530         struct iwl3945_channel_power_info *power_info;
1531         int power_changed = 0;
1532         int i;
1533         const s8 *clip_pwrs;
1534         int power;
1535
1536         /* Get this chnlgrp's rate-to-max/clip-powers table */
1537         clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1538
1539         /* Get this channel's rate-to-current-power settings table */
1540         power_info = ch_info->power_info;
1541
1542         /* update OFDM Txpower settings */
1543         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1544              i++, ++power_info) {
1545                 int delta_idx;
1546
1547                 /* limit new power to be no more than h/w capability */
1548                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1549                 if (power == power_info->requested_power)
1550                         continue;
1551
1552                 /* find difference between old and new requested powers,
1553                  *    update base (non-temp-compensated) power index */
1554                 delta_idx = (power - power_info->requested_power) * 2;
1555                 power_info->base_power_index -= delta_idx;
1556
1557                 /* save new requested power value */
1558                 power_info->requested_power = power;
1559
1560                 power_changed = 1;
1561         }
1562
1563         /* update CCK Txpower settings, based on OFDM 12M setting ...
1564          *    ... all CCK power settings for a given channel are the *same*. */
1565         if (power_changed) {
1566                 power =
1567                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1568                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1569
1570                 /* do all CCK rates' iwl3945_channel_power_info structures */
1571                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1572                         power_info->requested_power = power;
1573                         power_info->base_power_index =
1574                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1575                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1576                         ++power_info;
1577                 }
1578         }
1579
1580         return 0;
1581 }
1582
1583 /**
1584  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1585  *
1586  * NOTE: Returned power limit may be less (but not more) than requested,
1587  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1588  *       (no consideration for h/w clipping limitations).
1589  */
1590 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1591 {
1592         s8 max_power;
1593
1594 #if 0
1595         /* if we're using TGd limits, use lower of TGd or EEPROM */
1596         if (ch_info->tgd_data.max_power != 0)
1597                 max_power = min(ch_info->tgd_data.max_power,
1598                                 ch_info->eeprom.max_power_avg);
1599
1600         /* else just use EEPROM limits */
1601         else
1602 #endif
1603                 max_power = ch_info->eeprom.max_power_avg;
1604
1605         return min(max_power, ch_info->max_power_avg);
1606 }
1607
1608 /**
1609  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1610  *
1611  * Compensate txpower settings of *all* channels for temperature.
1612  * This only accounts for the difference between current temperature
1613  *   and the factory calibration temperatures, and bases the new settings
1614  *   on the channel's base_power_index.
1615  *
1616  * If RxOn is "associated", this sends the new Txpower to NIC!
1617  */
1618 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1619 {
1620         struct iwl_channel_info *ch_info = NULL;
1621         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1622         int delta_index;
1623         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1624         u8 a_band;
1625         u8 rate_index;
1626         u8 scan_tbl_index;
1627         u8 i;
1628         int ref_temp;
1629         int temperature = priv->temperature;
1630
1631         if (priv->disable_tx_power_cal ||
1632             test_bit(STATUS_SCANNING, &priv->status)) {
1633                 /* do not perform tx power calibration */
1634                 return 0;
1635         }
1636         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1637         for (i = 0; i < priv->channel_count; i++) {
1638                 ch_info = &priv->channel_info[i];
1639                 a_band = is_channel_a_band(ch_info);
1640
1641                 /* Get this chnlgrp's factory calibration temperature */
1642                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1643                     temperature;
1644
1645                 /* get power index adjustment based on current and factory
1646                  * temps */
1647                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1648                                                               ref_temp);
1649
1650                 /* set tx power value for all rates, OFDM and CCK */
1651                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1652                      rate_index++) {
1653                         int power_idx =
1654                             ch_info->power_info[rate_index].base_power_index;
1655
1656                         /* temperature compensate */
1657                         power_idx += delta_index;
1658
1659                         /* stay within table range */
1660                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1661                         ch_info->power_info[rate_index].
1662                             power_table_index = (u8) power_idx;
1663                         ch_info->power_info[rate_index].tpc =
1664                             power_gain_table[a_band][power_idx];
1665                 }
1666
1667                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1668                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1669
1670                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1671                 for (scan_tbl_index = 0;
1672                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1673                         s32 actual_index = (scan_tbl_index == 0) ?
1674                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1675                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1676                                            actual_index, clip_pwrs,
1677                                            ch_info, a_band);
1678                 }
1679         }
1680
1681         /* send Txpower command for current channel to ucode */
1682         return priv->cfg->ops->lib->send_tx_power(priv);
1683 }
1684
1685 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1686 {
1687         struct iwl_channel_info *ch_info;
1688         s8 max_power;
1689         u8 a_band;
1690         u8 i;
1691
1692         if (priv->tx_power_user_lmt == power) {
1693                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1694                                 "limit: %ddBm.\n", power);
1695                 return 0;
1696         }
1697
1698         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1699         priv->tx_power_user_lmt = power;
1700
1701         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1702
1703         for (i = 0; i < priv->channel_count; i++) {
1704                 ch_info = &priv->channel_info[i];
1705                 a_band = is_channel_a_band(ch_info);
1706
1707                 /* find minimum power of all user and regulatory constraints
1708                  *    (does not consider h/w clipping limitations) */
1709                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1710                 max_power = min(power, max_power);
1711                 if (max_power != ch_info->curr_txpow) {
1712                         ch_info->curr_txpow = max_power;
1713
1714                         /* this considers the h/w clipping limitations */
1715                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1716                 }
1717         }
1718
1719         /* update txpower settings for all channels,
1720          *   send to NIC if associated. */
1721         is_temp_calib_needed(priv);
1722         iwl3945_hw_reg_comp_txpower_temp(priv);
1723
1724         return 0;
1725 }
1726
1727 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv,
1728                                    struct iwl_rxon_context *ctx)
1729 {
1730         int rc = 0;
1731         struct iwl_rx_packet *pkt;
1732         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1733         struct iwl_host_cmd cmd = {
1734                 .id = REPLY_RXON_ASSOC,
1735                 .len = sizeof(rxon_assoc),
1736                 .flags = CMD_WANT_SKB,
1737                 .data = &rxon_assoc,
1738         };
1739         const struct iwl_rxon_cmd *rxon1 = &ctx->staging;
1740         const struct iwl_rxon_cmd *rxon2 = &ctx->active;
1741
1742         if ((rxon1->flags == rxon2->flags) &&
1743             (rxon1->filter_flags == rxon2->filter_flags) &&
1744             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1745             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1746                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1747                 return 0;
1748         }
1749
1750         rxon_assoc.flags = ctx->staging.flags;
1751         rxon_assoc.filter_flags = ctx->staging.filter_flags;
1752         rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1753         rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1754         rxon_assoc.reserved = 0;
1755
1756         rc = iwl_send_cmd_sync(priv, &cmd);
1757         if (rc)
1758                 return rc;
1759
1760         pkt = (struct iwl_rx_packet *)cmd.reply_page;
1761         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1762                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1763                 rc = -EIO;
1764         }
1765
1766         iwl_free_pages(priv, cmd.reply_page);
1767
1768         return rc;
1769 }
1770
1771 /**
1772  * iwl3945_commit_rxon - commit staging_rxon to hardware
1773  *
1774  * The RXON command in staging_rxon is committed to the hardware and
1775  * the active_rxon structure is updated with the new data.  This
1776  * function correctly transitions out of the RXON_ASSOC_MSK state if
1777  * a HW tune is required based on the RXON structure changes.
1778  */
1779 int iwl3945_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
1780 {
1781         /* cast away the const for active_rxon in this function */
1782         struct iwl3945_rxon_cmd *active_rxon = (void *)&ctx->active;
1783         struct iwl3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
1784         int rc = 0;
1785         bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1786
1787         if (!iwl_is_alive(priv))
1788                 return -1;
1789
1790         /* always get timestamp with Rx frame */
1791         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1792
1793         /* select antenna */
1794         staging_rxon->flags &=
1795             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1796         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1797
1798         rc = iwl_check_rxon_cmd(priv, ctx);
1799         if (rc) {
1800                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1801                 return -EINVAL;
1802         }
1803
1804         /* If we don't need to send a full RXON, we can use
1805          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1806          * and other flags for the current radio configuration. */
1807         if (!iwl_full_rxon_required(priv, &priv->contexts[IWL_RXON_CTX_BSS])) {
1808                 rc = iwl_send_rxon_assoc(priv,
1809                                          &priv->contexts[IWL_RXON_CTX_BSS]);
1810                 if (rc) {
1811                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1812                                   "configuration (%d).\n", rc);
1813                         return rc;
1814                 }
1815
1816                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1817
1818                 return 0;
1819         }
1820
1821         /* If we are currently associated and the new config requires
1822          * an RXON_ASSOC and the new config wants the associated mask enabled,
1823          * we must clear the associated from the active configuration
1824          * before we apply the new config */
1825         if (iwl_is_associated(priv, IWL_RXON_CTX_BSS) && new_assoc) {
1826                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1827                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1828
1829                 /*
1830                  * reserved4 and 5 could have been filled by the iwlcore code.
1831                  * Let's clear them before pushing to the 3945.
1832                  */
1833                 active_rxon->reserved4 = 0;
1834                 active_rxon->reserved5 = 0;
1835                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1836                                       sizeof(struct iwl3945_rxon_cmd),
1837                                       &priv->contexts[IWL_RXON_CTX_BSS].active);
1838
1839                 /* If the mask clearing failed then we set
1840                  * active_rxon back to what it was previously */
1841                 if (rc) {
1842                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1843                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1844                                   "configuration (%d).\n", rc);
1845                         return rc;
1846                 }
1847                 iwl_clear_ucode_stations(priv,
1848                                          &priv->contexts[IWL_RXON_CTX_BSS]);
1849                 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1850         }
1851
1852         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1853                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1854                        "* channel = %d\n"
1855                        "* bssid = %pM\n",
1856                        (new_assoc ? "" : "out"),
1857                        le16_to_cpu(staging_rxon->channel),
1858                        staging_rxon->bssid_addr);
1859
1860         /*
1861          * reserved4 and 5 could have been filled by the iwlcore code.
1862          * Let's clear them before pushing to the 3945.
1863          */
1864         staging_rxon->reserved4 = 0;
1865         staging_rxon->reserved5 = 0;
1866
1867         iwl_set_rxon_hwcrypto(priv, ctx, !iwl3945_mod_params.sw_crypto);
1868
1869         /* Apply the new configuration */
1870         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1871                               sizeof(struct iwl3945_rxon_cmd),
1872                               staging_rxon);
1873         if (rc) {
1874                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1875                 return rc;
1876         }
1877
1878         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1879
1880         if (!new_assoc) {
1881                 iwl_clear_ucode_stations(priv,
1882                                          &priv->contexts[IWL_RXON_CTX_BSS]);
1883                 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1884         }
1885
1886         /* If we issue a new RXON command which required a tune then we must
1887          * send a new TXPOWER command or we won't be able to Tx any frames */
1888         rc = priv->cfg->ops->lib->send_tx_power(priv);
1889         if (rc) {
1890                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1891                 return rc;
1892         }
1893
1894         /* Init the hardware's rate fallback order based on the band */
1895         rc = iwl3945_init_hw_rate_table(priv);
1896         if (rc) {
1897                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1898                 return -EIO;
1899         }
1900
1901         return 0;
1902 }
1903
1904 /**
1905  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1906  *
1907  * -- reset periodic timer
1908  * -- see if temp has changed enough to warrant re-calibration ... if so:
1909  *     -- correct coeffs for temp (can reset temp timer)
1910  *     -- save this temp as "last",
1911  *     -- send new set of gain settings to NIC
1912  * NOTE:  This should continue working, even when we're not associated,
1913  *   so we can keep our internal table of scan powers current. */
1914 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1915 {
1916         /* This will kick in the "brute force"
1917          * iwl3945_hw_reg_comp_txpower_temp() below */
1918         if (!is_temp_calib_needed(priv))
1919                 goto reschedule;
1920
1921         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1922          * This is based *only* on current temperature,
1923          * ignoring any previous power measurements */
1924         iwl3945_hw_reg_comp_txpower_temp(priv);
1925
1926  reschedule:
1927         queue_delayed_work(priv->workqueue,
1928                            &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1929 }
1930
1931 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1932 {
1933         struct iwl_priv *priv = container_of(work, struct iwl_priv,
1934                                              _3945.thermal_periodic.work);
1935
1936         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1937                 return;
1938
1939         mutex_lock(&priv->mutex);
1940         iwl3945_reg_txpower_periodic(priv);
1941         mutex_unlock(&priv->mutex);
1942 }
1943
1944 /**
1945  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1946  *                                 for the channel.
1947  *
1948  * This function is used when initializing channel-info structs.
1949  *
1950  * NOTE: These channel groups do *NOT* match the bands above!
1951  *       These channel groups are based on factory-tested channels;
1952  *       on A-band, EEPROM's "group frequency" entries represent the top
1953  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
1954  */
1955 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1956                                        const struct iwl_channel_info *ch_info)
1957 {
1958         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1959         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1960         u8 group;
1961         u16 group_index = 0;    /* based on factory calib frequencies */
1962         u8 grp_channel;
1963
1964         /* Find the group index for the channel ... don't use index 1(?) */
1965         if (is_channel_a_band(ch_info)) {
1966                 for (group = 1; group < 5; group++) {
1967                         grp_channel = ch_grp[group].group_channel;
1968                         if (ch_info->channel <= grp_channel) {
1969                                 group_index = group;
1970                                 break;
1971                         }
1972                 }
1973                 /* group 4 has a few channels *above* its factory cal freq */
1974                 if (group == 5)
1975                         group_index = 4;
1976         } else
1977                 group_index = 0;        /* 2.4 GHz, group 0 */
1978
1979         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1980                         group_index);
1981         return group_index;
1982 }
1983
1984 /**
1985  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1986  *
1987  * Interpolate to get nominal (i.e. at factory calibration temperature) index
1988  *   into radio/DSP gain settings table for requested power.
1989  */
1990 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1991                                        s8 requested_power,
1992                                        s32 setting_index, s32 *new_index)
1993 {
1994         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
1995         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1996         s32 index0, index1;
1997         s32 power = 2 * requested_power;
1998         s32 i;
1999         const struct iwl3945_eeprom_txpower_sample *samples;
2000         s32 gains0, gains1;
2001         s32 res;
2002         s32 denominator;
2003
2004         chnl_grp = &eeprom->groups[setting_index];
2005         samples = chnl_grp->samples;
2006         for (i = 0; i < 5; i++) {
2007                 if (power == samples[i].power) {
2008                         *new_index = samples[i].gain_index;
2009                         return 0;
2010                 }
2011         }
2012
2013         if (power > samples[1].power) {
2014                 index0 = 0;
2015                 index1 = 1;
2016         } else if (power > samples[2].power) {
2017                 index0 = 1;
2018                 index1 = 2;
2019         } else if (power > samples[3].power) {
2020                 index0 = 2;
2021                 index1 = 3;
2022         } else {
2023                 index0 = 3;
2024                 index1 = 4;
2025         }
2026
2027         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2028         if (denominator == 0)
2029                 return -EINVAL;
2030         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2031         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2032         res = gains0 + (gains1 - gains0) *
2033             ((s32) power - (s32) samples[index0].power) / denominator +
2034             (1 << 18);
2035         *new_index = res >> 19;
2036         return 0;
2037 }
2038
2039 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2040 {
2041         u32 i;
2042         s32 rate_index;
2043         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2044         const struct iwl3945_eeprom_txpower_group *group;
2045
2046         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2047
2048         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2049                 s8 *clip_pwrs;  /* table of power levels for each rate */
2050                 s8 satur_pwr;   /* saturation power for each chnl group */
2051                 group = &eeprom->groups[i];
2052
2053                 /* sanity check on factory saturation power value */
2054                 if (group->saturation_power < 40) {
2055                         IWL_WARN(priv, "Error: saturation power is %d, "
2056                                     "less than minimum expected 40\n",
2057                                     group->saturation_power);
2058                         return;
2059                 }
2060
2061                 /*
2062                  * Derive requested power levels for each rate, based on
2063                  *   hardware capabilities (saturation power for band).
2064                  * Basic value is 3dB down from saturation, with further
2065                  *   power reductions for highest 3 data rates.  These
2066                  *   backoffs provide headroom for high rate modulation
2067                  *   power peaks, without too much distortion (clipping).
2068                  */
2069                 /* we'll fill in this array with h/w max power levels */
2070                 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2071
2072                 /* divide factory saturation power by 2 to find -3dB level */
2073                 satur_pwr = (s8) (group->saturation_power >> 1);
2074
2075                 /* fill in channel group's nominal powers for each rate */
2076                 for (rate_index = 0;
2077                      rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2078                         switch (rate_index) {
2079                         case IWL_RATE_36M_INDEX_TABLE:
2080                                 if (i == 0)     /* B/G */
2081                                         *clip_pwrs = satur_pwr;
2082                                 else    /* A */
2083                                         *clip_pwrs = satur_pwr - 5;
2084                                 break;
2085                         case IWL_RATE_48M_INDEX_TABLE:
2086                                 if (i == 0)
2087                                         *clip_pwrs = satur_pwr - 7;
2088                                 else
2089                                         *clip_pwrs = satur_pwr - 10;
2090                                 break;
2091                         case IWL_RATE_54M_INDEX_TABLE:
2092                                 if (i == 0)
2093                                         *clip_pwrs = satur_pwr - 9;
2094                                 else
2095                                         *clip_pwrs = satur_pwr - 12;
2096                                 break;
2097                         default:
2098                                 *clip_pwrs = satur_pwr;
2099                                 break;
2100                         }
2101                 }
2102         }
2103 }
2104
2105 /**
2106  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2107  *
2108  * Second pass (during init) to set up priv->channel_info
2109  *
2110  * Set up Tx-power settings in our channel info database for each VALID
2111  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2112  * and current temperature.
2113  *
2114  * Since this is based on current temperature (at init time), these values may
2115  * not be valid for very long, but it gives us a starting/default point,
2116  * and allows us to active (i.e. using Tx) scan.
2117  *
2118  * This does *not* write values to NIC, just sets up our internal table.
2119  */
2120 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2121 {
2122         struct iwl_channel_info *ch_info = NULL;
2123         struct iwl3945_channel_power_info *pwr_info;
2124         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2125         int delta_index;
2126         u8 rate_index;
2127         u8 scan_tbl_index;
2128         const s8 *clip_pwrs;    /* array of power levels for each rate */
2129         u8 gain, dsp_atten;
2130         s8 power;
2131         u8 pwr_index, base_pwr_index, a_band;
2132         u8 i;
2133         int temperature;
2134
2135         /* save temperature reference,
2136          *   so we can determine next time to calibrate */
2137         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2138         priv->last_temperature = temperature;
2139
2140         iwl3945_hw_reg_init_channel_groups(priv);
2141
2142         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2143         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2144              i++, ch_info++) {
2145                 a_band = is_channel_a_band(ch_info);
2146                 if (!is_channel_valid(ch_info))
2147                         continue;
2148
2149                 /* find this channel's channel group (*not* "band") index */
2150                 ch_info->group_index =
2151                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2152
2153                 /* Get this chnlgrp's rate->max/clip-powers table */
2154                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2155
2156                 /* calculate power index *adjustment* value according to
2157                  *  diff between current temperature and factory temperature */
2158                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2159                                 eeprom->groups[ch_info->group_index].
2160                                 temperature);
2161
2162                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2163                                 ch_info->channel, delta_index, temperature +
2164                                 IWL_TEMP_CONVERT);
2165
2166                 /* set tx power value for all OFDM rates */
2167                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2168                      rate_index++) {
2169                         s32 uninitialized_var(power_idx);
2170                         int rc;
2171
2172                         /* use channel group's clip-power table,
2173                          *   but don't exceed channel's max power */
2174                         s8 pwr = min(ch_info->max_power_avg,
2175                                      clip_pwrs[rate_index]);
2176
2177                         pwr_info = &ch_info->power_info[rate_index];
2178
2179                         /* get base (i.e. at factory-measured temperature)
2180                          *    power table index for this rate's power */
2181                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2182                                                          ch_info->group_index,
2183                                                          &power_idx);
2184                         if (rc) {
2185                                 IWL_ERR(priv, "Invalid power index\n");
2186                                 return rc;
2187                         }
2188                         pwr_info->base_power_index = (u8) power_idx;
2189
2190                         /* temperature compensate */
2191                         power_idx += delta_index;
2192
2193                         /* stay within range of gain table */
2194                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2195
2196                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2197                         pwr_info->requested_power = pwr;
2198                         pwr_info->power_table_index = (u8) power_idx;
2199                         pwr_info->tpc.tx_gain =
2200                             power_gain_table[a_band][power_idx].tx_gain;
2201                         pwr_info->tpc.dsp_atten =
2202                             power_gain_table[a_band][power_idx].dsp_atten;
2203                 }
2204
2205                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2206                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2207                 power = pwr_info->requested_power +
2208                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2209                 pwr_index = pwr_info->power_table_index +
2210                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2211                 base_pwr_index = pwr_info->base_power_index +
2212                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2213
2214                 /* stay within table range */
2215                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2216                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2217                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2218
2219                 /* fill each CCK rate's iwl3945_channel_power_info structure
2220                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2221                  * NOTE:  CCK rates start at end of OFDM rates! */
2222                 for (rate_index = 0;
2223                      rate_index < IWL_CCK_RATES; rate_index++) {
2224                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2225                         pwr_info->requested_power = power;
2226                         pwr_info->power_table_index = pwr_index;
2227                         pwr_info->base_power_index = base_pwr_index;
2228                         pwr_info->tpc.tx_gain = gain;
2229                         pwr_info->tpc.dsp_atten = dsp_atten;
2230                 }
2231
2232                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2233                 for (scan_tbl_index = 0;
2234                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2235                         s32 actual_index = (scan_tbl_index == 0) ?
2236                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2237                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2238                                 actual_index, clip_pwrs, ch_info, a_band);
2239                 }
2240         }
2241
2242         return 0;
2243 }
2244
2245 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2246 {
2247         int rc;
2248
2249         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2250         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2251                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2252         if (rc < 0)
2253                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2254
2255         return 0;
2256 }
2257
2258 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2259 {
2260         int txq_id = txq->q.id;
2261
2262         struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2263
2264         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2265
2266         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2267         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2268
2269         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2270                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2271                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2272                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2273                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2274                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2275
2276         /* fake read to flush all prev. writes */
2277         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2278
2279         return 0;
2280 }
2281
2282 /*
2283  * HCMD utils
2284  */
2285 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2286 {
2287         switch (cmd_id) {
2288         case REPLY_RXON:
2289                 return sizeof(struct iwl3945_rxon_cmd);
2290         case POWER_TABLE_CMD:
2291                 return sizeof(struct iwl3945_powertable_cmd);
2292         default:
2293                 return len;
2294         }
2295 }
2296
2297
2298 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2299 {
2300         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2301         addsta->mode = cmd->mode;
2302         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2303         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2304         addsta->station_flags = cmd->station_flags;
2305         addsta->station_flags_msk = cmd->station_flags_msk;
2306         addsta->tid_disable_tx = cpu_to_le16(0);
2307         addsta->rate_n_flags = cmd->rate_n_flags;
2308         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2309         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2310         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2311
2312         return (u16)sizeof(struct iwl3945_addsta_cmd);
2313 }
2314
2315 static int iwl3945_add_bssid_station(struct iwl_priv *priv,
2316                                      const u8 *addr, u8 *sta_id_r)
2317 {
2318         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2319         int ret;
2320         u8 sta_id;
2321         unsigned long flags;
2322
2323         if (sta_id_r)
2324                 *sta_id_r = IWL_INVALID_STATION;
2325
2326         ret = iwl_add_station_common(priv, ctx, addr, 0, NULL, &sta_id);
2327         if (ret) {
2328                 IWL_ERR(priv, "Unable to add station %pM\n", addr);
2329                 return ret;
2330         }
2331
2332         if (sta_id_r)
2333                 *sta_id_r = sta_id;
2334
2335         spin_lock_irqsave(&priv->sta_lock, flags);
2336         priv->stations[sta_id].used |= IWL_STA_LOCAL;
2337         spin_unlock_irqrestore(&priv->sta_lock, flags);
2338
2339         return 0;
2340 }
2341 static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2342                                        struct ieee80211_vif *vif, bool add)
2343 {
2344         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2345         int ret;
2346
2347         if (add) {
2348                 ret = iwl3945_add_bssid_station(priv, vif->bss_conf.bssid,
2349                                                 &vif_priv->ibss_bssid_sta_id);
2350                 if (ret)
2351                         return ret;
2352
2353                 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
2354                                  (priv->band == IEEE80211_BAND_5GHZ) ?
2355                                  IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
2356                 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
2357
2358                 return 0;
2359         }
2360
2361         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2362                                   vif->bss_conf.bssid);
2363 }
2364
2365 /**
2366  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2367  */
2368 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2369 {
2370         int rc, i, index, prev_index;
2371         struct iwl3945_rate_scaling_cmd rate_cmd = {
2372                 .reserved = {0, 0, 0},
2373         };
2374         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2375
2376         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2377                 index = iwl3945_rates[i].table_rs_index;
2378
2379                 table[index].rate_n_flags =
2380                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2381                 table[index].try_cnt = priv->retry_rate;
2382                 prev_index = iwl3945_get_prev_ieee_rate(i);
2383                 table[index].next_rate_index =
2384                                 iwl3945_rates[prev_index].table_rs_index;
2385         }
2386
2387         switch (priv->band) {
2388         case IEEE80211_BAND_5GHZ:
2389                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2390                 /* If one of the following CCK rates is used,
2391                  * have it fall back to the 6M OFDM rate */
2392                 for (i = IWL_RATE_1M_INDEX_TABLE;
2393                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2394                         table[i].next_rate_index =
2395                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2396
2397                 /* Don't fall back to CCK rates */
2398                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2399                                                 IWL_RATE_9M_INDEX_TABLE;
2400
2401                 /* Don't drop out of OFDM rates */
2402                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2403                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2404                 break;
2405
2406         case IEEE80211_BAND_2GHZ:
2407                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2408                 /* If an OFDM rate is used, have it fall back to the
2409                  * 1M CCK rates */
2410
2411                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2412                     iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
2413
2414                         index = IWL_FIRST_CCK_RATE;
2415                         for (i = IWL_RATE_6M_INDEX_TABLE;
2416                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2417                                 table[i].next_rate_index =
2418                                         iwl3945_rates[index].table_rs_index;
2419
2420                         index = IWL_RATE_11M_INDEX_TABLE;
2421                         /* CCK shouldn't fall back to OFDM... */
2422                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2423                 }
2424                 break;
2425
2426         default:
2427                 WARN_ON(1);
2428                 break;
2429         }
2430
2431         /* Update the rate scaling for control frame Tx */
2432         rate_cmd.table_id = 0;
2433         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2434                               &rate_cmd);
2435         if (rc)
2436                 return rc;
2437
2438         /* Update the rate scaling for data frame Tx */
2439         rate_cmd.table_id = 1;
2440         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2441                                 &rate_cmd);
2442 }
2443
2444 /* Called when initializing driver */
2445 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2446 {
2447         memset((void *)&priv->hw_params, 0,
2448                sizeof(struct iwl_hw_params));
2449
2450         priv->_3945.shared_virt =
2451                 dma_alloc_coherent(&priv->pci_dev->dev,
2452                                    sizeof(struct iwl3945_shared),
2453                                    &priv->_3945.shared_phys, GFP_KERNEL);
2454         if (!priv->_3945.shared_virt) {
2455                 IWL_ERR(priv, "failed to allocate pci memory\n");
2456                 return -ENOMEM;
2457         }
2458
2459         /* Assign number of Usable TX queues */
2460         priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
2461
2462         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2463         priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2464         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2465         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2466         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2467         priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id = IWL3945_BROADCAST_ID;
2468
2469         priv->sta_key_max_num = STA_KEY_MAX_NUM;
2470
2471         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2472         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2473         priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
2474
2475         return 0;
2476 }
2477
2478 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2479                           struct iwl3945_frame *frame, u8 rate)
2480 {
2481         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2482         unsigned int frame_size;
2483
2484         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2485         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2486
2487         tx_beacon_cmd->tx.sta_id =
2488                 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
2489         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2490
2491         frame_size = iwl3945_fill_beacon_frame(priv,
2492                                 tx_beacon_cmd->frame,
2493                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2494
2495         BUG_ON(frame_size > MAX_MPDU_SIZE);
2496         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2497
2498         tx_beacon_cmd->tx.rate = rate;
2499         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2500                                       TX_CMD_FLG_TSF_MSK);
2501
2502         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2503         tx_beacon_cmd->tx.supp_rates[0] =
2504                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2505
2506         tx_beacon_cmd->tx.supp_rates[1] =
2507                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2508
2509         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2510 }
2511
2512 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2513 {
2514         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2515         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2516 }
2517
2518 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2519 {
2520         INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2521                           iwl3945_bg_reg_txpower_periodic);
2522 }
2523
2524 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2525 {
2526         cancel_delayed_work(&priv->_3945.thermal_periodic);
2527 }
2528
2529 /* check contents of special bootstrap uCode SRAM */
2530 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2531  {
2532         __le32 *image = priv->ucode_boot.v_addr;
2533         u32 len = priv->ucode_boot.len;
2534         u32 reg;
2535         u32 val;
2536
2537         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2538
2539         /* verify BSM SRAM contents */
2540         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2541         for (reg = BSM_SRAM_LOWER_BOUND;
2542              reg < BSM_SRAM_LOWER_BOUND + len;
2543              reg += sizeof(u32), image++) {
2544                 val = iwl_read_prph(priv, reg);
2545                 if (val != le32_to_cpu(*image)) {
2546                         IWL_ERR(priv, "BSM uCode verification failed at "
2547                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2548                                   BSM_SRAM_LOWER_BOUND,
2549                                   reg - BSM_SRAM_LOWER_BOUND, len,
2550                                   val, le32_to_cpu(*image));
2551                         return -EIO;
2552                 }
2553         }
2554
2555         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2556
2557         return 0;
2558 }
2559
2560
2561 /******************************************************************************
2562  *
2563  * EEPROM related functions
2564  *
2565  ******************************************************************************/
2566
2567 /*
2568  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2569  * embedded controller) as EEPROM reader; each read is a series of pulses
2570  * to/from the EEPROM chip, not a single event, so even reads could conflict
2571  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2572  * simply claims ownership, which should be safe when this function is called
2573  * (i.e. before loading uCode!).
2574  */
2575 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2576 {
2577         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2578         return 0;
2579 }
2580
2581
2582 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2583 {
2584         return;
2585 }
2586
2587  /**
2588   * iwl3945_load_bsm - Load bootstrap instructions
2589   *
2590   * BSM operation:
2591   *
2592   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2593   * in special SRAM that does not power down during RFKILL.  When powering back
2594   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2595   * the bootstrap program into the on-board processor, and starts it.
2596   *
2597   * The bootstrap program loads (via DMA) instructions and data for a new
2598   * program from host DRAM locations indicated by the host driver in the
2599   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2600   * automatically.
2601   *
2602   * When initializing the NIC, the host driver points the BSM to the
2603   * "initialize" uCode image.  This uCode sets up some internal data, then
2604   * notifies host via "initialize alive" that it is complete.
2605   *
2606   * The host then replaces the BSM_DRAM_* pointer values to point to the
2607   * normal runtime uCode instructions and a backup uCode data cache buffer
2608   * (filled initially with starting data values for the on-board processor),
2609   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2610   * which begins normal operation.
2611   *
2612   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2613   * the backup data cache in DRAM before SRAM is powered down.
2614   *
2615   * When powering back up, the BSM loads the bootstrap program.  This reloads
2616   * the runtime uCode instructions and the backup data cache into SRAM,
2617   * and re-launches the runtime uCode from where it left off.
2618   */
2619 static int iwl3945_load_bsm(struct iwl_priv *priv)
2620 {
2621         __le32 *image = priv->ucode_boot.v_addr;
2622         u32 len = priv->ucode_boot.len;
2623         dma_addr_t pinst;
2624         dma_addr_t pdata;
2625         u32 inst_len;
2626         u32 data_len;
2627         int rc;
2628         int i;
2629         u32 done;
2630         u32 reg_offset;
2631
2632         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2633
2634         /* make sure bootstrap program is no larger than BSM's SRAM size */
2635         if (len > IWL39_MAX_BSM_SIZE)
2636                 return -EINVAL;
2637
2638         /* Tell bootstrap uCode where to find the "Initialize" uCode
2639         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2640         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2641         *        after the "initialize" uCode has run, to point to
2642         *        runtime/protocol instructions and backup data cache. */
2643         pinst = priv->ucode_init.p_addr;
2644         pdata = priv->ucode_init_data.p_addr;
2645         inst_len = priv->ucode_init.len;
2646         data_len = priv->ucode_init_data.len;
2647
2648         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2649         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2650         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2651         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2652
2653         /* Fill BSM memory with bootstrap instructions */
2654         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2655              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2656              reg_offset += sizeof(u32), image++)
2657                 _iwl_write_prph(priv, reg_offset,
2658                                           le32_to_cpu(*image));
2659
2660         rc = iwl3945_verify_bsm(priv);
2661         if (rc)
2662                 return rc;
2663
2664         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2665         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2666         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2667                                  IWL39_RTC_INST_LOWER_BOUND);
2668         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2669
2670         /* Load bootstrap code into instruction SRAM now,
2671          *   to prepare to load "initialize" uCode */
2672         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2673                 BSM_WR_CTRL_REG_BIT_START);
2674
2675         /* Wait for load of bootstrap uCode to finish */
2676         for (i = 0; i < 100; i++) {
2677                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2678                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2679                         break;
2680                 udelay(10);
2681         }
2682         if (i < 100)
2683                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2684         else {
2685                 IWL_ERR(priv, "BSM write did not complete!\n");
2686                 return -EIO;
2687         }
2688
2689         /* Enable future boot loads whenever power management unit triggers it
2690          *   (e.g. when powering back up after power-save shutdown) */
2691         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2692                 BSM_WR_CTRL_REG_BIT_START_EN);
2693
2694         return 0;
2695 }
2696
2697 static struct iwl_hcmd_ops iwl3945_hcmd = {
2698         .rxon_assoc = iwl3945_send_rxon_assoc,
2699         .commit_rxon = iwl3945_commit_rxon,
2700         .send_bt_config = iwl_send_bt_config,
2701 };
2702
2703 static struct iwl_lib_ops iwl3945_lib = {
2704         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2705         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2706         .txq_init = iwl3945_hw_tx_queue_init,
2707         .load_ucode = iwl3945_load_bsm,
2708         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2709         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2710         .apm_ops = {
2711                 .init = iwl3945_apm_init,
2712                 .config = iwl3945_nic_config,
2713         },
2714         .eeprom_ops = {
2715                 .regulatory_bands = {
2716                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2717                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2718                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2719                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2720                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2721                         EEPROM_REGULATORY_BAND_NO_HT40,
2722                         EEPROM_REGULATORY_BAND_NO_HT40,
2723                 },
2724                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2725                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2726                 .query_addr = iwlcore_eeprom_query_addr,
2727         },
2728         .send_tx_power  = iwl3945_send_tx_power,
2729         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2730         .isr_ops = {
2731                 .isr = iwl_isr_legacy,
2732         },
2733         .recover_from_tx_stall = iwl_bg_monitor_recover,
2734         .check_plcp_health = iwl3945_good_plcp_health,
2735
2736         .debugfs_ops = {
2737                 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2738                 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2739                 .general_stats_read = iwl3945_ucode_general_stats_read,
2740         },
2741 };
2742
2743 static const struct iwl_legacy_ops iwl3945_legacy_ops = {
2744         .post_associate = iwl3945_post_associate,
2745         .config_ap = iwl3945_config_ap,
2746         .manage_ibss_station = iwl3945_manage_ibss_station,
2747 };
2748
2749 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2750         .get_hcmd_size = iwl3945_get_hcmd_size,
2751         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2752         .tx_cmd_protection = iwl_legacy_tx_cmd_protection,
2753         .request_scan = iwl3945_request_scan,
2754         .post_scan = iwl3945_post_scan,
2755 };
2756
2757 static const struct iwl_ops iwl3945_ops = {
2758         .lib = &iwl3945_lib,
2759         .hcmd = &iwl3945_hcmd,
2760         .utils = &iwl3945_hcmd_utils,
2761         .led = &iwl3945_led_ops,
2762         .legacy = &iwl3945_legacy_ops,
2763         .ieee80211_ops = &iwl3945_hw_ops,
2764 };
2765
2766 static struct iwl_base_params iwl3945_base_params = {
2767         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2768         .num_of_queues = IWL39_NUM_QUEUES,
2769         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2770         .set_l0s = false,
2771         .use_bsm = true,
2772         .use_isr_legacy = true,
2773         .led_compensation = 64,
2774         .broken_powersave = true,
2775         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2776         .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
2777         .max_event_log_size = 512,
2778         .tx_power_by_driver = true,
2779 };
2780
2781 static struct iwl_cfg iwl3945_bg_cfg = {
2782         .name = "3945BG",
2783         .fw_name_pre = IWL3945_FW_PRE,
2784         .ucode_api_max = IWL3945_UCODE_API_MAX,
2785         .ucode_api_min = IWL3945_UCODE_API_MIN,
2786         .sku = IWL_SKU_G,
2787         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2788         .ops = &iwl3945_ops,
2789         .mod_params = &iwl3945_mod_params,
2790         .base_params = &iwl3945_base_params,
2791         .led_mode = IWL_LED_BLINK,
2792 };
2793
2794 static struct iwl_cfg iwl3945_abg_cfg = {
2795         .name = "3945ABG",
2796         .fw_name_pre = IWL3945_FW_PRE,
2797         .ucode_api_max = IWL3945_UCODE_API_MAX,
2798         .ucode_api_min = IWL3945_UCODE_API_MIN,
2799         .sku = IWL_SKU_A|IWL_SKU_G,
2800         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2801         .ops = &iwl3945_ops,
2802         .mod_params = &iwl3945_mod_params,
2803         .base_params = &iwl3945_base_params,
2804         .led_mode = IWL_LED_BLINK,
2805 };
2806
2807 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2808         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2809         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2810         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2811         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2812         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2813         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2814         {0}
2815 };
2816
2817 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);