drivers/net/wireless/bcm43xx/bcm43xx_main.c

   1 /*
   2
   3   Broadcom BCM43xx wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   6                      Stefano Brivio <st3@riseup.net>
   7                      Michael Buesch <mbuesch@freenet.de>
   8                      Danny van Dyk <kugelfang@gentoo.org>
   9                      Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <net/iw_handler.h>
  43
  44 #include "bcm43xx.h"
  45 #include "bcm43xx_main.h"
  46 #include "bcm43xx_debugfs.h"
  47 #include "bcm43xx_radio.h"
  48 #include "bcm43xx_phy.h"
  49 #include "bcm43xx_dma.h"
  50 #include "bcm43xx_pio.h"
  51 #include "bcm43xx_power.h"
  52 #include "bcm43xx_wx.h"
  53 #include "bcm43xx_ethtool.h"
  54 #include "bcm43xx_xmit.h"
  55 #include "bcm43xx_sysfs.h"
  56
  57
  58 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
  59 MODULE_AUTHOR("Martin Langer");
  60 MODULE_AUTHOR("Stefano Brivio");
  61 MODULE_AUTHOR("Michael Buesch");
  62 MODULE_LICENSE("GPL");
  63
  64 #ifdef CONFIG_BCM947XX
  65 extern char *nvram_get(char *name);
  66 #endif
  67
  68 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
  69 static int modparam_pio;
  70 module_param_named(pio, modparam_pio, int, 0444);
  71 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  72 #elif defined(CONFIG_BCM43XX_DMA)
  73 # define modparam_pio   0
  74 #elif defined(CONFIG_BCM43XX_PIO)
  75 # define modparam_pio   1
  76 #endif
  77
  78 static int modparam_bad_frames_preempt;
  79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  80 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
  81
  82 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
  83 module_param_named(short_retry, modparam_short_retry, int, 0444);
  84 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
  85
  86 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
  87 module_param_named(long_retry, modparam_long_retry, int, 0444);
  88 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
  89
  90 static int modparam_locale = -1;
  91 module_param_named(locale, modparam_locale, int, 0444);
  92 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
  93
  94 static int modparam_noleds;
  95 module_param_named(noleds, modparam_noleds, int, 0444);
  96 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
  97
  98 static char modparam_fwpostfix[64];
  99 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
 100 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for using multiple firmware image versions.");
 101
 102
 103 /* If you want to debug with just a single device, enable this,
 104  * where the string is the pci device ID (as given by the kernel's
 105  * pci_name function) of the device to be used.
 106  */
 107 //#define DEBUG_SINGLE_DEVICE_ONLY      "0001:11:00.0"
 108
 109 /* If you want to enable printing of each MMIO access, enable this. */
 110 //#define DEBUG_ENABLE_MMIO_PRINT
 111
 112 /* If you want to enable printing of MMIO access within
 113  * ucode/pcm upload, initvals write, enable this.
 114  */
 115 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
 116
 117 /* If you want to enable printing of PCI Config Space access, enable this */
 118 //#define DEBUG_ENABLE_PCILOG
 119
 120
 121 /* Detailed list maintained at:
 122  * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
 123  */
 124         static struct pci_device_id bcm43xx_pci_tbl[] = {
 125         /* Broadcom 4303 802.11b */
 126         { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 127         /* Broadcom 4307 802.11b */
 128         { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 129         /* Broadcom 4311 802.11(a)/b/g */
 130         { PCI_VENDOR_ID_BROADCOM, 0x4311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 131         /* Broadcom 4312 802.11a/b/g */
 132         { PCI_VENDOR_ID_BROADCOM, 0x4312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 133         /* Broadcom 4318 802.11b/g */
 134         { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 135         /* Broadcom 4319 802.11a/b/g */
 136         { PCI_VENDOR_ID_BROADCOM, 0x4319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 137         /* Broadcom 4306 802.11b/g */
 138         { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 139         /* Broadcom 4306 802.11a */
 140 //      { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 141         /* Broadcom 4309 802.11a/b/g */
 142         { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 143         /* Broadcom 43XG 802.11b/g */
 144         { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 145 #ifdef CONFIG_BCM947XX
 146         /* SB bus on BCM947xx */
 147         { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 148 #endif
 149         { 0 },
 150 };
 151 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
 152
 153 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
 154 {
 155         u32 status;
 156
 157         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
 158         if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
 159                 val = swab32(val);
 160
 161         bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
 162         mmiowb();
 163         bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
 164 }
 165
 166 static inline
 167 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
 168                               u16 routing, u16 offset)
 169 {
 170         u32 control;
 171
 172         /* "offset" is the WORD offset. */
 173
 174         control = routing;
 175         control <<= 16;
 176         control |= offset;
 177         bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
 178 }
 179
 180 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
 181                        u16 routing, u16 offset)
 182 {
 183         u32 ret;
 184
 185         if (routing == BCM43xx_SHM_SHARED) {
 186                 if (offset & 0x0003) {
 187                         /* Unaligned access */
 188                         bcm43xx_shm_control_word(bcm, routing, offset >> 2);
 189                         ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
 190                         ret <<= 16;
 191                         bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
 192                         ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
 193
 194                         return ret;
 195                 }
 196                 offset >>= 2;
 197         }
 198         bcm43xx_shm_control_word(bcm, routing, offset);
 199         ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
 200
 201         return ret;
 202 }
 203
 204 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
 205                        u16 routing, u16 offset)
 206 {
 207         u16 ret;
 208
 209         if (routing == BCM43xx_SHM_SHARED) {
 210                 if (offset & 0x0003) {
 211                         /* Unaligned access */
 212                         bcm43xx_shm_control_word(bcm, routing, offset >> 2);
 213                         ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
 214
 215                         return ret;
 216                 }
 217                 offset >>= 2;
 218         }
 219         bcm43xx_shm_control_word(bcm, routing, offset);
 220         ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
 221
 222         return ret;
 223 }
 224
 225 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
 226                          u16 routing, u16 offset,
 227                          u32 value)
 228 {
 229         if (routing == BCM43xx_SHM_SHARED) {
 230                 if (offset & 0x0003) {
 231                         /* Unaligned access */
 232                         bcm43xx_shm_control_word(bcm, routing, offset >> 2);
 233                         mmiowb();
 234                         bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
 235                                         (value >> 16) & 0xffff);
 236                         mmiowb();
 237                         bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
 238                         mmiowb();
 239                         bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
 240                                         value & 0xffff);
 241                         return;
 242                 }
 243                 offset >>= 2;
 244         }
 245         bcm43xx_shm_control_word(bcm, routing, offset);
 246         mmiowb();
 247         bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
 248 }
 249
 250 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
 251                          u16 routing, u16 offset,
 252                          u16 value)
 253 {
 254         if (routing == BCM43xx_SHM_SHARED) {
 255                 if (offset & 0x0003) {
 256                         /* Unaligned access */
 257                         bcm43xx_shm_control_word(bcm, routing, offset >> 2);
 258                         mmiowb();
 259                         bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
 260                                         value);
 261                         return;
 262                 }
 263                 offset >>= 2;
 264         }
 265         bcm43xx_shm_control_word(bcm, routing, offset);
 266         mmiowb();
 267         bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
 268 }
 269
 270 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
 271 {
 272         /* We need to be careful. As we read the TSF from multiple
 273          * registers, we should take care of register overflows.
 274          * In theory, the whole tsf read process should be atomic.
 275          * We try to be atomic here, by restaring the read process,
 276          * if any of the high registers changed (overflew).
 277          */
 278         if (bcm->current_core->rev >= 3) {
 279                 u32 low, high, high2;
 280
 281                 do {
 282                         high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
 283                         low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
 284                         high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
 285                 } while (unlikely(high != high2));
 286
 287                 *tsf = high;
 288                 *tsf <<= 32;
 289                 *tsf |= low;
 290         } else {
 291                 u64 tmp;
 292                 u16 v0, v1, v2, v3;
 293                 u16 test1, test2, test3;
 294
 295                 do {
 296                         v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
 297                         v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
 298                         v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
 299                         v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
 300
 301                         test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
 302                         test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
 303                         test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
 304                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 305
 306                 *tsf = v3;
 307                 *tsf <<= 48;
 308                 tmp = v2;
 309                 tmp <<= 32;
 310                 *tsf |= tmp;
 311                 tmp = v1;
 312                 tmp <<= 16;
 313                 *tsf |= tmp;
 314                 *tsf |= v0;
 315         }
 316 }
 317
 318 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
 319 {
 320         u32 status;
 321
 322         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
 323         status |= BCM43xx_SBF_TIME_UPDATE;
 324         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
 325         mmiowb();
 326
 327         /* Be careful with the in-progress timer.
 328          * First zero out the low register, so we have a full
 329          * register-overflow duration to complete the operation.
 330          */
 331         if (bcm->current_core->rev >= 3) {
 332                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 333                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 334
 335                 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
 336                 mmiowb();
 337                 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
 338                 mmiowb();
 339                 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
 340         } else {
 341                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 342                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 343                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 344                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 345
 346                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
 347                 mmiowb();
 348                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
 349                 mmiowb();
 350                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
 351                 mmiowb();
 352                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
 353                 mmiowb();
 354                 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
 355         }
 356
 357         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
 358         status &= ~BCM43xx_SBF_TIME_UPDATE;
 359         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
 360 }
 361
 362 static
 363 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
 364                            u16 offset,
 365                            const u8 *mac)
 366 {
 367         u16 data;
 368
 369         offset |= 0x0020;
 370         bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
 371
 372         data = mac[0];
 373         data |= mac[1] << 8;
 374         bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
 375         data = mac[2];
 376         data |= mac[3] << 8;
 377         bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
 378         data = mac[4];
 379         data |= mac[5] << 8;
 380         bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
 381 }
 382
 383 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
 384                                     u16 offset)
 385 {
 386         const u8 zero_addr[ETH_ALEN] = { 0 };
 387
 388         bcm43xx_macfilter_set(bcm, offset, zero_addr);
 389 }
 390
 391 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
 392 {
 393         const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
 394         const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
 395         u8 mac_bssid[ETH_ALEN * 2];
 396         int i;
 397
 398         memcpy(mac_bssid, mac, ETH_ALEN);
 399         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 400
 401         /* Write our MAC address and BSSID to template ram */
 402         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
 403                 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
 404         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
 405                 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
 406         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
 407                 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
 408 }
 409
 410 //FIXME: Well, we should probably call them from somewhere.
 411 #if 0
 412 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
 413 {
 414         /* slot_time is in usec. */
 415         if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
 416                 return;
 417         bcm43xx_write16(bcm, 0x684, 510 + slot_time);
 418         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
 419 }
 420
 421 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
 422 {
 423         bcm43xx_set_slot_time(bcm, 9);
 424 }
 425
 426 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
 427 {
 428         bcm43xx_set_slot_time(bcm, 20);
 429 }
 430 #endif
 431
 432 /* FIXME: To get the MAC-filter working, we need to implement the
 433  *        following functions (and rename them :)
 434  */
 435 #if 0
 436 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
 437 {
 438         bcm43xx_mac_suspend(bcm);
 439         bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
 440
 441         bcm43xx_ram_write(bcm, 0x0026, 0x0000);
 442         bcm43xx_ram_write(bcm, 0x0028, 0x0000);
 443         bcm43xx_ram_write(bcm, 0x007E, 0x0000);
 444         bcm43xx_ram_write(bcm, 0x0080, 0x0000);
 445         bcm43xx_ram_write(bcm, 0x047E, 0x0000);
 446         bcm43xx_ram_write(bcm, 0x0480, 0x0000);
 447
 448         if (bcm->current_core->rev < 3) {
 449                 bcm43xx_write16(bcm, 0x0610, 0x8000);
 450                 bcm43xx_write16(bcm, 0x060E, 0x0000);
 451         } else
 452                 bcm43xx_write32(bcm, 0x0188, 0x80000000);
 453
 454         bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
 455
 456         if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
 457             ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
 458                 bcm43xx_short_slot_timing_enable(bcm);
 459
 460         bcm43xx_mac_enable(bcm);
 461 }
 462
 463 static void bcm43xx_associate(struct bcm43xx_private *bcm,
 464                               const u8 *mac)
 465 {
 466         memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
 467
 468         bcm43xx_mac_suspend(bcm);
 469         bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
 470         bcm43xx_write_mac_bssid_templates(bcm);
 471         bcm43xx_mac_enable(bcm);
 472 }
 473 #endif
 474
 475 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 476  * Returns the _previously_ enabled IRQ mask.
 477  */
 478 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
 479 {
 480         u32 old_mask;
 481
 482         old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
 483         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
 484
 485         return old_mask;
 486 }
 487
 488 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 489  * Returns the _previously_ enabled IRQ mask.
 490  */
 491 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
 492 {
 493         u32 old_mask;
 494
 495         old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
 496         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 497
 498         return old_mask;
 499 }
 500
 501 /* Synchronize IRQ top- and bottom-half.
 502  * IRQs must be masked before calling this.
 503  * This must not be called with the irq_lock held.
 504  */
 505 static void bcm43xx_synchronize_irq(struct bcm43xx_private *bcm)
 506 {
 507         synchronize_irq(bcm->irq);
 508         tasklet_disable(&bcm->isr_tasklet);
 509 }
 510
 511 /* Make sure we don't receive more data from the device. */
 512 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm)
 513 {
 514         unsigned long flags;
 515
 516         spin_lock_irqsave(&bcm->irq_lock, flags);
 517         if (unlikely(bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)) {
 518                 spin_unlock_irqrestore(&bcm->irq_lock, flags);
 519                 return -EBUSY;
 520         }
 521         bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
 522         bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK); /* flush */
 523         spin_unlock_irqrestore(&bcm->irq_lock, flags);
 524         bcm43xx_synchronize_irq(bcm);
 525
 526         return 0;
 527 }
 528
 529 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
 530 {
 531         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
 532         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
 533         u32 radio_id;
 534         u16 manufact;
 535         u16 version;
 536         u8 revision;
 537
 538         if (bcm->chip_id == 0x4317) {
 539                 if (bcm->chip_rev == 0x00)
 540                         radio_id = 0x3205017F;
 541                 else if (bcm->chip_rev == 0x01)
 542                         radio_id = 0x4205017F;
 543                 else
 544                         radio_id = 0x5205017F;
 545         } else {
 546                 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
 547                 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
 548                 radio_id <<= 16;
 549                 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
 550                 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
 551         }
 552
 553         manufact = (radio_id & 0x00000FFF);
 554         version = (radio_id & 0x0FFFF000) >> 12;
 555         revision = (radio_id & 0xF0000000) >> 28;
 556
 557         dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
 558                 radio_id, manufact, version, revision);
 559
 560         switch (phy->type) {
 561         case BCM43xx_PHYTYPE_A:
 562                 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
 563                         goto err_unsupported_radio;
 564                 break;
 565         case BCM43xx_PHYTYPE_B:
 566                 if ((version & 0xFFF0) != 0x2050)
 567                         goto err_unsupported_radio;
 568                 break;
 569         case BCM43xx_PHYTYPE_G:
 570                 if (version != 0x2050)
 571                         goto err_unsupported_radio;
 572                 break;
 573         }
 574
 575         radio->manufact = manufact;
 576         radio->version = version;
 577         radio->revision = revision;
 578
 579         if (phy->type == BCM43xx_PHYTYPE_A)
 580                 radio->txpower_desired = bcm->sprom.maxpower_aphy;
 581         else
 582                 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
 583
 584         return 0;
 585
 586 err_unsupported_radio:
 587         printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
 588         return -ENODEV;
 589 }
 590
 591 static const char * bcm43xx_locale_iso(u8 locale)
 592 {
 593         /* ISO 3166-1 country codes.
 594          * Note that there aren't ISO 3166-1 codes for
 595          * all or locales. (Not all locales are countries)
 596          */
 597         switch (locale) {
 598         case BCM43xx_LOCALE_WORLD:
 599         case BCM43xx_LOCALE_ALL:
 600                 return "XX";
 601         case BCM43xx_LOCALE_THAILAND:
 602                 return "TH";
 603         case BCM43xx_LOCALE_ISRAEL:
 604                 return "IL";
 605         case BCM43xx_LOCALE_JORDAN:
 606                 return "JO";
 607         case BCM43xx_LOCALE_CHINA:
 608                 return "CN";
 609         case BCM43xx_LOCALE_JAPAN:
 610         case BCM43xx_LOCALE_JAPAN_HIGH:
 611                 return "JP";
 612         case BCM43xx_LOCALE_USA_CANADA_ANZ:
 613         case BCM43xx_LOCALE_USA_LOW:
 614                 return "US";
 615         case BCM43xx_LOCALE_EUROPE:
 616                 return "EU";
 617         case BCM43xx_LOCALE_NONE:
 618                 return "  ";
 619         }
 620         assert(0);
 621         return "  ";
 622 }
 623
 624 static const char * bcm43xx_locale_string(u8 locale)
 625 {
 626         switch (locale) {
 627         case BCM43xx_LOCALE_WORLD:
 628                 return "World";
 629         case BCM43xx_LOCALE_THAILAND:
 630                 return "Thailand";
 631         case BCM43xx_LOCALE_ISRAEL:
 632                 return "Israel";
 633         case BCM43xx_LOCALE_JORDAN:
 634                 return "Jordan";
 635         case BCM43xx_LOCALE_CHINA:
 636                 return "China";
 637         case BCM43xx_LOCALE_JAPAN:
 638                 return "Japan";
 639         case BCM43xx_LOCALE_USA_CANADA_ANZ:
 640                 return "USA/Canada/ANZ";
 641         case BCM43xx_LOCALE_EUROPE:
 642                 return "Europe";
 643         case BCM43xx_LOCALE_USA_LOW:
 644                 return "USAlow";
 645         case BCM43xx_LOCALE_JAPAN_HIGH:
 646                 return "JapanHigh";
 647         case BCM43xx_LOCALE_ALL:
 648                 return "All";
 649         case BCM43xx_LOCALE_NONE:
 650                 return "None";
 651         }
 652         assert(0);
 653         return "";
 654 }
 655
 656 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
 657 {
 658         static const u8 t[] = {
 659                 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
 660                 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
 661                 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
 662                 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
 663                 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
 664                 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
 665                 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
 666                 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
 667                 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
 668                 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
 669                 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
 670                 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
 671                 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
 672                 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
 673                 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
 674                 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
 675                 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
 676                 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
 677                 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
 678                 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
 679                 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
 680                 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
 681                 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
 682                 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
 683                 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
 684                 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
 685                 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
 686                 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
 687                 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
 688                 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
 689                 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
 690                 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
 691         };
 692         return t[crc ^ data];
 693 }
 694
 695 static u8 bcm43xx_sprom_crc(const u16 *sprom)
 696 {
 697         int word;
 698         u8 crc = 0xFF;
 699
 700         for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
 701                 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
 702                 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
 703         }
 704         crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
 705         crc ^= 0xFF;
 706
 707         return crc;
 708 }
 709
 710 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
 711 {
 712         int i;
 713         u8 crc, expected_crc;
 714
 715         for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
 716                 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
 717         /* CRC-8 check. */
 718         crc = bcm43xx_sprom_crc(sprom);
 719         expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
 720         if (crc != expected_crc) {
 721                 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
 722                                         "(0x%02X, expected: 0x%02X)\n",
 723                        crc, expected_crc);
 724                 return -EINVAL;
 725         }
 726
 727         return 0;
 728 }
 729
 730 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
 731 {
 732         int i, err;
 733         u8 crc, expected_crc;
 734         u32 spromctl;
 735
 736         /* CRC-8 validation of the input data. */
 737         crc = bcm43xx_sprom_crc(sprom);
 738         expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
 739         if (crc != expected_crc) {
 740                 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
 741                 return -EINVAL;
 742         }
 743
 744         printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
 745         err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
 746         if (err)
 747                 goto err_ctlreg;
 748         spromctl |= 0x10; /* SPROM WRITE enable. */
 749         err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
 750         if (err)
 751                 goto err_ctlreg;
 752         /* We must burn lots of CPU cycles here, but that does not
 753          * really matter as one does not write the SPROM every other minute...
 754          */
 755         printk(KERN_INFO PFX "[ 0%%");
 756         mdelay(500);
 757         for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
 758                 if (i == 16)
 759                         printk("25%%");
 760                 else if (i == 32)
 761                         printk("50%%");
 762                 else if (i == 48)
 763                         printk("75%%");
 764                 else if (i % 2)
 765                         printk(".");
 766                 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
 767                 mmiowb();
 768                 mdelay(20);
 769         }
 770         spromctl &= ~0x10; /* SPROM WRITE enable. */
 771         err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
 772         if (err)
 773                 goto err_ctlreg;
 774         mdelay(500);
 775         printk("100%% ]\n");
 776         printk(KERN_INFO PFX "SPROM written.\n");
 777         bcm43xx_controller_restart(bcm, "SPROM update");
 778
 779         return 0;
 780 err_ctlreg:
 781         printk(KERN_ERR PFX "Could not access SPROM control register.\n");
 782         return -ENODEV;
 783 }
 784
 785 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
 786 {
 787         u16 value;
 788         u16 *sprom;
 789 #ifdef CONFIG_BCM947XX
 790         char *c;
 791 #endif
 792
 793         sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
 794                         GFP_KERNEL);
 795         if (!sprom) {
 796                 printk(KERN_ERR PFX "sprom_extract OOM\n");
 797                 return -ENOMEM;
 798         }
 799 #ifdef CONFIG_BCM947XX
 800         sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
 801         sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
 802
 803         if ((c = nvram_get("il0macaddr")) != NULL)
 804                 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
 805
 806         if ((c = nvram_get("et1macaddr")) != NULL)
 807                 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
 808
 809         sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
 810         sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
 811         sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
 812
 813         sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
 814         sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
 815         sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
 816
 817         sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
 818 #else
 819         bcm43xx_sprom_read(bcm, sprom);
 820 #endif
 821
 822         /* boardflags2 */
 823         value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
 824         bcm->sprom.boardflags2 = value;
 825
 826         /* il0macaddr */
 827         value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
 828         *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
 829         value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
 830         *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
 831         value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
 832         *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
 833
 834         /* et0macaddr */
 835         value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
 836         *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
 837         value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
 838         *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
 839         value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
 840         *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
 841
 842         /* et1macaddr */
 843         value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
 844         *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
 845         value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
 846         *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
 847         value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
 848         *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
 849
 850         /* ethernet phy settings */
 851         value = sprom[BCM43xx_SPROM_ETHPHY];
 852         bcm->sprom.et0phyaddr = (value & 0x001F);
 853         bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
 854
 855         /* boardrev, antennas, locale */
 856         value = sprom[BCM43xx_SPROM_BOARDREV];
 857         bcm->sprom.boardrev = (value & 0x00FF);
 858         bcm->sprom.locale = (value & 0x0F00) >> 8;
 859         bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
 860         bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
 861         if (modparam_locale != -1) {
 862                 if (modparam_locale >= 0 && modparam_locale <= 11) {
 863                         bcm->sprom.locale = modparam_locale;
 864                         printk(KERN_WARNING PFX "Operating with modified "
 865                                                 "LocaleCode %u (%s)\n",
 866                                bcm->sprom.locale,
 867                                bcm43xx_locale_string(bcm->sprom.locale));
 868                 } else {
 869                         printk(KERN_WARNING PFX "Module parameter \"locale\" "
 870                                                 "invalid value. (0 - 11)\n");
 871                 }
 872         }
 873
 874         /* pa0b* */
 875         value = sprom[BCM43xx_SPROM_PA0B0];
 876         bcm->sprom.pa0b0 = value;
 877         value = sprom[BCM43xx_SPROM_PA0B1];
 878         bcm->sprom.pa0b1 = value;
 879         value = sprom[BCM43xx_SPROM_PA0B2];
 880         bcm->sprom.pa0b2 = value;
 881
 882         /* wl0gpio* */
 883         value = sprom[BCM43xx_SPROM_WL0GPIO0];
 884         if (value == 0x0000)
 885                 value = 0xFFFF;
 886         bcm->sprom.wl0gpio0 = value & 0x00FF;
 887         bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
 888         value = sprom[BCM43xx_SPROM_WL0GPIO2];
 889         if (value == 0x0000)
 890                 value = 0xFFFF;
 891         bcm->sprom.wl0gpio2 = value & 0x00FF;
 892         bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
 893
 894         /* maxpower */
 895         value = sprom[BCM43xx_SPROM_MAXPWR];
 896         bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
 897         bcm->sprom.maxpower_bgphy = value & 0x00FF;
 898
 899         /* pa1b* */
 900         value = sprom[BCM43xx_SPROM_PA1B0];
 901         bcm->sprom.pa1b0 = value;
 902         value = sprom[BCM43xx_SPROM_PA1B1];
 903         bcm->sprom.pa1b1 = value;
 904         value = sprom[BCM43xx_SPROM_PA1B2];
 905         bcm->sprom.pa1b2 = value;
 906
 907         /* idle tssi target */
 908         value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
 909         bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
 910         bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
 911
 912         /* boardflags */
 913         value = sprom[BCM43xx_SPROM_BOARDFLAGS];
 914         if (value == 0xFFFF)
 915                 value = 0x0000;
 916         bcm->sprom.boardflags = value;
 917         /* boardflags workarounds */
 918         if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
 919             bcm->chip_id == 0x4301 &&
 920             bcm->board_revision == 0x74)
 921                 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
 922         if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
 923             bcm->board_type == 0x4E &&
 924             bcm->board_revision > 0x40)
 925                 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
 926
 927         /* antenna gain */
 928         value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
 929         if (value == 0x0000 || value == 0xFFFF)
 930                 value = 0x0202;
 931         /* convert values to Q5.2 */
 932         bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
 933         bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
 934
 935         kfree(sprom);
 936
 937         return 0;
 938 }
 939
 940 static int bcm43xx_geo_init(struct bcm43xx_private *bcm)
 941 {
 942         struct ieee80211_geo *geo;
 943         struct ieee80211_channel *chan;
 944         int have_a = 0, have_bg = 0;
 945         int i;
 946         u8 channel;
 947         struct bcm43xx_phyinfo *phy;
 948         const char *iso_country;
 949
 950         geo = kzalloc(sizeof(*geo), GFP_KERNEL);
 951         if (!geo)
 952                 return -ENOMEM;
 953
 954         for (i = 0; i < bcm->nr_80211_available; i++) {
 955                 phy = &(bcm->core_80211_ext[i].phy);
 956                 switch (phy->type) {
 957                 case BCM43xx_PHYTYPE_B:
 958                 case BCM43xx_PHYTYPE_G:
 959                         have_bg = 1;
 960                         break;
 961                 case BCM43xx_PHYTYPE_A:
 962                         have_a = 1;
 963                         break;
 964                 default:
 965                         assert(0);
 966                 }
 967         }
 968         iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
 969
 970         if (have_a) {
 971                 for (i = 0, channel = IEEE80211_52GHZ_MIN_CHANNEL;
 972                       channel <= IEEE80211_52GHZ_MAX_CHANNEL; channel++) {
 973                         chan = &geo->a[i++];
 974                         chan->freq = bcm43xx_channel_to_freq_a(channel);
 975                         chan->channel = channel;
 976                 }
 977                 geo->a_channels = i;
 978         }
 979         if (have_bg) {
 980                 for (i = 0, channel = IEEE80211_24GHZ_MIN_CHANNEL;
 981                       channel <= IEEE80211_24GHZ_MAX_CHANNEL; channel++) {
 982                         chan = &geo->bg[i++];
 983                         chan->freq = bcm43xx_channel_to_freq_bg(channel);
 984                         chan->channel = channel;
 985                 }
 986                 geo->bg_channels = i;
 987         }
 988         memcpy(geo->name, iso_country, 2);
 989         if (0 /*TODO: Outdoor use only */)
 990                 geo->name[2] = 'O';
 991         else if (0 /*TODO: Indoor use only */)
 992                 geo->name[2] = 'I';
 993         else
 994                 geo->name[2] = ' ';
 995         geo->name[3] = '\0';
 996
 997         ieee80211_set_geo(bcm->ieee, geo);
 998         kfree(geo);
 999
1000         return 0;
1001 }
1002
1003 /* DummyTransmission function, as documented on
1004  * http://bcm-specs.sipsolutions.net/DummyTransmission
1005  */
1006 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
1007 {
1008         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1009         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1010         unsigned int i, max_loop;
1011         u16 value = 0;
1012         u32 buffer[5] = {
1013                 0x00000000,
1014                 0x0000D400,
1015                 0x00000000,
1016                 0x00000001,
1017                 0x00000000,
1018         };
1019
1020         switch (phy->type) {
1021         case BCM43xx_PHYTYPE_A:
1022                 max_loop = 0x1E;
1023                 buffer[0] = 0xCC010200;
1024                 break;
1025         case BCM43xx_PHYTYPE_B:
1026         case BCM43xx_PHYTYPE_G:
1027                 max_loop = 0xFA;
1028                 buffer[0] = 0x6E840B00;
1029                 break;
1030         default:
1031                 assert(0);
1032                 return;
1033         }
1034
1035         for (i = 0; i < 5; i++)
1036                 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1037
1038         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1039
1040         bcm43xx_write16(bcm, 0x0568, 0x0000);
1041         bcm43xx_write16(bcm, 0x07C0, 0x0000);
1042         bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1043         bcm43xx_write16(bcm, 0x0508, 0x0000);
1044         bcm43xx_write16(bcm, 0x050A, 0x0000);
1045         bcm43xx_write16(bcm, 0x054C, 0x0000);
1046         bcm43xx_write16(bcm, 0x056A, 0x0014);
1047         bcm43xx_write16(bcm, 0x0568, 0x0826);
1048         bcm43xx_write16(bcm, 0x0500, 0x0000);
1049         bcm43xx_write16(bcm, 0x0502, 0x0030);
1050
1051         if (radio->version == 0x2050 && radio->revision <= 0x5)
1052                 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1053         for (i = 0x00; i < max_loop; i++) {
1054                 value = bcm43xx_read16(bcm, 0x050E);
1055                 if (value & 0x0080)
1056                         break;
1057                 udelay(10);
1058         }
1059         for (i = 0x00; i < 0x0A; i++) {
1060                 value = bcm43xx_read16(bcm, 0x050E);
1061                 if (value & 0x0400)
1062                         break;
1063                 udelay(10);
1064         }
1065         for (i = 0x00; i < 0x0A; i++) {
1066                 value = bcm43xx_read16(bcm, 0x0690);
1067                 if (!(value & 0x0100))
1068                         break;
1069                 udelay(10);
1070         }
1071         if (radio->version == 0x2050 && radio->revision <= 0x5)
1072                 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1073 }
1074
1075 static void key_write(struct bcm43xx_private *bcm,
1076                       u8 index, u8 algorithm, const u16 *key)
1077 {
1078         unsigned int i, basic_wep = 0;
1079         u32 offset;
1080         u16 value;
1081
1082         /* Write associated key information */
1083         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1084                             ((index << 4) | (algorithm & 0x0F)));
1085
1086         /* The first 4 WEP keys need extra love */
1087         if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1088             (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1089                 basic_wep = 1;
1090
1091         /* Write key payload, 8 little endian words */
1092         offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1093         for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1094                 value = cpu_to_le16(key[i]);
1095                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1096                                     offset + (i * 2), value);
1097
1098                 if (!basic_wep)
1099                         continue;
1100
1101                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1102                                     offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1103                                     value);
1104         }
1105 }
1106
1107 static void keymac_write(struct bcm43xx_private *bcm,
1108                          u8 index, const u32 *addr)
1109 {
1110         /* for keys 0-3 there is no associated mac address */
1111         if (index < 4)
1112                 return;
1113
1114         index -= 4;
1115         if (bcm->current_core->rev >= 5) {
1116                 bcm43xx_shm_write32(bcm,
1117                                     BCM43xx_SHM_HWMAC,
1118                                     index * 2,
1119                                     cpu_to_be32(*addr));
1120                 bcm43xx_shm_write16(bcm,
1121                                     BCM43xx_SHM_HWMAC,
1122                                     (index * 2) + 1,
1123                                     cpu_to_be16(*((u16 *)(addr + 1))));
1124         } else {
1125                 if (index < 8) {
1126                         TODO(); /* Put them in the macaddress filter */
1127                 } else {
1128                         TODO();
1129                         /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1130                            Keep in mind to update the count of keymacs in 0x003E as well! */
1131                 }
1132         }
1133 }
1134
1135 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1136                              u8 index, u8 algorithm,
1137                              const u8 *_key, int key_len,
1138                              const u8 *mac_addr)
1139 {
1140         u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1141
1142         if (index >= ARRAY_SIZE(bcm->key))
1143                 return -EINVAL;
1144         if (key_len > ARRAY_SIZE(key))
1145                 return -EINVAL;
1146         if (algorithm < 1 || algorithm > 5)
1147                 return -EINVAL;
1148
1149         memcpy(key, _key, key_len);
1150         key_write(bcm, index, algorithm, (const u16 *)key);
1151         keymac_write(bcm, index, (const u32 *)mac_addr);
1152
1153         bcm->key[index].algorithm = algorithm;
1154
1155         return 0;
1156 }
1157
1158 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1159 {
1160         static const u32 zero_mac[2] = { 0 };
1161         unsigned int i,j, nr_keys = 54;
1162         u16 offset;
1163
1164         if (bcm->current_core->rev < 5)
1165                 nr_keys = 16;
1166         assert(nr_keys <= ARRAY_SIZE(bcm->key));
1167
1168         for (i = 0; i < nr_keys; i++) {
1169                 bcm->key[i].enabled = 0;
1170                 /* returns for i < 4 immediately */
1171                 keymac_write(bcm, i, zero_mac);
1172                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1173                                     0x100 + (i * 2), 0x0000);
1174                 for (j = 0; j < 8; j++) {
1175                         offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1176                         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1177                                             offset, 0x0000);
1178                 }
1179         }
1180         dprintk(KERN_INFO PFX "Keys cleared\n");
1181 }
1182
1183 /* Lowlevel core-switch function. This is only to be used in
1184  * bcm43xx_switch_core() and bcm43xx_probe_cores()
1185  */
1186 static int _switch_core(struct bcm43xx_private *bcm, int core)
1187 {
1188         int err;
1189         int attempts = 0;
1190         u32 current_core;
1191
1192         assert(core >= 0);
1193         while (1) {
1194                 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1195                                                  (core * 0x1000) + 0x18000000);
1196                 if (unlikely(err))
1197                         goto error;
1198                 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1199                                                 &current_core);
1200                 if (unlikely(err))
1201                         goto error;
1202                 current_core = (current_core - 0x18000000) / 0x1000;
1203                 if (current_core == core)
1204                         break;
1205
1206                 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1207                         goto error;
1208                 udelay(10);
1209         }
1210 #ifdef CONFIG_BCM947XX
1211         if (bcm->pci_dev->bus->number == 0)
1212                 bcm->current_core_offset = 0x1000 * core;
1213         else
1214                 bcm->current_core_offset = 0;
1215 #endif
1216
1217         return 0;
1218 error:
1219         printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1220         return -ENODEV;
1221 }
1222
1223 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1224 {
1225         int err;
1226
1227         if (unlikely(!new_core))
1228                 return 0;
1229         if (!new_core->available)
1230                 return -ENODEV;
1231         if (bcm->current_core == new_core)
1232                 return 0;
1233         err = _switch_core(bcm, new_core->index);
1234         if (unlikely(err))
1235                 goto out;
1236
1237         bcm->current_core = new_core;
1238 out:
1239         return err;
1240 }
1241
1242 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1243 {
1244         u32 value;
1245
1246         value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1247         value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1248                  | BCM43xx_SBTMSTATELOW_REJECT;
1249
1250         return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1251 }
1252
1253 /* disable current core */
1254 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1255 {
1256         u32 sbtmstatelow;
1257         u32 sbtmstatehigh;
1258         int i;
1259
1260         /* fetch sbtmstatelow from core information registers */
1261         sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1262
1263         /* core is already in reset */
1264         if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1265                 goto out;
1266
1267         if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1268                 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1269                                BCM43xx_SBTMSTATELOW_REJECT;
1270                 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1271
1272                 for (i = 0; i < 1000; i++) {
1273                         sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1274                         if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1275                                 i = -1;
1276                                 break;
1277                         }
1278                         udelay(10);
1279                 }
1280                 if (i != -1) {
1281                         printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1282                         return -EBUSY;
1283                 }
1284
1285                 for (i = 0; i < 1000; i++) {
1286                         sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1287                         if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1288                                 i = -1;
1289                                 break;
1290                         }
1291                         udelay(10);
1292                 }
1293                 if (i != -1) {
1294                         printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1295                         return -EBUSY;
1296                 }
1297
1298                 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1299                                BCM43xx_SBTMSTATELOW_REJECT |
1300                                BCM43xx_SBTMSTATELOW_RESET |
1301                                BCM43xx_SBTMSTATELOW_CLOCK |
1302                                core_flags;
1303                 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1304                 udelay(10);
1305         }
1306
1307         sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1308                        BCM43xx_SBTMSTATELOW_REJECT |
1309                        core_flags;
1310         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1311
1312 out:
1313         bcm->current_core->enabled = 0;
1314
1315         return 0;
1316 }
1317
1318 /* enable (reset) current core */
1319 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1320 {
1321         u32 sbtmstatelow;
1322         u32 sbtmstatehigh;
1323         u32 sbimstate;
1324         int err;
1325
1326         err = bcm43xx_core_disable(bcm, core_flags);
1327         if (err)
1328                 goto out;
1329
1330         sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1331                        BCM43xx_SBTMSTATELOW_RESET |
1332                        BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1333                        core_flags;
1334         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1335         udelay(1);
1336
1337         sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1338         if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1339                 sbtmstatehigh = 0x00000000;
1340                 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1341         }
1342
1343         sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1344         if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1345                 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1346                 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1347         }
1348
1349         sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1350                        BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1351                        core_flags;
1352         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1353         udelay(1);
1354
1355         sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1356         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1357         udelay(1);
1358
1359         bcm->current_core->enabled = 1;
1360         assert(err == 0);
1361 out:
1362         return err;
1363 }
1364
1365 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1366 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1367 {
1368         u32 flags = 0x00040000;
1369
1370         if ((bcm43xx_core_enabled(bcm)) &&
1371             !bcm43xx_using_pio(bcm)) {
1372 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1373 #if 0
1374 #ifndef CONFIG_BCM947XX
1375                 /* reset all used DMA controllers. */
1376                 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1377                 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1378                 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1379                 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1380                 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1381                 if (bcm->current_core->rev < 5)
1382                         bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1383 #endif
1384 #endif
1385         }
1386         if (bcm43xx_status(bcm) == BCM43xx_STAT_SHUTTINGDOWN) {
1387                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1388                                 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1389                                 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1390         } else {
1391                 if (connect_phy)
1392                         flags |= 0x20000000;
1393                 bcm43xx_phy_connect(bcm, connect_phy);
1394                 bcm43xx_core_enable(bcm, flags);
1395                 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1396                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1397                                 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1398                                 | BCM43xx_SBF_400);
1399         }
1400 }
1401
1402 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1403 {
1404         bcm43xx_radio_turn_off(bcm);
1405         bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1406         bcm43xx_core_disable(bcm, 0);
1407 }
1408
1409 /* Mark the current 80211 core inactive. */
1410 static void bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm)
1411 {
1412         u32 sbtmstatelow;
1413
1414         bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1415         bcm43xx_radio_turn_off(bcm);
1416         sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1417         sbtmstatelow &= 0xDFF5FFFF;
1418         sbtmstatelow |= 0x000A0000;
1419         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1420         udelay(1);
1421         sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1422         sbtmstatelow &= 0xFFF5FFFF;
1423         sbtmstatelow |= 0x00080000;
1424         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1425         udelay(1);
1426 }
1427
1428 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1429 {
1430         u32 v0, v1;
1431         u16 tmp;
1432         struct bcm43xx_xmitstatus stat;
1433
1434         while (1) {
1435                 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1436                 if (!v0)
1437                         break;
1438                 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1439
1440                 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1441                 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1442                 stat.flags = tmp & 0xFF;
1443                 stat.cnt1 = (tmp & 0x0F00) >> 8;
1444                 stat.cnt2 = (tmp & 0xF000) >> 12;
1445                 stat.seq = (u16)(v1 & 0xFFFF);
1446                 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1447
1448                 bcm43xx_debugfs_log_txstat(bcm, &stat);
1449
1450                 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1451                         continue;
1452                 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1453                         //TODO: packet was not acked (was lost)
1454                 }
1455                 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1456
1457                 if (bcm43xx_using_pio(bcm))
1458                         bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1459                 else
1460                         bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1461         }
1462 }
1463
1464 static void drain_txstatus_queue(struct bcm43xx_private *bcm)
1465 {
1466         u32 dummy;
1467
1468         if (bcm->current_core->rev < 5)
1469                 return;
1470         /* Read all entries from the microcode TXstatus FIFO
1471          * and throw them away.
1472          */
1473         while (1) {
1474                 dummy = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1475                 if (!dummy)
1476                         break;
1477                 dummy = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1478         }
1479 }
1480
1481 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1482 {
1483         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1484         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1485         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1486                         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1487         assert(bcm->noisecalc.core_at_start == bcm->current_core);
1488         assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1489 }
1490
1491 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1492 {
1493         /* Top half of Link Quality calculation. */
1494
1495         if (bcm->noisecalc.calculation_running)
1496                 return;
1497         bcm->noisecalc.core_at_start = bcm->current_core;
1498         bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1499         bcm->noisecalc.calculation_running = 1;
1500         bcm->noisecalc.nr_samples = 0;
1501
1502         bcm43xx_generate_noise_sample(bcm);
1503 }
1504
1505 static void handle_irq_noise(struct bcm43xx_private *bcm)
1506 {
1507         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1508         u16 tmp;
1509         u8 noise[4];
1510         u8 i, j;
1511         s32 average;
1512
1513         /* Bottom half of Link Quality calculation. */
1514
1515         assert(bcm->noisecalc.calculation_running);
1516         if (bcm->noisecalc.core_at_start != bcm->current_core ||
1517             bcm->noisecalc.channel_at_start != radio->channel)
1518                 goto drop_calculation;
1519         tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1520         noise[0] = (tmp & 0x00FF);
1521         noise[1] = (tmp & 0xFF00) >> 8;
1522         tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1523         noise[2] = (tmp & 0x00FF);
1524         noise[3] = (tmp & 0xFF00) >> 8;
1525         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1526             noise[2] == 0x7F || noise[3] == 0x7F)
1527                 goto generate_new;
1528
1529         /* Get the noise samples. */
1530         assert(bcm->noisecalc.nr_samples < 8);
1531         i = bcm->noisecalc.nr_samples;
1532         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1533         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1534         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1535         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1536         bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1537         bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1538         bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1539         bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1540         bcm->noisecalc.nr_samples++;
1541         if (bcm->noisecalc.nr_samples == 8) {
1542                 /* Calculate the Link Quality by the noise samples. */
1543                 average = 0;
1544                 for (i = 0; i < 8; i++) {
1545                         for (j = 0; j < 4; j++)
1546                                 average += bcm->noisecalc.samples[i][j];
1547                 }
1548                 average /= (8 * 4);
1549                 average *= 125;
1550                 average += 64;
1551                 average /= 128;
1552
1553                 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1554                 tmp = (tmp / 128) & 0x1F;
1555                 if (tmp >= 8)
1556                         average += 2;
1557                 else
1558                         average -= 25;
1559                 if (tmp == 8)
1560                         average -= 72;
1561                 else
1562                         average -= 48;
1563
1564                 bcm->stats.noise = average;
1565 drop_calculation:
1566                 bcm->noisecalc.calculation_running = 0;
1567                 return;
1568         }
1569 generate_new:
1570         bcm43xx_generate_noise_sample(bcm);
1571 }
1572
1573 static void handle_irq_ps(struct bcm43xx_private *bcm)
1574 {
1575         if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1576                 ///TODO: PS TBTT
1577         } else {
1578                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1579                         bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1580         }
1581         if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1582                 bcm->reg124_set_0x4 = 1;
1583         //FIXME else set to false?
1584 }
1585
1586 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1587 {
1588         if (!bcm->reg124_set_0x4)
1589                 return;
1590         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1591                         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1592                         | 0x4);
1593         //FIXME: reset reg124_set_0x4 to false?
1594 }
1595
1596 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1597 {
1598         u32 tmp;
1599
1600         //TODO: AP mode.
1601
1602         while (1) {
1603                 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1604                 if (!(tmp & 0x00000008))
1605                         break;
1606         }
1607         /* 16bit write is odd, but correct. */
1608         bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1609 }
1610
1611 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1612                                              u16 ram_offset, u16 shm_size_offset)
1613 {
1614         u32 value;
1615         u16 size = 0;
1616
1617         /* Timestamp. */
1618         //FIXME: assumption: The chip sets the timestamp
1619         value = 0;
1620         bcm43xx_ram_write(bcm, ram_offset++, value);
1621         bcm43xx_ram_write(bcm, ram_offset++, value);
1622         size += 8;
1623
1624         /* Beacon Interval / Capability Information */
1625         value = 0x0000;//FIXME: Which interval?
1626         value |= (1 << 0) << 16; /* ESS */
1627         value |= (1 << 2) << 16; /* CF Pollable */      //FIXME?
1628         value |= (1 << 3) << 16; /* CF Poll Request */  //FIXME?
1629         if (!bcm->ieee->open_wep)
1630                 value |= (1 << 4) << 16; /* Privacy */
1631         bcm43xx_ram_write(bcm, ram_offset++, value);
1632         size += 4;
1633
1634         /* SSID */
1635         //TODO
1636
1637         /* FH Parameter Set */
1638         //TODO
1639
1640         /* DS Parameter Set */
1641         //TODO
1642
1643         /* CF Parameter Set */
1644         //TODO
1645
1646         /* TIM */
1647         //TODO
1648
1649         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1650 }
1651
1652 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1653 {
1654         u32 status;
1655
1656         bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1657         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1658
1659         if ((status & 0x1) && (status & 0x2)) {
1660                 /* ACK beacon IRQ. */
1661                 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1662                                 BCM43xx_IRQ_BEACON);
1663                 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1664                 return;
1665         }
1666         if (!(status & 0x1)) {
1667                 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1668                 status |= 0x1;
1669                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1670         }
1671         if (!(status & 0x2)) {
1672                 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1673                 status |= 0x2;
1674                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1675         }
1676 }
1677
1678 /* Interrupt handler bottom-half */
1679 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1680 {
1681         u32 reason;
1682         u32 dma_reason[6];
1683         u32 merged_dma_reason = 0;
1684         int i, activity = 0;
1685         unsigned long flags;
1686
1687 #ifdef CONFIG_BCM43XX_DEBUG
1688         u32 _handled = 0x00000000;
1689 # define bcmirq_handled(irq)    do { _handled |= (irq); } while (0)
1690 #else
1691 # define bcmirq_handled(irq)    do { /* nothing */ } while (0)
1692 #endif /* CONFIG_BCM43XX_DEBUG*/
1693
1694         spin_lock_irqsave(&bcm->irq_lock, flags);
1695         reason = bcm->irq_reason;
1696         for (i = 5; i >= 0; i--) {
1697                 dma_reason[i] = bcm->dma_reason[i];
1698                 merged_dma_reason |= dma_reason[i];
1699         }
1700
1701         if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1702                 /* TX error. We get this when Template Ram is written in wrong endianess
1703                  * in dummy_tx(). We also get this if something is wrong with the TX header
1704                  * on DMA or PIO queues.
1705                  * Maybe we get this in other error conditions, too.
1706                  */
1707                 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1708                 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1709         }
1710         if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK)) {
1711                 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1712                                      "0x%08X, 0x%08X, 0x%08X, "
1713                                      "0x%08X, 0x%08X, 0x%08X\n",
1714                         dma_reason[0], dma_reason[1],
1715                         dma_reason[2], dma_reason[3],
1716                         dma_reason[4], dma_reason[5]);
1717                 bcm43xx_controller_restart(bcm, "DMA error");
1718                 mmiowb();
1719                 spin_unlock_irqrestore(&bcm->irq_lock, flags);
1720                 return;
1721         }
1722         if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK)) {
1723                 printkl(KERN_ERR PFX "DMA error: "
1724                                      "0x%08X, 0x%08X, 0x%08X, "
1725                                      "0x%08X, 0x%08X, 0x%08X\n",
1726                         dma_reason[0], dma_reason[1],
1727                         dma_reason[2], dma_reason[3],
1728                         dma_reason[4], dma_reason[5]);
1729         }
1730
1731         if (reason & BCM43xx_IRQ_PS) {
1732                 handle_irq_ps(bcm);
1733                 bcmirq_handled(BCM43xx_IRQ_PS);
1734         }
1735
1736         if (reason & BCM43xx_IRQ_REG124) {
1737                 handle_irq_reg124(bcm);
1738                 bcmirq_handled(BCM43xx_IRQ_REG124);
1739         }
1740
1741         if (reason & BCM43xx_IRQ_BEACON) {
1742                 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1743                         handle_irq_beacon(bcm);
1744                 bcmirq_handled(BCM43xx_IRQ_BEACON);
1745         }
1746
1747         if (reason & BCM43xx_IRQ_PMQ) {
1748                 handle_irq_pmq(bcm);
1749                 bcmirq_handled(BCM43xx_IRQ_PMQ);
1750         }
1751
1752         if (reason & BCM43xx_IRQ_SCAN) {
1753                 /*TODO*/
1754                 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1755         }
1756
1757         if (reason & BCM43xx_IRQ_NOISE) {
1758                 handle_irq_noise(bcm);
1759                 bcmirq_handled(BCM43xx_IRQ_NOISE);
1760         }
1761
1762         /* Check the DMA reason registers for received data. */
1763         if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1764                 if (bcm43xx_using_pio(bcm))
1765                         bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1766                 else
1767                         bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1768                 /* We intentionally don't set "activity" to 1, here. */
1769         }
1770         assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1771         assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1772         if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1773                 if (bcm43xx_using_pio(bcm))
1774                         bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1775                 else
1776                         bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring3);
1777                 activity = 1;
1778         }
1779         assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
1780         assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
1781         bcmirq_handled(BCM43xx_IRQ_RX);
1782
1783         if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1784                 handle_irq_transmit_status(bcm);
1785                 activity = 1;
1786                 //TODO: In AP mode, this also causes sending of powersave responses.
1787                 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1788         }
1789
1790         /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1791         bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1792 #ifdef CONFIG_BCM43XX_DEBUG
1793         if (unlikely(reason & ~_handled)) {
1794                 printkl(KERN_WARNING PFX
1795                         "Unhandled IRQ! Reason: 0x%08x,  Unhandled: 0x%08x,  "
1796                         "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1797                         reason, (reason & ~_handled),
1798                         dma_reason[0], dma_reason[1],
1799                         dma_reason[2], dma_reason[3]);
1800         }
1801 #endif
1802 #undef bcmirq_handled
1803
1804         if (!modparam_noleds)
1805                 bcm43xx_leds_update(bcm, activity);
1806         bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1807         mmiowb();
1808         spin_unlock_irqrestore(&bcm->irq_lock, flags);
1809 }
1810
1811 static void pio_irq_workaround(struct bcm43xx_private *bcm,
1812                                u16 base, int queueidx)
1813 {
1814         u16 rxctl;
1815
1816         rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1817         if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1818                 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1819         else
1820                 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1821 }
1822
1823 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1824 {
1825         if (bcm43xx_using_pio(bcm) &&
1826             (bcm->current_core->rev < 3) &&
1827             (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1828                 /* Apply a PIO specific workaround to the dma_reasons */
1829                 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1830                 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1831                 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1832                 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
1833         }
1834
1835         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1836
1837         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_REASON,
1838                         bcm->dma_reason[0]);
1839         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1840                         bcm->dma_reason[1]);
1841         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1842                         bcm->dma_reason[2]);
1843         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1844                         bcm->dma_reason[3]);
1845         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1846                         bcm->dma_reason[4]);
1847         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_REASON,
1848                         bcm->dma_reason[5]);
1849 }
1850
1851 /* Interrupt handler top-half */
1852 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id)
1853 {
1854         irqreturn_t ret = IRQ_HANDLED;
1855         struct bcm43xx_private *bcm = dev_id;
1856         u32 reason;
1857
1858         if (!bcm)
1859                 return IRQ_NONE;
1860
1861         spin_lock(&bcm->irq_lock);
1862
1863         assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
1864         assert(bcm->current_core->id == BCM43xx_COREID_80211);
1865
1866         reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1867         if (reason == 0xffffffff) {
1868                 /* irq not for us (shared irq) */
1869                 ret = IRQ_NONE;
1870                 goto out;
1871         }
1872         reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1873         if (!reason)
1874                 goto out;
1875
1876         bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA0_REASON)
1877                              & 0x0001DC00;
1878         bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1879                              & 0x0000DC00;
1880         bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1881                              & 0x0000DC00;
1882         bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1883                              & 0x0001DC00;
1884         bcm->dma_reason[4] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1885                              & 0x0000DC00;
1886         bcm->dma_reason[5] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA5_REASON)
1887                              & 0x0000DC00;
1888
1889         bcm43xx_interrupt_ack(bcm, reason);
1890
1891         /* disable all IRQs. They are enabled again in the bottom half. */
1892         bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1893         /* save the reason code and call our bottom half. */
1894         bcm->irq_reason = reason;
1895         tasklet_schedule(&bcm->isr_tasklet);
1896
1897 out:
1898         mmiowb();
1899         spin_unlock(&bcm->irq_lock);
1900
1901         return ret;
1902 }
1903
1904 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1905 {
1906         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1907
1908         if (bcm->firmware_norelease && !force)
1909                 return; /* Suspending or controller reset. */
1910         release_firmware(phy->ucode);
1911         phy->ucode = NULL;
1912         release_firmware(phy->pcm);
1913         phy->pcm = NULL;
1914         release_firmware(phy->initvals0);
1915         phy->initvals0 = NULL;
1916         release_firmware(phy->initvals1);
1917         phy->initvals1 = NULL;
1918 }
1919
1920 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1921 {
1922         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1923         u8 rev = bcm->current_core->rev;
1924         int err = 0;
1925         int nr;
1926         char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1927
1928         if (!phy->ucode) {
1929                 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1930                          (rev >= 5 ? 5 : rev),
1931                          modparam_fwpostfix);
1932                 err = request_firmware(&phy->ucode, buf, &bcm->pci_dev->dev);
1933                 if (err) {
1934                         printk(KERN_ERR PFX
1935                                "Error: Microcode \"%s\" not available or load failed.\n",
1936                                 buf);
1937                         goto error;
1938                 }
1939         }
1940
1941         if (!phy->pcm) {
1942                 snprintf(buf, ARRAY_SIZE(buf),
1943                          "bcm43xx_pcm%d%s.fw",
1944                          (rev < 5 ? 4 : 5),
1945                          modparam_fwpostfix);
1946                 err = request_firmware(&phy->pcm, buf, &bcm->pci_dev->dev);
1947                 if (err) {
1948                         printk(KERN_ERR PFX
1949                                "Error: PCM \"%s\" not available or load failed.\n",
1950                                buf);
1951                         goto error;
1952                 }
1953         }
1954
1955         if (!phy->initvals0) {
1956                 if (rev == 2 || rev == 4) {
1957                         switch (phy->type) {
1958                         case BCM43xx_PHYTYPE_A:
1959                                 nr = 3;
1960                                 break;
1961                         case BCM43xx_PHYTYPE_B:
1962                         case BCM43xx_PHYTYPE_G:
1963                                 nr = 1;
1964                                 break;
1965                         default:
1966                                 goto err_noinitval;
1967                         }
1968
1969                 } else if (rev >= 5) {
1970                         switch (phy->type) {
1971                         case BCM43xx_PHYTYPE_A:
1972                                 nr = 7;
1973                                 break;
1974                         case BCM43xx_PHYTYPE_B:
1975                         case BCM43xx_PHYTYPE_G:
1976                                 nr = 5;
1977                                 break;
1978                         default:
1979                                 goto err_noinitval;
1980                         }
1981                 } else
1982                         goto err_noinitval;
1983                 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1984                          nr, modparam_fwpostfix);
1985
1986                 err = request_firmware(&phy->initvals0, buf, &bcm->pci_dev->dev);
1987                 if (err) {
1988                         printk(KERN_ERR PFX
1989                                "Error: InitVals \"%s\" not available or load failed.\n",
1990                                 buf);
1991                         goto error;
1992                 }
1993                 if (phy->initvals0->size % sizeof(struct bcm43xx_initval)) {
1994                         printk(KERN_ERR PFX "InitVals fileformat error.\n");
1995                         goto error;
1996                 }
1997         }
1998
1999         if (!phy->initvals1) {
2000                 if (rev >= 5) {
2001                         u32 sbtmstatehigh;
2002
2003                         switch (phy->type) {
2004                         case BCM43xx_PHYTYPE_A:
2005                                 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
2006                                 if (sbtmstatehigh & 0x00010000)
2007                                         nr = 9;
2008                                 else
2009                                         nr = 10;
2010                                 break;
2011                         case BCM43xx_PHYTYPE_B:
2012                         case BCM43xx_PHYTYPE_G:
2013                                         nr = 6;
2014                                 break;
2015                         default:
2016                                 goto err_noinitval;
2017                         }
2018                         snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2019                                  nr, modparam_fwpostfix);
2020
2021                         err = request_firmware(&phy->initvals1, buf, &bcm->pci_dev->dev);
2022                         if (err) {
2023                                 printk(KERN_ERR PFX
2024                                        "Error: InitVals \"%s\" not available or load failed.\n",
2025                                         buf);
2026                                 goto error;
2027                         }
2028                         if (phy->initvals1->size % sizeof(struct bcm43xx_initval)) {
2029                                 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2030                                 goto error;
2031                         }
2032                 }
2033         }
2034
2035 out:
2036         return err;
2037 error:
2038         bcm43xx_release_firmware(bcm, 1);
2039         goto out;
2040 err_noinitval:
2041         printk(KERN_ERR PFX "Error: No InitVals available!\n");
2042         err = -ENOENT;
2043         goto error;
2044 }
2045
2046 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2047 {
2048         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2049         const u32 *data;
2050         unsigned int i, len;
2051
2052         /* Upload Microcode. */
2053         data = (u32 *)(phy->ucode->data);
2054         len = phy->ucode->size / sizeof(u32);
2055         bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2056         for (i = 0; i < len; i++) {
2057                 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2058                                 be32_to_cpu(data[i]));
2059                 udelay(10);
2060         }
2061
2062         /* Upload PCM data. */
2063         data = (u32 *)(phy->pcm->data);
2064         len = phy->pcm->size / sizeof(u32);
2065         bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2066         bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2067         bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2068         for (i = 0; i < len; i++) {
2069                 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2070                                 be32_to_cpu(data[i]));
2071                 udelay(10);
2072         }
2073 }
2074
2075 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2076                                   const struct bcm43xx_initval *data,
2077                                   const unsigned int len)
2078 {
2079         u16 offset, size;
2080         u32 value;
2081         unsigned int i;
2082
2083         for (i = 0; i < len; i++) {
2084                 offset = be16_to_cpu(data[i].offset);
2085                 size = be16_to_cpu(data[i].size);
2086                 value = be32_to_cpu(data[i].value);
2087
2088                 if (unlikely(offset >= 0x1000))
2089                         goto err_format;
2090                 if (size == 2) {
2091                         if (unlikely(value & 0xFFFF0000))
2092                                 goto err_format;
2093                         bcm43xx_write16(bcm, offset, (u16)value);
2094                 } else if (size == 4) {
2095                         bcm43xx_write32(bcm, offset, value);
2096                 } else
2097                         goto err_format;
2098         }
2099
2100         return 0;
2101
2102 err_format:
2103         printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2104                             "Please fix your bcm43xx firmware files.\n");
2105         return -EPROTO;
2106 }
2107
2108 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2109 {
2110         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2111         int err;
2112
2113         err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals0->data,
2114                                      phy->initvals0->size / sizeof(struct bcm43xx_initval));
2115         if (err)
2116                 goto out;
2117         if (phy->initvals1) {
2118                 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals1->data,
2119                                              phy->initvals1->size / sizeof(struct bcm43xx_initval));
2120                 if (err)
2121                         goto out;
2122         }
2123 out:
2124         return err;
2125 }
2126
2127 #ifdef CONFIG_BCM947XX
2128 static struct pci_device_id bcm43xx_47xx_ids[] = {
2129         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
2130         { 0 }
2131 };
2132 #endif
2133
2134 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2135 {
2136         int err;
2137
2138         bcm->irq = bcm->pci_dev->irq;
2139 #ifdef CONFIG_BCM947XX
2140         if (bcm->pci_dev->bus->number == 0) {
2141                 struct pci_dev *d;
2142                 struct pci_device_id *id;
2143                 for (id = bcm43xx_47xx_ids; id->vendor; id++) {
2144                         d = pci_get_device(id->vendor, id->device, NULL);
2145                         if (d != NULL) {
2146                                 bcm->irq = d->irq;
2147                                 pci_dev_put(d);
2148                                 break;
2149                         }
2150                 }
2151         }
2152 #endif
2153         err = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2154                           IRQF_SHARED, KBUILD_MODNAME, bcm);
2155         if (err)
2156                 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2157
2158         return err;
2159 }
2160
2161 /* Switch to the core used to write the GPIO register.
2162  * This is either the ChipCommon, or the PCI core.
2163  */
2164 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2165 {
2166         int err;
2167
2168         /* Where to find the GPIO register depends on the chipset.
2169          * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2170          * control register. Otherwise the register at offset 0x6c in the
2171          * PCI core is the GPIO control register.
2172          */
2173         err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2174         if (err == -ENODEV) {
2175                 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2176                 if (unlikely(err == -ENODEV)) {
2177                         printk(KERN_ERR PFX "gpio error: "
2178                                "Neither ChipCommon nor PCI core available!\n");
2179                 }
2180         }
2181
2182         return err;
2183 }
2184
2185 /* Initialize the GPIOs
2186  * http://bcm-specs.sipsolutions.net/GPIO
2187  */
2188 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2189 {
2190         struct bcm43xx_coreinfo *old_core;
2191         int err;
2192         u32 mask, set;
2193
2194         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2195                         bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2196                         & 0xFFFF3FFF);
2197
2198         bcm43xx_leds_switch_all(bcm, 0);
2199         bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2200                         bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2201
2202         mask = 0x0000001F;
2203         set = 0x0000000F;
2204         if (bcm->chip_id == 0x4301) {
2205                 mask |= 0x0060;
2206                 set |= 0x0060;
2207         }
2208         if (0 /* FIXME: conditional unknown */) {
2209                 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2210                                 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2211                                 | 0x0100);
2212                 mask |= 0x0180;
2213                 set |= 0x0180;
2214         }
2215         if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2216                 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2217                                 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2218                                 | 0x0200);
2219                 mask |= 0x0200;
2220                 set |= 0x0200;
2221         }
2222         if (bcm->current_core->rev >= 2)
2223                 mask  |= 0x0010; /* FIXME: This is redundant. */
2224
2225         old_core = bcm->current_core;
2226         err = switch_to_gpio_core(bcm);
2227         if (err)
2228                 goto out;
2229         bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2230                         (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
2231         err = bcm43xx_switch_core(bcm, old_core);
2232 out:
2233         return err;
2234 }
2235
2236 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2237 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2238 {
2239         struct bcm43xx_coreinfo *old_core;
2240         int err;
2241
2242         old_core = bcm->current_core;
2243         err = switch_to_gpio_core(bcm);
2244         if (err)
2245                 return err;
2246         bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2247         err = bcm43xx_switch_core(bcm, old_core);
2248         assert(err == 0);
2249
2250         return 0;
2251 }
2252
2253 /* http://bcm-specs.sipsolutions.net/EnableMac */
2254 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2255 {
2256         bcm->mac_suspended--;
2257         assert(bcm->mac_suspended >= 0);
2258         if (bcm->mac_suspended == 0) {
2259                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2260                                 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2261                                 | BCM43xx_SBF_MAC_ENABLED);
2262                 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2263                 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2264                 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2265                 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2266         }
2267 }
2268
2269 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2270 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2271 {
2272         int i;
2273         u32 tmp;
2274
2275         assert(bcm->mac_suspended >= 0);
2276         if (bcm->mac_suspended == 0) {
2277                 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2278                 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2279                                 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2280                                 & ~BCM43xx_SBF_MAC_ENABLED);
2281                 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2282                 for (i = 10000; i; i--) {
2283                         tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2284                         if (tmp & BCM43xx_IRQ_READY)
2285                                 goto out;
2286                         udelay(1);
2287                 }
2288                 printkl(KERN_ERR PFX "MAC suspend failed\n");
2289         }
2290 out:
2291         bcm->mac_suspended++;
2292 }
2293
2294 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2295                         int iw_mode)
2296 {
2297         unsigned long flags;
2298         struct net_device *net_dev = bcm->net_dev;
2299         u32 status;
2300         u16 value;
2301
2302         spin_lock_irqsave(&bcm->ieee->lock, flags);
2303         bcm->ieee->iw_mode = iw_mode;
2304         spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2305         if (iw_mode == IW_MODE_MONITOR)
2306                 net_dev->type = ARPHRD_IEEE80211;
2307         else
2308                 net_dev->type = ARPHRD_ETHER;
2309
2310         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2311         /* Reset status to infrastructured mode */
2312         status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2313         status &= ~BCM43xx_SBF_MODE_PROMISC;
2314         status |= BCM43xx_SBF_MODE_NOTADHOC;
2315
2316 /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2317 status |= BCM43xx_SBF_MODE_PROMISC;
2318
2319         switch (iw_mode) {
2320         case IW_MODE_MONITOR:
2321                 status |= BCM43xx_SBF_MODE_MONITOR;
2322                 status |= BCM43xx_SBF_MODE_PROMISC;
2323                 break;
2324         case IW_MODE_ADHOC:
2325                 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2326                 break;
2327         case IW_MODE_MASTER:
2328                 status |= BCM43xx_SBF_MODE_AP;
2329                 break;
2330         case IW_MODE_SECOND:
2331         case IW_MODE_REPEAT:
2332                 TODO(); /* TODO */
2333                 break;
2334         case IW_MODE_INFRA:
2335                 /* nothing to be done here... */
2336                 break;
2337         default:
2338                 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
2339         }
2340         if (net_dev->flags & IFF_PROMISC)
2341                 status |= BCM43xx_SBF_MODE_PROMISC;
2342         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2343
2344         value = 0x0002;
2345         if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2346                 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2347                         value = 0x0064;
2348                 else
2349                         value = 0x0032;
2350         }
2351         bcm43xx_write16(bcm, 0x0612, value);
2352 }
2353
2354 /* This is the opposite of bcm43xx_chip_init() */
2355 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2356 {
2357         bcm43xx_radio_turn_off(bcm);
2358         if (!modparam_noleds)
2359                 bcm43xx_leds_exit(bcm);
2360         bcm43xx_gpio_cleanup(bcm);
2361         bcm43xx_release_firmware(bcm, 0);
2362 }
2363
2364 /* Initialize the chip
2365  * http://bcm-specs.sipsolutions.net/ChipInit
2366  */
2367 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2368 {
2369         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2370         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2371         int err;
2372         int i, tmp;
2373         u32 value32;
2374         u16 value16;
2375
2376         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2377                         BCM43xx_SBF_CORE_READY
2378                         | BCM43xx_SBF_400);
2379
2380         err = bcm43xx_request_firmware(bcm);
2381         if (err)
2382                 goto out;
2383         bcm43xx_upload_microcode(bcm);
2384
2385         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xFFFFFFFF);
2386         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2387         i = 0;
2388         while (1) {
2389                 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2390                 if (value32 == BCM43xx_IRQ_READY)
2391                         break;
2392                 i++;
2393                 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2394                         printk(KERN_ERR PFX "IRQ_READY timeout\n");
2395                         err = -ENODEV;
2396                         goto err_release_fw;
2397                 }
2398                 udelay(10);
2399         }
2400         bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2401
2402         value16 = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2403                                      BCM43xx_UCODE_REVISION);
2404
2405         dprintk(KERN_INFO PFX "Microcode rev 0x%x, pl 0x%x "
2406                 "(20%.2i-%.2i-%.2i  %.2i:%.2i:%.2i)\n", value16,
2407                 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2408                                    BCM43xx_UCODE_PATCHLEVEL),
2409                 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2410                                     BCM43xx_UCODE_DATE) >> 12) & 0xf,
2411                 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2412                                     BCM43xx_UCODE_DATE) >> 8) & 0xf,
2413                 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2414                                    BCM43xx_UCODE_DATE) & 0xff,
2415                 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2416                                    BCM43xx_UCODE_TIME) >> 11) & 0x1f,
2417                 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2418                                    BCM43xx_UCODE_TIME) >> 5) & 0x3f,
2419                 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2420                                    BCM43xx_UCODE_TIME) & 0x1f);
2421
2422         if ( value16 > 0x128 ) {
2423                 printk(KERN_ERR PFX
2424                         "Firmware: no support for microcode extracted "
2425                         "from version 4.x binary drivers.\n");
2426                 err = -EOPNOTSUPP;
2427                 goto err_release_fw;
2428         }
2429
2430         err = bcm43xx_gpio_init(bcm);
2431         if (err)
2432                 goto err_release_fw;
2433
2434         err = bcm43xx_upload_initvals(bcm);
2435         if (err)
2436                 goto err_gpio_cleanup;
2437         bcm43xx_radio_turn_on(bcm);
2438
2439         bcm43xx_write16(bcm, 0x03E6, 0x0000);
2440         err = bcm43xx_phy_init(bcm);
2441         if (err)
2442                 goto err_radio_off;
2443
2444         /* Select initial Interference Mitigation. */
2445         tmp = radio->interfmode;
2446         radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2447         bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2448
2449         bcm43xx_phy_set_antenna_diversity(bcm);
2450         bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2451         if (phy->type == BCM43xx_PHYTYPE_B) {
2452                 value16 = bcm43xx_read16(bcm, 0x005E);
2453                 value16 |= 0x0004;
2454                 bcm43xx_write16(bcm, 0x005E, value16);
2455         }
2456         bcm43xx_write32(bcm, 0x0100, 0x01000000);
2457         if (bcm->current_core->rev < 5)
2458                 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2459
2460         value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2461         value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2462         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2463         value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2464         value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2465         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2466
2467         value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2468         value32 |= 0x100000;
2469         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2470
2471         if (bcm43xx_using_pio(bcm)) {
2472                 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2473                 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2474                 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2475                 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2476                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2477         }
2478
2479         /* Probe Response Timeout value */
2480         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2481         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2482
2483         /* Initially set the wireless operation mode. */
2484         bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
2485
2486         if (bcm->current_core->rev < 3) {
2487                 bcm43xx_write16(bcm, 0x060E, 0x0000);
2488                 bcm43xx_write16(bcm, 0x0610, 0x8000);
2489                 bcm43xx_write16(bcm, 0x0604, 0x0000);
2490                 bcm43xx_write16(bcm, 0x0606, 0x0200);
2491         } else {
2492                 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2493                 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2494         }
2495         bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2496         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2497         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2498         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2499         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2500         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2501         bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2502
2503         value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2504         value32 |= 0x00100000;
2505         bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2506
2507         bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2508
2509         assert(err == 0);
2510         dprintk(KERN_INFO PFX "Chip initialized\n");
2511 out:
2512         return err;
2513
2514 err_radio_off:
2515         bcm43xx_radio_turn_off(bcm);
2516 err_gpio_cleanup:
2517         bcm43xx_gpio_cleanup(bcm);
2518 err_release_fw:
2519         bcm43xx_release_firmware(bcm, 1);
2520         goto out;
2521 }
2522
2523 /* Validate chip access
2524  * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2525 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2526 {
2527         u32 value;
2528         u32 shm_backup;
2529
2530         shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2531         bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2532         if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2533                 goto error;
2534         bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2535         if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2536                 goto error;
2537         bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2538
2539         value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2540         if ((value | 0x80000000) != 0x80000400)
2541                 goto error;
2542
2543         value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2544         if (value != 0x00000000)
2545                 goto error;
2546
2547         return 0;
2548 error:
2549         printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2550         return -ENODEV;
2551 }
2552
2553 static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2554 {
2555         /* Initialize a "phyinfo" structure. The structure is already
2556          * zeroed out.
2557          * This is called on insmod time to initialize members.
2558          */
2559         phy->savedpctlreg = 0xFFFF;
2560         spin_lock_init(&phy->lock);
2561 }
2562
2563 static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2564 {
2565         /* Initialize a "radioinfo" structure. The structure is already
2566          * zeroed out.
2567          * This is called on insmod time to initialize members.
2568          */
2569         radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2570         radio->channel = 0xFF;
2571         radio->initial_channel = 0xFF;
2572 }
2573
2574 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2575 {
2576         int err, i;
2577         int current_core;
2578         u32 core_vendor, core_id, core_rev;
2579         u32 sb_id_hi, chip_id_32 = 0;
2580         u16 pci_device, chip_id_16;
2581         u8 core_count;
2582
2583         memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2584         memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2585         memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2586                                     * BCM43xx_MAX_80211_CORES);
2587         memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2588                                         * BCM43xx_MAX_80211_CORES);
2589         bcm->nr_80211_available = 0;
2590         bcm->current_core = NULL;
2591         bcm->active_80211_core = NULL;
2592
2593         /* map core 0 */
2594         err = _switch_core(bcm, 0);
2595         if (err)
2596                 goto out;
2597
2598         /* fetch sb_id_hi from core information registers */
2599         sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2600
2601         core_id = (sb_id_hi & 0x8FF0) >> 4;
2602         core_rev = (sb_id_hi & 0x7000) >> 8;
2603         core_rev |= (sb_id_hi & 0xF);
2604         core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2605
2606         /* if present, chipcommon is always core 0; read the chipid from it */
2607         if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2608                 chip_id_32 = bcm43xx_read32(bcm, 0);
2609                 chip_id_16 = chip_id_32 & 0xFFFF;
2610                 bcm->core_chipcommon.available = 1;
2611                 bcm->core_chipcommon.id = core_id;
2612                 bcm->core_chipcommon.rev = core_rev;
2613                 bcm->core_chipcommon.index = 0;
2614                 /* While we are at it, also read the capabilities. */
2615                 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2616         } else {
2617                 /* without a chipCommon, use a hard coded table. */
2618                 pci_device = bcm->pci_dev->device;
2619                 if (pci_device == 0x4301)
2620                         chip_id_16 = 0x4301;
2621                 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2622                         chip_id_16 = 0x4307;
2623                 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2624                         chip_id_16 = 0x4402;
2625                 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2626                         chip_id_16 = 0x4610;
2627                 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2628                         chip_id_16 = 0x4710;
2629 #ifdef CONFIG_BCM947XX
2630                 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2631                         chip_id_16 = 0x4309;
2632 #endif
2633                 else {
2634                         printk(KERN_ERR PFX "Could not determine Chip ID\n");
2635                         return -ENODEV;
2636                 }
2637         }
2638
2639         /* ChipCommon with Core Rev >=4 encodes number of cores,
2640          * otherwise consult hardcoded table */
2641         if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2642                 core_count = (chip_id_32 & 0x0F000000) >> 24;
2643         } else {
2644                 switch (chip_id_16) {
2645                         case 0x4610:
2646                         case 0x4704:
2647                         case 0x4710:
2648                                 core_count = 9;
2649                                 break;
2650                         case 0x4310:
2651                                 core_count = 8;
2652                                 break;
2653                         case 0x5365:
2654                                 core_count = 7;
2655                                 break;
2656                         case 0x4306:
2657                                 core_count = 6;
2658                                 break;
2659                         case 0x4301:
2660                         case 0x4307:
2661                                 core_count = 5;
2662                                 break;
2663                         case 0x4402:
2664                                 core_count = 3;
2665                                 break;
2666                         default:
2667                                 /* SOL if we get here */
2668                                 assert(0);
2669                                 core_count = 1;
2670                 }
2671         }
2672
2673         bcm->chip_id = chip_id_16;
2674         bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
2675         bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
2676
2677         dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2678                 bcm->chip_id, bcm->chip_rev);
2679         dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2680         if (bcm->core_chipcommon.available) {
2681                 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2682                         core_id, core_rev, core_vendor);
2683                 current_core = 1;
2684         } else
2685                 current_core = 0;
2686         for ( ; current_core < core_count; current_core++) {
2687                 struct bcm43xx_coreinfo *core;
2688                 struct bcm43xx_coreinfo_80211 *ext_80211;
2689
2690                 err = _switch_core(bcm, current_core);
2691                 if (err)
2692                         goto out;
2693                 /* Gather information */
2694                 /* fetch sb_id_hi from core information registers */
2695                 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2696
2697                 /* extract core_id, core_rev, core_vendor */
2698                 core_id = (sb_id_hi & 0x8FF0) >> 4;
2699                 core_rev = ((sb_id_hi & 0xF) | ((sb_id_hi & 0x7000) >> 8));
2700                 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2701
2702                 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2703                         current_core, core_id, core_rev, core_vendor);
2704
2705                 core = NULL;
2706                 switch (core_id) {
2707                 case BCM43xx_COREID_PCI:
2708                 case BCM43xx_COREID_PCIE:
2709                         core = &bcm->core_pci;
2710                         if (core->available) {
2711                                 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2712                                 continue;
2713                         }
2714                         break;
2715                 case BCM43xx_COREID_80211:
2716                         for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2717                                 core = &(bcm->core_80211[i]);
2718                                 ext_80211 = &(bcm->core_80211_ext[i]);
2719                                 if (!core->available)
2720                                         break;
2721                                 core = NULL;
2722                         }
2723                         if (!core) {
2724                                 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2725                                        BCM43xx_MAX_80211_CORES);
2726                                 continue;
2727                         }
2728                         if (i != 0) {
2729                                 /* More than one 80211 core is only supported
2730                                  * by special chips.
2731                                  * There are chips with two 80211 cores, but with
2732                                  * dangling pins on the second core. Be careful
2733                                  * and ignore these cores here.
2734                                  */
2735                                 if (bcm->pci_dev->device != 0x4324) {
2736                                         dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2737                                         continue;
2738                                 }
2739                         }
2740                         switch (core_rev) {
2741                         case 2:
2742                         case 4:
2743                         case 5:
2744                         case 6:
2745                         case 7:
2746                         case 9:
2747                         case 10:
2748                                 break;
2749                         default:
2750                                 printk(KERN_WARNING PFX
2751                                        "Unsupported 80211 core revision %u\n",
2752                                        core_rev);
2753                         }
2754                         bcm->nr_80211_available++;
2755                         core->priv = ext_80211;
2756                         bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2757                         bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2758                         break;
2759                 case BCM43xx_COREID_CHIPCOMMON:
2760                         printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2761                         break;
2762                 }
2763                 if (core) {
2764                         core->available = 1;
2765                         core->id = core_id;
2766                         core->rev = core_rev;
2767                         core->index = current_core;
2768                 }
2769         }
2770
2771         if (!bcm->core_80211[0].available) {
2772                 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2773                 err = -ENODEV;
2774                 goto out;
2775         }
2776
2777         err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2778
2779         assert(err == 0);
2780 out:
2781         return err;
2782 }
2783
2784 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2785 {
2786         const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2787         u8 *bssid = bcm->ieee->bssid;
2788
2789         switch (bcm->ieee->iw_mode) {
2790         case IW_MODE_ADHOC:
2791                 random_ether_addr(bssid);
2792                 break;
2793         case IW_MODE_MASTER:
2794         case IW_MODE_INFRA:
2795         case IW_MODE_REPEAT:
2796         case IW_MODE_SECOND:
2797         case IW_MODE_MONITOR:
2798                 memcpy(bssid, mac, ETH_ALEN);
2799                 break;
2800         default:
2801                 assert(0);
2802         }
2803 }
2804
2805 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2806                                       u16 rate,
2807                                       int is_ofdm)
2808 {
2809         u16 offset;
2810
2811         if (is_ofdm) {
2812                 offset = 0x480;
2813                 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2814         }
2815         else {
2816                 offset = 0x4C0;
2817                 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2818         }
2819         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2820                             bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2821 }
2822
2823 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2824 {
2825         switch (bcm43xx_current_phy(bcm)->type) {
2826         case BCM43xx_PHYTYPE_A:
2827         case BCM43xx_PHYTYPE_G:
2828                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2829                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2830                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2831                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2832                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2833                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2834                 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2835         case BCM43xx_PHYTYPE_B:
2836                 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2837                 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2838                 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2839                 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2840                 break;
2841         default:
2842                 assert(0);
2843         }
2844 }
2845
2846 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2847 {
2848         bcm43xx_chip_cleanup(bcm);
2849         bcm43xx_pio_free(bcm);
2850         bcm43xx_dma_free(bcm);
2851
2852         bcm->current_core->initialized = 0;
2853 }
2854
2855 /* http://bcm-specs.sipsolutions.net/80211Init */
2856 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
2857                                       int active_wlcore)
2858 {
2859         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2860         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2861         u32 ucodeflags;
2862         int err;
2863         u32 sbimconfiglow;
2864         u8 limit;
2865
2866         if (bcm->core_pci.rev <= 5 && bcm->core_pci.id != BCM43xx_COREID_PCIE) {
2867                 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2868                 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2869                 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2870                 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2871                         sbimconfiglow |= 0x32;
2872                 else
2873                         sbimconfiglow |= 0x53;
2874                 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2875         }
2876
2877         bcm43xx_phy_calibrate(bcm);
2878         err = bcm43xx_chip_init(bcm);
2879         if (err)
2880                 goto out;
2881
2882         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2883         ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2884
2885         if (0 /*FIXME: which condition has to be used here? */)
2886                 ucodeflags |= 0x00000010;
2887
2888         /* HW decryption needs to be set now */
2889         ucodeflags |= 0x40000000;
2890
2891         if (phy->type == BCM43xx_PHYTYPE_G) {
2892                 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2893                 if (phy->rev == 1)
2894                         ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2895                 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2896                         ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2897         } else if (phy->type == BCM43xx_PHYTYPE_B) {
2898                 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2899                 if (phy->rev >= 2 && radio->version == 0x2050)
2900                         ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2901         }
2902
2903         if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2904                                              BCM43xx_UCODEFLAGS_OFFSET)) {
2905                 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2906                                     BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2907         }
2908
2909         /* Short/Long Retry Limit.
2910          * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2911          * the chip-internal counter.
2912          */
2913         limit = limit_value(modparam_short_retry, 0, 0xF);
2914         bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2915         limit = limit_value(modparam_long_retry, 0, 0xF);
2916         bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2917
2918         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2919         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2920
2921         bcm43xx_rate_memory_init(bcm);
2922
2923         /* Minimum Contention Window */
2924         if (phy->type == BCM43xx_PHYTYPE_B)
2925                 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2926         else
2927                 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2928         /* Maximum Contention Window */
2929         bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2930
2931         bcm43xx_gen_bssid(bcm);
2932         bcm43xx_write_mac_bssid_templates(bcm);
2933
2934         if (bcm->current_core->rev >= 5)
2935                 bcm43xx_write16(bcm, 0x043C, 0x000C);
2936
2937         if (active_wlcore) {
2938                 if (bcm43xx_using_pio(bcm)) {
2939                         err = bcm43xx_pio_init(bcm);
2940                 } else {
2941                         err = bcm43xx_dma_init(bcm);
2942                         if (err == -ENOSYS)
2943                                 err = bcm43xx_pio_init(bcm);
2944                 }
2945                 if (err)
2946                         goto err_chip_cleanup;
2947         }
2948         bcm43xx_write16(bcm, 0x0612, 0x0050);
2949         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2950         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2951
2952         if (active_wlcore) {
2953                 if (radio->initial_channel != 0xFF)
2954                         bcm43xx_radio_selectchannel(bcm, radio->initial_channel, 0);
2955         }
2956
2957         /* Don't enable MAC/IRQ here, as it will race with the IRQ handler.
2958          * We enable it later.
2959          */
2960         bcm->current_core->initialized = 1;
2961 out:
2962         return err;
2963
2964 err_chip_cleanup:
2965         bcm43xx_chip_cleanup(bcm);
2966         goto out;
2967 }
2968
2969 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2970 {
2971         int err;
2972         u16 pci_status;
2973
2974         err = bcm43xx_pctl_set_crystal(bcm, 1);
2975         if (err)
2976                 goto out;
2977         err = bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2978         if (err)
2979                 goto out;
2980         err = bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2981
2982 out:
2983         return err;
2984 }
2985
2986 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2987 {
2988         bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2989         bcm43xx_pctl_set_crystal(bcm, 0);
2990 }
2991
2992 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2993                                             u32 address,
2994                                             u32 data)
2995 {
2996         bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2997         bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2998 }
2999
3000 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
3001 {
3002         int err = 0;
3003
3004         bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3005
3006         if (bcm->core_chipcommon.available) {
3007                 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
3008                 if (err)
3009                         goto out;
3010
3011                 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3012
3013                 /* this function is always called when a PCI core is mapped */
3014                 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3015                 if (err)
3016                         goto out;
3017         } else
3018                 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3019
3020         bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
3021
3022 out:
3023         return err;
3024 }
3025
3026 static u32 bcm43xx_pcie_reg_read(struct bcm43xx_private *bcm, u32 address)
3027 {
3028         bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3029         return bcm43xx_read32(bcm, BCM43xx_PCIECORE_REG_DATA);
3030 }
3031
3032 static void bcm43xx_pcie_reg_write(struct bcm43xx_private *bcm, u32 address,
3033                                     u32 data)
3034 {
3035         bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3036         bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_DATA, data);
3037 }
3038
3039 static void bcm43xx_pcie_mdio_write(struct bcm43xx_private *bcm, u8 dev, u8 reg,
3040                                     u16 data)
3041 {
3042         int i;
3043
3044         bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0x0082);
3045         bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_DATA, BCM43xx_PCIE_MDIO_ST |
3046                         BCM43xx_PCIE_MDIO_WT | (dev << BCM43xx_PCIE_MDIO_DEV) |
3047                         (reg << BCM43xx_PCIE_MDIO_REG) | BCM43xx_PCIE_MDIO_TA |
3048                         data);
3049         udelay(10);
3050
3051         for (i = 0; i < 10; i++) {
3052                 if (bcm43xx_read32(bcm, BCM43xx_PCIECORE_MDIO_CTL) &
3053                     BCM43xx_PCIE_MDIO_TC)
3054                         break;
3055                 msleep(1);
3056         }
3057         bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0);
3058 }
3059
3060 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
3061  * To enable core 0, pass a core_mask of 1<<0
3062  */
3063 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3064                                                   u32 core_mask)
3065 {
3066         u32 backplane_flag_nr;
3067         u32 value;
3068         struct bcm43xx_coreinfo *old_core;
3069         int err = 0;
3070
3071         value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
3072         backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
3073
3074         old_core = bcm->current_core;
3075         err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3076         if (err)
3077                 goto out;
3078
3079         if (bcm->current_core->rev < 6 &&
3080                 bcm->current_core->id == BCM43xx_COREID_PCI) {
3081                 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3082                 value |= (1 << backplane_flag_nr);
3083                 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
3084         } else {
3085                 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
3086                 if (err) {
3087                         printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3088                         goto out_switch_back;
3089                 }
3090                 value |= core_mask << 8;
3091                 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
3092                 if (err) {
3093                         printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3094                         goto out_switch_back;
3095                 }
3096         }
3097
3098         if (bcm->current_core->id == BCM43xx_COREID_PCI) {
3099                 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3100                 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3101                 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3102
3103                 if (bcm->current_core->rev < 5) {
3104                         value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3105                         value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3106                                  & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3107                         value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3108                                  & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3109                         bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3110                         err = bcm43xx_pcicore_commit_settings(bcm);
3111                         assert(err == 0);
3112                 } else if (bcm->current_core->rev >= 11) {
3113                         value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3114                         value |= BCM43xx_SBTOPCI2_MEMREAD_MULTI;
3115                         bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3116                 }
3117         } else {
3118                 if (bcm->current_core->rev == 0 || bcm->current_core->rev == 1) {
3119                         value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_TLP_WORKAROUND);
3120                         value |= 0x8;
3121                         bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_TLP_WORKAROUND,
3122                                                value);
3123                 }
3124                 if (bcm->current_core->rev == 0) {
3125                         bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3126                                                 BCM43xx_SERDES_RXTIMER, 0x8128);
3127                         bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3128                                                 BCM43xx_SERDES_CDR, 0x0100);
3129                         bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3130                                                 BCM43xx_SERDES_CDR_BW, 0x1466);
3131                 } else if (bcm->current_core->rev == 1) {
3132                         value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_DLLP_LINKCTL);
3133                         value |= 0x40;
3134                         bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_DLLP_LINKCTL,
3135                                                value);
3136                 }
3137         }
3138 out_switch_back:
3139         err = bcm43xx_switch_core(bcm, old_core);
3140 out:
3141         return err;
3142 }
3143
3144 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3145 {
3146         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3147
3148         if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3149                 return;
3150
3151         bcm43xx_mac_suspend(bcm);
3152         bcm43xx_phy_lo_g_measure(bcm);
3153         bcm43xx_mac_enable(bcm);
3154 }
3155
3156 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3157 {
3158         bcm43xx_phy_lo_mark_all_unused(bcm);
3159         if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3160                 bcm43xx_mac_suspend(bcm);
3161                 bcm43xx_calc_nrssi_slope(bcm);
3162                 bcm43xx_mac_enable(bcm);
3163         }
3164 }
3165
3166 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3167 {
3168         /* Update device statistics. */
3169         bcm43xx_calculate_link_quality(bcm);
3170 }
3171
3172 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3173 {
3174         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3175         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3176
3177         if (phy->type == BCM43xx_PHYTYPE_G) {
3178                 //TODO: update_aci_moving_average
3179                 if (radio->aci_enable && radio->aci_wlan_automatic) {
3180                         bcm43xx_mac_suspend(bcm);
3181                         if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3182                                 if (0 /*TODO: bunch of conditions*/) {
3183                                         bcm43xx_radio_set_interference_mitigation(bcm,
3184                                                                                   BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3185                                 }
3186                         } else if (1/*TODO*/) {
3187                                 /*
3188                                 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3189                                         bcm43xx_radio_set_interference_mitigation(bcm,
3190                                                                                   BCM43xx_RADIO_INTERFMODE_NONE);
3191                                 }
3192                                 */
3193                         }
3194                         bcm43xx_mac_enable(bcm);
3195                 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3196                            phy->rev == 1) {
3197                         //TODO: implement rev1 workaround
3198                 }
3199         }
3200         bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3201         //TODO for APHY (temperature?)
3202 }
3203
3204 static void do_periodic_work(struct bcm43xx_private *bcm)
3205 {
3206         if (bcm->periodic_state % 8 == 0)
3207                 bcm43xx_periodic_every120sec(bcm);
3208         if (bcm->periodic_state % 4 == 0)
3209                 bcm43xx_periodic_every60sec(bcm);
3210         if (bcm->periodic_state % 2 == 0)
3211                 bcm43xx_periodic_every30sec(bcm);
3212         bcm43xx_periodic_every15sec(bcm);
3213
3214         schedule_delayed_work(&bcm->periodic_work, HZ * 15);
3215 }
3216
3217 static void bcm43xx_periodic_work_handler(struct work_struct *work)
3218 {
3219         struct bcm43xx_private *bcm =
3220                 container_of(work, struct bcm43xx_private, periodic_work.work);
3221         struct net_device *net_dev = bcm->net_dev;
3222         unsigned long flags;
3223         u32 savedirqs = 0;
3224         unsigned long orig_trans_start = 0;
3225
3226         mutex_lock(&bcm->mutex);
3227         if (unlikely(bcm->periodic_state % 4 == 0)) {
3228                 /* Periodic work will take a long time, so we want it to
3229                  * be preemtible.
3230                  */
3231
3232                 netif_tx_lock_bh(net_dev);
3233                 /* We must fake a started transmission here, as we are going to
3234                  * disable TX. If we wouldn't fake a TX, it would be possible to
3235                  * trigger the netdev watchdog, if the last real TX is already
3236                  * some time on the past (slightly less than 5secs)
3237                  */
3238                 orig_trans_start = net_dev->trans_start;
3239                 net_dev->trans_start = jiffies;
3240                 netif_stop_queue(net_dev);
3241                 netif_tx_unlock_bh(net_dev);
3242
3243                 spin_lock_irqsave(&bcm->irq_lock, flags);
3244                 bcm43xx_mac_suspend(bcm);
3245                 if (bcm43xx_using_pio(bcm))
3246                         bcm43xx_pio_freeze_txqueues(bcm);
3247                 savedirqs = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3248                 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3249                 bcm43xx_synchronize_irq(bcm);
3250         } else {
3251                 /* Periodic work should take short time, so we want low
3252                  * locking overhead.
3253                  */
3254                 spin_lock_irqsave(&bcm->irq_lock, flags);
3255         }
3256
3257         do_periodic_work(bcm);
3258
3259         if (unlikely(bcm->periodic_state % 4 == 0)) {
3260                 spin_lock_irqsave(&bcm->irq_lock, flags);
3261                 tasklet_enable(&bcm->isr_tasklet);
3262                 bcm43xx_interrupt_enable(bcm, savedirqs);
3263                 if (bcm43xx_using_pio(bcm))
3264                         bcm43xx_pio_thaw_txqueues(bcm);
3265                 bcm43xx_mac_enable(bcm);
3266                 netif_wake_queue(bcm->net_dev);
3267                 net_dev->trans_start = orig_trans_start;
3268         }
3269         mmiowb();
3270         bcm->periodic_state++;
3271         spin_unlock_irqrestore(&bcm->irq_lock, flags);
3272         mutex_unlock(&bcm->mutex);
3273 }
3274
3275 void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3276 {
3277         cancel_rearming_delayed_work(&bcm->periodic_work);
3278 }
3279
3280 void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3281 {
3282         struct delayed_work *work = &bcm->periodic_work;
3283
3284         assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
3285         INIT_DELAYED_WORK(work, bcm43xx_periodic_work_handler);
3286         schedule_delayed_work(work, 0);
3287 }
3288
3289 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3290 {
3291         bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3292                                                   0x0056) * 2;
3293         bcm43xx_clear_keys(bcm);
3294 }
3295
3296 static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
3297 {
3298         struct bcm43xx_private *bcm = (struct bcm43xx_private *)rng->priv;
3299         unsigned long flags;
3300
3301         spin_lock_irqsave(&(bcm)->irq_lock, flags);
3302         *data = bcm43xx_read16(bcm, BCM43xx_MMIO_RNG);
3303         spin_unlock_irqrestore(&(bcm)->irq_lock, flags);
3304
3305         return (sizeof(u16));
3306 }
3307
3308 static void bcm43xx_rng_exit(struct bcm43xx_private *bcm)
3309 {
3310         hwrng_unregister(&bcm->rng);
3311 }
3312
3313 static int bcm43xx_rng_init(struct bcm43xx_private *bcm)
3314 {
3315         int err;
3316
3317         snprintf(bcm->rng_name, ARRAY_SIZE(bcm->rng_name),
3318                  "%s_%s", KBUILD_MODNAME, bcm->net_dev->name);
3319         bcm->rng.name = bcm->rng_name;
3320         bcm->rng.data_read = bcm43xx_rng_read;
3321         bcm->rng.priv = (unsigned long)bcm;
3322         err = hwrng_register(&bcm->rng);
3323         if (err)
3324                 printk(KERN_ERR PFX "RNG init failed (%d)\n", err);
3325
3326         return err;
3327 }
3328
3329 static int bcm43xx_shutdown_all_wireless_cores(struct bcm43xx_private *bcm)
3330 {
3331         int ret = 0;
3332         int i, err;
3333         struct bcm43xx_coreinfo *core;
3334
3335         bcm43xx_set_status(bcm, BCM43xx_STAT_SHUTTINGDOWN);
3336         for (i = 0; i < bcm->nr_80211_available; i++) {
3337                 core = &(bcm->core_80211[i]);
3338                 assert(core->available);
3339                 if (!core->initialized)
3340                         continue;
3341                 err = bcm43xx_switch_core(bcm, core);
3342                 if (err) {
3343                         dprintk(KERN_ERR PFX "shutdown_all_wireless_cores "
3344                                              "switch_core failed (%d)\n", err);
3345                         ret = err;
3346                         continue;
3347                 }
3348                 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3349                 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
3350                 bcm43xx_wireless_core_cleanup(bcm);
3351                 if (core == bcm->active_80211_core)
3352                         bcm->active_80211_core = NULL;
3353         }
3354         free_irq(bcm->irq, bcm);
3355         bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3356
3357         return ret;
3358 }
3359
3360 /* This is the opposite of bcm43xx_init_board() */
3361 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3362 {
3363         bcm43xx_rng_exit(bcm);
3364         bcm43xx_sysfs_unregister(bcm);
3365         bcm43xx_periodic_tasks_delete(bcm);
3366
3367         mutex_lock(&(bcm)->mutex);
3368         bcm43xx_shutdown_all_wireless_cores(bcm);
3369         bcm43xx_pctl_set_crystal(bcm, 0);
3370         mutex_unlock(&(bcm)->mutex);
3371 }
3372
3373 static void prepare_phydata_for_init(struct bcm43xx_phyinfo *phy)
3374 {
3375         phy->antenna_diversity = 0xFFFF;
3376         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3377         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3378
3379         /* Flags */
3380         phy->calibrated = 0;
3381         phy->is_locked = 0;
3382
3383         if (phy->_lo_pairs) {
3384                 memset(phy->_lo_pairs, 0,
3385                        sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT);
3386         }
3387         memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3388 }
3389
3390 static void prepare_radiodata_for_init(struct bcm43xx_private *bcm,
3391                                        struct bcm43xx_radioinfo *radio)
3392 {
3393         int i;
3394
3395         /* Set default attenuation values. */
3396         radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
3397         radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
3398         radio->txctl1 = bcm43xx_default_txctl1(bcm);
3399         radio->txctl2 = 0xFFFF;
3400         radio->txpwr_offset = 0;
3401
3402         /* NRSSI */
3403         radio->nrssislope = 0;
3404         for (i = 0; i < ARRAY_SIZE(radio->nrssi); i++)
3405                 radio->nrssi[i] = -1000;
3406         for (i = 0; i < ARRAY_SIZE(radio->nrssi_lt); i++)
3407                 radio->nrssi_lt[i] = i;
3408
3409         radio->lofcal = 0xFFFF;
3410         radio->initval = 0xFFFF;
3411
3412         radio->aci_enable = 0;
3413         radio->aci_wlan_automatic = 0;
3414         radio->aci_hw_rssi = 0;
3415 }
3416
3417 static void prepare_priv_for_init(struct bcm43xx_private *bcm)
3418 {
3419         int i;
3420         struct bcm43xx_coreinfo *core;
3421         struct bcm43xx_coreinfo_80211 *wlext;
3422
3423         assert(!bcm->active_80211_core);
3424
3425         bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3426
3427         /* Flags */
3428         bcm->was_initialized = 0;
3429         bcm->reg124_set_0x4 = 0;
3430
3431         /* Stats */
3432         memset(&bcm->stats, 0, sizeof(bcm->stats));
3433
3434         /* Wireless core data */
3435         for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3436                 core = &(bcm->core_80211[i]);
3437                 wlext = core->priv;
3438
3439                 if (!core->available)
3440                         continue;
3441                 assert(wlext == &(bcm->core_80211_ext[i]));
3442
3443                 prepare_phydata_for_init(&wlext->phy);
3444                 prepare_radiodata_for_init(bcm, &wlext->radio);
3445         }
3446
3447         /* IRQ related flags */
3448         bcm->irq_reason = 0;
3449         memset(bcm->dma_reason, 0, sizeof(bcm->dma_reason));
3450         bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3451
3452         bcm->mac_suspended = 1;
3453
3454         /* Noise calculation context */
3455         memset(&bcm->noisecalc, 0, sizeof(bcm->noisecalc));
3456
3457         /* Periodic work context */
3458         bcm->periodic_state = 0;
3459 }
3460
3461 static int wireless_core_up(struct bcm43xx_private *bcm,
3462                             int active_wlcore)
3463 {
3464         int err;
3465
3466         if (!bcm43xx_core_enabled(bcm))
3467                 bcm43xx_wireless_core_reset(bcm, 1);
3468         if (!active_wlcore)
3469                 bcm43xx_wireless_core_mark_inactive(bcm);
3470         err = bcm43xx_wireless_core_init(bcm, active_wlcore);
3471         if (err)
3472                 goto out;
3473         if (!active_wlcore)
3474                 bcm43xx_radio_turn_off(bcm);
3475 out:
3476         return err;
3477 }
3478
3479 /* Select and enable the "to be used" wireless core.
3480  * Locking: bcm->mutex must be aquired before calling this.
3481  *          bcm->irq_lock must not be aquired.
3482  */
3483 int bcm43xx_select_wireless_core(struct bcm43xx_private *bcm,
3484                                  int phytype)
3485 {
3486         int i, err;
3487         struct bcm43xx_coreinfo *active_core = NULL;
3488         struct bcm43xx_coreinfo_80211 *active_wlext = NULL;
3489         struct bcm43xx_coreinfo *core;
3490         struct bcm43xx_coreinfo_80211 *wlext;
3491         int adjust_active_sbtmstatelow = 0;
3492
3493         might_sleep();
3494
3495         if (phytype < 0) {
3496                 /* If no phytype is requested, select the first core. */
3497                 assert(bcm->core_80211[0].available);
3498                 wlext = bcm->core_80211[0].priv;
3499                 phytype = wlext->phy.type;
3500         }
3501         /* Find the requested core. */
3502         for (i = 0; i < bcm->nr_80211_available; i++) {
3503                 core = &(bcm->core_80211[i]);
3504                 wlext = core->priv;
3505                 if (wlext->phy.type == phytype) {
3506                         active_core = core;
3507                         active_wlext = wlext;
3508                         break;
3509                 }
3510         }
3511         if (!active_core)
3512                 return -ESRCH; /* No such PHYTYPE on this board. */
3513
3514         if (bcm->active_80211_core) {
3515                 /* We already selected a wl core in the past.
3516                  * So first clean up everything.
3517                  */
3518                 dprintk(KERN_INFO PFX "select_wireless_core: cleanup\n");
3519                 ieee80211softmac_stop(bcm->net_dev);
3520                 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3521                 err = bcm43xx_disable_interrupts_sync(bcm);
3522                 assert(!err);
3523                 tasklet_enable(&bcm->isr_tasklet);
3524                 err = bcm43xx_shutdown_all_wireless_cores(bcm);
3525                 if (err)
3526                         goto error;
3527                 /* Ok, everything down, continue to re-initialize. */
3528                 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3529         }
3530
3531         /* Reset all data structures. */
3532         prepare_priv_for_init(bcm);
3533
3534         err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3535         if (err)
3536                 goto error;
3537
3538         /* Mark all unused cores "inactive". */
3539         for (i = 0; i < bcm->nr_80211_available; i++) {
3540                 core = &(bcm->core_80211[i]);
3541                 wlext = core->priv;
3542
3543                 if (core == active_core)
3544                         continue;
3545                 err = bcm43xx_switch_core(bcm, core);
3546                 if (err) {
3547                         dprintk(KERN_ERR PFX "Could not switch to inactive "
3548                                              "802.11 core (%d)\n", err);
3549                         goto error;
3550                 }
3551                 err = wireless_core_up(bcm, 0);
3552                 if (err) {
3553                         dprintk(KERN_ERR PFX "core_up for inactive 802.11 core "
3554                                              "failed (%d)\n", err);
3555                         goto error;
3556                 }
3557                 adjust_active_sbtmstatelow = 1;
3558         }
3559
3560         /* Now initialize the active 802.11 core. */
3561         err = bcm43xx_switch_core(bcm, active_core);
3562         if (err) {
3563                 dprintk(KERN_ERR PFX "Could not switch to active "
3564                                      "802.11 core (%d)\n", err);
3565                 goto error;
3566         }
3567         if (adjust_active_sbtmstatelow &&
3568             active_wlext->phy.type == BCM43xx_PHYTYPE_G) {
3569                 u32 sbtmstatelow;
3570
3571                 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
3572                 sbtmstatelow |= 0x20000000;
3573                 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
3574         }
3575         err = wireless_core_up(bcm, 1);
3576         if (err) {
3577                 dprintk(KERN_ERR PFX "core_up for active 802.11 core "
3578                                      "failed (%d)\n", err);
3579                 goto error;
3580         }
3581         err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3582         if (err)
3583                 goto error;
3584         bcm->active_80211_core = active_core;
3585
3586         bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3587         bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3588         bcm43xx_security_init(bcm);
3589         drain_txstatus_queue(bcm);
3590         ieee80211softmac_start(bcm->net_dev);
3591
3592         /* Let's go! Be careful after enabling the IRQs.
3593          * Don't switch cores, for example.
3594          */
3595         bcm43xx_mac_enable(bcm);
3596         bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3597         err = bcm43xx_initialize_irq(bcm);
3598         if (err)
3599                 goto error;
3600         bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
3601
3602         dprintk(KERN_INFO PFX "Selected 802.11 core (phytype %d)\n",
3603                 active_wlext->phy.type);
3604
3605         return 0;
3606
3607 error:
3608         bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3609         bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
3610         return err;
3611 }
3612
3613 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3614 {
3615         int err;
3616
3617         mutex_lock(&(bcm)->mutex);
3618
3619         tasklet_enable(&bcm->isr_tasklet);
3620         err = bcm43xx_pctl_set_crystal(bcm, 1);
3621         if (err)
3622                 goto err_tasklet;
3623         err = bcm43xx_pctl_init(bcm);
3624         if (err)
3625                 goto err_crystal_off;
3626         err = bcm43xx_select_wireless_core(bcm, -1);
3627         if (err)
3628                 goto err_crystal_off;
3629         err = bcm43xx_sysfs_register(bcm);
3630         if (err)
3631                 goto err_wlshutdown;
3632         err = bcm43xx_rng_init(bcm);
3633         if (err)
3634                 goto err_sysfs_unreg;
3635         bcm43xx_periodic_tasks_setup(bcm);
3636
3637         /*FIXME: This should be handled by softmac instead. */
3638         schedule_delayed_work(&bcm->softmac->associnfo.work, 0);
3639
3640 out:
3641         mutex_unlock(&(bcm)->mutex);
3642
3643         return err;
3644
3645 err_sysfs_unreg:
3646         bcm43xx_sysfs_unregister(bcm);
3647 err_wlshutdown:
3648         bcm43xx_shutdown_all_wireless_cores(bcm);
3649 err_crystal_off:
3650         bcm43xx_pctl_set_crystal(bcm, 0);
3651 err_tasklet:
3652         tasklet_disable(&bcm->isr_tasklet);
3653         goto out;
3654 }
3655
3656 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3657 {
3658         struct pci_dev *pci_dev = bcm->pci_dev;
3659         int i;
3660
3661         bcm43xx_chipset_detach(bcm);
3662         /* Do _not_ access the chip, after it is detached. */
3663         pci_iounmap(pci_dev, bcm->mmio_addr);
3664         pci_release_regions(pci_dev);
3665         pci_disable_device(pci_dev);
3666
3667         /* Free allocated structures/fields */
3668         for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3669                 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3670                 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3671                         kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3672         }
3673 }
3674
3675 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3676 {
3677         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3678         u16 value;
3679         u8 phy_version;
3680         u8 phy_type;
3681         u8 phy_rev;
3682         int phy_rev_ok = 1;
3683         void *p;
3684
3685         value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3686
3687         phy_version = (value & 0xF000) >> 12;
3688         phy_type = (value & 0x0F00) >> 8;
3689         phy_rev = (value & 0x000F);
3690
3691         dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3692                 phy_version, phy_type, phy_rev);
3693
3694         switch (phy_type) {
3695         case BCM43xx_PHYTYPE_A:
3696                 if (phy_rev >= 4)
3697                         phy_rev_ok = 0;
3698                 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3699                  *       if we switch 80211 cores after init is done.
3700                  *       As we do not implement on the fly switching between
3701                  *       wireless cores, I will leave this as a future task.
3702                  */
3703                 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3704                 bcm->ieee->mode = IEEE_A;
3705                 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3706                                        IEEE80211_24GHZ_BAND;
3707                 break;
3708         case BCM43xx_PHYTYPE_B:
3709                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3710                         phy_rev_ok = 0;
3711                 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3712                 bcm->ieee->mode = IEEE_B;
3713                 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3714                 break;
3715         case BCM43xx_PHYTYPE_G:
3716                 if (phy_rev > 8)
3717                         phy_rev_ok = 0;
3718                 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3719                                         IEEE80211_CCK_MODULATION;
3720                 bcm->ieee->mode = IEEE_G;
3721                 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3722                 break;
3723         default:
3724                 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3725                        phy_type);
3726                 return -ENODEV;
3727         };
3728         bcm->ieee->perfect_rssi = RX_RSSI_MAX;
3729         bcm->ieee->worst_rssi = 0;
3730         if (!phy_rev_ok) {
3731                 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3732                        phy_rev);
3733         }
3734
3735         phy->version = phy_version;
3736         phy->type = phy_type;
3737         phy->rev = phy_rev;
3738         if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3739                 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3740                             GFP_KERNEL);
3741                 if (!p)
3742                         return -ENOMEM;
3743                 phy->_lo_pairs = p;
3744         }
3745
3746         return 0;
3747 }
3748
3749 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3750 {
3751         struct pci_dev *pci_dev = bcm->pci_dev;
3752         struct net_device *net_dev = bcm->net_dev;
3753         int err;
3754         int i;
3755         u32 coremask;
3756
3757         err = pci_enable_device(pci_dev);
3758         if (err) {
3759                 printk(KERN_ERR PFX "pci_enable_device() failed\n");
3760                 goto out;
3761         }
3762         err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3763         if (err) {
3764                 printk(KERN_ERR PFX "pci_request_regions() failed\n");
3765                 goto err_pci_disable;
3766         }
3767         /* enable PCI bus-mastering */
3768         pci_set_master(pci_dev);
3769         bcm->mmio_addr = pci_iomap(pci_dev, 0, ~0UL);
3770         if (!bcm->mmio_addr) {
3771                 printk(KERN_ERR PFX "pci_iomap() failed\n");
3772                 err = -EIO;
3773                 goto err_pci_release;
3774         }
3775         net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3776
3777         err = bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3778                                   &bcm->board_vendor);
3779         if (err)
3780                 goto err_iounmap;
3781         err = bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3782                                   &bcm->board_type);
3783         if (err)
3784                 goto err_iounmap;
3785         err = bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3786                                   &bcm->board_revision);
3787         if (err)
3788                 goto err_iounmap;
3789
3790         err = bcm43xx_chipset_attach(bcm);
3791         if (err)
3792                 goto err_iounmap;
3793         err = bcm43xx_pctl_init(bcm);
3794         if (err)
3795                 goto err_chipset_detach;
3796         err = bcm43xx_probe_cores(bcm);
3797         if (err)
3798                 goto err_chipset_detach;
3799
3800         /* Attach all IO cores to the backplane. */
3801         coremask = 0;
3802         for (i = 0; i < bcm->nr_80211_available; i++)
3803                 coremask |= (1 << bcm->core_80211[i].index);
3804         //FIXME: Also attach some non80211 cores?
3805         err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3806         if (err) {
3807                 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3808                 goto err_chipset_detach;
3809         }
3810
3811         err = bcm43xx_sprom_extract(bcm);
3812         if (err)
3813                 goto err_chipset_detach;
3814         err = bcm43xx_leds_init(bcm);
3815         if (err)
3816                 goto err_chipset_detach;
3817
3818         for (i = 0; i < bcm->nr_80211_available; i++) {
3819                 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3820                 assert(err != -ENODEV);
3821                 if (err)
3822                         goto err_80211_unwind;
3823
3824                 /* Enable the selected wireless core.
3825                  * Connect PHY only on the first core.
3826                  */
3827                 bcm43xx_wireless_core_reset(bcm, (i == 0));
3828
3829                 err = bcm43xx_read_phyinfo(bcm);
3830                 if (err && (i == 0))
3831                         goto err_80211_unwind;
3832
3833                 err = bcm43xx_read_radioinfo(bcm);
3834                 if (err && (i == 0))
3835                         goto err_80211_unwind;
3836
3837                 err = bcm43xx_validate_chip(bcm);
3838                 if (err && (i == 0))
3839                         goto err_80211_unwind;
3840
3841                 bcm43xx_radio_turn_off(bcm);
3842                 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3843                 if (err)
3844                         goto err_80211_unwind;
3845                 bcm43xx_wireless_core_disable(bcm);
3846         }
3847         err = bcm43xx_geo_init(bcm);
3848         if (err)
3849                 goto err_80211_unwind;
3850         bcm43xx_pctl_set_crystal(bcm, 0);
3851
3852         /* Set the MAC address in the networking subsystem */
3853         if (is_valid_ether_addr(bcm->sprom.et1macaddr))
3854                 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3855         else
3856                 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3857
3858         snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3859                  "Broadcom %04X", bcm->chip_id);
3860
3861         assert(err == 0);
3862 out:
3863         return err;
3864
3865 err_80211_unwind:
3866         for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3867                 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3868                 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3869                         kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3870         }
3871 err_chipset_detach:
3872         bcm43xx_chipset_detach(bcm);
3873 err_iounmap:
3874         pci_iounmap(pci_dev, bcm->mmio_addr);
3875 err_pci_release:
3876         pci_release_regions(pci_dev);
3877 err_pci_disable:
3878         pci_disable_device(pci_dev);
3879         printk(KERN_ERR PFX "Unable to attach board\n");
3880         goto out;
3881 }
3882
3883 /* Do the Hardware IO operations to send the txb */
3884 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3885                              struct ieee80211_txb *txb)
3886 {
3887         int err = -ENODEV;
3888
3889         if (bcm43xx_using_pio(bcm))
3890                 err = bcm43xx_pio_tx(bcm, txb);
3891         else
3892                 err = bcm43xx_dma_tx(bcm, txb);
3893         bcm->net_dev->trans_start = jiffies;
3894
3895         return err;
3896 }
3897
3898 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3899                                        u8 channel)
3900 {
3901         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3902         struct bcm43xx_radioinfo *radio;
3903         unsigned long flags;
3904
3905         mutex_lock(&bcm->mutex);
3906         spin_lock_irqsave(&bcm->irq_lock, flags);
3907         if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
3908                 bcm43xx_mac_suspend(bcm);
3909                 bcm43xx_radio_selectchannel(bcm, channel, 0);
3910                 bcm43xx_mac_enable(bcm);
3911         } else {
3912                 radio = bcm43xx_current_radio(bcm);
3913                 radio->initial_channel = channel;
3914         }
3915         spin_unlock_irqrestore(&bcm->irq_lock, flags);
3916         mutex_unlock(&bcm->mutex);
3917 }
3918
3919 /* set_security() callback in struct ieee80211_device */
3920 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3921                                            struct ieee80211_security *sec)
3922 {
3923         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3924         struct ieee80211_security *secinfo = &bcm->ieee->sec;
3925         unsigned long flags;
3926         int keyidx;
3927
3928         dprintk(KERN_INFO PFX "set security called");
3929
3930         mutex_lock(&bcm->mutex);
3931         spin_lock_irqsave(&bcm->irq_lock, flags);
3932
3933         for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3934                 if (sec->flags & (1<<keyidx)) {
3935                         secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3936                         secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3937                         memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3938                 }
3939
3940         if (sec->flags & SEC_ACTIVE_KEY) {
3941                 secinfo->active_key = sec->active_key;
3942                 dprintk(", .active_key = %d", sec->active_key);
3943         }
3944         if (sec->flags & SEC_UNICAST_GROUP) {
3945                 secinfo->unicast_uses_group = sec->unicast_uses_group;
3946                 dprintk(", .unicast_uses_group = %d", sec->unicast_uses_group);
3947         }
3948         if (sec->flags & SEC_LEVEL) {
3949                 secinfo->level = sec->level;
3950                 dprintk(", .level = %d", sec->level);
3951         }
3952         if (sec->flags & SEC_ENABLED) {
3953                 secinfo->enabled = sec->enabled;
3954                 dprintk(", .enabled = %d", sec->enabled);
3955         }
3956         if (sec->flags & SEC_ENCRYPT) {
3957                 secinfo->encrypt = sec->encrypt;
3958                 dprintk(", .encrypt = %d", sec->encrypt);
3959         }
3960         if (sec->flags & SEC_AUTH_MODE) {
3961                 secinfo->auth_mode = sec->auth_mode;
3962                 dprintk(", .auth_mode = %d", sec->auth_mode);
3963         }
3964         dprintk("\n");
3965         if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED &&
3966             !bcm->ieee->host_encrypt) {
3967                 if (secinfo->enabled) {
3968                         /* upload WEP keys to hardware */
3969                         char null_address[6] = { 0 };
3970                         u8 algorithm = 0;
3971                         for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3972                                 if (!(sec->flags & (1<<keyidx)))
3973                                         continue;
3974                                 switch (sec->encode_alg[keyidx]) {
3975                                         case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3976                                         case SEC_ALG_WEP:
3977                                                 algorithm = BCM43xx_SEC_ALGO_WEP;
3978                                                 if (secinfo->key_sizes[keyidx] == 13)
3979                                                         algorithm = BCM43xx_SEC_ALGO_WEP104;
3980                                                 break;
3981                                         case SEC_ALG_TKIP:
3982                                                 FIXME();
3983                                                 algorithm = BCM43xx_SEC_ALGO_TKIP;
3984                                                 break;
3985                                         case SEC_ALG_CCMP:
3986                                                 FIXME();
3987                                                 algorithm = BCM43xx_SEC_ALGO_AES;
3988                                                 break;
3989                                         default:
3990                                                 assert(0);
3991                                                 break;
3992                                 }
3993                                 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3994                                 bcm->key[keyidx].enabled = 1;
3995                                 bcm->key[keyidx].algorithm = algorithm;
3996                         }
3997                 } else
3998                                 bcm43xx_clear_keys(bcm);
3999         }
4000         spin_unlock_irqrestore(&bcm->irq_lock, flags);
4001         mutex_unlock(&bcm->mutex);
4002 }
4003
4004 /* hard_start_xmit() callback in struct ieee80211_device */
4005 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
4006                                              struct net_device *net_dev,
4007                                              int pri)
4008 {
4009         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4010         int err = -ENODEV;
4011         unsigned long flags;
4012
4013         spin_lock_irqsave(&bcm->irq_lock, flags);
4014         if (likely(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED))
4015                 err = bcm43xx_tx(bcm, txb);
4016         spin_unlock_irqrestore(&bcm->irq_lock, flags);
4017
4018         if (unlikely(err))
4019                 return NETDEV_TX_BUSY;
4020         return NETDEV_TX_OK;
4021 }
4022
4023 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
4024 {
4025         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4026         unsigned long flags;
4027
4028         spin_lock_irqsave(&bcm->irq_lock, flags);
4029         bcm43xx_controller_restart(bcm, "TX timeout");
4030         spin_unlock_irqrestore(&bcm->irq_lock, flags);
4031 }
4032
4033 #ifdef CONFIG_NET_POLL_CONTROLLER
4034 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
4035 {
4036         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4037         unsigned long flags;
4038
4039         local_irq_save(flags);
4040         if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED)
4041                 bcm43xx_interrupt_handler(bcm->irq, bcm);
4042         local_irq_restore(flags);
4043 }
4044 #endif /* CONFIG_NET_POLL_CONTROLLER */
4045
4046 static int bcm43xx_net_open(struct net_device *net_dev)
4047 {
4048         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4049
4050         return bcm43xx_init_board(bcm);
4051 }
4052
4053 static int bcm43xx_net_stop(struct net_device *net_dev)
4054 {
4055         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4056         int err;
4057
4058         ieee80211softmac_stop(net_dev);
4059         err = bcm43xx_disable_interrupts_sync(bcm);
4060         assert(!err);
4061         bcm43xx_free_board(bcm);
4062         flush_scheduled_work();
4063
4064         return 0;
4065 }
4066
4067 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
4068                                 struct net_device *net_dev,
4069                                 struct pci_dev *pci_dev)
4070 {
4071         bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
4072         bcm->ieee = netdev_priv(net_dev);
4073         bcm->softmac = ieee80211_priv(net_dev);
4074         bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
4075
4076         bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
4077         bcm->mac_suspended = 1;
4078         bcm->pci_dev = pci_dev;
4079         bcm->net_dev = net_dev;
4080         bcm->bad_frames_preempt = modparam_bad_frames_preempt;
4081         spin_lock_init(&bcm->irq_lock);
4082         spin_lock_init(&bcm->leds_lock);
4083         mutex_init(&bcm->mutex);
4084         tasklet_init(&bcm->isr_tasklet,
4085                      (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
4086                      (unsigned long)bcm);
4087         tasklet_disable_nosync(&bcm->isr_tasklet);
4088         if (modparam_pio)
4089                 bcm->__using_pio = 1;
4090         bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
4091
4092         /* default to sw encryption for now */
4093         bcm->ieee->host_build_iv = 0;
4094         bcm->ieee->host_encrypt = 1;
4095         bcm->ieee->host_decrypt = 1;
4096
4097         bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
4098         bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
4099         bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
4100         bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
4101
4102         return 0;
4103 }
4104
4105 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
4106                                       const struct pci_device_id *ent)
4107 {
4108         struct net_device *net_dev;
4109         struct bcm43xx_private *bcm;
4110         int err;
4111
4112 #ifdef CONFIG_BCM947XX
4113         if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
4114                 return -ENODEV;
4115 #endif
4116
4117 #ifdef DEBUG_SINGLE_DEVICE_ONLY
4118         if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
4119                 return -ENODEV;
4120 #endif
4121
4122         net_dev = alloc_ieee80211softmac(sizeof(*bcm));
4123         if (!net_dev) {
4124                 printk(KERN_ERR PFX
4125                        "could not allocate ieee80211 device %s\n",
4126                        pci_name(pdev));
4127                 err = -ENOMEM;
4128                 goto out;
4129         }
4130         /* initialize the net_device struct */
4131         SET_MODULE_OWNER(net_dev);
4132         SET_NETDEV_DEV(net_dev, &pdev->dev);
4133
4134         net_dev->open = bcm43xx_net_open;
4135         net_dev->stop = bcm43xx_net_stop;
4136         net_dev->tx_timeout = bcm43xx_net_tx_timeout;
4137 #ifdef CONFIG_NET_POLL_CONTROLLER
4138         net_dev->poll_controller = bcm43xx_net_poll_controller;
4139 #endif
4140         net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
4141         net_dev->irq = pdev->irq;
4142         SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
4143
4144         /* initialize the bcm43xx_private struct */
4145         bcm = bcm43xx_priv(net_dev);
4146         memset(bcm, 0, sizeof(*bcm));
4147         err = bcm43xx_init_private(bcm, net_dev, pdev);
4148         if (err)
4149                 goto err_free_netdev;
4150
4151         pci_set_drvdata(pdev, net_dev);
4152
4153         err = bcm43xx_attach_board(bcm);
4154         if (err)
4155                 goto err_free_netdev;
4156
4157         err = register_netdev(net_dev);
4158         if (err) {
4159                 printk(KERN_ERR PFX "Cannot register net device, "
4160                        "aborting.\n");
4161                 err = -ENOMEM;
4162                 goto err_detach_board;
4163         }
4164
4165         bcm43xx_debugfs_add_device(bcm);
4166
4167         assert(err == 0);
4168 out:
4169         return err;
4170
4171 err_detach_board:
4172         bcm43xx_detach_board(bcm);
4173 err_free_netdev:
4174         free_ieee80211softmac(net_dev);
4175         goto out;
4176 }
4177
4178 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
4179 {
4180         struct net_device *net_dev = pci_get_drvdata(pdev);
4181         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4182
4183         bcm43xx_debugfs_remove_device(bcm);
4184         unregister_netdev(net_dev);
4185         bcm43xx_detach_board(bcm);
4186         free_ieee80211softmac(net_dev);
4187 }
4188
4189 /* Hard-reset the chip. Do not call this directly.
4190  * Use bcm43xx_controller_restart()
4191  */
4192 static void bcm43xx_chip_reset(struct work_struct *work)
4193 {
4194         struct bcm43xx_private *bcm =
4195                 container_of(work, struct bcm43xx_private, restart_work);
4196         struct bcm43xx_phyinfo *phy;
4197         int err = -ENODEV;
4198
4199         mutex_lock(&(bcm)->mutex);
4200         if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4201                 bcm43xx_periodic_tasks_delete(bcm);
4202                 phy = bcm43xx_current_phy(bcm);
4203                 err = bcm43xx_select_wireless_core(bcm, phy->type);
4204                 if (!err)
4205                         bcm43xx_periodic_tasks_setup(bcm);
4206         }
4207         mutex_unlock(&(bcm)->mutex);
4208
4209         printk(KERN_ERR PFX "Controller restart%s\n",
4210                (err == 0) ? "ed" : " failed");
4211 }
4212
4213 /* Hard-reset the chip.
4214  * This can be called from interrupt or process context.
4215  * bcm->irq_lock must be locked.
4216  */
4217 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
4218 {
4219         if (bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)
4220                 return;
4221         printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
4222         INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset);
4223         schedule_work(&bcm->restart_work);
4224 }
4225
4226 #ifdef CONFIG_PM
4227
4228 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
4229 {
4230         struct net_device *net_dev = pci_get_drvdata(pdev);
4231         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4232         int err;
4233
4234         dprintk(KERN_INFO PFX "Suspending...\n");
4235
4236         netif_device_detach(net_dev);
4237         bcm->was_initialized = 0;
4238         if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4239                 bcm->was_initialized = 1;
4240                 ieee80211softmac_stop(net_dev);
4241                 err = bcm43xx_disable_interrupts_sync(bcm);
4242                 if (unlikely(err)) {
4243                         dprintk(KERN_ERR PFX "Suspend failed.\n");
4244                         return -EAGAIN;
4245                 }
4246                 bcm->firmware_norelease = 1;
4247                 bcm43xx_free_board(bcm);
4248                 bcm->firmware_norelease = 0;
4249         }
4250         bcm43xx_chipset_detach(bcm);
4251
4252         pci_save_state(pdev);
4253         pci_disable_device(pdev);
4254         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4255
4256         dprintk(KERN_INFO PFX "Device suspended.\n");
4257
4258         return 0;
4259 }
4260
4261 static int bcm43xx_resume(struct pci_dev *pdev)
4262 {
4263         struct net_device *net_dev = pci_get_drvdata(pdev);
4264         struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4265         int err = 0;
4266
4267         dprintk(KERN_INFO PFX "Resuming...\n");
4268
4269         pci_set_power_state(pdev, 0);
4270         err = pci_enable_device(pdev);
4271         if (err) {
4272                 printk(KERN_ERR PFX "Failure with pci_enable_device!\n");
4273                 return err;
4274         }
4275         pci_restore_state(pdev);
4276
4277         bcm43xx_chipset_attach(bcm);
4278         if (bcm->was_initialized)
4279                 err = bcm43xx_init_board(bcm);
4280         if (err) {
4281                 printk(KERN_ERR PFX "Resume failed!\n");
4282                 return err;
4283         }
4284         netif_device_attach(net_dev);
4285
4286         dprintk(KERN_INFO PFX "Device resumed.\n");
4287
4288         return 0;
4289 }
4290
4291 #endif                          /* CONFIG_PM */
4292
4293 static struct pci_driver bcm43xx_pci_driver = {
4294         .name = KBUILD_MODNAME,
4295         .id_table = bcm43xx_pci_tbl,
4296         .probe = bcm43xx_init_one,
4297         .remove = __devexit_p(bcm43xx_remove_one),
4298 #ifdef CONFIG_PM
4299         .suspend = bcm43xx_suspend,
4300         .resume = bcm43xx_resume,
4301 #endif                          /* CONFIG_PM */
4302 };
4303
4304 static int __init bcm43xx_init(void)
4305 {
4306         printk(KERN_INFO KBUILD_MODNAME " driver\n");
4307         bcm43xx_debugfs_init();
4308         return pci_register_driver(&bcm43xx_pci_driver);
4309 }
4310
4311 static void __exit bcm43xx_exit(void)
4312 {
4313         pci_unregister_driver(&bcm43xx_pci_driver);
4314         bcm43xx_debugfs_exit();
4315 }
4316
4317 module_init(bcm43xx_init)
4318 module_exit(bcm43xx_exit)