drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "radio_2057.h"
  36 #include "main.h"
  37
  38 struct nphy_txgains {
  39         u16 txgm[2];
  40         u16 pga[2];
  41         u16 pad[2];
  42         u16 ipa[2];
  43 };
  44
  45 struct nphy_iqcal_params {
  46         u16 txgm;
  47         u16 pga;
  48         u16 pad;
  49         u16 ipa;
  50         u16 cal_gain;
  51         u16 ncorr[5];
  52 };
  53
  54 struct nphy_iq_est {
  55         s32 iq0_prod;
  56         u32 i0_pwr;
  57         u32 q0_pwr;
  58         s32 iq1_prod;
  59         u32 i1_pwr;
  60         u32 q1_pwr;
  61 };
  62
  63 enum b43_nphy_rf_sequence {
  64         B43_RFSEQ_RX2TX,
  65         B43_RFSEQ_TX2RX,
  66         B43_RFSEQ_RESET2RX,
  67         B43_RFSEQ_UPDATE_GAINH,
  68         B43_RFSEQ_UPDATE_GAINL,
  69         B43_RFSEQ_UPDATE_GAINU,
  70 };
  71
  72 enum b43_nphy_rssi_type {
  73         B43_NPHY_RSSI_X = 0,
  74         B43_NPHY_RSSI_Y,
  75         B43_NPHY_RSSI_Z,
  76         B43_NPHY_RSSI_PWRDET,
  77         B43_NPHY_RSSI_TSSI_I,
  78         B43_NPHY_RSSI_TSSI_Q,
  79         B43_NPHY_RSSI_TBD,
  80 };
  81
  82 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
  83 {
  84         enum ieee80211_band band = b43_current_band(dev->wl);
  85         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  86                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
  87 }
  88
  89 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
  90 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
  91 {
  92         return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
  93                 B43_NPHY_RFSEQCA_RXEN_SHIFT;
  94 }
  95
  96 /**************************************************
  97  * RF (just without b43_nphy_rf_control_intc_override)
  98  **************************************************/
  99
 100 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
 101 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 102                                        enum b43_nphy_rf_sequence seq)
 103 {
 104         static const u16 trigger[] = {
 105                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 106                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 107                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 108                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 109                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 110                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 111         };
 112         int i;
 113         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
 114
 115         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 116
 117         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 118                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 119         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 120         for (i = 0; i < 200; i++) {
 121                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 122                         goto ok;
 123                 msleep(1);
 124         }
 125         b43err(dev->wl, "RF sequence status timeout\n");
 126 ok:
 127         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
 128 }
 129
 130 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
 131 static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
 132                                               u16 value, u8 core, bool off,
 133                                               u8 override)
 134 {
 135         const struct nphy_rf_control_override_rev7 *e;
 136         u16 en_addrs[3][2] = {
 137                 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
 138         };
 139         u16 en_addr;
 140         u16 en_mask = field;
 141         u16 val_addr;
 142         u8 i;
 143
 144         /* Remember: we can get NULL! */
 145         e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
 146
 147         for (i = 0; i < 2; i++) {
 148                 if (override >= ARRAY_SIZE(en_addrs)) {
 149                         b43err(dev->wl, "Invalid override value %d\n", override);
 150                         return;
 151                 }
 152                 en_addr = en_addrs[override][i];
 153
 154                 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
 155
 156                 if (off) {
 157                         b43_phy_mask(dev, en_addr, ~en_mask);
 158                         if (e) /* Do it safer, better than wl */
 159                                 b43_phy_mask(dev, val_addr, ~e->val_mask);
 160                 } else {
 161                         if (!core || (core & (1 << i))) {
 162                                 b43_phy_set(dev, en_addr, en_mask);
 163                                 if (e)
 164                                         b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
 165                         }
 166                 }
 167         }
 168 }
 169
 170 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
 171 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
 172                                                 u16 value, u8 core, bool off)
 173 {
 174         int i;
 175         u8 index = fls(field);
 176         u8 addr, en_addr, val_addr;
 177         /* we expect only one bit set */
 178         B43_WARN_ON(field & (~(1 << (index - 1))));
 179
 180         if (dev->phy.rev >= 3) {
 181                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
 182                 for (i = 0; i < 2; i++) {
 183                         if (index == 0 || index == 16) {
 184                                 b43err(dev->wl,
 185                                         "Unsupported RF Ctrl Override call\n");
 186                                 return;
 187                         }
 188
 189                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
 190                         en_addr = B43_PHY_N((i == 0) ?
 191                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
 192                         val_addr = B43_PHY_N((i == 0) ?
 193                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
 194
 195                         if (off) {
 196                                 b43_phy_mask(dev, en_addr, ~(field));
 197                                 b43_phy_mask(dev, val_addr,
 198                                                 ~(rf_ctrl->val_mask));
 199                         } else {
 200                                 if (core == 0 || ((1 << i) & core)) {
 201                                         b43_phy_set(dev, en_addr, field);
 202                                         b43_phy_maskset(dev, val_addr,
 203                                                 ~(rf_ctrl->val_mask),
 204                                                 (value << rf_ctrl->val_shift));
 205                                 }
 206                         }
 207                 }
 208         } else {
 209                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
 210                 if (off) {
 211                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
 212                         value = 0;
 213                 } else {
 214                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
 215                 }
 216
 217                 for (i = 0; i < 2; i++) {
 218                         if (index <= 1 || index == 16) {
 219                                 b43err(dev->wl,
 220                                         "Unsupported RF Ctrl Override call\n");
 221                                 return;
 222                         }
 223
 224                         if (index == 2 || index == 10 ||
 225                             (index >= 13 && index <= 15)) {
 226                                 core = 1;
 227                         }
 228
 229                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
 230                         addr = B43_PHY_N((i == 0) ?
 231                                 rf_ctrl->addr0 : rf_ctrl->addr1);
 232
 233                         if ((1 << i) & core)
 234                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
 235                                                 (value << rf_ctrl->shift));
 236
 237                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
 238                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 239                                         B43_NPHY_RFCTL_CMD_START);
 240                         udelay(1);
 241                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
 242                 }
 243         }
 244 }
 245
 246 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
 247 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
 248                                                 u16 value, u8 core)
 249 {
 250         u8 i, j;
 251         u16 reg, tmp, val;
 252
 253         B43_WARN_ON(dev->phy.rev < 3);
 254         B43_WARN_ON(field > 4);
 255
 256         for (i = 0; i < 2; i++) {
 257                 if ((core == 1 && i == 1) || (core == 2 && !i))
 258                         continue;
 259
 260                 reg = (i == 0) ?
 261                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
 262                 b43_phy_set(dev, reg, 0x400);
 263
 264                 switch (field) {
 265                 case 0:
 266                         b43_phy_write(dev, reg, 0);
 267                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 268                         break;
 269                 case 1:
 270                         if (!i) {
 271                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
 272                                                 0xFC3F, (value << 6));
 273                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
 274                                                 0xFFFE, 1);
 275                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 276                                                 B43_NPHY_RFCTL_CMD_START);
 277                                 for (j = 0; j < 100; j++) {
 278                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
 279                                                 j = 0;
 280                                                 break;
 281                                         }
 282                                         udelay(10);
 283                                 }
 284                                 if (j)
 285                                         b43err(dev->wl,
 286                                                 "intc override timeout\n");
 287                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
 288                                                 0xFFFE);
 289                         } else {
 290                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
 291                                                 0xFC3F, (value << 6));
 292                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 293                                                 0xFFFE, 1);
 294                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 295                                                 B43_NPHY_RFCTL_CMD_RXTX);
 296                                 for (j = 0; j < 100; j++) {
 297                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
 298                                                 j = 0;
 299                                                 break;
 300                                         }
 301                                         udelay(10);
 302                                 }
 303                                 if (j)
 304                                         b43err(dev->wl,
 305                                                 "intc override timeout\n");
 306                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
 307                                                 0xFFFE);
 308                         }
 309                         break;
 310                 case 2:
 311                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 312                                 tmp = 0x0020;
 313                                 val = value << 5;
 314                         } else {
 315                                 tmp = 0x0010;
 316                                 val = value << 4;
 317                         }
 318                         b43_phy_maskset(dev, reg, ~tmp, val);
 319                         break;
 320                 case 3:
 321                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 322                                 tmp = 0x0001;
 323                                 val = value;
 324                         } else {
 325                                 tmp = 0x0004;
 326                                 val = value << 2;
 327                         }
 328                         b43_phy_maskset(dev, reg, ~tmp, val);
 329                         break;
 330                 case 4:
 331                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 332                                 tmp = 0x0002;
 333                                 val = value << 1;
 334                         } else {
 335                                 tmp = 0x0008;
 336                                 val = value << 3;
 337                         }
 338                         b43_phy_maskset(dev, reg, ~tmp, val);
 339                         break;
 340                 }
 341         }
 342 }
 343
 344 /**************************************************
 345  * Various PHY ops
 346  **************************************************/
 347
 348 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 349 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 350                                           const u16 *clip_st)
 351 {
 352         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 353         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 354 }
 355
 356 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 357 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 358 {
 359         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 360         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 361 }
 362
 363 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 364 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 365 {
 366         u16 tmp;
 367
 368         if (dev->dev->core_rev == 16)
 369                 b43_mac_suspend(dev);
 370
 371         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 372         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 373                 B43_NPHY_CLASSCTL_WAITEDEN);
 374         tmp &= ~mask;
 375         tmp |= (val & mask);
 376         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 377
 378         if (dev->dev->core_rev == 16)
 379                 b43_mac_enable(dev);
 380
 381         return tmp;
 382 }
 383
 384 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 385 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 386 {
 387         u16 bbcfg;
 388
 389         b43_phy_force_clock(dev, 1);
 390         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 391         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 392         udelay(1);
 393         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 394         b43_phy_force_clock(dev, 0);
 395         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 396 }
 397
 398 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 399 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 400 {
 401         struct b43_phy *phy = &dev->phy;
 402         struct b43_phy_n *nphy = phy->n;
 403
 404         if (enable) {
 405                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
 406                 if (nphy->deaf_count++ == 0) {
 407                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 408                         b43_nphy_classifier(dev, 0x7, 0);
 409                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 410                         b43_nphy_write_clip_detection(dev, clip);
 411                 }
 412                 b43_nphy_reset_cca(dev);
 413         } else {
 414                 if (--nphy->deaf_count == 0) {
 415                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 416                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 417                 }
 418         }
 419 }
 420
 421 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 422 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 423 {
 424         struct b43_phy_n *nphy = dev->phy.n;
 425
 426         u8 i;
 427         s16 tmp;
 428         u16 data[4];
 429         s16 gain[2];
 430         u16 minmax[2];
 431         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
 432
 433         if (nphy->hang_avoid)
 434                 b43_nphy_stay_in_carrier_search(dev, 1);
 435
 436         if (nphy->gain_boost) {
 437                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 438                         gain[0] = 6;
 439                         gain[1] = 6;
 440                 } else {
 441                         tmp = 40370 - 315 * dev->phy.channel;
 442                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 443                         tmp = 23242 - 224 * dev->phy.channel;
 444                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 445                 }
 446         } else {
 447                 gain[0] = 0;
 448                 gain[1] = 0;
 449         }
 450
 451         for (i = 0; i < 2; i++) {
 452                 if (nphy->elna_gain_config) {
 453                         data[0] = 19 + gain[i];
 454                         data[1] = 25 + gain[i];
 455                         data[2] = 25 + gain[i];
 456                         data[3] = 25 + gain[i];
 457                 } else {
 458                         data[0] = lna_gain[0] + gain[i];
 459                         data[1] = lna_gain[1] + gain[i];
 460                         data[2] = lna_gain[2] + gain[i];
 461                         data[3] = lna_gain[3] + gain[i];
 462                 }
 463                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
 464
 465                 minmax[i] = 23 + gain[i];
 466         }
 467
 468         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 469                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 470         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 471                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 472
 473         if (nphy->hang_avoid)
 474                 b43_nphy_stay_in_carrier_search(dev, 0);
 475 }
 476
 477 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
 478 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
 479                                         u8 *events, u8 *delays, u8 length)
 480 {
 481         struct b43_phy_n *nphy = dev->phy.n;
 482         u8 i;
 483         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
 484         u16 offset1 = cmd << 4;
 485         u16 offset2 = offset1 + 0x80;
 486
 487         if (nphy->hang_avoid)
 488                 b43_nphy_stay_in_carrier_search(dev, true);
 489
 490         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
 491         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
 492
 493         for (i = length; i < 16; i++) {
 494                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
 495                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
 496         }
 497
 498         if (nphy->hang_avoid)
 499                 b43_nphy_stay_in_carrier_search(dev, false);
 500 }
 501
 502 /**************************************************
 503  * Radio 0x2057
 504  **************************************************/
 505
 506 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
 507 static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
 508 {
 509         struct b43_phy *phy = &dev->phy;
 510         u16 tmp;
 511
 512         if (phy->radio_rev == 5) {
 513                 b43_phy_mask(dev, 0x342, ~0x2);
 514                 udelay(10);
 515                 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
 516                 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
 517         }
 518
 519         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
 520         udelay(10);
 521         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
 522         if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
 523                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
 524                 return 0;
 525         }
 526         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
 527         tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
 528         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
 529
 530         if (phy->radio_rev == 5) {
 531                 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
 532                 b43_radio_mask(dev, 0x1ca, ~0x2);
 533         }
 534         if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
 535                 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
 536                 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
 537                                   tmp << 2);
 538         }
 539
 540         return tmp & 0x3e;
 541 }
 542
 543 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
 544 static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
 545 {
 546         struct b43_phy *phy = &dev->phy;
 547         bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
 548                         phy->radio_rev == 6);
 549         u16 tmp;
 550
 551         if (special) {
 552                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
 553                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
 554         } else {
 555                 b43_radio_write(dev, 0x1AE, 0x61);
 556                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
 557         }
 558         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 559         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 560         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 561                                   5000000))
 562                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 563         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 564         if (special) {
 565                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
 566                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 567         } else {
 568                 b43_radio_write(dev, 0x1AE, 0x69);
 569                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
 570         }
 571         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 572         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 573         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 574                                   5000000))
 575                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 576         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 577         if (special) {
 578                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
 579                 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
 580                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 581         } else {
 582                 b43_radio_write(dev, 0x1AE, 0x73);
 583                 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 584                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
 585         }
 586         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 587         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 588                                   5000000)) {
 589                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
 590                 return 0;
 591         }
 592         tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
 593         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 594         return tmp;
 595 }
 596
 597 static void b43_radio_2057_init_pre(struct b43_wldev *dev)
 598 {
 599         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 600         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 601         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
 602         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 603         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
 604 }
 605
 606 static void b43_radio_2057_init_post(struct b43_wldev *dev)
 607 {
 608         b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
 609
 610         b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
 611         b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
 612         mdelay(2);
 613         b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
 614         b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
 615
 616         if (dev->phy.n->init_por) {
 617                 b43_radio_2057_rcal(dev);
 618                 b43_radio_2057_rccal(dev);
 619         }
 620         b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
 621
 622         dev->phy.n->init_por = false;
 623 }
 624
 625 /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
 626 static void b43_radio_2057_init(struct b43_wldev *dev)
 627 {
 628         b43_radio_2057_init_pre(dev);
 629         r2057_upload_inittabs(dev);
 630         b43_radio_2057_init_post(dev);
 631 }
 632
 633 /**************************************************
 634  * Radio 0x2056
 635  **************************************************/
 636
 637 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 638                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 639 {
 640         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 641         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 642         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 643         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 644         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 645         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 646                                         e->radio_syn_pll_loopfilter1);
 647         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 648                                         e->radio_syn_pll_loopfilter2);
 649         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 650                                         e->radio_syn_pll_loopfilter3);
 651         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 652                                         e->radio_syn_pll_loopfilter4);
 653         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 654                                         e->radio_syn_pll_loopfilter5);
 655         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 656                                         e->radio_syn_reserved_addr27);
 657         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 658                                         e->radio_syn_reserved_addr28);
 659         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 660                                         e->radio_syn_reserved_addr29);
 661         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 662                                         e->radio_syn_logen_vcobuf1);
 663         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 664         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 665         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 666
 667         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 668                                         e->radio_rx0_lnaa_tune);
 669         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 670                                         e->radio_rx0_lnag_tune);
 671
 672         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 673                                         e->radio_tx0_intpaa_boost_tune);
 674         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 675                                         e->radio_tx0_intpag_boost_tune);
 676         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 677                                         e->radio_tx0_pada_boost_tune);
 678         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 679                                         e->radio_tx0_padg_boost_tune);
 680         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 681                                         e->radio_tx0_pgaa_boost_tune);
 682         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 683                                         e->radio_tx0_pgag_boost_tune);
 684         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 685                                         e->radio_tx0_mixa_boost_tune);
 686         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 687                                         e->radio_tx0_mixg_boost_tune);
 688
 689         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 690                                         e->radio_rx1_lnaa_tune);
 691         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 692                                         e->radio_rx1_lnag_tune);
 693
 694         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 695                                         e->radio_tx1_intpaa_boost_tune);
 696         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 697                                         e->radio_tx1_intpag_boost_tune);
 698         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 699                                         e->radio_tx1_pada_boost_tune);
 700         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 701                                         e->radio_tx1_padg_boost_tune);
 702         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 703                                         e->radio_tx1_pgaa_boost_tune);
 704         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 705                                         e->radio_tx1_pgag_boost_tune);
 706         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 707                                         e->radio_tx1_mixa_boost_tune);
 708         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 709                                         e->radio_tx1_mixg_boost_tune);
 710 }
 711
 712 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 713 static void b43_radio_2056_setup(struct b43_wldev *dev,
 714                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 715 {
 716         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 717         enum ieee80211_band band = b43_current_band(dev->wl);
 718         u16 offset;
 719         u8 i;
 720         u16 bias, cbias;
 721         u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
 722         u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
 723
 724         B43_WARN_ON(dev->phy.rev < 3);
 725
 726         b43_chantab_radio_2056_upload(dev, e);
 727         b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
 728
 729         if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
 730             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 731                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 732                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 733                 if (dev->dev->chip_id == 0x4716) {
 734                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
 735                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
 736                 } else {
 737                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
 738                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
 739                 }
 740         }
 741         if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
 742             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 743                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 744                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 745                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
 746                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
 747         }
 748
 749         if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
 750                 for (i = 0; i < 2; i++) {
 751                         offset = i ? B2056_TX1 : B2056_TX0;
 752                         if (dev->phy.rev >= 5) {
 753                                 b43_radio_write(dev,
 754                                         offset | B2056_TX_PADG_IDAC, 0xcc);
 755
 756                                 if (dev->dev->chip_id == 0x4716) {
 757                                         bias = 0x40;
 758                                         cbias = 0x45;
 759                                         pag_boost = 0x5;
 760                                         pgag_boost = 0x33;
 761                                         mixg_boost = 0x55;
 762                                 } else {
 763                                         bias = 0x25;
 764                                         cbias = 0x20;
 765                                         pag_boost = 0x4;
 766                                         pgag_boost = 0x03;
 767                                         mixg_boost = 0x65;
 768                                 }
 769                                 padg_boost = 0x77;
 770
 771                                 b43_radio_write(dev,
 772                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 773                                         bias);
 774                                 b43_radio_write(dev,
 775                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 776                                         bias);
 777                                 b43_radio_write(dev,
 778                                         offset | B2056_TX_INTPAG_CASCBIAS,
 779                                         cbias);
 780                                 b43_radio_write(dev,
 781                                         offset | B2056_TX_INTPAG_BOOST_TUNE,
 782                                         pag_boost);
 783                                 b43_radio_write(dev,
 784                                         offset | B2056_TX_PGAG_BOOST_TUNE,
 785                                         pgag_boost);
 786                                 b43_radio_write(dev,
 787                                         offset | B2056_TX_PADG_BOOST_TUNE,
 788                                         padg_boost);
 789                                 b43_radio_write(dev,
 790                                         offset | B2056_TX_MIXG_BOOST_TUNE,
 791                                         mixg_boost);
 792                         } else {
 793                                 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
 794                                 b43_radio_write(dev,
 795                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 796                                         bias);
 797                                 b43_radio_write(dev,
 798                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 799                                         bias);
 800                                 b43_radio_write(dev,
 801                                         offset | B2056_TX_INTPAG_CASCBIAS,
 802                                         0x30);
 803                         }
 804                         b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
 805                 }
 806         } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
 807                 u16 freq = dev->phy.channel_freq;
 808                 if (freq < 5100) {
 809                         paa_boost = 0xA;
 810                         pada_boost = 0x77;
 811                         pgaa_boost = 0xF;
 812                         mixa_boost = 0xF;
 813                 } else if (freq < 5340) {
 814                         paa_boost = 0x8;
 815                         pada_boost = 0x77;
 816                         pgaa_boost = 0xFB;
 817                         mixa_boost = 0xF;
 818                 } else if (freq < 5650) {
 819                         paa_boost = 0x0;
 820                         pada_boost = 0x77;
 821                         pgaa_boost = 0xB;
 822                         mixa_boost = 0xF;
 823                 } else {
 824                         paa_boost = 0x0;
 825                         pada_boost = 0x77;
 826                         if (freq != 5825)
 827                                 pgaa_boost = -(freq - 18) / 36 + 168;
 828                         else
 829                                 pgaa_boost = 6;
 830                         mixa_boost = 0xF;
 831                 }
 832
 833                 for (i = 0; i < 2; i++) {
 834                         offset = i ? B2056_TX1 : B2056_TX0;
 835
 836                         b43_radio_write(dev,
 837                                 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
 838                         b43_radio_write(dev,
 839                                 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
 840                         b43_radio_write(dev,
 841                                 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
 842                         b43_radio_write(dev,
 843                                 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
 844                         b43_radio_write(dev,
 845                                 offset | B2056_TX_TXSPARE1, 0x30);
 846                         b43_radio_write(dev,
 847                                 offset | B2056_TX_PA_SPARE2, 0xee);
 848                         b43_radio_write(dev,
 849                                 offset | B2056_TX_PADA_CASCBIAS, 0x03);
 850                         b43_radio_write(dev,
 851                                 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
 852                         b43_radio_write(dev,
 853                                 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
 854                         b43_radio_write(dev,
 855                                 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
 856                 }
 857         }
 858
 859         udelay(50);
 860         /* VCO calibration */
 861         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 862         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 863         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 864         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 865         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 866         udelay(300);
 867 }
 868
 869 static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
 870 {
 871         struct b43_phy *phy = &dev->phy;
 872         u16 mast2, tmp;
 873
 874         if (phy->rev != 3)
 875                 return 0;
 876
 877         mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
 878         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
 879
 880         udelay(10);
 881         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
 882         udelay(10);
 883         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
 884
 885         if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
 886                                   1000000)) {
 887                 b43err(dev->wl, "Radio recalibration timeout\n");
 888                 return 0;
 889         }
 890
 891         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
 892         tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
 893         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
 894
 895         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
 896
 897         return tmp & 0x1f;
 898 }
 899
 900 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 901 {
 902         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 903                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 904         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 905         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 906                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 907         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 908                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 909         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 910                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 911 }
 912
 913 static void b43_radio_init2056_post(struct b43_wldev *dev)
 914 {
 915         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 916         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 917         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 918         msleep(1);
 919         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 920         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 921         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 922         if (dev->phy.n->init_por)
 923                 b43_radio_2056_rcal(dev);
 924 }
 925
 926 /*
 927  * Initialize a Broadcom 2056 N-radio
 928  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 929  */
 930 static void b43_radio_init2056(struct b43_wldev *dev)
 931 {
 932         b43_radio_init2056_pre(dev);
 933         b2056_upload_inittabs(dev, 0, 0);
 934         b43_radio_init2056_post(dev);
 935
 936         dev->phy.n->init_por = false;
 937 }
 938
 939 /**************************************************
 940  * Radio 0x2055
 941  **************************************************/
 942
 943 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 944                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 945 {
 946         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 947         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 948         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 949         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 950         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 951
 952         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 953         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 954         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 955         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 956         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 957
 958         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 959         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 960         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 961         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 962         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 963
 964         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 965         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 966         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 967         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 968         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 969
 970         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 971         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 972         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 973         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 974         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 975
 976         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 977         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 978 }
 979
 980 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 981 static void b43_radio_2055_setup(struct b43_wldev *dev,
 982                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 983 {
 984         B43_WARN_ON(dev->phy.rev >= 3);
 985
 986         b43_chantab_radio_upload(dev, e);
 987         udelay(50);
 988         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 989         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 990         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 991         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 992         udelay(300);
 993 }
 994
 995 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 996 {
 997         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 998                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 999         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1000                     B43_NPHY_RFCTL_CMD_CHIP0PU |
1001                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
1002         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1003                     B43_NPHY_RFCTL_CMD_PORFORCE);
1004 }
1005
1006 static void b43_radio_init2055_post(struct b43_wldev *dev)
1007 {
1008         struct b43_phy_n *nphy = dev->phy.n;
1009         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1010         bool workaround = false;
1011
1012         if (sprom->revision < 4)
1013                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1014                               && dev->dev->board_type == 0x46D
1015                               && dev->dev->board_rev >= 0x41);
1016         else
1017                 workaround =
1018                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1019
1020         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1021         if (workaround) {
1022                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1023                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1024         }
1025         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1026         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1027         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1028         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1029         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1030         msleep(1);
1031         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1032         if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1033                 b43err(dev->wl, "radio post init timeout\n");
1034         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1035         b43_switch_channel(dev, dev->phy.channel);
1036         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1037         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1038         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1039         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1040         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1041         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1042         if (!nphy->gain_boost) {
1043                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1044                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1045         } else {
1046                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1047                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1048         }
1049         udelay(2);
1050 }
1051
1052 /*
1053  * Initialize a Broadcom 2055 N-radio
1054  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1055  */
1056 static void b43_radio_init2055(struct b43_wldev *dev)
1057 {
1058         b43_radio_init2055_pre(dev);
1059         if (b43_status(dev) < B43_STAT_INITIALIZED) {
1060                 /* Follow wl, not specs. Do not force uploading all regs */
1061                 b2055_upload_inittab(dev, 0, 0);
1062         } else {
1063                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1064                 b2055_upload_inittab(dev, ghz5, 0);
1065         }
1066         b43_radio_init2055_post(dev);
1067 }
1068
1069 /**************************************************
1070  * Samples
1071  **************************************************/
1072
1073 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1074 static int b43_nphy_load_samples(struct b43_wldev *dev,
1075                                         struct b43_c32 *samples, u16 len) {
1076         struct b43_phy_n *nphy = dev->phy.n;
1077         u16 i;
1078         u32 *data;
1079
1080         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1081         if (!data) {
1082                 b43err(dev->wl, "allocation for samples loading failed\n");
1083                 return -ENOMEM;
1084         }
1085         if (nphy->hang_avoid)
1086                 b43_nphy_stay_in_carrier_search(dev, 1);
1087
1088         for (i = 0; i < len; i++) {
1089                 data[i] = (samples[i].i & 0x3FF << 10);
1090                 data[i] |= samples[i].q & 0x3FF;
1091         }
1092         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1093
1094         kfree(data);
1095         if (nphy->hang_avoid)
1096                 b43_nphy_stay_in_carrier_search(dev, 0);
1097         return 0;
1098 }
1099
1100 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1101 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1102                                         bool test)
1103 {
1104         int i;
1105         u16 bw, len, rot, angle;
1106         struct b43_c32 *samples;
1107
1108
1109         bw = (dev->phy.is_40mhz) ? 40 : 20;
1110         len = bw << 3;
1111
1112         if (test) {
1113                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1114                         bw = 82;
1115                 else
1116                         bw = 80;
1117
1118                 if (dev->phy.is_40mhz)
1119                         bw <<= 1;
1120
1121                 len = bw << 1;
1122         }
1123
1124         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1125         if (!samples) {
1126                 b43err(dev->wl, "allocation for samples generation failed\n");
1127                 return 0;
1128         }
1129         rot = (((freq * 36) / bw) << 16) / 100;
1130         angle = 0;
1131
1132         for (i = 0; i < len; i++) {
1133                 samples[i] = b43_cordic(angle);
1134                 angle += rot;
1135                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1136                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1137         }
1138
1139         i = b43_nphy_load_samples(dev, samples, len);
1140         kfree(samples);
1141         return (i < 0) ? 0 : len;
1142 }
1143
1144 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1145 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1146                                         u16 wait, bool iqmode, bool dac_test)
1147 {
1148         struct b43_phy_n *nphy = dev->phy.n;
1149         int i;
1150         u16 seq_mode;
1151         u32 tmp;
1152
1153         if (nphy->hang_avoid)
1154                 b43_nphy_stay_in_carrier_search(dev, true);
1155
1156         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1157                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1158                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1159         }
1160
1161         if (!dev->phy.is_40mhz)
1162                 tmp = 0x6464;
1163         else
1164                 tmp = 0x4747;
1165         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1166
1167         if (nphy->hang_avoid)
1168                 b43_nphy_stay_in_carrier_search(dev, false);
1169
1170         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1171
1172         if (loops != 0xFFFF)
1173                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1174         else
1175                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1176
1177         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1178
1179         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1180
1181         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1182         if (iqmode) {
1183                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1184                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1185         } else {
1186                 if (dac_test)
1187                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1188                 else
1189                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1190         }
1191         for (i = 0; i < 100; i++) {
1192                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1193                         i = 0;
1194                         break;
1195                 }
1196                 udelay(10);
1197         }
1198         if (i)
1199                 b43err(dev->wl, "run samples timeout\n");
1200
1201         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1202 }
1203
1204 /**************************************************
1205  * RSSI
1206  **************************************************/
1207
1208 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1209 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1210                                         s8 offset, u8 core, u8 rail,
1211                                         enum b43_nphy_rssi_type type)
1212 {
1213         u16 tmp;
1214         bool core1or5 = (core == 1) || (core == 5);
1215         bool core2or5 = (core == 2) || (core == 5);
1216
1217         offset = clamp_val(offset, -32, 31);
1218         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1219
1220         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1221                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1222         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1223                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1224         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1225                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1226         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1227                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1228
1229         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1230                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1231         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1232                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1233         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1234                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1235         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1236                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1237
1238         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1239                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1240         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1241                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1242         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1243                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1244         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1245                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1246
1247         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1248                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1249         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1250                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1251         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1252                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1253         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1254                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1255
1256         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1257                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1258         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1259                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1260         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1261                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1262         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1263                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1264
1265         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
1266                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1267         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
1268                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1269
1270         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1271                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1272         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1273                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1274 }
1275
1276 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1277 {
1278         u8 i;
1279         u16 reg, val;
1280
1281         if (code == 0) {
1282                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1283                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1284                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1285                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1286                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1287                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1288                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1289                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1290         } else {
1291                 for (i = 0; i < 2; i++) {
1292                         if ((code == 1 && i == 1) || (code == 2 && !i))
1293                                 continue;
1294
1295                         reg = (i == 0) ?
1296                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1297                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1298
1299                         if (type < 3) {
1300                                 reg = (i == 0) ?
1301                                         B43_NPHY_AFECTL_C1 :
1302                                         B43_NPHY_AFECTL_C2;
1303                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1304
1305                                 reg = (i == 0) ?
1306                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1307                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1308                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1309
1310                                 if (type == 0)
1311                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1312                                 else if (type == 1)
1313                                         val = 16;
1314                                 else
1315                                         val = 32;
1316                                 b43_phy_set(dev, reg, val);
1317
1318                                 reg = (i == 0) ?
1319                                         B43_NPHY_TXF_40CO_B1S0 :
1320                                         B43_NPHY_TXF_40CO_B32S1;
1321                                 b43_phy_set(dev, reg, 0x0020);
1322                         } else {
1323                                 if (type == 6)
1324                                         val = 0x0100;
1325                                 else if (type == 3)
1326                                         val = 0x0200;
1327                                 else
1328                                         val = 0x0300;
1329
1330                                 reg = (i == 0) ?
1331                                         B43_NPHY_AFECTL_C1 :
1332                                         B43_NPHY_AFECTL_C2;
1333
1334                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1335                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1336
1337                                 if (type != 3 && type != 6) {
1338                                         enum ieee80211_band band =
1339                                                 b43_current_band(dev->wl);
1340
1341                                         if (b43_nphy_ipa(dev))
1342                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1343                                         else
1344                                                 val = 0x11;
1345                                         reg = (i == 0) ? 0x2000 : 0x3000;
1346                                         reg |= B2055_PADDRV;
1347                                         b43_radio_write16(dev, reg, val);
1348
1349                                         reg = (i == 0) ?
1350                                                 B43_NPHY_AFECTL_OVER1 :
1351                                                 B43_NPHY_AFECTL_OVER;
1352                                         b43_phy_set(dev, reg, 0x0200);
1353                                 }
1354                         }
1355                 }
1356         }
1357 }
1358
1359 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1360 {
1361         u16 val;
1362
1363         if (type < 3)
1364                 val = 0;
1365         else if (type == 6)
1366                 val = 1;
1367         else if (type == 3)
1368                 val = 2;
1369         else
1370                 val = 3;
1371
1372         val = (val << 12) | (val << 14);
1373         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1374         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1375
1376         if (type < 3) {
1377                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1378                                 (type + 1) << 4);
1379                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1380                                 (type + 1) << 4);
1381         }
1382
1383         if (code == 0) {
1384                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1385                 if (type < 3) {
1386                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1387                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1388                                   B43_NPHY_RFCTL_CMD_CORESEL));
1389                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1390                                 ~(0x1 << 12 |
1391                                   0x1 << 5 |
1392                                   0x1 << 1 |
1393                                   0x1));
1394                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1395                                 ~B43_NPHY_RFCTL_CMD_START);
1396                         udelay(20);
1397                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1398                 }
1399         } else {
1400                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1401                 if (type < 3) {
1402                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1403                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1404                                   B43_NPHY_RFCTL_CMD_CORESEL),
1405                                 (B43_NPHY_RFCTL_CMD_RXEN |
1406                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1407                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1408                                 (0x1 << 12 |
1409                                   0x1 << 5 |
1410                                   0x1 << 1 |
1411                                   0x1));
1412                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1413                                 B43_NPHY_RFCTL_CMD_START);
1414                         udelay(20);
1415                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1416                 }
1417         }
1418 }
1419
1420 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1421 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1422 {
1423         if (dev->phy.rev >= 3)
1424                 b43_nphy_rev3_rssi_select(dev, code, type);
1425         else
1426                 b43_nphy_rev2_rssi_select(dev, code, type);
1427 }
1428
1429 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1430 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1431 {
1432         int i;
1433         for (i = 0; i < 2; i++) {
1434                 if (type == 2) {
1435                         if (i == 0) {
1436                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1437                                                   0xFC, buf[0]);
1438                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1439                                                   0xFC, buf[1]);
1440                         } else {
1441                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1442                                                   0xFC, buf[2 * i]);
1443                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1444                                                   0xFC, buf[2 * i + 1]);
1445                         }
1446                 } else {
1447                         if (i == 0)
1448                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1449                                                   0xF3, buf[0] << 2);
1450                         else
1451                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1452                                                   0xF3, buf[2 * i + 1] << 2);
1453                 }
1454         }
1455 }
1456
1457 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1458 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1459                                 u8 nsamp)
1460 {
1461         int i;
1462         int out;
1463         u16 save_regs_phy[9];
1464         u16 s[2];
1465
1466         if (dev->phy.rev >= 3) {
1467                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1468                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1469                 save_regs_phy[2] = b43_phy_read(dev,
1470                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1471                 save_regs_phy[3] = b43_phy_read(dev,
1472                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1473                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1474                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1475                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1476                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1477                 save_regs_phy[8] = 0;
1478         } else {
1479                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1480                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1481                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1482                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1483                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1484                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1485                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1486                 save_regs_phy[7] = 0;
1487                 save_regs_phy[8] = 0;
1488         }
1489
1490         b43_nphy_rssi_select(dev, 5, type);
1491
1492         if (dev->phy.rev < 2) {
1493                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1494                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1495         }
1496
1497         for (i = 0; i < 4; i++)
1498                 buf[i] = 0;
1499
1500         for (i = 0; i < nsamp; i++) {
1501                 if (dev->phy.rev < 2) {
1502                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1503                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1504                 } else {
1505                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1506                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1507                 }
1508
1509                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1510                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1511                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1512                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1513         }
1514         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1515                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1516
1517         if (dev->phy.rev < 2)
1518                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1519
1520         if (dev->phy.rev >= 3) {
1521                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1522                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1523                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1524                                 save_regs_phy[2]);
1525                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1526                                 save_regs_phy[3]);
1527                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1528                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1529                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1530                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1531         } else {
1532                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1533                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1534                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1535                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1536                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1537                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1538                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1539         }
1540
1541         return out;
1542 }
1543
1544 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1545 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1546 {
1547         struct b43_phy_n *nphy = dev->phy.n;
1548
1549         u16 saved_regs_phy_rfctl[2];
1550         u16 saved_regs_phy[13];
1551         u16 regs_to_store[] = {
1552                 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1553                 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1554                 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1555                 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1556                 B43_NPHY_RFCTL_CMD,
1557                 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1558                 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1559         };
1560
1561         u16 class;
1562
1563         u16 clip_state[2];
1564         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1565
1566         u8 vcm_final = 0;
1567         s32 offset[4];
1568         s32 results[8][4] = { };
1569         s32 results_min[4] = { };
1570         s32 poll_results[4] = { };
1571
1572         u16 *rssical_radio_regs = NULL;
1573         u16 *rssical_phy_regs = NULL;
1574
1575         u16 r; /* routing */
1576         u8 rx_core_state;
1577         u8 core, i, j;
1578
1579         class = b43_nphy_classifier(dev, 0, 0);
1580         b43_nphy_classifier(dev, 7, 4);
1581         b43_nphy_read_clip_detection(dev, clip_state);
1582         b43_nphy_write_clip_detection(dev, clip_off);
1583
1584         saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1585         saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1586         for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1587                 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1588
1589         b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
1590         b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
1591         b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
1592         b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
1593         b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
1594         b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
1595
1596         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1597                 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
1598                 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
1599         } else {
1600                 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
1601                 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
1602         }
1603
1604         rx_core_state = b43_nphy_get_rx_core_state(dev);
1605         for (core = 0; core < 2; core++) {
1606                 if (!(rx_core_state & (1 << core)))
1607                         continue;
1608                 r = core ? B2056_RX1 : B2056_RX0;
1609                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, 2);
1610                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, 2);
1611                 for (i = 0; i < 8; i++) {
1612                         b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1613                                         i << 2);
1614                         b43_nphy_poll_rssi(dev, 2, results[i], 8);
1615                 }
1616                 for (i = 0; i < 4; i += 2) {
1617                         s32 curr;
1618                         s32 mind = 0x100000;
1619                         s32 minpoll = 249;
1620                         u8 minvcm = 0;
1621                         if (2 * core != i)
1622                                 continue;
1623                         for (j = 0; j < 8; j++) {
1624                                 curr = results[j][i] * results[j][i] +
1625                                         results[j][i + 1] * results[j][i];
1626                                 if (curr < mind) {
1627                                         mind = curr;
1628                                         minvcm = j;
1629                                 }
1630                                 if (results[j][i] < minpoll)
1631                                         minpoll = results[j][i];
1632                         }
1633                         vcm_final = minvcm;
1634                         results_min[i] = minpoll;
1635                 }
1636                 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1637                                   vcm_final << 2);
1638                 for (i = 0; i < 4; i++) {
1639                         if (core != i / 2)
1640                                 continue;
1641                         offset[i] = -results[vcm_final][i];
1642                         if (offset[i] < 0)
1643                                 offset[i] = -((abs(offset[i]) + 4) / 8);
1644                         else
1645                                 offset[i] = (offset[i] + 4) / 8;
1646                         if (results_min[i] == 248)
1647                                 offset[i] = -32;
1648                         b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1649                                                    (i / 2 == 0) ? 1 : 2,
1650                                                    (i % 2 == 0) ? 0 : 1,
1651                                                    2);
1652                 }
1653         }
1654         for (core = 0; core < 2; core++) {
1655                 if (!(rx_core_state & (1 << core)))
1656                         continue;
1657                 for (i = 0; i < 2; i++) {
1658                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, i);
1659                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, i);
1660                         b43_nphy_poll_rssi(dev, i, poll_results, 8);
1661                         for (j = 0; j < 4; j++) {
1662                                 if (j / 2 == core) {
1663                                         offset[j] = 232 - poll_results[j];
1664                                         if (offset[j] < 0)
1665                                                 offset[j] = -(abs(offset[j] + 4) / 8);
1666                                         else
1667                                                 offset[j] = (offset[j] + 4) / 8;
1668                                         b43_nphy_scale_offset_rssi(dev, 0,
1669                                                 offset[2 * core], core + 1, j % 2, i);
1670                                 }
1671                         }
1672                 }
1673         }
1674
1675         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1676         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1677
1678         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1679
1680         b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1681         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1682         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1683
1684         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1685         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1686         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1687
1688         for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1689                 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1690
1691         /* Store for future configuration */
1692         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1693                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1694                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1695         } else {
1696                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1697                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1698         }
1699         rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
1700         rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
1701         rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1702         rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1703         rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1704         rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1705         rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1706         rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1707         rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1708         rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1709         rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1710         rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1711         rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1712         rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1713
1714         /* Remember for which channel we store configuration */
1715         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1716                 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1717         else
1718                 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1719
1720         /* End of calibration, restore configuration */
1721         b43_nphy_classifier(dev, 7, class);
1722         b43_nphy_write_clip_detection(dev, clip_state);
1723 }
1724
1725 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1726 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1727 {
1728         int i, j;
1729         u8 state[4];
1730         u8 code, val;
1731         u16 class, override;
1732         u8 regs_save_radio[2];
1733         u16 regs_save_phy[2];
1734
1735         s32 offset[4];
1736         u8 core;
1737         u8 rail;
1738
1739         u16 clip_state[2];
1740         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1741         s32 results_min[4] = { };
1742         u8 vcm_final[4] = { };
1743         s32 results[4][4] = { };
1744         s32 miniq[4][2] = { };
1745
1746         if (type == 2) {
1747                 code = 0;
1748                 val = 6;
1749         } else if (type < 2) {
1750                 code = 25;
1751                 val = 4;
1752         } else {
1753                 B43_WARN_ON(1);
1754                 return;
1755         }
1756
1757         class = b43_nphy_classifier(dev, 0, 0);
1758         b43_nphy_classifier(dev, 7, 4);
1759         b43_nphy_read_clip_detection(dev, clip_state);
1760         b43_nphy_write_clip_detection(dev, clip_off);
1761
1762         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1763                 override = 0x140;
1764         else
1765                 override = 0x110;
1766
1767         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1768         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1769         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1770         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1771
1772         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1773         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1774         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1775         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1776
1777         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1778         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1779         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1780         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1781         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1782         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1783
1784         b43_nphy_rssi_select(dev, 5, type);
1785         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1786         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1787
1788         for (i = 0; i < 4; i++) {
1789                 u8 tmp[4];
1790                 for (j = 0; j < 4; j++)
1791                         tmp[j] = i;
1792                 if (type != 1)
1793                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1794                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1795                 if (type < 2)
1796                         for (j = 0; j < 2; j++)
1797                                 miniq[i][j] = min(results[i][2 * j],
1798                                                 results[i][2 * j + 1]);
1799         }
1800
1801         for (i = 0; i < 4; i++) {
1802                 s32 mind = 0x100000;
1803                 u8 minvcm = 0;
1804                 s32 minpoll = 249;
1805                 s32 curr;
1806                 for (j = 0; j < 4; j++) {
1807                         if (type == 2)
1808                                 curr = abs(results[j][i]);
1809                         else
1810                                 curr = abs(miniq[j][i / 2] - code * 8);
1811
1812                         if (curr < mind) {
1813                                 mind = curr;
1814                                 minvcm = j;
1815                         }
1816
1817                         if (results[j][i] < minpoll)
1818                                 minpoll = results[j][i];
1819                 }
1820                 results_min[i] = minpoll;
1821                 vcm_final[i] = minvcm;
1822         }
1823
1824         if (type != 1)
1825                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1826
1827         for (i = 0; i < 4; i++) {
1828                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1829
1830                 if (offset[i] < 0)
1831                         offset[i] = -((abs(offset[i]) + 4) / 8);
1832                 else
1833                         offset[i] = (offset[i] + 4) / 8;
1834
1835                 if (results_min[i] == 248)
1836                         offset[i] = code - 32;
1837
1838                 core = (i / 2) ? 2 : 1;
1839                 rail = (i % 2) ? 1 : 0;
1840
1841                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1842                                                 type);
1843         }
1844
1845         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1846         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1847
1848         switch (state[2]) {
1849         case 1:
1850                 b43_nphy_rssi_select(dev, 1, 2);
1851                 break;
1852         case 4:
1853                 b43_nphy_rssi_select(dev, 1, 0);
1854                 break;
1855         case 2:
1856                 b43_nphy_rssi_select(dev, 1, 1);
1857                 break;
1858         default:
1859                 b43_nphy_rssi_select(dev, 1, 1);
1860                 break;
1861         }
1862
1863         switch (state[3]) {
1864         case 1:
1865                 b43_nphy_rssi_select(dev, 2, 2);
1866                 break;
1867         case 4:
1868                 b43_nphy_rssi_select(dev, 2, 0);
1869                 break;
1870         default:
1871                 b43_nphy_rssi_select(dev, 2, 1);
1872                 break;
1873         }
1874
1875         b43_nphy_rssi_select(dev, 0, type);
1876
1877         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1878         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1879         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1880         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1881
1882         b43_nphy_classifier(dev, 7, class);
1883         b43_nphy_write_clip_detection(dev, clip_state);
1884         /* Specs don't say about reset here, but it makes wl and b43 dumps
1885            identical, it really seems wl performs this */
1886         b43_nphy_reset_cca(dev);
1887 }
1888
1889 /*
1890  * RSSI Calibration
1891  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1892  */
1893 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1894 {
1895         if (dev->phy.rev >= 3) {
1896                 b43_nphy_rev3_rssi_cal(dev);
1897         } else {
1898                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
1899                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
1900                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
1901         }
1902 }
1903
1904 /**************************************************
1905  * Workarounds
1906  **************************************************/
1907
1908 static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1909 {
1910         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1911
1912         bool ghz5;
1913         bool ext_lna;
1914         u16 rssi_gain;
1915         struct nphy_gain_ctl_workaround_entry *e;
1916         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1917         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1918
1919         /* Prepare values */
1920         ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1921                 & B43_NPHY_BANDCTL_5GHZ;
1922         ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1923                 sprom->boardflags_lo & B43_BFL_EXTLNA;
1924         e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1925         if (ghz5 && dev->phy.rev >= 5)
1926                 rssi_gain = 0x90;
1927         else
1928                 rssi_gain = 0x50;
1929
1930         b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1931
1932         /* Set Clip 2 detect */
1933         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1934                         B43_NPHY_C1_CGAINI_CL2DETECT);
1935         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1936                         B43_NPHY_C2_CGAINI_CL2DETECT);
1937
1938         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1939                         0x17);
1940         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1941                         0x17);
1942         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1943         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1944         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1945         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1946         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1947                         rssi_gain);
1948         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1949                         rssi_gain);
1950         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1951                         0x17);
1952         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1953                         0x17);
1954         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1955         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1956
1957         b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1958         b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1959         b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1960         b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1961         b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1962         b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1963         b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1964         b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1965         b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1966         b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1967         b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1968         b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1969
1970         b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1971         b43_phy_write(dev, 0x2A7, e->init_gain);
1972         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1973                                 e->rfseq_init);
1974
1975         /* TODO: check defines. Do not match variables names */
1976         b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1977         b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1978         b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1979         b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1980         b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1981         b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1982
1983         b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1984         b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1985         b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1986         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1987         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1988         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1989                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1990         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1991                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1992         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1993 }
1994
1995 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
1996 {
1997         struct b43_phy_n *nphy = dev->phy.n;
1998
1999         u8 i, j;
2000         u8 code;
2001         u16 tmp;
2002         u8 rfseq_events[3] = { 6, 8, 7 };
2003         u8 rfseq_delays[3] = { 10, 30, 1 };
2004
2005         /* Set Clip 2 detect */
2006         b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2007         b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2008
2009         /* Set narrowband clip threshold */
2010         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2011         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2012
2013         if (!dev->phy.is_40mhz) {
2014                 /* Set dwell lengths */
2015                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2016                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2017                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2018                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2019         }
2020
2021         /* Set wideband clip 2 threshold */
2022         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2023                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2024         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2025                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2026
2027         if (!dev->phy.is_40mhz) {
2028                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2029                         ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2030                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2031                         ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2032                 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2033                         ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2034                 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2035                         ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2036         }
2037
2038         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2039
2040         if (nphy->gain_boost) {
2041                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2042                         dev->phy.is_40mhz)
2043                         code = 4;
2044                 else
2045                         code = 5;
2046         } else {
2047                 code = dev->phy.is_40mhz ? 6 : 7;
2048         }
2049
2050         /* Set HPVGA2 index */
2051         b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2052                         code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2053         b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2054                         code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2055
2056         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2057         /* specs say about 2 loops, but wl does 4 */
2058         for (i = 0; i < 4; i++)
2059                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2060
2061         b43_nphy_adjust_lna_gain_table(dev);
2062
2063         if (nphy->elna_gain_config) {
2064                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2065                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2066                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2067                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2068                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2069
2070                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2071                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2072                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2073                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2074                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2075
2076                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2077                 /* specs say about 2 loops, but wl does 4 */
2078                 for (i = 0; i < 4; i++)
2079                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2080                                                 (code << 8 | 0x74));
2081         }
2082
2083         if (dev->phy.rev == 2) {
2084                 for (i = 0; i < 4; i++) {
2085                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2086                                         (0x0400 * i) + 0x0020);
2087                         for (j = 0; j < 21; j++) {
2088                                 tmp = j * (i < 2 ? 3 : 1);
2089                                 b43_phy_write(dev,
2090                                         B43_NPHY_TABLE_DATALO, tmp);
2091                         }
2092                 }
2093         }
2094
2095         b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2096         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2097                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2098                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2099
2100         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2101                 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2102 }
2103
2104 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2105 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2106 {
2107         if (dev->phy.rev >= 7)
2108                 ; /* TODO */
2109         else if (dev->phy.rev >= 3)
2110                 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2111         else
2112                 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2113 }
2114
2115 /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2116 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2117 {
2118         if (!offset)
2119                 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2120         return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2121 }
2122
2123 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2124 {
2125         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2126         struct b43_phy *phy = &dev->phy;
2127
2128         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2129                                         0x1F };
2130         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2131
2132         u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2133         u8 ntab7_138_146[] = { 0x11, 0x11 };
2134         u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2135
2136         u16 lpf_20, lpf_40, lpf_11b;
2137         u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2138         u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2139         bool rccal_ovrd = false;
2140
2141         u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2142         u16 bias, conv, filt;
2143
2144         u32 tmp32;
2145         u8 core;
2146
2147         if (phy->rev == 7) {
2148                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2149                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2150                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2151                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2152                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2153                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2154                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2155                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2156                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2157                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2158                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2159                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2160                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2161                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2162                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2163                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2164                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2165         }
2166         if (phy->rev <= 8) {
2167                 b43_phy_write(dev, 0x23F, 0x1B0);
2168                 b43_phy_write(dev, 0x240, 0x1B0);
2169         }
2170         if (phy->rev >= 8)
2171                 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2172
2173         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2174         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2175         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2176         tmp32 &= 0xffffff;
2177         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2178         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2179         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2180
2181         if (b43_nphy_ipa(dev))
2182                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2183                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2184
2185         b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000);
2186         b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000);
2187
2188         lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2189         lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2190         lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2191         if (b43_nphy_ipa(dev)) {
2192                 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2193                     phy->radio_rev == 7 || phy->radio_rev == 8) {
2194                         bcap_val = b43_radio_read(dev, 0x16b);
2195                         scap_val = b43_radio_read(dev, 0x16a);
2196                         scap_val_11b = scap_val;
2197                         bcap_val_11b = bcap_val;
2198                         if (phy->radio_rev == 5 && phy->is_40mhz) {
2199                                 scap_val_11n_20 = scap_val;
2200                                 bcap_val_11n_20 = bcap_val;
2201                                 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2202                                 rccal_ovrd = true;
2203                         } else { /* Rev 7/8 */
2204                                 lpf_20 = 4;
2205                                 lpf_11b = 1;
2206                                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2207                                         scap_val_11n_20 = 0xc;
2208                                         bcap_val_11n_20 = 0xc;
2209                                         scap_val_11n_40 = 0xa;
2210                                         bcap_val_11n_40 = 0xa;
2211                                 } else {
2212                                         scap_val_11n_20 = 0x14;
2213                                         bcap_val_11n_20 = 0x14;
2214                                         scap_val_11n_40 = 0xf;
2215                                         bcap_val_11n_40 = 0xf;
2216                                 }
2217                                 rccal_ovrd = true;
2218                         }
2219                 }
2220         } else {
2221                 if (phy->radio_rev == 5) {
2222                         lpf_20 = 1;
2223                         lpf_40 = 3;
2224                         bcap_val = b43_radio_read(dev, 0x16b);
2225                         scap_val = b43_radio_read(dev, 0x16a);
2226                         scap_val_11b = scap_val;
2227                         bcap_val_11b = bcap_val;
2228                         scap_val_11n_20 = 0x11;
2229                         scap_val_11n_40 = 0x11;
2230                         bcap_val_11n_20 = 0x13;
2231                         bcap_val_11n_40 = 0x13;
2232                         rccal_ovrd = true;
2233                 }
2234         }
2235         if (rccal_ovrd) {
2236                 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2237                                    (scap_val_11b << 3) |
2238                                    lpf_11b;
2239                 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2240                                    (scap_val_11n_20 << 3) |
2241                                    lpf_20;
2242                 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2243                                    (scap_val_11n_40 << 3) |
2244                                    lpf_40;
2245                 for (core = 0; core < 2; core++) {
2246                         b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2247                                        rx2tx_lut_20_11b);
2248                         b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2249                                        rx2tx_lut_20_11n);
2250                         b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2251                                        rx2tx_lut_20_11n);
2252                         b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2253                                        rx2tx_lut_40_11n);
2254                         b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2255                                        rx2tx_lut_40_11n);
2256                         b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2257                                        rx2tx_lut_40_11n);
2258                         b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2259                                        rx2tx_lut_40_11n);
2260                         b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2261                                        rx2tx_lut_40_11n);
2262                 }
2263                 b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2);
2264         }
2265         b43_phy_write(dev, 0x32F, 0x3);
2266         if (phy->radio_rev == 4 || phy->radio_rev == 6)
2267                 b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0);
2268
2269         if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2270                 if (sprom->revision &&
2271                     sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2272                         b43_radio_write(dev, 0x5, 0x05);
2273                         b43_radio_write(dev, 0x6, 0x30);
2274                         b43_radio_write(dev, 0x7, 0x00);
2275                         b43_radio_set(dev, 0x4f, 0x1);
2276                         b43_radio_set(dev, 0xd4, 0x1);
2277                         bias = 0x1f;
2278                         conv = 0x6f;
2279                         filt = 0xaa;
2280                 } else {
2281                         bias = 0x2b;
2282                         conv = 0x7f;
2283                         filt = 0xee;
2284                 }
2285                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2286                         for (core = 0; core < 2; core++) {
2287                                 if (core == 0) {
2288                                         b43_radio_write(dev, 0x5F, bias);
2289                                         b43_radio_write(dev, 0x64, conv);
2290                                         b43_radio_write(dev, 0x66, filt);
2291                                 } else {
2292                                         b43_radio_write(dev, 0xE8, bias);
2293                                         b43_radio_write(dev, 0xE9, conv);
2294                                         b43_radio_write(dev, 0xEB, filt);
2295                                 }
2296                         }
2297                 }
2298         }
2299
2300         if (b43_nphy_ipa(dev)) {
2301                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2302                         if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2303                             phy->radio_rev == 6) {
2304                                 for (core = 0; core < 2; core++) {
2305                                         if (core == 0)
2306                                                 b43_radio_write(dev, 0x51,
2307                                                                 0x7f);
2308                                         else
2309                                                 b43_radio_write(dev, 0xd6,
2310                                                                 0x7f);
2311                                 }
2312                         }
2313                         if (phy->radio_rev == 3) {
2314                                 for (core = 0; core < 2; core++) {
2315                                         if (core == 0) {
2316                                                 b43_radio_write(dev, 0x64,
2317                                                                 0x13);
2318                                                 b43_radio_write(dev, 0x5F,
2319                                                                 0x1F);
2320                                                 b43_radio_write(dev, 0x66,
2321                                                                 0xEE);
2322                                                 b43_radio_write(dev, 0x59,
2323                                                                 0x8A);
2324                                                 b43_radio_write(dev, 0x80,
2325                                                                 0x3E);
2326                                         } else {
2327                                                 b43_radio_write(dev, 0x69,
2328                                                                 0x13);
2329                                                 b43_radio_write(dev, 0xE8,
2330                                                                 0x1F);
2331                                                 b43_radio_write(dev, 0xEB,
2332                                                                 0xEE);
2333                                                 b43_radio_write(dev, 0xDE,
2334                                                                 0x8A);
2335                                                 b43_radio_write(dev, 0x105,
2336                                                                 0x3E);
2337                                         }
2338                                 }
2339                         } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2340                                 if (!phy->is_40mhz) {
2341                                         b43_radio_write(dev, 0x5F, 0x14);
2342                                         b43_radio_write(dev, 0xE8, 0x12);
2343                                 } else {
2344                                         b43_radio_write(dev, 0x5F, 0x16);
2345                                         b43_radio_write(dev, 0xE8, 0x16);
2346                                 }
2347                         }
2348                 } else {
2349                         u16 freq = phy->channel_freq;
2350                         if ((freq >= 5180 && freq <= 5230) ||
2351                             (freq >= 5745 && freq <= 5805)) {
2352                                 b43_radio_write(dev, 0x7D, 0xFF);
2353                                 b43_radio_write(dev, 0xFE, 0xFF);
2354                         }
2355                 }
2356         } else {
2357                 if (phy->radio_rev != 5) {
2358                         for (core = 0; core < 2; core++) {
2359                                 if (core == 0) {
2360                                         b43_radio_write(dev, 0x5c, 0x61);
2361                                         b43_radio_write(dev, 0x51, 0x70);
2362                                 } else {
2363                                         b43_radio_write(dev, 0xe1, 0x61);
2364                                         b43_radio_write(dev, 0xd6, 0x70);
2365                                 }
2366                         }
2367                 }
2368         }
2369
2370         if (phy->radio_rev == 4) {
2371                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2372                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2373                 for (core = 0; core < 2; core++) {
2374                         if (core == 0) {
2375                                 b43_radio_write(dev, 0x1a1, 0x00);
2376                                 b43_radio_write(dev, 0x1a2, 0x3f);
2377                                 b43_radio_write(dev, 0x1a6, 0x3f);
2378                         } else {
2379                                 b43_radio_write(dev, 0x1a7, 0x00);
2380                                 b43_radio_write(dev, 0x1ab, 0x3f);
2381                                 b43_radio_write(dev, 0x1ac, 0x3f);
2382                         }
2383                 }
2384         } else {
2385                 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2386                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2387                 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2388                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2389
2390                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2391                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2392                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2393                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2394                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2395                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2396
2397                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2398                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2399                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2400                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2401         }
2402
2403         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2404
2405         b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2406         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2407         b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2408         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2409         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2410         b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2411         b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2412
2413         if (!phy->is_40mhz) {
2414                 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2415                 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2416         } else {
2417                 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2418                 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2419         }
2420
2421         b43_nphy_gain_ctl_workarounds(dev);
2422
2423         /* TODO
2424         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2425                             aux_adc_vmid_rev7_core0);
2426         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2427                             aux_adc_vmid_rev7_core1);
2428         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2429                             aux_adc_gain_rev7);
2430         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2431                             aux_adc_gain_rev7);
2432         */
2433 }
2434
2435 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2436 {
2437         struct b43_phy_n *nphy = dev->phy.n;
2438         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2439
2440         /* TX to RX */
2441         u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
2442         u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
2443         /* RX to TX */
2444         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2445                                         0x1F };
2446         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2447         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2448         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2449
2450         u16 tmp16;
2451         u32 tmp32;
2452
2453         b43_phy_write(dev, 0x23f, 0x1f8);
2454         b43_phy_write(dev, 0x240, 0x1f8);
2455
2456         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2457         tmp32 &= 0xffffff;
2458         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2459
2460         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2461         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2462         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2463         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2464         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2465         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2466
2467         b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
2468         b43_phy_write(dev, 0x2AE, 0x000C);
2469
2470         /* TX to RX */
2471         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2472                                  ARRAY_SIZE(tx2rx_events));
2473
2474         /* RX to TX */
2475         if (b43_nphy_ipa(dev))
2476                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2477                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2478         if (nphy->hw_phyrxchain != 3 &&
2479             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2480                 if (b43_nphy_ipa(dev)) {
2481                         rx2tx_delays[5] = 59;
2482                         rx2tx_delays[6] = 1;
2483                         rx2tx_events[7] = 0x1F;
2484                 }
2485                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
2486                                          ARRAY_SIZE(rx2tx_events));
2487         }
2488
2489         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2490                 0x2 : 0x9C40;
2491         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2492
2493         b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
2494
2495         if (!dev->phy.is_40mhz) {
2496                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2497                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2498         } else {
2499                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2500                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2501         }
2502
2503         b43_nphy_gain_ctl_workarounds(dev);
2504
2505         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2506         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
2507
2508         /* TODO */
2509
2510         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2511         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2512         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2513         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2514         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2515         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2516         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2517         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2518         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2519         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2520         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2521         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2522
2523         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2524
2525         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2526              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2527             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2528              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2529                 tmp32 = 0x00088888;
2530         else
2531                 tmp32 = 0x88888888;
2532         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2533         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2534         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2535
2536         if (dev->phy.rev == 4 &&
2537             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2538                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2539                                 0x70);
2540                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2541                                 0x70);
2542         }
2543
2544         /* Dropped probably-always-true condition */
2545         b43_phy_write(dev, 0x224, 0x03eb);
2546         b43_phy_write(dev, 0x225, 0x03eb);
2547         b43_phy_write(dev, 0x226, 0x0341);
2548         b43_phy_write(dev, 0x227, 0x0341);
2549         b43_phy_write(dev, 0x228, 0x042b);
2550         b43_phy_write(dev, 0x229, 0x042b);
2551         b43_phy_write(dev, 0x22a, 0x0381);
2552         b43_phy_write(dev, 0x22b, 0x0381);
2553         b43_phy_write(dev, 0x22c, 0x042b);
2554         b43_phy_write(dev, 0x22d, 0x042b);
2555         b43_phy_write(dev, 0x22e, 0x0381);
2556         b43_phy_write(dev, 0x22f, 0x0381);
2557
2558         if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2559                 ; /* TODO: 0x0080000000000000 HF */
2560 }
2561
2562 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2563 {
2564         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2565         struct b43_phy *phy = &dev->phy;
2566         struct b43_phy_n *nphy = phy->n;
2567
2568         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2569         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
2570
2571         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2572         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2573
2574         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2575             dev->dev->board_type == 0x8B) {
2576                 delays1[0] = 0x1;
2577                 delays1[5] = 0x14;
2578         }
2579
2580         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2581             nphy->band5g_pwrgain) {
2582                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2583                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2584         } else {
2585                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2586                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2587         }
2588
2589         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2590         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2591         if (dev->phy.rev < 3) {
2592                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2593                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2594         }
2595
2596         if (dev->phy.rev < 2) {
2597                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2598                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2599                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2600                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2601                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2602                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2603         }
2604
2605         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2606         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2607         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2608         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2609
2610         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2611         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2612
2613         b43_nphy_gain_ctl_workarounds(dev);
2614
2615         if (dev->phy.rev < 2) {
2616                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2617                         b43_hf_write(dev, b43_hf_read(dev) |
2618                                         B43_HF_MLADVW);
2619         } else if (dev->phy.rev == 2) {
2620                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2621                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2622         }
2623
2624         if (dev->phy.rev < 2)
2625                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2626                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2627
2628         /* Set phase track alpha and beta */
2629         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2630         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2631         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2632         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2633         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2634         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2635
2636         if (dev->phy.rev < 3) {
2637                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2638                              ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2639                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2640                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2641                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2642         }
2643
2644         if (dev->phy.rev == 2)
2645                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2646                                 B43_NPHY_FINERX2_CGC_DECGC);
2647 }
2648
2649 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2650 static void b43_nphy_workarounds(struct b43_wldev *dev)
2651 {
2652         struct b43_phy *phy = &dev->phy;
2653         struct b43_phy_n *nphy = phy->n;
2654
2655         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2656                 b43_nphy_classifier(dev, 1, 0);
2657         else
2658                 b43_nphy_classifier(dev, 1, 1);
2659
2660         if (nphy->hang_avoid)
2661                 b43_nphy_stay_in_carrier_search(dev, 1);
2662
2663         b43_phy_set(dev, B43_NPHY_IQFLIP,
2664                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2665
2666         if (dev->phy.rev >= 7)
2667                 b43_nphy_workarounds_rev7plus(dev);
2668         else if (dev->phy.rev >= 3)
2669                 b43_nphy_workarounds_rev3plus(dev);
2670         else
2671                 b43_nphy_workarounds_rev1_2(dev);
2672
2673         if (nphy->hang_avoid)
2674                 b43_nphy_stay_in_carrier_search(dev, 0);
2675 }
2676
2677 /**************************************************
2678  * Tx/Rx common
2679  **************************************************/
2680
2681 /*
2682  * Transmits a known value for LO calibration
2683  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2684  */
2685 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2686                                 bool iqmode, bool dac_test)
2687 {
2688         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2689         if (samp == 0)
2690                 return -1;
2691         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2692         return 0;
2693 }
2694
2695 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2696 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2697 {
2698         struct b43_phy_n *nphy = dev->phy.n;
2699
2700         bool override = false;
2701         u16 chain = 0x33;
2702
2703         if (nphy->txrx_chain == 0) {
2704                 chain = 0x11;
2705                 override = true;
2706         } else if (nphy->txrx_chain == 1) {
2707                 chain = 0x22;
2708                 override = true;
2709         }
2710
2711         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2712                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2713                         chain);
2714
2715         if (override)
2716                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2717                                 B43_NPHY_RFSEQMODE_CAOVER);
2718         else
2719                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2720                                 ~B43_NPHY_RFSEQMODE_CAOVER);
2721 }
2722
2723 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2724 static void b43_nphy_stop_playback(struct b43_wldev *dev)
2725 {
2726         struct b43_phy_n *nphy = dev->phy.n;
2727         u16 tmp;
2728
2729         if (nphy->hang_avoid)
2730                 b43_nphy_stay_in_carrier_search(dev, 1);
2731
2732         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2733         if (tmp & 0x1)
2734                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2735         else if (tmp & 0x2)
2736                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2737
2738         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2739
2740         if (nphy->bb_mult_save & 0x80000000) {
2741                 tmp = nphy->bb_mult_save & 0xFFFF;
2742                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2743                 nphy->bb_mult_save = 0;
2744         }
2745
2746         if (nphy->hang_avoid)
2747                 b43_nphy_stay_in_carrier_search(dev, 0);
2748 }
2749
2750 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2751 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2752                                         struct nphy_txgains target,
2753                                         struct nphy_iqcal_params *params)
2754 {
2755         int i, j, indx;
2756         u16 gain;
2757
2758         if (dev->phy.rev >= 3) {
2759                 params->txgm = target.txgm[core];
2760                 params->pga = target.pga[core];
2761                 params->pad = target.pad[core];
2762                 params->ipa = target.ipa[core];
2763                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2764                                         (params->pad << 4) | (params->ipa);
2765                 for (j = 0; j < 5; j++)
2766                         params->ncorr[j] = 0x79;
2767         } else {
2768                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2769                         (target.txgm[core] << 8);
2770
2771                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2772                         1 : 0;
2773                 for (i = 0; i < 9; i++)
2774                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2775                                 break;
2776                 i = min(i, 8);
2777
2778                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2779                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2780                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2781                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2782                                         (params->pad << 2);
2783                 for (j = 0; j < 4; j++)
2784                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2785         }
2786 }
2787
2788 /**************************************************
2789  * Tx and Rx
2790  **************************************************/
2791
2792 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2793 {//TODO
2794 }
2795
2796 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2797                                                         bool ignore_tssi)
2798 {//TODO
2799         return B43_TXPWR_RES_DONE;
2800 }
2801
2802 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2803 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2804 {
2805         struct b43_phy_n *nphy = dev->phy.n;
2806         u8 i;
2807         u16 bmask, val, tmp;
2808         enum ieee80211_band band = b43_current_band(dev->wl);
2809
2810         if (nphy->hang_avoid)
2811                 b43_nphy_stay_in_carrier_search(dev, 1);
2812
2813         nphy->txpwrctrl = enable;
2814         if (!enable) {
2815                 if (dev->phy.rev >= 3 &&
2816                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2817                      (B43_NPHY_TXPCTL_CMD_COEFF |
2818                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2819                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2820                         /* We disable enabled TX pwr ctl, save it's state */
2821                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2822                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2823                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2824                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2825                 }
2826
2827                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2828                 for (i = 0; i < 84; i++)
2829                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2830
2831                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2832                 for (i = 0; i < 84; i++)
2833                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2834
2835                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2836                 if (dev->phy.rev >= 3)
2837                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2838                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
2839
2840                 if (dev->phy.rev >= 3) {
2841                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2842                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2843                 } else {
2844                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2845                 }
2846
2847                 if (dev->phy.rev == 2)
2848                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2849                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2850                 else if (dev->phy.rev < 2)
2851                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2852                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
2853
2854                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2855                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
2856         } else {
2857                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2858                                     nphy->adj_pwr_tbl);
2859                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2860                                     nphy->adj_pwr_tbl);
2861
2862                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2863                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2864                 /* wl does useless check for "enable" param here */
2865                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2866                 if (dev->phy.rev >= 3) {
2867                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2868                         if (val)
2869                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2870                 }
2871                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
2872
2873                 if (band == IEEE80211_BAND_5GHZ) {
2874                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2875                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2876                         if (dev->phy.rev > 1)
2877                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2878                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2879                                                 0x64);
2880                 }
2881
2882                 if (dev->phy.rev >= 3) {
2883                         if (nphy->tx_pwr_idx[0] != 128 &&
2884                             nphy->tx_pwr_idx[1] != 128) {
2885                                 /* Recover TX pwr ctl state */
2886                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2887                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
2888                                                 nphy->tx_pwr_idx[0]);
2889                                 if (dev->phy.rev > 1)
2890                                         b43_phy_maskset(dev,
2891                                                 B43_NPHY_TXPCTL_INIT,
2892                                                 ~0xff, nphy->tx_pwr_idx[1]);
2893                         }
2894                 }
2895
2896                 if (dev->phy.rev >= 3) {
2897                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2898                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2899                 } else {
2900                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2901                 }
2902
2903                 if (dev->phy.rev == 2)
2904                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2905                 else if (dev->phy.rev < 2)
2906                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
2907
2908                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2909                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
2910
2911                 if (b43_nphy_ipa(dev)) {
2912                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2913                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
2914                 }
2915         }
2916
2917         if (nphy->hang_avoid)
2918                 b43_nphy_stay_in_carrier_search(dev, 0);
2919 }
2920
2921 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
2922 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
2923 {
2924         struct b43_phy_n *nphy = dev->phy.n;
2925         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2926
2927         u8 txpi[2], bbmult, i;
2928         u16 tmp, radio_gain, dac_gain;
2929         u16 freq = dev->phy.channel_freq;
2930         u32 txgain;
2931         /* u32 gaintbl; rev3+ */
2932
2933         if (nphy->hang_avoid)
2934                 b43_nphy_stay_in_carrier_search(dev, 1);
2935
2936         if (dev->phy.rev >= 7) {
2937                 txpi[0] = txpi[1] = 30;
2938         } else if (dev->phy.rev >= 3) {
2939                 txpi[0] = 40;
2940                 txpi[1] = 40;
2941         } else if (sprom->revision < 4) {
2942                 txpi[0] = 72;
2943                 txpi[1] = 72;
2944         } else {
2945                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2946                         txpi[0] = sprom->txpid2g[0];
2947                         txpi[1] = sprom->txpid2g[1];
2948                 } else if (freq >= 4900 && freq < 5100) {
2949                         txpi[0] = sprom->txpid5gl[0];
2950                         txpi[1] = sprom->txpid5gl[1];
2951                 } else if (freq >= 5100 && freq < 5500) {
2952                         txpi[0] = sprom->txpid5g[0];
2953                         txpi[1] = sprom->txpid5g[1];
2954                 } else if (freq >= 5500) {
2955                         txpi[0] = sprom->txpid5gh[0];
2956                         txpi[1] = sprom->txpid5gh[1];
2957                 } else {
2958                         txpi[0] = 91;
2959                         txpi[1] = 91;
2960                 }
2961         }
2962         if (dev->phy.rev < 7 &&
2963             (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
2964                 txpi[0] = txpi[1] = 91;
2965
2966         /*
2967         for (i = 0; i < 2; i++) {
2968                 nphy->txpwrindex[i].index_internal = txpi[i];
2969                 nphy->txpwrindex[i].index_internal_save = txpi[i];
2970         }
2971         */
2972
2973         for (i = 0; i < 2; i++) {
2974                 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
2975
2976                 if (dev->phy.rev >= 3)
2977                         radio_gain = (txgain >> 16) & 0x1FFFF;
2978                 else
2979                         radio_gain = (txgain >> 16) & 0x1FFF;
2980
2981                 if (dev->phy.rev >= 7)
2982                         dac_gain = (txgain >> 8) & 0x7;
2983                 else
2984                         dac_gain = (txgain >> 8) & 0x3F;
2985                 bbmult = txgain & 0xFF;
2986
2987                 if (dev->phy.rev >= 3) {
2988                         if (i == 0)
2989                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2990                         else
2991                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2992                 } else {
2993                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2994                 }
2995
2996                 if (i == 0)
2997                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
2998                 else
2999                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3000
3001                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3002
3003                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3004                 if (i == 0)
3005                         tmp = (tmp & 0x00FF) | (bbmult << 8);
3006                 else
3007                         tmp = (tmp & 0xFF00) | bbmult;
3008                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3009
3010                 if (b43_nphy_ipa(dev)) {
3011                         u32 tmp32;
3012                         u16 reg = (i == 0) ?
3013                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3014                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3015                                                               576 + txpi[i]));
3016                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3017                         b43_phy_set(dev, reg, 0x4);
3018                 }
3019         }
3020
3021         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3022
3023         if (nphy->hang_avoid)
3024                 b43_nphy_stay_in_carrier_search(dev, 0);
3025 }
3026
3027 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3028 {
3029         struct b43_phy *phy = &dev->phy;
3030
3031         u8 core;
3032         u16 r; /* routing */
3033
3034         if (phy->rev >= 7) {
3035                 for (core = 0; core < 2; core++) {
3036                         r = core ? 0x190 : 0x170;
3037                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3038                                 b43_radio_write(dev, r + 0x5, 0x5);
3039                                 b43_radio_write(dev, r + 0x9, 0xE);
3040                                 if (phy->rev != 5)
3041                                         b43_radio_write(dev, r + 0xA, 0);
3042                                 if (phy->rev != 7)
3043                                         b43_radio_write(dev, r + 0xB, 1);
3044                                 else
3045                                         b43_radio_write(dev, r + 0xB, 0x31);
3046                         } else {
3047                                 b43_radio_write(dev, r + 0x5, 0x9);
3048                                 b43_radio_write(dev, r + 0x9, 0xC);
3049                                 b43_radio_write(dev, r + 0xB, 0x0);
3050                                 if (phy->rev != 5)
3051                                         b43_radio_write(dev, r + 0xA, 1);
3052                                 else
3053                                         b43_radio_write(dev, r + 0xA, 0x31);
3054                         }
3055                         b43_radio_write(dev, r + 0x6, 0);
3056                         b43_radio_write(dev, r + 0x7, 0);
3057                         b43_radio_write(dev, r + 0x8, 3);
3058                         b43_radio_write(dev, r + 0xC, 0);
3059                 }
3060         } else {
3061                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3062                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3063                 else
3064                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3065                 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3066                 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3067
3068                 for (core = 0; core < 2; core++) {
3069                         r = core ? B2056_TX1 : B2056_TX0;
3070
3071                         b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3072                         b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3073                         b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3074                         b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3075                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3076                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3077                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3078                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3079                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3080                                                 0x5);
3081                                 if (phy->rev != 5)
3082                                         b43_radio_write(dev, r | B2056_TX_TSSIA,
3083                                                         0x00);
3084                                 if (phy->rev >= 5)
3085                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3086                                                         0x31);
3087                                 else
3088                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3089                                                         0x11);
3090                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3091                                                 0xE);
3092                         } else {
3093                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3094                                                 0x9);
3095                                 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3096                                 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3097                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3098                                                 0xC);
3099                         }
3100                 }
3101         }
3102 }
3103
3104 /*
3105  * Stop radio and transmit known signal. Then check received signal strength to
3106  * get TSSI (Transmit Signal Strength Indicator).
3107  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3108  */
3109 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3110 {
3111         struct b43_phy *phy = &dev->phy;
3112         struct b43_phy_n *nphy = dev->phy.n;
3113
3114         u32 tmp;
3115         s32 rssi[4] = { };
3116
3117         /* TODO: check if we can transmit */
3118
3119         if (b43_nphy_ipa(dev))
3120                 b43_nphy_ipa_internal_tssi_setup(dev);
3121
3122         if (phy->rev >= 7)
3123                 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0);
3124         else if (phy->rev >= 3)
3125                 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
3126
3127         b43_nphy_stop_playback(dev);
3128         b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3129         udelay(20);
3130         tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1);
3131         b43_nphy_stop_playback(dev);
3132         b43_nphy_rssi_select(dev, 0, 0);
3133
3134         if (phy->rev >= 7)
3135                 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0);
3136         else if (phy->rev >= 3)
3137                 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
3138
3139         if (phy->rev >= 3) {
3140                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3141                 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3142         } else {
3143                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3144                 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3145         }
3146         nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3147         nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3148 }
3149
3150 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3151 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3152 {
3153         struct b43_phy_n *nphy = dev->phy.n;
3154
3155         u8 idx, delta;
3156         u8 i, stf_mode;
3157
3158         for (i = 0; i < 4; i++)
3159                 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3160
3161         for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3162                 delta = 0;
3163                 switch (stf_mode) {
3164                 case 0:
3165                         if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3166                                 idx = 68;
3167                         } else {
3168                                 delta = 1;
3169                                 idx = dev->phy.is_40mhz ? 52 : 4;
3170                         }
3171                         break;
3172                 case 1:
3173                         idx = dev->phy.is_40mhz ? 76 : 28;
3174                         break;
3175                 case 2:
3176                         idx = dev->phy.is_40mhz ? 84 : 36;
3177                         break;
3178                 case 3:
3179                         idx = dev->phy.is_40mhz ? 92 : 44;
3180                         break;
3181                 }
3182
3183                 for (i = 0; i < 20; i++) {
3184                         nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3185                                 nphy->tx_power_offset[idx];
3186                         if (i == 0)
3187                                 idx += delta;
3188                         if (i == 14)
3189                                 idx += 1 - delta;
3190                         if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3191                             i == 13)
3192                                 idx += 1;
3193                 }
3194         }
3195 }
3196
3197 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3198 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3199 {
3200         struct b43_phy_n *nphy = dev->phy.n;
3201         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3202
3203         s16 a1[2], b0[2], b1[2];
3204         u8 idle[2];
3205         s8 target[2];
3206         s32 num, den, pwr;
3207         u32 regval[64];
3208
3209         u16 freq = dev->phy.channel_freq;
3210         u16 tmp;
3211         u16 r; /* routing */
3212         u8 i, c;
3213
3214         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3215                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3216                 b43_read32(dev, B43_MMIO_MACCTL);
3217                 udelay(1);
3218         }
3219
3220         if (nphy->hang_avoid)
3221                 b43_nphy_stay_in_carrier_search(dev, true);
3222
3223         b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3224         if (dev->phy.rev >= 3)
3225                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3226                              ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3227         else
3228                 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3229                             B43_NPHY_TXPCTL_CMD_PCTLEN);
3230
3231         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3232                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3233
3234         if (sprom->revision < 4) {
3235                 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3236                 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3237                 target[0] = target[1] = 52;
3238                 a1[0] = a1[1] = -424;
3239                 b0[0] = b0[1] = 5612;
3240                 b1[0] = b1[1] = -1393;
3241         } else {
3242                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3243                         for (c = 0; c < 2; c++) {
3244                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3245                                 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3246                                 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3247                                 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3248                                 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3249                         }
3250                 } else if (freq >= 4900 && freq < 5100) {
3251                         for (c = 0; c < 2; c++) {
3252                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3253                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3254                                 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3255                                 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3256                                 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3257                         }
3258                 } else if (freq >= 5100 && freq < 5500) {
3259                         for (c = 0; c < 2; c++) {
3260                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3261                                 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3262                                 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3263                                 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3264                                 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3265                         }
3266                 } else if (freq >= 5500) {
3267                         for (c = 0; c < 2; c++) {
3268                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3269                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3270                                 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3271                                 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3272                                 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3273                         }
3274                 } else {
3275                         idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3276                         idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3277                         target[0] = target[1] = 52;
3278                         a1[0] = a1[1] = -424;
3279                         b0[0] = b0[1] = 5612;
3280                         b1[0] = b1[1] = -1393;
3281                 }
3282         }
3283         /* target[0] = target[1] = nphy->tx_power_max; */
3284
3285         if (dev->phy.rev >= 3) {
3286                 if (sprom->fem.ghz2.tssipos)
3287                         b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3288                 if (dev->phy.rev >= 7) {
3289                         for (c = 0; c < 2; c++) {
3290                                 r = c ? 0x190 : 0x170;
3291                                 if (b43_nphy_ipa(dev))
3292                                         b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3293                         }
3294                 } else {
3295                         if (b43_nphy_ipa(dev)) {
3296                                 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3297                                 b43_radio_write(dev,
3298                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3299                                 b43_radio_write(dev,
3300                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3301                         } else {
3302                                 b43_radio_write(dev,
3303                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3304                                 b43_radio_write(dev,
3305                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3306                         }
3307                 }
3308         }
3309
3310         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3311                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3312                 b43_read32(dev, B43_MMIO_MACCTL);
3313                 udelay(1);
3314         }
3315
3316         if (dev->phy.rev >= 7) {
3317                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3318                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3319                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3320                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3321         } else {
3322                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3323                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3324                 if (dev->phy.rev > 1)
3325                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3326                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3327         }
3328
3329         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3330                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3331
3332         b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3333                       0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3334                       3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3335         b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3336                       idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3337                       idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3338                       B43_NPHY_TXPCTL_ITSSI_BINF);
3339         b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3340                       target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3341                       target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3342
3343         for (c = 0; c < 2; c++) {
3344                 for (i = 0; i < 64; i++) {
3345                         num = 8 * (16 * b0[c] + b1[c] * i);
3346                         den = 32768 + a1[c] * i;
3347                         pwr = max((4 * num + den / 2) / den, -8);
3348                         if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3349                                 pwr = max(pwr, target[c] + 1);
3350                         regval[i] = pwr;
3351                 }
3352                 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3353         }
3354
3355         b43_nphy_tx_prepare_adjusted_power_table(dev);
3356         /*
3357         b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3358         b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3359         */
3360
3361         if (nphy->hang_avoid)
3362                 b43_nphy_stay_in_carrier_search(dev, false);
3363 }
3364
3365 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3366 {
3367         struct b43_phy *phy = &dev->phy;
3368
3369         const u32 *table = NULL;
3370         u32 rfpwr_offset;
3371         u8 pga_gain;
3372         int i;
3373
3374         table = b43_nphy_get_tx_gain_table(dev);
3375         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3376         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3377
3378         if (phy->rev >= 3) {
3379 #if 0
3380                 nphy->gmval = (table[0] >> 16) & 0x7000;
3381 #endif
3382
3383                 for (i = 0; i < 128; i++) {
3384                         pga_gain = (table[i] >> 24) & 0xF;
3385                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3386                                 rfpwr_offset =
3387                                  b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
3388                         else
3389                                 rfpwr_offset =
3390                                  0; /* FIXME */
3391                         b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3392                                        rfpwr_offset);
3393                         b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3394                                        rfpwr_offset);
3395                 }
3396         }
3397 }
3398
3399 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3400 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
3401 {
3402         struct b43_phy_n *nphy = dev->phy.n;
3403         enum ieee80211_band band;
3404         u16 tmp;
3405
3406         if (!enable) {
3407                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3408                                                        B43_NPHY_RFCTL_INTC1);
3409                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3410                                                        B43_NPHY_RFCTL_INTC2);
3411                 band = b43_current_band(dev->wl);
3412                 if (dev->phy.rev >= 3) {
3413                         if (band == IEEE80211_BAND_5GHZ)
3414                                 tmp = 0x600;
3415                         else
3416                                 tmp = 0x480;
3417                 } else {
3418                         if (band == IEEE80211_BAND_5GHZ)
3419                                 tmp = 0x180;
3420                         else
3421                                 tmp = 0x120;
3422                 }
3423                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3424                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3425         } else {
3426                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3427                                 nphy->rfctrl_intc1_save);
3428                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3429                                 nphy->rfctrl_intc2_save);
3430         }
3431 }
3432
3433 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3434 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3435 {
3436         u16 tmp;
3437
3438         if (dev->phy.rev >= 3) {
3439                 if (b43_nphy_ipa(dev)) {
3440                         tmp = 4;
3441                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3442                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3443                 }
3444
3445                 tmp = 1;
3446                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3447                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3448         }
3449 }
3450
3451 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3452 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3453                                 u16 samps, u8 time, bool wait)
3454 {
3455         int i;
3456         u16 tmp;
3457
3458         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3459         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3460         if (wait)
3461                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
3462         else
3463                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
3464
3465         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3466
3467         for (i = 1000; i; i--) {
3468                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3469                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3470                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3471                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3472                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3473                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3474                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3475                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3476
3477                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3478                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3479                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3480                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3481                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3482                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3483                         return;
3484                 }
3485                 udelay(10);
3486         }
3487         memset(est, 0, sizeof(*est));
3488 }
3489
3490 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3491 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3492                                         struct b43_phy_n_iq_comp *pcomp)
3493 {
3494         if (write) {
3495                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3496                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3497                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3498                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
3499         } else {
3500                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3501                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3502                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3503                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3504         }
3505 }
3506
3507 #if 0
3508 /* Ready but not used anywhere */
3509 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3510 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3511 {
3512         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3513
3514         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3515         if (core == 0) {
3516                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3517                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3518         } else {
3519                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3520                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3521         }
3522         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3523         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3524         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3525         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3526         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3527         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3528         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3529         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3530 }
3531
3532 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3533 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3534 {
3535         u8 rxval, txval;
3536         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3537
3538         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3539         if (core == 0) {
3540                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3541                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3542         } else {
3543                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3544                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3545         }
3546         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3547         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3548         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3549         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3550         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3551         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3552         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3553         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3554
3555         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3556         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3557
3558         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3559                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3560                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3561         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3562                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3563         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3564                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3565         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3566                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
3567
3568         if (core == 0) {
3569                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3570                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3571         } else {
3572                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3573                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3574         }
3575
3576         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
3577         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
3578         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3579
3580         if (core == 0) {
3581                 rxval = 1;
3582                 txval = 8;
3583         } else {
3584                 rxval = 4;
3585                 txval = 2;
3586         }
3587         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
3588         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
3589 }
3590 #endif
3591
3592 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3593 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
3594 {
3595         int i;
3596         s32 iq;
3597         u32 ii;
3598         u32 qq;
3599         int iq_nbits, qq_nbits;
3600         int arsh, brsh;
3601         u16 tmp, a, b;
3602
3603         struct nphy_iq_est est;
3604         struct b43_phy_n_iq_comp old;
3605         struct b43_phy_n_iq_comp new = { };
3606         bool error = false;
3607
3608         if (mask == 0)
3609                 return;
3610
3611         b43_nphy_rx_iq_coeffs(dev, false, &old);
3612         b43_nphy_rx_iq_coeffs(dev, true, &new);
3613         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3614         new = old;
3615
3616         for (i = 0; i < 2; i++) {
3617                 if (i == 0 && (mask & 1)) {
3618                         iq = est.iq0_prod;
3619                         ii = est.i0_pwr;
3620                         qq = est.q0_pwr;
3621                 } else if (i == 1 && (mask & 2)) {
3622                         iq = est.iq1_prod;
3623                         ii = est.i1_pwr;
3624                         qq = est.q1_pwr;
3625                 } else {
3626                         continue;
3627                 }
3628
3629                 if (ii + qq < 2) {
3630                         error = true;
3631                         break;
3632                 }
3633
3634                 iq_nbits = fls(abs(iq));
3635                 qq_nbits = fls(qq);
3636
3637                 arsh = iq_nbits - 20;
3638                 if (arsh >= 0) {
3639                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3640                         tmp = ii >> arsh;
3641                 } else {
3642                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3643                         tmp = ii << -arsh;
3644                 }
3645                 if (tmp == 0) {
3646                         error = true;
3647                         break;
3648                 }
3649                 a /= tmp;
3650
3651                 brsh = qq_nbits - 11;
3652                 if (brsh >= 0) {
3653                         b = (qq << (31 - qq_nbits));
3654                         tmp = ii >> brsh;
3655                 } else {
3656                         b = (qq << (31 - qq_nbits));
3657                         tmp = ii << -brsh;
3658                 }
3659                 if (tmp == 0) {
3660                         error = true;
3661                         break;
3662                 }
3663                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
3664
3665                 if (i == 0 && (mask & 0x1)) {
3666                         if (dev->phy.rev >= 3) {
3667                                 new.a0 = a & 0x3FF;
3668                                 new.b0 = b & 0x3FF;
3669                         } else {
3670                                 new.a0 = b & 0x3FF;
3671                                 new.b0 = a & 0x3FF;
3672                         }
3673                 } else if (i == 1 && (mask & 0x2)) {
3674                         if (dev->phy.rev >= 3) {
3675                                 new.a1 = a & 0x3FF;
3676                                 new.b1 = b & 0x3FF;
3677                         } else {
3678                                 new.a1 = b & 0x3FF;
3679                                 new.b1 = a & 0x3FF;
3680                         }
3681                 }
3682         }
3683
3684         if (error)
3685                 new = old;
3686
3687         b43_nphy_rx_iq_coeffs(dev, true, &new);
3688 }
3689
3690 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3691 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3692 {
3693         u16 array[4];
3694         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
3695
3696         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3697         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3698         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3699         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
3700 }
3701
3702 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3703 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3704 {
3705         struct b43_phy_n *nphy = dev->phy.n;
3706
3707         u8 channel = dev->phy.channel;
3708         int tone[2] = { 57, 58 };
3709         u32 noise[2] = { 0x3FF, 0x3FF };
3710
3711         B43_WARN_ON(dev->phy.rev < 3);
3712
3713         if (nphy->hang_avoid)
3714                 b43_nphy_stay_in_carrier_search(dev, 1);
3715
3716         if (nphy->gband_spurwar_en) {
3717                 /* TODO: N PHY Adjust Analog Pfbw (7) */
3718                 if (channel == 11 && dev->phy.is_40mhz)
3719                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3720                 else
3721                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3722                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
3723         }
3724
3725         if (nphy->aband_spurwar_en) {
3726                 if (channel == 54) {
3727                         tone[0] = 0x20;
3728                         noise[0] = 0x25F;
3729                 } else if (channel == 38 || channel == 102 || channel == 118) {
3730                         if (0 /* FIXME */) {
3731                                 tone[0] = 0x20;
3732                                 noise[0] = 0x21F;
3733                         } else {
3734                                 tone[0] = 0;
3735                                 noise[0] = 0;
3736                         }
3737                 } else if (channel == 134) {
3738                         tone[0] = 0x20;
3739                         noise[0] = 0x21F;
3740                 } else if (channel == 151) {
3741                         tone[0] = 0x10;
3742                         noise[0] = 0x23F;
3743                 } else if (channel == 153 || channel == 161) {
3744                         tone[0] = 0x30;
3745                         noise[0] = 0x23F;
3746                 } else {
3747                         tone[0] = 0;
3748                         noise[0] = 0;
3749                 }
3750
3751                 if (!tone[0] && !noise[0])
3752                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
3753                 else
3754                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3755         }
3756
3757         if (nphy->hang_avoid)
3758                 b43_nphy_stay_in_carrier_search(dev, 0);
3759 }
3760
3761 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3762 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3763 {
3764         struct b43_phy_n *nphy = dev->phy.n;
3765         int i, j;
3766         u32 tmp;
3767         u32 cur_real, cur_imag, real_part, imag_part;
3768
3769         u16 buffer[7];
3770
3771         if (nphy->hang_avoid)
3772                 b43_nphy_stay_in_carrier_search(dev, true);
3773
3774         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3775
3776         for (i = 0; i < 2; i++) {
3777                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3778                         (buffer[i * 2 + 1] & 0x3FF);
3779                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3780                                 (((i + 26) << 10) | 320));
3781                 for (j = 0; j < 128; j++) {
3782                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3783                                         ((tmp >> 16) & 0xFFFF));
3784                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3785                                         (tmp & 0xFFFF));
3786                 }
3787         }
3788
3789         for (i = 0; i < 2; i++) {
3790                 tmp = buffer[5 + i];
3791                 real_part = (tmp >> 8) & 0xFF;
3792                 imag_part = (tmp & 0xFF);
3793                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3794                                 (((i + 26) << 10) | 448));
3795
3796                 if (dev->phy.rev >= 3) {
3797                         cur_real = real_part;
3798                         cur_imag = imag_part;
3799                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3800                 }
3801
3802                 for (j = 0; j < 128; j++) {
3803                         if (dev->phy.rev < 3) {
3804                                 cur_real = (real_part * loscale[j] + 128) >> 8;
3805                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3806                                 tmp = ((cur_real & 0xFF) << 8) |
3807                                         (cur_imag & 0xFF);
3808                         }
3809                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3810                                         ((tmp >> 16) & 0xFFFF));
3811                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3812                                         (tmp & 0xFFFF));
3813                 }
3814         }
3815
3816         if (dev->phy.rev >= 3) {
3817                 b43_shm_write16(dev, B43_SHM_SHARED,
3818                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3819                 b43_shm_write16(dev, B43_SHM_SHARED,
3820                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
3821         }
3822
3823         if (nphy->hang_avoid)
3824                 b43_nphy_stay_in_carrier_search(dev, false);
3825 }
3826
3827 /*
3828  * Restore RSSI Calibration
3829  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3830  */
3831 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3832 {
3833         struct b43_phy_n *nphy = dev->phy.n;
3834
3835         u16 *rssical_radio_regs = NULL;
3836         u16 *rssical_phy_regs = NULL;
3837
3838         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3839                 if (!nphy->rssical_chanspec_2G.center_freq)
3840                         return;
3841                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3842                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3843         } else {
3844                 if (!nphy->rssical_chanspec_5G.center_freq)
3845                         return;
3846                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3847                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3848         }
3849
3850         /* TODO use some definitions */
3851         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
3852         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
3853
3854         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3855         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3856         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3857         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3858
3859         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3860         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3861         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3862         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3863
3864         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3865         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3866         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3867         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3868 }
3869
3870 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
3871 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3872 {
3873         struct b43_phy_n *nphy = dev->phy.n;
3874         u16 *save = nphy->tx_rx_cal_radio_saveregs;
3875         u16 tmp;
3876         u8 offset, i;
3877
3878         if (dev->phy.rev >= 3) {
3879             for (i = 0; i < 2; i++) {
3880                 tmp = (i == 0) ? 0x2000 : 0x3000;
3881                 offset = i * 11;
3882
3883                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
3884                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
3885                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
3886                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
3887                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
3888                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
3889                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
3890                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
3891                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
3892                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
3893                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
3894
3895                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3896                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3897                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3898                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3899                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3900                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3901                         if (nphy->ipa5g_on) {
3902                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
3903                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
3904                         } else {
3905                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3906                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
3907                         }
3908                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3909                 } else {
3910                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3911                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3912                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3913                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3914                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3915                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
3916                         if (nphy->ipa2g_on) {
3917                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
3918                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
3919                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
3920                         } else {
3921                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3922                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3923                         }
3924                 }
3925                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
3926                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
3927                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
3928             }
3929         } else {
3930                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
3931                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3932
3933                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
3934                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3935
3936                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
3937                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3938
3939                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
3940                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3941
3942                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
3943                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
3944
3945                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3946                     B43_NPHY_BANDCTL_5GHZ)) {
3947                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
3948                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
3949                 } else {
3950                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
3951                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
3952                 }
3953
3954                 if (dev->phy.rev < 2) {
3955                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
3956                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
3957                 } else {
3958                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
3959                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
3960                 }
3961         }
3962 }
3963
3964 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3965 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3966 {
3967         struct b43_phy_n *nphy = dev->phy.n;
3968         int i;
3969         u16 scale, entry;
3970
3971         u16 tmp = nphy->txcal_bbmult;
3972         if (core == 0)
3973                 tmp >>= 8;
3974         tmp &= 0xff;
3975
3976         for (i = 0; i < 18; i++) {
3977                 scale = (ladder_lo[i].percent * tmp) / 100;
3978                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
3979                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
3980
3981                 scale = (ladder_iq[i].percent * tmp) / 100;
3982                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
3983                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
3984         }
3985 }
3986
3987 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
3988 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
3989 {
3990         int i;
3991         for (i = 0; i < 15; i++)
3992                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
3993                                 tbl_tx_filter_coef_rev4[2][i]);
3994 }
3995
3996 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
3997 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
3998 {
3999         int i, j;
4000         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
4001         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4002
4003         for (i = 0; i < 3; i++)
4004                 for (j = 0; j < 15; j++)
4005                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4006                                         tbl_tx_filter_coef_rev4[i][j]);
4007
4008         if (dev->phy.is_40mhz) {
4009                 for (j = 0; j < 15; j++)
4010                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4011                                         tbl_tx_filter_coef_rev4[3][j]);
4012         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4013                 for (j = 0; j < 15; j++)
4014                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4015                                         tbl_tx_filter_coef_rev4[5][j]);
4016         }
4017
4018         if (dev->phy.channel == 14)
4019                 for (j = 0; j < 15; j++)
4020                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4021                                         tbl_tx_filter_coef_rev4[6][j]);
4022 }
4023
4024 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4025 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4026 {
4027         struct b43_phy_n *nphy = dev->phy.n;
4028
4029         u16 curr_gain[2];
4030         struct nphy_txgains target;
4031         const u32 *table = NULL;
4032
4033         if (!nphy->txpwrctrl) {
4034                 int i;
4035
4036                 if (nphy->hang_avoid)
4037                         b43_nphy_stay_in_carrier_search(dev, true);
4038                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
4039                 if (nphy->hang_avoid)
4040                         b43_nphy_stay_in_carrier_search(dev, false);
4041
4042                 for (i = 0; i < 2; ++i) {
4043                         if (dev->phy.rev >= 3) {
4044                                 target.ipa[i] = curr_gain[i] & 0x000F;
4045                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4046                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4047                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4048                         } else {
4049                                 target.ipa[i] = curr_gain[i] & 0x0003;
4050                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4051                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4052                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4053                         }
4054                 }
4055         } else {
4056                 int i;
4057                 u16 index[2];
4058                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4059                         B43_NPHY_TXPCTL_STAT_BIDX) >>
4060                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4061                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4062                         B43_NPHY_TXPCTL_STAT_BIDX) >>
4063                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4064
4065                 for (i = 0; i < 2; ++i) {
4066                         table = b43_nphy_get_tx_gain_table(dev);
4067                         if (dev->phy.rev >= 3) {
4068                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4069                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4070                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4071                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4072                         } else {
4073                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4074                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4075                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4076                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4077                         }
4078                 }
4079         }
4080
4081         return target;
4082 }
4083
4084 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4085 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4086 {
4087         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4088
4089         if (dev->phy.rev >= 3) {
4090                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4091                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4092                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4093                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4094                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
4095                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4096                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
4097                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4098                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4099                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4100                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4101                 b43_nphy_reset_cca(dev);
4102         } else {
4103                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4104                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4105                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4106                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4107                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
4108                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4109                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4110         }
4111 }
4112
4113 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4114 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4115 {
4116         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4117         u16 tmp;
4118
4119         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4120         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4121         if (dev->phy.rev >= 3) {
4122                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4123                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4124
4125                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4126                 regs[2] = tmp;
4127                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4128
4129                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4130                 regs[3] = tmp;
4131                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4132
4133                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
4134                 b43_phy_mask(dev, B43_NPHY_BBCFG,
4135                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4136
4137                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
4138                 regs[5] = tmp;
4139                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
4140
4141                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
4142                 regs[6] = tmp;
4143                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
4144                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4145                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4146
4147                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
4148                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
4149                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
4150
4151                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4152                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4153                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4154                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4155         } else {
4156                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4157                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4158                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4159                 regs[2] = tmp;
4160                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
4161                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
4162                 regs[3] = tmp;
4163                 tmp |= 0x2000;
4164                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
4165                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
4166                 regs[4] = tmp;
4167                 tmp |= 0x2000;
4168                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
4169                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4170                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4171                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4172                         tmp = 0x0180;
4173                 else
4174                         tmp = 0x0120;
4175                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4176                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4177         }
4178 }
4179
4180 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4181 static void b43_nphy_save_cal(struct b43_wldev *dev)
4182 {
4183         struct b43_phy_n *nphy = dev->phy.n;
4184
4185         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4186         u16 *txcal_radio_regs = NULL;
4187         struct b43_chanspec *iqcal_chanspec;
4188         u16 *table = NULL;
4189
4190         if (nphy->hang_avoid)
4191                 b43_nphy_stay_in_carrier_search(dev, 1);
4192
4193         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4194                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4195                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4196                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4197                 table = nphy->cal_cache.txcal_coeffs_2G;
4198         } else {
4199                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4200                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4201                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4202                 table = nphy->cal_cache.txcal_coeffs_5G;
4203         }
4204
4205         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4206         /* TODO use some definitions */
4207         if (dev->phy.rev >= 3) {
4208                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4209                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4210                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4211                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4212                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4213                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4214                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4215                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4216         } else {
4217                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4218                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4219                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4220                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4221         }
4222         iqcal_chanspec->center_freq = dev->phy.channel_freq;
4223         iqcal_chanspec->channel_type = dev->phy.channel_type;
4224         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
4225
4226         if (nphy->hang_avoid)
4227                 b43_nphy_stay_in_carrier_search(dev, 0);
4228 }
4229
4230 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4231 static void b43_nphy_restore_cal(struct b43_wldev *dev)
4232 {
4233         struct b43_phy_n *nphy = dev->phy.n;
4234
4235         u16 coef[4];
4236         u16 *loft = NULL;
4237         u16 *table = NULL;
4238
4239         int i;
4240         u16 *txcal_radio_regs = NULL;
4241         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4242
4243         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4244                 if (!nphy->iqcal_chanspec_2G.center_freq)
4245                         return;
4246                 table = nphy->cal_cache.txcal_coeffs_2G;
4247                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4248         } else {
4249                 if (!nphy->iqcal_chanspec_5G.center_freq)
4250                         return;
4251                 table = nphy->cal_cache.txcal_coeffs_5G;
4252                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4253         }
4254
4255         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
4256
4257         for (i = 0; i < 4; i++) {
4258                 if (dev->phy.rev >= 3)
4259                         table[i] = coef[i];
4260                 else
4261                         coef[i] = 0;
4262         }
4263
4264         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4265         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4266         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
4267
4268         if (dev->phy.rev < 2)
4269                 b43_nphy_tx_iq_workaround(dev);
4270
4271         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4272                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4273                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4274         } else {
4275                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4276                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4277         }
4278
4279         /* TODO use some definitions */
4280         if (dev->phy.rev >= 3) {
4281                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4282                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4283                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4284                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4285                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4286                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4287                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4288                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4289         } else {
4290                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4291                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4292                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4293                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4294         }
4295         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4296 }
4297
4298 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4299 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4300                                 struct nphy_txgains target,
4301                                 bool full, bool mphase)
4302 {
4303         struct b43_phy_n *nphy = dev->phy.n;
4304         int i;
4305         int error = 0;
4306         int freq;
4307         bool avoid = false;
4308         u8 length;
4309         u16 tmp, core, type, count, max, numb, last = 0, cmd;
4310         const u16 *table;
4311         bool phy6or5x;
4312
4313         u16 buffer[11];
4314         u16 diq_start = 0;
4315         u16 save[2];
4316         u16 gain[2];
4317         struct nphy_iqcal_params params[2];
4318         bool updated[2] = { };
4319
4320         b43_nphy_stay_in_carrier_search(dev, true);
4321
4322         if (dev->phy.rev >= 4) {
4323                 avoid = nphy->hang_avoid;
4324                 nphy->hang_avoid = false;
4325         }
4326
4327         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4328
4329         for (i = 0; i < 2; i++) {
4330                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4331                 gain[i] = params[i].cal_gain;
4332         }
4333
4334         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
4335
4336         b43_nphy_tx_cal_radio_setup(dev);
4337         b43_nphy_tx_cal_phy_setup(dev);
4338
4339         phy6or5x = dev->phy.rev >= 6 ||
4340                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4341                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4342         if (phy6or5x) {
4343                 if (dev->phy.is_40mhz) {
4344                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4345                                         tbl_tx_iqlo_cal_loft_ladder_40);
4346                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4347                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
4348                 } else {
4349                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4350                                         tbl_tx_iqlo_cal_loft_ladder_20);
4351                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4352                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
4353                 }
4354         }
4355
4356         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4357
4358         if (!dev->phy.is_40mhz)
4359                 freq = 2500;
4360         else
4361                 freq = 5000;
4362
4363         if (nphy->mphase_cal_phase_id > 2)
4364                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4365                                         0xFFFF, 0, true, false);
4366         else
4367                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
4368
4369         if (error == 0) {
4370                 if (nphy->mphase_cal_phase_id > 2) {
4371                         table = nphy->mphase_txcal_bestcoeffs;
4372                         length = 11;
4373                         if (dev->phy.rev < 3)
4374                                 length -= 2;
4375                 } else {
4376                         if (!full && nphy->txiqlocal_coeffsvalid) {
4377                                 table = nphy->txiqlocal_bestc;
4378                                 length = 11;
4379                                 if (dev->phy.rev < 3)
4380                                         length -= 2;
4381                         } else {
4382                                 full = true;
4383                                 if (dev->phy.rev >= 3) {
4384                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4385                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4386                                 } else {
4387                                         table = tbl_tx_iqlo_cal_startcoefs;
4388                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4389                                 }
4390                         }
4391                 }
4392
4393                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
4394
4395                 if (full) {
4396                         if (dev->phy.rev >= 3)
4397                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4398                         else
4399                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4400                 } else {
4401                         if (dev->phy.rev >= 3)
4402                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4403                         else
4404                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4405                 }
4406
4407                 if (mphase) {
4408                         count = nphy->mphase_txcal_cmdidx;
4409                         numb = min(max,
4410                                 (u16)(count + nphy->mphase_txcal_numcmds));
4411                 } else {
4412                         count = 0;
4413                         numb = max;
4414                 }
4415
4416                 for (; count < numb; count++) {
4417                         if (full) {
4418                                 if (dev->phy.rev >= 3)
4419                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4420                                 else
4421                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4422                         } else {
4423                                 if (dev->phy.rev >= 3)
4424                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4425                                 else
4426                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4427                         }
4428
4429                         core = (cmd & 0x3000) >> 12;
4430                         type = (cmd & 0x0F00) >> 8;
4431
4432                         if (phy6or5x && updated[core] == 0) {
4433                                 b43_nphy_update_tx_cal_ladder(dev, core);
4434                                 updated[core] = true;
4435                         }
4436
4437                         tmp = (params[core].ncorr[type] << 8) | 0x66;
4438                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4439
4440                         if (type == 1 || type == 3 || type == 4) {
4441                                 buffer[0] = b43_ntab_read(dev,
4442                                                 B43_NTAB16(15, 69 + core));
4443                                 diq_start = buffer[0];
4444                                 buffer[0] = 0;
4445                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4446                                                 0);
4447                         }
4448
4449                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4450                         for (i = 0; i < 2000; i++) {
4451                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4452                                 if (tmp & 0xC000)
4453                                         break;
4454                                 udelay(10);
4455                         }
4456
4457                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4458                                                 buffer);
4459                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4460                                                 buffer);
4461
4462                         if (type == 1 || type == 3 || type == 4)
4463                                 buffer[0] = diq_start;
4464                 }
4465
4466                 if (mphase)
4467                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4468
4469                 last = (dev->phy.rev < 3) ? 6 : 7;
4470
4471                 if (!mphase || nphy->mphase_cal_phase_id == last) {
4472                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
4473                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
4474                         if (dev->phy.rev < 3) {
4475                                 buffer[0] = 0;
4476                                 buffer[1] = 0;
4477                                 buffer[2] = 0;
4478                                 buffer[3] = 0;
4479                         }
4480                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4481                                                 buffer);
4482                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
4483                                                 buffer);
4484                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4485                                                 buffer);
4486                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4487                                                 buffer);
4488                         length = 11;
4489                         if (dev->phy.rev < 3)
4490                                 length -= 2;
4491                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4492                                                 nphy->txiqlocal_bestc);
4493                         nphy->txiqlocal_coeffsvalid = true;
4494                         nphy->txiqlocal_chanspec.center_freq =
4495                                                         dev->phy.channel_freq;
4496                         nphy->txiqlocal_chanspec.channel_type =
4497                                                         dev->phy.channel_type;
4498                 } else {
4499                         length = 11;
4500                         if (dev->phy.rev < 3)
4501                                 length -= 2;
4502                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4503                                                 nphy->mphase_txcal_bestcoeffs);
4504                 }
4505
4506                 b43_nphy_stop_playback(dev);
4507                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4508         }
4509
4510         b43_nphy_tx_cal_phy_cleanup(dev);
4511         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4512
4513         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4514                 b43_nphy_tx_iq_workaround(dev);
4515
4516         if (dev->phy.rev >= 4)
4517                 nphy->hang_avoid = avoid;
4518
4519         b43_nphy_stay_in_carrier_search(dev, false);
4520
4521         return error;
4522 }
4523
4524 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4525 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4526 {
4527         struct b43_phy_n *nphy = dev->phy.n;
4528         u8 i;
4529         u16 buffer[7];
4530         bool equal = true;
4531
4532         if (!nphy->txiqlocal_coeffsvalid ||
4533             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4534             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
4535                 return;
4536
4537         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4538         for (i = 0; i < 4; i++) {
4539                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4540                         equal = false;
4541                         break;
4542                 }
4543         }
4544
4545         if (!equal) {
4546                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4547                                         nphy->txiqlocal_bestc);
4548                 for (i = 0; i < 4; i++)
4549                         buffer[i] = 0;
4550                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4551                                         buffer);
4552                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4553                                         &nphy->txiqlocal_bestc[5]);
4554                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4555                                         &nphy->txiqlocal_bestc[5]);
4556         }
4557 }
4558
4559 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4560 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4561                         struct nphy_txgains target, u8 type, bool debug)
4562 {
4563         struct b43_phy_n *nphy = dev->phy.n;
4564         int i, j, index;
4565         u8 rfctl[2];
4566         u8 afectl_core;
4567         u16 tmp[6];
4568         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
4569         u32 real, imag;
4570         enum ieee80211_band band;
4571
4572         u8 use;
4573         u16 cur_hpf;
4574         u16 lna[3] = { 3, 3, 1 };
4575         u16 hpf1[3] = { 7, 2, 0 };
4576         u16 hpf2[3] = { 2, 0, 0 };
4577         u32 power[3] = { };
4578         u16 gain_save[2];
4579         u16 cal_gain[2];
4580         struct nphy_iqcal_params cal_params[2];
4581         struct nphy_iq_est est;
4582         int ret = 0;
4583         bool playtone = true;
4584         int desired = 13;
4585
4586         b43_nphy_stay_in_carrier_search(dev, 1);
4587
4588         if (dev->phy.rev < 2)
4589                 b43_nphy_reapply_tx_cal_coeffs(dev);
4590         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4591         for (i = 0; i < 2; i++) {
4592                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4593                 cal_gain[i] = cal_params[i].cal_gain;
4594         }
4595         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
4596
4597         for (i = 0; i < 2; i++) {
4598                 if (i == 0) {
4599                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
4600                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
4601                         afectl_core = B43_NPHY_AFECTL_C1;
4602                 } else {
4603                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
4604                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
4605                         afectl_core = B43_NPHY_AFECTL_C2;
4606                 }
4607
4608                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4609                 tmp[2] = b43_phy_read(dev, afectl_core);
4610                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4611                 tmp[4] = b43_phy_read(dev, rfctl[0]);
4612                 tmp[5] = b43_phy_read(dev, rfctl[1]);
4613
4614                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4615                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4616                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4617                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4618                                 (1 - i));
4619                 b43_phy_set(dev, afectl_core, 0x0006);
4620                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4621
4622                 band = b43_current_band(dev->wl);
4623
4624                 if (nphy->rxcalparams & 0xFF000000) {
4625                         if (band == IEEE80211_BAND_5GHZ)
4626                                 b43_phy_write(dev, rfctl[0], 0x140);
4627                         else
4628                                 b43_phy_write(dev, rfctl[0], 0x110);
4629                 } else {
4630                         if (band == IEEE80211_BAND_5GHZ)
4631                                 b43_phy_write(dev, rfctl[0], 0x180);
4632                         else
4633                                 b43_phy_write(dev, rfctl[0], 0x120);
4634                 }
4635
4636                 if (band == IEEE80211_BAND_5GHZ)
4637                         b43_phy_write(dev, rfctl[1], 0x148);
4638                 else
4639                         b43_phy_write(dev, rfctl[1], 0x114);
4640
4641                 if (nphy->rxcalparams & 0x10000) {
4642                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4643                                         (i + 1));
4644                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4645                                         (2 - i));
4646                 }
4647
4648                 for (j = 0; j < 4; j++) {
4649                         if (j < 3) {
4650                                 cur_lna = lna[j];
4651                                 cur_hpf1 = hpf1[j];
4652                                 cur_hpf2 = hpf2[j];
4653                         } else {
4654                                 if (power[1] > 10000) {
4655                                         use = 1;
4656                                         cur_hpf = cur_hpf1;
4657                                         index = 2;
4658                                 } else {
4659                                         if (power[0] > 10000) {
4660                                                 use = 1;
4661                                                 cur_hpf = cur_hpf1;
4662                                                 index = 1;
4663                                         } else {
4664                                                 index = 0;
4665                                                 use = 2;
4666                                                 cur_hpf = cur_hpf2;
4667                                         }
4668                                 }
4669                                 cur_lna = lna[index];
4670                                 cur_hpf1 = hpf1[index];
4671                                 cur_hpf2 = hpf2[index];
4672                                 cur_hpf += desired - hweight32(power[index]);
4673                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
4674                                 if (use == 1)
4675                                         cur_hpf1 = cur_hpf;
4676                                 else
4677                                         cur_hpf2 = cur_hpf;
4678                         }
4679
4680                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4681                                         (cur_lna << 2));
4682                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
4683                                                                         false);
4684                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4685                         b43_nphy_stop_playback(dev);
4686
4687                         if (playtone) {
4688                                 ret = b43_nphy_tx_tone(dev, 4000,
4689                                                 (nphy->rxcalparams & 0xFFFF),
4690                                                 false, false);
4691                                 playtone = false;
4692                         } else {
4693                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4694                                                         false, false);
4695                         }
4696
4697                         if (ret == 0) {
4698                                 if (j < 3) {
4699                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4700                                                                         false);
4701                                         if (i == 0) {
4702                                                 real = est.i0_pwr;
4703                                                 imag = est.q0_pwr;
4704                                         } else {
4705                                                 real = est.i1_pwr;
4706                                                 imag = est.q1_pwr;
4707                                         }
4708                                         power[i] = ((real + imag) / 1024) + 1;
4709                                 } else {
4710                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4711                                 }
4712                                 b43_nphy_stop_playback(dev);
4713                         }
4714
4715                         if (ret != 0)
4716                                 break;
4717                 }
4718
4719                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4720                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4721                 b43_phy_write(dev, rfctl[1], tmp[5]);
4722                 b43_phy_write(dev, rfctl[0], tmp[4]);
4723                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4724                 b43_phy_write(dev, afectl_core, tmp[2]);
4725                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4726
4727                 if (ret != 0)
4728                         break;
4729         }
4730
4731         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
4732         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4733         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4734
4735         b43_nphy_stay_in_carrier_search(dev, 0);
4736
4737         return ret;
4738 }
4739
4740 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4741                         struct nphy_txgains target, u8 type, bool debug)
4742 {
4743         return -1;
4744 }
4745
4746 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4747 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4748                         struct nphy_txgains target, u8 type, bool debug)
4749 {
4750         if (dev->phy.rev >= 3)
4751                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4752         else
4753                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4754 }
4755
4756 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4757 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4758 {
4759         struct b43_phy *phy = &dev->phy;
4760         struct b43_phy_n *nphy = phy->n;
4761         /* u16 buf[16]; it's rev3+ */
4762
4763         nphy->phyrxchain = mask;
4764
4765         if (0 /* FIXME clk */)
4766                 return;
4767
4768         b43_mac_suspend(dev);
4769
4770         if (nphy->hang_avoid)
4771                 b43_nphy_stay_in_carrier_search(dev, true);
4772
4773         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4774                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4775
4776         if ((mask & 0x3) != 0x3) {
4777                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4778                 if (dev->phy.rev >= 3) {
4779                         /* TODO */
4780                 }
4781         } else {
4782                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4783                 if (dev->phy.rev >= 3) {
4784                         /* TODO */
4785                 }
4786         }
4787
4788         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4789
4790         if (nphy->hang_avoid)
4791                 b43_nphy_stay_in_carrier_search(dev, false);
4792
4793         b43_mac_enable(dev);
4794 }
4795
4796 /**************************************************
4797  * N-PHY init
4798  **************************************************/
4799
4800 /*
4801  * Upload the N-PHY tables.
4802  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
4803  */
4804 static void b43_nphy_tables_init(struct b43_wldev *dev)
4805 {
4806         if (dev->phy.rev < 3)
4807                 b43_nphy_rev0_1_2_tables_init(dev);
4808         else
4809                 b43_nphy_rev3plus_tables_init(dev);
4810 }
4811
4812 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4813 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4814 {
4815         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4816
4817         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4818         if (preamble == 1)
4819                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4820         else
4821                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4822
4823         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4824 }
4825
4826 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4827 static void b43_nphy_bphy_init(struct b43_wldev *dev)
4828 {
4829         unsigned int i;
4830         u16 val;
4831
4832         val = 0x1E1F;
4833         for (i = 0; i < 16; i++) {
4834                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4835                 val -= 0x202;
4836         }
4837         val = 0x3E3F;
4838         for (i = 0; i < 16; i++) {
4839                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4840                 val -= 0x202;
4841         }
4842         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4843 }
4844
4845 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4846 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4847 {
4848         if (dev->phy.rev >= 3) {
4849                 if (!init)
4850                         return;
4851                 if (0 /* FIXME */) {
4852                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4853                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4854                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4855                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4856                 }
4857         } else {
4858                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4859                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4860
4861                 switch (dev->dev->bus_type) {
4862 #ifdef CONFIG_B43_BCMA
4863                 case B43_BUS_BCMA:
4864                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4865                                                  0xFC00, 0xFC00);
4866                         break;
4867 #endif
4868 #ifdef CONFIG_B43_SSB
4869                 case B43_BUS_SSB:
4870                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4871                                                 0xFC00, 0xFC00);
4872                         break;
4873 #endif
4874                 }
4875
4876                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4877                 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4878                 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4879                               0);
4880
4881                 if (init) {
4882                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4883                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4884                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4885                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4886                 }
4887         }
4888 }
4889
4890 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
4891 static int b43_phy_initn(struct b43_wldev *dev)
4892 {
4893         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4894         struct b43_phy *phy = &dev->phy;
4895         struct b43_phy_n *nphy = phy->n;
4896         u8 tx_pwr_state;
4897         struct nphy_txgains target;
4898         u16 tmp;
4899         enum ieee80211_band tmp2;
4900         bool do_rssi_cal;
4901
4902         u16 clip[2];
4903         bool do_cal = false;
4904
4905         if ((dev->phy.rev >= 3) &&
4906            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
4907            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
4908                 switch (dev->dev->bus_type) {
4909 #ifdef CONFIG_B43_BCMA
4910                 case B43_BUS_BCMA:
4911                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4912                                       BCMA_CC_CHIPCTL, 0x40);
4913                         break;
4914 #endif
4915 #ifdef CONFIG_B43_SSB
4916                 case B43_BUS_SSB:
4917                         chipco_set32(&dev->dev->sdev->bus->chipco,
4918                                      SSB_CHIPCO_CHIPCTL, 0x40);
4919                         break;
4920 #endif
4921                 }
4922         }
4923         nphy->deaf_count = 0;
4924         b43_nphy_tables_init(dev);
4925         nphy->crsminpwr_adjusted = false;
4926         nphy->noisevars_adjusted = false;
4927
4928         /* Clear all overrides */
4929         if (dev->phy.rev >= 3) {
4930                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4931                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4932                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4933                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4934         } else {
4935                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4936         }
4937         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4938         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
4939         if (dev->phy.rev < 6) {
4940                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4941                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4942         }
4943         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4944                      ~(B43_NPHY_RFSEQMODE_CAOVER |
4945                        B43_NPHY_RFSEQMODE_TROVER));
4946         if (dev->phy.rev >= 3)
4947                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
4948         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4949
4950         if (dev->phy.rev <= 2) {
4951                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
4952                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
4953                                 ~B43_NPHY_BPHY_CTL3_SCALE,
4954                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
4955         }
4956         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
4957         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
4958
4959         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
4960             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4961              dev->dev->board_type == 0x8B))
4962                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
4963         else
4964                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
4965         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
4966         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
4967         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
4968
4969         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4970         b43_nphy_update_txrx_chain(dev);
4971
4972         if (phy->rev < 2) {
4973                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
4974                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
4975         }
4976
4977         tmp2 = b43_current_band(dev->wl);
4978         if (b43_nphy_ipa(dev)) {
4979                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
4980                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
4981                                 nphy->papd_epsilon_offset[0] << 7);
4982                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
4983                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
4984                                 nphy->papd_epsilon_offset[1] << 7);
4985                 b43_nphy_int_pa_set_tx_dig_filters(dev);
4986         } else if (phy->rev >= 5) {
4987                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
4988         }
4989
4990         b43_nphy_workarounds(dev);
4991
4992         /* Reset CCA, in init code it differs a little from standard way */
4993         b43_phy_force_clock(dev, 1);
4994         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
4995         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
4996         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
4997         b43_phy_force_clock(dev, 0);
4998
4999         b43_mac_phy_clock_set(dev, true);
5000
5001         b43_nphy_pa_override(dev, false);
5002         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5003         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5004         b43_nphy_pa_override(dev, true);
5005
5006         b43_nphy_classifier(dev, 0, 0);
5007         b43_nphy_read_clip_detection(dev, clip);
5008         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5009                 b43_nphy_bphy_init(dev);
5010
5011         tx_pwr_state = nphy->txpwrctrl;
5012         b43_nphy_tx_power_ctrl(dev, false);
5013         b43_nphy_tx_power_fix(dev);
5014         b43_nphy_tx_power_ctl_idle_tssi(dev);
5015         b43_nphy_tx_power_ctl_setup(dev);
5016         b43_nphy_tx_gain_table_upload(dev);
5017
5018         if (nphy->phyrxchain != 3)
5019                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
5020         if (nphy->mphase_cal_phase_id > 0)
5021                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5022
5023         do_rssi_cal = false;
5024         if (phy->rev >= 3) {
5025                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5026                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
5027                 else
5028                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
5029
5030                 if (do_rssi_cal)
5031                         b43_nphy_rssi_cal(dev);
5032                 else
5033                         b43_nphy_restore_rssi_cal(dev);
5034         } else {
5035                 b43_nphy_rssi_cal(dev);
5036         }
5037
5038         if (!((nphy->measure_hold & 0x6) != 0)) {
5039                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5040                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
5041                 else
5042                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
5043
5044                 if (nphy->mute)
5045                         do_cal = false;
5046
5047                 if (do_cal) {
5048                         target = b43_nphy_get_tx_gains(dev);
5049
5050                         if (nphy->antsel_type == 2)
5051                                 b43_nphy_superswitch_init(dev, true);
5052                         if (nphy->perical != 2) {
5053                                 b43_nphy_rssi_cal(dev);
5054                                 if (phy->rev >= 3) {
5055                                         nphy->cal_orig_pwr_idx[0] =
5056                                             nphy->txpwrindex[0].index_internal;
5057                                         nphy->cal_orig_pwr_idx[1] =
5058                                             nphy->txpwrindex[1].index_internal;
5059                                         /* TODO N PHY Pre Calibrate TX Gain */
5060                                         target = b43_nphy_get_tx_gains(dev);
5061                                 }
5062                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5063                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5064                                                 b43_nphy_save_cal(dev);
5065                         } else if (nphy->mphase_cal_phase_id == 0)
5066                                 ;/* N PHY Periodic Calibration with arg 3 */
5067                 } else {
5068                         b43_nphy_restore_cal(dev);
5069                 }
5070         }
5071
5072         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
5073         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
5074         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5075         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5076         if (phy->rev >= 3 && phy->rev <= 6)
5077                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
5078         b43_nphy_tx_lp_fbw(dev);
5079         if (phy->rev >= 3)
5080                 b43_nphy_spur_workaround(dev);
5081
5082         return 0;
5083 }
5084
5085 /**************************************************
5086  * Channel switching ops.
5087  **************************************************/
5088
5089 static void b43_chantab_phy_upload(struct b43_wldev *dev,
5090                                    const struct b43_phy_n_sfo_cfg *e)
5091 {
5092         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5093         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5094         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5095         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5096         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5097         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5098 }
5099
5100 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5101 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5102 {
5103         struct bcma_drv_cc __maybe_unused *cc;
5104         u32 __maybe_unused pmu_ctl;
5105
5106         switch (dev->dev->bus_type) {
5107 #ifdef CONFIG_B43_BCMA
5108         case B43_BUS_BCMA:
5109                 cc = &dev->dev->bdev->bus->drv_cc;
5110                 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
5111                         if (avoid) {
5112                                 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
5113                                 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
5114                                 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
5115                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5116                                 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
5117                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5118                         } else {
5119                                 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
5120                                 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
5121                                 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
5122                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5123                                 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
5124                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5125                         }
5126                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
5127                 } else if (dev->dev->chip_id == 0x4716) {
5128                         if (avoid) {
5129                                 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
5130                                 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
5131                                 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
5132                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5133                                 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
5134                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5135                         } else {
5136                                 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
5137                                 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
5138                                 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
5139                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5140                                 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
5141                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5142                         }
5143                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
5144                                   BCMA_CC_PMU_CTL_NOILPONW;
5145                 } else if (dev->dev->chip_id == 0x4322 ||
5146                            dev->dev->chip_id == 0x4340 ||
5147                            dev->dev->chip_id == 0x4341) {
5148                         bcma_chipco_pll_write(cc, 0x0, 0x11100070);
5149                         bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
5150                         bcma_chipco_pll_write(cc, 0x5, 0x88888854);
5151                         if (avoid)
5152                                 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
5153                         else
5154                                 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
5155                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
5156                 } else {
5157                         return;
5158                 }
5159                 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
5160                 break;
5161 #endif
5162 #ifdef CONFIG_B43_SSB
5163         case B43_BUS_SSB:
5164                 /* FIXME */
5165                 break;
5166 #endif
5167         }
5168 }
5169
5170 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
5171 static void b43_nphy_channel_setup(struct b43_wldev *dev,
5172                                 const struct b43_phy_n_sfo_cfg *e,
5173                                 struct ieee80211_channel *new_channel)
5174 {
5175         struct b43_phy *phy = &dev->phy;
5176         struct b43_phy_n *nphy = dev->phy.n;
5177         int ch = new_channel->hw_value;
5178
5179         u16 old_band_5ghz;
5180         u32 tmp32;
5181
5182         old_band_5ghz =
5183                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5184         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
5185                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5186                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5187                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5188                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5189                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
5190         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
5191                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5192                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5193                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5194                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
5195                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5196         }
5197
5198         b43_chantab_phy_upload(dev, e);
5199
5200         if (new_channel->hw_value == 14) {
5201                 b43_nphy_classifier(dev, 2, 0);
5202                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5203         } else {
5204                 b43_nphy_classifier(dev, 2, 2);
5205                 if (new_channel->band == IEEE80211_BAND_2GHZ)
5206                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5207         }
5208
5209         if (!nphy->txpwrctrl)
5210                 b43_nphy_tx_power_fix(dev);
5211
5212         if (dev->phy.rev < 3)
5213                 b43_nphy_adjust_lna_gain_table(dev);
5214
5215         b43_nphy_tx_lp_fbw(dev);
5216
5217         if (dev->phy.rev >= 3 &&
5218             dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5219                 bool avoid = false;
5220                 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5221                         avoid = true;
5222                 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5223                         if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5224                                 avoid = true;
5225                 } else { /* 40MHz */
5226                         if (nphy->aband_spurwar_en &&
5227                             (ch == 38 || ch == 102 || ch == 118))
5228                                 avoid = dev->dev->chip_id == 0x4716;
5229                 }
5230
5231                 b43_nphy_pmu_spur_avoid(dev, avoid);
5232
5233                 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5234                     dev->dev->chip_id == 43225) {
5235                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5236                                     avoid ? 0x5341 : 0x8889);
5237                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5238                 }
5239
5240                 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5241                         ; /* TODO: reset PLL */
5242
5243                 if (avoid)
5244                         b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5245                 else
5246                         b43_phy_mask(dev, B43_NPHY_BBCFG,
5247                                      ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5248
5249                 b43_nphy_reset_cca(dev);
5250
5251                 /* wl sets useless phy_isspuravoid here */
5252         }
5253
5254         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5255
5256         if (phy->rev >= 3)
5257                 b43_nphy_spur_workaround(dev);
5258 }
5259
5260 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
5261 static int b43_nphy_set_channel(struct b43_wldev *dev,
5262                                 struct ieee80211_channel *channel,
5263                                 enum nl80211_channel_type channel_type)
5264 {
5265         struct b43_phy *phy = &dev->phy;
5266
5267         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5268         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
5269
5270         u8 tmp;
5271
5272         if (dev->phy.rev >= 3) {
5273                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5274                                                         channel->center_freq);
5275                 if (!tabent_r3)
5276                         return -ESRCH;
5277         } else {
5278                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5279                                                         channel->hw_value);
5280                 if (!tabent_r2)
5281                         return -ESRCH;
5282         }
5283
5284         /* Channel is set later in common code, but we need to set it on our
5285            own to let this function's subcalls work properly. */
5286         phy->channel = channel->hw_value;
5287         phy->channel_freq = channel->center_freq;
5288
5289         if (b43_channel_type_is_40mhz(phy->channel_type) !=
5290                 b43_channel_type_is_40mhz(channel_type))
5291                 ; /* TODO: BMAC BW Set (channel_type) */
5292
5293         if (channel_type == NL80211_CHAN_HT40PLUS)
5294                 b43_phy_set(dev, B43_NPHY_RXCTL,
5295                                 B43_NPHY_RXCTL_BSELU20);
5296         else if (channel_type == NL80211_CHAN_HT40MINUS)
5297                 b43_phy_mask(dev, B43_NPHY_RXCTL,
5298                                 ~B43_NPHY_RXCTL_BSELU20);
5299
5300         if (dev->phy.rev >= 3) {
5301                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
5302                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
5303                 b43_radio_2056_setup(dev, tabent_r3);
5304                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
5305         } else {
5306                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
5307                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
5308                 b43_radio_2055_setup(dev, tabent_r2);
5309                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
5310         }
5311
5312         return 0;
5313 }
5314
5315 /**************************************************
5316  * Basic PHY ops.
5317  **************************************************/
5318
5319 static int b43_nphy_op_allocate(struct b43_wldev *dev)
5320 {
5321         struct b43_phy_n *nphy;
5322
5323         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5324         if (!nphy)
5325                 return -ENOMEM;
5326         dev->phy.n = nphy;
5327
5328         return 0;
5329 }
5330
5331 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
5332 {
5333         struct b43_phy *phy = &dev->phy;
5334         struct b43_phy_n *nphy = phy->n;
5335         struct ssb_sprom *sprom = dev->dev->bus_sprom;
5336
5337         memset(nphy, 0, sizeof(*nphy));
5338
5339         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
5340         nphy->spur_avoid = (phy->rev >= 3) ?
5341                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
5342         nphy->init_por = true;
5343         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5344         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5345         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
5346         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
5347         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5348          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5349         nphy->tx_pwr_idx[0] = 128;
5350         nphy->tx_pwr_idx[1] = 128;
5351
5352         /* Hardware TX power control and 5GHz power gain */
5353         nphy->txpwrctrl = false;
5354         nphy->pwg_gain_5ghz = false;
5355         if (dev->phy.rev >= 3 ||
5356             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5357              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5358                 nphy->txpwrctrl = true;
5359                 nphy->pwg_gain_5ghz = true;
5360         } else if (sprom->revision >= 4) {
5361                 if (dev->phy.rev >= 2 &&
5362                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5363                         nphy->txpwrctrl = true;
5364 #ifdef CONFIG_B43_SSB
5365                         if (dev->dev->bus_type == B43_BUS_SSB &&
5366                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5367                                 struct pci_dev *pdev =
5368                                         dev->dev->sdev->bus->host_pci;
5369                                 if (pdev->device == 0x4328 ||
5370                                     pdev->device == 0x432a)
5371                                         nphy->pwg_gain_5ghz = true;
5372                         }
5373 #endif
5374                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5375                         nphy->pwg_gain_5ghz = true;
5376                 }
5377         }
5378
5379         if (dev->phy.rev >= 3) {
5380                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5381                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5382         }
5383
5384         nphy->init_por = true;
5385 }
5386
5387 static void b43_nphy_op_free(struct b43_wldev *dev)
5388 {
5389         struct b43_phy *phy = &dev->phy;
5390         struct b43_phy_n *nphy = phy->n;
5391
5392         kfree(nphy);
5393         phy->n = NULL;
5394 }
5395
5396 static int b43_nphy_op_init(struct b43_wldev *dev)
5397 {
5398         return b43_phy_initn(dev);
5399 }
5400
5401 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5402 {
5403 #if B43_DEBUG
5404         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5405                 /* OFDM registers are onnly available on A/G-PHYs */
5406                 b43err(dev->wl, "Invalid OFDM PHY access at "
5407                        "0x%04X on N-PHY\n", offset);
5408                 dump_stack();
5409         }
5410         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5411                 /* Ext-G registers are only available on G-PHYs */
5412                 b43err(dev->wl, "Invalid EXT-G PHY access at "
5413                        "0x%04X on N-PHY\n", offset);
5414                 dump_stack();
5415         }
5416 #endif /* B43_DEBUG */
5417 }
5418
5419 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5420 {
5421         check_phyreg(dev, reg);
5422         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5423         return b43_read16(dev, B43_MMIO_PHY_DATA);
5424 }
5425
5426 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5427 {
5428         check_phyreg(dev, reg);
5429         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5430         b43_write16(dev, B43_MMIO_PHY_DATA, value);
5431 }
5432
5433 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5434                                  u16 set)
5435 {
5436         check_phyreg(dev, reg);
5437         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5438         b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
5439 }
5440
5441 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5442 {
5443         /* Register 1 is a 32-bit register. */
5444         B43_WARN_ON(reg == 1);
5445         /* N-PHY needs 0x100 for read access */
5446         reg |= 0x100;
5447
5448         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5449         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5450 }
5451
5452 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5453 {
5454         /* Register 1 is a 32-bit register. */
5455         B43_WARN_ON(reg == 1);
5456
5457         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5458         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5459 }
5460
5461 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
5462 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
5463                                         bool blocked)
5464 {
5465         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5466                 b43err(dev->wl, "MAC not suspended\n");
5467
5468         if (blocked) {
5469                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5470                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
5471                 if (dev->phy.rev >= 7) {
5472                         /* TODO */
5473                 } else if (dev->phy.rev >= 3) {
5474                         b43_radio_mask(dev, 0x09, ~0x2);
5475
5476                         b43_radio_write(dev, 0x204D, 0);
5477                         b43_radio_write(dev, 0x2053, 0);
5478                         b43_radio_write(dev, 0x2058, 0);
5479                         b43_radio_write(dev, 0x205E, 0);
5480                         b43_radio_mask(dev, 0x2062, ~0xF0);
5481                         b43_radio_write(dev, 0x2064, 0);
5482
5483                         b43_radio_write(dev, 0x304D, 0);
5484                         b43_radio_write(dev, 0x3053, 0);
5485                         b43_radio_write(dev, 0x3058, 0);
5486                         b43_radio_write(dev, 0x305E, 0);
5487                         b43_radio_mask(dev, 0x3062, ~0xF0);
5488                         b43_radio_write(dev, 0x3064, 0);
5489                 }
5490         } else {
5491                 if (dev->phy.rev >= 7) {
5492                         b43_radio_2057_init(dev);
5493                         b43_switch_channel(dev, dev->phy.channel);
5494                 } else if (dev->phy.rev >= 3) {
5495                         b43_radio_init2056(dev);
5496                         b43_switch_channel(dev, dev->phy.channel);
5497                 } else {
5498                         b43_radio_init2055(dev);
5499                 }
5500         }
5501 }
5502
5503 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
5504 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5505 {
5506         u16 override = on ? 0x0 : 0x7FFF;
5507         u16 core = on ? 0xD : 0x00FD;
5508
5509         if (dev->phy.rev >= 3) {
5510                 if (on) {
5511                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5512                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5513                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5514                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5515                 } else {
5516                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5517                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5518                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5519                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5520                 }
5521         } else {
5522                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5523         }
5524 }
5525
5526 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5527                                       unsigned int new_channel)
5528 {
5529         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
5530         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
5531
5532         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5533                 if ((new_channel < 1) || (new_channel > 14))
5534                         return -EINVAL;
5535         } else {
5536                 if (new_channel > 200)
5537                         return -EINVAL;
5538         }
5539
5540         return b43_nphy_set_channel(dev, channel, channel_type);
5541 }
5542
5543 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5544 {
5545         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5546                 return 1;
5547         return 36;
5548 }
5549
5550 const struct b43_phy_operations b43_phyops_n = {
5551         .allocate               = b43_nphy_op_allocate,
5552         .free                   = b43_nphy_op_free,
5553         .prepare_structs        = b43_nphy_op_prepare_structs,
5554         .init                   = b43_nphy_op_init,
5555         .phy_read               = b43_nphy_op_read,
5556         .phy_write              = b43_nphy_op_write,
5557         .phy_maskset            = b43_nphy_op_maskset,
5558         .radio_read             = b43_nphy_op_radio_read,
5559         .radio_write            = b43_nphy_op_radio_write,
5560         .software_rfkill        = b43_nphy_op_software_rfkill,
5561         .switch_analog          = b43_nphy_op_switch_analog,
5562         .switch_channel         = b43_nphy_op_switch_channel,
5563         .get_default_chan       = b43_nphy_op_get_default_chan,
5564         .recalc_txpower         = b43_nphy_op_recalc_txpower,
5565         .adjust_txpower         = b43_nphy_op_adjust_txpower,
5566 };