drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/types.h>
  28
  29 #include "b43.h"
  30 #include "phy_n.h"
  31 #include "tables_nphy.h"
  32 #include "main.h"
  33
  34 struct nphy_txgains {
  35         u16 txgm[2];
  36         u16 pga[2];
  37         u16 pad[2];
  38         u16 ipa[2];
  39 };
  40
  41 struct nphy_iqcal_params {
  42         u16 txgm;
  43         u16 pga;
  44         u16 pad;
  45         u16 ipa;
  46         u16 cal_gain;
  47         u16 ncorr[5];
  48 };
  49
  50 struct nphy_iq_est {
  51         s32 iq0_prod;
  52         u32 i0_pwr;
  53         u32 q0_pwr;
  54         s32 iq1_prod;
  55         u32 i1_pwr;
  56         u32 q1_pwr;
  57 };
  58
  59 enum b43_nphy_rf_sequence {
  60         B43_RFSEQ_RX2TX,
  61         B43_RFSEQ_TX2RX,
  62         B43_RFSEQ_RESET2RX,
  63         B43_RFSEQ_UPDATE_GAINH,
  64         B43_RFSEQ_UPDATE_GAINL,
  65         B43_RFSEQ_UPDATE_GAINU,
  66 };
  67
  68 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  69                                         u8 *events, u8 *delays, u8 length);
  70 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  71                                        enum b43_nphy_rf_sequence seq);
  72 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  73                                                 u16 value, u8 core, bool off);
  74 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  75                                                 u16 value, u8 core);
  76
  77 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  78 {//TODO
  79 }
  80
  81 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  82 {//TODO
  83 }
  84
  85 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  86                                                         bool ignore_tssi)
  87 {//TODO
  88         return B43_TXPWR_RES_DONE;
  89 }
  90
  91 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  92                                      const struct b43_nphy_channeltab_entry *e)
  93 {
  94         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  95         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  96         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  97         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  98         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  99         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 100         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 101         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 102         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 103         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 104         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 105         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 106         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 107         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 108         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 109         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 110         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 111         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 112         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 113         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 114         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 115         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 116 }
 117
 118 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 119                                    const struct b43_nphy_channeltab_entry *e)
 120 {
 121         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 122         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 123         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 124         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 125         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 126         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 127 }
 128
 129 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 130 {
 131         //TODO
 132 }
 133
 134 /* Tune the hardware to a new channel. */
 135 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 136 {
 137         const struct b43_nphy_channeltab_entry *tabent;
 138
 139         tabent = b43_nphy_get_chantabent(dev, channel);
 140         if (!tabent)
 141                 return -ESRCH;
 142
 143         //FIXME enable/disable band select upper20 in RXCTL
 144         if (0 /*FIXME 5Ghz*/)
 145                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 146         else
 147                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 148         b43_chantab_radio_upload(dev, tabent);
 149         udelay(50);
 150         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 151         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 152         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 153         udelay(300);
 154         if (0 /*FIXME 5Ghz*/)
 155                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 156         else
 157                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 158         b43_chantab_phy_upload(dev, tabent);
 159         b43_nphy_tx_power_fix(dev);
 160
 161         return 0;
 162 }
 163
 164 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 165 {
 166         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 167                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 168         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 169                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 170                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 171         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 172                     B43_NPHY_RFCTL_CMD_PORFORCE);
 173 }
 174
 175 static void b43_radio_init2055_post(struct b43_wldev *dev)
 176 {
 177         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 178         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 179         int i;
 180         u16 val;
 181
 182         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 183         msleep(1);
 184         if ((sprom->revision != 4) ||
 185            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 186                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 187                     (binfo->type != 0x46D) ||
 188                     (binfo->rev < 0x41)) {
 189                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 190                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 191                         msleep(1);
 192                 }
 193         }
 194         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 195         msleep(1);
 196         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 197         msleep(1);
 198         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 199         msleep(1);
 200         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 201         msleep(1);
 202         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 203         msleep(1);
 204         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 205         msleep(1);
 206         for (i = 0; i < 100; i++) {
 207                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 208                 if (val & 0x80)
 209                         break;
 210                 udelay(10);
 211         }
 212         msleep(1);
 213         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 214         msleep(1);
 215         nphy_channel_switch(dev, dev->phy.channel);
 216         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 217         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 218         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 219         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 220 }
 221
 222 /* Initialize a Broadcom 2055 N-radio */
 223 static void b43_radio_init2055(struct b43_wldev *dev)
 224 {
 225         b43_radio_init2055_pre(dev);
 226         if (b43_status(dev) < B43_STAT_INITIALIZED)
 227                 b2055_upload_inittab(dev, 0, 1);
 228         else
 229                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 230         b43_radio_init2055_post(dev);
 231 }
 232
 233 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 234 {
 235         b43_radio_init2055(dev);
 236 }
 237
 238 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 239 {
 240         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 241                      ~B43_NPHY_RFCTL_CMD_EN);
 242 }
 243
 244 /*
 245  * Upload the N-PHY tables.
 246  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 247  */
 248 static void b43_nphy_tables_init(struct b43_wldev *dev)
 249 {
 250         if (dev->phy.rev < 3)
 251                 b43_nphy_rev0_1_2_tables_init(dev);
 252         else
 253                 b43_nphy_rev3plus_tables_init(dev);
 254 }
 255
 256 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 257 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 258 {
 259         struct b43_phy_n *nphy = dev->phy.n;
 260         enum ieee80211_band band;
 261         u16 tmp;
 262
 263         if (!enable) {
 264                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 265                                                        B43_NPHY_RFCTL_INTC1);
 266                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 267                                                        B43_NPHY_RFCTL_INTC2);
 268                 band = b43_current_band(dev->wl);
 269                 if (dev->phy.rev >= 3) {
 270                         if (band == IEEE80211_BAND_5GHZ)
 271                                 tmp = 0x600;
 272                         else
 273                                 tmp = 0x480;
 274                 } else {
 275                         if (band == IEEE80211_BAND_5GHZ)
 276                                 tmp = 0x180;
 277                         else
 278                                 tmp = 0x120;
 279                 }
 280                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 281                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 282         } else {
 283                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 284                                 nphy->rfctrl_intc1_save);
 285                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 286                                 nphy->rfctrl_intc2_save);
 287         }
 288 }
 289
 290 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 291 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 292 {
 293         struct b43_phy_n *nphy = dev->phy.n;
 294         u16 tmp;
 295         enum ieee80211_band band = b43_current_band(dev->wl);
 296         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 297                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 298
 299         if (dev->phy.rev >= 3) {
 300                 if (ipa) {
 301                         tmp = 4;
 302                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 303                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 304                 }
 305
 306                 tmp = 1;
 307                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 308                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 309         }
 310 }
 311
 312 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 313 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 314 {
 315         u32 tmslow;
 316
 317         if (dev->phy.type != B43_PHYTYPE_N)
 318                 return;
 319
 320         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 321         if (force)
 322                 tmslow |= SSB_TMSLOW_FGC;
 323         else
 324                 tmslow &= ~SSB_TMSLOW_FGC;
 325         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 326 }
 327
 328 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 329 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 330 {
 331         u16 bbcfg;
 332
 333         b43_nphy_bmac_clock_fgc(dev, 1);
 334         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 335         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 336         udelay(1);
 337         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 338         b43_nphy_bmac_clock_fgc(dev, 0);
 339         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 340 }
 341
 342 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 343 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 344 {
 345         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 346
 347         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 348         if (preamble == 1)
 349                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 350         else
 351                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 352
 353         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 354 }
 355
 356 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 357 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 358 {
 359         struct b43_phy_n *nphy = dev->phy.n;
 360
 361         bool override = false;
 362         u16 chain = 0x33;
 363
 364         if (nphy->txrx_chain == 0) {
 365                 chain = 0x11;
 366                 override = true;
 367         } else if (nphy->txrx_chain == 1) {
 368                 chain = 0x22;
 369                 override = true;
 370         }
 371
 372         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 373                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 374                         chain);
 375
 376         if (override)
 377                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 378                                 B43_NPHY_RFSEQMODE_CAOVER);
 379         else
 380                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 381                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 382 }
 383
 384 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 385 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 386                                 u16 samps, u8 time, bool wait)
 387 {
 388         int i;
 389         u16 tmp;
 390
 391         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 392         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 393         if (wait)
 394                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 395         else
 396                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 397
 398         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 399
 400         for (i = 1000; i; i--) {
 401                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 402                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 403                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 404                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 405                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 406                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 407                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 408                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 409
 410                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 411                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 412                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 413                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 414                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 415                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 416                         return;
 417                 }
 418                 udelay(10);
 419         }
 420         memset(est, 0, sizeof(*est));
 421 }
 422
 423 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 424 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 425                                         struct b43_phy_n_iq_comp *pcomp)
 426 {
 427         if (write) {
 428                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 429                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 430                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 431                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 432         } else {
 433                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 434                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 435                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 436                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 437         }
 438 }
 439
 440 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 441 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 442 {
 443         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 444
 445         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 446         if (core == 0) {
 447                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 448                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 449         } else {
 450                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 451                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 452         }
 453         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 454         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 455         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 456         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 457         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 458         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 459         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 460         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 461 }
 462
 463 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 464 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 465 {
 466         u8 rxval, txval;
 467         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 468
 469         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 470         if (core == 0) {
 471                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 472                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 473         } else {
 474                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 475                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 476         }
 477         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 478         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 479         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 480         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 481         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 482         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 483         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 484         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 485
 486         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 487         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 488
 489         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 490                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 491         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 492                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 493         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 494                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 495         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 496                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 497
 498         if (core == 0) {
 499                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 500                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 501         } else {
 502                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 503                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 504         }
 505
 506         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 507         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 508         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 509
 510         if (core == 0) {
 511                 rxval = 1;
 512                 txval = 8;
 513         } else {
 514                 rxval = 4;
 515                 txval = 2;
 516         }
 517         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 518         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 519 }
 520
 521 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 522 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 523 {
 524         int i;
 525         s32 iq;
 526         u32 ii;
 527         u32 qq;
 528         int iq_nbits, qq_nbits;
 529         int arsh, brsh;
 530         u16 tmp, a, b;
 531
 532         struct nphy_iq_est est;
 533         struct b43_phy_n_iq_comp old;
 534         struct b43_phy_n_iq_comp new = { };
 535         bool error = false;
 536
 537         if (mask == 0)
 538                 return;
 539
 540         b43_nphy_rx_iq_coeffs(dev, false, &old);
 541         b43_nphy_rx_iq_coeffs(dev, true, &new);
 542         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 543         new = old;
 544
 545         for (i = 0; i < 2; i++) {
 546                 if (i == 0 && (mask & 1)) {
 547                         iq = est.iq0_prod;
 548                         ii = est.i0_pwr;
 549                         qq = est.q0_pwr;
 550                 } else if (i == 1 && (mask & 2)) {
 551                         iq = est.iq1_prod;
 552                         ii = est.i1_pwr;
 553                         qq = est.q1_pwr;
 554                 } else {
 555                         B43_WARN_ON(1);
 556                         continue;
 557                 }
 558
 559                 if (ii + qq < 2) {
 560                         error = true;
 561                         break;
 562                 }
 563
 564                 iq_nbits = fls(abs(iq));
 565                 qq_nbits = fls(qq);
 566
 567                 arsh = iq_nbits - 20;
 568                 if (arsh >= 0) {
 569                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 570                         tmp = ii >> arsh;
 571                 } else {
 572                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 573                         tmp = ii << -arsh;
 574                 }
 575                 if (tmp == 0) {
 576                         error = true;
 577                         break;
 578                 }
 579                 a /= tmp;
 580
 581                 brsh = qq_nbits - 11;
 582                 if (brsh >= 0) {
 583                         b = (qq << (31 - qq_nbits));
 584                         tmp = ii >> brsh;
 585                 } else {
 586                         b = (qq << (31 - qq_nbits));
 587                         tmp = ii << -brsh;
 588                 }
 589                 if (tmp == 0) {
 590                         error = true;
 591                         break;
 592                 }
 593                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 594
 595                 if (i == 0 && (mask & 0x1)) {
 596                         if (dev->phy.rev >= 3) {
 597                                 new.a0 = a & 0x3FF;
 598                                 new.b0 = b & 0x3FF;
 599                         } else {
 600                                 new.a0 = b & 0x3FF;
 601                                 new.b0 = a & 0x3FF;
 602                         }
 603                 } else if (i == 1 && (mask & 0x2)) {
 604                         if (dev->phy.rev >= 3) {
 605                                 new.a1 = a & 0x3FF;
 606                                 new.b1 = b & 0x3FF;
 607                         } else {
 608                                 new.a1 = b & 0x3FF;
 609                                 new.b1 = a & 0x3FF;
 610                         }
 611                 }
 612         }
 613
 614         if (error)
 615                 new = old;
 616
 617         b43_nphy_rx_iq_coeffs(dev, true, &new);
 618 }
 619
 620 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 621 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 622 {
 623         u16 array[4];
 624         int i;
 625
 626         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 627         for (i = 0; i < 4; i++)
 628                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 629
 630         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 631         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 632         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 633         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 634 }
 635
 636 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 637 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 638 {
 639         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 640         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 641 }
 642
 643 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 644 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 645 {
 646         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 647         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 648 }
 649
 650 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 651 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 652 {
 653         u16 tmp;
 654
 655         if (dev->dev->id.revision == 16)
 656                 b43_mac_suspend(dev);
 657
 658         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 659         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 660                 B43_NPHY_CLASSCTL_WAITEDEN);
 661         tmp &= ~mask;
 662         tmp |= (val & mask);
 663         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 664
 665         if (dev->dev->id.revision == 16)
 666                 b43_mac_enable(dev);
 667
 668         return tmp;
 669 }
 670
 671 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 672 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 673 {
 674         struct b43_phy *phy = &dev->phy;
 675         struct b43_phy_n *nphy = phy->n;
 676
 677         if (enable) {
 678                 u16 clip[] = { 0xFFFF, 0xFFFF };
 679                 if (nphy->deaf_count++ == 0) {
 680                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 681                         b43_nphy_classifier(dev, 0x7, 0);
 682                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 683                         b43_nphy_write_clip_detection(dev, clip);
 684                 }
 685                 b43_nphy_reset_cca(dev);
 686         } else {
 687                 if (--nphy->deaf_count == 0) {
 688                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 689                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 690                 }
 691         }
 692 }
 693
 694 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 695 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 696 {
 697         struct b43_phy_n *nphy = dev->phy.n;
 698         u16 tmp;
 699
 700         if (nphy->hang_avoid)
 701                 b43_nphy_stay_in_carrier_search(dev, 1);
 702
 703         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 704         if (tmp & 0x1)
 705                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 706         else if (tmp & 0x2)
 707                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 708
 709         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 710
 711         if (nphy->bb_mult_save & 0x80000000) {
 712                 tmp = nphy->bb_mult_save & 0xFFFF;
 713                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 714                 nphy->bb_mult_save = 0;
 715         }
 716
 717         if (nphy->hang_avoid)
 718                 b43_nphy_stay_in_carrier_search(dev, 0);
 719 }
 720
 721 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 722 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 723 {
 724         struct b43_phy_n *nphy = dev->phy.n;
 725
 726         unsigned int channel;
 727         int tone[2] = { 57, 58 };
 728         u32 noise[2] = { 0x3FF, 0x3FF };
 729
 730         B43_WARN_ON(dev->phy.rev < 3);
 731
 732         if (nphy->hang_avoid)
 733                 b43_nphy_stay_in_carrier_search(dev, 1);
 734
 735         /* FIXME: channel = radio_chanspec */
 736
 737         if (nphy->gband_spurwar_en) {
 738                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 739                 if (channel == 11 && dev->phy.is_40mhz)
 740                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 741                 else
 742                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 743                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 744         }
 745
 746         if (nphy->aband_spurwar_en) {
 747                 if (channel == 54) {
 748                         tone[0] = 0x20;
 749                         noise[0] = 0x25F;
 750                 } else if (channel == 38 || channel == 102 || channel == 118) {
 751                         if (0 /* FIXME */) {
 752                                 tone[0] = 0x20;
 753                                 noise[0] = 0x21F;
 754                         } else {
 755                                 tone[0] = 0;
 756                                 noise[0] = 0;
 757                         }
 758                 } else if (channel == 134) {
 759                         tone[0] = 0x20;
 760                         noise[0] = 0x21F;
 761                 } else if (channel == 151) {
 762                         tone[0] = 0x10;
 763                         noise[0] = 0x23F;
 764                 } else if (channel == 153 || channel == 161) {
 765                         tone[0] = 0x30;
 766                         noise[0] = 0x23F;
 767                 } else {
 768                         tone[0] = 0;
 769                         noise[0] = 0;
 770                 }
 771
 772                 if (!tone[0] && !noise[0])
 773                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 774                 else
 775                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 776         }
 777
 778         if (nphy->hang_avoid)
 779                 b43_nphy_stay_in_carrier_search(dev, 0);
 780 }
 781
 782 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 783 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
 784 {
 785         struct b43_phy_n *nphy = dev->phy.n;
 786         u8 i, j;
 787         u8 code;
 788
 789         /* TODO: for PHY >= 3
 790         s8 *lna1_gain, *lna2_gain;
 791         u8 *gain_db, *gain_bits;
 792         u16 *rfseq_init;
 793         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 794         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 795         */
 796
 797         u8 rfseq_events[3] = { 6, 8, 7 };
 798         u8 rfseq_delays[3] = { 10, 30, 1 };
 799
 800         if (dev->phy.rev >= 3) {
 801                 /* TODO */
 802         } else {
 803                 /* Set Clip 2 detect */
 804                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 805                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 806                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 807                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 808
 809                 /* Set narrowband clip threshold */
 810                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 811                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 812
 813                 if (!dev->phy.is_40mhz) {
 814                         /* Set dwell lengths */
 815                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 816                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 817                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 818                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 819                 }
 820
 821                 /* Set wideband clip 2 threshold */
 822                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 823                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 824                                 21);
 825                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 826                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 827                                 21);
 828
 829                 if (!dev->phy.is_40mhz) {
 830                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 831                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 832                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 833                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 834                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 835                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 836                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 837                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 838                 }
 839
 840                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 841
 842                 if (nphy->gain_boost) {
 843                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 844                             dev->phy.is_40mhz)
 845                                 code = 4;
 846                         else
 847                                 code = 5;
 848                 } else {
 849                         code = dev->phy.is_40mhz ? 6 : 7;
 850                 }
 851
 852                 /* Set HPVGA2 index */
 853                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 854                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 855                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 856                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 857                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 858                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 859
 860                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 861                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 862                                         (code << 8 | 0x7C));
 863                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 864                                         (code << 8 | 0x7C));
 865
 866                 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
 867
 868                 if (nphy->elna_gain_config) {
 869                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 870                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 871                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 872                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 873                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 874
 875                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 876                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 877                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 878                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 879                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 880
 881                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 882                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 883                                         (code << 8 | 0x74));
 884                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 885                                         (code << 8 | 0x74));
 886                 }
 887
 888                 if (dev->phy.rev == 2) {
 889                         for (i = 0; i < 4; i++) {
 890                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 891                                                 (0x0400 * i) + 0x0020);
 892                                 for (j = 0; j < 21; j++)
 893                                         b43_phy_write(dev,
 894                                                 B43_NPHY_TABLE_DATALO, 3 * j);
 895                         }
 896
 897                         b43_nphy_set_rf_sequence(dev, 5,
 898                                         rfseq_events, rfseq_delays, 3);
 899                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
 900                                 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
 901                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
 902
 903                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 904                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
 905                                                 0xFF80, 4);
 906                 }
 907         }
 908 }
 909
 910 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
 911 static void b43_nphy_workarounds(struct b43_wldev *dev)
 912 {
 913         struct ssb_bus *bus = dev->dev->bus;
 914         struct b43_phy *phy = &dev->phy;
 915         struct b43_phy_n *nphy = phy->n;
 916
 917         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
 918         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
 919
 920         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
 921         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
 922
 923         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 924                 b43_nphy_classifier(dev, 1, 0);
 925         else
 926                 b43_nphy_classifier(dev, 1, 1);
 927
 928         if (nphy->hang_avoid)
 929                 b43_nphy_stay_in_carrier_search(dev, 1);
 930
 931         b43_phy_set(dev, B43_NPHY_IQFLIP,
 932                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 933
 934         if (dev->phy.rev >= 3) {
 935                 /* TODO */
 936         } else {
 937                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
 938                     nphy->band5g_pwrgain) {
 939                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
 940                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
 941                 } else {
 942                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 943                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
 944                 }
 945
 946                 /* TODO: convert to b43_ntab_write? */
 947                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
 948                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 949                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
 950                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 951                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
 952                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 953                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
 954                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 955
 956                 if (dev->phy.rev < 2) {
 957                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
 958                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 959                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
 960                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 961                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
 962                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 963                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
 964                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 965                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
 966                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
 967                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
 968                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
 969                 }
 970
 971                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 972                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 973                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 974                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 975
 976                 if (bus->sprom.boardflags2_lo & 0x100 &&
 977                     bus->boardinfo.type == 0x8B) {
 978                         delays1[0] = 0x1;
 979                         delays1[5] = 0x14;
 980                 }
 981                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
 982                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
 983
 984                 b43_nphy_gain_crtl_workarounds(dev);
 985
 986                 if (dev->phy.rev < 2) {
 987                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
 988                                 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
 989                 } else if (dev->phy.rev == 2) {
 990                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
 991                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
 992                 }
 993
 994                 if (dev->phy.rev < 2)
 995                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 996                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
 997
 998                 /* Set phase track alpha and beta */
 999                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1000                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1001                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1002                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1003                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1004                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1005
1006                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1007                                 (u16)~B43_NPHY_PIL_DW_64QAM);
1008                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1009                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1010                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1011
1012                 if (dev->phy.rev == 2)
1013                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1014                                         B43_NPHY_FINERX2_CGC_DECGC);
1015         }
1016
1017         if (nphy->hang_avoid)
1018                 b43_nphy_stay_in_carrier_search(dev, 0);
1019 }
1020
1021 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1022 static int b43_nphy_load_samples(struct b43_wldev *dev,
1023                                         struct b43_c32 *samples, u16 len) {
1024         struct b43_phy_n *nphy = dev->phy.n;
1025         u16 i;
1026         u32 *data;
1027
1028         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1029         if (!data) {
1030                 b43err(dev->wl, "allocation for samples loading failed\n");
1031                 return -ENOMEM;
1032         }
1033         if (nphy->hang_avoid)
1034                 b43_nphy_stay_in_carrier_search(dev, 1);
1035
1036         for (i = 0; i < len; i++) {
1037                 data[i] = (samples[i].i & 0x3FF << 10);
1038                 data[i] |= samples[i].q & 0x3FF;
1039         }
1040         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1041
1042         kfree(data);
1043         if (nphy->hang_avoid)
1044                 b43_nphy_stay_in_carrier_search(dev, 0);
1045         return 0;
1046 }
1047
1048 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1049 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1050                                         bool test)
1051 {
1052         int i;
1053         u16 bw, len, rot, angle;
1054         struct b43_c32 *samples;
1055
1056
1057         bw = (dev->phy.is_40mhz) ? 40 : 20;
1058         len = bw << 3;
1059
1060         if (test) {
1061                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1062                         bw = 82;
1063                 else
1064                         bw = 80;
1065
1066                 if (dev->phy.is_40mhz)
1067                         bw <<= 1;
1068
1069                 len = bw << 1;
1070         }
1071
1072         samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1073         if (!samples) {
1074                 b43err(dev->wl, "allocation for samples generation failed\n");
1075                 return 0;
1076         }
1077         rot = (((freq * 36) / bw) << 16) / 100;
1078         angle = 0;
1079
1080         for (i = 0; i < len; i++) {
1081                 samples[i] = b43_cordic(angle);
1082                 angle += rot;
1083                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1084                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1085         }
1086
1087         i = b43_nphy_load_samples(dev, samples, len);
1088         kfree(samples);
1089         return (i < 0) ? 0 : len;
1090 }
1091
1092 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1093 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1094                                         u16 wait, bool iqmode, bool dac_test)
1095 {
1096         struct b43_phy_n *nphy = dev->phy.n;
1097         int i;
1098         u16 seq_mode;
1099         u32 tmp;
1100
1101         if (nphy->hang_avoid)
1102                 b43_nphy_stay_in_carrier_search(dev, true);
1103
1104         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1105                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1106                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1107         }
1108
1109         if (!dev->phy.is_40mhz)
1110                 tmp = 0x6464;
1111         else
1112                 tmp = 0x4747;
1113         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1114
1115         if (nphy->hang_avoid)
1116                 b43_nphy_stay_in_carrier_search(dev, false);
1117
1118         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1119
1120         if (loops != 0xFFFF)
1121                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1122         else
1123                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1124
1125         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1126
1127         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1128
1129         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1130         if (iqmode) {
1131                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1132                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1133         } else {
1134                 if (dac_test)
1135                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1136                 else
1137                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1138         }
1139         for (i = 0; i < 100; i++) {
1140                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1141                         i = 0;
1142                         break;
1143                 }
1144                 udelay(10);
1145         }
1146         if (i)
1147                 b43err(dev->wl, "run samples timeout\n");
1148
1149         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1150 }
1151
1152 /*
1153  * Transmits a known value for LO calibration
1154  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1155  */
1156 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1157                                 bool iqmode, bool dac_test)
1158 {
1159         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1160         if (samp == 0)
1161                 return -1;
1162         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1163         return 0;
1164 }
1165
1166 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1167 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1168 {
1169         struct b43_phy_n *nphy = dev->phy.n;
1170         int i, j;
1171         u32 tmp;
1172         u32 cur_real, cur_imag, real_part, imag_part;
1173
1174         u16 buffer[7];
1175
1176         if (nphy->hang_avoid)
1177                 b43_nphy_stay_in_carrier_search(dev, true);
1178
1179         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1180
1181         for (i = 0; i < 2; i++) {
1182                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1183                         (buffer[i * 2 + 1] & 0x3FF);
1184                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1185                                 (((i + 26) << 10) | 320));
1186                 for (j = 0; j < 128; j++) {
1187                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1188                                         ((tmp >> 16) & 0xFFFF));
1189                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1190                                         (tmp & 0xFFFF));
1191                 }
1192         }
1193
1194         for (i = 0; i < 2; i++) {
1195                 tmp = buffer[5 + i];
1196                 real_part = (tmp >> 8) & 0xFF;
1197                 imag_part = (tmp & 0xFF);
1198                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1199                                 (((i + 26) << 10) | 448));
1200
1201                 if (dev->phy.rev >= 3) {
1202                         cur_real = real_part;
1203                         cur_imag = imag_part;
1204                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1205                 }
1206
1207                 for (j = 0; j < 128; j++) {
1208                         if (dev->phy.rev < 3) {
1209                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1210                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1211                                 tmp = ((cur_real & 0xFF) << 8) |
1212                                         (cur_imag & 0xFF);
1213                         }
1214                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1215                                         ((tmp >> 16) & 0xFFFF));
1216                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1217                                         (tmp & 0xFFFF));
1218                 }
1219         }
1220
1221         if (dev->phy.rev >= 3) {
1222                 b43_shm_write16(dev, B43_SHM_SHARED,
1223                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1224                 b43_shm_write16(dev, B43_SHM_SHARED,
1225                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1226         }
1227
1228         if (nphy->hang_avoid)
1229                 b43_nphy_stay_in_carrier_search(dev, false);
1230 }
1231
1232 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1233 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1234                                         u8 *events, u8 *delays, u8 length)
1235 {
1236         struct b43_phy_n *nphy = dev->phy.n;
1237         u8 i;
1238         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1239         u16 offset1 = cmd << 4;
1240         u16 offset2 = offset1 + 0x80;
1241
1242         if (nphy->hang_avoid)
1243                 b43_nphy_stay_in_carrier_search(dev, true);
1244
1245         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1246         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1247
1248         for (i = length; i < 16; i++) {
1249                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1250                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1251         }
1252
1253         if (nphy->hang_avoid)
1254                 b43_nphy_stay_in_carrier_search(dev, false);
1255 }
1256
1257 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1258 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1259                                        enum b43_nphy_rf_sequence seq)
1260 {
1261         static const u16 trigger[] = {
1262                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1263                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1264                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1265                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1266                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1267                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1268         };
1269         int i;
1270         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1271
1272         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1273
1274         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1275                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1276         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1277         for (i = 0; i < 200; i++) {
1278                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1279                         goto ok;
1280                 msleep(1);
1281         }
1282         b43err(dev->wl, "RF sequence status timeout\n");
1283 ok:
1284         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1285 }
1286
1287 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1288 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1289                                                 u16 value, u8 core, bool off)
1290 {
1291         int i;
1292         u8 index = fls(field);
1293         u8 addr, en_addr, val_addr;
1294         /* we expect only one bit set */
1295         B43_WARN_ON(field & (~(1 << (index - 1))));
1296
1297         if (dev->phy.rev >= 3) {
1298                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1299                 for (i = 0; i < 2; i++) {
1300                         if (index == 0 || index == 16) {
1301                                 b43err(dev->wl,
1302                                         "Unsupported RF Ctrl Override call\n");
1303                                 return;
1304                         }
1305
1306                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1307                         en_addr = B43_PHY_N((i == 0) ?
1308                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1309                         val_addr = B43_PHY_N((i == 0) ?
1310                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1311
1312                         if (off) {
1313                                 b43_phy_mask(dev, en_addr, ~(field));
1314                                 b43_phy_mask(dev, val_addr,
1315                                                 ~(rf_ctrl->val_mask));
1316                         } else {
1317                                 if (core == 0 || ((1 << core) & i) != 0) {
1318                                         b43_phy_set(dev, en_addr, field);
1319                                         b43_phy_maskset(dev, val_addr,
1320                                                 ~(rf_ctrl->val_mask),
1321                                                 (value << rf_ctrl->val_shift));
1322                                 }
1323                         }
1324                 }
1325         } else {
1326                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1327                 if (off) {
1328                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1329                         value = 0;
1330                 } else {
1331                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1332                 }
1333
1334                 for (i = 0; i < 2; i++) {
1335                         if (index <= 1 || index == 16) {
1336                                 b43err(dev->wl,
1337                                         "Unsupported RF Ctrl Override call\n");
1338                                 return;
1339                         }
1340
1341                         if (index == 2 || index == 10 ||
1342                             (index >= 13 && index <= 15)) {
1343                                 core = 1;
1344                         }
1345
1346                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1347                         addr = B43_PHY_N((i == 0) ?
1348                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1349
1350                         if ((core & (1 << i)) != 0)
1351                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1352                                                 (value << rf_ctrl->shift));
1353
1354                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1355                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1356                                         B43_NPHY_RFCTL_CMD_START);
1357                         udelay(1);
1358                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1359                 }
1360         }
1361 }
1362
1363 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1364 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1365                                                 u16 value, u8 core)
1366 {
1367         u8 i, j;
1368         u16 reg, tmp, val;
1369
1370         B43_WARN_ON(dev->phy.rev < 3);
1371         B43_WARN_ON(field > 4);
1372
1373         for (i = 0; i < 2; i++) {
1374                 if ((core == 1 && i == 1) || (core == 2 && !i))
1375                         continue;
1376
1377                 reg = (i == 0) ?
1378                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1379                 b43_phy_mask(dev, reg, 0xFBFF);
1380
1381                 switch (field) {
1382                 case 0:
1383                         b43_phy_write(dev, reg, 0);
1384                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1385                         break;
1386                 case 1:
1387                         if (!i) {
1388                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1389                                                 0xFC3F, (value << 6));
1390                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1391                                                 0xFFFE, 1);
1392                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1393                                                 B43_NPHY_RFCTL_CMD_START);
1394                                 for (j = 0; j < 100; j++) {
1395                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1396                                                 j = 0;
1397                                                 break;
1398                                         }
1399                                         udelay(10);
1400                                 }
1401                                 if (j)
1402                                         b43err(dev->wl,
1403                                                 "intc override timeout\n");
1404                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1405                                                 0xFFFE);
1406                         } else {
1407                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1408                                                 0xFC3F, (value << 6));
1409                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1410                                                 0xFFFE, 1);
1411                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1412                                                 B43_NPHY_RFCTL_CMD_RXTX);
1413                                 for (j = 0; j < 100; j++) {
1414                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1415                                                 j = 0;
1416                                                 break;
1417                                         }
1418                                         udelay(10);
1419                                 }
1420                                 if (j)
1421                                         b43err(dev->wl,
1422                                                 "intc override timeout\n");
1423                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1424                                                 0xFFFE);
1425                         }
1426                         break;
1427                 case 2:
1428                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1429                                 tmp = 0x0020;
1430                                 val = value << 5;
1431                         } else {
1432                                 tmp = 0x0010;
1433                                 val = value << 4;
1434                         }
1435                         b43_phy_maskset(dev, reg, ~tmp, val);
1436                         break;
1437                 case 3:
1438                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1439                                 tmp = 0x0001;
1440                                 val = value;
1441                         } else {
1442                                 tmp = 0x0004;
1443                                 val = value << 2;
1444                         }
1445                         b43_phy_maskset(dev, reg, ~tmp, val);
1446                         break;
1447                 case 4:
1448                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1449                                 tmp = 0x0002;
1450                                 val = value << 1;
1451                         } else {
1452                                 tmp = 0x0008;
1453                                 val = value << 3;
1454                         }
1455                         b43_phy_maskset(dev, reg, ~tmp, val);
1456                         break;
1457                 }
1458         }
1459 }
1460
1461 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1462 {
1463         unsigned int i;
1464         u16 val;
1465
1466         val = 0x1E1F;
1467         for (i = 0; i < 14; i++) {
1468                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1469                 val -= 0x202;
1470         }
1471         val = 0x3E3F;
1472         for (i = 0; i < 16; i++) {
1473                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1474                 val -= 0x202;
1475         }
1476         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1477 }
1478
1479 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1480 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1481                                        s8 offset, u8 core, u8 rail, u8 type)
1482 {
1483         u16 tmp;
1484         bool core1or5 = (core == 1) || (core == 5);
1485         bool core2or5 = (core == 2) || (core == 5);
1486
1487         offset = clamp_val(offset, -32, 31);
1488         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1489
1490         if (core1or5 && (rail == 0) && (type == 2))
1491                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1492         if (core1or5 && (rail == 1) && (type == 2))
1493                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1494         if (core2or5 && (rail == 0) && (type == 2))
1495                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1496         if (core2or5 && (rail == 1) && (type == 2))
1497                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1498         if (core1or5 && (rail == 0) && (type == 0))
1499                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1500         if (core1or5 && (rail == 1) && (type == 0))
1501                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1502         if (core2or5 && (rail == 0) && (type == 0))
1503                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1504         if (core2or5 && (rail == 1) && (type == 0))
1505                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1506         if (core1or5 && (rail == 0) && (type == 1))
1507                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1508         if (core1or5 && (rail == 1) && (type == 1))
1509                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1510         if (core2or5 && (rail == 0) && (type == 1))
1511                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1512         if (core2or5 && (rail == 1) && (type == 1))
1513                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1514         if (core1or5 && (rail == 0) && (type == 6))
1515                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1516         if (core1or5 && (rail == 1) && (type == 6))
1517                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1518         if (core2or5 && (rail == 0) && (type == 6))
1519                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1520         if (core2or5 && (rail == 1) && (type == 6))
1521                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1522         if (core1or5 && (rail == 0) && (type == 3))
1523                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1524         if (core1or5 && (rail == 1) && (type == 3))
1525                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1526         if (core2or5 && (rail == 0) && (type == 3))
1527                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1528         if (core2or5 && (rail == 1) && (type == 3))
1529                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1530         if (core1or5 && (type == 4))
1531                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1532         if (core2or5 && (type == 4))
1533                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1534         if (core1or5 && (type == 5))
1535                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1536         if (core2or5 && (type == 5))
1537                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1538 }
1539
1540 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1541 {
1542         u16 val;
1543
1544         if (type < 3)
1545                 val = 0;
1546         else if (type == 6)
1547                 val = 1;
1548         else if (type == 3)
1549                 val = 2;
1550         else
1551                 val = 3;
1552
1553         val = (val << 12) | (val << 14);
1554         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1555         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1556
1557         if (type < 3) {
1558                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1559                                 (type + 1) << 4);
1560                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1561                                 (type + 1) << 4);
1562         }
1563
1564         /* TODO use some definitions */
1565         if (code == 0) {
1566                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1567                 if (type < 3) {
1568                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1569                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1570                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1571                         udelay(20);
1572                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1573                 }
1574         } else {
1575                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1576                                 0x3000);
1577                 if (type < 3) {
1578                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1579                                         0xFEC7, 0x0180);
1580                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1581                                         0xEFDC, (code << 1 | 0x1021));
1582                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1583                         udelay(20);
1584                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1585                 }
1586         }
1587 }
1588
1589 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1590 {
1591         struct b43_phy_n *nphy = dev->phy.n;
1592         u8 i;
1593         u16 reg, val;
1594
1595         if (code == 0) {
1596                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1597                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1598                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1599                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1600                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1601                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1602                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1603                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1604         } else {
1605                 for (i = 0; i < 2; i++) {
1606                         if ((code == 1 && i == 1) || (code == 2 && !i))
1607                                 continue;
1608
1609                         reg = (i == 0) ?
1610                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1611                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1612
1613                         if (type < 3) {
1614                                 reg = (i == 0) ?
1615                                         B43_NPHY_AFECTL_C1 :
1616                                         B43_NPHY_AFECTL_C2;
1617                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1618
1619                                 reg = (i == 0) ?
1620                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1621                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1622                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1623
1624                                 if (type == 0)
1625                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1626                                 else if (type == 1)
1627                                         val = 16;
1628                                 else
1629                                         val = 32;
1630                                 b43_phy_set(dev, reg, val);
1631
1632                                 reg = (i == 0) ?
1633                                         B43_NPHY_TXF_40CO_B1S0 :
1634                                         B43_NPHY_TXF_40CO_B32S1;
1635                                 b43_phy_set(dev, reg, 0x0020);
1636                         } else {
1637                                 if (type == 6)
1638                                         val = 0x0100;
1639                                 else if (type == 3)
1640                                         val = 0x0200;
1641                                 else
1642                                         val = 0x0300;
1643
1644                                 reg = (i == 0) ?
1645                                         B43_NPHY_AFECTL_C1 :
1646                                         B43_NPHY_AFECTL_C2;
1647
1648                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1649                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1650
1651                                 if (type != 3 && type != 6) {
1652                                         enum ieee80211_band band =
1653                                                 b43_current_band(dev->wl);
1654
1655                                         if ((nphy->ipa2g_on &&
1656                                                 band == IEEE80211_BAND_2GHZ) ||
1657                                                 (nphy->ipa5g_on &&
1658                                                 band == IEEE80211_BAND_5GHZ))
1659                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1660                                         else
1661                                                 val = 0x11;
1662                                         reg = (i == 0) ? 0x2000 : 0x3000;
1663                                         reg |= B2055_PADDRV;
1664                                         b43_radio_write16(dev, reg, val);
1665
1666                                         reg = (i == 0) ?
1667                                                 B43_NPHY_AFECTL_OVER1 :
1668                                                 B43_NPHY_AFECTL_OVER;
1669                                         b43_phy_set(dev, reg, 0x0200);
1670                                 }
1671                         }
1672                 }
1673         }
1674 }
1675
1676 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1677 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1678 {
1679         if (dev->phy.rev >= 3)
1680                 b43_nphy_rev3_rssi_select(dev, code, type);
1681         else
1682                 b43_nphy_rev2_rssi_select(dev, code, type);
1683 }
1684
1685 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1686 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1687 {
1688         int i;
1689         for (i = 0; i < 2; i++) {
1690                 if (type == 2) {
1691                         if (i == 0) {
1692                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1693                                                   0xFC, buf[0]);
1694                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1695                                                   0xFC, buf[1]);
1696                         } else {
1697                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1698                                                   0xFC, buf[2 * i]);
1699                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1700                                                   0xFC, buf[2 * i + 1]);
1701                         }
1702                 } else {
1703                         if (i == 0)
1704                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1705                                                   0xF3, buf[0] << 2);
1706                         else
1707                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1708                                                   0xF3, buf[2 * i + 1] << 2);
1709                 }
1710         }
1711 }
1712
1713 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1714 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1715                                 u8 nsamp)
1716 {
1717         int i;
1718         int out;
1719         u16 save_regs_phy[9];
1720         u16 s[2];
1721
1722         if (dev->phy.rev >= 3) {
1723                 save_regs_phy[0] = b43_phy_read(dev,
1724                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1725                 save_regs_phy[1] = b43_phy_read(dev,
1726                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1727                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1728                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1729                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1730                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1731                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1732                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1733         }
1734
1735         b43_nphy_rssi_select(dev, 5, type);
1736
1737         if (dev->phy.rev < 2) {
1738                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1739                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1740         }
1741
1742         for (i = 0; i < 4; i++)
1743                 buf[i] = 0;
1744
1745         for (i = 0; i < nsamp; i++) {
1746                 if (dev->phy.rev < 2) {
1747                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1748                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1749                 } else {
1750                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1751                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1752                 }
1753
1754                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1755                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1756                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1757                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1758         }
1759         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1760                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1761
1762         if (dev->phy.rev < 2)
1763                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1764
1765         if (dev->phy.rev >= 3) {
1766                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1767                                 save_regs_phy[0]);
1768                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1769                                 save_regs_phy[1]);
1770                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1771                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1772                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1773                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1774                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1775                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1776         }
1777
1778         return out;
1779 }
1780
1781 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1782 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1783 {
1784         int i, j;
1785         u8 state[4];
1786         u8 code, val;
1787         u16 class, override;
1788         u8 regs_save_radio[2];
1789         u16 regs_save_phy[2];
1790         s8 offset[4];
1791
1792         u16 clip_state[2];
1793         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1794         s32 results_min[4] = { };
1795         u8 vcm_final[4] = { };
1796         s32 results[4][4] = { };
1797         s32 miniq[4][2] = { };
1798
1799         if (type == 2) {
1800                 code = 0;
1801                 val = 6;
1802         } else if (type < 2) {
1803                 code = 25;
1804                 val = 4;
1805         } else {
1806                 B43_WARN_ON(1);
1807                 return;
1808         }
1809
1810         class = b43_nphy_classifier(dev, 0, 0);
1811         b43_nphy_classifier(dev, 7, 4);
1812         b43_nphy_read_clip_detection(dev, clip_state);
1813         b43_nphy_write_clip_detection(dev, clip_off);
1814
1815         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1816                 override = 0x140;
1817         else
1818                 override = 0x110;
1819
1820         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1821         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1822         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1823         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1824
1825         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1826         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1827         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1828         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1829
1830         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1831         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1832         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1833         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1834         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1835         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1836
1837         b43_nphy_rssi_select(dev, 5, type);
1838         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1839         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1840
1841         for (i = 0; i < 4; i++) {
1842                 u8 tmp[4];
1843                 for (j = 0; j < 4; j++)
1844                         tmp[j] = i;
1845                 if (type != 1)
1846                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1847                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1848                 if (type < 2)
1849                         for (j = 0; j < 2; j++)
1850                                 miniq[i][j] = min(results[i][2 * j],
1851                                                 results[i][2 * j + 1]);
1852         }
1853
1854         for (i = 0; i < 4; i++) {
1855                 s32 mind = 40;
1856                 u8 minvcm = 0;
1857                 s32 minpoll = 249;
1858                 s32 curr;
1859                 for (j = 0; j < 4; j++) {
1860                         if (type == 2)
1861                                 curr = abs(results[j][i]);
1862                         else
1863                                 curr = abs(miniq[j][i / 2] - code * 8);
1864
1865                         if (curr < mind) {
1866                                 mind = curr;
1867                                 minvcm = j;
1868                         }
1869
1870                         if (results[j][i] < minpoll)
1871                                 minpoll = results[j][i];
1872                 }
1873                 results_min[i] = minpoll;
1874                 vcm_final[i] = minvcm;
1875         }
1876
1877         if (type != 1)
1878                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1879
1880         for (i = 0; i < 4; i++) {
1881                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1882
1883                 if (offset[i] < 0)
1884                         offset[i] = -((abs(offset[i]) + 4) / 8);
1885                 else
1886                         offset[i] = (offset[i] + 4) / 8;
1887
1888                 if (results_min[i] == 248)
1889                         offset[i] = code - 32;
1890
1891                 if (i % 2 == 0)
1892                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1893                                                         type);
1894                 else
1895                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1896                                                         type);
1897         }
1898
1899         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1900         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1901
1902         switch (state[2]) {
1903         case 1:
1904                 b43_nphy_rssi_select(dev, 1, 2);
1905                 break;
1906         case 4:
1907                 b43_nphy_rssi_select(dev, 1, 0);
1908                 break;
1909         case 2:
1910                 b43_nphy_rssi_select(dev, 1, 1);
1911                 break;
1912         default:
1913                 b43_nphy_rssi_select(dev, 1, 1);
1914                 break;
1915         }
1916
1917         switch (state[3]) {
1918         case 1:
1919                 b43_nphy_rssi_select(dev, 2, 2);
1920                 break;
1921         case 4:
1922                 b43_nphy_rssi_select(dev, 2, 0);
1923                 break;
1924         default:
1925                 b43_nphy_rssi_select(dev, 2, 1);
1926                 break;
1927         }
1928
1929         b43_nphy_rssi_select(dev, 0, type);
1930
1931         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1932         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1933         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1934         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1935
1936         b43_nphy_classifier(dev, 7, class);
1937         b43_nphy_write_clip_detection(dev, clip_state);
1938 }
1939
1940 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1941 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1942 {
1943         /* TODO */
1944 }
1945
1946 /*
1947  * RSSI Calibration
1948  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1949  */
1950 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1951 {
1952         if (dev->phy.rev >= 3) {
1953                 b43_nphy_rev3_rssi_cal(dev);
1954         } else {
1955                 b43_nphy_rev2_rssi_cal(dev, 2);
1956                 b43_nphy_rev2_rssi_cal(dev, 0);
1957                 b43_nphy_rev2_rssi_cal(dev, 1);
1958         }
1959 }
1960
1961 /*
1962  * Restore RSSI Calibration
1963  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1964  */
1965 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1966 {
1967         struct b43_phy_n *nphy = dev->phy.n;
1968
1969         u16 *rssical_radio_regs = NULL;
1970         u16 *rssical_phy_regs = NULL;
1971
1972         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1973                 if (!nphy->rssical_chanspec_2G)
1974                         return;
1975                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1976                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1977         } else {
1978                 if (!nphy->rssical_chanspec_5G)
1979                         return;
1980                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1981                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1982         }
1983
1984         /* TODO use some definitions */
1985         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1986         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1987
1988         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1989         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1990         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1991         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1992
1993         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1994         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1995         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1996         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1997
1998         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1999         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2000         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2001         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2002 }
2003
2004 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2005 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2006 {
2007         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2008                 if (dev->phy.rev >= 6) {
2009                         /* TODO If the chip is 47162
2010                                 return txpwrctrl_tx_gain_ipa_rev5 */
2011                         return txpwrctrl_tx_gain_ipa_rev6;
2012                 } else if (dev->phy.rev >= 5) {
2013                         return txpwrctrl_tx_gain_ipa_rev5;
2014                 } else {
2015                         return txpwrctrl_tx_gain_ipa;
2016                 }
2017         } else {
2018                 return txpwrctrl_tx_gain_ipa_5g;
2019         }
2020 }
2021
2022 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2023 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2024 {
2025         struct b43_phy_n *nphy = dev->phy.n;
2026         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2027         u16 tmp;
2028         u8 offset, i;
2029
2030         if (dev->phy.rev >= 3) {
2031             for (i = 0; i < 2; i++) {
2032                 tmp = (i == 0) ? 0x2000 : 0x3000;
2033                 offset = i * 11;
2034
2035                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2036                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2037                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2038                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2039                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2040                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2041                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2042                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2043                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2044                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2045                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2046
2047                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2048                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2049                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2050                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2051                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2052                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2053                         if (nphy->ipa5g_on) {
2054                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2055                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2056                         } else {
2057                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2058                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2059                         }
2060                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2061                 } else {
2062                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2063                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2064                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2065                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2066                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2067                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2068                         if (nphy->ipa2g_on) {
2069                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2070                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2071                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2072                         } else {
2073                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2074                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2075                         }
2076                 }
2077                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2078                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2079                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2080             }
2081         } else {
2082                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2083                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2084
2085                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2086                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2087
2088                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2089                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2090
2091                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2092                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2093
2094                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2095                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2096
2097                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2098                     B43_NPHY_BANDCTL_5GHZ)) {
2099                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2100                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2101                 } else {
2102                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2103                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2104                 }
2105
2106                 if (dev->phy.rev < 2) {
2107                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2108                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2109                 } else {
2110                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2111                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2112                 }
2113         }
2114 }
2115
2116 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2117 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2118                                         struct nphy_txgains target,
2119                                         struct nphy_iqcal_params *params)
2120 {
2121         int i, j, indx;
2122         u16 gain;
2123
2124         if (dev->phy.rev >= 3) {
2125                 params->txgm = target.txgm[core];
2126                 params->pga = target.pga[core];
2127                 params->pad = target.pad[core];
2128                 params->ipa = target.ipa[core];
2129                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2130                                         (params->pad << 4) | (params->ipa);
2131                 for (j = 0; j < 5; j++)
2132                         params->ncorr[j] = 0x79;
2133         } else {
2134                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2135                         (target.txgm[core] << 8);
2136
2137                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2138                         1 : 0;
2139                 for (i = 0; i < 9; i++)
2140                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2141                                 break;
2142                 i = min(i, 8);
2143
2144                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2145                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2146                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2147                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2148                                         (params->pad << 2);
2149                 for (j = 0; j < 4; j++)
2150                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2151         }
2152 }
2153
2154 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2155 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2156 {
2157         struct b43_phy_n *nphy = dev->phy.n;
2158         int i;
2159         u16 scale, entry;
2160
2161         u16 tmp = nphy->txcal_bbmult;
2162         if (core == 0)
2163                 tmp >>= 8;
2164         tmp &= 0xff;
2165
2166         for (i = 0; i < 18; i++) {
2167                 scale = (ladder_lo[i].percent * tmp) / 100;
2168                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2169                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2170
2171                 scale = (ladder_iq[i].percent * tmp) / 100;
2172                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2173                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2174         }
2175 }
2176
2177 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2178 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2179 {
2180         int i;
2181         for (i = 0; i < 15; i++)
2182                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2183                                 tbl_tx_filter_coef_rev4[2][i]);
2184 }
2185
2186 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2187 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2188 {
2189         int i, j;
2190         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2191         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2192
2193         for (i = 0; i < 3; i++)
2194                 for (j = 0; j < 15; j++)
2195                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2196                                         tbl_tx_filter_coef_rev4[i][j]);
2197
2198         if (dev->phy.is_40mhz) {
2199                 for (j = 0; j < 15; j++)
2200                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2201                                         tbl_tx_filter_coef_rev4[3][j]);
2202         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2203                 for (j = 0; j < 15; j++)
2204                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2205                                         tbl_tx_filter_coef_rev4[5][j]);
2206         }
2207
2208         if (dev->phy.channel == 14)
2209                 for (j = 0; j < 15; j++)
2210                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2211                                         tbl_tx_filter_coef_rev4[6][j]);
2212 }
2213
2214 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2215 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2216 {
2217         struct b43_phy_n *nphy = dev->phy.n;
2218
2219         u16 curr_gain[2];
2220         struct nphy_txgains target;
2221         const u32 *table = NULL;
2222
2223         if (nphy->txpwrctrl == 0) {
2224                 int i;
2225
2226                 if (nphy->hang_avoid)
2227                         b43_nphy_stay_in_carrier_search(dev, true);
2228                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2229                 if (nphy->hang_avoid)
2230                         b43_nphy_stay_in_carrier_search(dev, false);
2231
2232                 for (i = 0; i < 2; ++i) {
2233                         if (dev->phy.rev >= 3) {
2234                                 target.ipa[i] = curr_gain[i] & 0x000F;
2235                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2236                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2237                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2238                         } else {
2239                                 target.ipa[i] = curr_gain[i] & 0x0003;
2240                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2241                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2242                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2243                         }
2244                 }
2245         } else {
2246                 int i;
2247                 u16 index[2];
2248                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2249                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2250                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2251                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2252                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2253                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2254
2255                 for (i = 0; i < 2; ++i) {
2256                         if (dev->phy.rev >= 3) {
2257                                 enum ieee80211_band band =
2258                                         b43_current_band(dev->wl);
2259
2260                                 if ((nphy->ipa2g_on &&
2261                                      band == IEEE80211_BAND_2GHZ) ||
2262                                     (nphy->ipa5g_on &&
2263                                      band == IEEE80211_BAND_5GHZ)) {
2264                                         table = b43_nphy_get_ipa_gain_table(dev);
2265                                 } else {
2266                                         if (band == IEEE80211_BAND_5GHZ) {
2267                                                 if (dev->phy.rev == 3)
2268                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2269                                                 else if (dev->phy.rev == 4)
2270                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2271                                                 else
2272                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2273                                         } else {
2274                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2275                                         }
2276                                 }
2277
2278                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2279                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2280                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2281                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2282                         } else {
2283                                 table = b43_ntab_tx_gain_rev0_1_2;
2284
2285                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2286                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2287                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2288                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2289                         }
2290                 }
2291         }
2292
2293         return target;
2294 }
2295
2296 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2297 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2298 {
2299         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2300
2301         if (dev->phy.rev >= 3) {
2302                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2303                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2304                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2305                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2306                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2307                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2308                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2309                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2310                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2311                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2312                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2313                 b43_nphy_reset_cca(dev);
2314         } else {
2315                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2316                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2317                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2318                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2319                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2320                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2321                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2322         }
2323 }
2324
2325 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2326 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2327 {
2328         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2329         u16 tmp;
2330
2331         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2332         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2333         if (dev->phy.rev >= 3) {
2334                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2335                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2336
2337                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2338                 regs[2] = tmp;
2339                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2340
2341                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2342                 regs[3] = tmp;
2343                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2344
2345                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2346                 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2347
2348                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2349                 regs[5] = tmp;
2350                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2351
2352                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2353                 regs[6] = tmp;
2354                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2355                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2356                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2357
2358                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2359                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2360                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2361
2362                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2363                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2364                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2365                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2366         } else {
2367                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2368                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2369                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2370                 regs[2] = tmp;
2371                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2372                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2373                 regs[3] = tmp;
2374                 tmp |= 0x2000;
2375                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2376                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2377                 regs[4] = tmp;
2378                 tmp |= 0x2000;
2379                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2380                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2381                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2382                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2383                         tmp = 0x0180;
2384                 else
2385                         tmp = 0x0120;
2386                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2387                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2388         }
2389 }
2390
2391 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2392 static void b43_nphy_save_cal(struct b43_wldev *dev)
2393 {
2394         struct b43_phy_n *nphy = dev->phy.n;
2395
2396         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2397         u16 *txcal_radio_regs = NULL;
2398         u8 *iqcal_chanspec;
2399         u16 *table = NULL;
2400
2401         if (nphy->hang_avoid)
2402                 b43_nphy_stay_in_carrier_search(dev, 1);
2403
2404         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2405                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2406                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2407                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2408                 table = nphy->cal_cache.txcal_coeffs_2G;
2409         } else {
2410                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2411                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2412                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2413                 table = nphy->cal_cache.txcal_coeffs_5G;
2414         }
2415
2416         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2417         /* TODO use some definitions */
2418         if (dev->phy.rev >= 3) {
2419                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2420                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2421                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2422                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2423                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2424                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2425                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2426                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2427         } else {
2428                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2429                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2430                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2431                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2432         }
2433         *iqcal_chanspec = nphy->radio_chanspec;
2434         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2435
2436         if (nphy->hang_avoid)
2437                 b43_nphy_stay_in_carrier_search(dev, 0);
2438 }
2439
2440 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2441 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2442 {
2443         struct b43_phy_n *nphy = dev->phy.n;
2444
2445         u16 coef[4];
2446         u16 *loft = NULL;
2447         u16 *table = NULL;
2448
2449         int i;
2450         u16 *txcal_radio_regs = NULL;
2451         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2452
2453         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2454                 if (nphy->iqcal_chanspec_2G == 0)
2455                         return;
2456                 table = nphy->cal_cache.txcal_coeffs_2G;
2457                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2458         } else {
2459                 if (nphy->iqcal_chanspec_5G == 0)
2460                         return;
2461                 table = nphy->cal_cache.txcal_coeffs_5G;
2462                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2463         }
2464
2465         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2466
2467         for (i = 0; i < 4; i++) {
2468                 if (dev->phy.rev >= 3)
2469                         table[i] = coef[i];
2470                 else
2471                         coef[i] = 0;
2472         }
2473
2474         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2475         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2476         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2477
2478         if (dev->phy.rev < 2)
2479                 b43_nphy_tx_iq_workaround(dev);
2480
2481         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2482                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2483                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2484         } else {
2485                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2486                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2487         }
2488
2489         /* TODO use some definitions */
2490         if (dev->phy.rev >= 3) {
2491                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2492                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2493                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2494                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2495                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2496                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2497                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2498                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2499         } else {
2500                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2501                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2502                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2503                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2504         }
2505         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2506 }
2507
2508 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2509 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2510                                 struct nphy_txgains target,
2511                                 bool full, bool mphase)
2512 {
2513         struct b43_phy_n *nphy = dev->phy.n;
2514         int i;
2515         int error = 0;
2516         int freq;
2517         bool avoid = false;
2518         u8 length;
2519         u16 tmp, core, type, count, max, numb, last, cmd;
2520         const u16 *table;
2521         bool phy6or5x;
2522
2523         u16 buffer[11];
2524         u16 diq_start = 0;
2525         u16 save[2];
2526         u16 gain[2];
2527         struct nphy_iqcal_params params[2];
2528         bool updated[2] = { };
2529
2530         b43_nphy_stay_in_carrier_search(dev, true);
2531
2532         if (dev->phy.rev >= 4) {
2533                 avoid = nphy->hang_avoid;
2534                 nphy->hang_avoid = 0;
2535         }
2536
2537         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2538
2539         for (i = 0; i < 2; i++) {
2540                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2541                 gain[i] = params[i].cal_gain;
2542         }
2543
2544         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2545
2546         b43_nphy_tx_cal_radio_setup(dev);
2547         b43_nphy_tx_cal_phy_setup(dev);
2548
2549         phy6or5x = dev->phy.rev >= 6 ||
2550                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2551                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2552         if (phy6or5x) {
2553                 if (dev->phy.is_40mhz) {
2554                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2555                                         tbl_tx_iqlo_cal_loft_ladder_40);
2556                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2557                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2558                 } else {
2559                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2560                                         tbl_tx_iqlo_cal_loft_ladder_20);
2561                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2562                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2563                 }
2564         }
2565
2566         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2567
2568         if (!dev->phy.is_40mhz)
2569                 freq = 2500;
2570         else
2571                 freq = 5000;
2572
2573         if (nphy->mphase_cal_phase_id > 2)
2574                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2575                                         0xFFFF, 0, true, false);
2576         else
2577                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2578
2579         if (error == 0) {
2580                 if (nphy->mphase_cal_phase_id > 2) {
2581                         table = nphy->mphase_txcal_bestcoeffs;
2582                         length = 11;
2583                         if (dev->phy.rev < 3)
2584                                 length -= 2;
2585                 } else {
2586                         if (!full && nphy->txiqlocal_coeffsvalid) {
2587                                 table = nphy->txiqlocal_bestc;
2588                                 length = 11;
2589                                 if (dev->phy.rev < 3)
2590                                         length -= 2;
2591                         } else {
2592                                 full = true;
2593                                 if (dev->phy.rev >= 3) {
2594                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2595                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2596                                 } else {
2597                                         table = tbl_tx_iqlo_cal_startcoefs;
2598                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2599                                 }
2600                         }
2601                 }
2602
2603                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2604
2605                 if (full) {
2606                         if (dev->phy.rev >= 3)
2607                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2608                         else
2609                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2610                 } else {
2611                         if (dev->phy.rev >= 3)
2612                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2613                         else
2614                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2615                 }
2616
2617                 if (mphase) {
2618                         count = nphy->mphase_txcal_cmdidx;
2619                         numb = min(max,
2620                                 (u16)(count + nphy->mphase_txcal_numcmds));
2621                 } else {
2622                         count = 0;
2623                         numb = max;
2624                 }
2625
2626                 for (; count < numb; count++) {
2627                         if (full) {
2628                                 if (dev->phy.rev >= 3)
2629                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2630                                 else
2631                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2632                         } else {
2633                                 if (dev->phy.rev >= 3)
2634                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2635                                 else
2636                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2637                         }
2638
2639                         core = (cmd & 0x3000) >> 12;
2640                         type = (cmd & 0x0F00) >> 8;
2641
2642                         if (phy6or5x && updated[core] == 0) {
2643                                 b43_nphy_update_tx_cal_ladder(dev, core);
2644                                 updated[core] = 1;
2645                         }
2646
2647                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2648                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2649
2650                         if (type == 1 || type == 3 || type == 4) {
2651                                 buffer[0] = b43_ntab_read(dev,
2652                                                 B43_NTAB16(15, 69 + core));
2653                                 diq_start = buffer[0];
2654                                 buffer[0] = 0;
2655                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2656                                                 0);
2657                         }
2658
2659                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2660                         for (i = 0; i < 2000; i++) {
2661                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2662                                 if (tmp & 0xC000)
2663                                         break;
2664                                 udelay(10);
2665                         }
2666
2667                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2668                                                 buffer);
2669                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2670                                                 buffer);
2671
2672                         if (type == 1 || type == 3 || type == 4)
2673                                 buffer[0] = diq_start;
2674                 }
2675
2676                 if (mphase)
2677                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2678
2679                 last = (dev->phy.rev < 3) ? 6 : 7;
2680
2681                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2682                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2683                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2684                         if (dev->phy.rev < 3) {
2685                                 buffer[0] = 0;
2686                                 buffer[1] = 0;
2687                                 buffer[2] = 0;
2688                                 buffer[3] = 0;
2689                         }
2690                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2691                                                 buffer);
2692                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2693                                                 buffer);
2694                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2695                                                 buffer);
2696                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2697                                                 buffer);
2698                         length = 11;
2699                         if (dev->phy.rev < 3)
2700                                 length -= 2;
2701                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2702                                                 nphy->txiqlocal_bestc);
2703                         nphy->txiqlocal_coeffsvalid = true;
2704                         /* TODO: Set nphy->txiqlocal_chanspec to
2705                                 the current channel */
2706                 } else {
2707                         length = 11;
2708                         if (dev->phy.rev < 3)
2709                                 length -= 2;
2710                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2711                                                 nphy->mphase_txcal_bestcoeffs);
2712                 }
2713
2714                 b43_nphy_stop_playback(dev);
2715                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2716         }
2717
2718         b43_nphy_tx_cal_phy_cleanup(dev);
2719         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2720
2721         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2722                 b43_nphy_tx_iq_workaround(dev);
2723
2724         if (dev->phy.rev >= 4)
2725                 nphy->hang_avoid = avoid;
2726
2727         b43_nphy_stay_in_carrier_search(dev, false);
2728
2729         return error;
2730 }
2731
2732 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2733 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2734 {
2735         struct b43_phy_n *nphy = dev->phy.n;
2736         u8 i;
2737         u16 buffer[7];
2738         bool equal = true;
2739
2740         if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */)
2741                 return;
2742
2743         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2744         for (i = 0; i < 4; i++) {
2745                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2746                         equal = false;
2747                         break;
2748                 }
2749         }
2750
2751         if (!equal) {
2752                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2753                                         nphy->txiqlocal_bestc);
2754                 for (i = 0; i < 4; i++)
2755                         buffer[i] = 0;
2756                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2757                                         buffer);
2758                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2759                                         &nphy->txiqlocal_bestc[5]);
2760                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2761                                         &nphy->txiqlocal_bestc[5]);
2762         }
2763 }
2764
2765 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2766 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2767                         struct nphy_txgains target, u8 type, bool debug)
2768 {
2769         struct b43_phy_n *nphy = dev->phy.n;
2770         int i, j, index;
2771         u8 rfctl[2];
2772         u8 afectl_core;
2773         u16 tmp[6];
2774         u16 cur_hpf1, cur_hpf2, cur_lna;
2775         u32 real, imag;
2776         enum ieee80211_band band;
2777
2778         u8 use;
2779         u16 cur_hpf;
2780         u16 lna[3] = { 3, 3, 1 };
2781         u16 hpf1[3] = { 7, 2, 0 };
2782         u16 hpf2[3] = { 2, 0, 0 };
2783         u32 power[3] = { };
2784         u16 gain_save[2];
2785         u16 cal_gain[2];
2786         struct nphy_iqcal_params cal_params[2];
2787         struct nphy_iq_est est;
2788         int ret = 0;
2789         bool playtone = true;
2790         int desired = 13;
2791
2792         b43_nphy_stay_in_carrier_search(dev, 1);
2793
2794         if (dev->phy.rev < 2)
2795                 b43_nphy_reapply_tx_cal_coeffs(dev);
2796         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2797         for (i = 0; i < 2; i++) {
2798                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2799                 cal_gain[i] = cal_params[i].cal_gain;
2800         }
2801         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2802
2803         for (i = 0; i < 2; i++) {
2804                 if (i == 0) {
2805                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2806                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2807                         afectl_core = B43_NPHY_AFECTL_C1;
2808                 } else {
2809                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2810                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2811                         afectl_core = B43_NPHY_AFECTL_C2;
2812                 }
2813
2814                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2815                 tmp[2] = b43_phy_read(dev, afectl_core);
2816                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2817                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2818                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2819
2820                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2821                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2822                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2823                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2824                                 (1 - i));
2825                 b43_phy_set(dev, afectl_core, 0x0006);
2826                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2827
2828                 band = b43_current_band(dev->wl);
2829
2830                 if (nphy->rxcalparams & 0xFF000000) {
2831                         if (band == IEEE80211_BAND_5GHZ)
2832                                 b43_phy_write(dev, rfctl[0], 0x140);
2833                         else
2834                                 b43_phy_write(dev, rfctl[0], 0x110);
2835                 } else {
2836                         if (band == IEEE80211_BAND_5GHZ)
2837                                 b43_phy_write(dev, rfctl[0], 0x180);
2838                         else
2839                                 b43_phy_write(dev, rfctl[0], 0x120);
2840                 }
2841
2842                 if (band == IEEE80211_BAND_5GHZ)
2843                         b43_phy_write(dev, rfctl[1], 0x148);
2844                 else
2845                         b43_phy_write(dev, rfctl[1], 0x114);
2846
2847                 if (nphy->rxcalparams & 0x10000) {
2848                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2849                                         (i + 1));
2850                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2851                                         (2 - i));
2852                 }
2853
2854                 for (j = 0; i < 4; j++) {
2855                         if (j < 3) {
2856                                 cur_lna = lna[j];
2857                                 cur_hpf1 = hpf1[j];
2858                                 cur_hpf2 = hpf2[j];
2859                         } else {
2860                                 if (power[1] > 10000) {
2861                                         use = 1;
2862                                         cur_hpf = cur_hpf1;
2863                                         index = 2;
2864                                 } else {
2865                                         if (power[0] > 10000) {
2866                                                 use = 1;
2867                                                 cur_hpf = cur_hpf1;
2868                                                 index = 1;
2869                                         } else {
2870                                                 index = 0;
2871                                                 use = 2;
2872                                                 cur_hpf = cur_hpf2;
2873                                         }
2874                                 }
2875                                 cur_lna = lna[index];
2876                                 cur_hpf1 = hpf1[index];
2877                                 cur_hpf2 = hpf2[index];
2878                                 cur_hpf += desired - hweight32(power[index]);
2879                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2880                                 if (use == 1)
2881                                         cur_hpf1 = cur_hpf;
2882                                 else
2883                                         cur_hpf2 = cur_hpf;
2884                         }
2885
2886                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2887                                         (cur_lna << 2));
2888                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2889                                                                         false);
2890                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2891                         b43_nphy_stop_playback(dev);
2892
2893                         if (playtone) {
2894                                 ret = b43_nphy_tx_tone(dev, 4000,
2895                                                 (nphy->rxcalparams & 0xFFFF),
2896                                                 false, false);
2897                                 playtone = false;
2898                         } else {
2899                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2900                                                         false, false);
2901                         }
2902
2903                         if (ret == 0) {
2904                                 if (j < 3) {
2905                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2906                                                                         false);
2907                                         if (i == 0) {
2908                                                 real = est.i0_pwr;
2909                                                 imag = est.q0_pwr;
2910                                         } else {
2911                                                 real = est.i1_pwr;
2912                                                 imag = est.q1_pwr;
2913                                         }
2914                                         power[i] = ((real + imag) / 1024) + 1;
2915                                 } else {
2916                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2917                                 }
2918                                 b43_nphy_stop_playback(dev);
2919                         }
2920
2921                         if (ret != 0)
2922                                 break;
2923                 }
2924
2925                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2926                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2927                 b43_phy_write(dev, rfctl[1], tmp[5]);
2928                 b43_phy_write(dev, rfctl[0], tmp[4]);
2929                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2930                 b43_phy_write(dev, afectl_core, tmp[2]);
2931                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2932
2933                 if (ret != 0)
2934                         break;
2935         }
2936
2937         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2938         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2939         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2940
2941         b43_nphy_stay_in_carrier_search(dev, 0);
2942
2943         return ret;
2944 }
2945
2946 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2947                         struct nphy_txgains target, u8 type, bool debug)
2948 {
2949         return -1;
2950 }
2951
2952 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2953 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2954                         struct nphy_txgains target, u8 type, bool debug)
2955 {
2956         if (dev->phy.rev >= 3)
2957                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2958         else
2959                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2960 }
2961
2962 /*
2963  * Init N-PHY
2964  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2965  */
2966 int b43_phy_initn(struct b43_wldev *dev)
2967 {
2968         struct ssb_bus *bus = dev->dev->bus;
2969         struct b43_phy *phy = &dev->phy;
2970         struct b43_phy_n *nphy = phy->n;
2971         u8 tx_pwr_state;
2972         struct nphy_txgains target;
2973         u16 tmp;
2974         enum ieee80211_band tmp2;
2975         bool do_rssi_cal;
2976
2977         u16 clip[2];
2978         bool do_cal = false;
2979
2980         if ((dev->phy.rev >= 3) &&
2981            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2982            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2983                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2984         }
2985         nphy->deaf_count = 0;
2986         b43_nphy_tables_init(dev);
2987         nphy->crsminpwr_adjusted = false;
2988         nphy->noisevars_adjusted = false;
2989
2990         /* Clear all overrides */
2991         if (dev->phy.rev >= 3) {
2992                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2993                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2994                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2995                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2996         } else {
2997                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2998         }
2999         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3000         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3001         if (dev->phy.rev < 6) {
3002                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3003                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3004         }
3005         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3006                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3007                        B43_NPHY_RFSEQMODE_TROVER));
3008         if (dev->phy.rev >= 3)
3009                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3010         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3011
3012         if (dev->phy.rev <= 2) {
3013                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3014                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3015                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3016                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3017         }
3018         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3019         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3020
3021         if (bus->sprom.boardflags2_lo & 0x100 ||
3022             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3023              bus->boardinfo.type == 0x8B))
3024                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3025         else
3026                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3027         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3028         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3029         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3030
3031         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3032         b43_nphy_update_txrx_chain(dev);
3033
3034         if (phy->rev < 2) {
3035                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3036                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3037         }
3038
3039         tmp2 = b43_current_band(dev->wl);
3040         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3041             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3042                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3043                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3044                                 nphy->papd_epsilon_offset[0] << 7);
3045                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3046                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3047                                 nphy->papd_epsilon_offset[1] << 7);
3048                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3049         } else if (phy->rev >= 5) {
3050                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3051         }
3052
3053         b43_nphy_workarounds(dev);
3054
3055         /* Reset CCA, in init code it differs a little from standard way */
3056         b43_nphy_bmac_clock_fgc(dev, 1);
3057         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3058         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3059         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3060         b43_nphy_bmac_clock_fgc(dev, 0);
3061
3062         /* TODO N PHY MAC PHY Clock Set with argument 1 */
3063
3064         b43_nphy_pa_override(dev, false);
3065         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3066         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3067         b43_nphy_pa_override(dev, true);
3068
3069         b43_nphy_classifier(dev, 0, 0);
3070         b43_nphy_read_clip_detection(dev, clip);
3071         tx_pwr_state = nphy->txpwrctrl;
3072         /* TODO N PHY TX power control with argument 0
3073                 (turning off power control) */
3074         /* TODO Fix the TX Power Settings */
3075         /* TODO N PHY TX Power Control Idle TSSI */
3076         /* TODO N PHY TX Power Control Setup */
3077
3078         if (phy->rev >= 3) {
3079                 /* TODO */
3080         } else {
3081                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3082                                         b43_ntab_tx_gain_rev0_1_2);
3083                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3084                                         b43_ntab_tx_gain_rev0_1_2);
3085         }
3086
3087         if (nphy->phyrxchain != 3)
3088                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3089         if (nphy->mphase_cal_phase_id > 0)
3090                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3091
3092         do_rssi_cal = false;
3093         if (phy->rev >= 3) {
3094                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3095                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
3096                 else
3097                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
3098
3099                 if (do_rssi_cal)
3100                         b43_nphy_rssi_cal(dev);
3101                 else
3102                         b43_nphy_restore_rssi_cal(dev);
3103         } else {
3104                 b43_nphy_rssi_cal(dev);
3105         }
3106
3107         if (!((nphy->measure_hold & 0x6) != 0)) {
3108                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3109                         do_cal = (nphy->iqcal_chanspec_2G == 0);
3110                 else
3111                         do_cal = (nphy->iqcal_chanspec_5G == 0);
3112
3113                 if (nphy->mute)
3114                         do_cal = false;
3115
3116                 if (do_cal) {
3117                         target = b43_nphy_get_tx_gains(dev);
3118
3119                         if (nphy->antsel_type == 2)
3120                                 ;/*TODO NPHY Superswitch Init with argument 1*/
3121                         if (nphy->perical != 2) {
3122                                 b43_nphy_rssi_cal(dev);
3123                                 if (phy->rev >= 3) {
3124                                         nphy->cal_orig_pwr_idx[0] =
3125                                             nphy->txpwrindex[0].index_internal;
3126                                         nphy->cal_orig_pwr_idx[1] =
3127                                             nphy->txpwrindex[1].index_internal;
3128                                         /* TODO N PHY Pre Calibrate TX Gain */
3129                                         target = b43_nphy_get_tx_gains(dev);
3130                                 }
3131                         }
3132                 }
3133         }
3134
3135         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3136                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3137                         b43_nphy_save_cal(dev);
3138                 else if (nphy->mphase_cal_phase_id == 0)
3139                         ;/* N PHY Periodic Calibration with argument 3 */
3140         } else {
3141                 b43_nphy_restore_cal(dev);
3142         }
3143
3144         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3145         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3146         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3147         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3148         if (phy->rev >= 3 && phy->rev <= 6)
3149                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3150         b43_nphy_tx_lp_fbw(dev);
3151         if (phy->rev >= 3)
3152                 b43_nphy_spur_workaround(dev);
3153
3154         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3155         return 0;
3156 }
3157
3158 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3159 {
3160         struct b43_phy_n *nphy;
3161
3162         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3163         if (!nphy)
3164                 return -ENOMEM;
3165         dev->phy.n = nphy;
3166
3167         return 0;
3168 }
3169
3170 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3171 {
3172         struct b43_phy *phy = &dev->phy;
3173         struct b43_phy_n *nphy = phy->n;
3174
3175         memset(nphy, 0, sizeof(*nphy));
3176
3177         //TODO init struct b43_phy_n
3178 }
3179
3180 static void b43_nphy_op_free(struct b43_wldev *dev)
3181 {
3182         struct b43_phy *phy = &dev->phy;
3183         struct b43_phy_n *nphy = phy->n;
3184
3185         kfree(nphy);
3186         phy->n = NULL;
3187 }
3188
3189 static int b43_nphy_op_init(struct b43_wldev *dev)
3190 {
3191         return b43_phy_initn(dev);
3192 }
3193
3194 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3195 {
3196 #if B43_DEBUG
3197         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3198                 /* OFDM registers are onnly available on A/G-PHYs */
3199                 b43err(dev->wl, "Invalid OFDM PHY access at "
3200                        "0x%04X on N-PHY\n", offset);
3201                 dump_stack();
3202         }
3203         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3204                 /* Ext-G registers are only available on G-PHYs */
3205                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3206                        "0x%04X on N-PHY\n", offset);
3207                 dump_stack();
3208         }
3209 #endif /* B43_DEBUG */
3210 }
3211
3212 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3213 {
3214         check_phyreg(dev, reg);
3215         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3216         return b43_read16(dev, B43_MMIO_PHY_DATA);
3217 }
3218
3219 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3220 {
3221         check_phyreg(dev, reg);
3222         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3223         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3224 }
3225
3226 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3227 {
3228         /* Register 1 is a 32-bit register. */
3229         B43_WARN_ON(reg == 1);
3230         /* N-PHY needs 0x100 for read access */
3231         reg |= 0x100;
3232
3233         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3234         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3235 }
3236
3237 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3238 {
3239         /* Register 1 is a 32-bit register. */
3240         B43_WARN_ON(reg == 1);
3241
3242         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3243         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3244 }
3245
3246 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3247                                         bool blocked)
3248 {//TODO
3249 }
3250
3251 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3252 {
3253         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3254                       on ? 0 : 0x7FFF);
3255 }
3256
3257 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3258                                       unsigned int new_channel)
3259 {
3260         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3261                 if ((new_channel < 1) || (new_channel > 14))
3262                         return -EINVAL;
3263         } else {
3264                 if (new_channel > 200)
3265                         return -EINVAL;
3266         }
3267
3268         return nphy_channel_switch(dev, new_channel);
3269 }
3270
3271 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3272 {
3273         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3274                 return 1;
3275         return 36;
3276 }
3277
3278 const struct b43_phy_operations b43_phyops_n = {
3279         .allocate               = b43_nphy_op_allocate,
3280         .free                   = b43_nphy_op_free,
3281         .prepare_structs        = b43_nphy_op_prepare_structs,
3282         .init                   = b43_nphy_op_init,
3283         .phy_read               = b43_nphy_op_read,
3284         .phy_write              = b43_nphy_op_write,
3285         .radio_read             = b43_nphy_op_radio_read,
3286         .radio_write            = b43_nphy_op_radio_write,
3287         .software_rfkill        = b43_nphy_op_software_rfkill,
3288         .switch_analog          = b43_nphy_op_switch_analog,
3289         .switch_channel         = b43_nphy_op_switch_channel,
3290         .get_default_chan       = b43_nphy_op_get_default_chan,
3291         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3292         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3293 };