drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 enum b43_nphy_rf_sequence {
  59         B43_RFSEQ_RX2TX,
  60         B43_RFSEQ_TX2RX,
  61         B43_RFSEQ_RESET2RX,
  62         B43_RFSEQ_UPDATE_GAINH,
  63         B43_RFSEQ_UPDATE_GAINL,
  64         B43_RFSEQ_UPDATE_GAINU,
  65 };
  66
  67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  68                                         u8 *events, u8 *delays, u8 length);
  69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  70                                        enum b43_nphy_rf_sequence seq);
  71 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  72                                                 u16 value, u8 core, bool off);
  73 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  74                                                 u16 value, u8 core);
  75
  76 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  77 {//TODO
  78 }
  79
  80 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  81 {//TODO
  82 }
  83
  84 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  85                                                         bool ignore_tssi)
  86 {//TODO
  87         return B43_TXPWR_RES_DONE;
  88 }
  89
  90 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  91                                      const struct b43_nphy_channeltab_entry *e)
  92 {
  93         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  94         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  95         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  96         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  97         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  98         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  99         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 100         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 101         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 102         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 103         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 104         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 105         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 106         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 107         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 108         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 109         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 110         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 111         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 112         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 113         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 114         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 115 }
 116
 117 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 118                                    const struct b43_nphy_channeltab_entry *e)
 119 {
 120         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 121         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 122         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 123         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 124         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 125         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 126 }
 127
 128 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 129 {
 130         //TODO
 131 }
 132
 133 /* Tune the hardware to a new channel. */
 134 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 135 {
 136         const struct b43_nphy_channeltab_entry *tabent;
 137
 138         tabent = b43_nphy_get_chantabent(dev, channel);
 139         if (!tabent)
 140                 return -ESRCH;
 141
 142         //FIXME enable/disable band select upper20 in RXCTL
 143         if (0 /*FIXME 5Ghz*/)
 144                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 145         else
 146                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 147         b43_chantab_radio_upload(dev, tabent);
 148         udelay(50);
 149         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 150         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 151         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 152         udelay(300);
 153         if (0 /*FIXME 5Ghz*/)
 154                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 155         else
 156                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 157         b43_chantab_phy_upload(dev, tabent);
 158         b43_nphy_tx_power_fix(dev);
 159
 160         return 0;
 161 }
 162
 163 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 164 {
 165         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 166                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 167         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 168                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 169                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 170         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 171                     B43_NPHY_RFCTL_CMD_PORFORCE);
 172 }
 173
 174 static void b43_radio_init2055_post(struct b43_wldev *dev)
 175 {
 176         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 177         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 178         int i;
 179         u16 val;
 180
 181         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 182         msleep(1);
 183         if ((sprom->revision != 4) ||
 184            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 185                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 186                     (binfo->type != 0x46D) ||
 187                     (binfo->rev < 0x41)) {
 188                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 189                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 190                         msleep(1);
 191                 }
 192         }
 193         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 194         msleep(1);
 195         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 196         msleep(1);
 197         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 198         msleep(1);
 199         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 200         msleep(1);
 201         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 202         msleep(1);
 203         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 204         msleep(1);
 205         for (i = 0; i < 100; i++) {
 206                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 207                 if (val & 0x80)
 208                         break;
 209                 udelay(10);
 210         }
 211         msleep(1);
 212         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 213         msleep(1);
 214         nphy_channel_switch(dev, dev->phy.channel);
 215         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 216         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 217         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 218         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 219 }
 220
 221 /* Initialize a Broadcom 2055 N-radio */
 222 static void b43_radio_init2055(struct b43_wldev *dev)
 223 {
 224         b43_radio_init2055_pre(dev);
 225         if (b43_status(dev) < B43_STAT_INITIALIZED)
 226                 b2055_upload_inittab(dev, 0, 1);
 227         else
 228                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 229         b43_radio_init2055_post(dev);
 230 }
 231
 232 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 233 {
 234         b43_radio_init2055(dev);
 235 }
 236
 237 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 238 {
 239         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 240                      ~B43_NPHY_RFCTL_CMD_EN);
 241 }
 242
 243 /*
 244  * Upload the N-PHY tables.
 245  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 246  */
 247 static void b43_nphy_tables_init(struct b43_wldev *dev)
 248 {
 249         if (dev->phy.rev < 3)
 250                 b43_nphy_rev0_1_2_tables_init(dev);
 251         else
 252                 b43_nphy_rev3plus_tables_init(dev);
 253 }
 254
 255 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 256 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 257 {
 258         struct b43_phy_n *nphy = dev->phy.n;
 259         enum ieee80211_band band;
 260         u16 tmp;
 261
 262         if (!enable) {
 263                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 264                                                        B43_NPHY_RFCTL_INTC1);
 265                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 266                                                        B43_NPHY_RFCTL_INTC2);
 267                 band = b43_current_band(dev->wl);
 268                 if (dev->phy.rev >= 3) {
 269                         if (band == IEEE80211_BAND_5GHZ)
 270                                 tmp = 0x600;
 271                         else
 272                                 tmp = 0x480;
 273                 } else {
 274                         if (band == IEEE80211_BAND_5GHZ)
 275                                 tmp = 0x180;
 276                         else
 277                                 tmp = 0x120;
 278                 }
 279                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 280                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 281         } else {
 282                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 283                                 nphy->rfctrl_intc1_save);
 284                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 285                                 nphy->rfctrl_intc2_save);
 286         }
 287 }
 288
 289 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 290 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 291 {
 292         struct b43_phy_n *nphy = dev->phy.n;
 293         u16 tmp;
 294         enum ieee80211_band band = b43_current_band(dev->wl);
 295         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 296                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 297
 298         if (dev->phy.rev >= 3) {
 299                 if (ipa) {
 300                         tmp = 4;
 301                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 302                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 303                 }
 304
 305                 tmp = 1;
 306                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 307                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 308         }
 309 }
 310
 311 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 312 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 313 {
 314         u32 tmslow;
 315
 316         if (dev->phy.type != B43_PHYTYPE_N)
 317                 return;
 318
 319         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 320         if (force)
 321                 tmslow |= SSB_TMSLOW_FGC;
 322         else
 323                 tmslow &= ~SSB_TMSLOW_FGC;
 324         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 325 }
 326
 327 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 328 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 329 {
 330         u16 bbcfg;
 331
 332         b43_nphy_bmac_clock_fgc(dev, 1);
 333         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 334         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 335         udelay(1);
 336         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 337         b43_nphy_bmac_clock_fgc(dev, 0);
 338         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 339 }
 340
 341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 342 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 343 {
 344         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 345
 346         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 347         if (preamble == 1)
 348                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 349         else
 350                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 351
 352         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 353 }
 354
 355 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 356 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 357 {
 358         struct b43_phy_n *nphy = dev->phy.n;
 359
 360         bool override = false;
 361         u16 chain = 0x33;
 362
 363         if (nphy->txrx_chain == 0) {
 364                 chain = 0x11;
 365                 override = true;
 366         } else if (nphy->txrx_chain == 1) {
 367                 chain = 0x22;
 368                 override = true;
 369         }
 370
 371         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 372                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 373                         chain);
 374
 375         if (override)
 376                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 377                                 B43_NPHY_RFSEQMODE_CAOVER);
 378         else
 379                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 380                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 381 }
 382
 383 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 384 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 385                                 u16 samps, u8 time, bool wait)
 386 {
 387         int i;
 388         u16 tmp;
 389
 390         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 391         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 392         if (wait)
 393                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 394         else
 395                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 396
 397         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 398
 399         for (i = 1000; i; i--) {
 400                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 401                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 402                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 403                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 404                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 405                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 406                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 407                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 408
 409                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 410                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 411                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 412                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 413                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 414                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 415                         return;
 416                 }
 417                 udelay(10);
 418         }
 419         memset(est, 0, sizeof(*est));
 420 }
 421
 422 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 423 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 424                                         struct b43_phy_n_iq_comp *pcomp)
 425 {
 426         if (write) {
 427                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 428                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 429                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 430                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 431         } else {
 432                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 433                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 434                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 435                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 436         }
 437 }
 438
 439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 440 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 441 {
 442         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 443
 444         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 445         if (core == 0) {
 446                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 447                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 448         } else {
 449                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 450                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 451         }
 452         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 453         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 454         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 455         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 456         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 457         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 458         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 459         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 460 }
 461
 462 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 463 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 464 {
 465         u8 rxval, txval;
 466         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 467
 468         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 469         if (core == 0) {
 470                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 471                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 472         } else {
 473                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 474                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 475         }
 476         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 477         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 478         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 479         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 480         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 481         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 482         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 483         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 484
 485         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 486         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 487
 488         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 489                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 490         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 491                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 492         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 493                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 494         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 495                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 496
 497         if (core == 0) {
 498                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 499                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 500         } else {
 501                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 502                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 503         }
 504
 505         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 506         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 507         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 508
 509         if (core == 0) {
 510                 rxval = 1;
 511                 txval = 8;
 512         } else {
 513                 rxval = 4;
 514                 txval = 2;
 515         }
 516         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 517         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 518 }
 519
 520 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 521 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 522 {
 523         int i;
 524         s32 iq;
 525         u32 ii;
 526         u32 qq;
 527         int iq_nbits, qq_nbits;
 528         int arsh, brsh;
 529         u16 tmp, a, b;
 530
 531         struct nphy_iq_est est;
 532         struct b43_phy_n_iq_comp old;
 533         struct b43_phy_n_iq_comp new = { };
 534         bool error = false;
 535
 536         if (mask == 0)
 537                 return;
 538
 539         b43_nphy_rx_iq_coeffs(dev, false, &old);
 540         b43_nphy_rx_iq_coeffs(dev, true, &new);
 541         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 542         new = old;
 543
 544         for (i = 0; i < 2; i++) {
 545                 if (i == 0 && (mask & 1)) {
 546                         iq = est.iq0_prod;
 547                         ii = est.i0_pwr;
 548                         qq = est.q0_pwr;
 549                 } else if (i == 1 && (mask & 2)) {
 550                         iq = est.iq1_prod;
 551                         ii = est.i1_pwr;
 552                         qq = est.q1_pwr;
 553                 } else {
 554                         B43_WARN_ON(1);
 555                         continue;
 556                 }
 557
 558                 if (ii + qq < 2) {
 559                         error = true;
 560                         break;
 561                 }
 562
 563                 iq_nbits = fls(abs(iq));
 564                 qq_nbits = fls(qq);
 565
 566                 arsh = iq_nbits - 20;
 567                 if (arsh >= 0) {
 568                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 569                         tmp = ii >> arsh;
 570                 } else {
 571                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 572                         tmp = ii << -arsh;
 573                 }
 574                 if (tmp == 0) {
 575                         error = true;
 576                         break;
 577                 }
 578                 a /= tmp;
 579
 580                 brsh = qq_nbits - 11;
 581                 if (brsh >= 0) {
 582                         b = (qq << (31 - qq_nbits));
 583                         tmp = ii >> brsh;
 584                 } else {
 585                         b = (qq << (31 - qq_nbits));
 586                         tmp = ii << -brsh;
 587                 }
 588                 if (tmp == 0) {
 589                         error = true;
 590                         break;
 591                 }
 592                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 593
 594                 if (i == 0 && (mask & 0x1)) {
 595                         if (dev->phy.rev >= 3) {
 596                                 new.a0 = a & 0x3FF;
 597                                 new.b0 = b & 0x3FF;
 598                         } else {
 599                                 new.a0 = b & 0x3FF;
 600                                 new.b0 = a & 0x3FF;
 601                         }
 602                 } else if (i == 1 && (mask & 0x2)) {
 603                         if (dev->phy.rev >= 3) {
 604                                 new.a1 = a & 0x3FF;
 605                                 new.b1 = b & 0x3FF;
 606                         } else {
 607                                 new.a1 = b & 0x3FF;
 608                                 new.b1 = a & 0x3FF;
 609                         }
 610                 }
 611         }
 612
 613         if (error)
 614                 new = old;
 615
 616         b43_nphy_rx_iq_coeffs(dev, true, &new);
 617 }
 618
 619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 620 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 621 {
 622         u16 array[4];
 623         int i;
 624
 625         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 626         for (i = 0; i < 4; i++)
 627                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 628
 629         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 630         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 631         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 632         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 633 }
 634
 635 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 636 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 637 {
 638         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 639         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 640 }
 641
 642 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 643 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 644 {
 645         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 646         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 647 }
 648
 649 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 650 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 651 {
 652         u16 tmp;
 653
 654         if (dev->dev->id.revision == 16)
 655                 b43_mac_suspend(dev);
 656
 657         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 658         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 659                 B43_NPHY_CLASSCTL_WAITEDEN);
 660         tmp &= ~mask;
 661         tmp |= (val & mask);
 662         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 663
 664         if (dev->dev->id.revision == 16)
 665                 b43_mac_enable(dev);
 666
 667         return tmp;
 668 }
 669
 670 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 671 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 672 {
 673         struct b43_phy *phy = &dev->phy;
 674         struct b43_phy_n *nphy = phy->n;
 675
 676         if (enable) {
 677                 u16 clip[] = { 0xFFFF, 0xFFFF };
 678                 if (nphy->deaf_count++ == 0) {
 679                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 680                         b43_nphy_classifier(dev, 0x7, 0);
 681                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 682                         b43_nphy_write_clip_detection(dev, clip);
 683                 }
 684                 b43_nphy_reset_cca(dev);
 685         } else {
 686                 if (--nphy->deaf_count == 0) {
 687                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 688                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 689                 }
 690         }
 691 }
 692
 693 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 694 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 695 {
 696         struct b43_phy_n *nphy = dev->phy.n;
 697         u16 tmp;
 698
 699         if (nphy->hang_avoid)
 700                 b43_nphy_stay_in_carrier_search(dev, 1);
 701
 702         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 703         if (tmp & 0x1)
 704                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 705         else if (tmp & 0x2)
 706                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 707
 708         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 709
 710         if (nphy->bb_mult_save & 0x80000000) {
 711                 tmp = nphy->bb_mult_save & 0xFFFF;
 712                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 713                 nphy->bb_mult_save = 0;
 714         }
 715
 716         if (nphy->hang_avoid)
 717                 b43_nphy_stay_in_carrier_search(dev, 0);
 718 }
 719
 720 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 721 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 722 {
 723         struct b43_phy_n *nphy = dev->phy.n;
 724
 725         unsigned int channel;
 726         int tone[2] = { 57, 58 };
 727         u32 noise[2] = { 0x3FF, 0x3FF };
 728
 729         B43_WARN_ON(dev->phy.rev < 3);
 730
 731         if (nphy->hang_avoid)
 732                 b43_nphy_stay_in_carrier_search(dev, 1);
 733
 734         /* FIXME: channel = radio_chanspec */
 735
 736         if (nphy->gband_spurwar_en) {
 737                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 738                 if (channel == 11 && dev->phy.is_40mhz)
 739                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 740                 else
 741                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 742                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 743         }
 744
 745         if (nphy->aband_spurwar_en) {
 746                 if (channel == 54) {
 747                         tone[0] = 0x20;
 748                         noise[0] = 0x25F;
 749                 } else if (channel == 38 || channel == 102 || channel == 118) {
 750                         if (0 /* FIXME */) {
 751                                 tone[0] = 0x20;
 752                                 noise[0] = 0x21F;
 753                         } else {
 754                                 tone[0] = 0;
 755                                 noise[0] = 0;
 756                         }
 757                 } else if (channel == 134) {
 758                         tone[0] = 0x20;
 759                         noise[0] = 0x21F;
 760                 } else if (channel == 151) {
 761                         tone[0] = 0x10;
 762                         noise[0] = 0x23F;
 763                 } else if (channel == 153 || channel == 161) {
 764                         tone[0] = 0x30;
 765                         noise[0] = 0x23F;
 766                 } else {
 767                         tone[0] = 0;
 768                         noise[0] = 0;
 769                 }
 770
 771                 if (!tone[0] && !noise[0])
 772                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 773                 else
 774                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 775         }
 776
 777         if (nphy->hang_avoid)
 778                 b43_nphy_stay_in_carrier_search(dev, 0);
 779 }
 780
 781 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 782 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
 783 {
 784         struct b43_phy_n *nphy = dev->phy.n;
 785         u8 i, j;
 786         u8 code;
 787
 788         /* TODO: for PHY >= 3
 789         s8 *lna1_gain, *lna2_gain;
 790         u8 *gain_db, *gain_bits;
 791         u16 *rfseq_init;
 792         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 793         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 794         */
 795
 796         u8 rfseq_events[3] = { 6, 8, 7 };
 797         u8 rfseq_delays[3] = { 10, 30, 1 };
 798
 799         if (dev->phy.rev >= 3) {
 800                 /* TODO */
 801         } else {
 802                 /* Set Clip 2 detect */
 803                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 804                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 805                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 806                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 807
 808                 /* Set narrowband clip threshold */
 809                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 810                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 811
 812                 if (!dev->phy.is_40mhz) {
 813                         /* Set dwell lengths */
 814                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 815                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 816                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 817                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 818                 }
 819
 820                 /* Set wideband clip 2 threshold */
 821                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 822                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 823                                 21);
 824                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 825                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 826                                 21);
 827
 828                 if (!dev->phy.is_40mhz) {
 829                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 830                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 831                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 832                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 833                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 834                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 835                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 836                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 837                 }
 838
 839                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 840
 841                 if (nphy->gain_boost) {
 842                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 843                             dev->phy.is_40mhz)
 844                                 code = 4;
 845                         else
 846                                 code = 5;
 847                 } else {
 848                         code = dev->phy.is_40mhz ? 6 : 7;
 849                 }
 850
 851                 /* Set HPVGA2 index */
 852                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 853                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 854                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 855                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 856                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 857                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 858
 859                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 860                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 861                                         (code << 8 | 0x7C));
 862                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 863                                         (code << 8 | 0x7C));
 864
 865                 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
 866
 867                 if (nphy->elna_gain_config) {
 868                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 869                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 870                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 871                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 872                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 873
 874                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 875                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 876                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 877                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 878                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 879
 880                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 881                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 882                                         (code << 8 | 0x74));
 883                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 884                                         (code << 8 | 0x74));
 885                 }
 886
 887                 if (dev->phy.rev == 2) {
 888                         for (i = 0; i < 4; i++) {
 889                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 890                                                 (0x0400 * i) + 0x0020);
 891                                 for (j = 0; j < 21; j++)
 892                                         b43_phy_write(dev,
 893                                                 B43_NPHY_TABLE_DATALO, 3 * j);
 894                         }
 895
 896                         b43_nphy_set_rf_sequence(dev, 5,
 897                                         rfseq_events, rfseq_delays, 3);
 898                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
 899                                 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
 900                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
 901
 902                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 903                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
 904                                                 0xFF80, 4);
 905                 }
 906         }
 907 }
 908
 909 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
 910 static void b43_nphy_workarounds(struct b43_wldev *dev)
 911 {
 912         struct ssb_bus *bus = dev->dev->bus;
 913         struct b43_phy *phy = &dev->phy;
 914         struct b43_phy_n *nphy = phy->n;
 915
 916         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
 917         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
 918
 919         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
 920         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
 921
 922         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 923                 b43_nphy_classifier(dev, 1, 0);
 924         else
 925                 b43_nphy_classifier(dev, 1, 1);
 926
 927         if (nphy->hang_avoid)
 928                 b43_nphy_stay_in_carrier_search(dev, 1);
 929
 930         b43_phy_set(dev, B43_NPHY_IQFLIP,
 931                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 932
 933         if (dev->phy.rev >= 3) {
 934                 /* TODO */
 935         } else {
 936                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
 937                     nphy->band5g_pwrgain) {
 938                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
 939                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
 940                 } else {
 941                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 942                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
 943                 }
 944
 945                 /* TODO: convert to b43_ntab_write? */
 946                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
 947                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 948                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
 949                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 950                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
 951                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 952                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
 953                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 954
 955                 if (dev->phy.rev < 2) {
 956                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
 957                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 958                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
 959                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 960                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
 961                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 962                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
 963                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 964                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
 965                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
 966                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
 967                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
 968                 }
 969
 970                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 971                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 972                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 973                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 974
 975                 if (bus->sprom.boardflags2_lo & 0x100 &&
 976                     bus->boardinfo.type == 0x8B) {
 977                         delays1[0] = 0x1;
 978                         delays1[5] = 0x14;
 979                 }
 980                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
 981                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
 982
 983                 b43_nphy_gain_crtl_workarounds(dev);
 984
 985                 if (dev->phy.rev < 2) {
 986                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
 987                                 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
 988                 } else if (dev->phy.rev == 2) {
 989                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
 990                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
 991                 }
 992
 993                 if (dev->phy.rev < 2)
 994                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 995                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
 996
 997                 /* Set phase track alpha and beta */
 998                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 999                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1000                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1001                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1002                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1003                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1004
1005                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1006                                 (u16)~B43_NPHY_PIL_DW_64QAM);
1007                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1008                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1009                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1010
1011                 if (dev->phy.rev == 2)
1012                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1013                                         B43_NPHY_FINERX2_CGC_DECGC);
1014         }
1015
1016         if (nphy->hang_avoid)
1017                 b43_nphy_stay_in_carrier_search(dev, 0);
1018 }
1019
1020 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1021 static int b43_nphy_load_samples(struct b43_wldev *dev,
1022                                         struct b43_c32 *samples, u16 len) {
1023         struct b43_phy_n *nphy = dev->phy.n;
1024         u16 i;
1025         u32 *data;
1026
1027         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1028         if (!data) {
1029                 b43err(dev->wl, "allocation for samples loading failed\n");
1030                 return -ENOMEM;
1031         }
1032         if (nphy->hang_avoid)
1033                 b43_nphy_stay_in_carrier_search(dev, 1);
1034
1035         for (i = 0; i < len; i++) {
1036                 data[i] = (samples[i].i & 0x3FF << 10);
1037                 data[i] |= samples[i].q & 0x3FF;
1038         }
1039         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1040
1041         kfree(data);
1042         if (nphy->hang_avoid)
1043                 b43_nphy_stay_in_carrier_search(dev, 0);
1044         return 0;
1045 }
1046
1047 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1048 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1049                                         bool test)
1050 {
1051         int i;
1052         u16 bw, len, rot, angle;
1053         struct b43_c32 *samples;
1054
1055
1056         bw = (dev->phy.is_40mhz) ? 40 : 20;
1057         len = bw << 3;
1058
1059         if (test) {
1060                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1061                         bw = 82;
1062                 else
1063                         bw = 80;
1064
1065                 if (dev->phy.is_40mhz)
1066                         bw <<= 1;
1067
1068                 len = bw << 1;
1069         }
1070
1071         samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1072         if (!samples) {
1073                 b43err(dev->wl, "allocation for samples generation failed\n");
1074                 return 0;
1075         }
1076         rot = (((freq * 36) / bw) << 16) / 100;
1077         angle = 0;
1078
1079         for (i = 0; i < len; i++) {
1080                 samples[i] = b43_cordic(angle);
1081                 angle += rot;
1082                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1083                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1084         }
1085
1086         i = b43_nphy_load_samples(dev, samples, len);
1087         kfree(samples);
1088         return (i < 0) ? 0 : len;
1089 }
1090
1091 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1092 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1093                                         u16 wait, bool iqmode, bool dac_test)
1094 {
1095         struct b43_phy_n *nphy = dev->phy.n;
1096         int i;
1097         u16 seq_mode;
1098         u32 tmp;
1099
1100         if (nphy->hang_avoid)
1101                 b43_nphy_stay_in_carrier_search(dev, true);
1102
1103         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1104                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1105                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1106         }
1107
1108         if (!dev->phy.is_40mhz)
1109                 tmp = 0x6464;
1110         else
1111                 tmp = 0x4747;
1112         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1113
1114         if (nphy->hang_avoid)
1115                 b43_nphy_stay_in_carrier_search(dev, false);
1116
1117         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1118
1119         if (loops != 0xFFFF)
1120                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1121         else
1122                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1123
1124         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1125
1126         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1127
1128         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1129         if (iqmode) {
1130                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1131                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1132         } else {
1133                 if (dac_test)
1134                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1135                 else
1136                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1137         }
1138         for (i = 0; i < 100; i++) {
1139                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1140                         i = 0;
1141                         break;
1142                 }
1143                 udelay(10);
1144         }
1145         if (i)
1146                 b43err(dev->wl, "run samples timeout\n");
1147
1148         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1149 }
1150
1151 /*
1152  * Transmits a known value for LO calibration
1153  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1154  */
1155 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1156                                 bool iqmode, bool dac_test)
1157 {
1158         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1159         if (samp == 0)
1160                 return -1;
1161         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1162         return 0;
1163 }
1164
1165 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1166 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1167 {
1168         struct b43_phy_n *nphy = dev->phy.n;
1169         int i, j;
1170         u32 tmp;
1171         u32 cur_real, cur_imag, real_part, imag_part;
1172
1173         u16 buffer[7];
1174
1175         if (nphy->hang_avoid)
1176                 b43_nphy_stay_in_carrier_search(dev, true);
1177
1178         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1179
1180         for (i = 0; i < 2; i++) {
1181                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1182                         (buffer[i * 2 + 1] & 0x3FF);
1183                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1184                                 (((i + 26) << 10) | 320));
1185                 for (j = 0; j < 128; j++) {
1186                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1187                                         ((tmp >> 16) & 0xFFFF));
1188                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1189                                         (tmp & 0xFFFF));
1190                 }
1191         }
1192
1193         for (i = 0; i < 2; i++) {
1194                 tmp = buffer[5 + i];
1195                 real_part = (tmp >> 8) & 0xFF;
1196                 imag_part = (tmp & 0xFF);
1197                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1198                                 (((i + 26) << 10) | 448));
1199
1200                 if (dev->phy.rev >= 3) {
1201                         cur_real = real_part;
1202                         cur_imag = imag_part;
1203                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1204                 }
1205
1206                 for (j = 0; j < 128; j++) {
1207                         if (dev->phy.rev < 3) {
1208                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1209                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1210                                 tmp = ((cur_real & 0xFF) << 8) |
1211                                         (cur_imag & 0xFF);
1212                         }
1213                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1214                                         ((tmp >> 16) & 0xFFFF));
1215                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1216                                         (tmp & 0xFFFF));
1217                 }
1218         }
1219
1220         if (dev->phy.rev >= 3) {
1221                 b43_shm_write16(dev, B43_SHM_SHARED,
1222                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1223                 b43_shm_write16(dev, B43_SHM_SHARED,
1224                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1225         }
1226
1227         if (nphy->hang_avoid)
1228                 b43_nphy_stay_in_carrier_search(dev, false);
1229 }
1230
1231 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1232 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1233                                         u8 *events, u8 *delays, u8 length)
1234 {
1235         struct b43_phy_n *nphy = dev->phy.n;
1236         u8 i;
1237         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1238         u16 offset1 = cmd << 4;
1239         u16 offset2 = offset1 + 0x80;
1240
1241         if (nphy->hang_avoid)
1242                 b43_nphy_stay_in_carrier_search(dev, true);
1243
1244         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1245         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1246
1247         for (i = length; i < 16; i++) {
1248                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1249                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1250         }
1251
1252         if (nphy->hang_avoid)
1253                 b43_nphy_stay_in_carrier_search(dev, false);
1254 }
1255
1256 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1257 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1258                                        enum b43_nphy_rf_sequence seq)
1259 {
1260         static const u16 trigger[] = {
1261                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1262                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1263                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1264                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1265                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1266                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1267         };
1268         int i;
1269         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1270
1271         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1272
1273         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1274                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1275         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1276         for (i = 0; i < 200; i++) {
1277                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1278                         goto ok;
1279                 msleep(1);
1280         }
1281         b43err(dev->wl, "RF sequence status timeout\n");
1282 ok:
1283         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1284 }
1285
1286 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1287 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1288                                                 u16 value, u8 core, bool off)
1289 {
1290         int i;
1291         u8 index = fls(field);
1292         u8 addr, en_addr, val_addr;
1293         /* we expect only one bit set */
1294         B43_WARN_ON(field & (~(1 << (index - 1))));
1295
1296         if (dev->phy.rev >= 3) {
1297                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1298                 for (i = 0; i < 2; i++) {
1299                         if (index == 0 || index == 16) {
1300                                 b43err(dev->wl,
1301                                         "Unsupported RF Ctrl Override call\n");
1302                                 return;
1303                         }
1304
1305                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1306                         en_addr = B43_PHY_N((i == 0) ?
1307                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1308                         val_addr = B43_PHY_N((i == 0) ?
1309                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1310
1311                         if (off) {
1312                                 b43_phy_mask(dev, en_addr, ~(field));
1313                                 b43_phy_mask(dev, val_addr,
1314                                                 ~(rf_ctrl->val_mask));
1315                         } else {
1316                                 if (core == 0 || ((1 << core) & i) != 0) {
1317                                         b43_phy_set(dev, en_addr, field);
1318                                         b43_phy_maskset(dev, val_addr,
1319                                                 ~(rf_ctrl->val_mask),
1320                                                 (value << rf_ctrl->val_shift));
1321                                 }
1322                         }
1323                 }
1324         } else {
1325                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1326                 if (off) {
1327                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1328                         value = 0;
1329                 } else {
1330                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1331                 }
1332
1333                 for (i = 0; i < 2; i++) {
1334                         if (index <= 1 || index == 16) {
1335                                 b43err(dev->wl,
1336                                         "Unsupported RF Ctrl Override call\n");
1337                                 return;
1338                         }
1339
1340                         if (index == 2 || index == 10 ||
1341                             (index >= 13 && index <= 15)) {
1342                                 core = 1;
1343                         }
1344
1345                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1346                         addr = B43_PHY_N((i == 0) ?
1347                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1348
1349                         if ((core & (1 << i)) != 0)
1350                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1351                                                 (value << rf_ctrl->shift));
1352
1353                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1354                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1355                                         B43_NPHY_RFCTL_CMD_START);
1356                         udelay(1);
1357                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1358                 }
1359         }
1360 }
1361
1362 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1363 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1364                                                 u16 value, u8 core)
1365 {
1366         u8 i, j;
1367         u16 reg, tmp, val;
1368
1369         B43_WARN_ON(dev->phy.rev < 3);
1370         B43_WARN_ON(field > 4);
1371
1372         for (i = 0; i < 2; i++) {
1373                 if ((core == 1 && i == 1) || (core == 2 && !i))
1374                         continue;
1375
1376                 reg = (i == 0) ?
1377                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1378                 b43_phy_mask(dev, reg, 0xFBFF);
1379
1380                 switch (field) {
1381                 case 0:
1382                         b43_phy_write(dev, reg, 0);
1383                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1384                         break;
1385                 case 1:
1386                         if (!i) {
1387                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1388                                                 0xFC3F, (value << 6));
1389                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1390                                                 0xFFFE, 1);
1391                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1392                                                 B43_NPHY_RFCTL_CMD_START);
1393                                 for (j = 0; j < 100; j++) {
1394                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1395                                                 j = 0;
1396                                                 break;
1397                                         }
1398                                         udelay(10);
1399                                 }
1400                                 if (j)
1401                                         b43err(dev->wl,
1402                                                 "intc override timeout\n");
1403                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1404                                                 0xFFFE);
1405                         } else {
1406                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1407                                                 0xFC3F, (value << 6));
1408                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1409                                                 0xFFFE, 1);
1410                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1411                                                 B43_NPHY_RFCTL_CMD_RXTX);
1412                                 for (j = 0; j < 100; j++) {
1413                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1414                                                 j = 0;
1415                                                 break;
1416                                         }
1417                                         udelay(10);
1418                                 }
1419                                 if (j)
1420                                         b43err(dev->wl,
1421                                                 "intc override timeout\n");
1422                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1423                                                 0xFFFE);
1424                         }
1425                         break;
1426                 case 2:
1427                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1428                                 tmp = 0x0020;
1429                                 val = value << 5;
1430                         } else {
1431                                 tmp = 0x0010;
1432                                 val = value << 4;
1433                         }
1434                         b43_phy_maskset(dev, reg, ~tmp, val);
1435                         break;
1436                 case 3:
1437                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1438                                 tmp = 0x0001;
1439                                 val = value;
1440                         } else {
1441                                 tmp = 0x0004;
1442                                 val = value << 2;
1443                         }
1444                         b43_phy_maskset(dev, reg, ~tmp, val);
1445                         break;
1446                 case 4:
1447                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1448                                 tmp = 0x0002;
1449                                 val = value << 1;
1450                         } else {
1451                                 tmp = 0x0008;
1452                                 val = value << 3;
1453                         }
1454                         b43_phy_maskset(dev, reg, ~tmp, val);
1455                         break;
1456                 }
1457         }
1458 }
1459
1460 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1461 {
1462         unsigned int i;
1463         u16 val;
1464
1465         val = 0x1E1F;
1466         for (i = 0; i < 14; i++) {
1467                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1468                 val -= 0x202;
1469         }
1470         val = 0x3E3F;
1471         for (i = 0; i < 16; i++) {
1472                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1473                 val -= 0x202;
1474         }
1475         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1476 }
1477
1478 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1479 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1480                                        s8 offset, u8 core, u8 rail, u8 type)
1481 {
1482         u16 tmp;
1483         bool core1or5 = (core == 1) || (core == 5);
1484         bool core2or5 = (core == 2) || (core == 5);
1485
1486         offset = clamp_val(offset, -32, 31);
1487         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1488
1489         if (core1or5 && (rail == 0) && (type == 2))
1490                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1491         if (core1or5 && (rail == 1) && (type == 2))
1492                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1493         if (core2or5 && (rail == 0) && (type == 2))
1494                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1495         if (core2or5 && (rail == 1) && (type == 2))
1496                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1497         if (core1or5 && (rail == 0) && (type == 0))
1498                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1499         if (core1or5 && (rail == 1) && (type == 0))
1500                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1501         if (core2or5 && (rail == 0) && (type == 0))
1502                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1503         if (core2or5 && (rail == 1) && (type == 0))
1504                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1505         if (core1or5 && (rail == 0) && (type == 1))
1506                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1507         if (core1or5 && (rail == 1) && (type == 1))
1508                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1509         if (core2or5 && (rail == 0) && (type == 1))
1510                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1511         if (core2or5 && (rail == 1) && (type == 1))
1512                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1513         if (core1or5 && (rail == 0) && (type == 6))
1514                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1515         if (core1or5 && (rail == 1) && (type == 6))
1516                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1517         if (core2or5 && (rail == 0) && (type == 6))
1518                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1519         if (core2or5 && (rail == 1) && (type == 6))
1520                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1521         if (core1or5 && (rail == 0) && (type == 3))
1522                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1523         if (core1or5 && (rail == 1) && (type == 3))
1524                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1525         if (core2or5 && (rail == 0) && (type == 3))
1526                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1527         if (core2or5 && (rail == 1) && (type == 3))
1528                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1529         if (core1or5 && (type == 4))
1530                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1531         if (core2or5 && (type == 4))
1532                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1533         if (core1or5 && (type == 5))
1534                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1535         if (core2or5 && (type == 5))
1536                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1537 }
1538
1539 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1540 {
1541         u16 val;
1542
1543         if (type < 3)
1544                 val = 0;
1545         else if (type == 6)
1546                 val = 1;
1547         else if (type == 3)
1548                 val = 2;
1549         else
1550                 val = 3;
1551
1552         val = (val << 12) | (val << 14);
1553         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1554         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1555
1556         if (type < 3) {
1557                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1558                                 (type + 1) << 4);
1559                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1560                                 (type + 1) << 4);
1561         }
1562
1563         /* TODO use some definitions */
1564         if (code == 0) {
1565                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1566                 if (type < 3) {
1567                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1568                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1569                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1570                         udelay(20);
1571                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1572                 }
1573         } else {
1574                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1575                                 0x3000);
1576                 if (type < 3) {
1577                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1578                                         0xFEC7, 0x0180);
1579                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1580                                         0xEFDC, (code << 1 | 0x1021));
1581                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1582                         udelay(20);
1583                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1584                 }
1585         }
1586 }
1587
1588 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1589 {
1590         struct b43_phy_n *nphy = dev->phy.n;
1591         u8 i;
1592         u16 reg, val;
1593
1594         if (code == 0) {
1595                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1596                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1597                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1598                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1599                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1600                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1601                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1602                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1603         } else {
1604                 for (i = 0; i < 2; i++) {
1605                         if ((code == 1 && i == 1) || (code == 2 && !i))
1606                                 continue;
1607
1608                         reg = (i == 0) ?
1609                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1610                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1611
1612                         if (type < 3) {
1613                                 reg = (i == 0) ?
1614                                         B43_NPHY_AFECTL_C1 :
1615                                         B43_NPHY_AFECTL_C2;
1616                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1617
1618                                 reg = (i == 0) ?
1619                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1620                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1621                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1622
1623                                 if (type == 0)
1624                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1625                                 else if (type == 1)
1626                                         val = 16;
1627                                 else
1628                                         val = 32;
1629                                 b43_phy_set(dev, reg, val);
1630
1631                                 reg = (i == 0) ?
1632                                         B43_NPHY_TXF_40CO_B1S0 :
1633                                         B43_NPHY_TXF_40CO_B32S1;
1634                                 b43_phy_set(dev, reg, 0x0020);
1635                         } else {
1636                                 if (type == 6)
1637                                         val = 0x0100;
1638                                 else if (type == 3)
1639                                         val = 0x0200;
1640                                 else
1641                                         val = 0x0300;
1642
1643                                 reg = (i == 0) ?
1644                                         B43_NPHY_AFECTL_C1 :
1645                                         B43_NPHY_AFECTL_C2;
1646
1647                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1648                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1649
1650                                 if (type != 3 && type != 6) {
1651                                         enum ieee80211_band band =
1652                                                 b43_current_band(dev->wl);
1653
1654                                         if ((nphy->ipa2g_on &&
1655                                                 band == IEEE80211_BAND_2GHZ) ||
1656                                                 (nphy->ipa5g_on &&
1657                                                 band == IEEE80211_BAND_5GHZ))
1658                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1659                                         else
1660                                                 val = 0x11;
1661                                         reg = (i == 0) ? 0x2000 : 0x3000;
1662                                         reg |= B2055_PADDRV;
1663                                         b43_radio_write16(dev, reg, val);
1664
1665                                         reg = (i == 0) ?
1666                                                 B43_NPHY_AFECTL_OVER1 :
1667                                                 B43_NPHY_AFECTL_OVER;
1668                                         b43_phy_set(dev, reg, 0x0200);
1669                                 }
1670                         }
1671                 }
1672         }
1673 }
1674
1675 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1676 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1677 {
1678         if (dev->phy.rev >= 3)
1679                 b43_nphy_rev3_rssi_select(dev, code, type);
1680         else
1681                 b43_nphy_rev2_rssi_select(dev, code, type);
1682 }
1683
1684 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1685 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1686 {
1687         int i;
1688         for (i = 0; i < 2; i++) {
1689                 if (type == 2) {
1690                         if (i == 0) {
1691                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1692                                                   0xFC, buf[0]);
1693                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1694                                                   0xFC, buf[1]);
1695                         } else {
1696                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1697                                                   0xFC, buf[2 * i]);
1698                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1699                                                   0xFC, buf[2 * i + 1]);
1700                         }
1701                 } else {
1702                         if (i == 0)
1703                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1704                                                   0xF3, buf[0] << 2);
1705                         else
1706                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1707                                                   0xF3, buf[2 * i + 1] << 2);
1708                 }
1709         }
1710 }
1711
1712 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1713 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1714                                 u8 nsamp)
1715 {
1716         int i;
1717         int out;
1718         u16 save_regs_phy[9];
1719         u16 s[2];
1720
1721         if (dev->phy.rev >= 3) {
1722                 save_regs_phy[0] = b43_phy_read(dev,
1723                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1724                 save_regs_phy[1] = b43_phy_read(dev,
1725                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1726                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1727                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1728                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1729                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1730                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1731                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1732         }
1733
1734         b43_nphy_rssi_select(dev, 5, type);
1735
1736         if (dev->phy.rev < 2) {
1737                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1738                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1739         }
1740
1741         for (i = 0; i < 4; i++)
1742                 buf[i] = 0;
1743
1744         for (i = 0; i < nsamp; i++) {
1745                 if (dev->phy.rev < 2) {
1746                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1747                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1748                 } else {
1749                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1750                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1751                 }
1752
1753                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1754                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1755                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1756                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1757         }
1758         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1759                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1760
1761         if (dev->phy.rev < 2)
1762                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1763
1764         if (dev->phy.rev >= 3) {
1765                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1766                                 save_regs_phy[0]);
1767                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1768                                 save_regs_phy[1]);
1769                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1770                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1771                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1772                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1773                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1774                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1775         }
1776
1777         return out;
1778 }
1779
1780 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1781 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1782 {
1783         int i, j;
1784         u8 state[4];
1785         u8 code, val;
1786         u16 class, override;
1787         u8 regs_save_radio[2];
1788         u16 regs_save_phy[2];
1789         s8 offset[4];
1790
1791         u16 clip_state[2];
1792         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1793         s32 results_min[4] = { };
1794         u8 vcm_final[4] = { };
1795         s32 results[4][4] = { };
1796         s32 miniq[4][2] = { };
1797
1798         if (type == 2) {
1799                 code = 0;
1800                 val = 6;
1801         } else if (type < 2) {
1802                 code = 25;
1803                 val = 4;
1804         } else {
1805                 B43_WARN_ON(1);
1806                 return;
1807         }
1808
1809         class = b43_nphy_classifier(dev, 0, 0);
1810         b43_nphy_classifier(dev, 7, 4);
1811         b43_nphy_read_clip_detection(dev, clip_state);
1812         b43_nphy_write_clip_detection(dev, clip_off);
1813
1814         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1815                 override = 0x140;
1816         else
1817                 override = 0x110;
1818
1819         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1820         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1821         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1822         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1823
1824         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1825         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1826         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1827         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1828
1829         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1830         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1831         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1832         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1833         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1834         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1835
1836         b43_nphy_rssi_select(dev, 5, type);
1837         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1838         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1839
1840         for (i = 0; i < 4; i++) {
1841                 u8 tmp[4];
1842                 for (j = 0; j < 4; j++)
1843                         tmp[j] = i;
1844                 if (type != 1)
1845                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1846                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1847                 if (type < 2)
1848                         for (j = 0; j < 2; j++)
1849                                 miniq[i][j] = min(results[i][2 * j],
1850                                                 results[i][2 * j + 1]);
1851         }
1852
1853         for (i = 0; i < 4; i++) {
1854                 s32 mind = 40;
1855                 u8 minvcm = 0;
1856                 s32 minpoll = 249;
1857                 s32 curr;
1858                 for (j = 0; j < 4; j++) {
1859                         if (type == 2)
1860                                 curr = abs(results[j][i]);
1861                         else
1862                                 curr = abs(miniq[j][i / 2] - code * 8);
1863
1864                         if (curr < mind) {
1865                                 mind = curr;
1866                                 minvcm = j;
1867                         }
1868
1869                         if (results[j][i] < minpoll)
1870                                 minpoll = results[j][i];
1871                 }
1872                 results_min[i] = minpoll;
1873                 vcm_final[i] = minvcm;
1874         }
1875
1876         if (type != 1)
1877                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1878
1879         for (i = 0; i < 4; i++) {
1880                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1881
1882                 if (offset[i] < 0)
1883                         offset[i] = -((abs(offset[i]) + 4) / 8);
1884                 else
1885                         offset[i] = (offset[i] + 4) / 8;
1886
1887                 if (results_min[i] == 248)
1888                         offset[i] = code - 32;
1889
1890                 if (i % 2 == 0)
1891                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1892                                                         type);
1893                 else
1894                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1895                                                         type);
1896         }
1897
1898         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1899         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1900
1901         switch (state[2]) {
1902         case 1:
1903                 b43_nphy_rssi_select(dev, 1, 2);
1904                 break;
1905         case 4:
1906                 b43_nphy_rssi_select(dev, 1, 0);
1907                 break;
1908         case 2:
1909                 b43_nphy_rssi_select(dev, 1, 1);
1910                 break;
1911         default:
1912                 b43_nphy_rssi_select(dev, 1, 1);
1913                 break;
1914         }
1915
1916         switch (state[3]) {
1917         case 1:
1918                 b43_nphy_rssi_select(dev, 2, 2);
1919                 break;
1920         case 4:
1921                 b43_nphy_rssi_select(dev, 2, 0);
1922                 break;
1923         default:
1924                 b43_nphy_rssi_select(dev, 2, 1);
1925                 break;
1926         }
1927
1928         b43_nphy_rssi_select(dev, 0, type);
1929
1930         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1931         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1932         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1933         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1934
1935         b43_nphy_classifier(dev, 7, class);
1936         b43_nphy_write_clip_detection(dev, clip_state);
1937 }
1938
1939 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1940 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1941 {
1942         /* TODO */
1943 }
1944
1945 /*
1946  * RSSI Calibration
1947  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1948  */
1949 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1950 {
1951         if (dev->phy.rev >= 3) {
1952                 b43_nphy_rev3_rssi_cal(dev);
1953         } else {
1954                 b43_nphy_rev2_rssi_cal(dev, 2);
1955                 b43_nphy_rev2_rssi_cal(dev, 0);
1956                 b43_nphy_rev2_rssi_cal(dev, 1);
1957         }
1958 }
1959
1960 /*
1961  * Restore RSSI Calibration
1962  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1963  */
1964 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1965 {
1966         struct b43_phy_n *nphy = dev->phy.n;
1967
1968         u16 *rssical_radio_regs = NULL;
1969         u16 *rssical_phy_regs = NULL;
1970
1971         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1972                 if (!nphy->rssical_chanspec_2G)
1973                         return;
1974                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1975                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1976         } else {
1977                 if (!nphy->rssical_chanspec_5G)
1978                         return;
1979                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1980                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1981         }
1982
1983         /* TODO use some definitions */
1984         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1985         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1986
1987         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1988         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1989         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1990         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1991
1992         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1993         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1994         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1995         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1996
1997         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1998         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1999         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2000         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2001 }
2002
2003 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2004 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2005 {
2006         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2007                 if (dev->phy.rev >= 6) {
2008                         /* TODO If the chip is 47162
2009                                 return txpwrctrl_tx_gain_ipa_rev5 */
2010                         return txpwrctrl_tx_gain_ipa_rev6;
2011                 } else if (dev->phy.rev >= 5) {
2012                         return txpwrctrl_tx_gain_ipa_rev5;
2013                 } else {
2014                         return txpwrctrl_tx_gain_ipa;
2015                 }
2016         } else {
2017                 return txpwrctrl_tx_gain_ipa_5g;
2018         }
2019 }
2020
2021 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2022 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2023 {
2024         struct b43_phy_n *nphy = dev->phy.n;
2025         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2026         u16 tmp;
2027         u8 offset, i;
2028
2029         if (dev->phy.rev >= 3) {
2030             for (i = 0; i < 2; i++) {
2031                 tmp = (i == 0) ? 0x2000 : 0x3000;
2032                 offset = i * 11;
2033
2034                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2035                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2036                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2037                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2038                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2039                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2040                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2041                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2042                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2043                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2044                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2045
2046                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2047                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2048                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2049                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2050                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2051                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2052                         if (nphy->ipa5g_on) {
2053                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2054                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2055                         } else {
2056                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2057                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2058                         }
2059                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2060                 } else {
2061                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2062                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2063                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2064                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2065                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2066                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2067                         if (nphy->ipa2g_on) {
2068                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2069                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2070                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2071                         } else {
2072                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2073                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2074                         }
2075                 }
2076                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2077                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2078                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2079             }
2080         } else {
2081                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2082                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2083
2084                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2085                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2086
2087                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2088                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2089
2090                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2091                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2092
2093                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2094                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2095
2096                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2097                     B43_NPHY_BANDCTL_5GHZ)) {
2098                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2099                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2100                 } else {
2101                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2102                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2103                 }
2104
2105                 if (dev->phy.rev < 2) {
2106                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2107                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2108                 } else {
2109                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2110                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2111                 }
2112         }
2113 }
2114
2115 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2116 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2117                                         struct nphy_txgains target,
2118                                         struct nphy_iqcal_params *params)
2119 {
2120         int i, j, indx;
2121         u16 gain;
2122
2123         if (dev->phy.rev >= 3) {
2124                 params->txgm = target.txgm[core];
2125                 params->pga = target.pga[core];
2126                 params->pad = target.pad[core];
2127                 params->ipa = target.ipa[core];
2128                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2129                                         (params->pad << 4) | (params->ipa);
2130                 for (j = 0; j < 5; j++)
2131                         params->ncorr[j] = 0x79;
2132         } else {
2133                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2134                         (target.txgm[core] << 8);
2135
2136                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2137                         1 : 0;
2138                 for (i = 0; i < 9; i++)
2139                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2140                                 break;
2141                 i = min(i, 8);
2142
2143                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2144                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2145                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2146                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2147                                         (params->pad << 2);
2148                 for (j = 0; j < 4; j++)
2149                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2150         }
2151 }
2152
2153 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2154 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2155 {
2156         struct b43_phy_n *nphy = dev->phy.n;
2157         int i;
2158         u16 scale, entry;
2159
2160         u16 tmp = nphy->txcal_bbmult;
2161         if (core == 0)
2162                 tmp >>= 8;
2163         tmp &= 0xff;
2164
2165         for (i = 0; i < 18; i++) {
2166                 scale = (ladder_lo[i].percent * tmp) / 100;
2167                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2168                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2169
2170                 scale = (ladder_iq[i].percent * tmp) / 100;
2171                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2172                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2173         }
2174 }
2175
2176 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2177 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2178 {
2179         int i;
2180         for (i = 0; i < 15; i++)
2181                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2182                                 tbl_tx_filter_coef_rev4[2][i]);
2183 }
2184
2185 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2186 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2187 {
2188         int i, j;
2189         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2190         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2191
2192         for (i = 0; i < 3; i++)
2193                 for (j = 0; j < 15; j++)
2194                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2195                                         tbl_tx_filter_coef_rev4[i][j]);
2196
2197         if (dev->phy.is_40mhz) {
2198                 for (j = 0; j < 15; j++)
2199                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2200                                         tbl_tx_filter_coef_rev4[3][j]);
2201         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2202                 for (j = 0; j < 15; j++)
2203                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2204                                         tbl_tx_filter_coef_rev4[5][j]);
2205         }
2206
2207         if (dev->phy.channel == 14)
2208                 for (j = 0; j < 15; j++)
2209                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2210                                         tbl_tx_filter_coef_rev4[6][j]);
2211 }
2212
2213 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2214 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2215 {
2216         struct b43_phy_n *nphy = dev->phy.n;
2217
2218         u16 curr_gain[2];
2219         struct nphy_txgains target;
2220         const u32 *table = NULL;
2221
2222         if (nphy->txpwrctrl == 0) {
2223                 int i;
2224
2225                 if (nphy->hang_avoid)
2226                         b43_nphy_stay_in_carrier_search(dev, true);
2227                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2228                 if (nphy->hang_avoid)
2229                         b43_nphy_stay_in_carrier_search(dev, false);
2230
2231                 for (i = 0; i < 2; ++i) {
2232                         if (dev->phy.rev >= 3) {
2233                                 target.ipa[i] = curr_gain[i] & 0x000F;
2234                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2235                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2236                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2237                         } else {
2238                                 target.ipa[i] = curr_gain[i] & 0x0003;
2239                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2240                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2241                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2242                         }
2243                 }
2244         } else {
2245                 int i;
2246                 u16 index[2];
2247                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2248                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2249                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2250                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2251                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2252                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2253
2254                 for (i = 0; i < 2; ++i) {
2255                         if (dev->phy.rev >= 3) {
2256                                 enum ieee80211_band band =
2257                                         b43_current_band(dev->wl);
2258
2259                                 if ((nphy->ipa2g_on &&
2260                                      band == IEEE80211_BAND_2GHZ) ||
2261                                     (nphy->ipa5g_on &&
2262                                      band == IEEE80211_BAND_5GHZ)) {
2263                                         table = b43_nphy_get_ipa_gain_table(dev);
2264                                 } else {
2265                                         if (band == IEEE80211_BAND_5GHZ) {
2266                                                 if (dev->phy.rev == 3)
2267                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2268                                                 else if (dev->phy.rev == 4)
2269                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2270                                                 else
2271                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2272                                         } else {
2273                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2274                                         }
2275                                 }
2276
2277                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2278                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2279                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2280                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2281                         } else {
2282                                 table = b43_ntab_tx_gain_rev0_1_2;
2283
2284                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2285                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2286                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2287                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2288                         }
2289                 }
2290         }
2291
2292         return target;
2293 }
2294
2295 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2296 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2297 {
2298         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2299
2300         if (dev->phy.rev >= 3) {
2301                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2302                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2303                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2304                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2305                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2306                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2307                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2308                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2309                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2310                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2311                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2312                 b43_nphy_reset_cca(dev);
2313         } else {
2314                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2315                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2316                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2317                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2318                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2319                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2320                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2321         }
2322 }
2323
2324 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2325 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2326 {
2327         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2328         u16 tmp;
2329
2330         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2331         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2332         if (dev->phy.rev >= 3) {
2333                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2334                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2335
2336                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2337                 regs[2] = tmp;
2338                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2339
2340                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2341                 regs[3] = tmp;
2342                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2343
2344                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2345                 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2346
2347                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2348                 regs[5] = tmp;
2349                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2350
2351                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2352                 regs[6] = tmp;
2353                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2354                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2355                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2356
2357                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2358                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2359                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2360
2361                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2362                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2363                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2364                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2365         } else {
2366                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2367                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2368                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2369                 regs[2] = tmp;
2370                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2371                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2372                 regs[3] = tmp;
2373                 tmp |= 0x2000;
2374                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2375                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2376                 regs[4] = tmp;
2377                 tmp |= 0x2000;
2378                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2379                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2380                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2381                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2382                         tmp = 0x0180;
2383                 else
2384                         tmp = 0x0120;
2385                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2386                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2387         }
2388 }
2389
2390 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2391 static void b43_nphy_save_cal(struct b43_wldev *dev)
2392 {
2393         struct b43_phy_n *nphy = dev->phy.n;
2394
2395         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2396         u16 *txcal_radio_regs = NULL;
2397         u8 *iqcal_chanspec;
2398         u16 *table = NULL;
2399
2400         if (nphy->hang_avoid)
2401                 b43_nphy_stay_in_carrier_search(dev, 1);
2402
2403         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2404                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2405                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2406                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2407                 table = nphy->cal_cache.txcal_coeffs_2G;
2408         } else {
2409                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2410                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2411                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2412                 table = nphy->cal_cache.txcal_coeffs_5G;
2413         }
2414
2415         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2416         /* TODO use some definitions */
2417         if (dev->phy.rev >= 3) {
2418                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2419                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2420                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2421                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2422                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2423                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2424                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2425                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2426         } else {
2427                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2428                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2429                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2430                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2431         }
2432         *iqcal_chanspec = nphy->radio_chanspec;
2433         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2434
2435         if (nphy->hang_avoid)
2436                 b43_nphy_stay_in_carrier_search(dev, 0);
2437 }
2438
2439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2440 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2441 {
2442         struct b43_phy_n *nphy = dev->phy.n;
2443
2444         u16 coef[4];
2445         u16 *loft = NULL;
2446         u16 *table = NULL;
2447
2448         int i;
2449         u16 *txcal_radio_regs = NULL;
2450         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2451
2452         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2453                 if (nphy->iqcal_chanspec_2G == 0)
2454                         return;
2455                 table = nphy->cal_cache.txcal_coeffs_2G;
2456                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2457         } else {
2458                 if (nphy->iqcal_chanspec_5G == 0)
2459                         return;
2460                 table = nphy->cal_cache.txcal_coeffs_5G;
2461                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2462         }
2463
2464         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2465
2466         for (i = 0; i < 4; i++) {
2467                 if (dev->phy.rev >= 3)
2468                         table[i] = coef[i];
2469                 else
2470                         coef[i] = 0;
2471         }
2472
2473         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2474         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2475         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2476
2477         if (dev->phy.rev < 2)
2478                 b43_nphy_tx_iq_workaround(dev);
2479
2480         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2481                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2482                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2483         } else {
2484                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2485                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2486         }
2487
2488         /* TODO use some definitions */
2489         if (dev->phy.rev >= 3) {
2490                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2491                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2492                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2493                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2494                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2495                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2496                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2497                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2498         } else {
2499                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2500                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2501                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2502                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2503         }
2504         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2505 }
2506
2507 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2508 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2509                                 struct nphy_txgains target,
2510                                 bool full, bool mphase)
2511 {
2512         struct b43_phy_n *nphy = dev->phy.n;
2513         int i;
2514         int error = 0;
2515         int freq;
2516         bool avoid = false;
2517         u8 length;
2518         u16 tmp, core, type, count, max, numb, last, cmd;
2519         const u16 *table;
2520         bool phy6or5x;
2521
2522         u16 buffer[11];
2523         u16 diq_start = 0;
2524         u16 save[2];
2525         u16 gain[2];
2526         struct nphy_iqcal_params params[2];
2527         bool updated[2] = { };
2528
2529         b43_nphy_stay_in_carrier_search(dev, true);
2530
2531         if (dev->phy.rev >= 4) {
2532                 avoid = nphy->hang_avoid;
2533                 nphy->hang_avoid = 0;
2534         }
2535
2536         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2537
2538         for (i = 0; i < 2; i++) {
2539                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2540                 gain[i] = params[i].cal_gain;
2541         }
2542
2543         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2544
2545         b43_nphy_tx_cal_radio_setup(dev);
2546         b43_nphy_tx_cal_phy_setup(dev);
2547
2548         phy6or5x = dev->phy.rev >= 6 ||
2549                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2550                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2551         if (phy6or5x) {
2552                 if (dev->phy.is_40mhz) {
2553                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2554                                         tbl_tx_iqlo_cal_loft_ladder_40);
2555                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2556                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2557                 } else {
2558                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2559                                         tbl_tx_iqlo_cal_loft_ladder_20);
2560                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2561                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2562                 }
2563         }
2564
2565         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2566
2567         if (!dev->phy.is_40mhz)
2568                 freq = 2500;
2569         else
2570                 freq = 5000;
2571
2572         if (nphy->mphase_cal_phase_id > 2)
2573                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2574                                         0xFFFF, 0, true, false);
2575         else
2576                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2577
2578         if (error == 0) {
2579                 if (nphy->mphase_cal_phase_id > 2) {
2580                         table = nphy->mphase_txcal_bestcoeffs;
2581                         length = 11;
2582                         if (dev->phy.rev < 3)
2583                                 length -= 2;
2584                 } else {
2585                         if (!full && nphy->txiqlocal_coeffsvalid) {
2586                                 table = nphy->txiqlocal_bestc;
2587                                 length = 11;
2588                                 if (dev->phy.rev < 3)
2589                                         length -= 2;
2590                         } else {
2591                                 full = true;
2592                                 if (dev->phy.rev >= 3) {
2593                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2594                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2595                                 } else {
2596                                         table = tbl_tx_iqlo_cal_startcoefs;
2597                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2598                                 }
2599                         }
2600                 }
2601
2602                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2603
2604                 if (full) {
2605                         if (dev->phy.rev >= 3)
2606                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2607                         else
2608                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2609                 } else {
2610                         if (dev->phy.rev >= 3)
2611                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2612                         else
2613                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2614                 }
2615
2616                 if (mphase) {
2617                         count = nphy->mphase_txcal_cmdidx;
2618                         numb = min(max,
2619                                 (u16)(count + nphy->mphase_txcal_numcmds));
2620                 } else {
2621                         count = 0;
2622                         numb = max;
2623                 }
2624
2625                 for (; count < numb; count++) {
2626                         if (full) {
2627                                 if (dev->phy.rev >= 3)
2628                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2629                                 else
2630                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2631                         } else {
2632                                 if (dev->phy.rev >= 3)
2633                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2634                                 else
2635                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2636                         }
2637
2638                         core = (cmd & 0x3000) >> 12;
2639                         type = (cmd & 0x0F00) >> 8;
2640
2641                         if (phy6or5x && updated[core] == 0) {
2642                                 b43_nphy_update_tx_cal_ladder(dev, core);
2643                                 updated[core] = 1;
2644                         }
2645
2646                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2647                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2648
2649                         if (type == 1 || type == 3 || type == 4) {
2650                                 buffer[0] = b43_ntab_read(dev,
2651                                                 B43_NTAB16(15, 69 + core));
2652                                 diq_start = buffer[0];
2653                                 buffer[0] = 0;
2654                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2655                                                 0);
2656                         }
2657
2658                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2659                         for (i = 0; i < 2000; i++) {
2660                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2661                                 if (tmp & 0xC000)
2662                                         break;
2663                                 udelay(10);
2664                         }
2665
2666                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2667                                                 buffer);
2668                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2669                                                 buffer);
2670
2671                         if (type == 1 || type == 3 || type == 4)
2672                                 buffer[0] = diq_start;
2673                 }
2674
2675                 if (mphase)
2676                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2677
2678                 last = (dev->phy.rev < 3) ? 6 : 7;
2679
2680                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2681                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2682                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2683                         if (dev->phy.rev < 3) {
2684                                 buffer[0] = 0;
2685                                 buffer[1] = 0;
2686                                 buffer[2] = 0;
2687                                 buffer[3] = 0;
2688                         }
2689                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2690                                                 buffer);
2691                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2692                                                 buffer);
2693                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2694                                                 buffer);
2695                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2696                                                 buffer);
2697                         length = 11;
2698                         if (dev->phy.rev < 3)
2699                                 length -= 2;
2700                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2701                                                 nphy->txiqlocal_bestc);
2702                         nphy->txiqlocal_coeffsvalid = true;
2703                         /* TODO: Set nphy->txiqlocal_chanspec to
2704                                 the current channel */
2705                 } else {
2706                         length = 11;
2707                         if (dev->phy.rev < 3)
2708                                 length -= 2;
2709                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2710                                                 nphy->mphase_txcal_bestcoeffs);
2711                 }
2712
2713                 b43_nphy_stop_playback(dev);
2714                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2715         }
2716
2717         b43_nphy_tx_cal_phy_cleanup(dev);
2718         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2719
2720         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2721                 b43_nphy_tx_iq_workaround(dev);
2722
2723         if (dev->phy.rev >= 4)
2724                 nphy->hang_avoid = avoid;
2725
2726         b43_nphy_stay_in_carrier_search(dev, false);
2727
2728         return error;
2729 }
2730
2731 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2732 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2733 {
2734         struct b43_phy_n *nphy = dev->phy.n;
2735         u8 i;
2736         u16 buffer[7];
2737         bool equal = true;
2738
2739         if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */)
2740                 return;
2741
2742         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2743         for (i = 0; i < 4; i++) {
2744                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2745                         equal = false;
2746                         break;
2747                 }
2748         }
2749
2750         if (!equal) {
2751                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2752                                         nphy->txiqlocal_bestc);
2753                 for (i = 0; i < 4; i++)
2754                         buffer[i] = 0;
2755                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2756                                         buffer);
2757                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2758                                         &nphy->txiqlocal_bestc[5]);
2759                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2760                                         &nphy->txiqlocal_bestc[5]);
2761         }
2762 }
2763
2764 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2765 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2766                         struct nphy_txgains target, u8 type, bool debug)
2767 {
2768         struct b43_phy_n *nphy = dev->phy.n;
2769         int i, j, index;
2770         u8 rfctl[2];
2771         u8 afectl_core;
2772         u16 tmp[6];
2773         u16 cur_hpf1, cur_hpf2, cur_lna;
2774         u32 real, imag;
2775         enum ieee80211_band band;
2776
2777         u8 use;
2778         u16 cur_hpf;
2779         u16 lna[3] = { 3, 3, 1 };
2780         u16 hpf1[3] = { 7, 2, 0 };
2781         u16 hpf2[3] = { 2, 0, 0 };
2782         u32 power[3] = { };
2783         u16 gain_save[2];
2784         u16 cal_gain[2];
2785         struct nphy_iqcal_params cal_params[2];
2786         struct nphy_iq_est est;
2787         int ret = 0;
2788         bool playtone = true;
2789         int desired = 13;
2790
2791         b43_nphy_stay_in_carrier_search(dev, 1);
2792
2793         if (dev->phy.rev < 2)
2794                 b43_nphy_reapply_tx_cal_coeffs(dev);
2795         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2796         for (i = 0; i < 2; i++) {
2797                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2798                 cal_gain[i] = cal_params[i].cal_gain;
2799         }
2800         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2801
2802         for (i = 0; i < 2; i++) {
2803                 if (i == 0) {
2804                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2805                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2806                         afectl_core = B43_NPHY_AFECTL_C1;
2807                 } else {
2808                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2809                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2810                         afectl_core = B43_NPHY_AFECTL_C2;
2811                 }
2812
2813                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2814                 tmp[2] = b43_phy_read(dev, afectl_core);
2815                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2816                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2817                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2818
2819                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2820                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2821                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2822                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2823                                 (1 - i));
2824                 b43_phy_set(dev, afectl_core, 0x0006);
2825                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2826
2827                 band = b43_current_band(dev->wl);
2828
2829                 if (nphy->rxcalparams & 0xFF000000) {
2830                         if (band == IEEE80211_BAND_5GHZ)
2831                                 b43_phy_write(dev, rfctl[0], 0x140);
2832                         else
2833                                 b43_phy_write(dev, rfctl[0], 0x110);
2834                 } else {
2835                         if (band == IEEE80211_BAND_5GHZ)
2836                                 b43_phy_write(dev, rfctl[0], 0x180);
2837                         else
2838                                 b43_phy_write(dev, rfctl[0], 0x120);
2839                 }
2840
2841                 if (band == IEEE80211_BAND_5GHZ)
2842                         b43_phy_write(dev, rfctl[1], 0x148);
2843                 else
2844                         b43_phy_write(dev, rfctl[1], 0x114);
2845
2846                 if (nphy->rxcalparams & 0x10000) {
2847                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2848                                         (i + 1));
2849                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2850                                         (2 - i));
2851                 }
2852
2853                 for (j = 0; i < 4; j++) {
2854                         if (j < 3) {
2855                                 cur_lna = lna[j];
2856                                 cur_hpf1 = hpf1[j];
2857                                 cur_hpf2 = hpf2[j];
2858                         } else {
2859                                 if (power[1] > 10000) {
2860                                         use = 1;
2861                                         cur_hpf = cur_hpf1;
2862                                         index = 2;
2863                                 } else {
2864                                         if (power[0] > 10000) {
2865                                                 use = 1;
2866                                                 cur_hpf = cur_hpf1;
2867                                                 index = 1;
2868                                         } else {
2869                                                 index = 0;
2870                                                 use = 2;
2871                                                 cur_hpf = cur_hpf2;
2872                                         }
2873                                 }
2874                                 cur_lna = lna[index];
2875                                 cur_hpf1 = hpf1[index];
2876                                 cur_hpf2 = hpf2[index];
2877                                 cur_hpf += desired - hweight32(power[index]);
2878                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2879                                 if (use == 1)
2880                                         cur_hpf1 = cur_hpf;
2881                                 else
2882                                         cur_hpf2 = cur_hpf;
2883                         }
2884
2885                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2886                                         (cur_lna << 2));
2887                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2888                                                                         false);
2889                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2890                         b43_nphy_stop_playback(dev);
2891
2892                         if (playtone) {
2893                                 ret = b43_nphy_tx_tone(dev, 4000,
2894                                                 (nphy->rxcalparams & 0xFFFF),
2895                                                 false, false);
2896                                 playtone = false;
2897                         } else {
2898                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2899                                                         false, false);
2900                         }
2901
2902                         if (ret == 0) {
2903                                 if (j < 3) {
2904                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2905                                                                         false);
2906                                         if (i == 0) {
2907                                                 real = est.i0_pwr;
2908                                                 imag = est.q0_pwr;
2909                                         } else {
2910                                                 real = est.i1_pwr;
2911                                                 imag = est.q1_pwr;
2912                                         }
2913                                         power[i] = ((real + imag) / 1024) + 1;
2914                                 } else {
2915                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2916                                 }
2917                                 b43_nphy_stop_playback(dev);
2918                         }
2919
2920                         if (ret != 0)
2921                                 break;
2922                 }
2923
2924                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2925                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2926                 b43_phy_write(dev, rfctl[1], tmp[5]);
2927                 b43_phy_write(dev, rfctl[0], tmp[4]);
2928                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2929                 b43_phy_write(dev, afectl_core, tmp[2]);
2930                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2931
2932                 if (ret != 0)
2933                         break;
2934         }
2935
2936         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2937         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2938         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2939
2940         b43_nphy_stay_in_carrier_search(dev, 0);
2941
2942         return ret;
2943 }
2944
2945 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2946                         struct nphy_txgains target, u8 type, bool debug)
2947 {
2948         return -1;
2949 }
2950
2951 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2952 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2953                         struct nphy_txgains target, u8 type, bool debug)
2954 {
2955         if (dev->phy.rev >= 3)
2956                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2957         else
2958                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2959 }
2960
2961 /*
2962  * Init N-PHY
2963  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2964  */
2965 int b43_phy_initn(struct b43_wldev *dev)
2966 {
2967         struct ssb_bus *bus = dev->dev->bus;
2968         struct b43_phy *phy = &dev->phy;
2969         struct b43_phy_n *nphy = phy->n;
2970         u8 tx_pwr_state;
2971         struct nphy_txgains target;
2972         u16 tmp;
2973         enum ieee80211_band tmp2;
2974         bool do_rssi_cal;
2975
2976         u16 clip[2];
2977         bool do_cal = false;
2978
2979         if ((dev->phy.rev >= 3) &&
2980            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2981            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2982                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2983         }
2984         nphy->deaf_count = 0;
2985         b43_nphy_tables_init(dev);
2986         nphy->crsminpwr_adjusted = false;
2987         nphy->noisevars_adjusted = false;
2988
2989         /* Clear all overrides */
2990         if (dev->phy.rev >= 3) {
2991                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2992                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2993                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2994                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2995         } else {
2996                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2997         }
2998         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2999         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3000         if (dev->phy.rev < 6) {
3001                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3002                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3003         }
3004         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3005                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3006                        B43_NPHY_RFSEQMODE_TROVER));
3007         if (dev->phy.rev >= 3)
3008                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3009         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3010
3011         if (dev->phy.rev <= 2) {
3012                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3013                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3014                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3015                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3016         }
3017         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3018         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3019
3020         if (bus->sprom.boardflags2_lo & 0x100 ||
3021             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3022              bus->boardinfo.type == 0x8B))
3023                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3024         else
3025                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3026         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3027         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3028         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3029
3030         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3031         b43_nphy_update_txrx_chain(dev);
3032
3033         if (phy->rev < 2) {
3034                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3035                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3036         }
3037
3038         tmp2 = b43_current_band(dev->wl);
3039         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3040             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3041                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3042                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3043                                 nphy->papd_epsilon_offset[0] << 7);
3044                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3045                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3046                                 nphy->papd_epsilon_offset[1] << 7);
3047                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3048         } else if (phy->rev >= 5) {
3049                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3050         }
3051
3052         b43_nphy_workarounds(dev);
3053
3054         /* Reset CCA, in init code it differs a little from standard way */
3055         b43_nphy_bmac_clock_fgc(dev, 1);
3056         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3057         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3058         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3059         b43_nphy_bmac_clock_fgc(dev, 0);
3060
3061         /* TODO N PHY MAC PHY Clock Set with argument 1 */
3062
3063         b43_nphy_pa_override(dev, false);
3064         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3065         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3066         b43_nphy_pa_override(dev, true);
3067
3068         b43_nphy_classifier(dev, 0, 0);
3069         b43_nphy_read_clip_detection(dev, clip);
3070         tx_pwr_state = nphy->txpwrctrl;
3071         /* TODO N PHY TX power control with argument 0
3072                 (turning off power control) */
3073         /* TODO Fix the TX Power Settings */
3074         /* TODO N PHY TX Power Control Idle TSSI */
3075         /* TODO N PHY TX Power Control Setup */
3076
3077         if (phy->rev >= 3) {
3078                 /* TODO */
3079         } else {
3080                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3081                                         b43_ntab_tx_gain_rev0_1_2);
3082                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3083                                         b43_ntab_tx_gain_rev0_1_2);
3084         }
3085
3086         if (nphy->phyrxchain != 3)
3087                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3088         if (nphy->mphase_cal_phase_id > 0)
3089                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3090
3091         do_rssi_cal = false;
3092         if (phy->rev >= 3) {
3093                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3094                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
3095                 else
3096                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
3097
3098                 if (do_rssi_cal)
3099                         b43_nphy_rssi_cal(dev);
3100                 else
3101                         b43_nphy_restore_rssi_cal(dev);
3102         } else {
3103                 b43_nphy_rssi_cal(dev);
3104         }
3105
3106         if (!((nphy->measure_hold & 0x6) != 0)) {
3107                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3108                         do_cal = (nphy->iqcal_chanspec_2G == 0);
3109                 else
3110                         do_cal = (nphy->iqcal_chanspec_5G == 0);
3111
3112                 if (nphy->mute)
3113                         do_cal = false;
3114
3115                 if (do_cal) {
3116                         target = b43_nphy_get_tx_gains(dev);
3117
3118                         if (nphy->antsel_type == 2)
3119                                 ;/*TODO NPHY Superswitch Init with argument 1*/
3120                         if (nphy->perical != 2) {
3121                                 b43_nphy_rssi_cal(dev);
3122                                 if (phy->rev >= 3) {
3123                                         nphy->cal_orig_pwr_idx[0] =
3124                                             nphy->txpwrindex[0].index_internal;
3125                                         nphy->cal_orig_pwr_idx[1] =
3126                                             nphy->txpwrindex[1].index_internal;
3127                                         /* TODO N PHY Pre Calibrate TX Gain */
3128                                         target = b43_nphy_get_tx_gains(dev);
3129                                 }
3130                         }
3131                 }
3132         }
3133
3134         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3135                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3136                         b43_nphy_save_cal(dev);
3137                 else if (nphy->mphase_cal_phase_id == 0)
3138                         ;/* N PHY Periodic Calibration with argument 3 */
3139         } else {
3140                 b43_nphy_restore_cal(dev);
3141         }
3142
3143         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3144         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3145         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3146         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3147         if (phy->rev >= 3 && phy->rev <= 6)
3148                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3149         b43_nphy_tx_lp_fbw(dev);
3150         if (phy->rev >= 3)
3151                 b43_nphy_spur_workaround(dev);
3152
3153         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3154         return 0;
3155 }
3156
3157 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3158 {
3159         struct b43_phy_n *nphy;
3160
3161         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3162         if (!nphy)
3163                 return -ENOMEM;
3164         dev->phy.n = nphy;
3165
3166         return 0;
3167 }
3168
3169 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3170 {
3171         struct b43_phy *phy = &dev->phy;
3172         struct b43_phy_n *nphy = phy->n;
3173
3174         memset(nphy, 0, sizeof(*nphy));
3175
3176         //TODO init struct b43_phy_n
3177 }
3178
3179 static void b43_nphy_op_free(struct b43_wldev *dev)
3180 {
3181         struct b43_phy *phy = &dev->phy;
3182         struct b43_phy_n *nphy = phy->n;
3183
3184         kfree(nphy);
3185         phy->n = NULL;
3186 }
3187
3188 static int b43_nphy_op_init(struct b43_wldev *dev)
3189 {
3190         return b43_phy_initn(dev);
3191 }
3192
3193 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3194 {
3195 #if B43_DEBUG
3196         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3197                 /* OFDM registers are onnly available on A/G-PHYs */
3198                 b43err(dev->wl, "Invalid OFDM PHY access at "
3199                        "0x%04X on N-PHY\n", offset);
3200                 dump_stack();
3201         }
3202         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3203                 /* Ext-G registers are only available on G-PHYs */
3204                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3205                        "0x%04X on N-PHY\n", offset);
3206                 dump_stack();
3207         }
3208 #endif /* B43_DEBUG */
3209 }
3210
3211 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3212 {
3213         check_phyreg(dev, reg);
3214         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3215         return b43_read16(dev, B43_MMIO_PHY_DATA);
3216 }
3217
3218 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3219 {
3220         check_phyreg(dev, reg);
3221         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3222         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3223 }
3224
3225 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3226 {
3227         /* Register 1 is a 32-bit register. */
3228         B43_WARN_ON(reg == 1);
3229         /* N-PHY needs 0x100 for read access */
3230         reg |= 0x100;
3231
3232         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3233         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3234 }
3235
3236 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3237 {
3238         /* Register 1 is a 32-bit register. */
3239         B43_WARN_ON(reg == 1);
3240
3241         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3242         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3243 }
3244
3245 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3246                                         bool blocked)
3247 {//TODO
3248 }
3249
3250 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3251 {
3252         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3253                       on ? 0 : 0x7FFF);
3254 }
3255
3256 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3257                                       unsigned int new_channel)
3258 {
3259         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3260                 if ((new_channel < 1) || (new_channel > 14))
3261                         return -EINVAL;
3262         } else {
3263                 if (new_channel > 200)
3264                         return -EINVAL;
3265         }
3266
3267         return nphy_channel_switch(dev, new_channel);
3268 }
3269
3270 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3271 {
3272         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3273                 return 1;
3274         return 36;
3275 }
3276
3277 const struct b43_phy_operations b43_phyops_n = {
3278         .allocate               = b43_nphy_op_allocate,
3279         .free                   = b43_nphy_op_free,
3280         .prepare_structs        = b43_nphy_op_prepare_structs,
3281         .init                   = b43_nphy_op_init,
3282         .phy_read               = b43_nphy_op_read,
3283         .phy_write              = b43_nphy_op_write,
3284         .radio_read             = b43_nphy_op_radio_read,
3285         .radio_write            = b43_nphy_op_radio_write,
3286         .software_rfkill        = b43_nphy_op_software_rfkill,
3287         .switch_analog          = b43_nphy_op_switch_analog,
3288         .switch_channel         = b43_nphy_op_switch_channel,
3289         .get_default_chan       = b43_nphy_op_get_default_chan,
3290         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3291         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3292 };