3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
31 #include "tables_nphy.h"
32 #include "radio_2055.h"
33 #include "radio_2056.h"
43 struct nphy_iqcal_params {
61 enum b43_nphy_rf_sequence {
65 B43_RFSEQ_UPDATE_GAINH,
66 B43_RFSEQ_UPDATE_GAINL,
67 B43_RFSEQ_UPDATE_GAINU,
70 enum b43_nphy_rssi_type {
80 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
82 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
83 u8 *events, u8 *delays, u8 length);
84 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
85 enum b43_nphy_rf_sequence seq);
86 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
87 u16 value, u8 core, bool off);
88 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
91 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
95 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
99 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
102 return B43_TXPWR_RES_DONE;
105 static void b43_chantab_radio_upload(struct b43_wldev *dev,
106 const struct b43_nphy_channeltab_entry_rev2 *e)
108 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
109 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
110 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
111 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
112 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
114 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
115 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
116 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
117 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
118 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
120 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
121 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
122 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
123 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
124 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
126 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
127 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
128 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
129 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
130 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
132 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
133 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
134 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
135 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
136 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
138 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
139 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
142 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
143 const struct b43_nphy_channeltab_entry_rev3 *e)
145 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
146 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
147 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
148 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
149 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
150 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
151 e->radio_syn_pll_loopfilter1);
152 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
153 e->radio_syn_pll_loopfilter2);
154 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
155 e->radio_syn_pll_loopfilter3);
156 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
157 e->radio_syn_pll_loopfilter4);
158 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
159 e->radio_syn_pll_loopfilter5);
160 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
161 e->radio_syn_reserved_addr27);
162 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
163 e->radio_syn_reserved_addr28);
164 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
165 e->radio_syn_reserved_addr29);
166 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
167 e->radio_syn_logen_vcobuf1);
168 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
169 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
170 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
172 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
173 e->radio_rx0_lnaa_tune);
174 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
175 e->radio_rx0_lnag_tune);
177 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
178 e->radio_tx0_intpaa_boost_tune);
179 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
180 e->radio_tx0_intpag_boost_tune);
181 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
182 e->radio_tx0_pada_boost_tune);
183 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
184 e->radio_tx0_padg_boost_tune);
185 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
186 e->radio_tx0_pgaa_boost_tune);
187 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
188 e->radio_tx0_pgag_boost_tune);
189 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
190 e->radio_tx0_mixa_boost_tune);
191 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
192 e->radio_tx0_mixg_boost_tune);
194 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
195 e->radio_rx1_lnaa_tune);
196 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
197 e->radio_rx1_lnag_tune);
199 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
200 e->radio_tx1_intpaa_boost_tune);
201 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
202 e->radio_tx1_intpag_boost_tune);
203 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
204 e->radio_tx1_pada_boost_tune);
205 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
206 e->radio_tx1_padg_boost_tune);
207 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
208 e->radio_tx1_pgaa_boost_tune);
209 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
210 e->radio_tx1_pgag_boost_tune);
211 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
212 e->radio_tx1_mixa_boost_tune);
213 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
214 e->radio_tx1_mixg_boost_tune);
217 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
218 static void b43_radio_2056_setup(struct b43_wldev *dev,
219 const struct b43_nphy_channeltab_entry_rev3 *e)
221 B43_WARN_ON(dev->phy.rev < 3);
223 b43_chantab_radio_2056_upload(dev, e);
226 /* VCO calibration */
227 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
228 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
229 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
230 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
231 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
235 static void b43_chantab_phy_upload(struct b43_wldev *dev,
236 const struct b43_phy_n_sfo_cfg *e)
238 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
239 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
240 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
241 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
242 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
243 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
246 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
247 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
249 struct b43_phy_n *nphy = dev->phy.n;
252 enum ieee80211_band band = b43_current_band(dev->wl);
254 if (nphy->hang_avoid)
255 b43_nphy_stay_in_carrier_search(dev, 1);
257 nphy->txpwrctrl = enable;
259 if (dev->phy.rev >= 3 &&
260 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
261 (B43_NPHY_TXPCTL_CMD_COEFF |
262 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
263 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
264 /* We disable enabled TX pwr ctl, save it's state */
265 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
266 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
267 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
268 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
271 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
272 for (i = 0; i < 84; i++)
273 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
275 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
276 for (i = 0; i < 84; i++)
277 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
279 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
280 if (dev->phy.rev >= 3)
281 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
282 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
284 if (dev->phy.rev >= 3) {
285 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
286 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
288 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
291 if (dev->phy.rev == 2)
292 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
293 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
294 else if (dev->phy.rev < 2)
295 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
296 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
298 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
299 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
301 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
303 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
306 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
307 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
308 /* wl does useless check for "enable" param here */
309 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
310 if (dev->phy.rev >= 3) {
311 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
313 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
315 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
317 if (band == IEEE80211_BAND_5GHZ) {
318 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
319 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
320 if (dev->phy.rev > 1)
321 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
322 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
326 if (dev->phy.rev >= 3) {
327 if (nphy->tx_pwr_idx[0] != 128 &&
328 nphy->tx_pwr_idx[1] != 128) {
329 /* Recover TX pwr ctl state */
330 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
331 ~B43_NPHY_TXPCTL_CMD_INIT,
332 nphy->tx_pwr_idx[0]);
333 if (dev->phy.rev > 1)
335 B43_NPHY_TXPCTL_INIT,
336 ~0xff, nphy->tx_pwr_idx[1]);
340 if (dev->phy.rev >= 3) {
341 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
342 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
344 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
347 if (dev->phy.rev == 2)
348 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
349 else if (dev->phy.rev < 2)
350 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
352 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
353 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
355 if ((nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
356 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ)) {
357 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
358 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
362 if (nphy->hang_avoid)
363 b43_nphy_stay_in_carrier_search(dev, 0);
366 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
367 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
369 struct b43_phy_n *nphy = dev->phy.n;
370 struct ssb_sprom *sprom = dev->dev->bus_sprom;
372 u8 txpi[2], bbmult, i;
373 u16 tmp, radio_gain, dac_gain;
374 u16 freq = dev->phy.channel_freq;
376 /* u32 gaintbl; rev3+ */
378 if (nphy->hang_avoid)
379 b43_nphy_stay_in_carrier_search(dev, 1);
381 if (dev->phy.rev >= 3) {
384 } else if (sprom->revision < 4) {
388 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
389 txpi[0] = sprom->txpid2g[0];
390 txpi[1] = sprom->txpid2g[1];
391 } else if (freq >= 4900 && freq < 5100) {
392 txpi[0] = sprom->txpid5gl[0];
393 txpi[1] = sprom->txpid5gl[1];
394 } else if (freq >= 5100 && freq < 5500) {
395 txpi[0] = sprom->txpid5g[0];
396 txpi[1] = sprom->txpid5g[1];
397 } else if (freq >= 5500) {
398 txpi[0] = sprom->txpid5gh[0];
399 txpi[1] = sprom->txpid5gh[1];
407 for (i = 0; i < 2; i++) {
408 nphy->txpwrindex[i].index_internal = txpi[i];
409 nphy->txpwrindex[i].index_internal_save = txpi[i];
413 for (i = 0; i < 2; i++) {
414 if (dev->phy.rev >= 3) {
415 /* FIXME: support 5GHz */
416 txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
417 radio_gain = (txgain >> 16) & 0x1FFFF;
419 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
420 radio_gain = (txgain >> 16) & 0x1FFF;
423 dac_gain = (txgain >> 8) & 0x3F;
424 bbmult = txgain & 0xFF;
426 if (dev->phy.rev >= 3) {
428 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
430 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
432 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
436 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
438 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
440 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
441 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
443 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
444 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
447 tmp = (tmp & 0x00FF) | (bbmult << 8);
449 tmp = (tmp & 0xFF00) | bbmult;
451 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
452 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
458 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
460 if (nphy->hang_avoid)
461 b43_nphy_stay_in_carrier_search(dev, 0);
465 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
466 static void b43_radio_2055_setup(struct b43_wldev *dev,
467 const struct b43_nphy_channeltab_entry_rev2 *e)
469 B43_WARN_ON(dev->phy.rev >= 3);
471 b43_chantab_radio_upload(dev, e);
473 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
474 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
475 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
476 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
480 static void b43_radio_init2055_pre(struct b43_wldev *dev)
482 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
483 ~B43_NPHY_RFCTL_CMD_PORFORCE);
484 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
485 B43_NPHY_RFCTL_CMD_CHIP0PU |
486 B43_NPHY_RFCTL_CMD_OEPORFORCE);
487 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
488 B43_NPHY_RFCTL_CMD_PORFORCE);
491 static void b43_radio_init2055_post(struct b43_wldev *dev)
493 struct b43_phy_n *nphy = dev->phy.n;
494 struct ssb_sprom *sprom = dev->dev->bus_sprom;
497 bool workaround = false;
499 if (sprom->revision < 4)
500 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
501 && dev->dev->board_type == 0x46D
502 && dev->dev->board_rev >= 0x41);
505 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
507 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
509 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
510 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
512 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
513 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
514 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
515 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
516 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
518 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
519 for (i = 0; i < 200; i++) {
520 val = b43_radio_read(dev, B2055_CAL_COUT2);
528 b43err(dev->wl, "radio post init timeout\n");
529 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
530 b43_switch_channel(dev, dev->phy.channel);
531 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
532 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
533 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
534 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
535 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
536 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
537 if (!nphy->gain_boost) {
538 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
539 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
541 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
542 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
548 * Initialize a Broadcom 2055 N-radio
549 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
551 static void b43_radio_init2055(struct b43_wldev *dev)
553 b43_radio_init2055_pre(dev);
554 if (b43_status(dev) < B43_STAT_INITIALIZED) {
555 /* Follow wl, not specs. Do not force uploading all regs */
556 b2055_upload_inittab(dev, 0, 0);
558 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
559 b2055_upload_inittab(dev, ghz5, 0);
561 b43_radio_init2055_post(dev);
564 static void b43_radio_init2056_pre(struct b43_wldev *dev)
566 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
567 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
568 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
569 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
570 B43_NPHY_RFCTL_CMD_OEPORFORCE);
571 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
572 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
573 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
574 B43_NPHY_RFCTL_CMD_CHIP0PU);
577 static void b43_radio_init2056_post(struct b43_wldev *dev)
579 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
580 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
581 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
583 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
584 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
585 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
588 Call Radio 2056 Recalibrate
593 * Initialize a Broadcom 2056 N-radio
594 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
596 static void b43_radio_init2056(struct b43_wldev *dev)
598 b43_radio_init2056_pre(dev);
599 b2056_upload_inittabs(dev, 0, 0);
600 b43_radio_init2056_post(dev);
604 * Upload the N-PHY tables.
605 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
607 static void b43_nphy_tables_init(struct b43_wldev *dev)
609 if (dev->phy.rev < 3)
610 b43_nphy_rev0_1_2_tables_init(dev);
612 b43_nphy_rev3plus_tables_init(dev);
615 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
616 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
618 struct b43_phy_n *nphy = dev->phy.n;
619 enum ieee80211_band band;
623 nphy->rfctrl_intc1_save = b43_phy_read(dev,
624 B43_NPHY_RFCTL_INTC1);
625 nphy->rfctrl_intc2_save = b43_phy_read(dev,
626 B43_NPHY_RFCTL_INTC2);
627 band = b43_current_band(dev->wl);
628 if (dev->phy.rev >= 3) {
629 if (band == IEEE80211_BAND_5GHZ)
634 if (band == IEEE80211_BAND_5GHZ)
639 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
640 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
642 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
643 nphy->rfctrl_intc1_save);
644 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
645 nphy->rfctrl_intc2_save);
649 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
650 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
652 struct b43_phy_n *nphy = dev->phy.n;
654 enum ieee80211_band band = b43_current_band(dev->wl);
655 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
656 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
658 if (dev->phy.rev >= 3) {
661 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
662 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
666 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
667 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
671 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
672 static void b43_nphy_reset_cca(struct b43_wldev *dev)
676 b43_phy_force_clock(dev, 1);
677 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
678 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
680 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
681 b43_phy_force_clock(dev, 0);
682 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
685 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
686 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
688 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
690 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
692 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
694 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
696 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
699 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
700 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
702 struct b43_phy_n *nphy = dev->phy.n;
704 bool override = false;
707 if (nphy->txrx_chain == 0) {
710 } else if (nphy->txrx_chain == 1) {
715 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
716 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
720 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
721 B43_NPHY_RFSEQMODE_CAOVER);
723 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
724 ~B43_NPHY_RFSEQMODE_CAOVER);
727 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
728 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
729 u16 samps, u8 time, bool wait)
734 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
735 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
737 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
739 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
741 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
743 for (i = 1000; i; i--) {
744 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
745 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
746 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
747 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
748 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
749 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
750 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
751 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
753 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
754 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
755 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
756 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
757 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
758 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
763 memset(est, 0, sizeof(*est));
766 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
767 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
768 struct b43_phy_n_iq_comp *pcomp)
771 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
772 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
773 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
774 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
776 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
777 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
778 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
779 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
784 /* Ready but not used anywhere */
785 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
786 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
788 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
790 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
792 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
793 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
795 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
796 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
798 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
799 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
800 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
801 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
802 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
803 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
804 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
805 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
808 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
809 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
812 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
814 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
816 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
817 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
819 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
820 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
822 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
823 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
824 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
825 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
826 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
827 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
828 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
829 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
831 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
832 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
834 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
835 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
836 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
837 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
838 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
839 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
840 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
841 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
842 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
845 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
846 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
848 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
849 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
852 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
853 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
854 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
863 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
864 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
868 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
869 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
875 int iq_nbits, qq_nbits;
879 struct nphy_iq_est est;
880 struct b43_phy_n_iq_comp old;
881 struct b43_phy_n_iq_comp new = { };
887 b43_nphy_rx_iq_coeffs(dev, false, &old);
888 b43_nphy_rx_iq_coeffs(dev, true, &new);
889 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
892 for (i = 0; i < 2; i++) {
893 if (i == 0 && (mask & 1)) {
897 } else if (i == 1 && (mask & 2)) {
910 iq_nbits = fls(abs(iq));
913 arsh = iq_nbits - 20;
915 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
918 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
927 brsh = qq_nbits - 11;
929 b = (qq << (31 - qq_nbits));
932 b = (qq << (31 - qq_nbits));
939 b = int_sqrt(b / tmp - a * a) - (1 << 10);
941 if (i == 0 && (mask & 0x1)) {
942 if (dev->phy.rev >= 3) {
949 } else if (i == 1 && (mask & 0x2)) {
950 if (dev->phy.rev >= 3) {
963 b43_nphy_rx_iq_coeffs(dev, true, &new);
966 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
967 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
972 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
973 for (i = 0; i < 4; i++)
974 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
976 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
977 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
978 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
979 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
982 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
983 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
986 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
987 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
990 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
991 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
993 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
994 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
997 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
998 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
1000 if (dev->phy.rev >= 3) {
1003 if (0 /* FIXME */) {
1004 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
1005 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
1006 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
1007 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
1010 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1011 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1013 switch (dev->dev->bus_type) {
1014 #ifdef CONFIG_B43_BCMA
1016 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1020 #ifdef CONFIG_B43_SSB
1022 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1028 b43_write32(dev, B43_MMIO_MACCTL,
1029 b43_read32(dev, B43_MMIO_MACCTL) &
1030 ~B43_MACCTL_GPOUTSMSK);
1031 b43_write16(dev, B43_MMIO_GPIO_MASK,
1032 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
1033 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
1034 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
1037 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1038 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1039 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1040 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1045 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
1046 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
1050 if (dev->dev->core_rev == 16)
1051 b43_mac_suspend(dev);
1053 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
1054 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
1055 B43_NPHY_CLASSCTL_WAITEDEN);
1057 tmp |= (val & mask);
1058 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
1060 if (dev->dev->core_rev == 16)
1061 b43_mac_enable(dev);
1066 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1067 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1069 struct b43_phy *phy = &dev->phy;
1070 struct b43_phy_n *nphy = phy->n;
1073 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1074 if (nphy->deaf_count++ == 0) {
1075 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1076 b43_nphy_classifier(dev, 0x7, 0);
1077 b43_nphy_read_clip_detection(dev, nphy->clip_state);
1078 b43_nphy_write_clip_detection(dev, clip);
1080 b43_nphy_reset_cca(dev);
1082 if (--nphy->deaf_count == 0) {
1083 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1084 b43_nphy_write_clip_detection(dev, nphy->clip_state);
1089 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1090 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1092 struct b43_phy_n *nphy = dev->phy.n;
1095 if (nphy->hang_avoid)
1096 b43_nphy_stay_in_carrier_search(dev, 1);
1098 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1100 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1102 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1104 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1106 if (nphy->bb_mult_save & 0x80000000) {
1107 tmp = nphy->bb_mult_save & 0xFFFF;
1108 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1109 nphy->bb_mult_save = 0;
1112 if (nphy->hang_avoid)
1113 b43_nphy_stay_in_carrier_search(dev, 0);
1116 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1117 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1119 struct b43_phy_n *nphy = dev->phy.n;
1121 u8 channel = dev->phy.channel;
1122 int tone[2] = { 57, 58 };
1123 u32 noise[2] = { 0x3FF, 0x3FF };
1125 B43_WARN_ON(dev->phy.rev < 3);
1127 if (nphy->hang_avoid)
1128 b43_nphy_stay_in_carrier_search(dev, 1);
1130 if (nphy->gband_spurwar_en) {
1131 /* TODO: N PHY Adjust Analog Pfbw (7) */
1132 if (channel == 11 && dev->phy.is_40mhz)
1133 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1135 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1136 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1139 if (nphy->aband_spurwar_en) {
1140 if (channel == 54) {
1143 } else if (channel == 38 || channel == 102 || channel == 118) {
1144 if (0 /* FIXME */) {
1151 } else if (channel == 134) {
1154 } else if (channel == 151) {
1157 } else if (channel == 153 || channel == 161) {
1165 if (!tone[0] && !noise[0])
1166 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1168 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1171 if (nphy->hang_avoid)
1172 b43_nphy_stay_in_carrier_search(dev, 0);
1175 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1176 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1178 struct b43_phy_n *nphy = dev->phy.n;
1185 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1187 if (nphy->hang_avoid)
1188 b43_nphy_stay_in_carrier_search(dev, 1);
1190 if (nphy->gain_boost) {
1191 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1195 tmp = 40370 - 315 * dev->phy.channel;
1196 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1197 tmp = 23242 - 224 * dev->phy.channel;
1198 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1205 for (i = 0; i < 2; i++) {
1206 if (nphy->elna_gain_config) {
1207 data[0] = 19 + gain[i];
1208 data[1] = 25 + gain[i];
1209 data[2] = 25 + gain[i];
1210 data[3] = 25 + gain[i];
1212 data[0] = lna_gain[0] + gain[i];
1213 data[1] = lna_gain[1] + gain[i];
1214 data[2] = lna_gain[2] + gain[i];
1215 data[3] = lna_gain[3] + gain[i];
1217 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1219 minmax[i] = 23 + gain[i];
1222 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1223 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1224 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1225 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1227 if (nphy->hang_avoid)
1228 b43_nphy_stay_in_carrier_search(dev, 0);
1231 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1232 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1234 struct b43_phy_n *nphy = dev->phy.n;
1235 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1237 /* PHY rev 0, 1, 2 */
1241 u8 rfseq_events[3] = { 6, 8, 7 };
1242 u8 rfseq_delays[3] = { 10, 30, 1 };
1248 struct nphy_gain_ctl_workaround_entry *e;
1249 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1250 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1252 if (dev->phy.rev >= 3) {
1253 /* Prepare values */
1254 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1255 & B43_NPHY_BANDCTL_5GHZ;
1256 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1257 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1258 if (ghz5 && dev->phy.rev >= 5)
1263 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1265 /* Set Clip 2 detect */
1266 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1267 B43_NPHY_C1_CGAINI_CL2DETECT);
1268 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1269 B43_NPHY_C2_CGAINI_CL2DETECT);
1271 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1273 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1275 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1276 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1277 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1278 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1279 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1281 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1283 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1285 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1287 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1288 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1290 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1291 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1292 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1293 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1294 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1295 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1296 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1297 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1298 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1299 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1300 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1301 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1303 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1304 b43_phy_write(dev, 0x2A7, e->init_gain);
1305 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1307 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1309 /* TODO: check defines. Do not match variables names */
1310 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1311 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1312 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1313 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1314 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1315 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1317 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1318 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1319 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1320 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1321 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1322 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1323 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1324 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1325 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1326 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1328 /* Set Clip 2 detect */
1329 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1330 B43_NPHY_C1_CGAINI_CL2DETECT);
1331 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1332 B43_NPHY_C2_CGAINI_CL2DETECT);
1334 /* Set narrowband clip threshold */
1335 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1336 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1338 if (!dev->phy.is_40mhz) {
1339 /* Set dwell lengths */
1340 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1341 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1342 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1343 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1346 /* Set wideband clip 2 threshold */
1347 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1348 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1350 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1351 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1354 if (!dev->phy.is_40mhz) {
1355 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1356 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1357 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1358 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1359 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1360 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1361 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1362 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1365 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1367 if (nphy->gain_boost) {
1368 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1374 code = dev->phy.is_40mhz ? 6 : 7;
1377 /* Set HPVGA2 index */
1378 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1379 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1380 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1381 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1382 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1383 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1385 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1386 /* specs say about 2 loops, but wl does 4 */
1387 for (i = 0; i < 4; i++)
1388 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1389 (code << 8 | 0x7C));
1391 b43_nphy_adjust_lna_gain_table(dev);
1393 if (nphy->elna_gain_config) {
1394 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1395 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1396 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1397 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1398 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1400 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1401 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1402 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1403 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1404 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1406 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1407 /* specs say about 2 loops, but wl does 4 */
1408 for (i = 0; i < 4; i++)
1409 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1410 (code << 8 | 0x74));
1413 if (dev->phy.rev == 2) {
1414 for (i = 0; i < 4; i++) {
1415 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1416 (0x0400 * i) + 0x0020);
1417 for (j = 0; j < 21; j++) {
1418 tmp = j * (i < 2 ? 3 : 1);
1420 B43_NPHY_TABLE_DATALO, tmp);
1425 b43_nphy_set_rf_sequence(dev, 5,
1426 rfseq_events, rfseq_delays, 3);
1427 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1428 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1429 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1431 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1432 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1437 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1438 static void b43_nphy_workarounds(struct b43_wldev *dev)
1440 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1441 struct b43_phy *phy = &dev->phy;
1442 struct b43_phy_n *nphy = phy->n;
1444 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1445 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1447 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1448 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1453 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1454 b43_nphy_classifier(dev, 1, 0);
1456 b43_nphy_classifier(dev, 1, 1);
1458 if (nphy->hang_avoid)
1459 b43_nphy_stay_in_carrier_search(dev, 1);
1461 b43_phy_set(dev, B43_NPHY_IQFLIP,
1462 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1464 if (dev->phy.rev >= 3) {
1465 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1467 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1469 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1470 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1471 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1472 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1473 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1474 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1476 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1477 b43_phy_write(dev, 0x2AE, 0x000C);
1481 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1483 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1485 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1487 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1488 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1490 b43_nphy_gain_ctrl_workarounds(dev);
1492 b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1493 b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1497 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1498 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1499 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1500 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1501 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1502 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1503 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1504 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1505 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1506 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1508 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1510 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1511 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1512 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1513 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1517 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1518 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1519 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1521 if (dev->phy.rev == 4 &&
1522 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1523 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1525 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1529 b43_phy_write(dev, 0x224, 0x039C);
1530 b43_phy_write(dev, 0x225, 0x0357);
1531 b43_phy_write(dev, 0x226, 0x0317);
1532 b43_phy_write(dev, 0x227, 0x02D7);
1533 b43_phy_write(dev, 0x228, 0x039C);
1534 b43_phy_write(dev, 0x229, 0x0357);
1535 b43_phy_write(dev, 0x22A, 0x0317);
1536 b43_phy_write(dev, 0x22B, 0x02D7);
1537 b43_phy_write(dev, 0x22C, 0x039C);
1538 b43_phy_write(dev, 0x22D, 0x0357);
1539 b43_phy_write(dev, 0x22E, 0x0317);
1540 b43_phy_write(dev, 0x22F, 0x02D7);
1542 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1543 nphy->band5g_pwrgain) {
1544 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1545 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1547 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1548 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1551 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1552 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1553 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1554 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1556 if (dev->phy.rev < 2) {
1557 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1558 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1559 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1560 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1561 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1562 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1565 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1566 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1567 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1568 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1570 if (sprom->boardflags2_lo & 0x100 &&
1571 dev->dev->board_type == 0x8B) {
1575 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1576 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1578 b43_nphy_gain_ctrl_workarounds(dev);
1580 if (dev->phy.rev < 2) {
1581 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1582 b43_hf_write(dev, b43_hf_read(dev) |
1584 } else if (dev->phy.rev == 2) {
1585 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1586 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1589 if (dev->phy.rev < 2)
1590 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1591 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1593 /* Set phase track alpha and beta */
1594 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1595 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1596 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1597 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1598 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1599 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1601 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1602 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1603 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1604 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1605 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1607 if (dev->phy.rev == 2)
1608 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1609 B43_NPHY_FINERX2_CGC_DECGC);
1612 if (nphy->hang_avoid)
1613 b43_nphy_stay_in_carrier_search(dev, 0);
1616 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1617 static int b43_nphy_load_samples(struct b43_wldev *dev,
1618 struct b43_c32 *samples, u16 len) {
1619 struct b43_phy_n *nphy = dev->phy.n;
1623 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1625 b43err(dev->wl, "allocation for samples loading failed\n");
1628 if (nphy->hang_avoid)
1629 b43_nphy_stay_in_carrier_search(dev, 1);
1631 for (i = 0; i < len; i++) {
1632 data[i] = (samples[i].i & 0x3FF << 10);
1633 data[i] |= samples[i].q & 0x3FF;
1635 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1638 if (nphy->hang_avoid)
1639 b43_nphy_stay_in_carrier_search(dev, 0);
1643 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1644 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1648 u16 bw, len, rot, angle;
1649 struct b43_c32 *samples;
1652 bw = (dev->phy.is_40mhz) ? 40 : 20;
1656 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1661 if (dev->phy.is_40mhz)
1667 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1669 b43err(dev->wl, "allocation for samples generation failed\n");
1672 rot = (((freq * 36) / bw) << 16) / 100;
1675 for (i = 0; i < len; i++) {
1676 samples[i] = b43_cordic(angle);
1678 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1679 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1682 i = b43_nphy_load_samples(dev, samples, len);
1684 return (i < 0) ? 0 : len;
1687 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1688 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1689 u16 wait, bool iqmode, bool dac_test)
1691 struct b43_phy_n *nphy = dev->phy.n;
1696 if (nphy->hang_avoid)
1697 b43_nphy_stay_in_carrier_search(dev, true);
1699 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1700 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1701 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1704 if (!dev->phy.is_40mhz)
1708 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1710 if (nphy->hang_avoid)
1711 b43_nphy_stay_in_carrier_search(dev, false);
1713 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1715 if (loops != 0xFFFF)
1716 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1718 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1720 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1722 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1724 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1726 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1727 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1730 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1732 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1734 for (i = 0; i < 100; i++) {
1735 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1742 b43err(dev->wl, "run samples timeout\n");
1744 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1748 * Transmits a known value for LO calibration
1749 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1751 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1752 bool iqmode, bool dac_test)
1754 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1757 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1761 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1762 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1764 struct b43_phy_n *nphy = dev->phy.n;
1767 u32 cur_real, cur_imag, real_part, imag_part;
1771 if (nphy->hang_avoid)
1772 b43_nphy_stay_in_carrier_search(dev, true);
1774 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1776 for (i = 0; i < 2; i++) {
1777 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1778 (buffer[i * 2 + 1] & 0x3FF);
1779 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1780 (((i + 26) << 10) | 320));
1781 for (j = 0; j < 128; j++) {
1782 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1783 ((tmp >> 16) & 0xFFFF));
1784 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1789 for (i = 0; i < 2; i++) {
1790 tmp = buffer[5 + i];
1791 real_part = (tmp >> 8) & 0xFF;
1792 imag_part = (tmp & 0xFF);
1793 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1794 (((i + 26) << 10) | 448));
1796 if (dev->phy.rev >= 3) {
1797 cur_real = real_part;
1798 cur_imag = imag_part;
1799 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1802 for (j = 0; j < 128; j++) {
1803 if (dev->phy.rev < 3) {
1804 cur_real = (real_part * loscale[j] + 128) >> 8;
1805 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1806 tmp = ((cur_real & 0xFF) << 8) |
1809 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1810 ((tmp >> 16) & 0xFFFF));
1811 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1816 if (dev->phy.rev >= 3) {
1817 b43_shm_write16(dev, B43_SHM_SHARED,
1818 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1819 b43_shm_write16(dev, B43_SHM_SHARED,
1820 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1823 if (nphy->hang_avoid)
1824 b43_nphy_stay_in_carrier_search(dev, false);
1827 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1828 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1829 u8 *events, u8 *delays, u8 length)
1831 struct b43_phy_n *nphy = dev->phy.n;
1833 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1834 u16 offset1 = cmd << 4;
1835 u16 offset2 = offset1 + 0x80;
1837 if (nphy->hang_avoid)
1838 b43_nphy_stay_in_carrier_search(dev, true);
1840 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1841 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1843 for (i = length; i < 16; i++) {
1844 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1845 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1848 if (nphy->hang_avoid)
1849 b43_nphy_stay_in_carrier_search(dev, false);
1852 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1853 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1854 enum b43_nphy_rf_sequence seq)
1856 static const u16 trigger[] = {
1857 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1858 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1859 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1860 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1861 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1862 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1865 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1867 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1869 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1870 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1871 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1872 for (i = 0; i < 200; i++) {
1873 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1877 b43err(dev->wl, "RF sequence status timeout\n");
1879 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1882 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1883 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1884 u16 value, u8 core, bool off)
1887 u8 index = fls(field);
1888 u8 addr, en_addr, val_addr;
1889 /* we expect only one bit set */
1890 B43_WARN_ON(field & (~(1 << (index - 1))));
1892 if (dev->phy.rev >= 3) {
1893 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1894 for (i = 0; i < 2; i++) {
1895 if (index == 0 || index == 16) {
1897 "Unsupported RF Ctrl Override call\n");
1901 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1902 en_addr = B43_PHY_N((i == 0) ?
1903 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1904 val_addr = B43_PHY_N((i == 0) ?
1905 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1908 b43_phy_mask(dev, en_addr, ~(field));
1909 b43_phy_mask(dev, val_addr,
1910 ~(rf_ctrl->val_mask));
1912 if (core == 0 || ((1 << core) & i) != 0) {
1913 b43_phy_set(dev, en_addr, field);
1914 b43_phy_maskset(dev, val_addr,
1915 ~(rf_ctrl->val_mask),
1916 (value << rf_ctrl->val_shift));
1921 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1923 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1926 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1929 for (i = 0; i < 2; i++) {
1930 if (index <= 1 || index == 16) {
1932 "Unsupported RF Ctrl Override call\n");
1936 if (index == 2 || index == 10 ||
1937 (index >= 13 && index <= 15)) {
1941 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1942 addr = B43_PHY_N((i == 0) ?
1943 rf_ctrl->addr0 : rf_ctrl->addr1);
1945 if ((core & (1 << i)) != 0)
1946 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1947 (value << rf_ctrl->shift));
1949 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1950 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1951 B43_NPHY_RFCTL_CMD_START);
1953 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1958 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1959 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1965 B43_WARN_ON(dev->phy.rev < 3);
1966 B43_WARN_ON(field > 4);
1968 for (i = 0; i < 2; i++) {
1969 if ((core == 1 && i == 1) || (core == 2 && !i))
1973 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1974 b43_phy_mask(dev, reg, 0xFBFF);
1978 b43_phy_write(dev, reg, 0);
1979 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1983 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1984 0xFC3F, (value << 6));
1985 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1987 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1988 B43_NPHY_RFCTL_CMD_START);
1989 for (j = 0; j < 100; j++) {
1990 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1998 "intc override timeout\n");
1999 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
2002 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
2003 0xFC3F, (value << 6));
2004 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
2006 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2007 B43_NPHY_RFCTL_CMD_RXTX);
2008 for (j = 0; j < 100; j++) {
2009 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
2017 "intc override timeout\n");
2018 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2023 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2030 b43_phy_maskset(dev, reg, ~tmp, val);
2033 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2040 b43_phy_maskset(dev, reg, ~tmp, val);
2043 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2050 b43_phy_maskset(dev, reg, ~tmp, val);
2056 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
2057 static void b43_nphy_bphy_init(struct b43_wldev *dev)
2063 for (i = 0; i < 16; i++) {
2064 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2068 for (i = 0; i < 16; i++) {
2069 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2072 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2075 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2076 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2077 s8 offset, u8 core, u8 rail,
2078 enum b43_nphy_rssi_type type)
2081 bool core1or5 = (core == 1) || (core == 5);
2082 bool core2or5 = (core == 2) || (core == 5);
2084 offset = clamp_val(offset, -32, 31);
2085 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2087 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2088 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2089 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2090 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2091 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2092 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2093 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2094 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2096 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2097 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2098 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2099 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2100 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2101 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2102 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2103 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2105 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2106 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2107 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2108 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2109 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2110 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2111 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2112 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2114 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2115 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2116 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2117 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2118 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2119 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2120 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2121 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2123 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2124 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2125 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2126 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2127 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2128 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2129 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2130 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2132 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2133 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2134 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2135 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2137 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2138 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2139 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2140 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2143 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2156 val = (val << 12) | (val << 14);
2157 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2158 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2161 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2163 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2168 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2170 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2171 ~(B43_NPHY_RFCTL_CMD_RXEN |
2172 B43_NPHY_RFCTL_CMD_CORESEL));
2173 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2178 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2179 ~B43_NPHY_RFCTL_CMD_START);
2181 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2184 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2186 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2187 ~(B43_NPHY_RFCTL_CMD_RXEN |
2188 B43_NPHY_RFCTL_CMD_CORESEL),
2189 (B43_NPHY_RFCTL_CMD_RXEN |
2190 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2191 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2196 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2197 B43_NPHY_RFCTL_CMD_START);
2199 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2204 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2206 struct b43_phy_n *nphy = dev->phy.n;
2211 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2212 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2213 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2214 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2215 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2216 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2217 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2218 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2220 for (i = 0; i < 2; i++) {
2221 if ((code == 1 && i == 1) || (code == 2 && !i))
2225 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2226 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2230 B43_NPHY_AFECTL_C1 :
2232 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2235 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2236 B43_NPHY_RFCTL_LUT_TRSW_UP2;
2237 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2240 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2245 b43_phy_set(dev, reg, val);
2248 B43_NPHY_TXF_40CO_B1S0 :
2249 B43_NPHY_TXF_40CO_B32S1;
2250 b43_phy_set(dev, reg, 0x0020);
2260 B43_NPHY_AFECTL_C1 :
2263 b43_phy_maskset(dev, reg, 0xFCFF, val);
2264 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2266 if (type != 3 && type != 6) {
2267 enum ieee80211_band band =
2268 b43_current_band(dev->wl);
2270 if ((nphy->ipa2g_on &&
2271 band == IEEE80211_BAND_2GHZ) ||
2273 band == IEEE80211_BAND_5GHZ))
2274 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2277 reg = (i == 0) ? 0x2000 : 0x3000;
2278 reg |= B2055_PADDRV;
2279 b43_radio_write16(dev, reg, val);
2282 B43_NPHY_AFECTL_OVER1 :
2283 B43_NPHY_AFECTL_OVER;
2284 b43_phy_set(dev, reg, 0x0200);
2291 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2292 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2294 if (dev->phy.rev >= 3)
2295 b43_nphy_rev3_rssi_select(dev, code, type);
2297 b43_nphy_rev2_rssi_select(dev, code, type);
2300 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2301 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2304 for (i = 0; i < 2; i++) {
2307 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2309 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2312 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2314 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2315 0xFC, buf[2 * i + 1]);
2319 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2322 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2323 0xF3, buf[2 * i + 1] << 2);
2328 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2329 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2334 u16 save_regs_phy[9];
2337 if (dev->phy.rev >= 3) {
2338 save_regs_phy[0] = b43_phy_read(dev,
2339 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2340 save_regs_phy[1] = b43_phy_read(dev,
2341 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2342 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2343 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2344 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2345 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2346 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2347 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2348 save_regs_phy[8] = 0;
2350 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2351 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2352 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2353 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2354 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2355 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2356 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2357 save_regs_phy[7] = 0;
2358 save_regs_phy[8] = 0;
2361 b43_nphy_rssi_select(dev, 5, type);
2363 if (dev->phy.rev < 2) {
2364 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2365 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2368 for (i = 0; i < 4; i++)
2371 for (i = 0; i < nsamp; i++) {
2372 if (dev->phy.rev < 2) {
2373 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2374 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2376 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2377 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2380 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2381 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2382 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2383 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2385 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2386 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2388 if (dev->phy.rev < 2)
2389 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2391 if (dev->phy.rev >= 3) {
2392 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2394 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2396 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2397 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2398 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2399 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2400 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2401 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2403 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2404 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2405 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2406 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2407 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2408 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2409 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2415 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2416 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2421 u16 class, override;
2422 u8 regs_save_radio[2];
2423 u16 regs_save_phy[2];
2430 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2431 s32 results_min[4] = { };
2432 u8 vcm_final[4] = { };
2433 s32 results[4][4] = { };
2434 s32 miniq[4][2] = { };
2439 } else if (type < 2) {
2447 class = b43_nphy_classifier(dev, 0, 0);
2448 b43_nphy_classifier(dev, 7, 4);
2449 b43_nphy_read_clip_detection(dev, clip_state);
2450 b43_nphy_write_clip_detection(dev, clip_off);
2452 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2457 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2458 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2459 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2460 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2462 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2463 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2464 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2465 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2467 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2468 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2469 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2470 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2471 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2472 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2474 b43_nphy_rssi_select(dev, 5, type);
2475 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2476 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2478 for (i = 0; i < 4; i++) {
2480 for (j = 0; j < 4; j++)
2483 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2484 b43_nphy_poll_rssi(dev, type, results[i], 8);
2486 for (j = 0; j < 2; j++)
2487 miniq[i][j] = min(results[i][2 * j],
2488 results[i][2 * j + 1]);
2491 for (i = 0; i < 4; i++) {
2496 for (j = 0; j < 4; j++) {
2498 curr = abs(results[j][i]);
2500 curr = abs(miniq[j][i / 2] - code * 8);
2507 if (results[j][i] < minpoll)
2508 minpoll = results[j][i];
2510 results_min[i] = minpoll;
2511 vcm_final[i] = minvcm;
2515 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2517 for (i = 0; i < 4; i++) {
2518 offset[i] = (code * 8) - results[vcm_final[i]][i];
2521 offset[i] = -((abs(offset[i]) + 4) / 8);
2523 offset[i] = (offset[i] + 4) / 8;
2525 if (results_min[i] == 248)
2526 offset[i] = code - 32;
2528 core = (i / 2) ? 2 : 1;
2529 rail = (i % 2) ? 1 : 0;
2531 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2535 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2536 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2540 b43_nphy_rssi_select(dev, 1, 2);
2543 b43_nphy_rssi_select(dev, 1, 0);
2546 b43_nphy_rssi_select(dev, 1, 1);
2549 b43_nphy_rssi_select(dev, 1, 1);
2555 b43_nphy_rssi_select(dev, 2, 2);
2558 b43_nphy_rssi_select(dev, 2, 0);
2561 b43_nphy_rssi_select(dev, 2, 1);
2565 b43_nphy_rssi_select(dev, 0, type);
2567 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2568 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2569 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2570 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2572 b43_nphy_classifier(dev, 7, class);
2573 b43_nphy_write_clip_detection(dev, clip_state);
2574 /* Specs don't say about reset here, but it makes wl and b43 dumps
2575 identical, it really seems wl performs this */
2576 b43_nphy_reset_cca(dev);
2579 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2580 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2587 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2589 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2591 if (dev->phy.rev >= 3) {
2592 b43_nphy_rev3_rssi_cal(dev);
2594 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2595 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2596 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2601 * Restore RSSI Calibration
2602 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2604 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2606 struct b43_phy_n *nphy = dev->phy.n;
2608 u16 *rssical_radio_regs = NULL;
2609 u16 *rssical_phy_regs = NULL;
2611 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2612 if (!nphy->rssical_chanspec_2G.center_freq)
2614 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2615 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2617 if (!nphy->rssical_chanspec_5G.center_freq)
2619 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2620 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2623 /* TODO use some definitions */
2624 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2625 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2627 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2628 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2629 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2630 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2632 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2633 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2634 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2635 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2637 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2638 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2639 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2640 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2643 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2644 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2646 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2647 if (dev->phy.rev >= 6) {
2648 /* TODO If the chip is 47162
2649 return txpwrctrl_tx_gain_ipa_rev5 */
2650 return txpwrctrl_tx_gain_ipa_rev6;
2651 } else if (dev->phy.rev >= 5) {
2652 return txpwrctrl_tx_gain_ipa_rev5;
2654 return txpwrctrl_tx_gain_ipa;
2657 return txpwrctrl_tx_gain_ipa_5g;
2661 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2662 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2664 struct b43_phy_n *nphy = dev->phy.n;
2665 u16 *save = nphy->tx_rx_cal_radio_saveregs;
2669 if (dev->phy.rev >= 3) {
2670 for (i = 0; i < 2; i++) {
2671 tmp = (i == 0) ? 0x2000 : 0x3000;
2674 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2675 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2676 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2677 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2678 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2679 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2680 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2681 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2682 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2683 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2684 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2686 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2687 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2688 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2689 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2690 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2691 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2692 if (nphy->ipa5g_on) {
2693 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2694 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2696 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2697 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2699 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2701 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2702 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2703 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2704 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2705 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2706 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2707 if (nphy->ipa2g_on) {
2708 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2709 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2710 (dev->phy.rev < 5) ? 0x11 : 0x01);
2712 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2713 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2716 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2717 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2718 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2721 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2722 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2724 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2725 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2727 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2728 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2730 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2731 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2733 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2734 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2736 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2737 B43_NPHY_BANDCTL_5GHZ)) {
2738 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2739 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2741 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2742 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2745 if (dev->phy.rev < 2) {
2746 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2747 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2749 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2750 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2755 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2756 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2757 struct nphy_txgains target,
2758 struct nphy_iqcal_params *params)
2763 if (dev->phy.rev >= 3) {
2764 params->txgm = target.txgm[core];
2765 params->pga = target.pga[core];
2766 params->pad = target.pad[core];
2767 params->ipa = target.ipa[core];
2768 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2769 (params->pad << 4) | (params->ipa);
2770 for (j = 0; j < 5; j++)
2771 params->ncorr[j] = 0x79;
2773 gain = (target.pad[core]) | (target.pga[core] << 4) |
2774 (target.txgm[core] << 8);
2776 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2778 for (i = 0; i < 9; i++)
2779 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2783 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2784 params->pga = tbl_iqcal_gainparams[indx][i][2];
2785 params->pad = tbl_iqcal_gainparams[indx][i][3];
2786 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2788 for (j = 0; j < 4; j++)
2789 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2793 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2794 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2796 struct b43_phy_n *nphy = dev->phy.n;
2800 u16 tmp = nphy->txcal_bbmult;
2805 for (i = 0; i < 18; i++) {
2806 scale = (ladder_lo[i].percent * tmp) / 100;
2807 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2808 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2810 scale = (ladder_iq[i].percent * tmp) / 100;
2811 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2812 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2816 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2817 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2820 for (i = 0; i < 15; i++)
2821 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2822 tbl_tx_filter_coef_rev4[2][i]);
2825 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2826 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2829 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2830 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2832 for (i = 0; i < 3; i++)
2833 for (j = 0; j < 15; j++)
2834 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2835 tbl_tx_filter_coef_rev4[i][j]);
2837 if (dev->phy.is_40mhz) {
2838 for (j = 0; j < 15; j++)
2839 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2840 tbl_tx_filter_coef_rev4[3][j]);
2841 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2842 for (j = 0; j < 15; j++)
2843 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2844 tbl_tx_filter_coef_rev4[5][j]);
2847 if (dev->phy.channel == 14)
2848 for (j = 0; j < 15; j++)
2849 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2850 tbl_tx_filter_coef_rev4[6][j]);
2853 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2854 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2856 struct b43_phy_n *nphy = dev->phy.n;
2859 struct nphy_txgains target;
2860 const u32 *table = NULL;
2862 if (!nphy->txpwrctrl) {
2865 if (nphy->hang_avoid)
2866 b43_nphy_stay_in_carrier_search(dev, true);
2867 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2868 if (nphy->hang_avoid)
2869 b43_nphy_stay_in_carrier_search(dev, false);
2871 for (i = 0; i < 2; ++i) {
2872 if (dev->phy.rev >= 3) {
2873 target.ipa[i] = curr_gain[i] & 0x000F;
2874 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2875 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2876 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2878 target.ipa[i] = curr_gain[i] & 0x0003;
2879 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2880 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2881 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2887 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2888 B43_NPHY_TXPCTL_STAT_BIDX) >>
2889 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2890 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2891 B43_NPHY_TXPCTL_STAT_BIDX) >>
2892 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2894 for (i = 0; i < 2; ++i) {
2895 if (dev->phy.rev >= 3) {
2896 enum ieee80211_band band =
2897 b43_current_band(dev->wl);
2899 if ((nphy->ipa2g_on &&
2900 band == IEEE80211_BAND_2GHZ) ||
2902 band == IEEE80211_BAND_5GHZ)) {
2903 table = b43_nphy_get_ipa_gain_table(dev);
2905 if (band == IEEE80211_BAND_5GHZ) {
2906 if (dev->phy.rev == 3)
2907 table = b43_ntab_tx_gain_rev3_5ghz;
2908 else if (dev->phy.rev == 4)
2909 table = b43_ntab_tx_gain_rev4_5ghz;
2911 table = b43_ntab_tx_gain_rev5plus_5ghz;
2913 table = b43_ntab_tx_gain_rev3plus_2ghz;
2917 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2918 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2919 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2920 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2922 table = b43_ntab_tx_gain_rev0_1_2;
2924 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2925 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2926 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2927 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2935 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2936 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2938 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2940 if (dev->phy.rev >= 3) {
2941 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2942 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2943 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2944 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2945 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2946 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2947 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2948 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2949 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2950 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2951 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2952 b43_nphy_reset_cca(dev);
2954 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2955 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2956 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2957 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2958 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2959 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2960 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2964 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2965 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2967 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2970 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2971 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2972 if (dev->phy.rev >= 3) {
2973 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2974 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2976 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2978 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2980 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2982 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2984 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2985 b43_phy_mask(dev, B43_NPHY_BBCFG,
2986 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2988 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2990 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2992 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2994 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2995 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2996 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2998 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2999 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3000 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
3002 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3003 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3004 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3005 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3007 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3008 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3009 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3011 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
3012 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
3015 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
3016 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
3019 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
3020 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3021 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3022 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3026 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3027 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3031 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3032 static void b43_nphy_save_cal(struct b43_wldev *dev)
3034 struct b43_phy_n *nphy = dev->phy.n;
3036 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3037 u16 *txcal_radio_regs = NULL;
3038 struct b43_chanspec *iqcal_chanspec;
3041 if (nphy->hang_avoid)
3042 b43_nphy_stay_in_carrier_search(dev, 1);
3044 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3045 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3046 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3047 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3048 table = nphy->cal_cache.txcal_coeffs_2G;
3050 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3051 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3052 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3053 table = nphy->cal_cache.txcal_coeffs_5G;
3056 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3057 /* TODO use some definitions */
3058 if (dev->phy.rev >= 3) {
3059 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3060 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3061 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3062 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3063 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3064 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3065 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3066 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3068 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3069 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3070 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3071 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3073 iqcal_chanspec->center_freq = dev->phy.channel_freq;
3074 iqcal_chanspec->channel_type = dev->phy.channel_type;
3075 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3077 if (nphy->hang_avoid)
3078 b43_nphy_stay_in_carrier_search(dev, 0);
3081 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3082 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3084 struct b43_phy_n *nphy = dev->phy.n;
3091 u16 *txcal_radio_regs = NULL;
3092 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3094 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3095 if (!nphy->iqcal_chanspec_2G.center_freq)
3097 table = nphy->cal_cache.txcal_coeffs_2G;
3098 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3100 if (!nphy->iqcal_chanspec_5G.center_freq)
3102 table = nphy->cal_cache.txcal_coeffs_5G;
3103 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3106 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3108 for (i = 0; i < 4; i++) {
3109 if (dev->phy.rev >= 3)
3115 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3116 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3117 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3119 if (dev->phy.rev < 2)
3120 b43_nphy_tx_iq_workaround(dev);
3122 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3123 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3124 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3126 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3127 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3130 /* TODO use some definitions */
3131 if (dev->phy.rev >= 3) {
3132 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3133 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3134 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3135 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3136 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3137 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3138 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3139 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3141 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3142 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3143 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3144 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3146 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3149 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3150 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3151 struct nphy_txgains target,
3152 bool full, bool mphase)
3154 struct b43_phy_n *nphy = dev->phy.n;
3160 u16 tmp, core, type, count, max, numb, last = 0, cmd;
3168 struct nphy_iqcal_params params[2];
3169 bool updated[2] = { };
3171 b43_nphy_stay_in_carrier_search(dev, true);
3173 if (dev->phy.rev >= 4) {
3174 avoid = nphy->hang_avoid;
3175 nphy->hang_avoid = 0;
3178 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3180 for (i = 0; i < 2; i++) {
3181 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
3182 gain[i] = params[i].cal_gain;
3185 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3187 b43_nphy_tx_cal_radio_setup(dev);
3188 b43_nphy_tx_cal_phy_setup(dev);
3190 phy6or5x = dev->phy.rev >= 6 ||
3191 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3192 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3194 if (dev->phy.is_40mhz) {
3195 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3196 tbl_tx_iqlo_cal_loft_ladder_40);
3197 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3198 tbl_tx_iqlo_cal_iqimb_ladder_40);
3200 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3201 tbl_tx_iqlo_cal_loft_ladder_20);
3202 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3203 tbl_tx_iqlo_cal_iqimb_ladder_20);
3207 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3209 if (!dev->phy.is_40mhz)
3214 if (nphy->mphase_cal_phase_id > 2)
3215 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3216 0xFFFF, 0, true, false);
3218 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3221 if (nphy->mphase_cal_phase_id > 2) {
3222 table = nphy->mphase_txcal_bestcoeffs;
3224 if (dev->phy.rev < 3)
3227 if (!full && nphy->txiqlocal_coeffsvalid) {
3228 table = nphy->txiqlocal_bestc;
3230 if (dev->phy.rev < 3)
3234 if (dev->phy.rev >= 3) {
3235 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3236 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3238 table = tbl_tx_iqlo_cal_startcoefs;
3239 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3244 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3247 if (dev->phy.rev >= 3)
3248 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3250 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3252 if (dev->phy.rev >= 3)
3253 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3255 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3259 count = nphy->mphase_txcal_cmdidx;
3261 (u16)(count + nphy->mphase_txcal_numcmds));
3267 for (; count < numb; count++) {
3269 if (dev->phy.rev >= 3)
3270 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3272 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3274 if (dev->phy.rev >= 3)
3275 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3277 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3280 core = (cmd & 0x3000) >> 12;
3281 type = (cmd & 0x0F00) >> 8;
3283 if (phy6or5x && updated[core] == 0) {
3284 b43_nphy_update_tx_cal_ladder(dev, core);
3288 tmp = (params[core].ncorr[type] << 8) | 0x66;
3289 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3291 if (type == 1 || type == 3 || type == 4) {
3292 buffer[0] = b43_ntab_read(dev,
3293 B43_NTAB16(15, 69 + core));
3294 diq_start = buffer[0];
3296 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3300 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3301 for (i = 0; i < 2000; i++) {
3302 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3308 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3310 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3313 if (type == 1 || type == 3 || type == 4)
3314 buffer[0] = diq_start;
3318 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3320 last = (dev->phy.rev < 3) ? 6 : 7;
3322 if (!mphase || nphy->mphase_cal_phase_id == last) {
3323 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3324 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3325 if (dev->phy.rev < 3) {
3331 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3333 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3335 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3337 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3340 if (dev->phy.rev < 3)
3342 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3343 nphy->txiqlocal_bestc);
3344 nphy->txiqlocal_coeffsvalid = true;
3345 nphy->txiqlocal_chanspec.center_freq =
3346 dev->phy.channel_freq;
3347 nphy->txiqlocal_chanspec.channel_type =
3348 dev->phy.channel_type;
3351 if (dev->phy.rev < 3)
3353 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3354 nphy->mphase_txcal_bestcoeffs);
3357 b43_nphy_stop_playback(dev);
3358 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3361 b43_nphy_tx_cal_phy_cleanup(dev);
3362 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3364 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3365 b43_nphy_tx_iq_workaround(dev);
3367 if (dev->phy.rev >= 4)
3368 nphy->hang_avoid = avoid;
3370 b43_nphy_stay_in_carrier_search(dev, false);
3375 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3376 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3378 struct b43_phy_n *nphy = dev->phy.n;
3383 if (!nphy->txiqlocal_coeffsvalid ||
3384 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3385 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3388 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3389 for (i = 0; i < 4; i++) {
3390 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3397 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3398 nphy->txiqlocal_bestc);
3399 for (i = 0; i < 4; i++)
3401 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3403 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3404 &nphy->txiqlocal_bestc[5]);
3405 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3406 &nphy->txiqlocal_bestc[5]);
3410 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3411 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3412 struct nphy_txgains target, u8 type, bool debug)
3414 struct b43_phy_n *nphy = dev->phy.n;
3419 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3421 enum ieee80211_band band;
3425 u16 lna[3] = { 3, 3, 1 };
3426 u16 hpf1[3] = { 7, 2, 0 };
3427 u16 hpf2[3] = { 2, 0, 0 };
3431 struct nphy_iqcal_params cal_params[2];
3432 struct nphy_iq_est est;
3434 bool playtone = true;
3437 b43_nphy_stay_in_carrier_search(dev, 1);
3439 if (dev->phy.rev < 2)
3440 b43_nphy_reapply_tx_cal_coeffs(dev);
3441 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3442 for (i = 0; i < 2; i++) {
3443 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3444 cal_gain[i] = cal_params[i].cal_gain;
3446 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3448 for (i = 0; i < 2; i++) {
3450 rfctl[0] = B43_NPHY_RFCTL_INTC1;
3451 rfctl[1] = B43_NPHY_RFCTL_INTC2;
3452 afectl_core = B43_NPHY_AFECTL_C1;
3454 rfctl[0] = B43_NPHY_RFCTL_INTC2;
3455 rfctl[1] = B43_NPHY_RFCTL_INTC1;
3456 afectl_core = B43_NPHY_AFECTL_C2;
3459 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3460 tmp[2] = b43_phy_read(dev, afectl_core);
3461 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3462 tmp[4] = b43_phy_read(dev, rfctl[0]);
3463 tmp[5] = b43_phy_read(dev, rfctl[1]);
3465 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3466 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3467 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3468 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3470 b43_phy_set(dev, afectl_core, 0x0006);
3471 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3473 band = b43_current_band(dev->wl);
3475 if (nphy->rxcalparams & 0xFF000000) {
3476 if (band == IEEE80211_BAND_5GHZ)
3477 b43_phy_write(dev, rfctl[0], 0x140);
3479 b43_phy_write(dev, rfctl[0], 0x110);
3481 if (band == IEEE80211_BAND_5GHZ)
3482 b43_phy_write(dev, rfctl[0], 0x180);
3484 b43_phy_write(dev, rfctl[0], 0x120);
3487 if (band == IEEE80211_BAND_5GHZ)
3488 b43_phy_write(dev, rfctl[1], 0x148);
3490 b43_phy_write(dev, rfctl[1], 0x114);
3492 if (nphy->rxcalparams & 0x10000) {
3493 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3495 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3499 for (j = 0; j < 4; j++) {
3505 if (power[1] > 10000) {
3510 if (power[0] > 10000) {
3520 cur_lna = lna[index];
3521 cur_hpf1 = hpf1[index];
3522 cur_hpf2 = hpf2[index];
3523 cur_hpf += desired - hweight32(power[index]);
3524 cur_hpf = clamp_val(cur_hpf, 0, 10);
3531 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3533 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3535 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3536 b43_nphy_stop_playback(dev);
3539 ret = b43_nphy_tx_tone(dev, 4000,
3540 (nphy->rxcalparams & 0xFFFF),
3544 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3550 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3559 power[i] = ((real + imag) / 1024) + 1;
3561 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3563 b43_nphy_stop_playback(dev);
3570 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3571 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3572 b43_phy_write(dev, rfctl[1], tmp[5]);
3573 b43_phy_write(dev, rfctl[0], tmp[4]);
3574 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3575 b43_phy_write(dev, afectl_core, tmp[2]);
3576 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3582 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3583 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3584 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3586 b43_nphy_stay_in_carrier_search(dev, 0);
3591 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3592 struct nphy_txgains target, u8 type, bool debug)
3597 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3598 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3599 struct nphy_txgains target, u8 type, bool debug)
3601 if (dev->phy.rev >= 3)
3602 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3604 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3607 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3608 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3610 struct b43_phy *phy = &dev->phy;
3611 struct b43_phy_n *nphy = phy->n;
3612 /* u16 buf[16]; it's rev3+ */
3614 nphy->phyrxchain = mask;
3616 if (0 /* FIXME clk */)
3619 b43_mac_suspend(dev);
3621 if (nphy->hang_avoid)
3622 b43_nphy_stay_in_carrier_search(dev, true);
3624 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3625 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3627 if ((mask & 0x3) != 0x3) {
3628 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3629 if (dev->phy.rev >= 3) {
3633 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3634 if (dev->phy.rev >= 3) {
3639 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3641 if (nphy->hang_avoid)
3642 b43_nphy_stay_in_carrier_search(dev, false);
3644 b43_mac_enable(dev);
3649 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3651 int b43_phy_initn(struct b43_wldev *dev)
3653 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3654 struct b43_phy *phy = &dev->phy;
3655 struct b43_phy_n *nphy = phy->n;
3657 struct nphy_txgains target;
3659 enum ieee80211_band tmp2;
3663 bool do_cal = false;
3665 if ((dev->phy.rev >= 3) &&
3666 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3667 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3668 switch (dev->dev->bus_type) {
3669 #ifdef CONFIG_B43_BCMA
3671 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3672 BCMA_CC_CHIPCTL, 0x40);
3675 #ifdef CONFIG_B43_SSB
3677 chipco_set32(&dev->dev->sdev->bus->chipco,
3678 SSB_CHIPCO_CHIPCTL, 0x40);
3683 nphy->deaf_count = 0;
3684 b43_nphy_tables_init(dev);
3685 nphy->crsminpwr_adjusted = false;
3686 nphy->noisevars_adjusted = false;
3688 /* Clear all overrides */
3689 if (dev->phy.rev >= 3) {
3690 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3691 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3692 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3693 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3695 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3697 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3698 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3699 if (dev->phy.rev < 6) {
3700 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3701 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3703 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3704 ~(B43_NPHY_RFSEQMODE_CAOVER |
3705 B43_NPHY_RFSEQMODE_TROVER));
3706 if (dev->phy.rev >= 3)
3707 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3708 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3710 if (dev->phy.rev <= 2) {
3711 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3712 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3713 ~B43_NPHY_BPHY_CTL3_SCALE,
3714 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3716 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3717 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3719 if (sprom->boardflags2_lo & 0x100 ||
3720 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3721 dev->dev->board_type == 0x8B))
3722 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3724 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3725 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3726 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3727 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3729 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3730 b43_nphy_update_txrx_chain(dev);
3733 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3734 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3737 tmp2 = b43_current_band(dev->wl);
3738 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3739 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3740 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3741 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3742 nphy->papd_epsilon_offset[0] << 7);
3743 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3744 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3745 nphy->papd_epsilon_offset[1] << 7);
3746 b43_nphy_int_pa_set_tx_dig_filters(dev);
3747 } else if (phy->rev >= 5) {
3748 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3751 b43_nphy_workarounds(dev);
3753 /* Reset CCA, in init code it differs a little from standard way */
3754 b43_phy_force_clock(dev, 1);
3755 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3756 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3757 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3758 b43_phy_force_clock(dev, 0);
3760 b43_mac_phy_clock_set(dev, true);
3762 b43_nphy_pa_override(dev, false);
3763 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3764 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3765 b43_nphy_pa_override(dev, true);
3767 b43_nphy_classifier(dev, 0, 0);
3768 b43_nphy_read_clip_detection(dev, clip);
3769 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3770 b43_nphy_bphy_init(dev);
3772 tx_pwr_state = nphy->txpwrctrl;
3773 b43_nphy_tx_power_ctrl(dev, false);
3774 b43_nphy_tx_power_fix(dev);
3775 /* TODO N PHY TX Power Control Idle TSSI */
3776 /* TODO N PHY TX Power Control Setup */
3778 if (phy->rev >= 3) {
3781 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3782 b43_ntab_tx_gain_rev0_1_2);
3783 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3784 b43_ntab_tx_gain_rev0_1_2);
3787 if (nphy->phyrxchain != 3)
3788 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3789 if (nphy->mphase_cal_phase_id > 0)
3790 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3792 do_rssi_cal = false;
3793 if (phy->rev >= 3) {
3794 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3795 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3797 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3800 b43_nphy_rssi_cal(dev);
3802 b43_nphy_restore_rssi_cal(dev);
3804 b43_nphy_rssi_cal(dev);
3807 if (!((nphy->measure_hold & 0x6) != 0)) {
3808 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3809 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3811 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3817 target = b43_nphy_get_tx_gains(dev);
3819 if (nphy->antsel_type == 2)
3820 b43_nphy_superswitch_init(dev, true);
3821 if (nphy->perical != 2) {
3822 b43_nphy_rssi_cal(dev);
3823 if (phy->rev >= 3) {
3824 nphy->cal_orig_pwr_idx[0] =
3825 nphy->txpwrindex[0].index_internal;
3826 nphy->cal_orig_pwr_idx[1] =
3827 nphy->txpwrindex[1].index_internal;
3828 /* TODO N PHY Pre Calibrate TX Gain */
3829 target = b43_nphy_get_tx_gains(dev);
3831 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3832 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3833 b43_nphy_save_cal(dev);
3834 } else if (nphy->mphase_cal_phase_id == 0)
3835 ;/* N PHY Periodic Calibration with arg 3 */
3837 b43_nphy_restore_cal(dev);
3841 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3842 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3843 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3844 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3845 if (phy->rev >= 3 && phy->rev <= 6)
3846 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3847 b43_nphy_tx_lp_fbw(dev);
3849 b43_nphy_spur_workaround(dev);
3854 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3855 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3856 const struct b43_phy_n_sfo_cfg *e,
3857 struct ieee80211_channel *new_channel)
3859 struct b43_phy *phy = &dev->phy;
3860 struct b43_phy_n *nphy = dev->phy.n;
3866 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3867 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3868 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3869 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3870 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3871 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3872 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3873 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3874 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3875 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3876 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3877 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3878 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3881 b43_chantab_phy_upload(dev, e);
3883 if (new_channel->hw_value == 14) {
3884 b43_nphy_classifier(dev, 2, 0);
3885 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3887 b43_nphy_classifier(dev, 2, 2);
3888 if (new_channel->band == IEEE80211_BAND_2GHZ)
3889 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3892 if (!nphy->txpwrctrl)
3893 b43_nphy_tx_power_fix(dev);
3895 if (dev->phy.rev < 3)
3896 b43_nphy_adjust_lna_gain_table(dev);
3898 b43_nphy_tx_lp_fbw(dev);
3900 if (dev->phy.rev >= 3 && 0) {
3904 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3907 b43_nphy_spur_workaround(dev);
3910 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3911 static int b43_nphy_set_channel(struct b43_wldev *dev,
3912 struct ieee80211_channel *channel,
3913 enum nl80211_channel_type channel_type)
3915 struct b43_phy *phy = &dev->phy;
3917 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
3918 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
3922 if (dev->phy.rev >= 3) {
3923 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3924 channel->center_freq);
3928 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3934 /* Channel is set later in common code, but we need to set it on our
3935 own to let this function's subcalls work properly. */
3936 phy->channel = channel->hw_value;
3937 phy->channel_freq = channel->center_freq;
3939 if (b43_channel_type_is_40mhz(phy->channel_type) !=
3940 b43_channel_type_is_40mhz(channel_type))
3941 ; /* TODO: BMAC BW Set (channel_type) */
3943 if (channel_type == NL80211_CHAN_HT40PLUS)
3944 b43_phy_set(dev, B43_NPHY_RXCTL,
3945 B43_NPHY_RXCTL_BSELU20);
3946 else if (channel_type == NL80211_CHAN_HT40MINUS)
3947 b43_phy_mask(dev, B43_NPHY_RXCTL,
3948 ~B43_NPHY_RXCTL_BSELU20);
3950 if (dev->phy.rev >= 3) {
3951 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3952 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3953 b43_radio_2056_setup(dev, tabent_r3);
3954 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3956 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3957 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3958 b43_radio_2055_setup(dev, tabent_r2);
3959 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3965 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3967 struct b43_phy_n *nphy;
3969 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3977 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3979 struct b43_phy *phy = &dev->phy;
3980 struct b43_phy_n *nphy = phy->n;
3982 memset(nphy, 0, sizeof(*nphy));
3984 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
3985 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3986 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3987 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
3988 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
3989 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
3990 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
3991 nphy->tx_pwr_idx[0] = 128;
3992 nphy->tx_pwr_idx[1] = 128;
3995 static void b43_nphy_op_free(struct b43_wldev *dev)
3997 struct b43_phy *phy = &dev->phy;
3998 struct b43_phy_n *nphy = phy->n;
4004 static int b43_nphy_op_init(struct b43_wldev *dev)
4006 return b43_phy_initn(dev);
4009 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4012 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4013 /* OFDM registers are onnly available on A/G-PHYs */
4014 b43err(dev->wl, "Invalid OFDM PHY access at "
4015 "0x%04X on N-PHY\n", offset);
4018 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4019 /* Ext-G registers are only available on G-PHYs */
4020 b43err(dev->wl, "Invalid EXT-G PHY access at "
4021 "0x%04X on N-PHY\n", offset);
4024 #endif /* B43_DEBUG */
4027 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4029 check_phyreg(dev, reg);
4030 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4031 return b43_read16(dev, B43_MMIO_PHY_DATA);
4034 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4036 check_phyreg(dev, reg);
4037 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4038 b43_write16(dev, B43_MMIO_PHY_DATA, value);
4041 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4044 check_phyreg(dev, reg);
4045 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4046 b43_write16(dev, B43_MMIO_PHY_DATA,
4047 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4050 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4052 /* Register 1 is a 32-bit register. */
4053 B43_WARN_ON(reg == 1);
4054 /* N-PHY needs 0x100 for read access */
4057 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4058 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4061 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4063 /* Register 1 is a 32-bit register. */
4064 B43_WARN_ON(reg == 1);
4066 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4067 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4070 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4071 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4074 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4075 b43err(dev->wl, "MAC not suspended\n");
4078 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4079 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4080 if (dev->phy.rev >= 3) {
4081 b43_radio_mask(dev, 0x09, ~0x2);
4083 b43_radio_write(dev, 0x204D, 0);
4084 b43_radio_write(dev, 0x2053, 0);
4085 b43_radio_write(dev, 0x2058, 0);
4086 b43_radio_write(dev, 0x205E, 0);
4087 b43_radio_mask(dev, 0x2062, ~0xF0);
4088 b43_radio_write(dev, 0x2064, 0);
4090 b43_radio_write(dev, 0x304D, 0);
4091 b43_radio_write(dev, 0x3053, 0);
4092 b43_radio_write(dev, 0x3058, 0);
4093 b43_radio_write(dev, 0x305E, 0);
4094 b43_radio_mask(dev, 0x3062, ~0xF0);
4095 b43_radio_write(dev, 0x3064, 0);
4098 if (dev->phy.rev >= 3) {
4099 b43_radio_init2056(dev);
4100 b43_switch_channel(dev, dev->phy.channel);
4102 b43_radio_init2055(dev);
4107 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4108 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4110 u16 override = on ? 0x0 : 0x7FFF;
4111 u16 core = on ? 0xD : 0x00FD;
4113 if (dev->phy.rev >= 3) {
4115 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4116 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4117 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4118 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4120 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4121 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4122 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4123 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4126 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4130 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4131 unsigned int new_channel)
4133 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4134 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4136 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4137 if ((new_channel < 1) || (new_channel > 14))
4140 if (new_channel > 200)
4144 return b43_nphy_set_channel(dev, channel, channel_type);
4147 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4149 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4154 const struct b43_phy_operations b43_phyops_n = {
4155 .allocate = b43_nphy_op_allocate,
4156 .free = b43_nphy_op_free,
4157 .prepare_structs = b43_nphy_op_prepare_structs,
4158 .init = b43_nphy_op_init,
4159 .phy_read = b43_nphy_op_read,
4160 .phy_write = b43_nphy_op_write,
4161 .phy_maskset = b43_nphy_op_maskset,
4162 .radio_read = b43_nphy_op_radio_read,
4163 .radio_write = b43_nphy_op_radio_write,
4164 .software_rfkill = b43_nphy_op_software_rfkill,
4165 .switch_analog = b43_nphy_op_switch_analog,
4166 .switch_channel = b43_nphy_op_switch_channel,
4167 .get_default_chan = b43_nphy_op_get_default_chan,
4168 .recalc_txpower = b43_nphy_op_recalc_txpower,
4169 .adjust_txpower = b43_nphy_op_adjust_txpower,