drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/types.h>
  28
  29 #include "b43.h"
  30 #include "phy_n.h"
  31 #include "tables_nphy.h"
  32 #include "radio_2055.h"
  33 #include "radio_2056.h"
  34 #include "main.h"
  35
  36 struct nphy_txgains {
  37         u16 txgm[2];
  38         u16 pga[2];
  39         u16 pad[2];
  40         u16 ipa[2];
  41 };
  42
  43 struct nphy_iqcal_params {
  44         u16 txgm;
  45         u16 pga;
  46         u16 pad;
  47         u16 ipa;
  48         u16 cal_gain;
  49         u16 ncorr[5];
  50 };
  51
  52 struct nphy_iq_est {
  53         s32 iq0_prod;
  54         u32 i0_pwr;
  55         u32 q0_pwr;
  56         s32 iq1_prod;
  57         u32 i1_pwr;
  58         u32 q1_pwr;
  59 };
  60
  61 enum b43_nphy_rf_sequence {
  62         B43_RFSEQ_RX2TX,
  63         B43_RFSEQ_TX2RX,
  64         B43_RFSEQ_RESET2RX,
  65         B43_RFSEQ_UPDATE_GAINH,
  66         B43_RFSEQ_UPDATE_GAINL,
  67         B43_RFSEQ_UPDATE_GAINU,
  68 };
  69
  70 enum b43_nphy_rssi_type {
  71         B43_NPHY_RSSI_X = 0,
  72         B43_NPHY_RSSI_Y,
  73         B43_NPHY_RSSI_Z,
  74         B43_NPHY_RSSI_PWRDET,
  75         B43_NPHY_RSSI_TSSI_I,
  76         B43_NPHY_RSSI_TSSI_Q,
  77         B43_NPHY_RSSI_TBD,
  78 };
  79
  80 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
  81                                                 bool enable);
  82 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  83                                         u8 *events, u8 *delays, u8 length);
  84 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  85                                        enum b43_nphy_rf_sequence seq);
  86 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  87                                                 u16 value, u8 core, bool off);
  88 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  89                                                 u16 value, u8 core);
  90
  91 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  92 {//TODO
  93 }
  94
  95 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  96 {//TODO
  97 }
  98
  99 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
 100                                                         bool ignore_tssi)
 101 {//TODO
 102         return B43_TXPWR_RES_DONE;
 103 }
 104
 105 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 106                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 107 {
 108         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 109         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 110         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 111         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 112         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 113
 114         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 115         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 116         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 117         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 118         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 119
 120         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 121         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 122         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 123         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 124         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 125
 126         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 127         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 128         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 129         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 130         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 131
 132         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 133         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 134         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 135         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 136         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 137
 138         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 139         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 140 }
 141
 142 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 143                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 144 {
 145         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 146         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 147         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 148         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 149         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 150         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 151                                         e->radio_syn_pll_loopfilter1);
 152         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 153                                         e->radio_syn_pll_loopfilter2);
 154         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 155                                         e->radio_syn_pll_loopfilter3);
 156         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 157                                         e->radio_syn_pll_loopfilter4);
 158         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 159                                         e->radio_syn_pll_loopfilter5);
 160         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 161                                         e->radio_syn_reserved_addr27);
 162         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 163                                         e->radio_syn_reserved_addr28);
 164         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 165                                         e->radio_syn_reserved_addr29);
 166         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 167                                         e->radio_syn_logen_vcobuf1);
 168         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 169         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 170         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 171
 172         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 173                                         e->radio_rx0_lnaa_tune);
 174         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 175                                         e->radio_rx0_lnag_tune);
 176
 177         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 178                                         e->radio_tx0_intpaa_boost_tune);
 179         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 180                                         e->radio_tx0_intpag_boost_tune);
 181         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 182                                         e->radio_tx0_pada_boost_tune);
 183         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 184                                         e->radio_tx0_padg_boost_tune);
 185         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 186                                         e->radio_tx0_pgaa_boost_tune);
 187         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 188                                         e->radio_tx0_pgag_boost_tune);
 189         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 190                                         e->radio_tx0_mixa_boost_tune);
 191         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 192                                         e->radio_tx0_mixg_boost_tune);
 193
 194         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 195                                         e->radio_rx1_lnaa_tune);
 196         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 197                                         e->radio_rx1_lnag_tune);
 198
 199         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 200                                         e->radio_tx1_intpaa_boost_tune);
 201         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 202                                         e->radio_tx1_intpag_boost_tune);
 203         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 204                                         e->radio_tx1_pada_boost_tune);
 205         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 206                                         e->radio_tx1_padg_boost_tune);
 207         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 208                                         e->radio_tx1_pgaa_boost_tune);
 209         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 210                                         e->radio_tx1_pgag_boost_tune);
 211         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 212                                         e->radio_tx1_mixa_boost_tune);
 213         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 214                                         e->radio_tx1_mixg_boost_tune);
 215 }
 216
 217 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 218 static void b43_radio_2056_setup(struct b43_wldev *dev,
 219                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 220 {
 221         B43_WARN_ON(dev->phy.rev < 3);
 222
 223         b43_chantab_radio_2056_upload(dev, e);
 224         /* TODO */
 225         udelay(50);
 226         /* VCO calibration */
 227         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 228         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 229         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 230         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 231         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 232         udelay(300);
 233 }
 234
 235 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 236                                    const struct b43_phy_n_sfo_cfg *e)
 237 {
 238         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 239         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 240         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 241         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 242         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 243         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 244 }
 245
 246 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
 247 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
 248 {
 249         struct b43_phy_n *nphy = dev->phy.n;
 250         u8 i;
 251         u16 tmp;
 252
 253         if (nphy->hang_avoid)
 254                 b43_nphy_stay_in_carrier_search(dev, 1);
 255
 256         nphy->txpwrctrl = enable;
 257         if (!enable) {
 258                 if (dev->phy.rev >= 3)
 259                         ; /* TODO */
 260
 261                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
 262                 for (i = 0; i < 84; i++)
 263                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 264
 265                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
 266                 for (i = 0; i < 84; i++)
 267                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 268
 269                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 270                 if (dev->phy.rev >= 3)
 271                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 272                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
 273
 274                 if (dev->phy.rev >= 3) {
 275                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 276                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 277                 } else {
 278                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 279                 }
 280
 281                 if (dev->phy.rev == 2)
 282                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 283                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
 284                 else if (dev->phy.rev < 2)
 285                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 286                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
 287
 288                 if (dev->phy.rev < 2 && 0)
 289                         ; /* TODO */
 290         } else {
 291                 b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
 292         }
 293
 294         if (nphy->hang_avoid)
 295                 b43_nphy_stay_in_carrier_search(dev, 0);
 296 }
 297
 298 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
 299 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 300 {
 301         struct b43_phy_n *nphy = dev->phy.n;
 302         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 303
 304         u8 txpi[2], bbmult, i;
 305         u16 tmp, radio_gain, dac_gain;
 306         u16 freq = dev->phy.channel_freq;
 307         u32 txgain;
 308         /* u32 gaintbl; rev3+ */
 309
 310         if (nphy->hang_avoid)
 311                 b43_nphy_stay_in_carrier_search(dev, 1);
 312
 313         if (dev->phy.rev >= 3) {
 314                 txpi[0] = 40;
 315                 txpi[1] = 40;
 316         } else if (sprom->revision < 4) {
 317                 txpi[0] = 72;
 318                 txpi[1] = 72;
 319         } else {
 320                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 321                         txpi[0] = sprom->txpid2g[0];
 322                         txpi[1] = sprom->txpid2g[1];
 323                 } else if (freq >= 4900 && freq < 5100) {
 324                         txpi[0] = sprom->txpid5gl[0];
 325                         txpi[1] = sprom->txpid5gl[1];
 326                 } else if (freq >= 5100 && freq < 5500) {
 327                         txpi[0] = sprom->txpid5g[0];
 328                         txpi[1] = sprom->txpid5g[1];
 329                 } else if (freq >= 5500) {
 330                         txpi[0] = sprom->txpid5gh[0];
 331                         txpi[1] = sprom->txpid5gh[1];
 332                 } else {
 333                         txpi[0] = 91;
 334                         txpi[1] = 91;
 335                 }
 336         }
 337
 338         /*
 339         for (i = 0; i < 2; i++) {
 340                 nphy->txpwrindex[i].index_internal = txpi[i];
 341                 nphy->txpwrindex[i].index_internal_save = txpi[i];
 342         }
 343         */
 344
 345         for (i = 0; i < 2; i++) {
 346                 if (dev->phy.rev >= 3) {
 347                         /* FIXME: support 5GHz */
 348                         txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
 349                         radio_gain = (txgain >> 16) & 0x1FFFF;
 350                 } else {
 351                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
 352                         radio_gain = (txgain >> 16) & 0x1FFF;
 353                 }
 354
 355                 dac_gain = (txgain >> 8) & 0x3F;
 356                 bbmult = txgain & 0xFF;
 357
 358                 if (dev->phy.rev >= 3) {
 359                         if (i == 0)
 360                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 361                         else
 362                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 363                 } else {
 364                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 365                 }
 366
 367                 if (i == 0)
 368                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
 369                 else
 370                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
 371
 372                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
 373                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
 374
 375                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 376                 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 377
 378                 if (i == 0)
 379                         tmp = (tmp & 0x00FF) | (bbmult << 8);
 380                 else
 381                         tmp = (tmp & 0xFF00) | bbmult;
 382
 383                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 384                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
 385
 386                 if (0)
 387                         ; /* TODO */
 388         }
 389
 390         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
 391
 392         if (nphy->hang_avoid)
 393                 b43_nphy_stay_in_carrier_search(dev, 0);
 394 }
 395
 396
 397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 398 static void b43_radio_2055_setup(struct b43_wldev *dev,
 399                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 400 {
 401         B43_WARN_ON(dev->phy.rev >= 3);
 402
 403         b43_chantab_radio_upload(dev, e);
 404         udelay(50);
 405         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 406         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 407         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 408         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 409         udelay(300);
 410 }
 411
 412 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 413 {
 414         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 415                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 416         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 417                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 418                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 419         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 420                     B43_NPHY_RFCTL_CMD_PORFORCE);
 421 }
 422
 423 static void b43_radio_init2055_post(struct b43_wldev *dev)
 424 {
 425         struct b43_phy_n *nphy = dev->phy.n;
 426         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 427         int i;
 428         u16 val;
 429         bool workaround = false;
 430
 431         if (sprom->revision < 4)
 432                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
 433                               && dev->dev->board_type == 0x46D
 434                               && dev->dev->board_rev >= 0x41);
 435         else
 436                 workaround =
 437                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 438
 439         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 440         if (workaround) {
 441                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 442                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 443         }
 444         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 445         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 446         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 447         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 448         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 449         msleep(1);
 450         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 451         for (i = 0; i < 200; i++) {
 452                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 453                 if (val & 0x80) {
 454                         i = 0;
 455                         break;
 456                 }
 457                 udelay(10);
 458         }
 459         if (i)
 460                 b43err(dev->wl, "radio post init timeout\n");
 461         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 462         b43_switch_channel(dev, dev->phy.channel);
 463         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 464         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 465         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 466         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 467         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 468         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 469         if (!nphy->gain_boost) {
 470                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 471                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 472         } else {
 473                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 474                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 475         }
 476         udelay(2);
 477 }
 478
 479 /*
 480  * Initialize a Broadcom 2055 N-radio
 481  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 482  */
 483 static void b43_radio_init2055(struct b43_wldev *dev)
 484 {
 485         b43_radio_init2055_pre(dev);
 486         if (b43_status(dev) < B43_STAT_INITIALIZED) {
 487                 /* Follow wl, not specs. Do not force uploading all regs */
 488                 b2055_upload_inittab(dev, 0, 0);
 489         } else {
 490                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 491                 b2055_upload_inittab(dev, ghz5, 0);
 492         }
 493         b43_radio_init2055_post(dev);
 494 }
 495
 496 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 497 {
 498         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 499                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 500         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 501         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 502                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 503         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 504                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 505         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 506                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 507 }
 508
 509 static void b43_radio_init2056_post(struct b43_wldev *dev)
 510 {
 511         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 512         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 513         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 514         msleep(1);
 515         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 516         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 517         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 518         /*
 519         if (nphy->init_por)
 520                 Call Radio 2056 Recalibrate
 521         */
 522 }
 523
 524 /*
 525  * Initialize a Broadcom 2056 N-radio
 526  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 527  */
 528 static void b43_radio_init2056(struct b43_wldev *dev)
 529 {
 530         b43_radio_init2056_pre(dev);
 531         b2056_upload_inittabs(dev, 0, 0);
 532         b43_radio_init2056_post(dev);
 533 }
 534
 535 /*
 536  * Upload the N-PHY tables.
 537  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 538  */
 539 static void b43_nphy_tables_init(struct b43_wldev *dev)
 540 {
 541         if (dev->phy.rev < 3)
 542                 b43_nphy_rev0_1_2_tables_init(dev);
 543         else
 544                 b43_nphy_rev3plus_tables_init(dev);
 545 }
 546
 547 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 548 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 549 {
 550         struct b43_phy_n *nphy = dev->phy.n;
 551         enum ieee80211_band band;
 552         u16 tmp;
 553
 554         if (!enable) {
 555                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 556                                                        B43_NPHY_RFCTL_INTC1);
 557                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 558                                                        B43_NPHY_RFCTL_INTC2);
 559                 band = b43_current_band(dev->wl);
 560                 if (dev->phy.rev >= 3) {
 561                         if (band == IEEE80211_BAND_5GHZ)
 562                                 tmp = 0x600;
 563                         else
 564                                 tmp = 0x480;
 565                 } else {
 566                         if (band == IEEE80211_BAND_5GHZ)
 567                                 tmp = 0x180;
 568                         else
 569                                 tmp = 0x120;
 570                 }
 571                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 572                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 573         } else {
 574                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 575                                 nphy->rfctrl_intc1_save);
 576                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 577                                 nphy->rfctrl_intc2_save);
 578         }
 579 }
 580
 581 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 582 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 583 {
 584         struct b43_phy_n *nphy = dev->phy.n;
 585         u16 tmp;
 586         enum ieee80211_band band = b43_current_band(dev->wl);
 587         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 588                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 589
 590         if (dev->phy.rev >= 3) {
 591                 if (ipa) {
 592                         tmp = 4;
 593                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 594                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 595                 }
 596
 597                 tmp = 1;
 598                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 599                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 600         }
 601 }
 602
 603 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 604 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 605 {
 606         u16 bbcfg;
 607
 608         b43_phy_force_clock(dev, 1);
 609         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 610         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 611         udelay(1);
 612         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 613         b43_phy_force_clock(dev, 0);
 614         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 615 }
 616
 617 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 618 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 619 {
 620         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 621
 622         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 623         if (preamble == 1)
 624                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 625         else
 626                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 627
 628         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 629 }
 630
 631 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 632 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 633 {
 634         struct b43_phy_n *nphy = dev->phy.n;
 635
 636         bool override = false;
 637         u16 chain = 0x33;
 638
 639         if (nphy->txrx_chain == 0) {
 640                 chain = 0x11;
 641                 override = true;
 642         } else if (nphy->txrx_chain == 1) {
 643                 chain = 0x22;
 644                 override = true;
 645         }
 646
 647         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 648                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 649                         chain);
 650
 651         if (override)
 652                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 653                                 B43_NPHY_RFSEQMODE_CAOVER);
 654         else
 655                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 656                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 657 }
 658
 659 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 660 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 661                                 u16 samps, u8 time, bool wait)
 662 {
 663         int i;
 664         u16 tmp;
 665
 666         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 667         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 668         if (wait)
 669                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 670         else
 671                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 672
 673         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 674
 675         for (i = 1000; i; i--) {
 676                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 677                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 678                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 679                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 680                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 681                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 682                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 683                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 684
 685                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 686                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 687                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 688                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 689                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 690                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 691                         return;
 692                 }
 693                 udelay(10);
 694         }
 695         memset(est, 0, sizeof(*est));
 696 }
 697
 698 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 699 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 700                                         struct b43_phy_n_iq_comp *pcomp)
 701 {
 702         if (write) {
 703                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 704                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 705                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 706                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 707         } else {
 708                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 709                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 710                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 711                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 712         }
 713 }
 714
 715 #if 0
 716 /* Ready but not used anywhere */
 717 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 718 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 719 {
 720         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 721
 722         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 723         if (core == 0) {
 724                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 725                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 726         } else {
 727                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 728                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 729         }
 730         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 731         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 732         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 733         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 734         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 735         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 736         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 737         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 738 }
 739
 740 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 741 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 742 {
 743         u8 rxval, txval;
 744         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 745
 746         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 747         if (core == 0) {
 748                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 749                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 750         } else {
 751                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 752                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 753         }
 754         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 755         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 756         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 757         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 758         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 759         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 760         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 761         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 762
 763         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 764         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 765
 766         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 767                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
 768                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 769         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 770                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 771         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 772                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 773         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 774                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 775
 776         if (core == 0) {
 777                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 778                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 779         } else {
 780                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 781                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 782         }
 783
 784         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 785         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 786         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 787
 788         if (core == 0) {
 789                 rxval = 1;
 790                 txval = 8;
 791         } else {
 792                 rxval = 4;
 793                 txval = 2;
 794         }
 795         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 796         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 797 }
 798 #endif
 799
 800 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 801 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 802 {
 803         int i;
 804         s32 iq;
 805         u32 ii;
 806         u32 qq;
 807         int iq_nbits, qq_nbits;
 808         int arsh, brsh;
 809         u16 tmp, a, b;
 810
 811         struct nphy_iq_est est;
 812         struct b43_phy_n_iq_comp old;
 813         struct b43_phy_n_iq_comp new = { };
 814         bool error = false;
 815
 816         if (mask == 0)
 817                 return;
 818
 819         b43_nphy_rx_iq_coeffs(dev, false, &old);
 820         b43_nphy_rx_iq_coeffs(dev, true, &new);
 821         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 822         new = old;
 823
 824         for (i = 0; i < 2; i++) {
 825                 if (i == 0 && (mask & 1)) {
 826                         iq = est.iq0_prod;
 827                         ii = est.i0_pwr;
 828                         qq = est.q0_pwr;
 829                 } else if (i == 1 && (mask & 2)) {
 830                         iq = est.iq1_prod;
 831                         ii = est.i1_pwr;
 832                         qq = est.q1_pwr;
 833                 } else {
 834                         continue;
 835                 }
 836
 837                 if (ii + qq < 2) {
 838                         error = true;
 839                         break;
 840                 }
 841
 842                 iq_nbits = fls(abs(iq));
 843                 qq_nbits = fls(qq);
 844
 845                 arsh = iq_nbits - 20;
 846                 if (arsh >= 0) {
 847                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 848                         tmp = ii >> arsh;
 849                 } else {
 850                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 851                         tmp = ii << -arsh;
 852                 }
 853                 if (tmp == 0) {
 854                         error = true;
 855                         break;
 856                 }
 857                 a /= tmp;
 858
 859                 brsh = qq_nbits - 11;
 860                 if (brsh >= 0) {
 861                         b = (qq << (31 - qq_nbits));
 862                         tmp = ii >> brsh;
 863                 } else {
 864                         b = (qq << (31 - qq_nbits));
 865                         tmp = ii << -brsh;
 866                 }
 867                 if (tmp == 0) {
 868                         error = true;
 869                         break;
 870                 }
 871                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 872
 873                 if (i == 0 && (mask & 0x1)) {
 874                         if (dev->phy.rev >= 3) {
 875                                 new.a0 = a & 0x3FF;
 876                                 new.b0 = b & 0x3FF;
 877                         } else {
 878                                 new.a0 = b & 0x3FF;
 879                                 new.b0 = a & 0x3FF;
 880                         }
 881                 } else if (i == 1 && (mask & 0x2)) {
 882                         if (dev->phy.rev >= 3) {
 883                                 new.a1 = a & 0x3FF;
 884                                 new.b1 = b & 0x3FF;
 885                         } else {
 886                                 new.a1 = b & 0x3FF;
 887                                 new.b1 = a & 0x3FF;
 888                         }
 889                 }
 890         }
 891
 892         if (error)
 893                 new = old;
 894
 895         b43_nphy_rx_iq_coeffs(dev, true, &new);
 896 }
 897
 898 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 899 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 900 {
 901         u16 array[4];
 902         int i;
 903
 904         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 905         for (i = 0; i < 4; i++)
 906                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 907
 908         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 909         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 910         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 911         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 912 }
 913
 914 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 915 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 916                                           const u16 *clip_st)
 917 {
 918         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 919         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 920 }
 921
 922 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 923 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 924 {
 925         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 926         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 927 }
 928
 929 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 930 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 931 {
 932         if (dev->phy.rev >= 3) {
 933                 if (!init)
 934                         return;
 935                 if (0 /* FIXME */) {
 936                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 937                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 938                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 939                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 940                 }
 941         } else {
 942                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 943                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 944
 945                 switch (dev->dev->bus_type) {
 946 #ifdef CONFIG_B43_BCMA
 947                 case B43_BUS_BCMA:
 948                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
 949                                                  0xFC00, 0xFC00);
 950                         break;
 951 #endif
 952 #ifdef CONFIG_B43_SSB
 953                 case B43_BUS_SSB:
 954                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
 955                                                 0xFC00, 0xFC00);
 956                         break;
 957 #endif
 958                 }
 959
 960                 b43_write32(dev, B43_MMIO_MACCTL,
 961                         b43_read32(dev, B43_MMIO_MACCTL) &
 962                         ~B43_MACCTL_GPOUTSMSK);
 963                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 964                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 965                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 966                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 967
 968                 if (init) {
 969                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 970                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 971                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 972                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 973                 }
 974         }
 975 }
 976
 977 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 978 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 979 {
 980         u16 tmp;
 981
 982         if (dev->dev->core_rev == 16)
 983                 b43_mac_suspend(dev);
 984
 985         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 986         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 987                 B43_NPHY_CLASSCTL_WAITEDEN);
 988         tmp &= ~mask;
 989         tmp |= (val & mask);
 990         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 991
 992         if (dev->dev->core_rev == 16)
 993                 b43_mac_enable(dev);
 994
 995         return tmp;
 996 }
 997
 998 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 999 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1000 {
1001         struct b43_phy *phy = &dev->phy;
1002         struct b43_phy_n *nphy = phy->n;
1003
1004         if (enable) {
1005                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1006                 if (nphy->deaf_count++ == 0) {
1007                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1008                         b43_nphy_classifier(dev, 0x7, 0);
1009                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
1010                         b43_nphy_write_clip_detection(dev, clip);
1011                 }
1012                 b43_nphy_reset_cca(dev);
1013         } else {
1014                 if (--nphy->deaf_count == 0) {
1015                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1016                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
1017                 }
1018         }
1019 }
1020
1021 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1022 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1023 {
1024         struct b43_phy_n *nphy = dev->phy.n;
1025         u16 tmp;
1026
1027         if (nphy->hang_avoid)
1028                 b43_nphy_stay_in_carrier_search(dev, 1);
1029
1030         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1031         if (tmp & 0x1)
1032                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1033         else if (tmp & 0x2)
1034                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1035
1036         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1037
1038         if (nphy->bb_mult_save & 0x80000000) {
1039                 tmp = nphy->bb_mult_save & 0xFFFF;
1040                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1041                 nphy->bb_mult_save = 0;
1042         }
1043
1044         if (nphy->hang_avoid)
1045                 b43_nphy_stay_in_carrier_search(dev, 0);
1046 }
1047
1048 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1049 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1050 {
1051         struct b43_phy_n *nphy = dev->phy.n;
1052
1053         u8 channel = dev->phy.channel;
1054         int tone[2] = { 57, 58 };
1055         u32 noise[2] = { 0x3FF, 0x3FF };
1056
1057         B43_WARN_ON(dev->phy.rev < 3);
1058
1059         if (nphy->hang_avoid)
1060                 b43_nphy_stay_in_carrier_search(dev, 1);
1061
1062         if (nphy->gband_spurwar_en) {
1063                 /* TODO: N PHY Adjust Analog Pfbw (7) */
1064                 if (channel == 11 && dev->phy.is_40mhz)
1065                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1066                 else
1067                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1068                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1069         }
1070
1071         if (nphy->aband_spurwar_en) {
1072                 if (channel == 54) {
1073                         tone[0] = 0x20;
1074                         noise[0] = 0x25F;
1075                 } else if (channel == 38 || channel == 102 || channel == 118) {
1076                         if (0 /* FIXME */) {
1077                                 tone[0] = 0x20;
1078                                 noise[0] = 0x21F;
1079                         } else {
1080                                 tone[0] = 0;
1081                                 noise[0] = 0;
1082                         }
1083                 } else if (channel == 134) {
1084                         tone[0] = 0x20;
1085                         noise[0] = 0x21F;
1086                 } else if (channel == 151) {
1087                         tone[0] = 0x10;
1088                         noise[0] = 0x23F;
1089                 } else if (channel == 153 || channel == 161) {
1090                         tone[0] = 0x30;
1091                         noise[0] = 0x23F;
1092                 } else {
1093                         tone[0] = 0;
1094                         noise[0] = 0;
1095                 }
1096
1097                 if (!tone[0] && !noise[0])
1098                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1099                 else
1100                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1101         }
1102
1103         if (nphy->hang_avoid)
1104                 b43_nphy_stay_in_carrier_search(dev, 0);
1105 }
1106
1107 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1108 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1109 {
1110         struct b43_phy_n *nphy = dev->phy.n;
1111
1112         u8 i;
1113         s16 tmp;
1114         u16 data[4];
1115         s16 gain[2];
1116         u16 minmax[2];
1117         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1118
1119         if (nphy->hang_avoid)
1120                 b43_nphy_stay_in_carrier_search(dev, 1);
1121
1122         if (nphy->gain_boost) {
1123                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1124                         gain[0] = 6;
1125                         gain[1] = 6;
1126                 } else {
1127                         tmp = 40370 - 315 * dev->phy.channel;
1128                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1129                         tmp = 23242 - 224 * dev->phy.channel;
1130                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1131                 }
1132         } else {
1133                 gain[0] = 0;
1134                 gain[1] = 0;
1135         }
1136
1137         for (i = 0; i < 2; i++) {
1138                 if (nphy->elna_gain_config) {
1139                         data[0] = 19 + gain[i];
1140                         data[1] = 25 + gain[i];
1141                         data[2] = 25 + gain[i];
1142                         data[3] = 25 + gain[i];
1143                 } else {
1144                         data[0] = lna_gain[0] + gain[i];
1145                         data[1] = lna_gain[1] + gain[i];
1146                         data[2] = lna_gain[2] + gain[i];
1147                         data[3] = lna_gain[3] + gain[i];
1148                 }
1149                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1150
1151                 minmax[i] = 23 + gain[i];
1152         }
1153
1154         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1155                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1156         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1157                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1158
1159         if (nphy->hang_avoid)
1160                 b43_nphy_stay_in_carrier_search(dev, 0);
1161 }
1162
1163 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1164 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1165 {
1166         struct b43_phy_n *nphy = dev->phy.n;
1167         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1168
1169         /* PHY rev 0, 1, 2 */
1170         u8 i, j;
1171         u8 code;
1172         u16 tmp;
1173         u8 rfseq_events[3] = { 6, 8, 7 };
1174         u8 rfseq_delays[3] = { 10, 30, 1 };
1175
1176         /* PHY rev >= 3 */
1177         bool ghz5;
1178         bool ext_lna;
1179         u16 rssi_gain;
1180         struct nphy_gain_ctl_workaround_entry *e;
1181         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1182         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1183
1184         if (dev->phy.rev >= 3) {
1185                 /* Prepare values */
1186                 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1187                         & B43_NPHY_BANDCTL_5GHZ;
1188                 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1189                 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1190                 if (ghz5 && dev->phy.rev >= 5)
1191                         rssi_gain = 0x90;
1192                 else
1193                         rssi_gain = 0x50;
1194
1195                 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1196
1197                 /* Set Clip 2 detect */
1198                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1199                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1200                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1201                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1202
1203                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1204                                 0x17);
1205                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1206                                 0x17);
1207                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1208                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1209                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1210                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1211                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1212                                 rssi_gain);
1213                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1214                                 rssi_gain);
1215                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1216                                 0x17);
1217                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1218                                 0x17);
1219                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1220                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1221
1222                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1223                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1224                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1225                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1226                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1227                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1228                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1229                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1230                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1231                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1232                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1233                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1234
1235                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1236                 b43_phy_write(dev, 0x2A7, e->init_gain);
1237                 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1238                                         e->rfseq_init);
1239                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1240
1241                 /* TODO: check defines. Do not match variables names */
1242                 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1243                 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1244                 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1245                 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1246                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1247                 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1248
1249                 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1250                 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1251                 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1252                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1253                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1254                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1255                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1256                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1257                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1258                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1259         } else {
1260                 /* Set Clip 2 detect */
1261                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1262                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1263                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1264                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1265
1266                 /* Set narrowband clip threshold */
1267                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1268                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1269
1270                 if (!dev->phy.is_40mhz) {
1271                         /* Set dwell lengths */
1272                         b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1273                         b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1274                         b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1275                         b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1276                 }
1277
1278                 /* Set wideband clip 2 threshold */
1279                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1280                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1281                                 21);
1282                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1283                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1284                                 21);
1285
1286                 if (!dev->phy.is_40mhz) {
1287                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1288                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1289                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1290                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1291                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1292                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1293                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1294                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1295                 }
1296
1297                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1298
1299                 if (nphy->gain_boost) {
1300                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1301                             dev->phy.is_40mhz)
1302                                 code = 4;
1303                         else
1304                                 code = 5;
1305                 } else {
1306                         code = dev->phy.is_40mhz ? 6 : 7;
1307                 }
1308
1309                 /* Set HPVGA2 index */
1310                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1311                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1312                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1313                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1314                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1315                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1316
1317                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1318                 /* specs say about 2 loops, but wl does 4 */
1319                 for (i = 0; i < 4; i++)
1320                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1321                                                         (code << 8 | 0x7C));
1322
1323                 b43_nphy_adjust_lna_gain_table(dev);
1324
1325                 if (nphy->elna_gain_config) {
1326                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1327                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1328                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1329                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1330                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1331
1332                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1333                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1334                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1335                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1336                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1337
1338                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1339                         /* specs say about 2 loops, but wl does 4 */
1340                         for (i = 0; i < 4; i++)
1341                                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1342                                                         (code << 8 | 0x74));
1343                 }
1344
1345                 if (dev->phy.rev == 2) {
1346                         for (i = 0; i < 4; i++) {
1347                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1348                                                 (0x0400 * i) + 0x0020);
1349                                 for (j = 0; j < 21; j++) {
1350                                         tmp = j * (i < 2 ? 3 : 1);
1351                                         b43_phy_write(dev,
1352                                                 B43_NPHY_TABLE_DATALO, tmp);
1353                                 }
1354                         }
1355                 }
1356
1357                 b43_nphy_set_rf_sequence(dev, 5,
1358                                 rfseq_events, rfseq_delays, 3);
1359                 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1360                         ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1361                         0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1362
1363                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1364                         b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1365                                         0xFF80, 4);
1366         }
1367 }
1368
1369 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1370 static void b43_nphy_workarounds(struct b43_wldev *dev)
1371 {
1372         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1373         struct b43_phy *phy = &dev->phy;
1374         struct b43_phy_n *nphy = phy->n;
1375
1376         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1377         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1378
1379         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1380         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1381
1382         u16 tmp16;
1383         u32 tmp32;
1384
1385         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1386                 b43_nphy_classifier(dev, 1, 0);
1387         else
1388                 b43_nphy_classifier(dev, 1, 1);
1389
1390         if (nphy->hang_avoid)
1391                 b43_nphy_stay_in_carrier_search(dev, 1);
1392
1393         b43_phy_set(dev, B43_NPHY_IQFLIP,
1394                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1395
1396         if (dev->phy.rev >= 3) {
1397                 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1398                 tmp32 &= 0xffffff;
1399                 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1400
1401                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1402                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1403                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1404                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1405                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1406                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1407
1408                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1409                 b43_phy_write(dev, 0x2AE, 0x000C);
1410
1411                 /* TODO */
1412
1413                 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1414                         0x2 : 0x9C40;
1415                 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1416
1417                 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1418
1419                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1420                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1421
1422                 b43_nphy_gain_ctrl_workarounds(dev);
1423
1424                 b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1425                 b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1426
1427                 /* TODO */
1428
1429                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1430                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1431                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1432                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1433                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1434                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1435                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1436                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1437                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1438                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1439
1440                 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1441
1442                 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1443                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1444                     (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1445                     b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1446                         tmp32 = 0x00088888;
1447                 else
1448                         tmp32 = 0x88888888;
1449                 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1450                 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1451                 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1452
1453                 if (dev->phy.rev == 4 &&
1454                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1455                         b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1456                                         0x70);
1457                         b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1458                                         0x70);
1459                 }
1460
1461                 b43_phy_write(dev, 0x224, 0x039C);
1462                 b43_phy_write(dev, 0x225, 0x0357);
1463                 b43_phy_write(dev, 0x226, 0x0317);
1464                 b43_phy_write(dev, 0x227, 0x02D7);
1465                 b43_phy_write(dev, 0x228, 0x039C);
1466                 b43_phy_write(dev, 0x229, 0x0357);
1467                 b43_phy_write(dev, 0x22A, 0x0317);
1468                 b43_phy_write(dev, 0x22B, 0x02D7);
1469                 b43_phy_write(dev, 0x22C, 0x039C);
1470                 b43_phy_write(dev, 0x22D, 0x0357);
1471                 b43_phy_write(dev, 0x22E, 0x0317);
1472                 b43_phy_write(dev, 0x22F, 0x02D7);
1473         } else {
1474                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1475                     nphy->band5g_pwrgain) {
1476                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1477                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1478                 } else {
1479                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1480                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1481                 }
1482
1483                 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1484                 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1485                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1486                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1487
1488                 if (dev->phy.rev < 2) {
1489                         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1490                         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1491                         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1492                         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1493                         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1494                         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1495                 }
1496
1497                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1498                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1499                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1500                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1501
1502                 if (sprom->boardflags2_lo & 0x100 &&
1503                     dev->dev->board_type == 0x8B) {
1504                         delays1[0] = 0x1;
1505                         delays1[5] = 0x14;
1506                 }
1507                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1508                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1509
1510                 b43_nphy_gain_ctrl_workarounds(dev);
1511
1512                 if (dev->phy.rev < 2) {
1513                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1514                                 b43_hf_write(dev, b43_hf_read(dev) |
1515                                                 B43_HF_MLADVW);
1516                 } else if (dev->phy.rev == 2) {
1517                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1518                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1519                 }
1520
1521                 if (dev->phy.rev < 2)
1522                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1523                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1524
1525                 /* Set phase track alpha and beta */
1526                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1527                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1528                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1529                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1530                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1531                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1532
1533                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1534                                 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1535                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1536                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1537                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1538
1539                 if (dev->phy.rev == 2)
1540                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1541                                         B43_NPHY_FINERX2_CGC_DECGC);
1542         }
1543
1544         if (nphy->hang_avoid)
1545                 b43_nphy_stay_in_carrier_search(dev, 0);
1546 }
1547
1548 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1549 static int b43_nphy_load_samples(struct b43_wldev *dev,
1550                                         struct b43_c32 *samples, u16 len) {
1551         struct b43_phy_n *nphy = dev->phy.n;
1552         u16 i;
1553         u32 *data;
1554
1555         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1556         if (!data) {
1557                 b43err(dev->wl, "allocation for samples loading failed\n");
1558                 return -ENOMEM;
1559         }
1560         if (nphy->hang_avoid)
1561                 b43_nphy_stay_in_carrier_search(dev, 1);
1562
1563         for (i = 0; i < len; i++) {
1564                 data[i] = (samples[i].i & 0x3FF << 10);
1565                 data[i] |= samples[i].q & 0x3FF;
1566         }
1567         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1568
1569         kfree(data);
1570         if (nphy->hang_avoid)
1571                 b43_nphy_stay_in_carrier_search(dev, 0);
1572         return 0;
1573 }
1574
1575 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1576 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1577                                         bool test)
1578 {
1579         int i;
1580         u16 bw, len, rot, angle;
1581         struct b43_c32 *samples;
1582
1583
1584         bw = (dev->phy.is_40mhz) ? 40 : 20;
1585         len = bw << 3;
1586
1587         if (test) {
1588                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1589                         bw = 82;
1590                 else
1591                         bw = 80;
1592
1593                 if (dev->phy.is_40mhz)
1594                         bw <<= 1;
1595
1596                 len = bw << 1;
1597         }
1598
1599         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1600         if (!samples) {
1601                 b43err(dev->wl, "allocation for samples generation failed\n");
1602                 return 0;
1603         }
1604         rot = (((freq * 36) / bw) << 16) / 100;
1605         angle = 0;
1606
1607         for (i = 0; i < len; i++) {
1608                 samples[i] = b43_cordic(angle);
1609                 angle += rot;
1610                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1611                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1612         }
1613
1614         i = b43_nphy_load_samples(dev, samples, len);
1615         kfree(samples);
1616         return (i < 0) ? 0 : len;
1617 }
1618
1619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1620 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1621                                         u16 wait, bool iqmode, bool dac_test)
1622 {
1623         struct b43_phy_n *nphy = dev->phy.n;
1624         int i;
1625         u16 seq_mode;
1626         u32 tmp;
1627
1628         if (nphy->hang_avoid)
1629                 b43_nphy_stay_in_carrier_search(dev, true);
1630
1631         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1632                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1633                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1634         }
1635
1636         if (!dev->phy.is_40mhz)
1637                 tmp = 0x6464;
1638         else
1639                 tmp = 0x4747;
1640         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1641
1642         if (nphy->hang_avoid)
1643                 b43_nphy_stay_in_carrier_search(dev, false);
1644
1645         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1646
1647         if (loops != 0xFFFF)
1648                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1649         else
1650                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1651
1652         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1653
1654         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1655
1656         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1657         if (iqmode) {
1658                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1659                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1660         } else {
1661                 if (dac_test)
1662                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1663                 else
1664                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1665         }
1666         for (i = 0; i < 100; i++) {
1667                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1668                         i = 0;
1669                         break;
1670                 }
1671                 udelay(10);
1672         }
1673         if (i)
1674                 b43err(dev->wl, "run samples timeout\n");
1675
1676         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1677 }
1678
1679 /*
1680  * Transmits a known value for LO calibration
1681  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1682  */
1683 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1684                                 bool iqmode, bool dac_test)
1685 {
1686         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1687         if (samp == 0)
1688                 return -1;
1689         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1690         return 0;
1691 }
1692
1693 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1694 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1695 {
1696         struct b43_phy_n *nphy = dev->phy.n;
1697         int i, j;
1698         u32 tmp;
1699         u32 cur_real, cur_imag, real_part, imag_part;
1700
1701         u16 buffer[7];
1702
1703         if (nphy->hang_avoid)
1704                 b43_nphy_stay_in_carrier_search(dev, true);
1705
1706         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1707
1708         for (i = 0; i < 2; i++) {
1709                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1710                         (buffer[i * 2 + 1] & 0x3FF);
1711                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1712                                 (((i + 26) << 10) | 320));
1713                 for (j = 0; j < 128; j++) {
1714                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1715                                         ((tmp >> 16) & 0xFFFF));
1716                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1717                                         (tmp & 0xFFFF));
1718                 }
1719         }
1720
1721         for (i = 0; i < 2; i++) {
1722                 tmp = buffer[5 + i];
1723                 real_part = (tmp >> 8) & 0xFF;
1724                 imag_part = (tmp & 0xFF);
1725                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1726                                 (((i + 26) << 10) | 448));
1727
1728                 if (dev->phy.rev >= 3) {
1729                         cur_real = real_part;
1730                         cur_imag = imag_part;
1731                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1732                 }
1733
1734                 for (j = 0; j < 128; j++) {
1735                         if (dev->phy.rev < 3) {
1736                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1737                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1738                                 tmp = ((cur_real & 0xFF) << 8) |
1739                                         (cur_imag & 0xFF);
1740                         }
1741                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1742                                         ((tmp >> 16) & 0xFFFF));
1743                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1744                                         (tmp & 0xFFFF));
1745                 }
1746         }
1747
1748         if (dev->phy.rev >= 3) {
1749                 b43_shm_write16(dev, B43_SHM_SHARED,
1750                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1751                 b43_shm_write16(dev, B43_SHM_SHARED,
1752                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1753         }
1754
1755         if (nphy->hang_avoid)
1756                 b43_nphy_stay_in_carrier_search(dev, false);
1757 }
1758
1759 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1760 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1761                                         u8 *events, u8 *delays, u8 length)
1762 {
1763         struct b43_phy_n *nphy = dev->phy.n;
1764         u8 i;
1765         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1766         u16 offset1 = cmd << 4;
1767         u16 offset2 = offset1 + 0x80;
1768
1769         if (nphy->hang_avoid)
1770                 b43_nphy_stay_in_carrier_search(dev, true);
1771
1772         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1773         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1774
1775         for (i = length; i < 16; i++) {
1776                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1777                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1778         }
1779
1780         if (nphy->hang_avoid)
1781                 b43_nphy_stay_in_carrier_search(dev, false);
1782 }
1783
1784 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1785 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1786                                        enum b43_nphy_rf_sequence seq)
1787 {
1788         static const u16 trigger[] = {
1789                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1790                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1791                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1792                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1793                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1794                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1795         };
1796         int i;
1797         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1798
1799         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1800
1801         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1802                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1803         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1804         for (i = 0; i < 200; i++) {
1805                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1806                         goto ok;
1807                 msleep(1);
1808         }
1809         b43err(dev->wl, "RF sequence status timeout\n");
1810 ok:
1811         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1812 }
1813
1814 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1815 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1816                                                 u16 value, u8 core, bool off)
1817 {
1818         int i;
1819         u8 index = fls(field);
1820         u8 addr, en_addr, val_addr;
1821         /* we expect only one bit set */
1822         B43_WARN_ON(field & (~(1 << (index - 1))));
1823
1824         if (dev->phy.rev >= 3) {
1825                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1826                 for (i = 0; i < 2; i++) {
1827                         if (index == 0 || index == 16) {
1828                                 b43err(dev->wl,
1829                                         "Unsupported RF Ctrl Override call\n");
1830                                 return;
1831                         }
1832
1833                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1834                         en_addr = B43_PHY_N((i == 0) ?
1835                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1836                         val_addr = B43_PHY_N((i == 0) ?
1837                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1838
1839                         if (off) {
1840                                 b43_phy_mask(dev, en_addr, ~(field));
1841                                 b43_phy_mask(dev, val_addr,
1842                                                 ~(rf_ctrl->val_mask));
1843                         } else {
1844                                 if (core == 0 || ((1 << core) & i) != 0) {
1845                                         b43_phy_set(dev, en_addr, field);
1846                                         b43_phy_maskset(dev, val_addr,
1847                                                 ~(rf_ctrl->val_mask),
1848                                                 (value << rf_ctrl->val_shift));
1849                                 }
1850                         }
1851                 }
1852         } else {
1853                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1854                 if (off) {
1855                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1856                         value = 0;
1857                 } else {
1858                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1859                 }
1860
1861                 for (i = 0; i < 2; i++) {
1862                         if (index <= 1 || index == 16) {
1863                                 b43err(dev->wl,
1864                                         "Unsupported RF Ctrl Override call\n");
1865                                 return;
1866                         }
1867
1868                         if (index == 2 || index == 10 ||
1869                             (index >= 13 && index <= 15)) {
1870                                 core = 1;
1871                         }
1872
1873                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1874                         addr = B43_PHY_N((i == 0) ?
1875                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1876
1877                         if ((core & (1 << i)) != 0)
1878                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1879                                                 (value << rf_ctrl->shift));
1880
1881                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1882                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1883                                         B43_NPHY_RFCTL_CMD_START);
1884                         udelay(1);
1885                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1886                 }
1887         }
1888 }
1889
1890 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1891 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1892                                                 u16 value, u8 core)
1893 {
1894         u8 i, j;
1895         u16 reg, tmp, val;
1896
1897         B43_WARN_ON(dev->phy.rev < 3);
1898         B43_WARN_ON(field > 4);
1899
1900         for (i = 0; i < 2; i++) {
1901                 if ((core == 1 && i == 1) || (core == 2 && !i))
1902                         continue;
1903
1904                 reg = (i == 0) ?
1905                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1906                 b43_phy_mask(dev, reg, 0xFBFF);
1907
1908                 switch (field) {
1909                 case 0:
1910                         b43_phy_write(dev, reg, 0);
1911                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1912                         break;
1913                 case 1:
1914                         if (!i) {
1915                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1916                                                 0xFC3F, (value << 6));
1917                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1918                                                 0xFFFE, 1);
1919                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1920                                                 B43_NPHY_RFCTL_CMD_START);
1921                                 for (j = 0; j < 100; j++) {
1922                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1923                                                 j = 0;
1924                                                 break;
1925                                         }
1926                                         udelay(10);
1927                                 }
1928                                 if (j)
1929                                         b43err(dev->wl,
1930                                                 "intc override timeout\n");
1931                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1932                                                 0xFFFE);
1933                         } else {
1934                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1935                                                 0xFC3F, (value << 6));
1936                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1937                                                 0xFFFE, 1);
1938                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1939                                                 B43_NPHY_RFCTL_CMD_RXTX);
1940                                 for (j = 0; j < 100; j++) {
1941                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1942                                                 j = 0;
1943                                                 break;
1944                                         }
1945                                         udelay(10);
1946                                 }
1947                                 if (j)
1948                                         b43err(dev->wl,
1949                                                 "intc override timeout\n");
1950                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1951                                                 0xFFFE);
1952                         }
1953                         break;
1954                 case 2:
1955                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1956                                 tmp = 0x0020;
1957                                 val = value << 5;
1958                         } else {
1959                                 tmp = 0x0010;
1960                                 val = value << 4;
1961                         }
1962                         b43_phy_maskset(dev, reg, ~tmp, val);
1963                         break;
1964                 case 3:
1965                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1966                                 tmp = 0x0001;
1967                                 val = value;
1968                         } else {
1969                                 tmp = 0x0004;
1970                                 val = value << 2;
1971                         }
1972                         b43_phy_maskset(dev, reg, ~tmp, val);
1973                         break;
1974                 case 4:
1975                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1976                                 tmp = 0x0002;
1977                                 val = value << 1;
1978                         } else {
1979                                 tmp = 0x0008;
1980                                 val = value << 3;
1981                         }
1982                         b43_phy_maskset(dev, reg, ~tmp, val);
1983                         break;
1984                 }
1985         }
1986 }
1987
1988 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
1989 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1990 {
1991         unsigned int i;
1992         u16 val;
1993
1994         val = 0x1E1F;
1995         for (i = 0; i < 16; i++) {
1996                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1997                 val -= 0x202;
1998         }
1999         val = 0x3E3F;
2000         for (i = 0; i < 16; i++) {
2001                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2002                 val -= 0x202;
2003         }
2004         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2005 }
2006
2007 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2008 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2009                                         s8 offset, u8 core, u8 rail,
2010                                         enum b43_nphy_rssi_type type)
2011 {
2012         u16 tmp;
2013         bool core1or5 = (core == 1) || (core == 5);
2014         bool core2or5 = (core == 2) || (core == 5);
2015
2016         offset = clamp_val(offset, -32, 31);
2017         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2018
2019         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2020                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2021         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2022                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2023         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2024                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2025         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2026                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2027
2028         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2029                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2030         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2031                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2032         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2033                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2034         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2035                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2036
2037         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2038                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2039         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2040                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2041         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2042                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2043         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2044                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2045
2046         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2047                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2048         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2049                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2050         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2051                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2052         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2053                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2054
2055         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2056                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2057         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2058                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2059         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2060                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2061         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2062                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2063
2064         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2065                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2066         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2067                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2068
2069         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2070                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2071         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2072                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2073 }
2074
2075 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2076 {
2077         u16 val;
2078
2079         if (type < 3)
2080                 val = 0;
2081         else if (type == 6)
2082                 val = 1;
2083         else if (type == 3)
2084                 val = 2;
2085         else
2086                 val = 3;
2087
2088         val = (val << 12) | (val << 14);
2089         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2090         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2091
2092         if (type < 3) {
2093                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2094                                 (type + 1) << 4);
2095                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2096                                 (type + 1) << 4);
2097         }
2098
2099         if (code == 0) {
2100                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2101                 if (type < 3) {
2102                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2103                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2104                                   B43_NPHY_RFCTL_CMD_CORESEL));
2105                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2106                                 ~(0x1 << 12 |
2107                                   0x1 << 5 |
2108                                   0x1 << 1 |
2109                                   0x1));
2110                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2111                                 ~B43_NPHY_RFCTL_CMD_START);
2112                         udelay(20);
2113                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2114                 }
2115         } else {
2116                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2117                 if (type < 3) {
2118                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2119                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2120                                   B43_NPHY_RFCTL_CMD_CORESEL),
2121                                 (B43_NPHY_RFCTL_CMD_RXEN |
2122                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2123                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2124                                 (0x1 << 12 |
2125                                   0x1 << 5 |
2126                                   0x1 << 1 |
2127                                   0x1));
2128                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2129                                 B43_NPHY_RFCTL_CMD_START);
2130                         udelay(20);
2131                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2132                 }
2133         }
2134 }
2135
2136 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2137 {
2138         struct b43_phy_n *nphy = dev->phy.n;
2139         u8 i;
2140         u16 reg, val;
2141
2142         if (code == 0) {
2143                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2144                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2145                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2146                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2147                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2148                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2149                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2150                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2151         } else {
2152                 for (i = 0; i < 2; i++) {
2153                         if ((code == 1 && i == 1) || (code == 2 && !i))
2154                                 continue;
2155
2156                         reg = (i == 0) ?
2157                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2158                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2159
2160                         if (type < 3) {
2161                                 reg = (i == 0) ?
2162                                         B43_NPHY_AFECTL_C1 :
2163                                         B43_NPHY_AFECTL_C2;
2164                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2165
2166                                 reg = (i == 0) ?
2167                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2168                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
2169                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2170
2171                                 if (type == 0)
2172                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2173                                 else if (type == 1)
2174                                         val = 16;
2175                                 else
2176                                         val = 32;
2177                                 b43_phy_set(dev, reg, val);
2178
2179                                 reg = (i == 0) ?
2180                                         B43_NPHY_TXF_40CO_B1S0 :
2181                                         B43_NPHY_TXF_40CO_B32S1;
2182                                 b43_phy_set(dev, reg, 0x0020);
2183                         } else {
2184                                 if (type == 6)
2185                                         val = 0x0100;
2186                                 else if (type == 3)
2187                                         val = 0x0200;
2188                                 else
2189                                         val = 0x0300;
2190
2191                                 reg = (i == 0) ?
2192                                         B43_NPHY_AFECTL_C1 :
2193                                         B43_NPHY_AFECTL_C2;
2194
2195                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
2196                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2197
2198                                 if (type != 3 && type != 6) {
2199                                         enum ieee80211_band band =
2200                                                 b43_current_band(dev->wl);
2201
2202                                         if ((nphy->ipa2g_on &&
2203                                                 band == IEEE80211_BAND_2GHZ) ||
2204                                                 (nphy->ipa5g_on &&
2205                                                 band == IEEE80211_BAND_5GHZ))
2206                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2207                                         else
2208                                                 val = 0x11;
2209                                         reg = (i == 0) ? 0x2000 : 0x3000;
2210                                         reg |= B2055_PADDRV;
2211                                         b43_radio_write16(dev, reg, val);
2212
2213                                         reg = (i == 0) ?
2214                                                 B43_NPHY_AFECTL_OVER1 :
2215                                                 B43_NPHY_AFECTL_OVER;
2216                                         b43_phy_set(dev, reg, 0x0200);
2217                                 }
2218                         }
2219                 }
2220         }
2221 }
2222
2223 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2224 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2225 {
2226         if (dev->phy.rev >= 3)
2227                 b43_nphy_rev3_rssi_select(dev, code, type);
2228         else
2229                 b43_nphy_rev2_rssi_select(dev, code, type);
2230 }
2231
2232 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2233 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2234 {
2235         int i;
2236         for (i = 0; i < 2; i++) {
2237                 if (type == 2) {
2238                         if (i == 0) {
2239                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2240                                                   0xFC, buf[0]);
2241                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2242                                                   0xFC, buf[1]);
2243                         } else {
2244                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2245                                                   0xFC, buf[2 * i]);
2246                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2247                                                   0xFC, buf[2 * i + 1]);
2248                         }
2249                 } else {
2250                         if (i == 0)
2251                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2252                                                   0xF3, buf[0] << 2);
2253                         else
2254                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2255                                                   0xF3, buf[2 * i + 1] << 2);
2256                 }
2257         }
2258 }
2259
2260 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2261 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2262                                 u8 nsamp)
2263 {
2264         int i;
2265         int out;
2266         u16 save_regs_phy[9];
2267         u16 s[2];
2268
2269         if (dev->phy.rev >= 3) {
2270                 save_regs_phy[0] = b43_phy_read(dev,
2271                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2272                 save_regs_phy[1] = b43_phy_read(dev,
2273                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2274                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2275                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2276                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2277                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2278                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2279                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2280                 save_regs_phy[8] = 0;
2281         } else {
2282                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2283                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2284                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2285                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2286                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2287                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2288                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2289                 save_regs_phy[7] = 0;
2290                 save_regs_phy[8] = 0;
2291         }
2292
2293         b43_nphy_rssi_select(dev, 5, type);
2294
2295         if (dev->phy.rev < 2) {
2296                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2297                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2298         }
2299
2300         for (i = 0; i < 4; i++)
2301                 buf[i] = 0;
2302
2303         for (i = 0; i < nsamp; i++) {
2304                 if (dev->phy.rev < 2) {
2305                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2306                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2307                 } else {
2308                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2309                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2310                 }
2311
2312                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2313                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2314                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2315                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2316         }
2317         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2318                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2319
2320         if (dev->phy.rev < 2)
2321                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2322
2323         if (dev->phy.rev >= 3) {
2324                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2325                                 save_regs_phy[0]);
2326                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2327                                 save_regs_phy[1]);
2328                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2329                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2330                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2331                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2332                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2333                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2334         } else {
2335                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2336                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2337                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2338                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2339                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2340                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2341                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2342         }
2343
2344         return out;
2345 }
2346
2347 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2348 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2349 {
2350         int i, j;
2351         u8 state[4];
2352         u8 code, val;
2353         u16 class, override;
2354         u8 regs_save_radio[2];
2355         u16 regs_save_phy[2];
2356
2357         s8 offset[4];
2358         u8 core;
2359         u8 rail;
2360
2361         u16 clip_state[2];
2362         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2363         s32 results_min[4] = { };
2364         u8 vcm_final[4] = { };
2365         s32 results[4][4] = { };
2366         s32 miniq[4][2] = { };
2367
2368         if (type == 2) {
2369                 code = 0;
2370                 val = 6;
2371         } else if (type < 2) {
2372                 code = 25;
2373                 val = 4;
2374         } else {
2375                 B43_WARN_ON(1);
2376                 return;
2377         }
2378
2379         class = b43_nphy_classifier(dev, 0, 0);
2380         b43_nphy_classifier(dev, 7, 4);
2381         b43_nphy_read_clip_detection(dev, clip_state);
2382         b43_nphy_write_clip_detection(dev, clip_off);
2383
2384         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2385                 override = 0x140;
2386         else
2387                 override = 0x110;
2388
2389         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2390         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2391         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2392         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2393
2394         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2395         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2396         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2397         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2398
2399         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2400         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2401         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2402         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2403         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2404         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2405
2406         b43_nphy_rssi_select(dev, 5, type);
2407         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2408         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2409
2410         for (i = 0; i < 4; i++) {
2411                 u8 tmp[4];
2412                 for (j = 0; j < 4; j++)
2413                         tmp[j] = i;
2414                 if (type != 1)
2415                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2416                 b43_nphy_poll_rssi(dev, type, results[i], 8);
2417                 if (type < 2)
2418                         for (j = 0; j < 2; j++)
2419                                 miniq[i][j] = min(results[i][2 * j],
2420                                                 results[i][2 * j + 1]);
2421         }
2422
2423         for (i = 0; i < 4; i++) {
2424                 s32 mind = 40;
2425                 u8 minvcm = 0;
2426                 s32 minpoll = 249;
2427                 s32 curr;
2428                 for (j = 0; j < 4; j++) {
2429                         if (type == 2)
2430                                 curr = abs(results[j][i]);
2431                         else
2432                                 curr = abs(miniq[j][i / 2] - code * 8);
2433
2434                         if (curr < mind) {
2435                                 mind = curr;
2436                                 minvcm = j;
2437                         }
2438
2439                         if (results[j][i] < minpoll)
2440                                 minpoll = results[j][i];
2441                 }
2442                 results_min[i] = minpoll;
2443                 vcm_final[i] = minvcm;
2444         }
2445
2446         if (type != 1)
2447                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2448
2449         for (i = 0; i < 4; i++) {
2450                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2451
2452                 if (offset[i] < 0)
2453                         offset[i] = -((abs(offset[i]) + 4) / 8);
2454                 else
2455                         offset[i] = (offset[i] + 4) / 8;
2456
2457                 if (results_min[i] == 248)
2458                         offset[i] = code - 32;
2459
2460                 core = (i / 2) ? 2 : 1;
2461                 rail = (i % 2) ? 1 : 0;
2462
2463                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2464                                                 type);
2465         }
2466
2467         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2468         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2469
2470         switch (state[2]) {
2471         case 1:
2472                 b43_nphy_rssi_select(dev, 1, 2);
2473                 break;
2474         case 4:
2475                 b43_nphy_rssi_select(dev, 1, 0);
2476                 break;
2477         case 2:
2478                 b43_nphy_rssi_select(dev, 1, 1);
2479                 break;
2480         default:
2481                 b43_nphy_rssi_select(dev, 1, 1);
2482                 break;
2483         }
2484
2485         switch (state[3]) {
2486         case 1:
2487                 b43_nphy_rssi_select(dev, 2, 2);
2488                 break;
2489         case 4:
2490                 b43_nphy_rssi_select(dev, 2, 0);
2491                 break;
2492         default:
2493                 b43_nphy_rssi_select(dev, 2, 1);
2494                 break;
2495         }
2496
2497         b43_nphy_rssi_select(dev, 0, type);
2498
2499         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2500         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2501         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2502         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2503
2504         b43_nphy_classifier(dev, 7, class);
2505         b43_nphy_write_clip_detection(dev, clip_state);
2506         /* Specs don't say about reset here, but it makes wl and b43 dumps
2507            identical, it really seems wl performs this */
2508         b43_nphy_reset_cca(dev);
2509 }
2510
2511 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2512 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2513 {
2514         /* TODO */
2515 }
2516
2517 /*
2518  * RSSI Calibration
2519  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2520  */
2521 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2522 {
2523         if (dev->phy.rev >= 3) {
2524                 b43_nphy_rev3_rssi_cal(dev);
2525         } else {
2526                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2527                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2528                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2529         }
2530 }
2531
2532 /*
2533  * Restore RSSI Calibration
2534  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2535  */
2536 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2537 {
2538         struct b43_phy_n *nphy = dev->phy.n;
2539
2540         u16 *rssical_radio_regs = NULL;
2541         u16 *rssical_phy_regs = NULL;
2542
2543         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2544                 if (!nphy->rssical_chanspec_2G.center_freq)
2545                         return;
2546                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2547                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2548         } else {
2549                 if (!nphy->rssical_chanspec_5G.center_freq)
2550                         return;
2551                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2552                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2553         }
2554
2555         /* TODO use some definitions */
2556         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2557         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2558
2559         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2560         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2561         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2562         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2563
2564         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2565         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2566         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2567         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2568
2569         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2570         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2571         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2572         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2573 }
2574
2575 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2576 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2577 {
2578         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2579                 if (dev->phy.rev >= 6) {
2580                         /* TODO If the chip is 47162
2581                                 return txpwrctrl_tx_gain_ipa_rev5 */
2582                         return txpwrctrl_tx_gain_ipa_rev6;
2583                 } else if (dev->phy.rev >= 5) {
2584                         return txpwrctrl_tx_gain_ipa_rev5;
2585                 } else {
2586                         return txpwrctrl_tx_gain_ipa;
2587                 }
2588         } else {
2589                 return txpwrctrl_tx_gain_ipa_5g;
2590         }
2591 }
2592
2593 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2594 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2595 {
2596         struct b43_phy_n *nphy = dev->phy.n;
2597         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2598         u16 tmp;
2599         u8 offset, i;
2600
2601         if (dev->phy.rev >= 3) {
2602             for (i = 0; i < 2; i++) {
2603                 tmp = (i == 0) ? 0x2000 : 0x3000;
2604                 offset = i * 11;
2605
2606                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2607                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2608                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2609                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2610                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2611                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2612                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2613                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2614                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2615                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2616                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2617
2618                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2619                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2620                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2621                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2622                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2623                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2624                         if (nphy->ipa5g_on) {
2625                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2626                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2627                         } else {
2628                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2629                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2630                         }
2631                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2632                 } else {
2633                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2634                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2635                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2636                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2637                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2638                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2639                         if (nphy->ipa2g_on) {
2640                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2641                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2642                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2643                         } else {
2644                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2645                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2646                         }
2647                 }
2648                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2649                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2650                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2651             }
2652         } else {
2653                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2654                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2655
2656                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2657                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2658
2659                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2660                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2661
2662                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2663                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2664
2665                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2666                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2667
2668                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2669                     B43_NPHY_BANDCTL_5GHZ)) {
2670                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2671                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2672                 } else {
2673                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2674                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2675                 }
2676
2677                 if (dev->phy.rev < 2) {
2678                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2679                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2680                 } else {
2681                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2682                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2683                 }
2684         }
2685 }
2686
2687 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2688 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2689                                         struct nphy_txgains target,
2690                                         struct nphy_iqcal_params *params)
2691 {
2692         int i, j, indx;
2693         u16 gain;
2694
2695         if (dev->phy.rev >= 3) {
2696                 params->txgm = target.txgm[core];
2697                 params->pga = target.pga[core];
2698                 params->pad = target.pad[core];
2699                 params->ipa = target.ipa[core];
2700                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2701                                         (params->pad << 4) | (params->ipa);
2702                 for (j = 0; j < 5; j++)
2703                         params->ncorr[j] = 0x79;
2704         } else {
2705                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2706                         (target.txgm[core] << 8);
2707
2708                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2709                         1 : 0;
2710                 for (i = 0; i < 9; i++)
2711                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2712                                 break;
2713                 i = min(i, 8);
2714
2715                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2716                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2717                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2718                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2719                                         (params->pad << 2);
2720                 for (j = 0; j < 4; j++)
2721                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2722         }
2723 }
2724
2725 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2726 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2727 {
2728         struct b43_phy_n *nphy = dev->phy.n;
2729         int i;
2730         u16 scale, entry;
2731
2732         u16 tmp = nphy->txcal_bbmult;
2733         if (core == 0)
2734                 tmp >>= 8;
2735         tmp &= 0xff;
2736
2737         for (i = 0; i < 18; i++) {
2738                 scale = (ladder_lo[i].percent * tmp) / 100;
2739                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2740                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2741
2742                 scale = (ladder_iq[i].percent * tmp) / 100;
2743                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2744                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2745         }
2746 }
2747
2748 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2749 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2750 {
2751         int i;
2752         for (i = 0; i < 15; i++)
2753                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2754                                 tbl_tx_filter_coef_rev4[2][i]);
2755 }
2756
2757 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2758 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2759 {
2760         int i, j;
2761         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2762         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2763
2764         for (i = 0; i < 3; i++)
2765                 for (j = 0; j < 15; j++)
2766                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2767                                         tbl_tx_filter_coef_rev4[i][j]);
2768
2769         if (dev->phy.is_40mhz) {
2770                 for (j = 0; j < 15; j++)
2771                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2772                                         tbl_tx_filter_coef_rev4[3][j]);
2773         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2774                 for (j = 0; j < 15; j++)
2775                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2776                                         tbl_tx_filter_coef_rev4[5][j]);
2777         }
2778
2779         if (dev->phy.channel == 14)
2780                 for (j = 0; j < 15; j++)
2781                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2782                                         tbl_tx_filter_coef_rev4[6][j]);
2783 }
2784
2785 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2786 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2787 {
2788         struct b43_phy_n *nphy = dev->phy.n;
2789
2790         u16 curr_gain[2];
2791         struct nphy_txgains target;
2792         const u32 *table = NULL;
2793
2794         if (!nphy->txpwrctrl) {
2795                 int i;
2796
2797                 if (nphy->hang_avoid)
2798                         b43_nphy_stay_in_carrier_search(dev, true);
2799                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2800                 if (nphy->hang_avoid)
2801                         b43_nphy_stay_in_carrier_search(dev, false);
2802
2803                 for (i = 0; i < 2; ++i) {
2804                         if (dev->phy.rev >= 3) {
2805                                 target.ipa[i] = curr_gain[i] & 0x000F;
2806                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2807                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2808                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2809                         } else {
2810                                 target.ipa[i] = curr_gain[i] & 0x0003;
2811                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2812                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2813                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2814                         }
2815                 }
2816         } else {
2817                 int i;
2818                 u16 index[2];
2819                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2820                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2821                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2822                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2823                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2824                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2825
2826                 for (i = 0; i < 2; ++i) {
2827                         if (dev->phy.rev >= 3) {
2828                                 enum ieee80211_band band =
2829                                         b43_current_band(dev->wl);
2830
2831                                 if ((nphy->ipa2g_on &&
2832                                      band == IEEE80211_BAND_2GHZ) ||
2833                                     (nphy->ipa5g_on &&
2834                                      band == IEEE80211_BAND_5GHZ)) {
2835                                         table = b43_nphy_get_ipa_gain_table(dev);
2836                                 } else {
2837                                         if (band == IEEE80211_BAND_5GHZ) {
2838                                                 if (dev->phy.rev == 3)
2839                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2840                                                 else if (dev->phy.rev == 4)
2841                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2842                                                 else
2843                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2844                                         } else {
2845                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2846                                         }
2847                                 }
2848
2849                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2850                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2851                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2852                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2853                         } else {
2854                                 table = b43_ntab_tx_gain_rev0_1_2;
2855
2856                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2857                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2858                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2859                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2860                         }
2861                 }
2862         }
2863
2864         return target;
2865 }
2866
2867 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2868 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2869 {
2870         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2871
2872         if (dev->phy.rev >= 3) {
2873                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2874                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2875                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2876                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2877                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2878                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2879                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2880                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2881                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2882                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2883                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2884                 b43_nphy_reset_cca(dev);
2885         } else {
2886                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2887                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2888                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2889                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2890                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2891                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2892                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2893         }
2894 }
2895
2896 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2897 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2898 {
2899         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2900         u16 tmp;
2901
2902         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2903         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2904         if (dev->phy.rev >= 3) {
2905                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2906                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2907
2908                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2909                 regs[2] = tmp;
2910                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2911
2912                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2913                 regs[3] = tmp;
2914                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2915
2916                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2917                 b43_phy_mask(dev, B43_NPHY_BBCFG,
2918                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2919
2920                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2921                 regs[5] = tmp;
2922                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2923
2924                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2925                 regs[6] = tmp;
2926                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2927                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2928                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2929
2930                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2931                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2932                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2933
2934                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2935                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2936                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2937                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2938         } else {
2939                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2940                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2941                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2942                 regs[2] = tmp;
2943                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2944                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2945                 regs[3] = tmp;
2946                 tmp |= 0x2000;
2947                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2948                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2949                 regs[4] = tmp;
2950                 tmp |= 0x2000;
2951                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2952                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2953                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2954                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2955                         tmp = 0x0180;
2956                 else
2957                         tmp = 0x0120;
2958                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2959                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2960         }
2961 }
2962
2963 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2964 static void b43_nphy_save_cal(struct b43_wldev *dev)
2965 {
2966         struct b43_phy_n *nphy = dev->phy.n;
2967
2968         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2969         u16 *txcal_radio_regs = NULL;
2970         struct b43_chanspec *iqcal_chanspec;
2971         u16 *table = NULL;
2972
2973         if (nphy->hang_avoid)
2974                 b43_nphy_stay_in_carrier_search(dev, 1);
2975
2976         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2977                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2978                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2979                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2980                 table = nphy->cal_cache.txcal_coeffs_2G;
2981         } else {
2982                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2983                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2984                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2985                 table = nphy->cal_cache.txcal_coeffs_5G;
2986         }
2987
2988         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2989         /* TODO use some definitions */
2990         if (dev->phy.rev >= 3) {
2991                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2992                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2993                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2994                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2995                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2996                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2997                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2998                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2999         } else {
3000                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3001                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3002                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3003                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3004         }
3005         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3006         iqcal_chanspec->channel_type = dev->phy.channel_type;
3007         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3008
3009         if (nphy->hang_avoid)
3010                 b43_nphy_stay_in_carrier_search(dev, 0);
3011 }
3012
3013 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3014 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3015 {
3016         struct b43_phy_n *nphy = dev->phy.n;
3017
3018         u16 coef[4];
3019         u16 *loft = NULL;
3020         u16 *table = NULL;
3021
3022         int i;
3023         u16 *txcal_radio_regs = NULL;
3024         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3025
3026         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3027                 if (!nphy->iqcal_chanspec_2G.center_freq)
3028                         return;
3029                 table = nphy->cal_cache.txcal_coeffs_2G;
3030                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3031         } else {
3032                 if (!nphy->iqcal_chanspec_5G.center_freq)
3033                         return;
3034                 table = nphy->cal_cache.txcal_coeffs_5G;
3035                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3036         }
3037
3038         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3039
3040         for (i = 0; i < 4; i++) {
3041                 if (dev->phy.rev >= 3)
3042                         table[i] = coef[i];
3043                 else
3044                         coef[i] = 0;
3045         }
3046
3047         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3048         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3049         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3050
3051         if (dev->phy.rev < 2)
3052                 b43_nphy_tx_iq_workaround(dev);
3053
3054         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3055                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3056                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3057         } else {
3058                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3059                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3060         }
3061
3062         /* TODO use some definitions */
3063         if (dev->phy.rev >= 3) {
3064                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3065                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3066                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3067                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3068                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3069                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3070                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3071                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3072         } else {
3073                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3074                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3075                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3076                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3077         }
3078         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3079 }
3080
3081 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3082 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3083                                 struct nphy_txgains target,
3084                                 bool full, bool mphase)
3085 {
3086         struct b43_phy_n *nphy = dev->phy.n;
3087         int i;
3088         int error = 0;
3089         int freq;
3090         bool avoid = false;
3091         u8 length;
3092         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3093         const u16 *table;
3094         bool phy6or5x;
3095
3096         u16 buffer[11];
3097         u16 diq_start = 0;
3098         u16 save[2];
3099         u16 gain[2];
3100         struct nphy_iqcal_params params[2];
3101         bool updated[2] = { };
3102
3103         b43_nphy_stay_in_carrier_search(dev, true);
3104
3105         if (dev->phy.rev >= 4) {
3106                 avoid = nphy->hang_avoid;
3107                 nphy->hang_avoid = 0;
3108         }
3109
3110         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3111
3112         for (i = 0; i < 2; i++) {
3113                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3114                 gain[i] = params[i].cal_gain;
3115         }
3116
3117         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3118
3119         b43_nphy_tx_cal_radio_setup(dev);
3120         b43_nphy_tx_cal_phy_setup(dev);
3121
3122         phy6or5x = dev->phy.rev >= 6 ||
3123                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3124                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3125         if (phy6or5x) {
3126                 if (dev->phy.is_40mhz) {
3127                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3128                                         tbl_tx_iqlo_cal_loft_ladder_40);
3129                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3130                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3131                 } else {
3132                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3133                                         tbl_tx_iqlo_cal_loft_ladder_20);
3134                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3135                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3136                 }
3137         }
3138
3139         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3140
3141         if (!dev->phy.is_40mhz)
3142                 freq = 2500;
3143         else
3144                 freq = 5000;
3145
3146         if (nphy->mphase_cal_phase_id > 2)
3147                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3148                                         0xFFFF, 0, true, false);
3149         else
3150                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3151
3152         if (error == 0) {
3153                 if (nphy->mphase_cal_phase_id > 2) {
3154                         table = nphy->mphase_txcal_bestcoeffs;
3155                         length = 11;
3156                         if (dev->phy.rev < 3)
3157                                 length -= 2;
3158                 } else {
3159                         if (!full && nphy->txiqlocal_coeffsvalid) {
3160                                 table = nphy->txiqlocal_bestc;
3161                                 length = 11;
3162                                 if (dev->phy.rev < 3)
3163                                         length -= 2;
3164                         } else {
3165                                 full = true;
3166                                 if (dev->phy.rev >= 3) {
3167                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3168                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3169                                 } else {
3170                                         table = tbl_tx_iqlo_cal_startcoefs;
3171                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3172                                 }
3173                         }
3174                 }
3175
3176                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3177
3178                 if (full) {
3179                         if (dev->phy.rev >= 3)
3180                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3181                         else
3182                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3183                 } else {
3184                         if (dev->phy.rev >= 3)
3185                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3186                         else
3187                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3188                 }
3189
3190                 if (mphase) {
3191                         count = nphy->mphase_txcal_cmdidx;
3192                         numb = min(max,
3193                                 (u16)(count + nphy->mphase_txcal_numcmds));
3194                 } else {
3195                         count = 0;
3196                         numb = max;
3197                 }
3198
3199                 for (; count < numb; count++) {
3200                         if (full) {
3201                                 if (dev->phy.rev >= 3)
3202                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3203                                 else
3204                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3205                         } else {
3206                                 if (dev->phy.rev >= 3)
3207                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3208                                 else
3209                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3210                         }
3211
3212                         core = (cmd & 0x3000) >> 12;
3213                         type = (cmd & 0x0F00) >> 8;
3214
3215                         if (phy6or5x && updated[core] == 0) {
3216                                 b43_nphy_update_tx_cal_ladder(dev, core);
3217                                 updated[core] = 1;
3218                         }
3219
3220                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3221                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3222
3223                         if (type == 1 || type == 3 || type == 4) {
3224                                 buffer[0] = b43_ntab_read(dev,
3225                                                 B43_NTAB16(15, 69 + core));
3226                                 diq_start = buffer[0];
3227                                 buffer[0] = 0;
3228                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3229                                                 0);
3230                         }
3231
3232                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3233                         for (i = 0; i < 2000; i++) {
3234                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3235                                 if (tmp & 0xC000)
3236                                         break;
3237                                 udelay(10);
3238                         }
3239
3240                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3241                                                 buffer);
3242                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3243                                                 buffer);
3244
3245                         if (type == 1 || type == 3 || type == 4)
3246                                 buffer[0] = diq_start;
3247                 }
3248
3249                 if (mphase)
3250                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3251
3252                 last = (dev->phy.rev < 3) ? 6 : 7;
3253
3254                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3255                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3256                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3257                         if (dev->phy.rev < 3) {
3258                                 buffer[0] = 0;
3259                                 buffer[1] = 0;
3260                                 buffer[2] = 0;
3261                                 buffer[3] = 0;
3262                         }
3263                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3264                                                 buffer);
3265                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3266                                                 buffer);
3267                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3268                                                 buffer);
3269                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3270                                                 buffer);
3271                         length = 11;
3272                         if (dev->phy.rev < 3)
3273                                 length -= 2;
3274                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3275                                                 nphy->txiqlocal_bestc);
3276                         nphy->txiqlocal_coeffsvalid = true;
3277                         nphy->txiqlocal_chanspec.center_freq =
3278                                                         dev->phy.channel_freq;
3279                         nphy->txiqlocal_chanspec.channel_type =
3280                                                         dev->phy.channel_type;
3281                 } else {
3282                         length = 11;
3283                         if (dev->phy.rev < 3)
3284                                 length -= 2;
3285                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3286                                                 nphy->mphase_txcal_bestcoeffs);
3287                 }
3288
3289                 b43_nphy_stop_playback(dev);
3290                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3291         }
3292
3293         b43_nphy_tx_cal_phy_cleanup(dev);
3294         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3295
3296         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3297                 b43_nphy_tx_iq_workaround(dev);
3298
3299         if (dev->phy.rev >= 4)
3300                 nphy->hang_avoid = avoid;
3301
3302         b43_nphy_stay_in_carrier_search(dev, false);
3303
3304         return error;
3305 }
3306
3307 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3308 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3309 {
3310         struct b43_phy_n *nphy = dev->phy.n;
3311         u8 i;
3312         u16 buffer[7];
3313         bool equal = true;
3314
3315         if (!nphy->txiqlocal_coeffsvalid ||
3316             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3317             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3318                 return;
3319
3320         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3321         for (i = 0; i < 4; i++) {
3322                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3323                         equal = false;
3324                         break;
3325                 }
3326         }
3327
3328         if (!equal) {
3329                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3330                                         nphy->txiqlocal_bestc);
3331                 for (i = 0; i < 4; i++)
3332                         buffer[i] = 0;
3333                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3334                                         buffer);
3335                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3336                                         &nphy->txiqlocal_bestc[5]);
3337                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3338                                         &nphy->txiqlocal_bestc[5]);
3339         }
3340 }
3341
3342 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3343 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3344                         struct nphy_txgains target, u8 type, bool debug)
3345 {
3346         struct b43_phy_n *nphy = dev->phy.n;
3347         int i, j, index;
3348         u8 rfctl[2];
3349         u8 afectl_core;
3350         u16 tmp[6];
3351         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3352         u32 real, imag;
3353         enum ieee80211_band band;
3354
3355         u8 use;
3356         u16 cur_hpf;
3357         u16 lna[3] = { 3, 3, 1 };
3358         u16 hpf1[3] = { 7, 2, 0 };
3359         u16 hpf2[3] = { 2, 0, 0 };
3360         u32 power[3] = { };
3361         u16 gain_save[2];
3362         u16 cal_gain[2];
3363         struct nphy_iqcal_params cal_params[2];
3364         struct nphy_iq_est est;
3365         int ret = 0;
3366         bool playtone = true;
3367         int desired = 13;
3368
3369         b43_nphy_stay_in_carrier_search(dev, 1);
3370
3371         if (dev->phy.rev < 2)
3372                 b43_nphy_reapply_tx_cal_coeffs(dev);
3373         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3374         for (i = 0; i < 2; i++) {
3375                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3376                 cal_gain[i] = cal_params[i].cal_gain;
3377         }
3378         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3379
3380         for (i = 0; i < 2; i++) {
3381                 if (i == 0) {
3382                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3383                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3384                         afectl_core = B43_NPHY_AFECTL_C1;
3385                 } else {
3386                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3387                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3388                         afectl_core = B43_NPHY_AFECTL_C2;
3389                 }
3390
3391                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3392                 tmp[2] = b43_phy_read(dev, afectl_core);
3393                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3394                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3395                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3396
3397                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3398                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3399                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3400                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3401                                 (1 - i));
3402                 b43_phy_set(dev, afectl_core, 0x0006);
3403                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3404
3405                 band = b43_current_band(dev->wl);
3406
3407                 if (nphy->rxcalparams & 0xFF000000) {
3408                         if (band == IEEE80211_BAND_5GHZ)
3409                                 b43_phy_write(dev, rfctl[0], 0x140);
3410                         else
3411                                 b43_phy_write(dev, rfctl[0], 0x110);
3412                 } else {
3413                         if (band == IEEE80211_BAND_5GHZ)
3414                                 b43_phy_write(dev, rfctl[0], 0x180);
3415                         else
3416                                 b43_phy_write(dev, rfctl[0], 0x120);
3417                 }
3418
3419                 if (band == IEEE80211_BAND_5GHZ)
3420                         b43_phy_write(dev, rfctl[1], 0x148);
3421                 else
3422                         b43_phy_write(dev, rfctl[1], 0x114);
3423
3424                 if (nphy->rxcalparams & 0x10000) {
3425                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3426                                         (i + 1));
3427                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3428                                         (2 - i));
3429                 }
3430
3431                 for (j = 0; j < 4; j++) {
3432                         if (j < 3) {
3433                                 cur_lna = lna[j];
3434                                 cur_hpf1 = hpf1[j];
3435                                 cur_hpf2 = hpf2[j];
3436                         } else {
3437                                 if (power[1] > 10000) {
3438                                         use = 1;
3439                                         cur_hpf = cur_hpf1;
3440                                         index = 2;
3441                                 } else {
3442                                         if (power[0] > 10000) {
3443                                                 use = 1;
3444                                                 cur_hpf = cur_hpf1;
3445                                                 index = 1;
3446                                         } else {
3447                                                 index = 0;
3448                                                 use = 2;
3449                                                 cur_hpf = cur_hpf2;
3450                                         }
3451                                 }
3452                                 cur_lna = lna[index];
3453                                 cur_hpf1 = hpf1[index];
3454                                 cur_hpf2 = hpf2[index];
3455                                 cur_hpf += desired - hweight32(power[index]);
3456                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3457                                 if (use == 1)
3458                                         cur_hpf1 = cur_hpf;
3459                                 else
3460                                         cur_hpf2 = cur_hpf;
3461                         }
3462
3463                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3464                                         (cur_lna << 2));
3465                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3466                                                                         false);
3467                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3468                         b43_nphy_stop_playback(dev);
3469
3470                         if (playtone) {
3471                                 ret = b43_nphy_tx_tone(dev, 4000,
3472                                                 (nphy->rxcalparams & 0xFFFF),
3473                                                 false, false);
3474                                 playtone = false;
3475                         } else {
3476                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3477                                                         false, false);
3478                         }
3479
3480                         if (ret == 0) {
3481                                 if (j < 3) {
3482                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3483                                                                         false);
3484                                         if (i == 0) {
3485                                                 real = est.i0_pwr;
3486                                                 imag = est.q0_pwr;
3487                                         } else {
3488                                                 real = est.i1_pwr;
3489                                                 imag = est.q1_pwr;
3490                                         }
3491                                         power[i] = ((real + imag) / 1024) + 1;
3492                                 } else {
3493                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3494                                 }
3495                                 b43_nphy_stop_playback(dev);
3496                         }
3497
3498                         if (ret != 0)
3499                                 break;
3500                 }
3501
3502                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3503                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3504                 b43_phy_write(dev, rfctl[1], tmp[5]);
3505                 b43_phy_write(dev, rfctl[0], tmp[4]);
3506                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3507                 b43_phy_write(dev, afectl_core, tmp[2]);
3508                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3509
3510                 if (ret != 0)
3511                         break;
3512         }
3513
3514         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3515         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3516         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3517
3518         b43_nphy_stay_in_carrier_search(dev, 0);
3519
3520         return ret;
3521 }
3522
3523 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3524                         struct nphy_txgains target, u8 type, bool debug)
3525 {
3526         return -1;
3527 }
3528
3529 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3530 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3531                         struct nphy_txgains target, u8 type, bool debug)
3532 {
3533         if (dev->phy.rev >= 3)
3534                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3535         else
3536                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3537 }
3538
3539 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3540 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3541 {
3542         struct b43_phy *phy = &dev->phy;
3543         struct b43_phy_n *nphy = phy->n;
3544         /* u16 buf[16]; it's rev3+ */
3545
3546         nphy->phyrxchain = mask;
3547
3548         if (0 /* FIXME clk */)
3549                 return;
3550
3551         b43_mac_suspend(dev);
3552
3553         if (nphy->hang_avoid)
3554                 b43_nphy_stay_in_carrier_search(dev, true);
3555
3556         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3557                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3558
3559         if ((mask & 0x3) != 0x3) {
3560                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3561                 if (dev->phy.rev >= 3) {
3562                         /* TODO */
3563                 }
3564         } else {
3565                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3566                 if (dev->phy.rev >= 3) {
3567                         /* TODO */
3568                 }
3569         }
3570
3571         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3572
3573         if (nphy->hang_avoid)
3574                 b43_nphy_stay_in_carrier_search(dev, false);
3575
3576         b43_mac_enable(dev);
3577 }
3578
3579 /*
3580  * Init N-PHY
3581  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3582  */
3583 int b43_phy_initn(struct b43_wldev *dev)
3584 {
3585         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3586         struct b43_phy *phy = &dev->phy;
3587         struct b43_phy_n *nphy = phy->n;
3588         u8 tx_pwr_state;
3589         struct nphy_txgains target;
3590         u16 tmp;
3591         enum ieee80211_band tmp2;
3592         bool do_rssi_cal;
3593
3594         u16 clip[2];
3595         bool do_cal = false;
3596
3597         if ((dev->phy.rev >= 3) &&
3598            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3599            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3600                 switch (dev->dev->bus_type) {
3601 #ifdef CONFIG_B43_BCMA
3602                 case B43_BUS_BCMA:
3603                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3604                                       BCMA_CC_CHIPCTL, 0x40);
3605                         break;
3606 #endif
3607 #ifdef CONFIG_B43_SSB
3608                 case B43_BUS_SSB:
3609                         chipco_set32(&dev->dev->sdev->bus->chipco,
3610                                      SSB_CHIPCO_CHIPCTL, 0x40);
3611                         break;
3612 #endif
3613                 }
3614         }
3615         nphy->deaf_count = 0;
3616         b43_nphy_tables_init(dev);
3617         nphy->crsminpwr_adjusted = false;
3618         nphy->noisevars_adjusted = false;
3619
3620         /* Clear all overrides */
3621         if (dev->phy.rev >= 3) {
3622                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3623                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3624                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3625                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3626         } else {
3627                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3628         }
3629         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3630         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3631         if (dev->phy.rev < 6) {
3632                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3633                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3634         }
3635         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3636                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3637                        B43_NPHY_RFSEQMODE_TROVER));
3638         if (dev->phy.rev >= 3)
3639                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3640         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3641
3642         if (dev->phy.rev <= 2) {
3643                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3644                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3645                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3646                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3647         }
3648         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3649         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3650
3651         if (sprom->boardflags2_lo & 0x100 ||
3652             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3653              dev->dev->board_type == 0x8B))
3654                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3655         else
3656                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3657         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3658         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3659         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3660
3661         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3662         b43_nphy_update_txrx_chain(dev);
3663
3664         if (phy->rev < 2) {
3665                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3666                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3667         }
3668
3669         tmp2 = b43_current_band(dev->wl);
3670         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3671             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3672                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3673                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3674                                 nphy->papd_epsilon_offset[0] << 7);
3675                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3676                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3677                                 nphy->papd_epsilon_offset[1] << 7);
3678                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3679         } else if (phy->rev >= 5) {
3680                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3681         }
3682
3683         b43_nphy_workarounds(dev);
3684
3685         /* Reset CCA, in init code it differs a little from standard way */
3686         b43_phy_force_clock(dev, 1);
3687         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3688         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3689         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3690         b43_phy_force_clock(dev, 0);
3691
3692         b43_mac_phy_clock_set(dev, true);
3693
3694         b43_nphy_pa_override(dev, false);
3695         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3696         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3697         b43_nphy_pa_override(dev, true);
3698
3699         b43_nphy_classifier(dev, 0, 0);
3700         b43_nphy_read_clip_detection(dev, clip);
3701         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3702                 b43_nphy_bphy_init(dev);
3703
3704         tx_pwr_state = nphy->txpwrctrl;
3705         b43_nphy_tx_power_ctrl(dev, false);
3706         b43_nphy_tx_power_fix(dev);
3707         /* TODO N PHY TX Power Control Idle TSSI */
3708         /* TODO N PHY TX Power Control Setup */
3709
3710         if (phy->rev >= 3) {
3711                 /* TODO */
3712         } else {
3713                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3714                                         b43_ntab_tx_gain_rev0_1_2);
3715                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3716                                         b43_ntab_tx_gain_rev0_1_2);
3717         }
3718
3719         if (nphy->phyrxchain != 3)
3720                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3721         if (nphy->mphase_cal_phase_id > 0)
3722                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3723
3724         do_rssi_cal = false;
3725         if (phy->rev >= 3) {
3726                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3727                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3728                 else
3729                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3730
3731                 if (do_rssi_cal)
3732                         b43_nphy_rssi_cal(dev);
3733                 else
3734                         b43_nphy_restore_rssi_cal(dev);
3735         } else {
3736                 b43_nphy_rssi_cal(dev);
3737         }
3738
3739         if (!((nphy->measure_hold & 0x6) != 0)) {
3740                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3741                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3742                 else
3743                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3744
3745                 if (nphy->mute)
3746                         do_cal = false;
3747
3748                 if (do_cal) {
3749                         target = b43_nphy_get_tx_gains(dev);
3750
3751                         if (nphy->antsel_type == 2)
3752                                 b43_nphy_superswitch_init(dev, true);
3753                         if (nphy->perical != 2) {
3754                                 b43_nphy_rssi_cal(dev);
3755                                 if (phy->rev >= 3) {
3756                                         nphy->cal_orig_pwr_idx[0] =
3757                                             nphy->txpwrindex[0].index_internal;
3758                                         nphy->cal_orig_pwr_idx[1] =
3759                                             nphy->txpwrindex[1].index_internal;
3760                                         /* TODO N PHY Pre Calibrate TX Gain */
3761                                         target = b43_nphy_get_tx_gains(dev);
3762                                 }
3763                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3764                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3765                                                 b43_nphy_save_cal(dev);
3766                         } else if (nphy->mphase_cal_phase_id == 0)
3767                                 ;/* N PHY Periodic Calibration with arg 3 */
3768                 } else {
3769                         b43_nphy_restore_cal(dev);
3770                 }
3771         }
3772
3773         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3774         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3775         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3776         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3777         if (phy->rev >= 3 && phy->rev <= 6)
3778                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3779         b43_nphy_tx_lp_fbw(dev);
3780         if (phy->rev >= 3)
3781                 b43_nphy_spur_workaround(dev);
3782
3783         return 0;
3784 }
3785
3786 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3787 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3788                                 const struct b43_phy_n_sfo_cfg *e,
3789                                 struct ieee80211_channel *new_channel)
3790 {
3791         struct b43_phy *phy = &dev->phy;
3792         struct b43_phy_n *nphy = dev->phy.n;
3793
3794         u16 old_band_5ghz;
3795         u32 tmp32;
3796
3797         old_band_5ghz =
3798                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3799         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3800                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3801                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3802                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3803                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3804                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3805         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3806                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3807                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3808                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3809                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3810                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3811         }
3812
3813         b43_chantab_phy_upload(dev, e);
3814
3815         if (new_channel->hw_value == 14) {
3816                 b43_nphy_classifier(dev, 2, 0);
3817                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3818         } else {
3819                 b43_nphy_classifier(dev, 2, 2);
3820                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3821                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3822         }
3823
3824         if (!nphy->txpwrctrl)
3825                 b43_nphy_tx_power_fix(dev);
3826
3827         if (dev->phy.rev < 3)
3828                 b43_nphy_adjust_lna_gain_table(dev);
3829
3830         b43_nphy_tx_lp_fbw(dev);
3831
3832         if (dev->phy.rev >= 3 && 0) {
3833                 /* TODO */
3834         }
3835
3836         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3837
3838         if (phy->rev >= 3)
3839                 b43_nphy_spur_workaround(dev);
3840 }
3841
3842 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3843 static int b43_nphy_set_channel(struct b43_wldev *dev,
3844                                 struct ieee80211_channel *channel,
3845                                 enum nl80211_channel_type channel_type)
3846 {
3847         struct b43_phy *phy = &dev->phy;
3848
3849         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
3850         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
3851
3852         u8 tmp;
3853
3854         if (dev->phy.rev >= 3) {
3855                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3856                                                         channel->center_freq);
3857                 if (!tabent_r3)
3858                         return -ESRCH;
3859         } else {
3860                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3861                                                         channel->hw_value);
3862                 if (!tabent_r2)
3863                         return -ESRCH;
3864         }
3865
3866         /* Channel is set later in common code, but we need to set it on our
3867            own to let this function's subcalls work properly. */
3868         phy->channel = channel->hw_value;
3869         phy->channel_freq = channel->center_freq;
3870
3871         if (b43_channel_type_is_40mhz(phy->channel_type) !=
3872                 b43_channel_type_is_40mhz(channel_type))
3873                 ; /* TODO: BMAC BW Set (channel_type) */
3874
3875         if (channel_type == NL80211_CHAN_HT40PLUS)
3876                 b43_phy_set(dev, B43_NPHY_RXCTL,
3877                                 B43_NPHY_RXCTL_BSELU20);
3878         else if (channel_type == NL80211_CHAN_HT40MINUS)
3879                 b43_phy_mask(dev, B43_NPHY_RXCTL,
3880                                 ~B43_NPHY_RXCTL_BSELU20);
3881
3882         if (dev->phy.rev >= 3) {
3883                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3884                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3885                 b43_radio_2056_setup(dev, tabent_r3);
3886                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3887         } else {
3888                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3889                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3890                 b43_radio_2055_setup(dev, tabent_r2);
3891                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3892         }
3893
3894         return 0;
3895 }
3896
3897 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3898 {
3899         struct b43_phy_n *nphy;
3900
3901         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3902         if (!nphy)
3903                 return -ENOMEM;
3904         dev->phy.n = nphy;
3905
3906         return 0;
3907 }
3908
3909 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3910 {
3911         struct b43_phy *phy = &dev->phy;
3912         struct b43_phy_n *nphy = phy->n;
3913
3914         memset(nphy, 0, sizeof(*nphy));
3915
3916         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
3917         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3918         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3919         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
3920         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
3921 }
3922
3923 static void b43_nphy_op_free(struct b43_wldev *dev)
3924 {
3925         struct b43_phy *phy = &dev->phy;
3926         struct b43_phy_n *nphy = phy->n;
3927
3928         kfree(nphy);
3929         phy->n = NULL;
3930 }
3931
3932 static int b43_nphy_op_init(struct b43_wldev *dev)
3933 {
3934         return b43_phy_initn(dev);
3935 }
3936
3937 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3938 {
3939 #if B43_DEBUG
3940         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3941                 /* OFDM registers are onnly available on A/G-PHYs */
3942                 b43err(dev->wl, "Invalid OFDM PHY access at "
3943                        "0x%04X on N-PHY\n", offset);
3944                 dump_stack();
3945         }
3946         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3947                 /* Ext-G registers are only available on G-PHYs */
3948                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3949                        "0x%04X on N-PHY\n", offset);
3950                 dump_stack();
3951         }
3952 #endif /* B43_DEBUG */
3953 }
3954
3955 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3956 {
3957         check_phyreg(dev, reg);
3958         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3959         return b43_read16(dev, B43_MMIO_PHY_DATA);
3960 }
3961
3962 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3963 {
3964         check_phyreg(dev, reg);
3965         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3966         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3967 }
3968
3969 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
3970                                  u16 set)
3971 {
3972         check_phyreg(dev, reg);
3973         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3974         b43_write16(dev, B43_MMIO_PHY_DATA,
3975                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
3976 }
3977
3978 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3979 {
3980         /* Register 1 is a 32-bit register. */
3981         B43_WARN_ON(reg == 1);
3982         /* N-PHY needs 0x100 for read access */
3983         reg |= 0x100;
3984
3985         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3986         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3987 }
3988
3989 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3990 {
3991         /* Register 1 is a 32-bit register. */
3992         B43_WARN_ON(reg == 1);
3993
3994         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3995         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3996 }
3997
3998 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3999 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4000                                         bool blocked)
4001 {
4002         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4003                 b43err(dev->wl, "MAC not suspended\n");
4004
4005         if (blocked) {
4006                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4007                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4008                 if (dev->phy.rev >= 3) {
4009                         b43_radio_mask(dev, 0x09, ~0x2);
4010
4011                         b43_radio_write(dev, 0x204D, 0);
4012                         b43_radio_write(dev, 0x2053, 0);
4013                         b43_radio_write(dev, 0x2058, 0);
4014                         b43_radio_write(dev, 0x205E, 0);
4015                         b43_radio_mask(dev, 0x2062, ~0xF0);
4016                         b43_radio_write(dev, 0x2064, 0);
4017
4018                         b43_radio_write(dev, 0x304D, 0);
4019                         b43_radio_write(dev, 0x3053, 0);
4020                         b43_radio_write(dev, 0x3058, 0);
4021                         b43_radio_write(dev, 0x305E, 0);
4022                         b43_radio_mask(dev, 0x3062, ~0xF0);
4023                         b43_radio_write(dev, 0x3064, 0);
4024                 }
4025         } else {
4026                 if (dev->phy.rev >= 3) {
4027                         b43_radio_init2056(dev);
4028                         b43_switch_channel(dev, dev->phy.channel);
4029                 } else {
4030                         b43_radio_init2055(dev);
4031                 }
4032         }
4033 }
4034
4035 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4036 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4037 {
4038         u16 override = on ? 0x0 : 0x7FFF;
4039         u16 core = on ? 0xD : 0x00FD;
4040
4041         if (dev->phy.rev >= 3) {
4042                 if (on) {
4043                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4044                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4045                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4046                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4047                 } else {
4048                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4049                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4050                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4051                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4052                 }
4053         } else {
4054                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4055         }
4056 }
4057
4058 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4059                                       unsigned int new_channel)
4060 {
4061         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4062         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4063
4064         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4065                 if ((new_channel < 1) || (new_channel > 14))
4066                         return -EINVAL;
4067         } else {
4068                 if (new_channel > 200)
4069                         return -EINVAL;
4070         }
4071
4072         return b43_nphy_set_channel(dev, channel, channel_type);
4073 }
4074
4075 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4076 {
4077         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4078                 return 1;
4079         return 36;
4080 }
4081
4082 const struct b43_phy_operations b43_phyops_n = {
4083         .allocate               = b43_nphy_op_allocate,
4084         .free                   = b43_nphy_op_free,
4085         .prepare_structs        = b43_nphy_op_prepare_structs,
4086         .init                   = b43_nphy_op_init,
4087         .phy_read               = b43_nphy_op_read,
4088         .phy_write              = b43_nphy_op_write,
4089         .phy_maskset            = b43_nphy_op_maskset,
4090         .radio_read             = b43_nphy_op_radio_read,
4091         .radio_write            = b43_nphy_op_radio_write,
4092         .software_rfkill        = b43_nphy_op_software_rfkill,
4093         .switch_analog          = b43_nphy_op_switch_analog,
4094         .switch_channel         = b43_nphy_op_switch_channel,
4095         .get_default_chan       = b43_nphy_op_get_default_chan,
4096         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4097         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4098 };