drivers/net/wireless/b43/phy_lp.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11g LP-PHY driver
   5
   6   Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include "b43.h"
  26 #include "main.h"
  27 #include "phy_lp.h"
  28 #include "phy_common.h"
  29 #include "tables_lpphy.h"
  30
  31
  32 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
  33 {
  34         struct b43_phy_lp *lpphy;
  35
  36         lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
  37         if (!lpphy)
  38                 return -ENOMEM;
  39         dev->phy.lp = lpphy;
  40
  41         return 0;
  42 }
  43
  44 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
  45 {
  46         struct b43_phy *phy = &dev->phy;
  47         struct b43_phy_lp *lpphy = phy->lp;
  48
  49         memset(lpphy, 0, sizeof(*lpphy));
  50
  51         //TODO
  52 }
  53
  54 static void b43_lpphy_op_free(struct b43_wldev *dev)
  55 {
  56         struct b43_phy_lp *lpphy = dev->phy.lp;
  57
  58         kfree(lpphy);
  59         dev->phy.lp = NULL;
  60 }
  61
  62 static void lpphy_table_init(struct b43_wldev *dev)
  63 {
  64         //TODO
  65 }
  66
  67 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
  68 {
  69         struct ssb_bus *bus = dev->dev->bus;
  70         u16 tmp, tmp2;
  71
  72         if (dev->phy.rev == 1 &&
  73            (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
  74                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
  75                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
  76                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
  77                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
  78                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
  79                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
  80                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
  81                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
  82                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
  83                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
  84                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
  85                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
  86                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
  87                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
  88                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
  89                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
  90         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
  91                   (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
  92                   (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
  93                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
  94                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
  95                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
  96                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
  97                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
  98                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
  99                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
 100                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
 101         } else if (dev->phy.rev == 1 ||
 102                   (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
 103                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
 104                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
 105                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
 106                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
 107                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
 108                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
 109                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
 110                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
 111         } else {
 112                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
 113                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
 114                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
 115                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
 116                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
 117                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
 118                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
 119                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
 120         }
 121         if (dev->phy.rev == 1) {
 122                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
 123                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
 124                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
 125                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
 126         }
 127         if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
 128             (bus->chip_id == 0x5354) &&
 129             (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
 130                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
 131                 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
 132                 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
 133                 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
 134         }
 135         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 136                 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
 137                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
 138                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
 139                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
 140                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
 141                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
 142                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
 143                 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
 144         } else { /* 5GHz */
 145                 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
 146                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
 147         }
 148         if (dev->phy.rev == 1) {
 149                 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
 150                 tmp2 = (tmp & 0x03E0) >> 5;
 151                 tmp2 |= tmp << 5;
 152                 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
 153                 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
 154                 tmp2 = (tmp & 0x1F00) >> 8;
 155                 tmp2 |= tmp << 5;
 156                 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
 157                 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
 158                 tmp2 = tmp & 0x00FF;
 159                 tmp2 |= tmp << 8;
 160                 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
 161         }
 162 }
 163
 164 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
 165 {
 166         struct ssb_bus *bus = dev->dev->bus;
 167         struct b43_phy_lp *lpphy = dev->phy.lp;
 168
 169         b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
 170         b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
 171         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
 172         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
 173         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
 174         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
 175         b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
 176         b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
 177         b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
 178         b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x78);
 179         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
 180         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
 181         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
 182         b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
 183         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
 184         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
 185         b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
 186         b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
 187         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
 188         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
 189         b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
 190         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
 191         b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
 192         b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
 193         b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
 194         b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
 195         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
 196         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
 197         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
 198         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
 199                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
 200                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
 201         } else {
 202                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
 203                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
 204         }
 205         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
 206         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
 207         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
 208         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
 209         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
 210         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
 211         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
 212         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
 213         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
 214         b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
 215
 216         b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
 217         b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
 218
 219         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 220                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
 221                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
 222                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
 223                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
 224                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
 225         } else /* 5GHz */
 226                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
 227
 228         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
 229         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
 230         b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
 231         b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
 232         b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
 233         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
 234         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
 235                       0x2000 | ((u16)lpphy->rssi_gs << 10) |
 236                       ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
 237 }
 238
 239 static void lpphy_baseband_init(struct b43_wldev *dev)
 240 {
 241         lpphy_table_init(dev);
 242         if (dev->phy.rev >= 2)
 243                 lpphy_baseband_rev2plus_init(dev);
 244         else
 245                 lpphy_baseband_rev0_1_init(dev);
 246 }
 247
 248 struct b2062_freqdata {
 249         u16 freq;
 250         u8 data[6];
 251 };
 252
 253 /* Initialize the 2062 radio. */
 254 static void lpphy_2062_init(struct b43_wldev *dev)
 255 {
 256         struct ssb_bus *bus = dev->dev->bus;
 257         u32 crystalfreq, pdiv, tmp, ref;
 258         unsigned int i;
 259         const struct b2062_freqdata *fd = NULL;
 260
 261         static const struct b2062_freqdata freqdata_tab[] = {
 262                 { .freq = 12000, .data[0] =  6, .data[1] =  6, .data[2] =  6,
 263                                  .data[3] =  6, .data[4] = 10, .data[5] =  6, },
 264                 { .freq = 13000, .data[0] =  4, .data[1] =  4, .data[2] =  4,
 265                                  .data[3] =  4, .data[4] = 11, .data[5] =  7, },
 266                 { .freq = 14400, .data[0] =  3, .data[1] =  3, .data[2] =  3,
 267                                  .data[3] =  3, .data[4] = 12, .data[5] =  7, },
 268                 { .freq = 16200, .data[0] =  3, .data[1] =  3, .data[2] =  3,
 269                                  .data[3] =  3, .data[4] = 13, .data[5] =  8, },
 270                 { .freq = 18000, .data[0] =  2, .data[1] =  2, .data[2] =  2,
 271                                  .data[3] =  2, .data[4] = 14, .data[5] =  8, },
 272                 { .freq = 19200, .data[0] =  1, .data[1] =  1, .data[2] =  1,
 273                                  .data[3] =  1, .data[4] = 14, .data[5] =  9, },
 274         };
 275
 276         b2062_upload_init_table(dev);
 277
 278         b43_radio_write(dev, B2062_N_TX_CTL3, 0);
 279         b43_radio_write(dev, B2062_N_TX_CTL4, 0);
 280         b43_radio_write(dev, B2062_N_TX_CTL5, 0);
 281         b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
 282         b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
 283         b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
 284         b43_radio_write(dev, B2062_N_CALIB_TS, 0);
 285         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 286                 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
 287         else
 288                 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
 289
 290         /* Get the crystal freq, in Hz. */
 291         crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
 292
 293         B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
 294         B43_WARN_ON(crystalfreq == 0);
 295
 296         if (crystalfreq >= 30000000) {
 297                 pdiv = 1;
 298                 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
 299         } else {
 300                 pdiv = 2;
 301                 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
 302         }
 303
 304         tmp = (800000000 * pdiv + crystalfreq) / (32000000 * pdiv);
 305         tmp = (tmp - 1) & 0xFF;
 306         b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
 307
 308         tmp = (2 * crystalfreq + 1000000 * pdiv) / (2000000 * pdiv);
 309         tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
 310         b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
 311
 312         ref = (1000 * pdiv + 2 * crystalfreq) / (2000 * pdiv);
 313         ref &= 0xFFFF;
 314         for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
 315                 if (ref < freqdata_tab[i].freq) {
 316                         fd = &freqdata_tab[i];
 317                         break;
 318                 }
 319         }
 320         if (!fd)
 321                 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
 322         b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
 323                fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
 324
 325         b43_radio_write(dev, B2062_S_RFPLL_CTL8,
 326                         ((u16)(fd->data[1]) << 4) | fd->data[0]);
 327         b43_radio_write(dev, B2062_S_RFPLL_CTL9,
 328                         ((u16)(fd->data[3]) << 4) | fd->data[2]);
 329         b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
 330         b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
 331 }
 332
 333 /* Initialize the 2063 radio. */
 334 static void lpphy_2063_init(struct b43_wldev *dev)
 335 {
 336         b2063_upload_init_table(dev);
 337         b43_radio_write(dev, B2063_LOGEN_SP5, 0);
 338         b43_radio_set(dev, B2063_COMM8, 0x38);
 339         b43_radio_write(dev, B2063_REG_SP1, 0x56);
 340         b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
 341         b43_radio_write(dev, B2063_PA_SP7, 0);
 342         b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
 343         b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
 344         b43_radio_write(dev, B2063_PA_SP3, 0xa0);
 345         b43_radio_write(dev, B2063_PA_SP4, 0xa0);
 346         b43_radio_write(dev, B2063_PA_SP2, 0x18);
 347 }
 348
 349 struct lpphy_stx_table_entry {
 350         u16 phy_offset;
 351         u16 phy_shift;
 352         u16 rf_addr;
 353         u16 rf_shift;
 354         u16 mask;
 355 };
 356
 357 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
 358         { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
 359         { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
 360         { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
 361         { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
 362         { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
 363         { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
 364         { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
 365         { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
 366         { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
 367         { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
 368         { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
 369         { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
 370         { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
 371         { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
 372         { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
 373         { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
 374         { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
 375         { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
 376         { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
 377         { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
 378         { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
 379         { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
 380         { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
 381         { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
 382         { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
 383         { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
 384         { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
 385         { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
 386         { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
 387 };
 388
 389 static void lpphy_sync_stx(struct b43_wldev *dev)
 390 {
 391         const struct lpphy_stx_table_entry *e;
 392         unsigned int i;
 393         u16 tmp;
 394
 395         for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
 396                 e = &lpphy_stx_table[i];
 397                 tmp = b43_radio_read(dev, e->rf_addr);
 398                 tmp >>= e->rf_shift;
 399                 tmp <<= e->phy_shift;
 400                 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
 401                                 e->mask << e->phy_shift, tmp);
 402         }
 403 }
 404
 405 static void lpphy_radio_init(struct b43_wldev *dev)
 406 {
 407         /* The radio is attached through the 4wire bus. */
 408         b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
 409         udelay(1);
 410         b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
 411         udelay(1);
 412
 413         if (dev->phy.rev < 2) {
 414                 lpphy_2062_init(dev);
 415         } else {
 416                 lpphy_2063_init(dev);
 417                 lpphy_sync_stx(dev);
 418                 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
 419                 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
 420                 if (dev->dev->bus->chip_id == 0x4325) {
 421                         // TODO SSB PMU recalibration
 422                 }
 423         }
 424 }
 425
 426 /* Read the TX power control mode from hardware. */
 427 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
 428 {
 429         struct b43_phy_lp *lpphy = dev->phy.lp;
 430         u16 ctl;
 431
 432         ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
 433         switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
 434         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
 435                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
 436                 break;
 437         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
 438                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
 439                 break;
 440         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
 441                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
 442                 break;
 443         default:
 444                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
 445                 B43_WARN_ON(1);
 446                 break;
 447         }
 448 }
 449
 450 /* Set the TX power control mode in hardware. */
 451 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
 452 {
 453         struct b43_phy_lp *lpphy = dev->phy.lp;
 454         u16 ctl;
 455
 456         switch (lpphy->txpctl_mode) {
 457         case B43_LPPHY_TXPCTL_OFF:
 458                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
 459                 break;
 460         case B43_LPPHY_TXPCTL_HW:
 461                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
 462                 break;
 463         case B43_LPPHY_TXPCTL_SW:
 464                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
 465                 break;
 466         default:
 467                 ctl = 0;
 468                 B43_WARN_ON(1);
 469         }
 470         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
 471                         (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
 472 }
 473
 474 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
 475                                        enum b43_lpphy_txpctl_mode mode)
 476 {
 477         struct b43_phy_lp *lpphy = dev->phy.lp;
 478         enum b43_lpphy_txpctl_mode oldmode;
 479
 480         oldmode = lpphy->txpctl_mode;
 481         lpphy_read_tx_pctl_mode_from_hardware(dev);
 482         if (lpphy->txpctl_mode == mode)
 483                 return;
 484         lpphy->txpctl_mode = mode;
 485
 486         if (oldmode == B43_LPPHY_TXPCTL_HW) {
 487                 //TODO Update TX Power NPT
 488                 //TODO Clear all TX Power offsets
 489         } else {
 490                 if (mode == B43_LPPHY_TXPCTL_HW) {
 491                         //TODO Recalculate target TX power
 492                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
 493                                         0xFF80, lpphy->tssi_idx);
 494                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
 495                                         0x8FFF, ((u16)lpphy->tssi_npt << 16));
 496                         //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
 497                         //TODO Disable TX gain override
 498                         lpphy->tx_pwr_idx_over = -1;
 499                 }
 500         }
 501         if (dev->phy.rev >= 2) {
 502                 if (mode == B43_LPPHY_TXPCTL_HW)
 503                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
 504                 else
 505                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
 506         }
 507         lpphy_write_tx_pctl_mode_to_hardware(dev);
 508 }
 509
 510 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
 511 {
 512         struct b43_phy_lp *lpphy = dev->phy.lp;
 513
 514         lpphy->tx_pwr_idx_over = index;
 515         if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
 516                 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
 517
 518         //TODO
 519 }
 520
 521 static void lpphy_btcoex_override(struct b43_wldev *dev)
 522 {
 523         b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
 524         b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
 525 }
 526
 527 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
 528 {
 529         struct b43_phy_lp *lpphy = dev->phy.lp;
 530         u32 *saved_tab;
 531         const unsigned int saved_tab_size = 256;
 532         enum b43_lpphy_txpctl_mode txpctl_mode;
 533         s8 tx_pwr_idx_over;
 534         u16 tssi_npt, tssi_idx;
 535
 536         saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
 537         if (!saved_tab) {
 538                 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
 539                 return;
 540         }
 541
 542         lpphy_read_tx_pctl_mode_from_hardware(dev);
 543         txpctl_mode = lpphy->txpctl_mode;
 544         tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
 545         tssi_npt = lpphy->tssi_npt;
 546         tssi_idx = lpphy->tssi_idx;
 547
 548         if (dev->phy.rev < 2) {
 549                 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
 550                                     saved_tab_size, saved_tab);
 551         } else {
 552                 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
 553                                     saved_tab_size, saved_tab);
 554         }
 555         //TODO
 556
 557         kfree(saved_tab);
 558 }
 559
 560 static void lpphy_calibration(struct b43_wldev *dev)
 561 {
 562         struct b43_phy_lp *lpphy = dev->phy.lp;
 563         enum b43_lpphy_txpctl_mode saved_pctl_mode;
 564
 565         b43_mac_suspend(dev);
 566
 567         lpphy_btcoex_override(dev);
 568         lpphy_read_tx_pctl_mode_from_hardware(dev);
 569         saved_pctl_mode = lpphy->txpctl_mode;
 570         lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
 571         //TODO Perform transmit power table I/Q LO calibration
 572         if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
 573                 lpphy_pr41573_workaround(dev);
 574         //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
 575         lpphy_set_tx_power_control(dev, saved_pctl_mode);
 576         //TODO Perform I/Q calibration with a single control value set
 577
 578         b43_mac_enable(dev);
 579 }
 580
 581 /* Initialize TX power control */
 582 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
 583 {
 584         if (0/*FIXME HWPCTL capable */) {
 585                 //TODO
 586         } else { /* This device is only software TX power control capable. */
 587                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 588                         //TODO
 589                 } else {
 590                         //TODO
 591                 }
 592                 //TODO set BB multiplier to 0x0096
 593         }
 594 }
 595
 596 static int b43_lpphy_op_init(struct b43_wldev *dev)
 597 {
 598         /* TODO: band SPROM */
 599         /* TODO: tables init */
 600         lpphy_baseband_init(dev);
 601         lpphy_radio_init(dev);
 602         //TODO calibrate RC
 603         //TODO set channel
 604         lpphy_tx_pctl_init(dev);
 605         //TODO full calib
 606
 607         return 0;
 608 }
 609
 610 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
 611 {
 612         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 613         return b43_read16(dev, B43_MMIO_PHY_DATA);
 614 }
 615
 616 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 617 {
 618         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 619         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 620 }
 621
 622 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 623 {
 624         /* Register 1 is a 32-bit register. */
 625         B43_WARN_ON(reg == 1);
 626         /* LP-PHY needs a special bit set for read access */
 627         if (dev->phy.rev < 2) {
 628                 if (reg != 0x4001)
 629                         reg |= 0x100;
 630         } else
 631                 reg |= 0x200;
 632
 633         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 634         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 635 }
 636
 637 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 638 {
 639         /* Register 1 is a 32-bit register. */
 640         B43_WARN_ON(reg == 1);
 641
 642         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 643         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 644 }
 645
 646 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
 647                                          bool blocked)
 648 {
 649         //TODO
 650 }
 651
 652 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
 653                                        unsigned int new_channel)
 654 {
 655         //TODO
 656         return 0;
 657 }
 658
 659 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
 660 {
 661         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 662                 return 1;
 663         return 36;
 664 }
 665
 666 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
 667 {
 668         //TODO
 669 }
 670
 671 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
 672 {
 673         //TODO
 674 }
 675
 676 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
 677                                                          bool ignore_tssi)
 678 {
 679         //TODO
 680         return B43_TXPWR_RES_DONE;
 681 }
 682
 683
 684 const struct b43_phy_operations b43_phyops_lp = {
 685         .allocate               = b43_lpphy_op_allocate,
 686         .free                   = b43_lpphy_op_free,
 687         .prepare_structs        = b43_lpphy_op_prepare_structs,
 688         .init                   = b43_lpphy_op_init,
 689         .phy_read               = b43_lpphy_op_read,
 690         .phy_write              = b43_lpphy_op_write,
 691         .radio_read             = b43_lpphy_op_radio_read,
 692         .radio_write            = b43_lpphy_op_radio_write,
 693         .software_rfkill        = b43_lpphy_op_software_rfkill,
 694         .switch_analog          = b43_phyop_switch_analog_generic,
 695         .switch_channel         = b43_lpphy_op_switch_channel,
 696         .get_default_chan       = b43_lpphy_op_get_default_chan,
 697         .set_rx_antenna         = b43_lpphy_op_set_rx_antenna,
 698         .recalc_txpower         = b43_lpphy_op_recalc_txpower,
 699         .adjust_txpower         = b43_lpphy_op_adjust_txpower,
 700 };