drivers/net/wireless/b43/phy.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   6   Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   This program is free software; you can redistribute it and/or modify
  12   it under the terms of the GNU General Public License as published by
  13   the Free Software Foundation; either version 2 of the License, or
  14   (at your option) any later version.
  15
  16   This program is distributed in the hope that it will be useful,
  17   but WITHOUT ANY WARRANTY; without even the implied warranty of
  18   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19   GNU General Public License for more details.
  20
  21   You should have received a copy of the GNU General Public License
  22   along with this program; see the file COPYING.  If not, write to
  23   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  24   Boston, MA 02110-1301, USA.
  25
  26 */
  27
  28 #include <linux/delay.h>
  29 #include <linux/io.h>
  30 #include <linux/types.h>
  31
  32 #include "b43.h"
  33 #include "phy.h"
  34 #include "main.h"
  35 #include "tables.h"
  36 #include "lo.h"
  37 #include "wa.h"
  38
  39
  40 static const s8 b43_tssi2dbm_b_table[] = {
  41         0x4D, 0x4C, 0x4B, 0x4A,
  42         0x4A, 0x49, 0x48, 0x47,
  43         0x47, 0x46, 0x45, 0x45,
  44         0x44, 0x43, 0x42, 0x42,
  45         0x41, 0x40, 0x3F, 0x3E,
  46         0x3D, 0x3C, 0x3B, 0x3A,
  47         0x39, 0x38, 0x37, 0x36,
  48         0x35, 0x34, 0x32, 0x31,
  49         0x30, 0x2F, 0x2D, 0x2C,
  50         0x2B, 0x29, 0x28, 0x26,
  51         0x25, 0x23, 0x21, 0x1F,
  52         0x1D, 0x1A, 0x17, 0x14,
  53         0x10, 0x0C, 0x06, 0x00,
  54         -7, -7, -7, -7,
  55         -7, -7, -7, -7,
  56         -7, -7, -7, -7,
  57 };
  58
  59 static const s8 b43_tssi2dbm_g_table[] = {
  60         77, 77, 77, 76,
  61         76, 76, 75, 75,
  62         74, 74, 73, 73,
  63         73, 72, 72, 71,
  64         71, 70, 70, 69,
  65         68, 68, 67, 67,
  66         66, 65, 65, 64,
  67         63, 63, 62, 61,
  68         60, 59, 58, 57,
  69         56, 55, 54, 53,
  70         52, 50, 49, 47,
  71         45, 43, 40, 37,
  72         33, 28, 22, 14,
  73         5, -7, -20, -20,
  74         -20, -20, -20, -20,
  75         -20, -20, -20, -20,
  76 };
  77
  78 const u8 b43_radio_channel_codes_bg[] = {
  79         12, 17, 22, 27,
  80         32, 37, 42, 47,
  81         52, 57, 62, 67,
  82         72, 84,
  83 };
  84
  85 static void b43_phy_initg(struct b43_wldev *dev);
  86
  87 /* Reverse the bits of a 4bit value.
  88  * Example:  1101 is flipped 1011
  89  */
  90 static u16 flip_4bit(u16 value)
  91 {
  92         u16 flipped = 0x0000;
  93
  94         B43_WARN_ON(value & ~0x000F);
  95
  96         flipped |= (value & 0x0001) << 3;
  97         flipped |= (value & 0x0002) << 1;
  98         flipped |= (value & 0x0004) >> 1;
  99         flipped |= (value & 0x0008) >> 3;
 100
 101         return flipped;
 102 }
 103
 104 static void generate_rfatt_list(struct b43_wldev *dev,
 105                                 struct b43_rfatt_list *list)
 106 {
 107         struct b43_phy *phy = &dev->phy;
 108
 109         /* APHY.rev < 5 || GPHY.rev < 6 */
 110         static const struct b43_rfatt rfatt_0[] = {
 111                 {.att = 3,.with_padmix = 0,},
 112                 {.att = 1,.with_padmix = 0,},
 113                 {.att = 5,.with_padmix = 0,},
 114                 {.att = 7,.with_padmix = 0,},
 115                 {.att = 9,.with_padmix = 0,},
 116                 {.att = 2,.with_padmix = 0,},
 117                 {.att = 0,.with_padmix = 0,},
 118                 {.att = 4,.with_padmix = 0,},
 119                 {.att = 6,.with_padmix = 0,},
 120                 {.att = 8,.with_padmix = 0,},
 121                 {.att = 1,.with_padmix = 1,},
 122                 {.att = 2,.with_padmix = 1,},
 123                 {.att = 3,.with_padmix = 1,},
 124                 {.att = 4,.with_padmix = 1,},
 125         };
 126         /* Radio.rev == 8 && Radio.version == 0x2050 */
 127         static const struct b43_rfatt rfatt_1[] = {
 128                 {.att = 2,.with_padmix = 1,},
 129                 {.att = 4,.with_padmix = 1,},
 130                 {.att = 6,.with_padmix = 1,},
 131                 {.att = 8,.with_padmix = 1,},
 132                 {.att = 10,.with_padmix = 1,},
 133                 {.att = 12,.with_padmix = 1,},
 134                 {.att = 14,.with_padmix = 1,},
 135         };
 136         /* Otherwise */
 137         static const struct b43_rfatt rfatt_2[] = {
 138                 {.att = 0,.with_padmix = 1,},
 139                 {.att = 2,.with_padmix = 1,},
 140                 {.att = 4,.with_padmix = 1,},
 141                 {.att = 6,.with_padmix = 1,},
 142                 {.att = 8,.with_padmix = 1,},
 143                 {.att = 9,.with_padmix = 1,},
 144                 {.att = 9,.with_padmix = 1,},
 145         };
 146
 147         if ((phy->type == B43_PHYTYPE_A && phy->rev < 5) ||
 148             (phy->type == B43_PHYTYPE_G && phy->rev < 6)) {
 149                 /* Software pctl */
 150                 list->list = rfatt_0;
 151                 list->len = ARRAY_SIZE(rfatt_0);
 152                 list->min_val = 0;
 153                 list->max_val = 9;
 154                 return;
 155         }
 156         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 157                 /* Hardware pctl */
 158                 list->list = rfatt_1;
 159                 list->len = ARRAY_SIZE(rfatt_1);
 160                 list->min_val = 2;
 161                 list->max_val = 14;
 162                 return;
 163         }
 164         /* Hardware pctl */
 165         list->list = rfatt_2;
 166         list->len = ARRAY_SIZE(rfatt_2);
 167         list->min_val = 0;
 168         list->max_val = 9;
 169 }
 170
 171 static void generate_bbatt_list(struct b43_wldev *dev,
 172                                 struct b43_bbatt_list *list)
 173 {
 174         static const struct b43_bbatt bbatt_0[] = {
 175                 {.att = 0,},
 176                 {.att = 1,},
 177                 {.att = 2,},
 178                 {.att = 3,},
 179                 {.att = 4,},
 180                 {.att = 5,},
 181                 {.att = 6,},
 182                 {.att = 7,},
 183                 {.att = 8,},
 184         };
 185
 186         list->list = bbatt_0;
 187         list->len = ARRAY_SIZE(bbatt_0);
 188         list->min_val = 0;
 189         list->max_val = 8;
 190 }
 191
 192 bool b43_has_hardware_pctl(struct b43_phy *phy)
 193 {
 194         if (!phy->hardware_power_control)
 195                 return 0;
 196         switch (phy->type) {
 197         case B43_PHYTYPE_A:
 198                 if (phy->rev >= 5)
 199                         return 1;
 200                 break;
 201         case B43_PHYTYPE_G:
 202                 if (phy->rev >= 6)
 203                         return 1;
 204                 break;
 205         default:
 206                 B43_WARN_ON(1);
 207         }
 208         return 0;
 209 }
 210
 211 static void b43_shm_clear_tssi(struct b43_wldev *dev)
 212 {
 213         struct b43_phy *phy = &dev->phy;
 214
 215         switch (phy->type) {
 216         case B43_PHYTYPE_A:
 217                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0068, 0x7F7F);
 218                 b43_shm_write16(dev, B43_SHM_SHARED, 0x006a, 0x7F7F);
 219                 break;
 220         case B43_PHYTYPE_B:
 221         case B43_PHYTYPE_G:
 222                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
 223                 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
 224                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
 225                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
 226                 break;
 227         }
 228 }
 229
 230 void b43_raw_phy_lock(struct b43_wldev *dev)
 231 {
 232         struct b43_phy *phy = &dev->phy;
 233
 234         B43_WARN_ON(!irqs_disabled());
 235
 236         /* We had a check for MACCTL==0 here, but I think that doesn't
 237          * make sense, as MACCTL is never 0 when this is called.
 238          *      --mb */
 239         B43_WARN_ON(b43_read32(dev, B43_MMIO_MACCTL) == 0);
 240
 241         if (dev->dev->id.revision < 3) {
 242                 b43_mac_suspend(dev);
 243                 spin_lock(&phy->lock);
 244         } else {
 245                 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
 246                         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
 247         }
 248         phy->locked = 1;
 249 }
 250
 251 void b43_raw_phy_unlock(struct b43_wldev *dev)
 252 {
 253         struct b43_phy *phy = &dev->phy;
 254
 255         B43_WARN_ON(!irqs_disabled());
 256         if (dev->dev->id.revision < 3) {
 257                 if (phy->locked) {
 258                         spin_unlock(&phy->lock);
 259                         b43_mac_enable(dev);
 260                 }
 261         } else {
 262                 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
 263                         b43_power_saving_ctl_bits(dev, 0);
 264         }
 265         phy->locked = 0;
 266 }
 267
 268 /* Different PHYs require different register routing flags.
 269  * This adjusts (and does sanity checks on) the routing flags.
 270  */
 271 static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
 272                                             u16 offset, struct b43_wldev *dev)
 273 {
 274         if (phy->type == B43_PHYTYPE_A) {
 275                 /* OFDM registers are base-registers for the A-PHY. */
 276                 offset &= ~B43_PHYROUTE_OFDM_GPHY;
 277         }
 278         if (offset & B43_PHYROUTE_EXT_GPHY) {
 279                 /* Ext-G registers are only available on G-PHYs */
 280                 if (phy->type != B43_PHYTYPE_G) {
 281                         b43dbg(dev->wl, "EXT-G PHY access at "
 282                                "0x%04X on %u type PHY\n", offset, phy->type);
 283                 }
 284         }
 285
 286         return offset;
 287 }
 288
 289 u16 b43_phy_read(struct b43_wldev * dev, u16 offset)
 290 {
 291         struct b43_phy *phy = &dev->phy;
 292
 293         offset = adjust_phyreg_for_phytype(phy, offset, dev);
 294         b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
 295         return b43_read16(dev, B43_MMIO_PHY_DATA);
 296 }
 297
 298 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
 299 {
 300         struct b43_phy *phy = &dev->phy;
 301
 302         offset = adjust_phyreg_for_phytype(phy, offset, dev);
 303         b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
 304         mmiowb();
 305         b43_write16(dev, B43_MMIO_PHY_DATA, val);
 306 }
 307
 308 /* Adjust the transmission power output (G-PHY) */
 309 void b43_set_txpower_g(struct b43_wldev *dev,
 310                        const struct b43_bbatt *bbatt,
 311                        const struct b43_rfatt *rfatt, u8 tx_control)
 312 {
 313         struct b43_phy *phy = &dev->phy;
 314         struct b43_txpower_lo_control *lo = phy->lo_control;
 315         u16 bb, rf;
 316         u16 tx_bias, tx_magn;
 317
 318         bb = bbatt->att;
 319         rf = rfatt->att;
 320         tx_bias = lo->tx_bias;
 321         tx_magn = lo->tx_magn;
 322         if (unlikely(tx_bias == 0xFF))
 323                 tx_bias = 0;
 324
 325         /* Save the values for later */
 326         phy->tx_control = tx_control;
 327         memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
 328         memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
 329
 330         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
 331                 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
 332                        "rfatt(%u), tx_control(0x%02X), "
 333                        "tx_bias(0x%02X), tx_magn(0x%02X)\n",
 334                        bb, rf, tx_control, tx_bias, tx_magn);
 335         }
 336
 337         b43_phy_set_baseband_attenuation(dev, bb);
 338         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
 339         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 340                 b43_radio_write16(dev, 0x43,
 341                                   (rf & 0x000F) | (tx_control & 0x0070));
 342         } else {
 343                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
 344                                               & 0xFFF0) | (rf & 0x000F));
 345                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 346                                               & ~0x0070) | (tx_control &
 347                                                             0x0070));
 348         }
 349         if (has_tx_magnification(phy)) {
 350                 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
 351         } else {
 352                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 353                                               & 0xFFF0) | (tx_bias & 0x000F));
 354         }
 355         if (phy->type == B43_PHYTYPE_G)
 356                 b43_lo_g_adjust(dev);
 357 }
 358
 359 static void default_baseband_attenuation(struct b43_wldev *dev,
 360                                          struct b43_bbatt *bb)
 361 {
 362         struct b43_phy *phy = &dev->phy;
 363
 364         if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
 365                 bb->att = 0;
 366         else
 367                 bb->att = 2;
 368 }
 369
 370 static void default_radio_attenuation(struct b43_wldev *dev,
 371                                       struct b43_rfatt *rf)
 372 {
 373         struct ssb_bus *bus = dev->dev->bus;
 374         struct b43_phy *phy = &dev->phy;
 375
 376         rf->with_padmix = 0;
 377
 378         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
 379             bus->boardinfo.type == SSB_BOARD_BCM4309G) {
 380                 if (bus->boardinfo.rev < 0x43) {
 381                         rf->att = 2;
 382                         return;
 383                 } else if (bus->boardinfo.rev < 0x51) {
 384                         rf->att = 3;
 385                         return;
 386                 }
 387         }
 388
 389         if (phy->type == B43_PHYTYPE_A) {
 390                 rf->att = 0x60;
 391                 return;
 392         }
 393
 394         switch (phy->radio_ver) {
 395         case 0x2053:
 396                 switch (phy->radio_rev) {
 397                 case 1:
 398                         rf->att = 6;
 399                         return;
 400                 }
 401                 break;
 402         case 0x2050:
 403                 switch (phy->radio_rev) {
 404                 case 0:
 405                         rf->att = 5;
 406                         return;
 407                 case 1:
 408                         if (phy->type == B43_PHYTYPE_G) {
 409                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
 410                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
 411                                     && bus->boardinfo.rev >= 30)
 412                                         rf->att = 3;
 413                                 else if (bus->boardinfo.vendor ==
 414                                          SSB_BOARDVENDOR_BCM
 415                                          && bus->boardinfo.type ==
 416                                          SSB_BOARD_BU4306)
 417                                         rf->att = 3;
 418                                 else
 419                                         rf->att = 1;
 420                         } else {
 421                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
 422                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
 423                                     && bus->boardinfo.rev >= 30)
 424                                         rf->att = 7;
 425                                 else
 426                                         rf->att = 6;
 427                         }
 428                         return;
 429                 case 2:
 430                         if (phy->type == B43_PHYTYPE_G) {
 431                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
 432                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
 433                                     && bus->boardinfo.rev >= 30)
 434                                         rf->att = 3;
 435                                 else if (bus->boardinfo.vendor ==
 436                                          SSB_BOARDVENDOR_BCM
 437                                          && bus->boardinfo.type ==
 438                                          SSB_BOARD_BU4306)
 439                                         rf->att = 5;
 440                                 else if (bus->chip_id == 0x4320)
 441                                         rf->att = 4;
 442                                 else
 443                                         rf->att = 3;
 444                         } else
 445                                 rf->att = 6;
 446                         return;
 447                 case 3:
 448                         rf->att = 5;
 449                         return;
 450                 case 4:
 451                 case 5:
 452                         rf->att = 1;
 453                         return;
 454                 case 6:
 455                 case 7:
 456                         rf->att = 5;
 457                         return;
 458                 case 8:
 459                         rf->att = 0xA;
 460                         rf->with_padmix = 1;
 461                         return;
 462                 case 9:
 463                 default:
 464                         rf->att = 5;
 465                         return;
 466                 }
 467         }
 468         rf->att = 5;
 469 }
 470
 471 static u16 default_tx_control(struct b43_wldev *dev)
 472 {
 473         struct b43_phy *phy = &dev->phy;
 474
 475         if (phy->radio_ver != 0x2050)
 476                 return 0;
 477         if (phy->radio_rev == 1)
 478                 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
 479         if (phy->radio_rev < 6)
 480                 return B43_TXCTL_PA2DB;
 481         if (phy->radio_rev == 8)
 482                 return B43_TXCTL_TXMIX;
 483         return 0;
 484 }
 485
 486 /* This func is called "PHY calibrate" in the specs... */
 487 void b43_phy_early_init(struct b43_wldev *dev)
 488 {
 489         struct b43_phy *phy = &dev->phy;
 490         struct b43_txpower_lo_control *lo = phy->lo_control;
 491
 492         default_baseband_attenuation(dev, &phy->bbatt);
 493         default_radio_attenuation(dev, &phy->rfatt);
 494         phy->tx_control = (default_tx_control(dev) << 4);
 495
 496         /* Commit previous writes */
 497         b43_read32(dev, B43_MMIO_MACCTL);
 498
 499         if (phy->type == B43_PHYTYPE_B || phy->type == B43_PHYTYPE_G) {
 500                 generate_rfatt_list(dev, &lo->rfatt_list);
 501                 generate_bbatt_list(dev, &lo->bbatt_list);
 502         }
 503         if (phy->type == B43_PHYTYPE_G && phy->rev == 1) {
 504                 /* Workaround: Temporarly disable gmode through the early init
 505                  * phase, as the gmode stuff is not needed for phy rev 1 */
 506                 phy->gmode = 0;
 507                 b43_wireless_core_reset(dev, 0);
 508                 b43_phy_initg(dev);
 509                 phy->gmode = 1;
 510                 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
 511         }
 512 }
 513
 514 /* GPHY_TSSI_Power_Lookup_Table_Init */
 515 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
 516 {
 517         struct b43_phy *phy = &dev->phy;
 518         int i;
 519         u16 value;
 520
 521         for (i = 0; i < 32; i++)
 522                 b43_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
 523         for (i = 32; i < 64; i++)
 524                 b43_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
 525         for (i = 0; i < 64; i += 2) {
 526                 value = (u16) phy->tssi2dbm[i];
 527                 value |= ((u16) phy->tssi2dbm[i + 1]) << 8;
 528                 b43_phy_write(dev, 0x380 + (i / 2), value);
 529         }
 530 }
 531
 532 /* GPHY_Gain_Lookup_Table_Init */
 533 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
 534 {
 535         struct b43_phy *phy = &dev->phy;
 536         struct b43_txpower_lo_control *lo = phy->lo_control;
 537         u16 nr_written = 0;
 538         u16 tmp;
 539         u8 rf, bb;
 540
 541         if (!lo->lo_measured) {
 542                 b43_phy_write(dev, 0x3FF, 0);
 543                 return;
 544         }
 545
 546         for (rf = 0; rf < lo->rfatt_list.len; rf++) {
 547                 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
 548                         if (nr_written >= 0x40)
 549                                 return;
 550                         tmp = lo->bbatt_list.list[bb].att;
 551                         tmp <<= 8;
 552                         if (phy->radio_rev == 8)
 553                                 tmp |= 0x50;
 554                         else
 555                                 tmp |= 0x40;
 556                         tmp |= lo->rfatt_list.list[rf].att;
 557                         b43_phy_write(dev, 0x3C0 + nr_written, tmp);
 558                         nr_written++;
 559                 }
 560         }
 561 }
 562
 563 /* GPHY_DC_Lookup_Table */
 564 void b43_gphy_dc_lt_init(struct b43_wldev *dev)
 565 {
 566         struct b43_phy *phy = &dev->phy;
 567         struct b43_txpower_lo_control *lo = phy->lo_control;
 568         struct b43_loctl *loctl0;
 569         struct b43_loctl *loctl1;
 570         int i;
 571         int rf_offset, bb_offset;
 572         u16 tmp;
 573
 574         for (i = 0; i < lo->rfatt_list.len + lo->bbatt_list.len; i += 2) {
 575                 rf_offset = i / lo->rfatt_list.len;
 576                 bb_offset = i % lo->rfatt_list.len;
 577
 578                 loctl0 = b43_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
 579                                           &lo->bbatt_list.list[bb_offset]);
 580                 if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
 581                         rf_offset = (i + 1) / lo->rfatt_list.len;
 582                         bb_offset = (i + 1) % lo->rfatt_list.len;
 583
 584                         loctl1 =
 585                             b43_get_lo_g_ctl(dev,
 586                                              &lo->rfatt_list.list[rf_offset],
 587                                              &lo->bbatt_list.list[bb_offset]);
 588                 } else
 589                         loctl1 = loctl0;
 590
 591                 tmp = ((u16) loctl0->q & 0xF);
 592                 tmp |= ((u16) loctl0->i & 0xF) << 4;
 593                 tmp |= ((u16) loctl1->q & 0xF) << 8;
 594                 tmp |= ((u16) loctl1->i & 0xF) << 12;   //FIXME?
 595                 b43_phy_write(dev, 0x3A0 + (i / 2), tmp);
 596         }
 597 }
 598
 599 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
 600 {
 601         //TODO
 602 }
 603
 604 static void hardware_pctl_init_gphy(struct b43_wldev *dev)
 605 {
 606         struct b43_phy *phy = &dev->phy;
 607
 608         b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
 609                       | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
 610         b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
 611                       | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
 612         b43_gphy_tssi_power_lt_init(dev);
 613         b43_gphy_gain_lt_init(dev);
 614         b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
 615         b43_phy_write(dev, 0x0014, 0x0000);
 616
 617         B43_WARN_ON(phy->rev < 6);
 618         b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
 619                       | 0x0800);
 620         b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
 621                       & 0xFEFF);
 622         b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
 623                       & 0xFFBF);
 624
 625         b43_gphy_dc_lt_init(dev);
 626 }
 627
 628 /* HardwarePowerControl init for A and G PHY */
 629 static void b43_hardware_pctl_init(struct b43_wldev *dev)
 630 {
 631         struct b43_phy *phy = &dev->phy;
 632
 633         if (!b43_has_hardware_pctl(phy)) {
 634                 /* No hardware power control */
 635                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
 636                 return;
 637         }
 638         /* Init the hwpctl related hardware */
 639         switch (phy->type) {
 640         case B43_PHYTYPE_A:
 641                 hardware_pctl_init_aphy(dev);
 642                 break;
 643         case B43_PHYTYPE_G:
 644                 hardware_pctl_init_gphy(dev);
 645                 break;
 646         default:
 647                 B43_WARN_ON(1);
 648         }
 649         /* Enable hardware pctl in firmware. */
 650         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
 651 }
 652
 653 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
 654 {
 655         struct b43_phy *phy = &dev->phy;
 656
 657         if (!b43_has_hardware_pctl(phy)) {
 658                 b43_phy_write(dev, 0x047A, 0xC111);
 659                 return;
 660         }
 661
 662         b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
 663         b43_phy_write(dev, 0x002F, 0x0202);
 664         b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
 665         b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
 666         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 667                 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
 668                                             & 0xFF0F) | 0x0010);
 669                 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
 670                               | 0x8000);
 671                 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
 672                                             & 0xFFC0) | 0x0010);
 673                 b43_phy_write(dev, 0x002E, 0xC07F);
 674                 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
 675                               | 0x0400);
 676         } else {
 677                 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
 678                               | 0x0200);
 679                 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
 680                               | 0x0400);
 681                 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
 682                               & 0x7FFF);
 683                 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
 684                               & 0xFFFE);
 685                 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
 686                                             & 0xFFC0) | 0x0010);
 687                 b43_phy_write(dev, 0x002E, 0xC07F);
 688                 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
 689                                             & 0xFF0F) | 0x0010);
 690         }
 691 }
 692
 693 /* Intialize B/G PHY power control
 694  * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
 695  */
 696 static void b43_phy_init_pctl(struct b43_wldev *dev)
 697 {
 698         struct ssb_bus *bus = dev->dev->bus;
 699         struct b43_phy *phy = &dev->phy;
 700         struct b43_rfatt old_rfatt;
 701         struct b43_bbatt old_bbatt;
 702         u8 old_tx_control = 0;
 703
 704         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
 705             (bus->boardinfo.type == SSB_BOARD_BU4306))
 706                 return;
 707
 708         b43_phy_write(dev, 0x0028, 0x8018);
 709
 710         /* This does something with the Analog... */
 711         b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
 712                     & 0xFFDF);
 713
 714         if (phy->type == B43_PHYTYPE_G && !phy->gmode)
 715                 return;
 716         b43_hardware_pctl_early_init(dev);
 717         if (phy->cur_idle_tssi == 0) {
 718                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
 719                         b43_radio_write16(dev, 0x0076,
 720                                           (b43_radio_read16(dev, 0x0076)
 721                                            & 0x00F7) | 0x0084);
 722                 } else {
 723                         struct b43_rfatt rfatt;
 724                         struct b43_bbatt bbatt;
 725
 726                         memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
 727                         memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
 728                         old_tx_control = phy->tx_control;
 729
 730                         bbatt.att = 11;
 731                         if (phy->radio_rev == 8) {
 732                                 rfatt.att = 15;
 733                                 rfatt.with_padmix = 1;
 734                         } else {
 735                                 rfatt.att = 9;
 736                                 rfatt.with_padmix = 0;
 737                         }
 738                         b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
 739                 }
 740                 b43_dummy_transmission(dev);
 741                 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
 742                 if (B43_DEBUG) {
 743                         /* Current-Idle-TSSI sanity check. */
 744                         if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
 745                                 b43dbg(dev->wl,
 746                                        "!WARNING! Idle-TSSI phy->cur_idle_tssi "
 747                                        "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
 748                                        "adjustment.\n", phy->cur_idle_tssi,
 749                                        phy->tgt_idle_tssi);
 750                                 phy->cur_idle_tssi = 0;
 751                         }
 752                 }
 753                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
 754                         b43_radio_write16(dev, 0x0076,
 755                                           b43_radio_read16(dev, 0x0076)
 756                                           & 0xFF7B);
 757                 } else {
 758                         b43_set_txpower_g(dev, &old_bbatt,
 759                                           &old_rfatt, old_tx_control);
 760                 }
 761         }
 762         b43_hardware_pctl_init(dev);
 763         b43_shm_clear_tssi(dev);
 764 }
 765
 766 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
 767 {
 768         int i;
 769
 770         if (dev->phy.rev < 3) {
 771                 if (enable)
 772                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 773                                 b43_ofdmtab_write16(dev,
 774                                         B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
 775                                 b43_ofdmtab_write16(dev,
 776                                         B43_OFDMTAB_WRSSI, i, 0xFFF8);
 777                         }
 778                 else
 779                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 780                                 b43_ofdmtab_write16(dev,
 781                                         B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
 782                                 b43_ofdmtab_write16(dev,
 783                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
 784                         }
 785         } else {
 786                 if (enable)
 787                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
 788                                 b43_ofdmtab_write16(dev,
 789                                         B43_OFDMTAB_WRSSI, i, 0x0820);
 790                 else
 791                         for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
 792                                 b43_ofdmtab_write16(dev,
 793                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
 794         }
 795 }
 796
 797 static void b43_phy_ww(struct b43_wldev *dev)
 798 {
 799         u16 b, curr_s, best_s = 0xFFFF;
 800         int i;
 801
 802         b43_phy_write(dev, B43_PHY_CRS0,
 803                 b43_phy_read(dev, B43_PHY_CRS0) & ~B43_PHY_CRS0_EN);
 804         b43_phy_write(dev, B43_PHY_OFDM(0x1B),
 805                 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) | 0x1000);
 806         b43_phy_write(dev, B43_PHY_OFDM(0x82),
 807                 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & 0xF0FF) | 0x0300);
 808         b43_radio_write16(dev, 0x0009,
 809                 b43_radio_read16(dev, 0x0009) | 0x0080);
 810         b43_radio_write16(dev, 0x0012,
 811                 (b43_radio_read16(dev, 0x0012) & 0xFFFC) | 0x0002);
 812         b43_wa_initgains(dev);
 813         b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
 814         b = b43_phy_read(dev, B43_PHY_PWRDOWN);
 815         b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
 816         b43_radio_write16(dev, 0x0004,
 817                 b43_radio_read16(dev, 0x0004) | 0x0004);
 818         for (i = 0x10; i <= 0x20; i++) {
 819                 b43_radio_write16(dev, 0x0013, i);
 820                 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
 821                 if (!curr_s) {
 822                         best_s = 0x0000;
 823                         break;
 824                 } else if (curr_s >= 0x0080)
 825                         curr_s = 0x0100 - curr_s;
 826                 if (curr_s < best_s)
 827                         best_s = curr_s;
 828         }
 829         b43_phy_write(dev, B43_PHY_PWRDOWN, b);
 830         b43_radio_write16(dev, 0x0004,
 831                 b43_radio_read16(dev, 0x0004) & 0xFFFB);
 832         b43_radio_write16(dev, 0x0013, best_s);
 833         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
 834         b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
 835         b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
 836         b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
 837         b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
 838         b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
 839         b43_phy_write(dev, B43_PHY_OFDM(0xBB),
 840                 (b43_phy_read(dev, B43_PHY_OFDM(0xBB)) & 0xF000) | 0x0053);
 841         b43_phy_write(dev, B43_PHY_OFDM61,
 842                 (b43_phy_read(dev, B43_PHY_OFDM61 & 0xFE1F)) | 0x0120);
 843         b43_phy_write(dev, B43_PHY_OFDM(0x13),
 844                 (b43_phy_read(dev, B43_PHY_OFDM(0x13)) & 0x0FFF) | 0x3000);
 845         b43_phy_write(dev, B43_PHY_OFDM(0x14),
 846                 (b43_phy_read(dev, B43_PHY_OFDM(0x14)) & 0x0FFF) | 0x3000);
 847         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
 848         for (i = 0; i < 6; i++)
 849                 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
 850         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
 851         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
 852         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
 853         b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
 854         b43_phy_write(dev, B43_PHY_CRS0,
 855                 b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
 856 }
 857
 858 /* Initialize APHY. This is also called for the GPHY in some cases. */
 859 static void b43_phy_inita(struct b43_wldev *dev)
 860 {
 861         struct ssb_bus *bus = dev->dev->bus;
 862         struct b43_phy *phy = &dev->phy;
 863
 864         might_sleep();
 865
 866         if (phy->rev >= 6) {
 867                 if (phy->type == B43_PHYTYPE_A)
 868                         b43_phy_write(dev, B43_PHY_OFDM(0x1B),
 869                                 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x1000);
 870                 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
 871                         b43_phy_write(dev, B43_PHY_ENCORE,
 872                                 b43_phy_read(dev, B43_PHY_ENCORE) | 0x0010);
 873                 else
 874                         b43_phy_write(dev, B43_PHY_ENCORE,
 875                                 b43_phy_read(dev, B43_PHY_ENCORE) & ~0x1010);
 876         }
 877
 878         b43_wa_all(dev);
 879
 880         if (phy->type == B43_PHYTYPE_A) {
 881                 if (phy->gmode && (phy->rev < 3))
 882                         b43_phy_write(dev, 0x0034,
 883                                 b43_phy_read(dev, 0x0034) | 0x0001);
 884                 b43_phy_rssiagc(dev, 0);
 885
 886                 b43_phy_write(dev, B43_PHY_CRS0,
 887                         b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
 888
 889                 b43_radio_init2060(dev);
 890
 891                 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
 892                     ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
 893                      (bus->boardinfo.type == SSB_BOARD_BU4309))) {
 894                         ; //TODO: A PHY LO
 895                 }
 896
 897                 if (phy->rev >= 3)
 898                         b43_phy_ww(dev);
 899
 900                 hardware_pctl_init_aphy(dev);
 901
 902                 //TODO: radar detection
 903         }
 904
 905         if ((phy->type == B43_PHYTYPE_G) &&
 906             (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL)) {
 907                 b43_phy_write(dev, B43_PHY_OFDM(0x6E),
 908                                   (b43_phy_read(dev, B43_PHY_OFDM(0x6E))
 909                                    & 0xE000) | 0x3CF);
 910         }
 911 }
 912
 913 static void b43_phy_initb2(struct b43_wldev *dev)
 914 {
 915         struct b43_phy *phy = &dev->phy;
 916         u16 offset, val;
 917
 918         b43_write16(dev, 0x03EC, 0x3F22);
 919         b43_phy_write(dev, 0x0020, 0x301C);
 920         b43_phy_write(dev, 0x0026, 0x0000);
 921         b43_phy_write(dev, 0x0030, 0x00C6);
 922         b43_phy_write(dev, 0x0088, 0x3E00);
 923         val = 0x3C3D;
 924         for (offset = 0x0089; offset < 0x00A7; offset++) {
 925                 b43_phy_write(dev, offset, val);
 926                 val -= 0x0202;
 927         }
 928         b43_phy_write(dev, 0x03E4, 0x3000);
 929         b43_radio_selectchannel(dev, phy->channel, 0);
 930         if (phy->radio_ver != 0x2050) {
 931                 b43_radio_write16(dev, 0x0075, 0x0080);
 932                 b43_radio_write16(dev, 0x0079, 0x0081);
 933         }
 934         b43_radio_write16(dev, 0x0050, 0x0020);
 935         b43_radio_write16(dev, 0x0050, 0x0023);
 936         if (phy->radio_ver == 0x2050) {
 937                 b43_radio_write16(dev, 0x0050, 0x0020);
 938                 b43_radio_write16(dev, 0x005A, 0x0070);
 939                 b43_radio_write16(dev, 0x005B, 0x007B);
 940                 b43_radio_write16(dev, 0x005C, 0x00B0);
 941                 b43_radio_write16(dev, 0x007A, 0x000F);
 942                 b43_phy_write(dev, 0x0038, 0x0677);
 943                 b43_radio_init2050(dev);
 944         }
 945         b43_phy_write(dev, 0x0014, 0x0080);
 946         b43_phy_write(dev, 0x0032, 0x00CA);
 947         b43_phy_write(dev, 0x0032, 0x00CC);
 948         b43_phy_write(dev, 0x0035, 0x07C2);
 949         b43_lo_b_measure(dev);
 950         b43_phy_write(dev, 0x0026, 0xCC00);
 951         if (phy->radio_ver != 0x2050)
 952                 b43_phy_write(dev, 0x0026, 0xCE00);
 953         b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1000);
 954         b43_phy_write(dev, 0x002A, 0x88A3);
 955         if (phy->radio_ver != 0x2050)
 956                 b43_phy_write(dev, 0x002A, 0x88C2);
 957         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
 958         b43_phy_init_pctl(dev);
 959 }
 960
 961 static void b43_phy_initb4(struct b43_wldev *dev)
 962 {
 963         struct b43_phy *phy = &dev->phy;
 964         u16 offset, val;
 965
 966         b43_write16(dev, 0x03EC, 0x3F22);
 967         b43_phy_write(dev, 0x0020, 0x301C);
 968         b43_phy_write(dev, 0x0026, 0x0000);
 969         b43_phy_write(dev, 0x0030, 0x00C6);
 970         b43_phy_write(dev, 0x0088, 0x3E00);
 971         val = 0x3C3D;
 972         for (offset = 0x0089; offset < 0x00A7; offset++) {
 973                 b43_phy_write(dev, offset, val);
 974                 val -= 0x0202;
 975         }
 976         b43_phy_write(dev, 0x03E4, 0x3000);
 977         b43_radio_selectchannel(dev, phy->channel, 0);
 978         if (phy->radio_ver != 0x2050) {
 979                 b43_radio_write16(dev, 0x0075, 0x0080);
 980                 b43_radio_write16(dev, 0x0079, 0x0081);
 981         }
 982         b43_radio_write16(dev, 0x0050, 0x0020);
 983         b43_radio_write16(dev, 0x0050, 0x0023);
 984         if (phy->radio_ver == 0x2050) {
 985                 b43_radio_write16(dev, 0x0050, 0x0020);
 986                 b43_radio_write16(dev, 0x005A, 0x0070);
 987                 b43_radio_write16(dev, 0x005B, 0x007B);
 988                 b43_radio_write16(dev, 0x005C, 0x00B0);
 989                 b43_radio_write16(dev, 0x007A, 0x000F);
 990                 b43_phy_write(dev, 0x0038, 0x0677);
 991                 b43_radio_init2050(dev);
 992         }
 993         b43_phy_write(dev, 0x0014, 0x0080);
 994         b43_phy_write(dev, 0x0032, 0x00CA);
 995         if (phy->radio_ver == 0x2050)
 996                 b43_phy_write(dev, 0x0032, 0x00E0);
 997         b43_phy_write(dev, 0x0035, 0x07C2);
 998
 999         b43_lo_b_measure(dev);
1000
1001         b43_phy_write(dev, 0x0026, 0xCC00);
1002         if (phy->radio_ver == 0x2050)
1003                 b43_phy_write(dev, 0x0026, 0xCE00);
1004         b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1100);
1005         b43_phy_write(dev, 0x002A, 0x88A3);
1006         if (phy->radio_ver == 0x2050)
1007                 b43_phy_write(dev, 0x002A, 0x88C2);
1008         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1009         if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
1010                 b43_calc_nrssi_slope(dev);
1011                 b43_calc_nrssi_threshold(dev);
1012         }
1013         b43_phy_init_pctl(dev);
1014 }
1015
1016 static void b43_phy_initb5(struct b43_wldev *dev)
1017 {
1018         struct ssb_bus *bus = dev->dev->bus;
1019         struct b43_phy *phy = &dev->phy;
1020         u16 offset, value;
1021         u8 old_channel;
1022
1023         if (phy->analog == 1) {
1024                 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1025                                   | 0x0050);
1026         }
1027         if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1028             (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1029                 value = 0x2120;
1030                 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1031                         b43_phy_write(dev, offset, value);
1032                         value += 0x202;
1033                 }
1034         }
1035         b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
1036                       | 0x0700);
1037         if (phy->radio_ver == 0x2050)
1038                 b43_phy_write(dev, 0x0038, 0x0667);
1039
1040         if (phy->gmode || phy->rev >= 2) {
1041                 if (phy->radio_ver == 0x2050) {
1042                         b43_radio_write16(dev, 0x007A,
1043                                           b43_radio_read16(dev, 0x007A)
1044                                           | 0x0020);
1045                         b43_radio_write16(dev, 0x0051,
1046                                           b43_radio_read16(dev, 0x0051)
1047                                           | 0x0004);
1048                 }
1049                 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1050
1051                 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1052                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1053
1054                 b43_phy_write(dev, 0x001C, 0x186A);
1055
1056                 b43_phy_write(dev, 0x0013,
1057                               (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1058                 b43_phy_write(dev, 0x0035,
1059                               (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1060                 b43_phy_write(dev, 0x005D,
1061                               (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1062         }
1063
1064         if (dev->bad_frames_preempt) {
1065                 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1066                               b43_phy_read(dev,
1067                                            B43_PHY_RADIO_BITFIELD) | (1 << 11));
1068         }
1069
1070         if (phy->analog == 1) {
1071                 b43_phy_write(dev, 0x0026, 0xCE00);
1072                 b43_phy_write(dev, 0x0021, 0x3763);
1073                 b43_phy_write(dev, 0x0022, 0x1BC3);
1074                 b43_phy_write(dev, 0x0023, 0x06F9);
1075                 b43_phy_write(dev, 0x0024, 0x037E);
1076         } else
1077                 b43_phy_write(dev, 0x0026, 0xCC00);
1078         b43_phy_write(dev, 0x0030, 0x00C6);
1079         b43_write16(dev, 0x03EC, 0x3F22);
1080
1081         if (phy->analog == 1)
1082                 b43_phy_write(dev, 0x0020, 0x3E1C);
1083         else
1084                 b43_phy_write(dev, 0x0020, 0x301C);
1085
1086         if (phy->analog == 0)
1087                 b43_write16(dev, 0x03E4, 0x3000);
1088
1089         old_channel = phy->channel;
1090         /* Force to channel 7, even if not supported. */
1091         b43_radio_selectchannel(dev, 7, 0);
1092
1093         if (phy->radio_ver != 0x2050) {
1094                 b43_radio_write16(dev, 0x0075, 0x0080);
1095                 b43_radio_write16(dev, 0x0079, 0x0081);
1096         }
1097
1098         b43_radio_write16(dev, 0x0050, 0x0020);
1099         b43_radio_write16(dev, 0x0050, 0x0023);
1100
1101         if (phy->radio_ver == 0x2050) {
1102                 b43_radio_write16(dev, 0x0050, 0x0020);
1103                 b43_radio_write16(dev, 0x005A, 0x0070);
1104         }
1105
1106         b43_radio_write16(dev, 0x005B, 0x007B);
1107         b43_radio_write16(dev, 0x005C, 0x00B0);
1108
1109         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1110
1111         b43_radio_selectchannel(dev, old_channel, 0);
1112
1113         b43_phy_write(dev, 0x0014, 0x0080);
1114         b43_phy_write(dev, 0x0032, 0x00CA);
1115         b43_phy_write(dev, 0x002A, 0x88A3);
1116
1117         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1118
1119         if (phy->radio_ver == 0x2050)
1120                 b43_radio_write16(dev, 0x005D, 0x000D);
1121
1122         b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1123 }
1124
1125 static void b43_phy_initb6(struct b43_wldev *dev)
1126 {
1127         struct b43_phy *phy = &dev->phy;
1128         u16 offset, val;
1129         u8 old_channel;
1130
1131         b43_phy_write(dev, 0x003E, 0x817A);
1132         b43_radio_write16(dev, 0x007A,
1133                           (b43_radio_read16(dev, 0x007A) | 0x0058));
1134         if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1135                 b43_radio_write16(dev, 0x51, 0x37);
1136                 b43_radio_write16(dev, 0x52, 0x70);
1137                 b43_radio_write16(dev, 0x53, 0xB3);
1138                 b43_radio_write16(dev, 0x54, 0x9B);
1139                 b43_radio_write16(dev, 0x5A, 0x88);
1140                 b43_radio_write16(dev, 0x5B, 0x88);
1141                 b43_radio_write16(dev, 0x5D, 0x88);
1142                 b43_radio_write16(dev, 0x5E, 0x88);
1143                 b43_radio_write16(dev, 0x7D, 0x88);
1144                 b43_hf_write(dev, b43_hf_read(dev)
1145                              | B43_HF_TSSIRPSMW);
1146         }
1147         B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7);        /* We had code for these revs here... */
1148         if (phy->radio_rev == 8) {
1149                 b43_radio_write16(dev, 0x51, 0);
1150                 b43_radio_write16(dev, 0x52, 0x40);
1151                 b43_radio_write16(dev, 0x53, 0xB7);
1152                 b43_radio_write16(dev, 0x54, 0x98);
1153                 b43_radio_write16(dev, 0x5A, 0x88);
1154                 b43_radio_write16(dev, 0x5B, 0x6B);
1155                 b43_radio_write16(dev, 0x5C, 0x0F);
1156                 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_ALTIQ) {
1157                         b43_radio_write16(dev, 0x5D, 0xFA);
1158                         b43_radio_write16(dev, 0x5E, 0xD8);
1159                 } else {
1160                         b43_radio_write16(dev, 0x5D, 0xF5);
1161                         b43_radio_write16(dev, 0x5E, 0xB8);
1162                 }
1163                 b43_radio_write16(dev, 0x0073, 0x0003);
1164                 b43_radio_write16(dev, 0x007D, 0x00A8);
1165                 b43_radio_write16(dev, 0x007C, 0x0001);
1166                 b43_radio_write16(dev, 0x007E, 0x0008);
1167         }
1168         val = 0x1E1F;
1169         for (offset = 0x0088; offset < 0x0098; offset++) {
1170                 b43_phy_write(dev, offset, val);
1171                 val -= 0x0202;
1172         }
1173         val = 0x3E3F;
1174         for (offset = 0x0098; offset < 0x00A8; offset++) {
1175                 b43_phy_write(dev, offset, val);
1176                 val -= 0x0202;
1177         }
1178         val = 0x2120;
1179         for (offset = 0x00A8; offset < 0x00C8; offset++) {
1180                 b43_phy_write(dev, offset, (val & 0x3F3F));
1181                 val += 0x0202;
1182         }
1183         if (phy->type == B43_PHYTYPE_G) {
1184                 b43_radio_write16(dev, 0x007A,
1185                                   b43_radio_read16(dev, 0x007A) | 0x0020);
1186                 b43_radio_write16(dev, 0x0051,
1187                                   b43_radio_read16(dev, 0x0051) | 0x0004);
1188                 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1189                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1190                 b43_phy_write(dev, 0x5B, 0);
1191                 b43_phy_write(dev, 0x5C, 0);
1192         }
1193
1194         old_channel = phy->channel;
1195         if (old_channel >= 8)
1196                 b43_radio_selectchannel(dev, 1, 0);
1197         else
1198                 b43_radio_selectchannel(dev, 13, 0);
1199
1200         b43_radio_write16(dev, 0x0050, 0x0020);
1201         b43_radio_write16(dev, 0x0050, 0x0023);
1202         udelay(40);
1203         if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1204                 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1205                                               | 0x0002));
1206                 b43_radio_write16(dev, 0x50, 0x20);
1207         }
1208         if (phy->radio_rev <= 2) {
1209                 b43_radio_write16(dev, 0x7C, 0x20);
1210                 b43_radio_write16(dev, 0x5A, 0x70);
1211                 b43_radio_write16(dev, 0x5B, 0x7B);
1212                 b43_radio_write16(dev, 0x5C, 0xB0);
1213         }
1214         b43_radio_write16(dev, 0x007A,
1215                           (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1216
1217         b43_radio_selectchannel(dev, old_channel, 0);
1218
1219         b43_phy_write(dev, 0x0014, 0x0200);
1220         if (phy->radio_rev >= 6)
1221                 b43_phy_write(dev, 0x2A, 0x88C2);
1222         else
1223                 b43_phy_write(dev, 0x2A, 0x8AC0);
1224         b43_phy_write(dev, 0x0038, 0x0668);
1225         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1226         if (phy->radio_rev <= 5) {
1227                 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1228                                           & 0xFF80) | 0x0003);
1229         }
1230         if (phy->radio_rev <= 2)
1231                 b43_radio_write16(dev, 0x005D, 0x000D);
1232
1233         if (phy->analog == 4) {
1234                 b43_write16(dev, 0x3E4, 9);
1235                 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
1236                               & 0x0FFF);
1237         } else {
1238                 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1239                               | 0x0004);
1240         }
1241         if (phy->type == B43_PHYTYPE_B) {
1242                 b43_write16(dev, 0x03E6, 0x8140);
1243                 b43_phy_write(dev, 0x0016, 0x0410);
1244                 b43_phy_write(dev, 0x0017, 0x0820);
1245                 b43_phy_write(dev, 0x0062, 0x0007);
1246                 b43_radio_init2050(dev);
1247                 b43_lo_g_measure(dev);
1248                 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
1249                         b43_calc_nrssi_slope(dev);
1250                         b43_calc_nrssi_threshold(dev);
1251                 }
1252                 b43_phy_init_pctl(dev);
1253         } else if (phy->type == B43_PHYTYPE_G)
1254                 b43_write16(dev, 0x03E6, 0x0);
1255 }
1256
1257 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1258 {
1259         struct b43_phy *phy = &dev->phy;
1260         u16 backup_phy[16] = { 0 };
1261         u16 backup_radio[3];
1262         u16 backup_bband;
1263         u16 i, j, loop_i_max;
1264         u16 trsw_rx;
1265         u16 loop1_outer_done, loop1_inner_done;
1266
1267         backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1268         backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1269         backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1270         backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1271         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1272                 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1273                 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1274         }
1275         backup_phy[6] = b43_phy_read(dev, B43_PHY_BASE(0x5A));
1276         backup_phy[7] = b43_phy_read(dev, B43_PHY_BASE(0x59));
1277         backup_phy[8] = b43_phy_read(dev, B43_PHY_BASE(0x58));
1278         backup_phy[9] = b43_phy_read(dev, B43_PHY_BASE(0x0A));
1279         backup_phy[10] = b43_phy_read(dev, B43_PHY_BASE(0x03));
1280         backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1281         backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1282         backup_phy[13] = b43_phy_read(dev, B43_PHY_BASE(0x2B));
1283         backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1284         backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1285         backup_bband = phy->bbatt.att;
1286         backup_radio[0] = b43_radio_read16(dev, 0x52);
1287         backup_radio[1] = b43_radio_read16(dev, 0x43);
1288         backup_radio[2] = b43_radio_read16(dev, 0x7A);
1289
1290         b43_phy_write(dev, B43_PHY_CRS0,
1291                       b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1292         b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
1293                       b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
1294         b43_phy_write(dev, B43_PHY_RFOVER,
1295                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
1296         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1297                       b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1298         b43_phy_write(dev, B43_PHY_RFOVER,
1299                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
1300         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1301                       b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1302         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1303                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1304                               b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
1305                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1306                               b43_phy_read(dev,
1307                                            B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1308                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1309                               b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
1310                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1311                               b43_phy_read(dev,
1312                                            B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1313         }
1314         b43_phy_write(dev, B43_PHY_RFOVER,
1315                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
1316         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1317                       b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
1318         b43_phy_write(dev, B43_PHY_RFOVER,
1319                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
1320         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1321                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1322                        & 0xFFCF) | 0x10);
1323
1324         b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0780);
1325         b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
1326         b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
1327
1328         b43_phy_write(dev, B43_PHY_BASE(0x0A),
1329                       b43_phy_read(dev, B43_PHY_BASE(0x0A)) | 0x2000);
1330         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1331                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1332                               b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
1333                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1334                               b43_phy_read(dev,
1335                                            B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1336         }
1337         b43_phy_write(dev, B43_PHY_BASE(0x03),
1338                       (b43_phy_read(dev, B43_PHY_BASE(0x03))
1339                        & 0xFF9F) | 0x40);
1340
1341         if (phy->radio_rev == 8) {
1342                 b43_radio_write16(dev, 0x43, 0x000F);
1343         } else {
1344                 b43_radio_write16(dev, 0x52, 0);
1345                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1346                                               & 0xFFF0) | 0x9);
1347         }
1348         b43_phy_set_baseband_attenuation(dev, 11);
1349
1350         if (phy->rev >= 3)
1351                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1352         else
1353                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1354         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1355
1356         b43_phy_write(dev, B43_PHY_BASE(0x2B),
1357                       (b43_phy_read(dev, B43_PHY_BASE(0x2B))
1358                        & 0xFFC0) | 0x01);
1359         b43_phy_write(dev, B43_PHY_BASE(0x2B),
1360                       (b43_phy_read(dev, B43_PHY_BASE(0x2B))
1361                        & 0xC0FF) | 0x800);
1362
1363         b43_phy_write(dev, B43_PHY_RFOVER,
1364                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
1365         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1366                       b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1367
1368         if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_EXTLNA) {
1369                 if (phy->rev >= 7) {
1370                         b43_phy_write(dev, B43_PHY_RFOVER,
1371                                       b43_phy_read(dev, B43_PHY_RFOVER)
1372                                       | 0x0800);
1373                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1374                                       b43_phy_read(dev, B43_PHY_RFOVERVAL)
1375                                       | 0x8000);
1376                 }
1377         }
1378         b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1379                           & 0x00F7);
1380
1381         j = 0;
1382         loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1383         for (i = 0; i < loop_i_max; i++) {
1384                 for (j = 0; j < 16; j++) {
1385                         b43_radio_write16(dev, 0x43, i);
1386                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1387                                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1388                                        & 0xF0FF) | (j << 8));
1389                         b43_phy_write(dev, B43_PHY_PGACTL,
1390                                       (b43_phy_read(dev, B43_PHY_PGACTL)
1391                                        & 0x0FFF) | 0xA000);
1392                         b43_phy_write(dev, B43_PHY_PGACTL,
1393                                       b43_phy_read(dev, B43_PHY_PGACTL)
1394                                       | 0xF000);
1395                         udelay(20);
1396                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1397                                 goto exit_loop1;
1398                 }
1399         }
1400       exit_loop1:
1401         loop1_outer_done = i;
1402         loop1_inner_done = j;
1403         if (j >= 8) {
1404                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1405                               b43_phy_read(dev, B43_PHY_RFOVERVAL)
1406                               | 0x30);
1407                 trsw_rx = 0x1B;
1408                 for (j = j - 8; j < 16; j++) {
1409                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1410                                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1411                                        & 0xF0FF) | (j << 8));
1412                         b43_phy_write(dev, B43_PHY_PGACTL,
1413                                       (b43_phy_read(dev, B43_PHY_PGACTL)
1414                                        & 0x0FFF) | 0xA000);
1415                         b43_phy_write(dev, B43_PHY_PGACTL,
1416                                       b43_phy_read(dev, B43_PHY_PGACTL)
1417                                       | 0xF000);
1418                         udelay(20);
1419                         trsw_rx -= 3;
1420                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1421                                 goto exit_loop2;
1422                 }
1423         } else
1424                 trsw_rx = 0x18;
1425       exit_loop2:
1426
1427         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1428                 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1429                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1430         }
1431         b43_phy_write(dev, B43_PHY_BASE(0x5A), backup_phy[6]);
1432         b43_phy_write(dev, B43_PHY_BASE(0x59), backup_phy[7]);
1433         b43_phy_write(dev, B43_PHY_BASE(0x58), backup_phy[8]);
1434         b43_phy_write(dev, B43_PHY_BASE(0x0A), backup_phy[9]);
1435         b43_phy_write(dev, B43_PHY_BASE(0x03), backup_phy[10]);
1436         b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1437         b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1438         b43_phy_write(dev, B43_PHY_BASE(0x2B), backup_phy[13]);
1439         b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1440
1441         b43_phy_set_baseband_attenuation(dev, backup_bband);
1442
1443         b43_radio_write16(dev, 0x52, backup_radio[0]);
1444         b43_radio_write16(dev, 0x43, backup_radio[1]);
1445         b43_radio_write16(dev, 0x7A, backup_radio[2]);
1446
1447         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1448         udelay(10);
1449         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1450         b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1451         b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1452         b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1453
1454         phy->max_lb_gain =
1455             ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1456         phy->trsw_rx_gain = trsw_rx * 2;
1457 }
1458
1459 static void b43_phy_initg(struct b43_wldev *dev)
1460 {
1461         struct b43_phy *phy = &dev->phy;
1462         u16 tmp;
1463
1464         if (phy->rev == 1)
1465                 b43_phy_initb5(dev);
1466         else
1467                 b43_phy_initb6(dev);
1468
1469         if (phy->rev >= 2 || phy->gmode)
1470                 b43_phy_inita(dev);
1471
1472         if (phy->rev >= 2) {
1473                 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
1474                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
1475         }
1476         if (phy->rev == 2) {
1477                 b43_phy_write(dev, B43_PHY_RFOVER, 0);
1478                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1479         }
1480         if (phy->rev > 5) {
1481                 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
1482                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1483         }
1484         if (phy->gmode || phy->rev >= 2) {
1485                 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
1486                 tmp &= B43_PHYVER_VERSION;
1487                 if (tmp == 3 || tmp == 5) {
1488                         b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
1489                         b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
1490                 }
1491                 if (tmp == 5) {
1492                         b43_phy_write(dev, B43_PHY_OFDM(0xCC),
1493                                       (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
1494                                        & 0x00FF) | 0x1F00);
1495                 }
1496         }
1497         if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
1498                 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
1499         if (phy->radio_rev == 8) {
1500                 b43_phy_write(dev, B43_PHY_EXTG(0x01),
1501                               b43_phy_read(dev, B43_PHY_EXTG(0x01))
1502                               | 0x80);
1503                 b43_phy_write(dev, B43_PHY_OFDM(0x3E),
1504                               b43_phy_read(dev, B43_PHY_OFDM(0x3E))
1505                               | 0x4);
1506         }
1507         if (has_loopback_gain(phy))
1508                 b43_calc_loopback_gain(dev);
1509
1510         if (phy->radio_rev != 8) {
1511                 if (phy->initval == 0xFFFF)
1512                         phy->initval = b43_radio_init2050(dev);
1513                 else
1514                         b43_radio_write16(dev, 0x0078, phy->initval);
1515         }
1516         if (phy->lo_control->tx_bias == 0xFF) {
1517                 b43_lo_g_measure(dev);
1518         } else {
1519                 if (has_tx_magnification(phy)) {
1520                         b43_radio_write16(dev, 0x52,
1521                                           (b43_radio_read16(dev, 0x52) & 0xFF00)
1522                                           | phy->lo_control->tx_bias | phy->
1523                                           lo_control->tx_magn);
1524                 } else {
1525                         b43_radio_write16(dev, 0x52,
1526                                           (b43_radio_read16(dev, 0x52) & 0xFFF0)
1527                                           | phy->lo_control->tx_bias);
1528                 }
1529                 if (phy->rev >= 6) {
1530                         b43_phy_write(dev, B43_PHY_BASE(0x36),
1531                                       (b43_phy_read(dev, B43_PHY_BASE(0x36))
1532                                        & 0x0FFF) | (phy->lo_control->
1533                                                     tx_bias << 12));
1534                 }
1535                 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL)
1536                         b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8075);
1537                 else
1538                         b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x807F);
1539                 if (phy->rev < 2)
1540                         b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x101);
1541                 else
1542                         b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x202);
1543         }
1544         if (phy->gmode || phy->rev >= 2) {
1545                 b43_lo_g_adjust(dev);
1546                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
1547         }
1548
1549         if (!(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
1550                 /* The specs state to update the NRSSI LT with
1551                  * the value 0x7FFFFFFF here. I think that is some weird
1552                  * compiler optimization in the original driver.
1553                  * Essentially, what we do here is resetting all NRSSI LT
1554                  * entries to -32 (see the limit_value() in nrssi_hw_update())
1555                  */
1556                 b43_nrssi_hw_update(dev, 0xFFFF);       //FIXME?
1557                 b43_calc_nrssi_threshold(dev);
1558         } else if (phy->gmode || phy->rev >= 2) {
1559                 if (phy->nrssi[0] == -1000) {
1560                         B43_WARN_ON(phy->nrssi[1] != -1000);
1561                         b43_calc_nrssi_slope(dev);
1562                 } else
1563                         b43_calc_nrssi_threshold(dev);
1564         }
1565         if (phy->radio_rev == 8)
1566                 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
1567         b43_phy_init_pctl(dev);
1568         /* FIXME: The spec says in the following if, the 0 should be replaced
1569            'if OFDM may not be used in the current locale'
1570            but OFDM is legal everywhere */
1571         if ((dev->dev->bus->chip_id == 0x4306
1572              && dev->dev->bus->chip_package == 2) || 0) {
1573                 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1574                               & 0xBFFF);
1575                 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
1576                               b43_phy_read(dev, B43_PHY_OFDM(0xC3))
1577                               & 0x7FFF);
1578         }
1579 }
1580
1581 /* Set the baseband attenuation value on chip. */
1582 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
1583                                       u16 baseband_attenuation)
1584 {
1585         struct b43_phy *phy = &dev->phy;
1586
1587         if (phy->analog == 0) {
1588                 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
1589                                                  & 0xFFF0) |
1590                             baseband_attenuation);
1591         } else if (phy->analog > 1) {
1592                 b43_phy_write(dev, B43_PHY_DACCTL,
1593                               (b43_phy_read(dev, B43_PHY_DACCTL)
1594                                & 0xFFC3) | (baseband_attenuation << 2));
1595         } else {
1596                 b43_phy_write(dev, B43_PHY_DACCTL,
1597                               (b43_phy_read(dev, B43_PHY_DACCTL)
1598                                & 0xFF87) | (baseband_attenuation << 3));
1599         }
1600 }
1601
1602 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1603  * This function converts a TSSI value to dBm in Q5.2
1604  */
1605 static s8 b43_phy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
1606 {
1607         struct b43_phy *phy = &dev->phy;
1608         s8 dbm = 0;
1609         s32 tmp;
1610
1611         tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
1612
1613         switch (phy->type) {
1614         case B43_PHYTYPE_A:
1615                 tmp += 0x80;
1616                 tmp = limit_value(tmp, 0x00, 0xFF);
1617                 dbm = phy->tssi2dbm[tmp];
1618                 //TODO: There's a FIXME on the specs
1619                 break;
1620         case B43_PHYTYPE_B:
1621         case B43_PHYTYPE_G:
1622                 tmp = limit_value(tmp, 0x00, 0x3F);
1623                 dbm = phy->tssi2dbm[tmp];
1624                 break;
1625         default:
1626                 B43_WARN_ON(1);
1627         }
1628
1629         return dbm;
1630 }
1631
1632 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
1633                                      int *_bbatt, int *_rfatt)
1634 {
1635         int rfatt = *_rfatt;
1636         int bbatt = *_bbatt;
1637         struct b43_txpower_lo_control *lo = dev->phy.lo_control;
1638
1639         /* Get baseband and radio attenuation values into their permitted ranges.
1640          * Radio attenuation affects power level 4 times as much as baseband. */
1641
1642         /* Range constants */
1643         const int rf_min = lo->rfatt_list.min_val;
1644         const int rf_max = lo->rfatt_list.max_val;
1645         const int bb_min = lo->bbatt_list.min_val;
1646         const int bb_max = lo->bbatt_list.max_val;
1647
1648         while (1) {
1649                 if (rfatt > rf_max && bbatt > bb_max - 4)
1650                         break;  /* Can not get it into ranges */
1651                 if (rfatt < rf_min && bbatt < bb_min + 4)
1652                         break;  /* Can not get it into ranges */
1653                 if (bbatt > bb_max && rfatt > rf_max - 1)
1654                         break;  /* Can not get it into ranges */
1655                 if (bbatt < bb_min && rfatt < rf_min + 1)
1656                         break;  /* Can not get it into ranges */
1657
1658                 if (bbatt > bb_max) {
1659                         bbatt -= 4;
1660                         rfatt += 1;
1661                         continue;
1662                 }
1663                 if (bbatt < bb_min) {
1664                         bbatt += 4;
1665                         rfatt -= 1;
1666                         continue;
1667                 }
1668                 if (rfatt > rf_max) {
1669                         rfatt -= 1;
1670                         bbatt += 4;
1671                         continue;
1672                 }
1673                 if (rfatt < rf_min) {
1674                         rfatt += 1;
1675                         bbatt -= 4;
1676                         continue;
1677                 }
1678                 break;
1679         }
1680
1681         *_rfatt = limit_value(rfatt, rf_min, rf_max);
1682         *_bbatt = limit_value(bbatt, bb_min, bb_max);
1683 }
1684
1685 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1686 void b43_phy_xmitpower(struct b43_wldev *dev)
1687 {
1688         struct ssb_bus *bus = dev->dev->bus;
1689         struct b43_phy *phy = &dev->phy;
1690
1691         if (phy->cur_idle_tssi == 0)
1692                 return;
1693         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1694             (bus->boardinfo.type == SSB_BOARD_BU4306))
1695                 return;
1696 #ifdef CONFIG_B43_DEBUG
1697         if (phy->manual_txpower_control)
1698                 return;
1699 #endif
1700
1701         switch (phy->type) {
1702         case B43_PHYTYPE_A:{
1703
1704                         //TODO: Nothing for A PHYs yet :-/
1705
1706                         break;
1707                 }
1708         case B43_PHYTYPE_B:
1709         case B43_PHYTYPE_G:{
1710                         u16 tmp;
1711                         s8 v0, v1, v2, v3;
1712                         s8 average;
1713                         int max_pwr;
1714                         int desired_pwr, estimated_pwr, pwr_adjust;
1715                         int rfatt_delta, bbatt_delta;
1716                         int rfatt, bbatt;
1717                         u8 tx_control;
1718                         unsigned long phylock_flags;
1719
1720                         tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
1721                         v0 = (s8) (tmp & 0x00FF);
1722                         v1 = (s8) ((tmp & 0xFF00) >> 8);
1723                         tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
1724                         v2 = (s8) (tmp & 0x00FF);
1725                         v3 = (s8) ((tmp & 0xFF00) >> 8);
1726                         tmp = 0;
1727
1728                         if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
1729                             || v3 == 0x7F) {
1730                                 tmp =
1731                                     b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
1732                                 v0 = (s8) (tmp & 0x00FF);
1733                                 v1 = (s8) ((tmp & 0xFF00) >> 8);
1734                                 tmp =
1735                                     b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
1736                                 v2 = (s8) (tmp & 0x00FF);
1737                                 v3 = (s8) ((tmp & 0xFF00) >> 8);
1738                                 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
1739                                     || v3 == 0x7F)
1740                                         return;
1741                                 v0 = (v0 + 0x20) & 0x3F;
1742                                 v1 = (v1 + 0x20) & 0x3F;
1743                                 v2 = (v2 + 0x20) & 0x3F;
1744                                 v3 = (v3 + 0x20) & 0x3F;
1745                                 tmp = 1;
1746                         }
1747                         b43_shm_clear_tssi(dev);
1748
1749                         average = (v0 + v1 + v2 + v3 + 2) / 4;
1750
1751                         if (tmp
1752                             && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) &
1753                                 0x8))
1754                                 average -= 13;
1755
1756                         estimated_pwr =
1757                             b43_phy_estimate_power_out(dev, average);
1758
1759                         max_pwr = dev->dev->bus->sprom.r1.maxpwr_bg;
1760                         if ((dev->dev->bus->sprom.r1.
1761                              boardflags_lo & B43_BFL_PACTRL)
1762                             && (phy->type == B43_PHYTYPE_G))
1763                                 max_pwr -= 0x3;
1764                         if (unlikely(max_pwr <= 0)) {
1765                                 b43warn(dev->wl,
1766                                         "Invalid max-TX-power value in SPROM.\n");
1767                                 max_pwr = 60;   /* fake it */
1768                                 dev->dev->bus->sprom.r1.maxpwr_bg = max_pwr;
1769                         }
1770
1771                         /*TODO:
1772                            max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
1773                            where REG is the max power as per the regulatory domain
1774                          */
1775
1776                         /* Get desired power (in Q5.2) */
1777                         desired_pwr = INT_TO_Q52(phy->power_level);
1778                         /* And limit it. max_pwr already is Q5.2 */
1779                         desired_pwr = limit_value(desired_pwr, 0, max_pwr);
1780                         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
1781                                 b43dbg(dev->wl,
1782                                        "Current TX power output: " Q52_FMT
1783                                        " dBm, " "Desired TX power output: "
1784                                        Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
1785                                        Q52_ARG(desired_pwr));
1786                         }
1787
1788                         /* Calculate the adjustment delta. */
1789                         pwr_adjust = desired_pwr - estimated_pwr;
1790
1791                         /* RF attenuation delta. */
1792                         rfatt_delta = ((pwr_adjust + 7) / 8);
1793                         /* Lower attenuation => Bigger power output. Negate it. */
1794                         rfatt_delta = -rfatt_delta;
1795
1796                         /* Baseband attenuation delta. */
1797                         bbatt_delta = pwr_adjust / 2;
1798                         /* Lower attenuation => Bigger power output. Negate it. */
1799                         bbatt_delta = -bbatt_delta;
1800                         /* RF att affects power level 4 times as much as
1801                          * Baseband attennuation. Subtract it. */
1802                         bbatt_delta -= 4 * rfatt_delta;
1803
1804                         /* So do we finally need to adjust something? */
1805                         if ((rfatt_delta == 0) && (bbatt_delta == 0)) {
1806                                 b43_lo_g_ctl_mark_cur_used(dev);
1807                                 return;
1808                         }
1809
1810                         /* Calculate the new attenuation values. */
1811                         bbatt = phy->bbatt.att;
1812                         bbatt += bbatt_delta;
1813                         rfatt = phy->rfatt.att;
1814                         rfatt += rfatt_delta;
1815
1816                         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
1817                         tx_control = phy->tx_control;
1818                         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
1819                                 if (rfatt <= 1) {
1820                                         if (tx_control == 0) {
1821                                                 tx_control =
1822                                                     B43_TXCTL_PA2DB |
1823                                                     B43_TXCTL_TXMIX;
1824                                                 rfatt += 2;
1825                                                 bbatt += 2;
1826                                         } else if (dev->dev->bus->sprom.r1.
1827                                                    boardflags_lo &
1828                                                    B43_BFL_PACTRL) {
1829                                                 bbatt += 4 * (rfatt - 2);
1830                                                 rfatt = 2;
1831                                         }
1832                                 } else if (rfatt > 4 && tx_control) {
1833                                         tx_control = 0;
1834                                         if (bbatt < 3) {
1835                                                 rfatt -= 3;
1836                                                 bbatt += 2;
1837                                         } else {
1838                                                 rfatt -= 2;
1839                                                 bbatt -= 2;
1840                                         }
1841                                 }
1842                         }
1843                         /* Save the control values */
1844                         phy->tx_control = tx_control;
1845                         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
1846                         phy->rfatt.att = rfatt;
1847                         phy->bbatt.att = bbatt;
1848
1849                         /* Adjust the hardware */
1850                         b43_phy_lock(dev, phylock_flags);
1851                         b43_radio_lock(dev);
1852                         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
1853                                           phy->tx_control);
1854                         b43_lo_g_ctl_mark_cur_used(dev);
1855                         b43_radio_unlock(dev);
1856                         b43_phy_unlock(dev, phylock_flags);
1857                         break;
1858                 }
1859         default:
1860                 B43_WARN_ON(1);
1861         }
1862 }
1863
1864 static inline s32 b43_tssi2dbm_ad(s32 num, s32 den)
1865 {
1866         if (num < 0)
1867                 return num / den;
1868         else
1869                 return (num + den / 2) / den;
1870 }
1871
1872 static inline
1873     s8 b43_tssi2dbm_entry(s8 entry[], u8 index, s16 pab0, s16 pab1, s16 pab2)
1874 {
1875         s32 m1, m2, f = 256, q, delta;
1876         s8 i = 0;
1877
1878         m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
1879         m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
1880         do {
1881                 if (i > 15)
1882                         return -EINVAL;
1883                 q = b43_tssi2dbm_ad(f * 4096 -
1884                                     b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
1885                 delta = abs(q - f);
1886                 f = q;
1887                 i++;
1888         } while (delta >= 2);
1889         entry[index] = limit_value(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
1890         return 0;
1891 }
1892
1893 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
1894 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
1895 {
1896         struct b43_phy *phy = &dev->phy;
1897         s16 pab0, pab1, pab2;
1898         u8 idx;
1899         s8 *dyn_tssi2dbm;
1900
1901         if (phy->type == B43_PHYTYPE_A) {
1902                 pab0 = (s16) (dev->dev->bus->sprom.r1.pa1b0);
1903                 pab1 = (s16) (dev->dev->bus->sprom.r1.pa1b1);
1904                 pab2 = (s16) (dev->dev->bus->sprom.r1.pa1b2);
1905         } else {
1906                 pab0 = (s16) (dev->dev->bus->sprom.r1.pa0b0);
1907                 pab1 = (s16) (dev->dev->bus->sprom.r1.pa0b1);
1908                 pab2 = (s16) (dev->dev->bus->sprom.r1.pa0b2);
1909         }
1910
1911         if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
1912                 phy->tgt_idle_tssi = 0x34;
1913                 phy->tssi2dbm = b43_tssi2dbm_b_table;
1914                 return 0;
1915         }
1916
1917         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
1918             pab0 != -1 && pab1 != -1 && pab2 != -1) {
1919                 /* The pabX values are set in SPROM. Use them. */
1920                 if (phy->type == B43_PHYTYPE_A) {
1921                         if ((s8) dev->dev->bus->sprom.r1.itssi_a != 0 &&
1922                             (s8) dev->dev->bus->sprom.r1.itssi_a != -1)
1923                                 phy->tgt_idle_tssi =
1924                                     (s8) (dev->dev->bus->sprom.r1.itssi_a);
1925                         else
1926                                 phy->tgt_idle_tssi = 62;
1927                 } else {
1928                         if ((s8) dev->dev->bus->sprom.r1.itssi_bg != 0 &&
1929                             (s8) dev->dev->bus->sprom.r1.itssi_bg != -1)
1930                                 phy->tgt_idle_tssi =
1931                                     (s8) (dev->dev->bus->sprom.r1.itssi_bg);
1932                         else
1933                                 phy->tgt_idle_tssi = 62;
1934                 }
1935                 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
1936                 if (dyn_tssi2dbm == NULL) {
1937                         b43err(dev->wl, "Could not allocate memory "
1938                                "for tssi2dbm table\n");
1939                         return -ENOMEM;
1940                 }
1941                 for (idx = 0; idx < 64; idx++)
1942                         if (b43_tssi2dbm_entry
1943                             (dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
1944                                 phy->tssi2dbm = NULL;
1945                                 b43err(dev->wl, "Could not generate "
1946                                        "tssi2dBm table\n");
1947                                 kfree(dyn_tssi2dbm);
1948                                 return -ENODEV;
1949                         }
1950                 phy->tssi2dbm = dyn_tssi2dbm;
1951                 phy->dyn_tssi_tbl = 1;
1952         } else {
1953                 /* pabX values not set in SPROM. */
1954                 switch (phy->type) {
1955                 case B43_PHYTYPE_A:
1956                         /* APHY needs a generated table. */
1957                         phy->tssi2dbm = NULL;
1958                         b43err(dev->wl, "Could not generate tssi2dBm "
1959                                "table (wrong SPROM info)!\n");
1960                         return -ENODEV;
1961                 case B43_PHYTYPE_B:
1962                         phy->tgt_idle_tssi = 0x34;
1963                         phy->tssi2dbm = b43_tssi2dbm_b_table;
1964                         break;
1965                 case B43_PHYTYPE_G:
1966                         phy->tgt_idle_tssi = 0x34;
1967                         phy->tssi2dbm = b43_tssi2dbm_g_table;
1968                         break;
1969                 }
1970         }
1971
1972         return 0;
1973 }
1974
1975 int b43_phy_init(struct b43_wldev *dev)
1976 {
1977         struct b43_phy *phy = &dev->phy;
1978         int err = -ENODEV;
1979
1980         switch (phy->type) {
1981         case B43_PHYTYPE_A:
1982                 if (phy->rev == 2 || phy->rev == 3) {
1983                         b43_phy_inita(dev);
1984                         err = 0;
1985                 }
1986                 break;
1987         case B43_PHYTYPE_B:
1988                 switch (phy->rev) {
1989                 case 2:
1990                         b43_phy_initb2(dev);
1991                         err = 0;
1992                         break;
1993                 case 4:
1994                         b43_phy_initb4(dev);
1995                         err = 0;
1996                         break;
1997                 case 5:
1998                         b43_phy_initb5(dev);
1999                         err = 0;
2000                         break;
2001                 case 6:
2002                         b43_phy_initb6(dev);
2003                         err = 0;
2004                         break;
2005                 }
2006                 break;
2007         case B43_PHYTYPE_G:
2008                 b43_phy_initg(dev);
2009                 err = 0;
2010                 break;
2011         }
2012         if (err)
2013                 b43err(dev->wl, "Unknown PHYTYPE found\n");
2014
2015         return err;
2016 }
2017
2018 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
2019 {
2020         struct b43_phy *phy = &dev->phy;
2021         u32 hf;
2022         u16 tmp;
2023         int autodiv = 0;
2024
2025         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2026                 autodiv = 1;
2027
2028         hf = b43_hf_read(dev);
2029         hf &= ~B43_HF_ANTDIVHELP;
2030         b43_hf_write(dev, hf);
2031
2032         switch (phy->type) {
2033         case B43_PHYTYPE_A:
2034         case B43_PHYTYPE_G:
2035                 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2036                 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2037                 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2038                     << B43_PHY_BBANDCFG_RXANT_SHIFT;
2039                 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2040
2041                 if (autodiv) {
2042                         tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2043                         if (antenna == B43_ANTENNA_AUTO0)
2044                                 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2045                         else
2046                                 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2047                         b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2048                 }
2049                 if (phy->type == B43_PHYTYPE_G) {
2050                         tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2051                         if (autodiv)
2052                                 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2053                         else
2054                                 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2055                         b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2056                         if (phy->rev >= 2) {
2057                                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2058                                 tmp |= B43_PHY_OFDM61_10;
2059                                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2060
2061                                 tmp =
2062                                     b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2063                                 tmp = (tmp & 0xFF00) | 0x15;
2064                                 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2065                                               tmp);
2066
2067                                 if (phy->rev == 2) {
2068                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2069                                                       8);
2070                                 } else {
2071                                         tmp =
2072                                             b43_phy_read(dev,
2073                                                          B43_PHY_ADIVRELATED);
2074                                         tmp = (tmp & 0xFF00) | 8;
2075                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2076                                                       tmp);
2077                                 }
2078                         }
2079                         if (phy->rev >= 6)
2080                                 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2081                 } else {
2082                         if (phy->rev < 3) {
2083                                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2084                                 tmp = (tmp & 0xFF00) | 0x24;
2085                                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2086                         } else {
2087                                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2088                                 tmp |= 0x10;
2089                                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2090                                 if (phy->analog == 3) {
2091                                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2092                                                       0x1D);
2093                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2094                                                       8);
2095                                 } else {
2096                                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2097                                                       0x3A);
2098                                         tmp =
2099                                             b43_phy_read(dev,
2100                                                          B43_PHY_ADIVRELATED);
2101                                         tmp = (tmp & 0xFF00) | 8;
2102                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2103                                                       tmp);
2104                                 }
2105                         }
2106                 }
2107                 break;
2108         case B43_PHYTYPE_B:
2109                 tmp = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
2110                 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2111                 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2112                     << B43_PHY_BBANDCFG_RXANT_SHIFT;
2113                 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
2114                 break;
2115         default:
2116                 B43_WARN_ON(1);
2117         }
2118
2119         hf |= B43_HF_ANTDIVHELP;
2120         b43_hf_write(dev, hf);
2121 }
2122
2123 /* Get the freq, as it has to be written to the device. */
2124 static inline u16 channel2freq_bg(u8 channel)
2125 {
2126         B43_WARN_ON(!(channel >= 1 && channel <= 14));
2127
2128         return b43_radio_channel_codes_bg[channel - 1];
2129 }
2130
2131 /* Get the freq, as it has to be written to the device. */
2132 static inline u16 channel2freq_a(u8 channel)
2133 {
2134         B43_WARN_ON(channel > 200);
2135
2136         return (5000 + 5 * channel);
2137 }
2138
2139 void b43_radio_lock(struct b43_wldev *dev)
2140 {
2141         u32 macctl;
2142
2143         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2144         macctl |= B43_MACCTL_RADIOLOCK;
2145         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2146         /* Commit the write and wait for the device
2147          * to exit any radio register access. */
2148         b43_read32(dev, B43_MMIO_MACCTL);
2149         udelay(10);
2150 }
2151
2152 void b43_radio_unlock(struct b43_wldev *dev)
2153 {
2154         u32 macctl;
2155
2156         /* Commit any write */
2157         b43_read16(dev, B43_MMIO_PHY_VER);
2158         /* unlock */
2159         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2160         macctl &= ~B43_MACCTL_RADIOLOCK;
2161         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2162 }
2163
2164 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2165 {
2166         struct b43_phy *phy = &dev->phy;
2167
2168         switch (phy->type) {
2169         case B43_PHYTYPE_A:
2170                 offset |= 0x0040;
2171                 break;
2172         case B43_PHYTYPE_B:
2173                 if (phy->radio_ver == 0x2053) {
2174                         if (offset < 0x70)
2175                                 offset += 0x80;
2176                         else if (offset < 0x80)
2177                                 offset += 0x70;
2178                 } else if (phy->radio_ver == 0x2050) {
2179                         offset |= 0x80;
2180                 } else
2181                         B43_WARN_ON(1);
2182                 break;
2183         case B43_PHYTYPE_G:
2184                 offset |= 0x80;
2185                 break;
2186         }
2187
2188         b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2189         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2190 }
2191
2192 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
2193 {
2194         b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2195         mmiowb();
2196         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
2197 }
2198
2199 static void b43_set_all_gains(struct b43_wldev *dev,
2200                               s16 first, s16 second, s16 third)
2201 {
2202         struct b43_phy *phy = &dev->phy;
2203         u16 i;
2204         u16 start = 0x08, end = 0x18;
2205         u16 tmp;
2206         u16 table;
2207
2208         if (phy->rev <= 1) {
2209                 start = 0x10;
2210                 end = 0x20;
2211         }
2212
2213         table = B43_OFDMTAB_GAINX;
2214         if (phy->rev <= 1)
2215                 table = B43_OFDMTAB_GAINX_R1;
2216         for (i = 0; i < 4; i++)
2217                 b43_ofdmtab_write16(dev, table, i, first);
2218
2219         for (i = start; i < end; i++)
2220                 b43_ofdmtab_write16(dev, table, i, second);
2221
2222         if (third != -1) {
2223                 tmp = ((u16) third << 14) | ((u16) third << 6);
2224                 b43_phy_write(dev, 0x04A0,
2225                               (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
2226                 b43_phy_write(dev, 0x04A1,
2227                               (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
2228                 b43_phy_write(dev, 0x04A2,
2229                               (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
2230         }
2231         b43_dummy_transmission(dev);
2232 }
2233
2234 static void b43_set_original_gains(struct b43_wldev *dev)
2235 {
2236         struct b43_phy *phy = &dev->phy;
2237         u16 i, tmp;
2238         u16 table;
2239         u16 start = 0x0008, end = 0x0018;
2240
2241         if (phy->rev <= 1) {
2242                 start = 0x0010;
2243                 end = 0x0020;
2244         }
2245
2246         table = B43_OFDMTAB_GAINX;
2247         if (phy->rev <= 1)
2248                 table = B43_OFDMTAB_GAINX_R1;
2249         for (i = 0; i < 4; i++) {
2250                 tmp = (i & 0xFFFC);
2251                 tmp |= (i & 0x0001) << 1;
2252                 tmp |= (i & 0x0002) >> 1;
2253
2254                 b43_ofdmtab_write16(dev, table, i, tmp);
2255         }
2256
2257         for (i = start; i < end; i++)
2258                 b43_ofdmtab_write16(dev, table, i, i - start);
2259
2260         b43_phy_write(dev, 0x04A0,
2261                       (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
2262         b43_phy_write(dev, 0x04A1,
2263                       (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
2264         b43_phy_write(dev, 0x04A2,
2265                       (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
2266         b43_dummy_transmission(dev);
2267 }
2268
2269 /* Synthetic PU workaround */
2270 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
2271 {
2272         struct b43_phy *phy = &dev->phy;
2273
2274         might_sleep();
2275
2276         if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
2277                 /* We do not need the workaround. */
2278                 return;
2279         }
2280
2281         if (channel <= 10) {
2282                 b43_write16(dev, B43_MMIO_CHANNEL,
2283                             channel2freq_bg(channel + 4));
2284         } else {
2285                 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
2286         }
2287         msleep(1);
2288         b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2289 }
2290
2291 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel)
2292 {
2293         struct b43_phy *phy = &dev->phy;
2294         u8 ret = 0;
2295         u16 saved, rssi, temp;
2296         int i, j = 0;
2297
2298         saved = b43_phy_read(dev, 0x0403);
2299         b43_radio_selectchannel(dev, channel, 0);
2300         b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2301         if (phy->aci_hw_rssi)
2302                 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2303         else
2304                 rssi = saved & 0x3F;
2305         /* clamp temp to signed 5bit */
2306         if (rssi > 32)
2307                 rssi -= 64;
2308         for (i = 0; i < 100; i++) {
2309                 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2310                 if (temp > 32)
2311                         temp -= 64;
2312                 if (temp < rssi)
2313                         j++;
2314                 if (j >= 20)
2315                         ret = 1;
2316         }
2317         b43_phy_write(dev, 0x0403, saved);
2318
2319         return ret;
2320 }
2321
2322 u8 b43_radio_aci_scan(struct b43_wldev * dev)
2323 {
2324         struct b43_phy *phy = &dev->phy;
2325         u8 ret[13];
2326         unsigned int channel = phy->channel;
2327         unsigned int i, j, start, end;
2328         unsigned long phylock_flags;
2329
2330         if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2331                 return 0;
2332
2333         b43_phy_lock(dev, phylock_flags);
2334         b43_radio_lock(dev);
2335         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2336         b43_phy_write(dev, B43_PHY_G_CRS,
2337                       b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2338         b43_set_all_gains(dev, 3, 8, 1);
2339
2340         start = (channel - 5 > 0) ? channel - 5 : 1;
2341         end = (channel + 5 < 14) ? channel + 5 : 13;
2342
2343         for (i = start; i <= end; i++) {
2344                 if (abs(channel - i) > 2)
2345                         ret[i - 1] = b43_radio_aci_detect(dev, i);
2346         }
2347         b43_radio_selectchannel(dev, channel, 0);
2348         b43_phy_write(dev, 0x0802,
2349                       (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2350         b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
2351         b43_phy_write(dev, B43_PHY_G_CRS,
2352                       b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2353         b43_set_original_gains(dev);
2354         for (i = 0; i < 13; i++) {
2355                 if (!ret[i])
2356                         continue;
2357                 end = (i + 5 < 13) ? i + 5 : 13;
2358                 for (j = i; j < end; j++)
2359                         ret[j] = 1;
2360         }
2361         b43_radio_unlock(dev);
2362         b43_phy_unlock(dev, phylock_flags);
2363
2364         return ret[channel - 1];
2365 }
2366
2367 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2368 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
2369 {
2370         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2371         mmiowb();
2372         b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
2373 }
2374
2375 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2376 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
2377 {
2378         u16 val;
2379
2380         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2381         val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
2382
2383         return (s16) val;
2384 }
2385
2386 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2387 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
2388 {
2389         u16 i;
2390         s16 tmp;
2391
2392         for (i = 0; i < 64; i++) {
2393                 tmp = b43_nrssi_hw_read(dev, i);
2394                 tmp -= val;
2395                 tmp = limit_value(tmp, -32, 31);
2396                 b43_nrssi_hw_write(dev, i, tmp);
2397         }
2398 }
2399
2400 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2401 void b43_nrssi_mem_update(struct b43_wldev *dev)
2402 {
2403         struct b43_phy *phy = &dev->phy;
2404         s16 i, delta;
2405         s32 tmp;
2406
2407         delta = 0x1F - phy->nrssi[0];
2408         for (i = 0; i < 64; i++) {
2409                 tmp = (i - delta) * phy->nrssislope;
2410                 tmp /= 0x10000;
2411                 tmp += 0x3A;
2412                 tmp = limit_value(tmp, 0, 0x3F);
2413                 phy->nrssi_lt[i] = tmp;
2414         }
2415 }
2416
2417 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
2418 {
2419         struct b43_phy *phy = &dev->phy;
2420         u16 backup[20] = { 0 };
2421         s16 v47F;
2422         u16 i;
2423         u16 saved = 0xFFFF;
2424
2425         backup[0] = b43_phy_read(dev, 0x0001);
2426         backup[1] = b43_phy_read(dev, 0x0811);
2427         backup[2] = b43_phy_read(dev, 0x0812);
2428         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2429                 backup[3] = b43_phy_read(dev, 0x0814);
2430                 backup[4] = b43_phy_read(dev, 0x0815);
2431         }
2432         backup[5] = b43_phy_read(dev, 0x005A);
2433         backup[6] = b43_phy_read(dev, 0x0059);
2434         backup[7] = b43_phy_read(dev, 0x0058);
2435         backup[8] = b43_phy_read(dev, 0x000A);
2436         backup[9] = b43_phy_read(dev, 0x0003);
2437         backup[10] = b43_radio_read16(dev, 0x007A);
2438         backup[11] = b43_radio_read16(dev, 0x0043);
2439
2440         b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
2441         b43_phy_write(dev, 0x0001,
2442                       (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
2443         b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2444         b43_phy_write(dev, 0x0812,
2445                       (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
2446         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
2447         if (phy->rev >= 6) {
2448                 backup[12] = b43_phy_read(dev, 0x002E);
2449                 backup[13] = b43_phy_read(dev, 0x002F);
2450                 backup[14] = b43_phy_read(dev, 0x080F);
2451                 backup[15] = b43_phy_read(dev, 0x0810);
2452                 backup[16] = b43_phy_read(dev, 0x0801);
2453                 backup[17] = b43_phy_read(dev, 0x0060);
2454                 backup[18] = b43_phy_read(dev, 0x0014);
2455                 backup[19] = b43_phy_read(dev, 0x0478);
2456
2457                 b43_phy_write(dev, 0x002E, 0);
2458                 b43_phy_write(dev, 0x002F, 0);
2459                 b43_phy_write(dev, 0x080F, 0);
2460                 b43_phy_write(dev, 0x0810, 0);
2461                 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
2462                 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
2463                 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
2464                 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
2465         }
2466         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
2467         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
2468         udelay(30);
2469
2470         v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2471         if (v47F >= 0x20)
2472                 v47F -= 0x40;
2473         if (v47F == 31) {
2474                 for (i = 7; i >= 4; i--) {
2475                         b43_radio_write16(dev, 0x007B, i);
2476                         udelay(20);
2477                         v47F =
2478                             (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2479                         if (v47F >= 0x20)
2480                                 v47F -= 0x40;
2481                         if (v47F < 31 && saved == 0xFFFF)
2482                                 saved = i;
2483                 }
2484                 if (saved == 0xFFFF)
2485                         saved = 4;
2486         } else {
2487                 b43_radio_write16(dev, 0x007A,
2488                                   b43_radio_read16(dev, 0x007A) & 0x007F);
2489                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2490                         b43_phy_write(dev, 0x0814,
2491                                       b43_phy_read(dev, 0x0814) | 0x0001);
2492                         b43_phy_write(dev, 0x0815,
2493                                       b43_phy_read(dev, 0x0815) & 0xFFFE);
2494                 }
2495                 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2496                 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
2497                 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
2498                 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
2499                 b43_phy_write(dev, 0x005A, 0x0480);
2500                 b43_phy_write(dev, 0x0059, 0x0810);
2501                 b43_phy_write(dev, 0x0058, 0x000D);
2502                 if (phy->rev == 0) {
2503                         b43_phy_write(dev, 0x0003, 0x0122);
2504                 } else {
2505                         b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
2506                                       | 0x2000);
2507                 }
2508                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2509                         b43_phy_write(dev, 0x0814,
2510                                       b43_phy_read(dev, 0x0814) | 0x0004);
2511                         b43_phy_write(dev, 0x0815,
2512                                       b43_phy_read(dev, 0x0815) & 0xFFFB);
2513                 }
2514                 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
2515                               | 0x0040);
2516                 b43_radio_write16(dev, 0x007A,
2517                                   b43_radio_read16(dev, 0x007A) | 0x000F);
2518                 b43_set_all_gains(dev, 3, 0, 1);
2519                 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
2520                                                 & 0x00F0) | 0x000F);
2521                 udelay(30);
2522                 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2523                 if (v47F >= 0x20)
2524                         v47F -= 0x40;
2525                 if (v47F == -32) {
2526                         for (i = 0; i < 4; i++) {
2527                                 b43_radio_write16(dev, 0x007B, i);
2528                                 udelay(20);
2529                                 v47F =
2530                                     (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
2531                                            0x003F);
2532                                 if (v47F >= 0x20)
2533                                         v47F -= 0x40;
2534                                 if (v47F > -31 && saved == 0xFFFF)
2535                                         saved = i;
2536                         }
2537                         if (saved == 0xFFFF)
2538                                 saved = 3;
2539                 } else
2540                         saved = 0;
2541         }
2542         b43_radio_write16(dev, 0x007B, saved);
2543
2544         if (phy->rev >= 6) {
2545                 b43_phy_write(dev, 0x002E, backup[12]);
2546                 b43_phy_write(dev, 0x002F, backup[13]);
2547                 b43_phy_write(dev, 0x080F, backup[14]);
2548                 b43_phy_write(dev, 0x0810, backup[15]);
2549         }
2550         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2551                 b43_phy_write(dev, 0x0814, backup[3]);
2552                 b43_phy_write(dev, 0x0815, backup[4]);
2553         }
2554         b43_phy_write(dev, 0x005A, backup[5]);
2555         b43_phy_write(dev, 0x0059, backup[6]);
2556         b43_phy_write(dev, 0x0058, backup[7]);
2557         b43_phy_write(dev, 0x000A, backup[8]);
2558         b43_phy_write(dev, 0x0003, backup[9]);
2559         b43_radio_write16(dev, 0x0043, backup[11]);
2560         b43_radio_write16(dev, 0x007A, backup[10]);
2561         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
2562         b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
2563         b43_set_original_gains(dev);
2564         if (phy->rev >= 6) {
2565                 b43_phy_write(dev, 0x0801, backup[16]);
2566                 b43_phy_write(dev, 0x0060, backup[17]);
2567                 b43_phy_write(dev, 0x0014, backup[18]);
2568                 b43_phy_write(dev, 0x0478, backup[19]);
2569         }
2570         b43_phy_write(dev, 0x0001, backup[0]);
2571         b43_phy_write(dev, 0x0812, backup[2]);
2572         b43_phy_write(dev, 0x0811, backup[1]);
2573 }
2574
2575 void b43_calc_nrssi_slope(struct b43_wldev *dev)
2576 {
2577         struct b43_phy *phy = &dev->phy;
2578         u16 backup[18] = { 0 };
2579         u16 tmp;
2580         s16 nrssi0, nrssi1;
2581
2582         switch (phy->type) {
2583         case B43_PHYTYPE_B:
2584                 backup[0] = b43_radio_read16(dev, 0x007A);
2585                 backup[1] = b43_radio_read16(dev, 0x0052);
2586                 backup[2] = b43_radio_read16(dev, 0x0043);
2587                 backup[3] = b43_phy_read(dev, 0x0030);
2588                 backup[4] = b43_phy_read(dev, 0x0026);
2589                 backup[5] = b43_phy_read(dev, 0x0015);
2590                 backup[6] = b43_phy_read(dev, 0x002A);
2591                 backup[7] = b43_phy_read(dev, 0x0020);
2592                 backup[8] = b43_phy_read(dev, 0x005A);
2593                 backup[9] = b43_phy_read(dev, 0x0059);
2594                 backup[10] = b43_phy_read(dev, 0x0058);
2595                 backup[11] = b43_read16(dev, 0x03E2);
2596                 backup[12] = b43_read16(dev, 0x03E6);
2597                 backup[13] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2598
2599                 tmp = b43_radio_read16(dev, 0x007A);
2600                 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
2601                 b43_radio_write16(dev, 0x007A, tmp);
2602                 b43_phy_write(dev, 0x0030, 0x00FF);
2603                 b43_write16(dev, 0x03EC, 0x7F7F);
2604                 b43_phy_write(dev, 0x0026, 0x0000);
2605                 b43_phy_write(dev, 0x0015, b43_phy_read(dev, 0x0015) | 0x0020);
2606                 b43_phy_write(dev, 0x002A, 0x08A3);
2607                 b43_radio_write16(dev, 0x007A,
2608                                   b43_radio_read16(dev, 0x007A) | 0x0080);
2609
2610                 nrssi0 = (s16) b43_phy_read(dev, 0x0027);
2611                 b43_radio_write16(dev, 0x007A,
2612                                   b43_radio_read16(dev, 0x007A) & 0x007F);
2613                 if (phy->rev >= 2) {
2614                         b43_write16(dev, 0x03E6, 0x0040);
2615                 } else if (phy->rev == 0) {
2616                         b43_write16(dev, 0x03E6, 0x0122);
2617                 } else {
2618                         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2619                                     b43_read16(dev,
2620                                                B43_MMIO_CHANNEL_EXT) & 0x2000);
2621                 }
2622                 b43_phy_write(dev, 0x0020, 0x3F3F);
2623                 b43_phy_write(dev, 0x0015, 0xF330);
2624                 b43_radio_write16(dev, 0x005A, 0x0060);
2625                 b43_radio_write16(dev, 0x0043,
2626                                   b43_radio_read16(dev, 0x0043) & 0x00F0);
2627                 b43_phy_write(dev, 0x005A, 0x0480);
2628                 b43_phy_write(dev, 0x0059, 0x0810);
2629                 b43_phy_write(dev, 0x0058, 0x000D);
2630                 udelay(20);
2631
2632                 nrssi1 = (s16) b43_phy_read(dev, 0x0027);
2633                 b43_phy_write(dev, 0x0030, backup[3]);
2634                 b43_radio_write16(dev, 0x007A, backup[0]);
2635                 b43_write16(dev, 0x03E2, backup[11]);
2636                 b43_phy_write(dev, 0x0026, backup[4]);
2637                 b43_phy_write(dev, 0x0015, backup[5]);
2638                 b43_phy_write(dev, 0x002A, backup[6]);
2639                 b43_synth_pu_workaround(dev, phy->channel);
2640                 if (phy->rev != 0)
2641                         b43_write16(dev, 0x03F4, backup[13]);
2642
2643                 b43_phy_write(dev, 0x0020, backup[7]);
2644                 b43_phy_write(dev, 0x005A, backup[8]);
2645                 b43_phy_write(dev, 0x0059, backup[9]);
2646                 b43_phy_write(dev, 0x0058, backup[10]);
2647                 b43_radio_write16(dev, 0x0052, backup[1]);
2648                 b43_radio_write16(dev, 0x0043, backup[2]);
2649
2650                 if (nrssi0 == nrssi1)
2651                         phy->nrssislope = 0x00010000;
2652                 else
2653                         phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2654
2655                 if (nrssi0 <= -4) {
2656                         phy->nrssi[0] = nrssi0;
2657                         phy->nrssi[1] = nrssi1;
2658                 }
2659                 break;
2660         case B43_PHYTYPE_G:
2661                 if (phy->radio_rev >= 9)
2662                         return;
2663                 if (phy->radio_rev == 8)
2664                         b43_calc_nrssi_offset(dev);
2665
2666                 b43_phy_write(dev, B43_PHY_G_CRS,
2667                               b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2668                 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2669                 backup[7] = b43_read16(dev, 0x03E2);
2670                 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
2671                 backup[0] = b43_radio_read16(dev, 0x007A);
2672                 backup[1] = b43_radio_read16(dev, 0x0052);
2673                 backup[2] = b43_radio_read16(dev, 0x0043);
2674                 backup[3] = b43_phy_read(dev, 0x0015);
2675                 backup[4] = b43_phy_read(dev, 0x005A);
2676                 backup[5] = b43_phy_read(dev, 0x0059);
2677                 backup[6] = b43_phy_read(dev, 0x0058);
2678                 backup[8] = b43_read16(dev, 0x03E6);
2679                 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2680                 if (phy->rev >= 3) {
2681                         backup[10] = b43_phy_read(dev, 0x002E);
2682                         backup[11] = b43_phy_read(dev, 0x002F);
2683                         backup[12] = b43_phy_read(dev, 0x080F);
2684                         backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
2685                         backup[14] = b43_phy_read(dev, 0x0801);
2686                         backup[15] = b43_phy_read(dev, 0x0060);
2687                         backup[16] = b43_phy_read(dev, 0x0014);
2688                         backup[17] = b43_phy_read(dev, 0x0478);
2689                         b43_phy_write(dev, 0x002E, 0);
2690                         b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
2691                         switch (phy->rev) {
2692                         case 4:
2693                         case 6:
2694                         case 7:
2695                                 b43_phy_write(dev, 0x0478,
2696                                               b43_phy_read(dev, 0x0478)
2697                                               | 0x0100);
2698                                 b43_phy_write(dev, 0x0801,
2699                                               b43_phy_read(dev, 0x0801)
2700                                               | 0x0040);
2701                                 break;
2702                         case 3:
2703                         case 5:
2704                                 b43_phy_write(dev, 0x0801,
2705                                               b43_phy_read(dev, 0x0801)
2706                                               & 0xFFBF);
2707                                 break;
2708                         }
2709                         b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
2710                                       | 0x0040);
2711                         b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
2712                                       | 0x0200);
2713                 }
2714                 b43_radio_write16(dev, 0x007A,
2715                                   b43_radio_read16(dev, 0x007A) | 0x0070);
2716                 b43_set_all_gains(dev, 0, 8, 0);
2717                 b43_radio_write16(dev, 0x007A,
2718                                   b43_radio_read16(dev, 0x007A) & 0x00F7);
2719                 if (phy->rev >= 2) {
2720                         b43_phy_write(dev, 0x0811,
2721                                       (b43_phy_read(dev, 0x0811) & 0xFFCF) |
2722                                       0x0030);
2723                         b43_phy_write(dev, 0x0812,
2724                                       (b43_phy_read(dev, 0x0812) & 0xFFCF) |
2725                                       0x0010);
2726                 }
2727                 b43_radio_write16(dev, 0x007A,
2728                                   b43_radio_read16(dev, 0x007A) | 0x0080);
2729                 udelay(20);
2730
2731                 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2732                 if (nrssi0 >= 0x0020)
2733                         nrssi0 -= 0x0040;
2734
2735                 b43_radio_write16(dev, 0x007A,
2736                                   b43_radio_read16(dev, 0x007A) & 0x007F);
2737                 if (phy->rev >= 2) {
2738                         b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
2739                                                     & 0xFF9F) | 0x0040);
2740                 }
2741
2742                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2743                             b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2744                             | 0x2000);
2745                 b43_radio_write16(dev, 0x007A,
2746                                   b43_radio_read16(dev, 0x007A) | 0x000F);
2747                 b43_phy_write(dev, 0x0015, 0xF330);
2748                 if (phy->rev >= 2) {
2749                         b43_phy_write(dev, 0x0812,
2750                                       (b43_phy_read(dev, 0x0812) & 0xFFCF) |
2751                                       0x0020);
2752                         b43_phy_write(dev, 0x0811,
2753                                       (b43_phy_read(dev, 0x0811) & 0xFFCF) |
2754                                       0x0020);
2755                 }
2756
2757                 b43_set_all_gains(dev, 3, 0, 1);
2758                 if (phy->radio_rev == 8) {
2759                         b43_radio_write16(dev, 0x0043, 0x001F);
2760                 } else {
2761                         tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
2762                         b43_radio_write16(dev, 0x0052, tmp | 0x0060);
2763                         tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
2764                         b43_radio_write16(dev, 0x0043, tmp | 0x0009);
2765                 }
2766                 b43_phy_write(dev, 0x005A, 0x0480);
2767                 b43_phy_write(dev, 0x0059, 0x0810);
2768                 b43_phy_write(dev, 0x0058, 0x000D);
2769                 udelay(20);
2770                 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2771                 if (nrssi1 >= 0x0020)
2772                         nrssi1 -= 0x0040;
2773                 if (nrssi0 == nrssi1)
2774                         phy->nrssislope = 0x00010000;
2775                 else
2776                         phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2777                 if (nrssi0 >= -4) {
2778                         phy->nrssi[0] = nrssi1;
2779                         phy->nrssi[1] = nrssi0;
2780                 }
2781                 if (phy->rev >= 3) {
2782                         b43_phy_write(dev, 0x002E, backup[10]);
2783                         b43_phy_write(dev, 0x002F, backup[11]);
2784                         b43_phy_write(dev, 0x080F, backup[12]);
2785                         b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
2786                 }
2787                 if (phy->rev >= 2) {
2788                         b43_phy_write(dev, 0x0812,
2789                                       b43_phy_read(dev, 0x0812) & 0xFFCF);
2790                         b43_phy_write(dev, 0x0811,
2791                                       b43_phy_read(dev, 0x0811) & 0xFFCF);
2792                 }
2793
2794                 b43_radio_write16(dev, 0x007A, backup[0]);
2795                 b43_radio_write16(dev, 0x0052, backup[1]);
2796                 b43_radio_write16(dev, 0x0043, backup[2]);
2797                 b43_write16(dev, 0x03E2, backup[7]);
2798                 b43_write16(dev, 0x03E6, backup[8]);
2799                 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
2800                 b43_phy_write(dev, 0x0015, backup[3]);
2801                 b43_phy_write(dev, 0x005A, backup[4]);
2802                 b43_phy_write(dev, 0x0059, backup[5]);
2803                 b43_phy_write(dev, 0x0058, backup[6]);
2804                 b43_synth_pu_workaround(dev, phy->channel);
2805                 b43_phy_write(dev, 0x0802,
2806                               b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
2807                 b43_set_original_gains(dev);
2808                 b43_phy_write(dev, B43_PHY_G_CRS,
2809                               b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2810                 if (phy->rev >= 3) {
2811                         b43_phy_write(dev, 0x0801, backup[14]);
2812                         b43_phy_write(dev, 0x0060, backup[15]);
2813                         b43_phy_write(dev, 0x0014, backup[16]);
2814                         b43_phy_write(dev, 0x0478, backup[17]);
2815                 }
2816                 b43_nrssi_mem_update(dev);
2817                 b43_calc_nrssi_threshold(dev);
2818                 break;
2819         default:
2820                 B43_WARN_ON(1);
2821         }
2822 }
2823
2824 void b43_calc_nrssi_threshold(struct b43_wldev *dev)
2825 {
2826         struct b43_phy *phy = &dev->phy;
2827         s32 threshold;
2828         s32 a, b;
2829         s16 tmp16;
2830         u16 tmp_u16;
2831
2832         switch (phy->type) {
2833         case B43_PHYTYPE_B:{
2834                         if (phy->radio_ver != 0x2050)
2835                                 return;
2836                         if (!
2837                             (dev->dev->bus->sprom.r1.
2838                              boardflags_lo & B43_BFL_RSSI))
2839                                 return;
2840
2841                         if (phy->radio_rev >= 6) {
2842                                 threshold =
2843                                     (phy->nrssi[1] - phy->nrssi[0]) * 32;
2844                                 threshold += 20 * (phy->nrssi[0] + 1);
2845                                 threshold /= 40;
2846                         } else
2847                                 threshold = phy->nrssi[1] - 5;
2848
2849                         threshold = limit_value(threshold, 0, 0x3E);
2850                         b43_phy_read(dev, 0x0020);      /* dummy read */
2851                         b43_phy_write(dev, 0x0020,
2852                                       (((u16) threshold) << 8) | 0x001C);
2853
2854                         if (phy->radio_rev >= 6) {
2855                                 b43_phy_write(dev, 0x0087, 0x0E0D);
2856                                 b43_phy_write(dev, 0x0086, 0x0C0B);
2857                                 b43_phy_write(dev, 0x0085, 0x0A09);
2858                                 b43_phy_write(dev, 0x0084, 0x0808);
2859                                 b43_phy_write(dev, 0x0083, 0x0808);
2860                                 b43_phy_write(dev, 0x0082, 0x0604);
2861                                 b43_phy_write(dev, 0x0081, 0x0302);
2862                                 b43_phy_write(dev, 0x0080, 0x0100);
2863                         }
2864                         break;
2865                 }
2866         case B43_PHYTYPE_G:
2867                 if (!phy->gmode ||
2868                     !(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
2869                         tmp16 = b43_nrssi_hw_read(dev, 0x20);
2870                         if (tmp16 >= 0x20)
2871                                 tmp16 -= 0x40;
2872                         if (tmp16 < 3) {
2873                                 b43_phy_write(dev, 0x048A,
2874                                               (b43_phy_read(dev, 0x048A)
2875                                                & 0xF000) | 0x09EB);
2876                         } else {
2877                                 b43_phy_write(dev, 0x048A,
2878                                               (b43_phy_read(dev, 0x048A)
2879                                                & 0xF000) | 0x0AED);
2880                         }
2881                 } else {
2882                         if (phy->interfmode == B43_INTERFMODE_NONWLAN) {
2883                                 a = 0xE;
2884                                 b = 0xA;
2885                         } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
2886                                 a = 0x13;
2887                                 b = 0x12;
2888                         } else {
2889                                 a = 0xE;
2890                                 b = 0x11;
2891                         }
2892
2893                         a = a * (phy->nrssi[1] - phy->nrssi[0]);
2894                         a += (phy->nrssi[0] << 6);
2895                         if (a < 32)
2896                                 a += 31;
2897                         else
2898                                 a += 32;
2899                         a = a >> 6;
2900                         a = limit_value(a, -31, 31);
2901
2902                         b = b * (phy->nrssi[1] - phy->nrssi[0]);
2903                         b += (phy->nrssi[0] << 6);
2904                         if (b < 32)
2905                                 b += 31;
2906                         else
2907                                 b += 32;
2908                         b = b >> 6;
2909                         b = limit_value(b, -31, 31);
2910
2911                         tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
2912                         tmp_u16 |= ((u32) b & 0x0000003F);
2913                         tmp_u16 |= (((u32) a & 0x0000003F) << 6);
2914                         b43_phy_write(dev, 0x048A, tmp_u16);
2915                 }
2916                 break;
2917         default:
2918                 B43_WARN_ON(1);
2919         }
2920 }
2921
2922 /* Stack implementation to save/restore values from the
2923  * interference mitigation code.
2924  * It is save to restore values in random order.
2925  */
2926 static void _stack_save(u32 * _stackptr, size_t * stackidx,
2927                         u8 id, u16 offset, u16 value)
2928 {
2929         u32 *stackptr = &(_stackptr[*stackidx]);
2930
2931         B43_WARN_ON(offset & 0xF000);
2932         B43_WARN_ON(id & 0xF0);
2933         *stackptr = offset;
2934         *stackptr |= ((u32) id) << 12;
2935         *stackptr |= ((u32) value) << 16;
2936         (*stackidx)++;
2937         B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
2938 }
2939
2940 static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
2941 {
2942         size_t i;
2943
2944         B43_WARN_ON(offset & 0xF000);
2945         B43_WARN_ON(id & 0xF0);
2946         for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
2947                 if ((*stackptr & 0x00000FFF) != offset)
2948                         continue;
2949                 if (((*stackptr & 0x0000F000) >> 12) != id)
2950                         continue;
2951                 return ((*stackptr & 0xFFFF0000) >> 16);
2952         }
2953         B43_WARN_ON(1);
2954
2955         return 0;
2956 }
2957
2958 #define phy_stacksave(offset)                                   \
2959         do {                                                    \
2960                 _stack_save(stack, &stackidx, 0x1, (offset),    \
2961                             b43_phy_read(dev, (offset)));       \
2962         } while (0)
2963 #define phy_stackrestore(offset)                                \
2964         do {                                                    \
2965                 b43_phy_write(dev, (offset),            \
2966                                   _stack_restore(stack, 0x1,    \
2967                                                  (offset)));    \
2968         } while (0)
2969 #define radio_stacksave(offset)                                         \
2970         do {                                                            \
2971                 _stack_save(stack, &stackidx, 0x2, (offset),            \
2972                             b43_radio_read16(dev, (offset)));   \
2973         } while (0)
2974 #define radio_stackrestore(offset)                                      \
2975         do {                                                            \
2976                 b43_radio_write16(dev, (offset),                        \
2977                                       _stack_restore(stack, 0x2,        \
2978                                                      (offset)));        \
2979         } while (0)
2980 #define ofdmtab_stacksave(table, offset)                        \
2981         do {                                                    \
2982                 _stack_save(stack, &stackidx, 0x3, (offset)|(table),    \
2983                             b43_ofdmtab_read16(dev, (table), (offset)));        \
2984         } while (0)
2985 #define ofdmtab_stackrestore(table, offset)                     \
2986         do {                                                    \
2987                 b43_ofdmtab_write16(dev, (table),       (offset),       \
2988                                   _stack_restore(stack, 0x3,    \
2989                                                  (offset)|(table)));    \
2990         } while (0)
2991
2992 static void
2993 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
2994 {
2995         struct b43_phy *phy = &dev->phy;
2996         u16 tmp, flipped;
2997         size_t stackidx = 0;
2998         u32 *stack = phy->interfstack;
2999
3000         switch (mode) {
3001         case B43_INTERFMODE_NONWLAN:
3002                 if (phy->rev != 1) {
3003                         b43_phy_write(dev, 0x042B,
3004                                       b43_phy_read(dev, 0x042B) | 0x0800);
3005                         b43_phy_write(dev, B43_PHY_G_CRS,
3006                                       b43_phy_read(dev,
3007                                                    B43_PHY_G_CRS) & ~0x4000);
3008                         break;
3009                 }
3010                 radio_stacksave(0x0078);
3011                 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
3012                 flipped = flip_4bit(tmp);
3013                 if (flipped < 10 && flipped >= 8)
3014                         flipped = 7;
3015                 else if (flipped >= 10)
3016                         flipped -= 3;
3017                 flipped = flip_4bit(flipped);
3018                 flipped = (flipped << 1) | 0x0020;
3019                 b43_radio_write16(dev, 0x0078, flipped);
3020
3021                 b43_calc_nrssi_threshold(dev);
3022
3023                 phy_stacksave(0x0406);
3024                 b43_phy_write(dev, 0x0406, 0x7E28);
3025
3026                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
3027                 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3028                               b43_phy_read(dev,
3029                                            B43_PHY_RADIO_BITFIELD) | 0x1000);
3030
3031                 phy_stacksave(0x04A0);
3032                 b43_phy_write(dev, 0x04A0,
3033                               (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
3034                 phy_stacksave(0x04A1);
3035                 b43_phy_write(dev, 0x04A1,
3036                               (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
3037                 phy_stacksave(0x04A2);
3038                 b43_phy_write(dev, 0x04A2,
3039                               (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
3040                 phy_stacksave(0x04A8);
3041                 b43_phy_write(dev, 0x04A8,
3042                               (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
3043                 phy_stacksave(0x04AB);
3044                 b43_phy_write(dev, 0x04AB,
3045                               (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
3046
3047                 phy_stacksave(0x04A7);
3048                 b43_phy_write(dev, 0x04A7, 0x0002);
3049                 phy_stacksave(0x04A3);
3050                 b43_phy_write(dev, 0x04A3, 0x287A);
3051                 phy_stacksave(0x04A9);
3052                 b43_phy_write(dev, 0x04A9, 0x2027);
3053                 phy_stacksave(0x0493);
3054                 b43_phy_write(dev, 0x0493, 0x32F5);
3055                 phy_stacksave(0x04AA);
3056                 b43_phy_write(dev, 0x04AA, 0x2027);
3057                 phy_stacksave(0x04AC);
3058                 b43_phy_write(dev, 0x04AC, 0x32F5);
3059                 break;
3060         case B43_INTERFMODE_MANUALWLAN:
3061                 if (b43_phy_read(dev, 0x0033) & 0x0800)
3062                         break;
3063
3064                 phy->aci_enable = 1;
3065
3066                 phy_stacksave(B43_PHY_RADIO_BITFIELD);
3067                 phy_stacksave(B43_PHY_G_CRS);
3068                 if (phy->rev < 2) {
3069                         phy_stacksave(0x0406);
3070                 } else {
3071                         phy_stacksave(0x04C0);
3072                         phy_stacksave(0x04C1);
3073                 }
3074                 phy_stacksave(0x0033);
3075                 phy_stacksave(0x04A7);
3076                 phy_stacksave(0x04A3);
3077                 phy_stacksave(0x04A9);
3078                 phy_stacksave(0x04AA);
3079                 phy_stacksave(0x04AC);
3080                 phy_stacksave(0x0493);
3081                 phy_stacksave(0x04A1);
3082                 phy_stacksave(0x04A0);
3083                 phy_stacksave(0x04A2);
3084                 phy_stacksave(0x048A);
3085                 phy_stacksave(0x04A8);
3086                 phy_stacksave(0x04AB);
3087                 if (phy->rev == 2) {
3088                         phy_stacksave(0x04AD);
3089                         phy_stacksave(0x04AE);
3090                 } else if (phy->rev >= 3) {
3091                         phy_stacksave(0x04AD);
3092                         phy_stacksave(0x0415);
3093                         phy_stacksave(0x0416);
3094                         phy_stacksave(0x0417);
3095                         ofdmtab_stacksave(0x1A00, 0x2);
3096                         ofdmtab_stacksave(0x1A00, 0x3);
3097                 }
3098                 phy_stacksave(0x042B);
3099                 phy_stacksave(0x048C);
3100
3101                 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3102                               b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3103                               & ~0x1000);
3104                 b43_phy_write(dev, B43_PHY_G_CRS,
3105                               (b43_phy_read(dev, B43_PHY_G_CRS)
3106                                & 0xFFFC) | 0x0002);
3107
3108                 b43_phy_write(dev, 0x0033, 0x0800);
3109                 b43_phy_write(dev, 0x04A3, 0x2027);
3110                 b43_phy_write(dev, 0x04A9, 0x1CA8);
3111                 b43_phy_write(dev, 0x0493, 0x287A);
3112                 b43_phy_write(dev, 0x04AA, 0x1CA8);
3113                 b43_phy_write(dev, 0x04AC, 0x287A);
3114
3115                 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3116                                             & 0xFFC0) | 0x001A);
3117                 b43_phy_write(dev, 0x04A7, 0x000D);
3118
3119                 if (phy->rev < 2) {
3120                         b43_phy_write(dev, 0x0406, 0xFF0D);
3121                 } else if (phy->rev == 2) {
3122                         b43_phy_write(dev, 0x04C0, 0xFFFF);
3123                         b43_phy_write(dev, 0x04C1, 0x00A9);
3124                 } else {
3125                         b43_phy_write(dev, 0x04C0, 0x00C1);
3126                         b43_phy_write(dev, 0x04C1, 0x0059);
3127                 }
3128
3129                 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3130                                             & 0xC0FF) | 0x1800);
3131                 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3132                                             & 0xFFC0) | 0x0015);
3133                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3134                                             & 0xCFFF) | 0x1000);
3135                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3136                                             & 0xF0FF) | 0x0A00);
3137                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3138                                             & 0xCFFF) | 0x1000);
3139                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3140                                             & 0xF0FF) | 0x0800);
3141                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3142                                             & 0xFFCF) | 0x0010);
3143                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3144                                             & 0xFFF0) | 0x0005);
3145                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3146                                             & 0xFFCF) | 0x0010);
3147                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3148                                             & 0xFFF0) | 0x0006);
3149                 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3150                                             & 0xF0FF) | 0x0800);
3151                 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3152                                             & 0xF0FF) | 0x0500);
3153                 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3154                                             & 0xFFF0) | 0x000B);
3155
3156                 if (phy->rev >= 3) {
3157                         b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3158                                       & ~0x8000);
3159                         b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
3160                                                     & 0x8000) | 0x36D8);
3161                         b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
3162                                                     & 0x8000) | 0x36D8);
3163                         b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
3164                                                     & 0xFE00) | 0x016D);
3165                 } else {
3166                         b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3167                                       | 0x1000);
3168                         b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
3169                                                     & 0x9FFF) | 0x2000);
3170                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
3171                 }
3172                 if (phy->rev >= 2) {
3173                         b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
3174                                       | 0x0800);
3175                 }
3176                 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
3177                                             & 0xF0FF) | 0x0200);
3178                 if (phy->rev == 2) {
3179                         b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
3180                                                     & 0xFF00) | 0x007F);
3181                         b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
3182                                                     & 0x00FF) | 0x1300);
3183                 } else if (phy->rev >= 6) {
3184                         b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
3185                         b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
3186                         b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
3187                                       & 0x00FF);
3188                 }
3189                 b43_calc_nrssi_slope(dev);
3190                 break;
3191         default:
3192                 B43_WARN_ON(1);
3193         }
3194 }
3195
3196 static void
3197 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
3198 {
3199         struct b43_phy *phy = &dev->phy;
3200         u32 *stack = phy->interfstack;
3201
3202         switch (mode) {
3203         case B43_INTERFMODE_NONWLAN:
3204                 if (phy->rev != 1) {
3205                         b43_phy_write(dev, 0x042B,
3206                                       b43_phy_read(dev, 0x042B) & ~0x0800);
3207                         b43_phy_write(dev, B43_PHY_G_CRS,
3208                                       b43_phy_read(dev,
3209                                                    B43_PHY_G_CRS) | 0x4000);
3210                         break;
3211                 }
3212                 radio_stackrestore(0x0078);
3213                 b43_calc_nrssi_threshold(dev);
3214                 phy_stackrestore(0x0406);
3215                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
3216                 if (!dev->bad_frames_preempt) {
3217                         b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3218                                       b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3219                                       & ~(1 << 11));
3220                 }
3221                 b43_phy_write(dev, B43_PHY_G_CRS,
3222                               b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
3223                 phy_stackrestore(0x04A0);
3224                 phy_stackrestore(0x04A1);
3225                 phy_stackrestore(0x04A2);
3226                 phy_stackrestore(0x04A8);
3227                 phy_stackrestore(0x04AB);
3228                 phy_stackrestore(0x04A7);
3229                 phy_stackrestore(0x04A3);
3230                 phy_stackrestore(0x04A9);
3231                 phy_stackrestore(0x0493);
3232                 phy_stackrestore(0x04AA);
3233                 phy_stackrestore(0x04AC);
3234                 break;
3235         case B43_INTERFMODE_MANUALWLAN:
3236                 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
3237                         break;
3238
3239                 phy->aci_enable = 0;
3240
3241                 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
3242                 phy_stackrestore(B43_PHY_G_CRS);
3243                 phy_stackrestore(0x0033);
3244                 phy_stackrestore(0x04A3);
3245                 phy_stackrestore(0x04A9);
3246                 phy_stackrestore(0x0493);
3247                 phy_stackrestore(0x04AA);
3248                 phy_stackrestore(0x04AC);
3249                 phy_stackrestore(0x04A0);
3250                 phy_stackrestore(0x04A7);
3251                 if (phy->rev >= 2) {
3252                         phy_stackrestore(0x04C0);
3253                         phy_stackrestore(0x04C1);
3254                 } else
3255                         phy_stackrestore(0x0406);
3256                 phy_stackrestore(0x04A1);
3257                 phy_stackrestore(0x04AB);
3258                 phy_stackrestore(0x04A8);
3259                 if (phy->rev == 2) {
3260                         phy_stackrestore(0x04AD);
3261                         phy_stackrestore(0x04AE);
3262                 } else if (phy->rev >= 3) {
3263                         phy_stackrestore(0x04AD);
3264                         phy_stackrestore(0x0415);
3265                         phy_stackrestore(0x0416);
3266                         phy_stackrestore(0x0417);
3267                         ofdmtab_stackrestore(0x1A00, 0x2);
3268                         ofdmtab_stackrestore(0x1A00, 0x3);
3269                 }
3270                 phy_stackrestore(0x04A2);
3271                 phy_stackrestore(0x048A);
3272                 phy_stackrestore(0x042B);
3273                 phy_stackrestore(0x048C);
3274                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
3275                 b43_calc_nrssi_slope(dev);
3276                 break;
3277         default:
3278                 B43_WARN_ON(1);
3279         }
3280 }
3281
3282 #undef phy_stacksave
3283 #undef phy_stackrestore
3284 #undef radio_stacksave
3285 #undef radio_stackrestore
3286 #undef ofdmtab_stacksave
3287 #undef ofdmtab_stackrestore
3288
3289 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode)
3290 {
3291         struct b43_phy *phy = &dev->phy;
3292         int currentmode;
3293
3294         if ((phy->type != B43_PHYTYPE_G) || (phy->rev == 0) || (!phy->gmode))
3295                 return -ENODEV;
3296
3297         phy->aci_wlan_automatic = 0;
3298         switch (mode) {
3299         case B43_INTERFMODE_AUTOWLAN:
3300                 phy->aci_wlan_automatic = 1;
3301                 if (phy->aci_enable)
3302                         mode = B43_INTERFMODE_MANUALWLAN;
3303                 else
3304                         mode = B43_INTERFMODE_NONE;
3305                 break;
3306         case B43_INTERFMODE_NONE:
3307         case B43_INTERFMODE_NONWLAN:
3308         case B43_INTERFMODE_MANUALWLAN:
3309                 break;
3310         default:
3311                 return -EINVAL;
3312         }
3313
3314         currentmode = phy->interfmode;
3315         if (currentmode == mode)
3316                 return 0;
3317         if (currentmode != B43_INTERFMODE_NONE)
3318                 b43_radio_interference_mitigation_disable(dev, currentmode);
3319
3320         if (mode == B43_INTERFMODE_NONE) {
3321                 phy->aci_enable = 0;
3322                 phy->aci_hw_rssi = 0;
3323         } else
3324                 b43_radio_interference_mitigation_enable(dev, mode);
3325         phy->interfmode = mode;
3326
3327         return 0;
3328 }
3329
3330 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
3331 {
3332         u16 reg, index, ret;
3333
3334         static const u8 rcc_table[] = {
3335                 0x02, 0x03, 0x01, 0x0F,
3336                 0x06, 0x07, 0x05, 0x0F,
3337                 0x0A, 0x0B, 0x09, 0x0F,
3338                 0x0E, 0x0F, 0x0D, 0x0F,
3339         };
3340
3341         reg = b43_radio_read16(dev, 0x60);
3342         index = (reg & 0x001E) >> 1;
3343         ret = rcc_table[index] << 1;
3344         ret |= (reg & 0x0001);
3345         ret |= 0x0020;
3346
3347         return ret;
3348 }
3349
3350 #define LPD(L, P, D)    (((L) << 2) | ((P) << 1) | ((D) << 0))
3351 static u16 radio2050_rfover_val(struct b43_wldev *dev,
3352                                 u16 phy_register, unsigned int lpd)
3353 {
3354         struct b43_phy *phy = &dev->phy;
3355         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
3356
3357         if (!phy->gmode)
3358                 return 0;
3359
3360         if (has_loopback_gain(phy)) {
3361                 int max_lb_gain = phy->max_lb_gain;
3362                 u16 extlna;
3363                 u16 i;
3364
3365                 if (phy->radio_rev == 8)
3366                         max_lb_gain += 0x3E;
3367                 else
3368                         max_lb_gain += 0x26;
3369                 if (max_lb_gain >= 0x46) {
3370                         extlna = 0x3000;
3371                         max_lb_gain -= 0x46;
3372                 } else if (max_lb_gain >= 0x3A) {
3373                         extlna = 0x1000;
3374                         max_lb_gain -= 0x3A;
3375                 } else if (max_lb_gain >= 0x2E) {
3376                         extlna = 0x2000;
3377                         max_lb_gain -= 0x2E;
3378                 } else {
3379                         extlna = 0;
3380                         max_lb_gain -= 0x10;
3381                 }
3382
3383                 for (i = 0; i < 16; i++) {
3384                         max_lb_gain -= (i * 6);
3385                         if (max_lb_gain < 6)
3386                                 break;
3387                 }
3388
3389                 if ((phy->rev < 7) ||
3390                     !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
3391                         if (phy_register == B43_PHY_RFOVER) {
3392                                 return 0x1B3;
3393                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3394                                 extlna |= (i << 8);
3395                                 switch (lpd) {
3396                                 case LPD(0, 1, 1):
3397                                         return 0x0F92;
3398                                 case LPD(0, 0, 1):
3399                                 case LPD(1, 0, 1):
3400                                         return (0x0092 | extlna);
3401                                 case LPD(1, 0, 0):
3402                                         return (0x0093 | extlna);
3403                                 }
3404                                 B43_WARN_ON(1);
3405                         }
3406                         B43_WARN_ON(1);
3407                 } else {
3408                         if (phy_register == B43_PHY_RFOVER) {
3409                                 return 0x9B3;
3410                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3411                                 if (extlna)
3412                                         extlna |= 0x8000;
3413                                 extlna |= (i << 8);
3414                                 switch (lpd) {
3415                                 case LPD(0, 1, 1):
3416                                         return 0x8F92;
3417                                 case LPD(0, 0, 1):
3418                                         return (0x8092 | extlna);
3419                                 case LPD(1, 0, 1):
3420                                         return (0x2092 | extlna);
3421                                 case LPD(1, 0, 0):
3422                                         return (0x2093 | extlna);
3423                                 }
3424                                 B43_WARN_ON(1);
3425                         }
3426                         B43_WARN_ON(1);
3427                 }
3428         } else {
3429                 if ((phy->rev < 7) ||
3430                     !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
3431                         if (phy_register == B43_PHY_RFOVER) {
3432                                 return 0x1B3;
3433                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3434                                 switch (lpd) {
3435                                 case LPD(0, 1, 1):
3436                                         return 0x0FB2;
3437                                 case LPD(0, 0, 1):
3438                                         return 0x00B2;
3439                                 case LPD(1, 0, 1):
3440                                         return 0x30B2;
3441                                 case LPD(1, 0, 0):
3442                                         return 0x30B3;
3443                                 }
3444                                 B43_WARN_ON(1);
3445                         }
3446                         B43_WARN_ON(1);
3447                 } else {
3448                         if (phy_register == B43_PHY_RFOVER) {
3449                                 return 0x9B3;
3450                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3451                                 switch (lpd) {
3452                                 case LPD(0, 1, 1):
3453                                         return 0x8FB2;
3454                                 case LPD(0, 0, 1):
3455                                         return 0x80B2;
3456                                 case LPD(1, 0, 1):
3457                                         return 0x20B2;
3458                                 case LPD(1, 0, 0):
3459                                         return 0x20B3;
3460                                 }
3461                                 B43_WARN_ON(1);
3462                         }
3463                         B43_WARN_ON(1);
3464                 }
3465         }
3466         return 0;
3467 }
3468
3469 struct init2050_saved_values {
3470         /* Core registers */
3471         u16 reg_3EC;
3472         u16 reg_3E6;
3473         u16 reg_3F4;
3474         /* Radio registers */
3475         u16 radio_43;
3476         u16 radio_51;
3477         u16 radio_52;
3478         /* PHY registers */
3479         u16 phy_pgactl;
3480         u16 phy_base_5A;
3481         u16 phy_base_59;
3482         u16 phy_base_58;
3483         u16 phy_base_30;
3484         u16 phy_rfover;
3485         u16 phy_rfoverval;
3486         u16 phy_analogover;
3487         u16 phy_analogoverval;
3488         u16 phy_crs0;
3489         u16 phy_classctl;
3490         u16 phy_lo_mask;
3491         u16 phy_lo_ctl;
3492         u16 phy_syncctl;
3493 };
3494
3495 u16 b43_radio_init2050(struct b43_wldev *dev)
3496 {
3497         struct b43_phy *phy = &dev->phy;
3498         struct init2050_saved_values sav;
3499         u16 rcc;
3500         u16 radio78;
3501         u16 ret;
3502         u16 i, j;
3503         u32 tmp1 = 0, tmp2 = 0;
3504
3505         memset(&sav, 0, sizeof(sav));   /* get rid of "may be used uninitialized..." */
3506
3507         sav.radio_43 = b43_radio_read16(dev, 0x43);
3508         sav.radio_51 = b43_radio_read16(dev, 0x51);
3509         sav.radio_52 = b43_radio_read16(dev, 0x52);
3510         sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
3511         sav.phy_base_5A = b43_phy_read(dev, B43_PHY_BASE(0x5A));
3512         sav.phy_base_59 = b43_phy_read(dev, B43_PHY_BASE(0x59));
3513         sav.phy_base_58 = b43_phy_read(dev, B43_PHY_BASE(0x58));
3514
3515         if (phy->type == B43_PHYTYPE_B) {
3516                 sav.phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30));
3517                 sav.reg_3EC = b43_read16(dev, 0x3EC);
3518
3519                 b43_phy_write(dev, B43_PHY_BASE(0x30), 0xFF);
3520                 b43_write16(dev, 0x3EC, 0x3F3F);
3521         } else if (phy->gmode || phy->rev >= 2) {
3522                 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
3523                 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
3524                 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
3525                 sav.phy_analogoverval =
3526                     b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
3527                 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
3528                 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
3529
3530                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
3531                               b43_phy_read(dev, B43_PHY_ANALOGOVER)
3532                               | 0x0003);
3533                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3534                               b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
3535                               & 0xFFFC);
3536                 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
3537                               & 0x7FFF);
3538                 b43_phy_write(dev, B43_PHY_CLASSCTL,
3539                               b43_phy_read(dev, B43_PHY_CLASSCTL)
3540                               & 0xFFFC);
3541                 if (has_loopback_gain(phy)) {
3542                         sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
3543                         sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
3544
3545                         if (phy->rev >= 3)
3546                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
3547                         else
3548                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
3549                         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
3550                 }
3551
3552                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3553                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3554                                                    LPD(0, 1, 1)));
3555                 b43_phy_write(dev, B43_PHY_RFOVER,
3556                               radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
3557         }
3558         b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
3559
3560         sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
3561         b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
3562                       & 0xFF7F);
3563         sav.reg_3E6 = b43_read16(dev, 0x3E6);
3564         sav.reg_3F4 = b43_read16(dev, 0x3F4);
3565
3566         if (phy->analog == 0) {
3567                 b43_write16(dev, 0x03E6, 0x0122);
3568         } else {
3569                 if (phy->analog >= 2) {
3570                         b43_phy_write(dev, B43_PHY_BASE(0x03),
3571                                       (b43_phy_read(dev, B43_PHY_BASE(0x03))
3572                                        & 0xFFBF) | 0x40);
3573                 }
3574                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3575                             (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
3576         }
3577
3578         rcc = b43_radio_core_calibration_value(dev);
3579
3580         if (phy->type == B43_PHYTYPE_B)
3581                 b43_radio_write16(dev, 0x78, 0x26);
3582         if (phy->gmode || phy->rev >= 2) {
3583                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3584                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3585                                                    LPD(0, 1, 1)));
3586         }
3587         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
3588         b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1403);
3589         if (phy->gmode || phy->rev >= 2) {
3590                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3591                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3592                                                    LPD(0, 0, 1)));
3593         }
3594         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
3595         b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
3596                           | 0x0004);
3597         if (phy->radio_rev == 8) {
3598                 b43_radio_write16(dev, 0x43, 0x1F);
3599         } else {
3600                 b43_radio_write16(dev, 0x52, 0);
3601                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
3602                                               & 0xFFF0) | 0x0009);
3603         }
3604         b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3605
3606         for (i = 0; i < 16; i++) {
3607                 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0480);
3608                 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
3609                 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
3610                 if (phy->gmode || phy->rev >= 2) {
3611                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3612                                       radio2050_rfover_val(dev,
3613                                                            B43_PHY_RFOVERVAL,
3614                                                            LPD(1, 0, 1)));
3615                 }
3616                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3617                 udelay(10);
3618                 if (phy->gmode || phy->rev >= 2) {
3619                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3620                                       radio2050_rfover_val(dev,
3621                                                            B43_PHY_RFOVERVAL,
3622                                                            LPD(1, 0, 1)));
3623                 }
3624                 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3625                 udelay(10);
3626                 if (phy->gmode || phy->rev >= 2) {
3627                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3628                                       radio2050_rfover_val(dev,
3629                                                            B43_PHY_RFOVERVAL,
3630                                                            LPD(1, 0, 0)));
3631                 }
3632                 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3633                 udelay(20);
3634                 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3635                 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3636                 if (phy->gmode || phy->rev >= 2) {
3637                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3638                                       radio2050_rfover_val(dev,
3639                                                            B43_PHY_RFOVERVAL,
3640                                                            LPD(1, 0, 1)));
3641                 }
3642                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3643         }
3644         udelay(10);
3645
3646         b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3647         tmp1++;
3648         tmp1 >>= 9;
3649
3650         for (i = 0; i < 16; i++) {
3651                 radio78 = ((flip_4bit(i) << 1) | 0x20);
3652                 b43_radio_write16(dev, 0x78, radio78);
3653                 udelay(10);
3654                 for (j = 0; j < 16; j++) {
3655                         b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0D80);
3656                         b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
3657                         b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
3658                         if (phy->gmode || phy->rev >= 2) {
3659                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3660                                               radio2050_rfover_val(dev,
3661                                                                    B43_PHY_RFOVERVAL,
3662                                                                    LPD(1, 0,
3663                                                                        1)));
3664                         }
3665                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3666                         udelay(10);
3667                         if (phy->gmode || phy->rev >= 2) {
3668                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3669                                               radio2050_rfover_val(dev,
3670                                                                    B43_PHY_RFOVERVAL,
3671                                                                    LPD(1, 0,
3672                                                                        1)));
3673                         }
3674                         b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3675                         udelay(10);
3676                         if (phy->gmode || phy->rev >= 2) {
3677                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3678                                               radio2050_rfover_val(dev,
3679                                                                    B43_PHY_RFOVERVAL,
3680                                                                    LPD(1, 0,
3681                                                                        0)));
3682                         }
3683                         b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3684                         udelay(10);
3685                         tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3686                         b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3687                         if (phy->gmode || phy->rev >= 2) {
3688                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3689                                               radio2050_rfover_val(dev,
3690                                                                    B43_PHY_RFOVERVAL,
3691                                                                    LPD(1, 0,
3692                                                                        1)));
3693                         }
3694                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3695                 }
3696                 tmp2++;
3697                 tmp2 >>= 8;
3698                 if (tmp1 < tmp2)
3699                         break;
3700         }
3701
3702         /* Restore the registers */
3703         b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
3704         b43_radio_write16(dev, 0x51, sav.radio_51);
3705         b43_radio_write16(dev, 0x52, sav.radio_52);
3706         b43_radio_write16(dev, 0x43, sav.radio_43);
3707         b43_phy_write(dev, B43_PHY_BASE(0x5A), sav.phy_base_5A);
3708         b43_phy_write(dev, B43_PHY_BASE(0x59), sav.phy_base_59);
3709         b43_phy_write(dev, B43_PHY_BASE(0x58), sav.phy_base_58);
3710         b43_write16(dev, 0x3E6, sav.reg_3E6);
3711         if (phy->analog != 0)
3712                 b43_write16(dev, 0x3F4, sav.reg_3F4);
3713         b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
3714         b43_synth_pu_workaround(dev, phy->channel);
3715         if (phy->type == B43_PHYTYPE_B) {
3716                 b43_phy_write(dev, B43_PHY_BASE(0x30), sav.phy_base_30);
3717                 b43_write16(dev, 0x3EC, sav.reg_3EC);
3718         } else if (phy->gmode) {
3719                 b43_write16(dev, B43_MMIO_PHY_RADIO,
3720                             b43_read16(dev, B43_MMIO_PHY_RADIO)
3721                             & 0x7FFF);
3722                 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
3723                 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
3724                 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
3725                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3726                               sav.phy_analogoverval);
3727                 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
3728                 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
3729                 if (has_loopback_gain(phy)) {
3730                         b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
3731                         b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
3732                 }
3733         }
3734         if (i > 15)
3735                 ret = radio78;
3736         else
3737                 ret = rcc;
3738
3739         return ret;
3740 }
3741
3742 void b43_radio_init2060(struct b43_wldev *dev)
3743 {
3744         int err;
3745
3746         b43_radio_write16(dev, 0x0004, 0x00C0);
3747         b43_radio_write16(dev, 0x0005, 0x0008);
3748         b43_radio_write16(dev, 0x0009, 0x0040);
3749         b43_radio_write16(dev, 0x0005, 0x00AA);
3750         b43_radio_write16(dev, 0x0032, 0x008F);
3751         b43_radio_write16(dev, 0x0006, 0x008F);
3752         b43_radio_write16(dev, 0x0034, 0x008F);
3753         b43_radio_write16(dev, 0x002C, 0x0007);
3754         b43_radio_write16(dev, 0x0082, 0x0080);
3755         b43_radio_write16(dev, 0x0080, 0x0000);
3756         b43_radio_write16(dev, 0x003F, 0x00DA);
3757         b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
3758         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
3759         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
3760         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
3761         msleep(1);              /* delay 400usec */
3762
3763         b43_radio_write16(dev, 0x0081,
3764                           (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
3765         msleep(1);              /* delay 400usec */
3766
3767         b43_radio_write16(dev, 0x0005,
3768                           (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
3769         b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
3770         b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
3771         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
3772         b43_radio_write16(dev, 0x0081,
3773                           (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
3774         b43_radio_write16(dev, 0x0005,
3775                           (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
3776         b43_phy_write(dev, 0x0063, 0xDDC6);
3777         b43_phy_write(dev, 0x0069, 0x07BE);
3778         b43_phy_write(dev, 0x006A, 0x0000);
3779
3780         err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_A, 0);
3781         B43_WARN_ON(err);
3782
3783         msleep(1);
3784 }
3785
3786 static inline u16 freq_r3A_value(u16 frequency)
3787 {
3788         u16 value;
3789
3790         if (frequency < 5091)
3791                 value = 0x0040;
3792         else if (frequency < 5321)
3793                 value = 0x0000;
3794         else if (frequency < 5806)
3795                 value = 0x0080;
3796         else
3797                 value = 0x0040;
3798
3799         return value;
3800 }
3801
3802 void b43_radio_set_tx_iq(struct b43_wldev *dev)
3803 {
3804         static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
3805         static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
3806         u16 tmp = b43_radio_read16(dev, 0x001E);
3807         int i, j;
3808
3809         for (i = 0; i < 5; i++) {
3810                 for (j = 0; j < 5; j++) {
3811                         if (tmp == (data_high[i] << 4 | data_low[j])) {
3812                                 b43_phy_write(dev, 0x0069,
3813                                               (i - j) << 8 | 0x00C0);
3814                                 return;
3815                         }
3816                 }
3817         }
3818 }
3819
3820 int b43_radio_selectchannel(struct b43_wldev *dev,
3821                             u8 channel, int synthetic_pu_workaround)
3822 {
3823         struct b43_phy *phy = &dev->phy;
3824         u16 r8, tmp;
3825         u16 freq;
3826         u16 channelcookie;
3827
3828         if (channel == 0xFF) {
3829                 switch (phy->type) {
3830                 case B43_PHYTYPE_A:
3831                         channel = B43_DEFAULT_CHANNEL_A;
3832                         break;
3833                 case B43_PHYTYPE_B:
3834                 case B43_PHYTYPE_G:
3835                         channel = B43_DEFAULT_CHANNEL_BG;
3836                         break;
3837                 default:
3838                         B43_WARN_ON(1);
3839                 }
3840         }
3841
3842         /* First we set the channel radio code to prevent the
3843          * firmware from sending ghost packets.
3844          */
3845         channelcookie = channel;
3846         if (phy->type == B43_PHYTYPE_A)
3847                 channelcookie |= 0x100;
3848         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
3849
3850         if (phy->type == B43_PHYTYPE_A) {
3851                 if (channel > 200)
3852                         return -EINVAL;
3853                 freq = channel2freq_a(channel);
3854
3855                 r8 = b43_radio_read16(dev, 0x0008);
3856                 b43_write16(dev, 0x03F0, freq);
3857                 b43_radio_write16(dev, 0x0008, r8);
3858
3859                 //TODO: write max channel TX power? to Radio 0x2D
3860                 tmp = b43_radio_read16(dev, 0x002E);
3861                 tmp &= 0x0080;
3862                 //TODO: OR tmp with the Power out estimation for this channel?
3863                 b43_radio_write16(dev, 0x002E, tmp);
3864
3865                 if (freq >= 4920 && freq <= 5500) {
3866                         /*
3867                          * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
3868                          *    = (freq * 0.025862069
3869                          */
3870                         r8 = 3 * freq / 116;    /* is equal to r8 = freq * 0.025862 */
3871                 }
3872                 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
3873                 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
3874                 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
3875                 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
3876                                                 & 0x000F) | (r8 << 4));
3877                 b43_radio_write16(dev, 0x002A, (r8 << 4));
3878                 b43_radio_write16(dev, 0x002B, (r8 << 4));
3879                 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
3880                                                 & 0x00F0) | (r8 << 4));
3881                 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
3882                                                 & 0xFF0F) | 0x00B0);
3883                 b43_radio_write16(dev, 0x0035, 0x00AA);
3884                 b43_radio_write16(dev, 0x0036, 0x0085);
3885                 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
3886                                                 & 0xFF20) |
3887                                   freq_r3A_value(freq));
3888                 b43_radio_write16(dev, 0x003D,
3889                                   b43_radio_read16(dev, 0x003D) & 0x00FF);
3890                 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
3891                                                 & 0xFF7F) | 0x0080);
3892                 b43_radio_write16(dev, 0x0035,
3893                                   b43_radio_read16(dev, 0x0035) & 0xFFEF);
3894                 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
3895                                                 & 0xFFEF) | 0x0010);
3896                 b43_radio_set_tx_iq(dev);
3897                 //TODO: TSSI2dbm workaround
3898                 b43_phy_xmitpower(dev); //FIXME correct?
3899         } else {
3900                 if ((channel < 1) || (channel > 14))
3901                         return -EINVAL;
3902
3903                 if (synthetic_pu_workaround)
3904                         b43_synth_pu_workaround(dev, channel);
3905
3906                 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
3907
3908                 if (channel == 14) {
3909                         if (dev->dev->bus->sprom.r1.country_code ==
3910                             SSB_SPROM1CCODE_JAPAN)
3911                                 b43_hf_write(dev,
3912                                              b43_hf_read(dev) & ~B43_HF_ACPR);
3913                         else
3914                                 b43_hf_write(dev,
3915                                              b43_hf_read(dev) | B43_HF_ACPR);
3916                         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3917                                     b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3918                                     | (1 << 11));
3919                 } else {
3920                         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3921                                     b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3922                                     & 0xF7BF);
3923                 }
3924         }
3925
3926         phy->channel = channel;
3927         /* Wait for the radio to tune to the channel and stabilize. */
3928         msleep(8);
3929
3930         return 0;
3931 }
3932
3933 void b43_radio_turn_on(struct b43_wldev *dev)
3934 {
3935         struct b43_phy *phy = &dev->phy;
3936         int err;
3937         u8 channel;
3938
3939         might_sleep();
3940
3941         if (phy->radio_on)
3942                 return;
3943
3944         switch (phy->type) {
3945         case B43_PHYTYPE_A:
3946                 b43_radio_write16(dev, 0x0004, 0x00C0);
3947                 b43_radio_write16(dev, 0x0005, 0x0008);
3948                 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) & 0xFFF7);
3949                 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) & 0xFFF7);
3950                 b43_radio_init2060(dev);
3951                 break;
3952         case B43_PHYTYPE_B:
3953         case B43_PHYTYPE_G:
3954                 b43_phy_write(dev, 0x0015, 0x8000);
3955                 b43_phy_write(dev, 0x0015, 0xCC00);
3956                 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
3957                 if (phy->radio_off_context.valid) {
3958                         /* Restore the RFover values. */
3959                         b43_phy_write(dev, B43_PHY_RFOVER,
3960                                       phy->radio_off_context.rfover);
3961                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3962                                       phy->radio_off_context.rfoverval);
3963                         phy->radio_off_context.valid = 0;
3964                 }
3965                 channel = phy->channel;
3966                 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 1);
3967                 err |= b43_radio_selectchannel(dev, channel, 0);
3968                 B43_WARN_ON(err);
3969                 break;
3970         default:
3971                 B43_WARN_ON(1);
3972         }
3973         phy->radio_on = 1;
3974 }
3975
3976 void b43_radio_turn_off(struct b43_wldev *dev, bool force)
3977 {
3978         struct b43_phy *phy = &dev->phy;
3979
3980         if (!phy->radio_on && !force)
3981                 return;
3982
3983         if (phy->type == B43_PHYTYPE_A) {
3984                 b43_radio_write16(dev, 0x0004, 0x00FF);
3985                 b43_radio_write16(dev, 0x0005, 0x00FB);
3986                 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
3987                 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
3988         }
3989         if (phy->type == B43_PHYTYPE_G && dev->dev->id.revision >= 5) {
3990                 u16 rfover, rfoverval;
3991
3992                 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
3993                 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
3994                 if (!force) {
3995                         phy->radio_off_context.rfover = rfover;
3996                         phy->radio_off_context.rfoverval = rfoverval;
3997                         phy->radio_off_context.valid = 1;
3998                 }
3999                 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
4000                 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
4001         } else
4002                 b43_phy_write(dev, 0x0015, 0xAA00);
4003         phy->radio_on = 0;
4004 }