3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
55 MODULE_AUTHOR("Martin Langer");
56 MODULE_AUTHOR("Stefano Brivio");
57 MODULE_AUTHOR("Michael Buesch");
58 MODULE_LICENSE("GPL");
61 static int modparam_bad_frames_preempt;
62 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
63 MODULE_PARM_DESC(bad_frames_preempt,
64 "enable(1) / disable(0) Bad Frames Preemption");
66 static char modparam_fwpostfix[16];
67 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
68 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
70 static int modparam_hwpctl;
71 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
72 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
74 static int modparam_nohwcrypt;
75 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
78 static const struct ssb_device_id b43_ssb_tbl[] = {
79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
88 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
90 /* Channel and ratetables are shared for all devices.
91 * They can't be const, because ieee80211 puts some precalculated
92 * data in there. This data is the same for all devices, so we don't
93 * get concurrency issues */
94 #define RATETAB_ENT(_rateid, _flags) \
96 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
101 static struct ieee80211_rate __b43_ratetable[] = {
102 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
103 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
104 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
105 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
106 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
107 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
108 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
109 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
110 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
111 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
112 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
113 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
116 #define b43_a_ratetable (__b43_ratetable + 4)
117 #define b43_a_ratetable_size 8
118 #define b43_b_ratetable (__b43_ratetable + 0)
119 #define b43_b_ratetable_size 4
120 #define b43_g_ratetable (__b43_ratetable + 0)
121 #define b43_g_ratetable_size 12
123 #define CHANTAB_ENT(_chanid, _freq) \
128 .flag = IEEE80211_CHAN_W_SCAN | \
129 IEEE80211_CHAN_W_ACTIVE_SCAN | \
130 IEEE80211_CHAN_W_IBSS, \
131 .power_level = 0xFF, \
132 .antenna_max = 0xFF, \
134 static struct ieee80211_channel b43_bg_chantable[] = {
135 CHANTAB_ENT(1, 2412),
136 CHANTAB_ENT(2, 2417),
137 CHANTAB_ENT(3, 2422),
138 CHANTAB_ENT(4, 2427),
139 CHANTAB_ENT(5, 2432),
140 CHANTAB_ENT(6, 2437),
141 CHANTAB_ENT(7, 2442),
142 CHANTAB_ENT(8, 2447),
143 CHANTAB_ENT(9, 2452),
144 CHANTAB_ENT(10, 2457),
145 CHANTAB_ENT(11, 2462),
146 CHANTAB_ENT(12, 2467),
147 CHANTAB_ENT(13, 2472),
148 CHANTAB_ENT(14, 2484),
151 #define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable)
152 static struct ieee80211_channel b43_a_chantable[] = {
153 CHANTAB_ENT(36, 5180),
154 CHANTAB_ENT(40, 5200),
155 CHANTAB_ENT(44, 5220),
156 CHANTAB_ENT(48, 5240),
157 CHANTAB_ENT(52, 5260),
158 CHANTAB_ENT(56, 5280),
159 CHANTAB_ENT(60, 5300),
160 CHANTAB_ENT(64, 5320),
161 CHANTAB_ENT(149, 5745),
162 CHANTAB_ENT(153, 5765),
163 CHANTAB_ENT(157, 5785),
164 CHANTAB_ENT(161, 5805),
165 CHANTAB_ENT(165, 5825),
168 #define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable)
170 static void b43_wireless_core_exit(struct b43_wldev *dev);
171 static int b43_wireless_core_init(struct b43_wldev *dev);
172 static void b43_wireless_core_stop(struct b43_wldev *dev);
173 static int b43_wireless_core_start(struct b43_wldev *dev);
175 static int b43_ratelimit(struct b43_wl *wl)
177 if (!wl || !wl->current_dev)
179 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
181 /* We are up and running.
182 * Ratelimit the messages to avoid DoS over the net. */
183 return net_ratelimit();
186 void b43info(struct b43_wl *wl, const char *fmt, ...)
190 if (!b43_ratelimit(wl))
193 printk(KERN_INFO "b43-%s: ",
194 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
199 void b43err(struct b43_wl *wl, const char *fmt, ...)
203 if (!b43_ratelimit(wl))
206 printk(KERN_ERR "b43-%s ERROR: ",
207 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
212 void b43warn(struct b43_wl *wl, const char *fmt, ...)
216 if (!b43_ratelimit(wl))
219 printk(KERN_WARNING "b43-%s warning: ",
220 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
226 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
231 printk(KERN_DEBUG "b43-%s debug: ",
232 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
238 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
242 B43_WARN_ON(offset % 4 != 0);
244 macctl = b43_read32(dev, B43_MMIO_MACCTL);
245 if (macctl & B43_MACCTL_BE)
248 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
250 b43_write32(dev, B43_MMIO_RAM_DATA, val);
254 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
258 /* "offset" is the WORD offset. */
263 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
266 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
270 if (routing == B43_SHM_SHARED) {
271 B43_WARN_ON(offset & 0x0001);
272 if (offset & 0x0003) {
273 /* Unaligned access */
274 b43_shm_control_word(dev, routing, offset >> 2);
275 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
277 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
278 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
284 b43_shm_control_word(dev, routing, offset);
285 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
290 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
294 if (routing == B43_SHM_SHARED) {
295 B43_WARN_ON(offset & 0x0001);
296 if (offset & 0x0003) {
297 /* Unaligned access */
298 b43_shm_control_word(dev, routing, offset >> 2);
299 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
305 b43_shm_control_word(dev, routing, offset);
306 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
311 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
313 if (routing == B43_SHM_SHARED) {
314 B43_WARN_ON(offset & 0x0001);
315 if (offset & 0x0003) {
316 /* Unaligned access */
317 b43_shm_control_word(dev, routing, offset >> 2);
319 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
320 (value >> 16) & 0xffff);
322 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
324 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
329 b43_shm_control_word(dev, routing, offset);
331 b43_write32(dev, B43_MMIO_SHM_DATA, value);
334 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
336 if (routing == B43_SHM_SHARED) {
337 B43_WARN_ON(offset & 0x0001);
338 if (offset & 0x0003) {
339 /* Unaligned access */
340 b43_shm_control_word(dev, routing, offset >> 2);
342 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
347 b43_shm_control_word(dev, routing, offset);
349 b43_write16(dev, B43_MMIO_SHM_DATA, value);
353 u32 b43_hf_read(struct b43_wldev * dev)
357 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
359 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
364 /* Write HostFlags */
365 void b43_hf_write(struct b43_wldev *dev, u32 value)
367 b43_shm_write16(dev, B43_SHM_SHARED,
368 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
369 b43_shm_write16(dev, B43_SHM_SHARED,
370 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
373 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
375 /* We need to be careful. As we read the TSF from multiple
376 * registers, we should take care of register overflows.
377 * In theory, the whole tsf read process should be atomic.
378 * We try to be atomic here, by restaring the read process,
379 * if any of the high registers changed (overflew).
381 if (dev->dev->id.revision >= 3) {
382 u32 low, high, high2;
385 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
386 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
387 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
388 } while (unlikely(high != high2));
396 u16 test1, test2, test3;
399 v3 = b43_read16(dev, B43_MMIO_TSF_3);
400 v2 = b43_read16(dev, B43_MMIO_TSF_2);
401 v1 = b43_read16(dev, B43_MMIO_TSF_1);
402 v0 = b43_read16(dev, B43_MMIO_TSF_0);
404 test3 = b43_read16(dev, B43_MMIO_TSF_3);
405 test2 = b43_read16(dev, B43_MMIO_TSF_2);
406 test1 = b43_read16(dev, B43_MMIO_TSF_1);
407 } while (v3 != test3 || v2 != test2 || v1 != test1);
421 static void b43_time_lock(struct b43_wldev *dev)
425 macctl = b43_read32(dev, B43_MMIO_MACCTL);
426 macctl |= B43_MACCTL_TBTTHOLD;
427 b43_write32(dev, B43_MMIO_MACCTL, macctl);
428 /* Commit the write */
429 b43_read32(dev, B43_MMIO_MACCTL);
432 static void b43_time_unlock(struct b43_wldev *dev)
436 macctl = b43_read32(dev, B43_MMIO_MACCTL);
437 macctl &= ~B43_MACCTL_TBTTHOLD;
438 b43_write32(dev, B43_MMIO_MACCTL, macctl);
439 /* Commit the write */
440 b43_read32(dev, B43_MMIO_MACCTL);
443 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
445 /* Be careful with the in-progress timer.
446 * First zero out the low register, so we have a full
447 * register-overflow duration to complete the operation.
449 if (dev->dev->id.revision >= 3) {
450 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
451 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
453 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
455 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
457 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
459 u16 v0 = (tsf & 0x000000000000FFFFULL);
460 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
461 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
462 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
464 b43_write16(dev, B43_MMIO_TSF_0, 0);
466 b43_write16(dev, B43_MMIO_TSF_3, v3);
468 b43_write16(dev, B43_MMIO_TSF_2, v2);
470 b43_write16(dev, B43_MMIO_TSF_1, v1);
472 b43_write16(dev, B43_MMIO_TSF_0, v0);
476 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
479 b43_tsf_write_locked(dev, tsf);
480 b43_time_unlock(dev);
484 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
486 static const u8 zero_addr[ETH_ALEN] = { 0 };
493 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
497 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
500 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
503 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
506 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
510 u8 mac_bssid[ETH_ALEN * 2];
514 bssid = dev->wl->bssid;
515 mac = dev->wl->mac_addr;
517 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
519 memcpy(mac_bssid, mac, ETH_ALEN);
520 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
522 /* Write our MAC address and BSSID to template ram */
523 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
524 tmp = (u32) (mac_bssid[i + 0]);
525 tmp |= (u32) (mac_bssid[i + 1]) << 8;
526 tmp |= (u32) (mac_bssid[i + 2]) << 16;
527 tmp |= (u32) (mac_bssid[i + 3]) << 24;
528 b43_ram_write(dev, 0x20 + i, tmp);
532 static void b43_upload_card_macaddress(struct b43_wldev *dev)
534 b43_write_mac_bssid_templates(dev);
535 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
538 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
540 /* slot_time is in usec. */
541 if (dev->phy.type != B43_PHYTYPE_G)
543 b43_write16(dev, 0x684, 510 + slot_time);
544 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
547 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
549 b43_set_slot_time(dev, 9);
553 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
555 b43_set_slot_time(dev, 20);
559 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
560 * Returns the _previously_ enabled IRQ mask.
562 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
566 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
567 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
572 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
573 * Returns the _previously_ enabled IRQ mask.
575 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
579 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
580 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
585 /* Synchronize IRQ top- and bottom-half.
586 * IRQs must be masked before calling this.
587 * This must not be called with the irq_lock held.
589 static void b43_synchronize_irq(struct b43_wldev *dev)
591 synchronize_irq(dev->dev->irq);
592 tasklet_kill(&dev->isr_tasklet);
595 /* DummyTransmission function, as documented on
596 * http://bcm-specs.sipsolutions.net/DummyTransmission
598 void b43_dummy_transmission(struct b43_wldev *dev)
600 struct b43_phy *phy = &dev->phy;
601 unsigned int i, max_loop;
614 buffer[0] = 0x000201CC;
619 buffer[0] = 0x000B846E;
626 for (i = 0; i < 5; i++)
627 b43_ram_write(dev, i * 4, buffer[i]);
630 b43_read32(dev, B43_MMIO_MACCTL);
632 b43_write16(dev, 0x0568, 0x0000);
633 b43_write16(dev, 0x07C0, 0x0000);
634 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
635 b43_write16(dev, 0x050C, value);
636 b43_write16(dev, 0x0508, 0x0000);
637 b43_write16(dev, 0x050A, 0x0000);
638 b43_write16(dev, 0x054C, 0x0000);
639 b43_write16(dev, 0x056A, 0x0014);
640 b43_write16(dev, 0x0568, 0x0826);
641 b43_write16(dev, 0x0500, 0x0000);
642 b43_write16(dev, 0x0502, 0x0030);
644 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
645 b43_radio_write16(dev, 0x0051, 0x0017);
646 for (i = 0x00; i < max_loop; i++) {
647 value = b43_read16(dev, 0x050E);
652 for (i = 0x00; i < 0x0A; i++) {
653 value = b43_read16(dev, 0x050E);
658 for (i = 0x00; i < 0x0A; i++) {
659 value = b43_read16(dev, 0x0690);
660 if (!(value & 0x0100))
664 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
665 b43_radio_write16(dev, 0x0051, 0x0037);
668 static void key_write(struct b43_wldev *dev,
669 u8 index, u8 algorithm, const u8 * key)
676 /* Key index/algo block */
677 kidx = b43_kidx_to_fw(dev, index);
678 value = ((kidx << 4) | algorithm);
679 b43_shm_write16(dev, B43_SHM_SHARED,
680 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
682 /* Write the key to the Key Table Pointer offset */
683 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
684 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
686 value |= (u16) (key[i + 1]) << 8;
687 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
691 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
693 u32 addrtmp[2] = { 0, 0, };
694 u8 per_sta_keys_start = 8;
696 if (b43_new_kidx_api(dev))
697 per_sta_keys_start = 4;
699 B43_WARN_ON(index < per_sta_keys_start);
700 /* We have two default TX keys and possibly two default RX keys.
701 * Physical mac 0 is mapped to physical key 4 or 8, depending
702 * on the firmware version.
703 * So we must adjust the index here.
705 index -= per_sta_keys_start;
708 addrtmp[0] = addr[0];
709 addrtmp[0] |= ((u32) (addr[1]) << 8);
710 addrtmp[0] |= ((u32) (addr[2]) << 16);
711 addrtmp[0] |= ((u32) (addr[3]) << 24);
712 addrtmp[1] = addr[4];
713 addrtmp[1] |= ((u32) (addr[5]) << 8);
716 if (dev->dev->id.revision >= 5) {
717 /* Receive match transmitter address mechanism */
718 b43_shm_write32(dev, B43_SHM_RCMTA,
719 (index * 2) + 0, addrtmp[0]);
720 b43_shm_write16(dev, B43_SHM_RCMTA,
721 (index * 2) + 1, addrtmp[1]);
723 /* RXE (Receive Engine) and
724 * PSM (Programmable State Machine) mechanism
727 /* TODO write to RCM 16, 19, 22 and 25 */
729 b43_shm_write32(dev, B43_SHM_SHARED,
730 B43_SHM_SH_PSM + (index * 6) + 0,
732 b43_shm_write16(dev, B43_SHM_SHARED,
733 B43_SHM_SH_PSM + (index * 6) + 4,
739 static void do_key_write(struct b43_wldev *dev,
740 u8 index, u8 algorithm,
741 const u8 * key, size_t key_len, const u8 * mac_addr)
743 u8 buf[B43_SEC_KEYSIZE] = { 0, };
744 u8 per_sta_keys_start = 8;
746 if (b43_new_kidx_api(dev))
747 per_sta_keys_start = 4;
749 B43_WARN_ON(index >= dev->max_nr_keys);
750 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
752 if (index >= per_sta_keys_start)
753 keymac_write(dev, index, NULL); /* First zero out mac. */
755 memcpy(buf, key, key_len);
756 key_write(dev, index, algorithm, buf);
757 if (index >= per_sta_keys_start)
758 keymac_write(dev, index, mac_addr);
760 dev->key[index].algorithm = algorithm;
763 static int b43_key_write(struct b43_wldev *dev,
764 int index, u8 algorithm,
765 const u8 * key, size_t key_len,
767 struct ieee80211_key_conf *keyconf)
772 if (key_len > B43_SEC_KEYSIZE)
774 for (i = 0; i < dev->max_nr_keys; i++) {
775 /* Check that we don't already have this key. */
776 B43_WARN_ON(dev->key[i].keyconf == keyconf);
779 /* Either pairwise key or address is 00:00:00:00:00:00
780 * for transmit-only keys. Search the index. */
781 if (b43_new_kidx_api(dev))
785 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
786 if (!dev->key[i].keyconf) {
793 b43err(dev->wl, "Out of hardware key memory\n");
797 B43_WARN_ON(index > 3);
799 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
800 if ((index <= 3) && !b43_new_kidx_api(dev)) {
802 B43_WARN_ON(mac_addr);
803 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
805 keyconf->hw_key_idx = index;
806 dev->key[index].keyconf = keyconf;
811 static int b43_key_clear(struct b43_wldev *dev, int index)
813 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
815 do_key_write(dev, index, B43_SEC_ALGO_NONE,
816 NULL, B43_SEC_KEYSIZE, NULL);
817 if ((index <= 3) && !b43_new_kidx_api(dev)) {
818 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
819 NULL, B43_SEC_KEYSIZE, NULL);
821 dev->key[index].keyconf = NULL;
826 static void b43_clear_keys(struct b43_wldev *dev)
830 for (i = 0; i < dev->max_nr_keys; i++)
831 b43_key_clear(dev, i);
834 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
842 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
843 (ps_flags & B43_PS_DISABLED));
844 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
846 if (ps_flags & B43_PS_ENABLED) {
848 } else if (ps_flags & B43_PS_DISABLED) {
851 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
852 // and thus is not an AP and we are associated, set bit 25
854 if (ps_flags & B43_PS_AWAKE) {
856 } else if (ps_flags & B43_PS_ASLEEP) {
859 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
860 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
861 // successful, set bit26
864 /* FIXME: For now we force awake-on and hwps-off */
868 macctl = b43_read32(dev, B43_MMIO_MACCTL);
870 macctl |= B43_MACCTL_HWPS;
872 macctl &= ~B43_MACCTL_HWPS;
874 macctl |= B43_MACCTL_AWAKE;
876 macctl &= ~B43_MACCTL_AWAKE;
877 b43_write32(dev, B43_MMIO_MACCTL, macctl);
879 b43_read32(dev, B43_MMIO_MACCTL);
880 if (awake && dev->dev->id.revision >= 5) {
881 /* Wait for the microcode to wake up. */
882 for (i = 0; i < 100; i++) {
883 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
884 B43_SHM_SH_UCODESTAT);
885 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
892 /* Turn the Analog ON/OFF */
893 static void b43_switch_analog(struct b43_wldev *dev, int on)
895 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
898 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
903 flags |= B43_TMSLOW_PHYCLKEN;
904 flags |= B43_TMSLOW_PHYRESET;
905 ssb_device_enable(dev->dev, flags);
906 msleep(2); /* Wait for the PLL to turn on. */
908 /* Now take the PHY out of Reset again */
909 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
910 tmslow |= SSB_TMSLOW_FGC;
911 tmslow &= ~B43_TMSLOW_PHYRESET;
912 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
913 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
915 tmslow &= ~SSB_TMSLOW_FGC;
916 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
917 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
921 b43_switch_analog(dev, 1);
923 macctl = b43_read32(dev, B43_MMIO_MACCTL);
924 macctl &= ~B43_MACCTL_GMODE;
925 if (flags & B43_TMSLOW_GMODE)
926 macctl |= B43_MACCTL_GMODE;
927 macctl |= B43_MACCTL_IHR_ENABLED;
928 b43_write32(dev, B43_MMIO_MACCTL, macctl);
931 static void handle_irq_transmit_status(struct b43_wldev *dev)
935 struct b43_txstatus stat;
938 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
939 if (!(v0 & 0x00000001))
941 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
943 stat.cookie = (v0 >> 16);
944 stat.seq = (v1 & 0x0000FFFF);
945 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
946 tmp = (v0 & 0x0000FFFF);
947 stat.frame_count = ((tmp & 0xF000) >> 12);
948 stat.rts_count = ((tmp & 0x0F00) >> 8);
949 stat.supp_reason = ((tmp & 0x001C) >> 2);
950 stat.pm_indicated = !!(tmp & 0x0080);
951 stat.intermediate = !!(tmp & 0x0040);
952 stat.for_ampdu = !!(tmp & 0x0020);
953 stat.acked = !!(tmp & 0x0002);
955 b43_handle_txstatus(dev, &stat);
959 static void drain_txstatus_queue(struct b43_wldev *dev)
963 if (dev->dev->id.revision < 5)
965 /* Read all entries from the microcode TXstatus FIFO
966 * and throw them away.
969 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
970 if (!(dummy & 0x00000001))
972 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
976 static u32 b43_jssi_read(struct b43_wldev *dev)
980 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
982 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
987 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
989 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
990 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
993 static void b43_generate_noise_sample(struct b43_wldev *dev)
995 b43_jssi_write(dev, 0x7F7F7F7F);
996 b43_write32(dev, B43_MMIO_MACCMD,
997 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
998 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1001 static void b43_calculate_link_quality(struct b43_wldev *dev)
1003 /* Top half of Link Quality calculation. */
1005 if (dev->noisecalc.calculation_running)
1007 dev->noisecalc.channel_at_start = dev->phy.channel;
1008 dev->noisecalc.calculation_running = 1;
1009 dev->noisecalc.nr_samples = 0;
1011 b43_generate_noise_sample(dev);
1014 static void handle_irq_noise(struct b43_wldev *dev)
1016 struct b43_phy *phy = &dev->phy;
1022 /* Bottom half of Link Quality calculation. */
1024 B43_WARN_ON(!dev->noisecalc.calculation_running);
1025 if (dev->noisecalc.channel_at_start != phy->channel)
1026 goto drop_calculation;
1027 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1028 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1029 noise[2] == 0x7F || noise[3] == 0x7F)
1032 /* Get the noise samples. */
1033 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1034 i = dev->noisecalc.nr_samples;
1035 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1036 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1037 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1038 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1039 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1040 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1041 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1042 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1043 dev->noisecalc.nr_samples++;
1044 if (dev->noisecalc.nr_samples == 8) {
1045 /* Calculate the Link Quality by the noise samples. */
1047 for (i = 0; i < 8; i++) {
1048 for (j = 0; j < 4; j++)
1049 average += dev->noisecalc.samples[i][j];
1055 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1056 tmp = (tmp / 128) & 0x1F;
1066 dev->stats.link_noise = average;
1068 dev->noisecalc.calculation_running = 0;
1072 b43_generate_noise_sample(dev);
1075 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1077 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1080 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1081 b43_power_saving_ctl_bits(dev, 0);
1083 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1087 static void handle_irq_atim_end(struct b43_wldev *dev)
1089 if (dev->dfq_valid) {
1090 b43_write32(dev, B43_MMIO_MACCMD,
1091 b43_read32(dev, B43_MMIO_MACCMD)
1092 | B43_MACCMD_DFQ_VALID);
1097 static void handle_irq_pmq(struct b43_wldev *dev)
1104 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1105 if (!(tmp & 0x00000008))
1108 /* 16bit write is odd, but correct. */
1109 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1112 static void b43_write_template_common(struct b43_wldev *dev,
1113 const u8 * data, u16 size,
1115 u16 shm_size_offset, u8 rate)
1118 struct b43_plcp_hdr4 plcp;
1121 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1122 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1123 ram_offset += sizeof(u32);
1124 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1125 * So leave the first two bytes of the next write blank.
1127 tmp = (u32) (data[0]) << 16;
1128 tmp |= (u32) (data[1]) << 24;
1129 b43_ram_write(dev, ram_offset, tmp);
1130 ram_offset += sizeof(u32);
1131 for (i = 2; i < size; i += sizeof(u32)) {
1132 tmp = (u32) (data[i + 0]);
1134 tmp |= (u32) (data[i + 1]) << 8;
1136 tmp |= (u32) (data[i + 2]) << 16;
1138 tmp |= (u32) (data[i + 3]) << 24;
1139 b43_ram_write(dev, ram_offset + i - 2, tmp);
1141 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1142 size + sizeof(struct b43_plcp_hdr6));
1145 static void b43_write_beacon_template(struct b43_wldev *dev,
1147 u16 shm_size_offset, u8 rate)
1152 B43_WARN_ON(!dev->cached_beacon);
1153 len = min((size_t) dev->cached_beacon->len,
1154 0x200 - sizeof(struct b43_plcp_hdr6));
1155 data = (const u8 *)(dev->cached_beacon->data);
1156 b43_write_template_common(dev, data,
1157 len, ram_offset, shm_size_offset, rate);
1160 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1161 u16 shm_offset, u16 size, u8 rate)
1163 struct b43_plcp_hdr4 plcp;
1168 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1169 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1170 dev->wl->if_id, size,
1171 B43_RATE_TO_BASE100KBPS(rate));
1172 /* Write PLCP in two parts and timing for packet transfer */
1173 tmp = le32_to_cpu(plcp.data);
1174 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1175 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1176 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1179 /* Instead of using custom probe response template, this function
1180 * just patches custom beacon template by:
1181 * 1) Changing packet type
1182 * 2) Patching duration field
1185 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1186 u16 * dest_size, u8 rate)
1190 u16 src_size, elem_size, src_pos, dest_pos;
1192 struct ieee80211_hdr *hdr;
1194 B43_WARN_ON(!dev->cached_beacon);
1195 src_size = dev->cached_beacon->len;
1196 src_data = (const u8 *)dev->cached_beacon->data;
1198 if (unlikely(src_size < 0x24)) {
1199 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1203 dest_data = kmalloc(src_size, GFP_ATOMIC);
1204 if (unlikely(!dest_data))
1207 /* 0x24 is offset of first variable-len Information-Element
1210 memcpy(dest_data, src_data, 0x24);
1211 src_pos = dest_pos = 0x24;
1212 for (; src_pos < src_size - 2; src_pos += elem_size) {
1213 elem_size = src_data[src_pos + 1] + 2;
1214 if (src_data[src_pos] != 0x05) { /* TIM */
1215 memcpy(dest_data + dest_pos, src_data + src_pos,
1217 dest_pos += elem_size;
1220 *dest_size = dest_pos;
1221 hdr = (struct ieee80211_hdr *)dest_data;
1223 /* Set the frame control. */
1224 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1225 IEEE80211_STYPE_PROBE_RESP);
1226 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1227 dev->wl->if_id, *dest_size,
1228 B43_RATE_TO_BASE100KBPS(rate));
1229 hdr->duration_id = dur;
1234 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1236 u16 shm_size_offset, u8 rate)
1238 u8 *probe_resp_data;
1241 B43_WARN_ON(!dev->cached_beacon);
1242 size = dev->cached_beacon->len;
1243 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1244 if (unlikely(!probe_resp_data))
1247 /* Looks like PLCP headers plus packet timings are stored for
1248 * all possible basic rates
1250 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1251 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1252 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1253 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1255 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1256 b43_write_template_common(dev, probe_resp_data,
1257 size, ram_offset, shm_size_offset, rate);
1258 kfree(probe_resp_data);
1261 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1262 struct sk_buff *beacon)
1264 if (dev->cached_beacon)
1265 kfree_skb(dev->cached_beacon);
1266 dev->cached_beacon = beacon;
1271 static void b43_update_templates(struct b43_wldev *dev)
1275 B43_WARN_ON(!dev->cached_beacon);
1277 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1278 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1279 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1281 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1282 cmd |= B43_MACCMD_BEACON0_VALID | B43_MACCMD_BEACON1_VALID;
1283 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1286 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1290 err = b43_refresh_cached_beacon(dev, beacon);
1293 b43_update_templates(dev);
1296 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1301 len = min((u16) ssid_len, (u16) 0x100);
1302 for (i = 0; i < len; i += sizeof(u32)) {
1303 tmp = (u32) (ssid[i + 0]);
1305 tmp |= (u32) (ssid[i + 1]) << 8;
1307 tmp |= (u32) (ssid[i + 2]) << 16;
1309 tmp |= (u32) (ssid[i + 3]) << 24;
1310 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1312 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1315 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1318 if (dev->dev->id.revision >= 3) {
1319 b43_write32(dev, 0x188, (beacon_int << 16));
1321 b43_write16(dev, 0x606, (beacon_int >> 6));
1322 b43_write16(dev, 0x610, beacon_int);
1324 b43_time_unlock(dev);
1327 static void handle_irq_beacon(struct b43_wldev *dev)
1331 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1334 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1335 status = b43_read32(dev, B43_MMIO_MACCMD);
1337 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1338 /* ACK beacon IRQ. */
1339 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1340 dev->irq_savedstate |= B43_IRQ_BEACON;
1341 if (dev->cached_beacon)
1342 kfree_skb(dev->cached_beacon);
1343 dev->cached_beacon = NULL;
1346 if (!(status & 0x1)) {
1347 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1349 b43_write32(dev, B43_MMIO_MACCMD, status);
1351 if (!(status & 0x2)) {
1352 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1354 b43_write32(dev, B43_MMIO_MACCMD, status);
1358 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1363 /* Interrupt handler bottom-half */
1364 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1367 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1368 u32 merged_dma_reason = 0;
1370 unsigned long flags;
1372 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1374 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1376 reason = dev->irq_reason;
1377 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1378 dma_reason[i] = dev->dma_reason[i];
1379 merged_dma_reason |= dma_reason[i];
1382 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1383 b43err(dev->wl, "MAC transmission error\n");
1385 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1386 b43err(dev->wl, "PHY transmission error\n");
1388 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1389 atomic_set(&dev->phy.txerr_cnt,
1390 B43_PHY_TX_BADNESS_LIMIT);
1391 b43err(dev->wl, "Too many PHY TX errors, "
1392 "restarting the controller\n");
1393 b43_controller_restart(dev, "PHY TX errors");
1397 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1398 B43_DMAIRQ_NONFATALMASK))) {
1399 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1400 b43err(dev->wl, "Fatal DMA error: "
1401 "0x%08X, 0x%08X, 0x%08X, "
1402 "0x%08X, 0x%08X, 0x%08X\n",
1403 dma_reason[0], dma_reason[1],
1404 dma_reason[2], dma_reason[3],
1405 dma_reason[4], dma_reason[5]);
1406 b43_controller_restart(dev, "DMA error");
1408 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1411 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1412 b43err(dev->wl, "DMA error: "
1413 "0x%08X, 0x%08X, 0x%08X, "
1414 "0x%08X, 0x%08X, 0x%08X\n",
1415 dma_reason[0], dma_reason[1],
1416 dma_reason[2], dma_reason[3],
1417 dma_reason[4], dma_reason[5]);
1421 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1422 handle_irq_ucode_debug(dev);
1423 if (reason & B43_IRQ_TBTT_INDI)
1424 handle_irq_tbtt_indication(dev);
1425 if (reason & B43_IRQ_ATIM_END)
1426 handle_irq_atim_end(dev);
1427 if (reason & B43_IRQ_BEACON)
1428 handle_irq_beacon(dev);
1429 if (reason & B43_IRQ_PMQ)
1430 handle_irq_pmq(dev);
1431 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1433 if (reason & B43_IRQ_NOISESAMPLE_OK)
1434 handle_irq_noise(dev);
1436 /* Check the DMA reason registers for received data. */
1437 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1438 b43_dma_rx(dev->dma.rx_ring0);
1439 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1440 b43_dma_rx(dev->dma.rx_ring3);
1441 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1442 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1443 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1444 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1446 if (reason & B43_IRQ_TX_OK)
1447 handle_irq_transmit_status(dev);
1449 b43_interrupt_enable(dev, dev->irq_savedstate);
1451 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1454 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1456 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1458 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1459 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1460 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1461 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1462 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1463 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1466 /* Interrupt handler top-half */
1467 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1469 irqreturn_t ret = IRQ_NONE;
1470 struct b43_wldev *dev = dev_id;
1476 spin_lock(&dev->wl->irq_lock);
1478 if (b43_status(dev) < B43_STAT_STARTED)
1480 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1481 if (reason == 0xffffffff) /* shared IRQ */
1484 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1488 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1490 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1492 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1494 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1496 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1498 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1501 b43_interrupt_ack(dev, reason);
1502 /* disable all IRQs. They are enabled again in the bottom half. */
1503 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1504 /* save the reason code and call our bottom half. */
1505 dev->irq_reason = reason;
1506 tasklet_schedule(&dev->isr_tasklet);
1509 spin_unlock(&dev->wl->irq_lock);
1514 static void b43_release_firmware(struct b43_wldev *dev)
1516 release_firmware(dev->fw.ucode);
1517 dev->fw.ucode = NULL;
1518 release_firmware(dev->fw.pcm);
1520 release_firmware(dev->fw.initvals);
1521 dev->fw.initvals = NULL;
1522 release_firmware(dev->fw.initvals_band);
1523 dev->fw.initvals_band = NULL;
1526 static void b43_print_fw_helptext(struct b43_wl *wl)
1528 b43err(wl, "You must go to "
1529 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1530 "and download the correct firmware (version 4).\n");
1533 static int do_request_fw(struct b43_wldev *dev,
1535 const struct firmware **fw)
1537 char path[sizeof(modparam_fwpostfix) + 32];
1538 struct b43_fw_header *hdr;
1545 snprintf(path, ARRAY_SIZE(path),
1547 modparam_fwpostfix, name);
1548 err = request_firmware(fw, path, dev->dev->dev);
1550 b43err(dev->wl, "Firmware file \"%s\" not found "
1551 "or load failed.\n", path);
1554 if ((*fw)->size < sizeof(struct b43_fw_header))
1556 hdr = (struct b43_fw_header *)((*fw)->data);
1557 switch (hdr->type) {
1558 case B43_FW_TYPE_UCODE:
1559 case B43_FW_TYPE_PCM:
1560 size = be32_to_cpu(hdr->size);
1561 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1564 case B43_FW_TYPE_IV:
1575 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1579 static int b43_request_firmware(struct b43_wldev *dev)
1581 struct b43_firmware *fw = &dev->fw;
1582 const u8 rev = dev->dev->id.revision;
1583 const char *filename;
1587 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1589 if ((rev >= 5) && (rev <= 10))
1590 filename = "ucode5";
1591 else if ((rev >= 11) && (rev <= 12))
1592 filename = "ucode11";
1594 filename = "ucode13";
1597 err = do_request_fw(dev, filename, &fw->ucode);
1602 if ((rev >= 5) && (rev <= 10))
1608 err = do_request_fw(dev, filename, &fw->pcm);
1612 if (!fw->initvals) {
1613 switch (dev->phy.type) {
1615 if ((rev >= 5) && (rev <= 10)) {
1616 if (tmshigh & B43_TMSHIGH_GPHY)
1617 filename = "a0g1initvals5";
1619 filename = "a0g0initvals5";
1621 goto err_no_initvals;
1624 if ((rev >= 5) && (rev <= 10))
1625 filename = "b0g0initvals5";
1627 filename = "lp0initvals13";
1629 goto err_no_initvals;
1632 goto err_no_initvals;
1634 err = do_request_fw(dev, filename, &fw->initvals);
1638 if (!fw->initvals_band) {
1639 switch (dev->phy.type) {
1641 if ((rev >= 5) && (rev <= 10)) {
1642 if (tmshigh & B43_TMSHIGH_GPHY)
1643 filename = "a0g1bsinitvals5";
1645 filename = "a0g0bsinitvals5";
1646 } else if (rev >= 11)
1649 goto err_no_initvals;
1652 if ((rev >= 5) && (rev <= 10))
1653 filename = "b0g0bsinitvals5";
1657 goto err_no_initvals;
1660 goto err_no_initvals;
1662 err = do_request_fw(dev, filename, &fw->initvals_band);
1670 b43_print_fw_helptext(dev->wl);
1675 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1680 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1685 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1686 "core rev %u\n", dev->phy.type, rev);
1690 b43_release_firmware(dev);
1694 static int b43_upload_microcode(struct b43_wldev *dev)
1696 const size_t hdr_len = sizeof(struct b43_fw_header);
1698 unsigned int i, len;
1699 u16 fwrev, fwpatch, fwdate, fwtime;
1703 /* Upload Microcode. */
1704 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1705 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1706 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1707 for (i = 0; i < len; i++) {
1708 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1713 /* Upload PCM data. */
1714 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1715 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1716 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1717 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1718 /* No need for autoinc bit in SHM_HW */
1719 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1720 for (i = 0; i < len; i++) {
1721 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1726 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1727 b43_write32(dev, B43_MMIO_MACCTL,
1728 B43_MACCTL_PSM_RUN |
1729 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1731 /* Wait for the microcode to load and respond */
1734 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1735 if (tmp == B43_IRQ_MAC_SUSPENDED)
1739 b43err(dev->wl, "Microcode not responding\n");
1740 b43_print_fw_helptext(dev->wl);
1746 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1748 /* Get and check the revisions. */
1749 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1750 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1751 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1752 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1754 if (fwrev <= 0x128) {
1755 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1756 "binary drivers older than version 4.x is unsupported. "
1757 "You must upgrade your firmware files.\n");
1758 b43_print_fw_helptext(dev->wl);
1759 b43_write32(dev, B43_MMIO_MACCTL, 0);
1763 b43dbg(dev->wl, "Loading firmware version %u.%u "
1764 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1766 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1767 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1769 dev->fw.rev = fwrev;
1770 dev->fw.patch = fwpatch;
1776 static int b43_write_initvals(struct b43_wldev *dev,
1777 const struct b43_iv *ivals,
1781 const struct b43_iv *iv;
1786 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1788 for (i = 0; i < count; i++) {
1789 if (array_size < sizeof(iv->offset_size))
1791 array_size -= sizeof(iv->offset_size);
1792 offset = be16_to_cpu(iv->offset_size);
1793 bit32 = !!(offset & B43_IV_32BIT);
1794 offset &= B43_IV_OFFSET_MASK;
1795 if (offset >= 0x1000)
1800 if (array_size < sizeof(iv->data.d32))
1802 array_size -= sizeof(iv->data.d32);
1804 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1805 b43_write32(dev, offset, value);
1807 iv = (const struct b43_iv *)((const uint8_t *)iv +
1813 if (array_size < sizeof(iv->data.d16))
1815 array_size -= sizeof(iv->data.d16);
1817 value = be16_to_cpu(iv->data.d16);
1818 b43_write16(dev, offset, value);
1820 iv = (const struct b43_iv *)((const uint8_t *)iv +
1831 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1832 b43_print_fw_helptext(dev->wl);
1837 static int b43_upload_initvals(struct b43_wldev *dev)
1839 const size_t hdr_len = sizeof(struct b43_fw_header);
1840 const struct b43_fw_header *hdr;
1841 struct b43_firmware *fw = &dev->fw;
1842 const struct b43_iv *ivals;
1846 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1847 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1848 count = be32_to_cpu(hdr->size);
1849 err = b43_write_initvals(dev, ivals, count,
1850 fw->initvals->size - hdr_len);
1853 if (fw->initvals_band) {
1854 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1855 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1856 count = be32_to_cpu(hdr->size);
1857 err = b43_write_initvals(dev, ivals, count,
1858 fw->initvals_band->size - hdr_len);
1867 /* Initialize the GPIOs
1868 * http://bcm-specs.sipsolutions.net/GPIO
1870 static int b43_gpio_init(struct b43_wldev *dev)
1872 struct ssb_bus *bus = dev->dev->bus;
1873 struct ssb_device *gpiodev, *pcidev = NULL;
1876 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1877 & ~B43_MACCTL_GPOUTSMSK);
1879 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1884 if (dev->dev->bus->chip_id == 0x4301) {
1888 if (0 /* FIXME: conditional unknown */ ) {
1889 b43_write16(dev, B43_MMIO_GPIO_MASK,
1890 b43_read16(dev, B43_MMIO_GPIO_MASK)
1895 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1896 b43_write16(dev, B43_MMIO_GPIO_MASK,
1897 b43_read16(dev, B43_MMIO_GPIO_MASK)
1902 if (dev->dev->id.revision >= 2)
1903 mask |= 0x0010; /* FIXME: This is redundant. */
1905 #ifdef CONFIG_SSB_DRIVER_PCICORE
1906 pcidev = bus->pcicore.dev;
1908 gpiodev = bus->chipco.dev ? : pcidev;
1911 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1912 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1918 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1919 static void b43_gpio_cleanup(struct b43_wldev *dev)
1921 struct ssb_bus *bus = dev->dev->bus;
1922 struct ssb_device *gpiodev, *pcidev = NULL;
1924 #ifdef CONFIG_SSB_DRIVER_PCICORE
1925 pcidev = bus->pcicore.dev;
1927 gpiodev = bus->chipco.dev ? : pcidev;
1930 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1933 /* http://bcm-specs.sipsolutions.net/EnableMac */
1934 void b43_mac_enable(struct b43_wldev *dev)
1936 dev->mac_suspended--;
1937 B43_WARN_ON(dev->mac_suspended < 0);
1938 B43_WARN_ON(irqs_disabled());
1939 if (dev->mac_suspended == 0) {
1940 b43_write32(dev, B43_MMIO_MACCTL,
1941 b43_read32(dev, B43_MMIO_MACCTL)
1942 | B43_MACCTL_ENABLED);
1943 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1944 B43_IRQ_MAC_SUSPENDED);
1946 b43_read32(dev, B43_MMIO_MACCTL);
1947 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1948 b43_power_saving_ctl_bits(dev, 0);
1950 /* Re-enable IRQs. */
1951 spin_lock_irq(&dev->wl->irq_lock);
1952 b43_interrupt_enable(dev, dev->irq_savedstate);
1953 spin_unlock_irq(&dev->wl->irq_lock);
1957 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1958 void b43_mac_suspend(struct b43_wldev *dev)
1964 B43_WARN_ON(irqs_disabled());
1965 B43_WARN_ON(dev->mac_suspended < 0);
1967 if (dev->mac_suspended == 0) {
1968 /* Mask IRQs before suspending MAC. Otherwise
1969 * the MAC stays busy and won't suspend. */
1970 spin_lock_irq(&dev->wl->irq_lock);
1971 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
1972 spin_unlock_irq(&dev->wl->irq_lock);
1973 b43_synchronize_irq(dev);
1974 dev->irq_savedstate = tmp;
1976 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1977 b43_write32(dev, B43_MMIO_MACCTL,
1978 b43_read32(dev, B43_MMIO_MACCTL)
1979 & ~B43_MACCTL_ENABLED);
1980 /* force pci to flush the write */
1981 b43_read32(dev, B43_MMIO_MACCTL);
1982 for (i = 40; i; i--) {
1983 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1984 if (tmp & B43_IRQ_MAC_SUSPENDED)
1988 b43err(dev->wl, "MAC suspend failed\n");
1991 dev->mac_suspended++;
1994 static void b43_adjust_opmode(struct b43_wldev *dev)
1996 struct b43_wl *wl = dev->wl;
2000 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2001 /* Reset status to STA infrastructure mode. */
2002 ctl &= ~B43_MACCTL_AP;
2003 ctl &= ~B43_MACCTL_KEEP_CTL;
2004 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2005 ctl &= ~B43_MACCTL_KEEP_BAD;
2006 ctl &= ~B43_MACCTL_PROMISC;
2007 ctl &= ~B43_MACCTL_BEACPROMISC;
2008 ctl |= B43_MACCTL_INFRA;
2010 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2011 ctl |= B43_MACCTL_AP;
2012 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2013 ctl &= ~B43_MACCTL_INFRA;
2015 if (wl->filter_flags & FIF_CONTROL)
2016 ctl |= B43_MACCTL_KEEP_CTL;
2017 if (wl->filter_flags & FIF_FCSFAIL)
2018 ctl |= B43_MACCTL_KEEP_BAD;
2019 if (wl->filter_flags & FIF_PLCPFAIL)
2020 ctl |= B43_MACCTL_KEEP_BADPLCP;
2021 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2022 ctl |= B43_MACCTL_PROMISC;
2023 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2024 ctl |= B43_MACCTL_BEACPROMISC;
2026 /* Workaround: On old hardware the HW-MAC-address-filter
2027 * doesn't work properly, so always run promisc in filter
2028 * it in software. */
2029 if (dev->dev->id.revision <= 4)
2030 ctl |= B43_MACCTL_PROMISC;
2032 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2035 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2036 if (dev->dev->bus->chip_id == 0x4306 &&
2037 dev->dev->bus->chip_rev == 3)
2042 b43_write16(dev, 0x612, cfp_pretbtt);
2045 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2051 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2054 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2056 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2057 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2060 static void b43_rate_memory_init(struct b43_wldev *dev)
2062 switch (dev->phy.type) {
2065 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2066 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2067 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2068 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2069 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2070 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2071 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2072 if (dev->phy.type == B43_PHYTYPE_A)
2076 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2077 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2078 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2079 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2086 /* Set the TX-Antenna for management frames sent by firmware. */
2087 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2094 ant |= B43_TX4_PHY_ANT0;
2097 ant |= B43_TX4_PHY_ANT1;
2099 case B43_ANTENNA_AUTO:
2100 ant |= B43_TX4_PHY_ANTLAST;
2106 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2109 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2110 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2111 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2113 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2114 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2115 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2116 /* For Probe Resposes */
2117 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2118 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2119 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2122 /* This is the opposite of b43_chip_init() */
2123 static void b43_chip_exit(struct b43_wldev *dev)
2125 b43_radio_turn_off(dev, 1);
2126 b43_gpio_cleanup(dev);
2127 /* firmware is released later */
2130 /* Initialize the chip
2131 * http://bcm-specs.sipsolutions.net/ChipInit
2133 static int b43_chip_init(struct b43_wldev *dev)
2135 struct b43_phy *phy = &dev->phy;
2140 b43_write32(dev, B43_MMIO_MACCTL,
2141 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2143 err = b43_request_firmware(dev);
2146 err = b43_upload_microcode(dev);
2148 goto out; /* firmware is released later */
2150 err = b43_gpio_init(dev);
2152 goto out; /* firmware is released later */
2154 err = b43_upload_initvals(dev);
2156 goto err_gpio_clean;
2157 b43_radio_turn_on(dev);
2159 b43_write16(dev, 0x03E6, 0x0000);
2160 err = b43_phy_init(dev);
2164 /* Select initial Interference Mitigation. */
2165 tmp = phy->interfmode;
2166 phy->interfmode = B43_INTERFMODE_NONE;
2167 b43_radio_set_interference_mitigation(dev, tmp);
2169 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2170 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2172 if (phy->type == B43_PHYTYPE_B) {
2173 value16 = b43_read16(dev, 0x005E);
2175 b43_write16(dev, 0x005E, value16);
2177 b43_write32(dev, 0x0100, 0x01000000);
2178 if (dev->dev->id.revision < 5)
2179 b43_write32(dev, 0x010C, 0x01000000);
2181 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2182 & ~B43_MACCTL_INFRA);
2183 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2184 | B43_MACCTL_INFRA);
2186 /* Probe Response Timeout value */
2187 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2188 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2190 /* Initially set the wireless operation mode. */
2191 b43_adjust_opmode(dev);
2193 if (dev->dev->id.revision < 3) {
2194 b43_write16(dev, 0x060E, 0x0000);
2195 b43_write16(dev, 0x0610, 0x8000);
2196 b43_write16(dev, 0x0604, 0x0000);
2197 b43_write16(dev, 0x0606, 0x0200);
2199 b43_write32(dev, 0x0188, 0x80000000);
2200 b43_write32(dev, 0x018C, 0x02000000);
2202 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2203 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2204 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2205 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2206 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2207 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2208 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2210 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2211 value32 |= 0x00100000;
2212 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2214 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2215 dev->dev->bus->chipco.fast_pwrup_delay);
2218 b43dbg(dev->wl, "Chip initialized\n");
2223 b43_radio_turn_off(dev, 1);
2225 b43_gpio_cleanup(dev);
2229 static void b43_periodic_every120sec(struct b43_wldev *dev)
2231 struct b43_phy *phy = &dev->phy;
2233 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2236 b43_mac_suspend(dev);
2237 b43_lo_g_measure(dev);
2238 b43_mac_enable(dev);
2239 if (b43_has_hardware_pctl(phy))
2240 b43_lo_g_ctl_mark_all_unused(dev);
2243 static void b43_periodic_every60sec(struct b43_wldev *dev)
2245 struct b43_phy *phy = &dev->phy;
2247 if (!b43_has_hardware_pctl(phy))
2248 b43_lo_g_ctl_mark_all_unused(dev);
2249 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2250 b43_mac_suspend(dev);
2251 b43_calc_nrssi_slope(dev);
2252 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2253 u8 old_chan = phy->channel;
2255 /* VCO Calibration */
2257 b43_radio_selectchannel(dev, 1, 0);
2259 b43_radio_selectchannel(dev, 13, 0);
2260 b43_radio_selectchannel(dev, old_chan, 0);
2262 b43_mac_enable(dev);
2266 static void b43_periodic_every30sec(struct b43_wldev *dev)
2268 /* Update device statistics. */
2269 b43_calculate_link_quality(dev);
2272 static void b43_periodic_every15sec(struct b43_wldev *dev)
2274 struct b43_phy *phy = &dev->phy;
2276 if (phy->type == B43_PHYTYPE_G) {
2277 //TODO: update_aci_moving_average
2278 if (phy->aci_enable && phy->aci_wlan_automatic) {
2279 b43_mac_suspend(dev);
2280 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2281 if (0 /*TODO: bunch of conditions */ ) {
2282 b43_radio_set_interference_mitigation
2283 (dev, B43_INTERFMODE_MANUALWLAN);
2285 } else if (1 /*TODO*/) {
2287 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2288 b43_radio_set_interference_mitigation(dev,
2289 B43_INTERFMODE_NONE);
2293 b43_mac_enable(dev);
2294 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2296 //TODO: implement rev1 workaround
2299 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2300 //TODO for APHY (temperature?)
2302 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2306 static void do_periodic_work(struct b43_wldev *dev)
2310 state = dev->periodic_state;
2312 b43_periodic_every120sec(dev);
2314 b43_periodic_every60sec(dev);
2316 b43_periodic_every30sec(dev);
2317 b43_periodic_every15sec(dev);
2320 /* Periodic work locking policy:
2321 * The whole periodic work handler is protected by
2322 * wl->mutex. If another lock is needed somewhere in the
2323 * pwork callchain, it's aquired in-place, where it's needed.
2325 static void b43_periodic_work_handler(struct work_struct *work)
2327 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2328 periodic_work.work);
2329 struct b43_wl *wl = dev->wl;
2330 unsigned long delay;
2332 mutex_lock(&wl->mutex);
2334 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2336 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2339 do_periodic_work(dev);
2341 dev->periodic_state++;
2343 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2344 delay = msecs_to_jiffies(50);
2346 delay = round_jiffies_relative(HZ * 15);
2347 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2349 mutex_unlock(&wl->mutex);
2352 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2354 struct delayed_work *work = &dev->periodic_work;
2356 dev->periodic_state = 0;
2357 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2358 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2361 /* Check if communication with the device works correctly. */
2362 static int b43_validate_chipaccess(struct b43_wldev *dev)
2366 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2368 /* Check for read/write and endianness problems. */
2369 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2370 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2372 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2373 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2376 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2378 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2379 /* The 32bit register shadows the two 16bit registers
2380 * with update sideeffects. Validate this. */
2381 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2382 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2383 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2385 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2388 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2390 v = b43_read32(dev, B43_MMIO_MACCTL);
2391 v |= B43_MACCTL_GMODE;
2392 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2397 b43err(dev->wl, "Failed to validate the chipaccess\n");
2401 static void b43_security_init(struct b43_wldev *dev)
2403 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2404 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2405 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2406 /* KTP is a word address, but we address SHM bytewise.
2407 * So multiply by two.
2410 if (dev->dev->id.revision >= 5) {
2411 /* Number of RCMTA address slots */
2412 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2414 b43_clear_keys(dev);
2417 static int b43_rng_read(struct hwrng *rng, u32 * data)
2419 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2420 unsigned long flags;
2422 /* Don't take wl->mutex here, as it could deadlock with
2423 * hwrng internal locking. It's not needed to take
2424 * wl->mutex here, anyway. */
2426 spin_lock_irqsave(&wl->irq_lock, flags);
2427 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2428 spin_unlock_irqrestore(&wl->irq_lock, flags);
2430 return (sizeof(u16));
2433 static void b43_rng_exit(struct b43_wl *wl)
2435 if (wl->rng_initialized)
2436 hwrng_unregister(&wl->rng);
2439 static int b43_rng_init(struct b43_wl *wl)
2443 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2444 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2445 wl->rng.name = wl->rng_name;
2446 wl->rng.data_read = b43_rng_read;
2447 wl->rng.priv = (unsigned long)wl;
2448 wl->rng_initialized = 1;
2449 err = hwrng_register(&wl->rng);
2451 wl->rng_initialized = 0;
2452 b43err(wl, "Failed to register the random "
2453 "number generator (%d)\n", err);
2459 static int b43_op_tx(struct ieee80211_hw *hw,
2460 struct sk_buff *skb,
2461 struct ieee80211_tx_control *ctl)
2463 struct b43_wl *wl = hw_to_b43_wl(hw);
2464 struct b43_wldev *dev = wl->current_dev;
2469 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2471 /* DMA-TX is done without a global lock. */
2472 err = b43_dma_tx(dev, skb, ctl);
2475 return NETDEV_TX_BUSY;
2476 return NETDEV_TX_OK;
2479 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2481 const struct ieee80211_tx_queue_params *params)
2486 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2487 struct ieee80211_tx_queue_stats *stats)
2489 struct b43_wl *wl = hw_to_b43_wl(hw);
2490 struct b43_wldev *dev = wl->current_dev;
2491 unsigned long flags;
2496 spin_lock_irqsave(&wl->irq_lock, flags);
2497 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2498 b43_dma_get_tx_stats(dev, stats);
2501 spin_unlock_irqrestore(&wl->irq_lock, flags);
2506 static int b43_op_get_stats(struct ieee80211_hw *hw,
2507 struct ieee80211_low_level_stats *stats)
2509 struct b43_wl *wl = hw_to_b43_wl(hw);
2510 unsigned long flags;
2512 spin_lock_irqsave(&wl->irq_lock, flags);
2513 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2514 spin_unlock_irqrestore(&wl->irq_lock, flags);
2519 static const char *phymode_to_string(unsigned int phymode)
2534 static int find_wldev_for_phymode(struct b43_wl *wl,
2535 unsigned int phymode,
2536 struct b43_wldev **dev, bool * gmode)
2538 struct b43_wldev *d;
2540 list_for_each_entry(d, &wl->devlist, list) {
2541 if (d->phy.possible_phymodes & phymode) {
2542 /* Ok, this device supports the PHY-mode.
2543 * Now figure out how the gmode bit has to be
2544 * set to support it. */
2545 if (phymode == B43_PHYMODE_A)
2558 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2560 struct ssb_device *sdev = dev->dev;
2563 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2564 tmslow &= ~B43_TMSLOW_GMODE;
2565 tmslow |= B43_TMSLOW_PHYRESET;
2566 tmslow |= SSB_TMSLOW_FGC;
2567 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2570 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2571 tmslow &= ~SSB_TMSLOW_FGC;
2572 tmslow |= B43_TMSLOW_PHYRESET;
2573 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2577 /* Expects wl->mutex locked */
2578 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2580 struct b43_wldev *up_dev;
2581 struct b43_wldev *down_dev;
2586 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2588 b43err(wl, "Could not find a device for %s-PHY mode\n",
2589 phymode_to_string(new_mode));
2592 if ((up_dev == wl->current_dev) &&
2593 (!!wl->current_dev->phy.gmode == !!gmode)) {
2594 /* This device is already running. */
2597 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2598 phymode_to_string(new_mode));
2599 down_dev = wl->current_dev;
2601 prev_status = b43_status(down_dev);
2602 /* Shutdown the currently running core. */
2603 if (prev_status >= B43_STAT_STARTED)
2604 b43_wireless_core_stop(down_dev);
2605 if (prev_status >= B43_STAT_INITIALIZED)
2606 b43_wireless_core_exit(down_dev);
2608 if (down_dev != up_dev) {
2609 /* We switch to a different core, so we put PHY into
2610 * RESET on the old core. */
2611 b43_put_phy_into_reset(down_dev);
2614 /* Now start the new core. */
2615 up_dev->phy.gmode = gmode;
2616 if (prev_status >= B43_STAT_INITIALIZED) {
2617 err = b43_wireless_core_init(up_dev);
2619 b43err(wl, "Fatal: Could not initialize device for "
2620 "newly selected %s-PHY mode\n",
2621 phymode_to_string(new_mode));
2625 if (prev_status >= B43_STAT_STARTED) {
2626 err = b43_wireless_core_start(up_dev);
2628 b43err(wl, "Fatal: Coult not start device for "
2629 "newly selected %s-PHY mode\n",
2630 phymode_to_string(new_mode));
2631 b43_wireless_core_exit(up_dev);
2635 B43_WARN_ON(b43_status(up_dev) != prev_status);
2637 wl->current_dev = up_dev;
2641 /* Whoops, failed to init the new core. No core is operating now. */
2642 wl->current_dev = NULL;
2646 /* Check if the use of the antenna that ieee80211 told us to
2647 * use is possible. This will fall back to DEFAULT.
2648 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2649 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2654 if (antenna_nr == 0) {
2655 /* Zero means "use default antenna". That's always OK. */
2659 /* Get the mask of available antennas. */
2661 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2663 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2665 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2666 /* This antenna is not available. Fall back to default. */
2673 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2675 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2677 case 0: /* default/diversity */
2678 return B43_ANTENNA_DEFAULT;
2679 case 1: /* Antenna 0 */
2680 return B43_ANTENNA0;
2681 case 2: /* Antenna 1 */
2682 return B43_ANTENNA1;
2684 return B43_ANTENNA_DEFAULT;
2688 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2690 struct b43_wl *wl = hw_to_b43_wl(hw);
2691 struct b43_wldev *dev;
2692 struct b43_phy *phy;
2693 unsigned long flags;
2694 unsigned int new_phymode = 0xFFFF;
2699 mutex_lock(&wl->mutex);
2701 /* Switch the PHY mode (if necessary). */
2702 switch (conf->phymode) {
2703 case MODE_IEEE80211A:
2704 new_phymode = B43_PHYMODE_A;
2706 case MODE_IEEE80211B:
2707 new_phymode = B43_PHYMODE_B;
2709 case MODE_IEEE80211G:
2710 new_phymode = B43_PHYMODE_G;
2715 err = b43_switch_phymode(wl, new_phymode);
2717 goto out_unlock_mutex;
2718 dev = wl->current_dev;
2721 /* Disable IRQs while reconfiguring the device.
2722 * This makes it possible to drop the spinlock throughout
2723 * the reconfiguration process. */
2724 spin_lock_irqsave(&wl->irq_lock, flags);
2725 if (b43_status(dev) < B43_STAT_STARTED) {
2726 spin_unlock_irqrestore(&wl->irq_lock, flags);
2727 goto out_unlock_mutex;
2729 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2730 spin_unlock_irqrestore(&wl->irq_lock, flags);
2731 b43_synchronize_irq(dev);
2733 /* Switch to the requested channel.
2734 * The firmware takes care of races with the TX handler. */
2735 if (conf->channel_val != phy->channel)
2736 b43_radio_selectchannel(dev, conf->channel_val, 0);
2738 /* Enable/Disable ShortSlot timing. */
2739 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2741 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2742 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2743 b43_short_slot_timing_enable(dev);
2745 b43_short_slot_timing_disable(dev);
2748 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2750 /* Adjust the desired TX power level. */
2751 if (conf->power_level != 0) {
2752 if (conf->power_level != phy->power_level) {
2753 phy->power_level = conf->power_level;
2754 b43_phy_xmitpower(dev);
2758 /* Antennas for RX and management frame TX. */
2759 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2760 b43_mgmtframe_txantenna(dev, antenna);
2761 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2762 b43_set_rx_antenna(dev, antenna);
2764 /* Update templates for AP mode. */
2765 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2766 b43_set_beacon_int(dev, conf->beacon_int);
2768 if (!!conf->radio_enabled != phy->radio_on) {
2769 if (conf->radio_enabled) {
2770 b43_radio_turn_on(dev);
2771 b43info(dev->wl, "Radio turned on by software\n");
2772 if (!dev->radio_hw_enable) {
2773 b43info(dev->wl, "The hardware RF-kill button "
2774 "still turns the radio physically off. "
2775 "Press the button to turn it on.\n");
2778 b43_radio_turn_off(dev, 0);
2779 b43info(dev->wl, "Radio turned off by software\n");
2783 spin_lock_irqsave(&wl->irq_lock, flags);
2784 b43_interrupt_enable(dev, savedirqs);
2786 spin_unlock_irqrestore(&wl->irq_lock, flags);
2788 mutex_unlock(&wl->mutex);
2793 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2794 const u8 *local_addr, const u8 *addr,
2795 struct ieee80211_key_conf *key)
2797 struct b43_wl *wl = hw_to_b43_wl(hw);
2798 struct b43_wldev *dev;
2799 unsigned long flags;
2803 DECLARE_MAC_BUF(mac);
2805 if (modparam_nohwcrypt)
2806 return -ENOSPC; /* User disabled HW-crypto */
2808 mutex_lock(&wl->mutex);
2809 spin_lock_irqsave(&wl->irq_lock, flags);
2811 dev = wl->current_dev;
2813 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2819 if (key->keylen == 5)
2820 algorithm = B43_SEC_ALGO_WEP40;
2822 algorithm = B43_SEC_ALGO_WEP104;
2825 algorithm = B43_SEC_ALGO_TKIP;
2828 algorithm = B43_SEC_ALGO_AES;
2834 index = (u8) (key->keyidx);
2840 if (algorithm == B43_SEC_ALGO_TKIP) {
2841 /* FIXME: No TKIP hardware encryption for now. */
2846 if (is_broadcast_ether_addr(addr)) {
2847 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2848 err = b43_key_write(dev, index, algorithm,
2849 key->key, key->keylen, NULL, key);
2852 * either pairwise key or address is 00:00:00:00:00:00
2853 * for transmit-only keys
2855 err = b43_key_write(dev, -1, algorithm,
2856 key->key, key->keylen, addr, key);
2861 if (algorithm == B43_SEC_ALGO_WEP40 ||
2862 algorithm == B43_SEC_ALGO_WEP104) {
2863 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2866 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2868 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2871 err = b43_key_clear(dev, key->hw_key_idx);
2880 spin_unlock_irqrestore(&wl->irq_lock, flags);
2881 mutex_unlock(&wl->mutex);
2883 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2885 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2886 print_mac(mac, addr));
2891 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2892 unsigned int changed, unsigned int *fflags,
2893 int mc_count, struct dev_addr_list *mc_list)
2895 struct b43_wl *wl = hw_to_b43_wl(hw);
2896 struct b43_wldev *dev = wl->current_dev;
2897 unsigned long flags;
2904 spin_lock_irqsave(&wl->irq_lock, flags);
2905 *fflags &= FIF_PROMISC_IN_BSS |
2911 FIF_BCN_PRBRESP_PROMISC;
2913 changed &= FIF_PROMISC_IN_BSS |
2919 FIF_BCN_PRBRESP_PROMISC;
2921 wl->filter_flags = *fflags;
2923 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2924 b43_adjust_opmode(dev);
2925 spin_unlock_irqrestore(&wl->irq_lock, flags);
2928 static int b43_op_config_interface(struct ieee80211_hw *hw,
2930 struct ieee80211_if_conf *conf)
2932 struct b43_wl *wl = hw_to_b43_wl(hw);
2933 struct b43_wldev *dev = wl->current_dev;
2934 unsigned long flags;
2938 mutex_lock(&wl->mutex);
2939 spin_lock_irqsave(&wl->irq_lock, flags);
2940 B43_WARN_ON(wl->if_id != if_id);
2942 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2944 memset(wl->bssid, 0, ETH_ALEN);
2945 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2946 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2947 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2948 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2950 b43_refresh_templates(dev, conf->beacon);
2952 b43_write_mac_bssid_templates(dev);
2954 spin_unlock_irqrestore(&wl->irq_lock, flags);
2955 mutex_unlock(&wl->mutex);
2960 /* Locking: wl->mutex */
2961 static void b43_wireless_core_stop(struct b43_wldev *dev)
2963 struct b43_wl *wl = dev->wl;
2964 unsigned long flags;
2966 if (b43_status(dev) < B43_STAT_STARTED)
2969 /* Disable and sync interrupts. We must do this before than
2970 * setting the status to INITIALIZED, as the interrupt handler
2971 * won't care about IRQs then. */
2972 spin_lock_irqsave(&wl->irq_lock, flags);
2973 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
2974 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
2975 spin_unlock_irqrestore(&wl->irq_lock, flags);
2976 b43_synchronize_irq(dev);
2978 b43_set_status(dev, B43_STAT_INITIALIZED);
2980 mutex_unlock(&wl->mutex);
2981 /* Must unlock as it would otherwise deadlock. No races here.
2982 * Cancel the possibly running self-rearming periodic work. */
2983 cancel_delayed_work_sync(&dev->periodic_work);
2984 mutex_lock(&wl->mutex);
2986 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
2988 b43_mac_suspend(dev);
2989 free_irq(dev->dev->irq, dev);
2990 b43dbg(wl, "Wireless interface stopped\n");
2993 /* Locking: wl->mutex */
2994 static int b43_wireless_core_start(struct b43_wldev *dev)
2998 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3000 drain_txstatus_queue(dev);
3001 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3002 IRQF_SHARED, KBUILD_MODNAME, dev);
3004 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3008 /* We are ready to run. */
3009 b43_set_status(dev, B43_STAT_STARTED);
3011 /* Start data flow (TX/RX). */
3012 b43_mac_enable(dev);
3013 b43_interrupt_enable(dev, dev->irq_savedstate);
3014 ieee80211_start_queues(dev->wl->hw);
3016 /* Start maintainance work */
3017 b43_periodic_tasks_setup(dev);
3019 b43dbg(dev->wl, "Wireless interface started\n");
3024 /* Get PHY and RADIO versioning numbers */
3025 static int b43_phy_versioning(struct b43_wldev *dev)
3027 struct b43_phy *phy = &dev->phy;
3035 int unsupported = 0;
3037 /* Get PHY versioning */
3038 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3039 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3040 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3041 phy_rev = (tmp & B43_PHYVER_VERSION);
3048 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3060 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3061 "(Analog %u, Type %u, Revision %u)\n",
3062 analog_type, phy_type, phy_rev);
3065 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3066 analog_type, phy_type, phy_rev);
3068 /* Get RADIO versioning */
3069 if (dev->dev->bus->chip_id == 0x4317) {
3070 if (dev->dev->bus->chip_rev == 0)
3072 else if (dev->dev->bus->chip_rev == 1)
3077 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3078 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3080 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3081 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3083 radio_manuf = (tmp & 0x00000FFF);
3084 radio_ver = (tmp & 0x0FFFF000) >> 12;
3085 radio_rev = (tmp & 0xF0000000) >> 28;
3088 if (radio_ver != 0x2060)
3092 if (radio_manuf != 0x17F)
3096 if ((radio_ver & 0xFFF0) != 0x2050)
3100 if (radio_ver != 0x2050)
3107 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3108 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3109 radio_manuf, radio_ver, radio_rev);
3112 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3113 radio_manuf, radio_ver, radio_rev);
3115 phy->radio_manuf = radio_manuf;
3116 phy->radio_ver = radio_ver;
3117 phy->radio_rev = radio_rev;
3119 phy->analog = analog_type;
3120 phy->type = phy_type;
3126 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3127 struct b43_phy *phy)
3129 struct b43_txpower_lo_control *lo;
3132 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3133 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3138 phy->aci_enable = 0;
3139 phy->aci_wlan_automatic = 0;
3140 phy->aci_hw_rssi = 0;
3142 phy->radio_off_context.valid = 0;
3144 lo = phy->lo_control;
3146 memset(lo, 0, sizeof(*(phy->lo_control)));
3150 phy->max_lb_gain = 0;
3151 phy->trsw_rx_gain = 0;
3152 phy->txpwr_offset = 0;
3155 phy->nrssislope = 0;
3156 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3157 phy->nrssi[i] = -1000;
3158 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3159 phy->nrssi_lt[i] = i;
3161 phy->lofcal = 0xFFFF;
3162 phy->initval = 0xFFFF;
3164 spin_lock_init(&phy->lock);
3165 phy->interfmode = B43_INTERFMODE_NONE;
3166 phy->channel = 0xFF;
3168 phy->hardware_power_control = !!modparam_hwpctl;
3170 /* PHY TX errors counter. */
3171 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3173 /* OFDM-table address caching. */
3174 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3177 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3181 /* Assume the radio is enabled. If it's not enabled, the state will
3182 * immediately get fixed on the first periodic work run. */
3183 dev->radio_hw_enable = 1;
3186 memset(&dev->stats, 0, sizeof(dev->stats));
3188 setup_struct_phy_for_init(dev, &dev->phy);
3190 /* IRQ related flags */
3191 dev->irq_reason = 0;
3192 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3193 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3195 dev->mac_suspended = 1;
3197 /* Noise calculation context */
3198 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3201 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3203 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3206 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3208 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3211 hf = b43_hf_read(dev);
3212 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3213 hf |= B43_HF_BTCOEXALT;
3215 hf |= B43_HF_BTCOEX;
3216 b43_hf_write(dev, hf);
3220 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3224 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3226 #ifdef CONFIG_SSB_DRIVER_PCICORE
3227 struct ssb_bus *bus = dev->dev->bus;
3230 if (bus->pcicore.dev &&
3231 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3232 bus->pcicore.dev->id.revision <= 5) {
3233 /* IMCFGLO timeouts workaround. */
3234 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3235 tmp &= ~SSB_IMCFGLO_REQTO;
3236 tmp &= ~SSB_IMCFGLO_SERTO;
3237 switch (bus->bustype) {
3238 case SSB_BUSTYPE_PCI:
3239 case SSB_BUSTYPE_PCMCIA:
3242 case SSB_BUSTYPE_SSB:
3246 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3248 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3251 /* Write the short and long frame retry limit values. */
3252 static void b43_set_retry_limits(struct b43_wldev *dev,
3253 unsigned int short_retry,
3254 unsigned int long_retry)
3256 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3257 * the chip-internal counter. */
3258 short_retry = min(short_retry, (unsigned int)0xF);
3259 long_retry = min(long_retry, (unsigned int)0xF);
3261 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3263 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3267 /* Shutdown a wireless core */
3268 /* Locking: wl->mutex */
3269 static void b43_wireless_core_exit(struct b43_wldev *dev)
3271 struct b43_phy *phy = &dev->phy;
3273 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3274 if (b43_status(dev) != B43_STAT_INITIALIZED)
3276 b43_set_status(dev, B43_STAT_UNINIT);
3279 b43_rng_exit(dev->wl);
3282 b43_radio_turn_off(dev, 1);
3283 b43_switch_analog(dev, 0);
3284 if (phy->dyn_tssi_tbl)
3285 kfree(phy->tssi2dbm);
3286 kfree(phy->lo_control);
3287 phy->lo_control = NULL;
3288 ssb_device_disable(dev->dev, 0);
3289 ssb_bus_may_powerdown(dev->dev->bus);
3292 /* Initialize a wireless core */
3293 static int b43_wireless_core_init(struct b43_wldev *dev)
3295 struct b43_wl *wl = dev->wl;
3296 struct ssb_bus *bus = dev->dev->bus;
3297 struct ssb_sprom *sprom = &bus->sprom;
3298 struct b43_phy *phy = &dev->phy;
3302 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3304 err = ssb_bus_powerup(bus, 0);
3307 if (!ssb_device_is_enabled(dev->dev)) {
3308 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3309 b43_wireless_core_reset(dev, tmp);
3312 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3314 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3315 if (!phy->lo_control) {
3320 setup_struct_wldev_for_init(dev);
3322 err = b43_phy_init_tssi2dbm_table(dev);
3324 goto err_kfree_lo_control;
3326 /* Enable IRQ routing to this device. */
3327 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3329 b43_imcfglo_timeouts_workaround(dev);
3330 b43_bluetooth_coext_disable(dev);
3331 b43_phy_early_init(dev);
3332 err = b43_chip_init(dev);
3334 goto err_kfree_tssitbl;
3335 b43_shm_write16(dev, B43_SHM_SHARED,
3336 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3337 hf = b43_hf_read(dev);
3338 if (phy->type == B43_PHYTYPE_G) {
3342 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3343 hf |= B43_HF_OFDMPABOOST;
3344 } else if (phy->type == B43_PHYTYPE_B) {
3346 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3349 b43_hf_write(dev, hf);
3351 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3352 B43_DEFAULT_LONG_RETRY_LIMIT);
3353 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3354 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3356 /* Disable sending probe responses from firmware.
3357 * Setting the MaxTime to one usec will always trigger
3358 * a timeout, so we never send any probe resp.
3359 * A timeout of zero is infinite. */
3360 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3362 b43_rate_memory_init(dev);
3364 /* Minimum Contention Window */
3365 if (phy->type == B43_PHYTYPE_B) {
3366 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3368 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3370 /* Maximum Contention Window */
3371 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3373 err = b43_dma_init(dev);
3380 b43_write16(dev, 0x0612, 0x0050);
3381 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3382 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3385 b43_bluetooth_coext_enable(dev);
3387 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3388 memset(wl->bssid, 0, ETH_ALEN);
3389 memset(wl->mac_addr, 0, ETH_ALEN);
3390 b43_upload_card_macaddress(dev);
3391 b43_security_init(dev);
3394 b43_set_status(dev, B43_STAT_INITIALIZED);
3403 if (phy->dyn_tssi_tbl)
3404 kfree(phy->tssi2dbm);
3405 err_kfree_lo_control:
3406 kfree(phy->lo_control);
3407 phy->lo_control = NULL;
3409 ssb_bus_may_powerdown(bus);
3410 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3414 static int b43_op_add_interface(struct ieee80211_hw *hw,
3415 struct ieee80211_if_init_conf *conf)
3417 struct b43_wl *wl = hw_to_b43_wl(hw);
3418 struct b43_wldev *dev;
3419 unsigned long flags;
3420 int err = -EOPNOTSUPP;
3422 /* TODO: allow WDS/AP devices to coexist */
3424 if (conf->type != IEEE80211_IF_TYPE_AP &&
3425 conf->type != IEEE80211_IF_TYPE_STA &&
3426 conf->type != IEEE80211_IF_TYPE_WDS &&
3427 conf->type != IEEE80211_IF_TYPE_IBSS)
3430 mutex_lock(&wl->mutex);
3432 goto out_mutex_unlock;
3434 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3436 dev = wl->current_dev;
3438 wl->if_id = conf->if_id;
3439 wl->if_type = conf->type;
3440 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3442 spin_lock_irqsave(&wl->irq_lock, flags);
3443 b43_adjust_opmode(dev);
3444 b43_upload_card_macaddress(dev);
3445 spin_unlock_irqrestore(&wl->irq_lock, flags);
3449 mutex_unlock(&wl->mutex);
3454 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3455 struct ieee80211_if_init_conf *conf)
3457 struct b43_wl *wl = hw_to_b43_wl(hw);
3458 struct b43_wldev *dev = wl->current_dev;
3459 unsigned long flags;
3461 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3463 mutex_lock(&wl->mutex);
3465 B43_WARN_ON(!wl->operating);
3466 B43_WARN_ON(wl->if_id != conf->if_id);
3470 spin_lock_irqsave(&wl->irq_lock, flags);
3471 b43_adjust_opmode(dev);
3472 memset(wl->mac_addr, 0, ETH_ALEN);
3473 b43_upload_card_macaddress(dev);
3474 spin_unlock_irqrestore(&wl->irq_lock, flags);
3476 mutex_unlock(&wl->mutex);
3479 static int b43_op_start(struct ieee80211_hw *hw)
3481 struct b43_wl *wl = hw_to_b43_wl(hw);
3482 struct b43_wldev *dev = wl->current_dev;
3486 /* First register RFkill.
3487 * LEDs that are registered later depend on it. */
3488 b43_rfkill_init(dev);
3490 mutex_lock(&wl->mutex);
3492 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3493 err = b43_wireless_core_init(dev);
3495 goto out_mutex_unlock;
3499 if (b43_status(dev) < B43_STAT_STARTED) {
3500 err = b43_wireless_core_start(dev);
3503 b43_wireless_core_exit(dev);
3504 goto out_mutex_unlock;
3509 mutex_unlock(&wl->mutex);
3514 static void b43_op_stop(struct ieee80211_hw *hw)
3516 struct b43_wl *wl = hw_to_b43_wl(hw);
3517 struct b43_wldev *dev = wl->current_dev;
3519 b43_rfkill_exit(dev);
3521 mutex_lock(&wl->mutex);
3522 if (b43_status(dev) >= B43_STAT_STARTED)
3523 b43_wireless_core_stop(dev);
3524 b43_wireless_core_exit(dev);
3525 mutex_unlock(&wl->mutex);
3528 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3529 u32 short_retry_limit, u32 long_retry_limit)
3531 struct b43_wl *wl = hw_to_b43_wl(hw);
3532 struct b43_wldev *dev;
3535 mutex_lock(&wl->mutex);
3536 dev = wl->current_dev;
3537 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3541 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3543 mutex_unlock(&wl->mutex);
3548 static const struct ieee80211_ops b43_hw_ops = {
3550 .conf_tx = b43_op_conf_tx,
3551 .add_interface = b43_op_add_interface,
3552 .remove_interface = b43_op_remove_interface,
3553 .config = b43_op_config,
3554 .config_interface = b43_op_config_interface,
3555 .configure_filter = b43_op_configure_filter,
3556 .set_key = b43_op_set_key,
3557 .get_stats = b43_op_get_stats,
3558 .get_tx_stats = b43_op_get_tx_stats,
3559 .start = b43_op_start,
3560 .stop = b43_op_stop,
3561 .set_retry_limit = b43_op_set_retry_limit,
3564 /* Hard-reset the chip. Do not call this directly.
3565 * Use b43_controller_restart()
3567 static void b43_chip_reset(struct work_struct *work)
3569 struct b43_wldev *dev =
3570 container_of(work, struct b43_wldev, restart_work);
3571 struct b43_wl *wl = dev->wl;
3575 mutex_lock(&wl->mutex);
3577 prev_status = b43_status(dev);
3578 /* Bring the device down... */
3579 if (prev_status >= B43_STAT_STARTED)
3580 b43_wireless_core_stop(dev);
3581 if (prev_status >= B43_STAT_INITIALIZED)
3582 b43_wireless_core_exit(dev);
3584 /* ...and up again. */
3585 if (prev_status >= B43_STAT_INITIALIZED) {
3586 err = b43_wireless_core_init(dev);
3590 if (prev_status >= B43_STAT_STARTED) {
3591 err = b43_wireless_core_start(dev);
3593 b43_wireless_core_exit(dev);
3598 mutex_unlock(&wl->mutex);
3600 b43err(wl, "Controller restart FAILED\n");
3602 b43info(wl, "Controller restarted\n");
3605 static int b43_setup_modes(struct b43_wldev *dev,
3606 int have_aphy, int have_bphy, int have_gphy)
3608 struct ieee80211_hw *hw = dev->wl->hw;
3609 struct ieee80211_hw_mode *mode;
3610 struct b43_phy *phy = &dev->phy;
3614 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3617 phy->possible_phymodes = 0;
3620 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3621 mode = &phy->hwmodes[cnt];
3623 mode->mode = MODE_IEEE80211A;
3624 mode->num_channels = b43_a_chantable_size;
3625 mode->channels = b43_a_chantable;
3626 mode->num_rates = b43_a_ratetable_size;
3627 mode->rates = b43_a_ratetable;
3628 err = ieee80211_register_hwmode(hw, mode);
3632 phy->possible_phymodes |= B43_PHYMODE_A;
3637 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3638 mode = &phy->hwmodes[cnt];
3640 mode->mode = MODE_IEEE80211B;
3641 mode->num_channels = b43_bg_chantable_size;
3642 mode->channels = b43_bg_chantable;
3643 mode->num_rates = b43_b_ratetable_size;
3644 mode->rates = b43_b_ratetable;
3645 err = ieee80211_register_hwmode(hw, mode);
3649 phy->possible_phymodes |= B43_PHYMODE_B;
3654 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3655 mode = &phy->hwmodes[cnt];
3657 mode->mode = MODE_IEEE80211G;
3658 mode->num_channels = b43_bg_chantable_size;
3659 mode->channels = b43_bg_chantable;
3660 mode->num_rates = b43_g_ratetable_size;
3661 mode->rates = b43_g_ratetable;
3662 err = ieee80211_register_hwmode(hw, mode);
3666 phy->possible_phymodes |= B43_PHYMODE_G;
3676 static void b43_wireless_core_detach(struct b43_wldev *dev)
3678 /* We release firmware that late to not be required to re-request
3679 * is all the time when we reinit the core. */
3680 b43_release_firmware(dev);
3683 static int b43_wireless_core_attach(struct b43_wldev *dev)
3685 struct b43_wl *wl = dev->wl;
3686 struct ssb_bus *bus = dev->dev->bus;
3687 struct pci_dev *pdev = bus->host_pci;
3689 int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3692 /* Do NOT do any device initialization here.
3693 * Do it in wireless_core_init() instead.
3694 * This function is for gathering basic information about the HW, only.
3695 * Also some structs may be set up here. But most likely you want to have
3696 * that in core_init(), too.
3699 err = ssb_bus_powerup(bus, 0);
3701 b43err(wl, "Bus powerup failed\n");
3704 /* Get the PHY type. */
3705 if (dev->dev->id.revision >= 5) {
3708 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3709 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3710 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3711 if (!have_aphy && !have_gphy)
3713 } else if (dev->dev->id.revision == 4) {
3719 dev->phy.gmode = (have_gphy || have_bphy);
3720 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3721 b43_wireless_core_reset(dev, tmp);
3723 err = b43_phy_versioning(dev);
3726 /* Check if this device supports multiband. */
3728 (pdev->device != 0x4312 &&
3729 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3730 /* No multiband support. */
3734 switch (dev->phy.type) {
3748 dev->phy.gmode = (have_gphy || have_bphy);
3749 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3750 b43_wireless_core_reset(dev, tmp);
3752 err = b43_validate_chipaccess(dev);
3755 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3759 /* Now set some default "current_dev" */
3760 if (!wl->current_dev)
3761 wl->current_dev = dev;
3762 INIT_WORK(&dev->restart_work, b43_chip_reset);
3764 b43_radio_turn_off(dev, 1);
3765 b43_switch_analog(dev, 0);
3766 ssb_device_disable(dev->dev, 0);
3767 ssb_bus_may_powerdown(bus);
3773 ssb_bus_may_powerdown(bus);
3777 static void b43_one_core_detach(struct ssb_device *dev)
3779 struct b43_wldev *wldev;
3782 wldev = ssb_get_drvdata(dev);
3784 cancel_work_sync(&wldev->restart_work);
3785 b43_debugfs_remove_device(wldev);
3786 b43_wireless_core_detach(wldev);
3787 list_del(&wldev->list);
3789 ssb_set_drvdata(dev, NULL);
3793 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3795 struct b43_wldev *wldev;
3796 struct pci_dev *pdev;
3799 if (!list_empty(&wl->devlist)) {
3800 /* We are not the first core on this chip. */
3801 pdev = dev->bus->host_pci;
3802 /* Only special chips support more than one wireless
3803 * core, although some of the other chips have more than
3804 * one wireless core as well. Check for this and
3808 ((pdev->device != 0x4321) &&
3809 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3810 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3815 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3821 b43_set_status(wldev, B43_STAT_UNINIT);
3822 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3823 tasklet_init(&wldev->isr_tasklet,
3824 (void (*)(unsigned long))b43_interrupt_tasklet,
3825 (unsigned long)wldev);
3826 INIT_LIST_HEAD(&wldev->list);
3828 err = b43_wireless_core_attach(wldev);
3830 goto err_kfree_wldev;
3832 list_add(&wldev->list, &wl->devlist);
3834 ssb_set_drvdata(dev, wldev);
3835 b43_debugfs_add_device(wldev);
3845 static void b43_sprom_fixup(struct ssb_bus *bus)
3847 /* boardflags workarounds */
3848 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3849 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3850 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3851 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3852 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3853 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3856 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3858 struct ieee80211_hw *hw = wl->hw;
3860 ssb_set_devtypedata(dev, NULL);
3861 ieee80211_free_hw(hw);
3864 static int b43_wireless_init(struct ssb_device *dev)
3866 struct ssb_sprom *sprom = &dev->bus->sprom;
3867 struct ieee80211_hw *hw;
3871 b43_sprom_fixup(dev->bus);
3873 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3875 b43err(NULL, "Could not allocate ieee80211 device\n");
3880 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3881 IEEE80211_HW_RX_INCLUDES_FCS;
3882 hw->max_signal = 100;
3883 hw->max_rssi = -110;
3884 hw->max_noise = -110;
3885 hw->queues = 1; /* FIXME: hardware has more queues */
3886 SET_IEEE80211_DEV(hw, dev->dev);
3887 if (is_valid_ether_addr(sprom->et1mac))
3888 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3890 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3892 /* Get and initialize struct b43_wl */
3893 wl = hw_to_b43_wl(hw);
3894 memset(wl, 0, sizeof(*wl));
3896 spin_lock_init(&wl->irq_lock);
3897 spin_lock_init(&wl->leds_lock);
3898 mutex_init(&wl->mutex);
3899 INIT_LIST_HEAD(&wl->devlist);
3901 ssb_set_devtypedata(dev, wl);
3902 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3908 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3914 wl = ssb_get_devtypedata(dev);
3916 /* Probing the first core. Must setup common struct b43_wl */
3918 err = b43_wireless_init(dev);
3921 wl = ssb_get_devtypedata(dev);
3924 err = b43_one_core_attach(dev, wl);
3926 goto err_wireless_exit;
3929 err = ieee80211_register_hw(wl->hw);
3931 goto err_one_core_detach;
3937 err_one_core_detach:
3938 b43_one_core_detach(dev);
3941 b43_wireless_exit(dev, wl);
3945 static void b43_remove(struct ssb_device *dev)
3947 struct b43_wl *wl = ssb_get_devtypedata(dev);
3948 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3951 if (wl->current_dev == wldev)
3952 ieee80211_unregister_hw(wl->hw);
3954 b43_one_core_detach(dev);
3956 if (list_empty(&wl->devlist)) {
3957 /* Last core on the chip unregistered.
3958 * We can destroy common struct b43_wl.
3960 b43_wireless_exit(dev, wl);
3964 /* Perform a hardware reset. This can be called from any context. */
3965 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3967 /* Must avoid requeueing, if we are in shutdown. */
3968 if (b43_status(dev) < B43_STAT_INITIALIZED)
3970 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3971 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3976 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
3978 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3979 struct b43_wl *wl = wldev->wl;
3981 b43dbg(wl, "Suspending...\n");
3983 mutex_lock(&wl->mutex);
3984 wldev->suspend_init_status = b43_status(wldev);
3985 if (wldev->suspend_init_status >= B43_STAT_STARTED)
3986 b43_wireless_core_stop(wldev);
3987 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
3988 b43_wireless_core_exit(wldev);
3989 mutex_unlock(&wl->mutex);
3991 b43dbg(wl, "Device suspended.\n");
3996 static int b43_resume(struct ssb_device *dev)
3998 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3999 struct b43_wl *wl = wldev->wl;
4002 b43dbg(wl, "Resuming...\n");
4004 mutex_lock(&wl->mutex);
4005 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4006 err = b43_wireless_core_init(wldev);
4008 b43err(wl, "Resume failed at core init\n");
4012 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4013 err = b43_wireless_core_start(wldev);
4015 b43_wireless_core_exit(wldev);
4016 b43err(wl, "Resume failed at core start\n");
4020 mutex_unlock(&wl->mutex);
4022 b43dbg(wl, "Device resumed.\n");
4027 #else /* CONFIG_PM */
4028 # define b43_suspend NULL
4029 # define b43_resume NULL
4030 #endif /* CONFIG_PM */
4032 static struct ssb_driver b43_ssb_driver = {
4033 .name = KBUILD_MODNAME,
4034 .id_table = b43_ssb_tbl,
4036 .remove = b43_remove,
4037 .suspend = b43_suspend,
4038 .resume = b43_resume,
4041 static int __init b43_init(void)
4046 err = b43_pcmcia_init();
4049 err = ssb_driver_register(&b43_ssb_driver);
4051 goto err_pcmcia_exit;
4062 static void __exit b43_exit(void)
4064 ssb_driver_unregister(&b43_ssb_driver);
4069 module_init(b43_init)
4070 module_exit(b43_exit)