3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
56 MODULE_AUTHOR("Martin Langer");
57 MODULE_AUTHOR("Stefano Brivio");
58 MODULE_AUTHOR("Michael Buesch");
59 MODULE_LICENSE("GPL");
61 extern char *nvram_get(char *name);
63 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
64 static int modparam_pio;
65 module_param_named(pio, modparam_pio, int, 0444);
66 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
67 #elif defined(CONFIG_B43_DMA)
68 # define modparam_pio 0
69 #elif defined(CONFIG_B43_PIO)
70 # define modparam_pio 1
73 static int modparam_bad_frames_preempt;
74 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
75 MODULE_PARM_DESC(bad_frames_preempt,
76 "enable(1) / disable(0) Bad Frames Preemption");
78 static char modparam_fwpostfix[16];
79 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
80 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
82 static int modparam_hwpctl;
83 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
84 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
86 static int modparam_nohwcrypt;
87 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
88 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
90 static const struct ssb_device_id b43_ssb_tbl[] = {
91 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
92 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
100 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
102 /* Channel and ratetables are shared for all devices.
103 * They can't be const, because ieee80211 puts some precalculated
104 * data in there. This data is the same for all devices, so we don't
105 * get concurrency issues */
106 #define RATETAB_ENT(_rateid, _flags) \
108 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
113 static struct ieee80211_rate __b43_ratetable[] = {
114 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
115 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
116 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
117 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
118 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
119 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
120 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
121 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
122 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
123 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
124 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
125 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
128 #define b43_a_ratetable (__b43_ratetable + 4)
129 #define b43_a_ratetable_size 8
130 #define b43_b_ratetable (__b43_ratetable + 0)
131 #define b43_b_ratetable_size 4
132 #define b43_g_ratetable (__b43_ratetable + 0)
133 #define b43_g_ratetable_size 12
135 #define CHANTAB_ENT(_chanid, _freq) \
140 .flag = IEEE80211_CHAN_W_SCAN | \
141 IEEE80211_CHAN_W_ACTIVE_SCAN | \
142 IEEE80211_CHAN_W_IBSS, \
143 .power_level = 0xFF, \
144 .antenna_max = 0xFF, \
146 static struct ieee80211_channel b43_bg_chantable[] = {
147 CHANTAB_ENT(1, 2412),
148 CHANTAB_ENT(2, 2417),
149 CHANTAB_ENT(3, 2422),
150 CHANTAB_ENT(4, 2427),
151 CHANTAB_ENT(5, 2432),
152 CHANTAB_ENT(6, 2437),
153 CHANTAB_ENT(7, 2442),
154 CHANTAB_ENT(8, 2447),
155 CHANTAB_ENT(9, 2452),
156 CHANTAB_ENT(10, 2457),
157 CHANTAB_ENT(11, 2462),
158 CHANTAB_ENT(12, 2467),
159 CHANTAB_ENT(13, 2472),
160 CHANTAB_ENT(14, 2484),
163 #define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable)
164 static struct ieee80211_channel b43_a_chantable[] = {
165 CHANTAB_ENT(36, 5180),
166 CHANTAB_ENT(40, 5200),
167 CHANTAB_ENT(44, 5220),
168 CHANTAB_ENT(48, 5240),
169 CHANTAB_ENT(52, 5260),
170 CHANTAB_ENT(56, 5280),
171 CHANTAB_ENT(60, 5300),
172 CHANTAB_ENT(64, 5320),
173 CHANTAB_ENT(149, 5745),
174 CHANTAB_ENT(153, 5765),
175 CHANTAB_ENT(157, 5785),
176 CHANTAB_ENT(161, 5805),
177 CHANTAB_ENT(165, 5825),
180 #define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable)
182 static void b43_wireless_core_exit(struct b43_wldev *dev);
183 static int b43_wireless_core_init(struct b43_wldev *dev);
184 static void b43_wireless_core_stop(struct b43_wldev *dev);
185 static int b43_wireless_core_start(struct b43_wldev *dev);
187 static int b43_ratelimit(struct b43_wl *wl)
189 if (!wl || !wl->current_dev)
191 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
193 /* We are up and running.
194 * Ratelimit the messages to avoid DoS over the net. */
195 return net_ratelimit();
198 void b43info(struct b43_wl *wl, const char *fmt, ...)
202 if (!b43_ratelimit(wl))
205 printk(KERN_INFO "b43-%s: ",
206 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
211 void b43err(struct b43_wl *wl, const char *fmt, ...)
215 if (!b43_ratelimit(wl))
218 printk(KERN_ERR "b43-%s ERROR: ",
219 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
224 void b43warn(struct b43_wl *wl, const char *fmt, ...)
228 if (!b43_ratelimit(wl))
231 printk(KERN_WARNING "b43-%s warning: ",
232 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
238 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
243 printk(KERN_DEBUG "b43-%s debug: ",
244 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
250 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
254 B43_WARN_ON(offset % 4 != 0);
256 macctl = b43_read32(dev, B43_MMIO_MACCTL);
257 if (macctl & B43_MACCTL_BE)
260 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
262 b43_write32(dev, B43_MMIO_RAM_DATA, val);
266 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
270 /* "offset" is the WORD offset. */
275 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
278 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
282 if (routing == B43_SHM_SHARED) {
283 B43_WARN_ON(offset & 0x0001);
284 if (offset & 0x0003) {
285 /* Unaligned access */
286 b43_shm_control_word(dev, routing, offset >> 2);
287 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
289 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
290 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
296 b43_shm_control_word(dev, routing, offset);
297 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
302 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
306 if (routing == B43_SHM_SHARED) {
307 B43_WARN_ON(offset & 0x0001);
308 if (offset & 0x0003) {
309 /* Unaligned access */
310 b43_shm_control_word(dev, routing, offset >> 2);
311 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
317 b43_shm_control_word(dev, routing, offset);
318 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
323 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
325 if (routing == B43_SHM_SHARED) {
326 B43_WARN_ON(offset & 0x0001);
327 if (offset & 0x0003) {
328 /* Unaligned access */
329 b43_shm_control_word(dev, routing, offset >> 2);
331 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
332 (value >> 16) & 0xffff);
334 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
336 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
341 b43_shm_control_word(dev, routing, offset);
343 b43_write32(dev, B43_MMIO_SHM_DATA, value);
346 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
348 if (routing == B43_SHM_SHARED) {
349 B43_WARN_ON(offset & 0x0001);
350 if (offset & 0x0003) {
351 /* Unaligned access */
352 b43_shm_control_word(dev, routing, offset >> 2);
354 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
359 b43_shm_control_word(dev, routing, offset);
361 b43_write16(dev, B43_MMIO_SHM_DATA, value);
365 u32 b43_hf_read(struct b43_wldev * dev)
369 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
371 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
376 /* Write HostFlags */
377 void b43_hf_write(struct b43_wldev *dev, u32 value)
379 b43_shm_write16(dev, B43_SHM_SHARED,
380 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
381 b43_shm_write16(dev, B43_SHM_SHARED,
382 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
385 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
387 /* We need to be careful. As we read the TSF from multiple
388 * registers, we should take care of register overflows.
389 * In theory, the whole tsf read process should be atomic.
390 * We try to be atomic here, by restaring the read process,
391 * if any of the high registers changed (overflew).
393 if (dev->dev->id.revision >= 3) {
394 u32 low, high, high2;
397 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
398 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
399 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
400 } while (unlikely(high != high2));
408 u16 test1, test2, test3;
411 v3 = b43_read16(dev, B43_MMIO_TSF_3);
412 v2 = b43_read16(dev, B43_MMIO_TSF_2);
413 v1 = b43_read16(dev, B43_MMIO_TSF_1);
414 v0 = b43_read16(dev, B43_MMIO_TSF_0);
416 test3 = b43_read16(dev, B43_MMIO_TSF_3);
417 test2 = b43_read16(dev, B43_MMIO_TSF_2);
418 test1 = b43_read16(dev, B43_MMIO_TSF_1);
419 } while (v3 != test3 || v2 != test2 || v1 != test1);
433 static void b43_time_lock(struct b43_wldev *dev)
437 macctl = b43_read32(dev, B43_MMIO_MACCTL);
438 macctl |= B43_MACCTL_TBTTHOLD;
439 b43_write32(dev, B43_MMIO_MACCTL, macctl);
440 /* Commit the write */
441 b43_read32(dev, B43_MMIO_MACCTL);
444 static void b43_time_unlock(struct b43_wldev *dev)
448 macctl = b43_read32(dev, B43_MMIO_MACCTL);
449 macctl &= ~B43_MACCTL_TBTTHOLD;
450 b43_write32(dev, B43_MMIO_MACCTL, macctl);
451 /* Commit the write */
452 b43_read32(dev, B43_MMIO_MACCTL);
455 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
457 /* Be careful with the in-progress timer.
458 * First zero out the low register, so we have a full
459 * register-overflow duration to complete the operation.
461 if (dev->dev->id.revision >= 3) {
462 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
463 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
465 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
467 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
469 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
471 u16 v0 = (tsf & 0x000000000000FFFFULL);
472 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
473 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
474 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
476 b43_write16(dev, B43_MMIO_TSF_0, 0);
478 b43_write16(dev, B43_MMIO_TSF_3, v3);
480 b43_write16(dev, B43_MMIO_TSF_2, v2);
482 b43_write16(dev, B43_MMIO_TSF_1, v1);
484 b43_write16(dev, B43_MMIO_TSF_0, v0);
488 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
491 b43_tsf_write_locked(dev, tsf);
492 b43_time_unlock(dev);
496 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
498 static const u8 zero_addr[ETH_ALEN] = { 0 };
505 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
509 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
512 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
515 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
518 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
522 u8 mac_bssid[ETH_ALEN * 2];
526 bssid = dev->wl->bssid;
527 mac = dev->wl->mac_addr;
529 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
531 memcpy(mac_bssid, mac, ETH_ALEN);
532 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
534 /* Write our MAC address and BSSID to template ram */
535 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
536 tmp = (u32) (mac_bssid[i + 0]);
537 tmp |= (u32) (mac_bssid[i + 1]) << 8;
538 tmp |= (u32) (mac_bssid[i + 2]) << 16;
539 tmp |= (u32) (mac_bssid[i + 3]) << 24;
540 b43_ram_write(dev, 0x20 + i, tmp);
544 static void b43_upload_card_macaddress(struct b43_wldev *dev)
546 b43_write_mac_bssid_templates(dev);
547 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
550 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
552 /* slot_time is in usec. */
553 if (dev->phy.type != B43_PHYTYPE_G)
555 b43_write16(dev, 0x684, 510 + slot_time);
556 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
559 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
561 b43_set_slot_time(dev, 9);
565 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
567 b43_set_slot_time(dev, 20);
571 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
572 * Returns the _previously_ enabled IRQ mask.
574 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
578 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
579 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
584 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
585 * Returns the _previously_ enabled IRQ mask.
587 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
591 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
592 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
597 /* Synchronize IRQ top- and bottom-half.
598 * IRQs must be masked before calling this.
599 * This must not be called with the irq_lock held.
601 static void b43_synchronize_irq(struct b43_wldev *dev)
603 synchronize_irq(dev->dev->irq);
604 tasklet_kill(&dev->isr_tasklet);
607 /* DummyTransmission function, as documented on
608 * http://bcm-specs.sipsolutions.net/DummyTransmission
610 void b43_dummy_transmission(struct b43_wldev *dev)
612 struct b43_phy *phy = &dev->phy;
613 unsigned int i, max_loop;
626 buffer[0] = 0x000201CC;
631 buffer[0] = 0x000B846E;
638 for (i = 0; i < 5; i++)
639 b43_ram_write(dev, i * 4, buffer[i]);
642 b43_read32(dev, B43_MMIO_MACCTL);
644 b43_write16(dev, 0x0568, 0x0000);
645 b43_write16(dev, 0x07C0, 0x0000);
646 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
647 b43_write16(dev, 0x050C, value);
648 b43_write16(dev, 0x0508, 0x0000);
649 b43_write16(dev, 0x050A, 0x0000);
650 b43_write16(dev, 0x054C, 0x0000);
651 b43_write16(dev, 0x056A, 0x0014);
652 b43_write16(dev, 0x0568, 0x0826);
653 b43_write16(dev, 0x0500, 0x0000);
654 b43_write16(dev, 0x0502, 0x0030);
656 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
657 b43_radio_write16(dev, 0x0051, 0x0017);
658 for (i = 0x00; i < max_loop; i++) {
659 value = b43_read16(dev, 0x050E);
664 for (i = 0x00; i < 0x0A; i++) {
665 value = b43_read16(dev, 0x050E);
670 for (i = 0x00; i < 0x0A; i++) {
671 value = b43_read16(dev, 0x0690);
672 if (!(value & 0x0100))
676 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
677 b43_radio_write16(dev, 0x0051, 0x0037);
680 static void key_write(struct b43_wldev *dev,
681 u8 index, u8 algorithm, const u8 * key)
688 /* Key index/algo block */
689 kidx = b43_kidx_to_fw(dev, index);
690 value = ((kidx << 4) | algorithm);
691 b43_shm_write16(dev, B43_SHM_SHARED,
692 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
694 /* Write the key to the Key Table Pointer offset */
695 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
696 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
698 value |= (u16) (key[i + 1]) << 8;
699 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
703 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
705 u32 addrtmp[2] = { 0, 0, };
706 u8 per_sta_keys_start = 8;
708 if (b43_new_kidx_api(dev))
709 per_sta_keys_start = 4;
711 B43_WARN_ON(index < per_sta_keys_start);
712 /* We have two default TX keys and possibly two default RX keys.
713 * Physical mac 0 is mapped to physical key 4 or 8, depending
714 * on the firmware version.
715 * So we must adjust the index here.
717 index -= per_sta_keys_start;
720 addrtmp[0] = addr[0];
721 addrtmp[0] |= ((u32) (addr[1]) << 8);
722 addrtmp[0] |= ((u32) (addr[2]) << 16);
723 addrtmp[0] |= ((u32) (addr[3]) << 24);
724 addrtmp[1] = addr[4];
725 addrtmp[1] |= ((u32) (addr[5]) << 8);
728 if (dev->dev->id.revision >= 5) {
729 /* Receive match transmitter address mechanism */
730 b43_shm_write32(dev, B43_SHM_RCMTA,
731 (index * 2) + 0, addrtmp[0]);
732 b43_shm_write16(dev, B43_SHM_RCMTA,
733 (index * 2) + 1, addrtmp[1]);
735 /* RXE (Receive Engine) and
736 * PSM (Programmable State Machine) mechanism
739 /* TODO write to RCM 16, 19, 22 and 25 */
741 b43_shm_write32(dev, B43_SHM_SHARED,
742 B43_SHM_SH_PSM + (index * 6) + 0,
744 b43_shm_write16(dev, B43_SHM_SHARED,
745 B43_SHM_SH_PSM + (index * 6) + 4,
751 static void do_key_write(struct b43_wldev *dev,
752 u8 index, u8 algorithm,
753 const u8 * key, size_t key_len, const u8 * mac_addr)
755 u8 buf[B43_SEC_KEYSIZE] = { 0, };
756 u8 per_sta_keys_start = 8;
758 if (b43_new_kidx_api(dev))
759 per_sta_keys_start = 4;
761 B43_WARN_ON(index >= dev->max_nr_keys);
762 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
764 if (index >= per_sta_keys_start)
765 keymac_write(dev, index, NULL); /* First zero out mac. */
767 memcpy(buf, key, key_len);
768 key_write(dev, index, algorithm, buf);
769 if (index >= per_sta_keys_start)
770 keymac_write(dev, index, mac_addr);
772 dev->key[index].algorithm = algorithm;
775 static int b43_key_write(struct b43_wldev *dev,
776 int index, u8 algorithm,
777 const u8 * key, size_t key_len,
779 struct ieee80211_key_conf *keyconf)
784 if (key_len > B43_SEC_KEYSIZE)
786 for (i = 0; i < dev->max_nr_keys; i++) {
787 /* Check that we don't already have this key. */
788 B43_WARN_ON(dev->key[i].keyconf == keyconf);
791 /* Either pairwise key or address is 00:00:00:00:00:00
792 * for transmit-only keys. Search the index. */
793 if (b43_new_kidx_api(dev))
797 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
798 if (!dev->key[i].keyconf) {
805 b43err(dev->wl, "Out of hardware key memory\n");
809 B43_WARN_ON(index > 3);
811 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
812 if ((index <= 3) && !b43_new_kidx_api(dev)) {
814 B43_WARN_ON(mac_addr);
815 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
817 keyconf->hw_key_idx = index;
818 dev->key[index].keyconf = keyconf;
823 static int b43_key_clear(struct b43_wldev *dev, int index)
825 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
827 do_key_write(dev, index, B43_SEC_ALGO_NONE,
828 NULL, B43_SEC_KEYSIZE, NULL);
829 if ((index <= 3) && !b43_new_kidx_api(dev)) {
830 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
831 NULL, B43_SEC_KEYSIZE, NULL);
833 dev->key[index].keyconf = NULL;
838 static void b43_clear_keys(struct b43_wldev *dev)
842 for (i = 0; i < dev->max_nr_keys; i++)
843 b43_key_clear(dev, i);
846 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
854 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
855 (ps_flags & B43_PS_DISABLED));
856 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
858 if (ps_flags & B43_PS_ENABLED) {
860 } else if (ps_flags & B43_PS_DISABLED) {
863 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
864 // and thus is not an AP and we are associated, set bit 25
866 if (ps_flags & B43_PS_AWAKE) {
868 } else if (ps_flags & B43_PS_ASLEEP) {
871 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
872 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
873 // successful, set bit26
876 /* FIXME: For now we force awake-on and hwps-off */
880 macctl = b43_read32(dev, B43_MMIO_MACCTL);
882 macctl |= B43_MACCTL_HWPS;
884 macctl &= ~B43_MACCTL_HWPS;
886 macctl |= B43_MACCTL_AWAKE;
888 macctl &= ~B43_MACCTL_AWAKE;
889 b43_write32(dev, B43_MMIO_MACCTL, macctl);
891 b43_read32(dev, B43_MMIO_MACCTL);
892 if (awake && dev->dev->id.revision >= 5) {
893 /* Wait for the microcode to wake up. */
894 for (i = 0; i < 100; i++) {
895 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
896 B43_SHM_SH_UCODESTAT);
897 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
904 /* Turn the Analog ON/OFF */
905 static void b43_switch_analog(struct b43_wldev *dev, int on)
907 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
910 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
915 flags |= B43_TMSLOW_PHYCLKEN;
916 flags |= B43_TMSLOW_PHYRESET;
917 ssb_device_enable(dev->dev, flags);
918 msleep(2); /* Wait for the PLL to turn on. */
920 /* Now take the PHY out of Reset again */
921 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
922 tmslow |= SSB_TMSLOW_FGC;
923 tmslow &= ~B43_TMSLOW_PHYRESET;
924 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
925 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
927 tmslow &= ~SSB_TMSLOW_FGC;
928 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
929 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
933 b43_switch_analog(dev, 1);
935 macctl = b43_read32(dev, B43_MMIO_MACCTL);
936 macctl &= ~B43_MACCTL_GMODE;
937 if (flags & B43_TMSLOW_GMODE)
938 macctl |= B43_MACCTL_GMODE;
939 macctl |= B43_MACCTL_IHR_ENABLED;
940 b43_write32(dev, B43_MMIO_MACCTL, macctl);
943 static void handle_irq_transmit_status(struct b43_wldev *dev)
947 struct b43_txstatus stat;
950 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
951 if (!(v0 & 0x00000001))
953 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
955 stat.cookie = (v0 >> 16);
956 stat.seq = (v1 & 0x0000FFFF);
957 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
958 tmp = (v0 & 0x0000FFFF);
959 stat.frame_count = ((tmp & 0xF000) >> 12);
960 stat.rts_count = ((tmp & 0x0F00) >> 8);
961 stat.supp_reason = ((tmp & 0x001C) >> 2);
962 stat.pm_indicated = !!(tmp & 0x0080);
963 stat.intermediate = !!(tmp & 0x0040);
964 stat.for_ampdu = !!(tmp & 0x0020);
965 stat.acked = !!(tmp & 0x0002);
967 b43_handle_txstatus(dev, &stat);
971 static void drain_txstatus_queue(struct b43_wldev *dev)
975 if (dev->dev->id.revision < 5)
977 /* Read all entries from the microcode TXstatus FIFO
978 * and throw them away.
981 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
982 if (!(dummy & 0x00000001))
984 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
988 static u32 b43_jssi_read(struct b43_wldev *dev)
992 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
994 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
999 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1001 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1002 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1005 static void b43_generate_noise_sample(struct b43_wldev *dev)
1007 b43_jssi_write(dev, 0x7F7F7F7F);
1008 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1009 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1011 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1014 static void b43_calculate_link_quality(struct b43_wldev *dev)
1016 /* Top half of Link Quality calculation. */
1018 if (dev->noisecalc.calculation_running)
1020 dev->noisecalc.channel_at_start = dev->phy.channel;
1021 dev->noisecalc.calculation_running = 1;
1022 dev->noisecalc.nr_samples = 0;
1024 b43_generate_noise_sample(dev);
1027 static void handle_irq_noise(struct b43_wldev *dev)
1029 struct b43_phy *phy = &dev->phy;
1035 /* Bottom half of Link Quality calculation. */
1037 B43_WARN_ON(!dev->noisecalc.calculation_running);
1038 if (dev->noisecalc.channel_at_start != phy->channel)
1039 goto drop_calculation;
1040 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1041 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1042 noise[2] == 0x7F || noise[3] == 0x7F)
1045 /* Get the noise samples. */
1046 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1047 i = dev->noisecalc.nr_samples;
1048 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1049 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1050 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1051 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1052 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1053 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1054 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1055 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1056 dev->noisecalc.nr_samples++;
1057 if (dev->noisecalc.nr_samples == 8) {
1058 /* Calculate the Link Quality by the noise samples. */
1060 for (i = 0; i < 8; i++) {
1061 for (j = 0; j < 4; j++)
1062 average += dev->noisecalc.samples[i][j];
1068 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1069 tmp = (tmp / 128) & 0x1F;
1079 dev->stats.link_noise = average;
1081 dev->noisecalc.calculation_running = 0;
1085 b43_generate_noise_sample(dev);
1088 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1090 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1093 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1094 b43_power_saving_ctl_bits(dev, 0);
1096 dev->reg124_set_0x4 = 0;
1097 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1098 dev->reg124_set_0x4 = 1;
1101 static void handle_irq_atim_end(struct b43_wldev *dev)
1103 if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1105 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1106 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1110 static void handle_irq_pmq(struct b43_wldev *dev)
1117 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1118 if (!(tmp & 0x00000008))
1121 /* 16bit write is odd, but correct. */
1122 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1125 static void b43_write_template_common(struct b43_wldev *dev,
1126 const u8 * data, u16 size,
1128 u16 shm_size_offset, u8 rate)
1131 struct b43_plcp_hdr4 plcp;
1134 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1135 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1136 ram_offset += sizeof(u32);
1137 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1138 * So leave the first two bytes of the next write blank.
1140 tmp = (u32) (data[0]) << 16;
1141 tmp |= (u32) (data[1]) << 24;
1142 b43_ram_write(dev, ram_offset, tmp);
1143 ram_offset += sizeof(u32);
1144 for (i = 2; i < size; i += sizeof(u32)) {
1145 tmp = (u32) (data[i + 0]);
1147 tmp |= (u32) (data[i + 1]) << 8;
1149 tmp |= (u32) (data[i + 2]) << 16;
1151 tmp |= (u32) (data[i + 3]) << 24;
1152 b43_ram_write(dev, ram_offset + i - 2, tmp);
1154 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1155 size + sizeof(struct b43_plcp_hdr6));
1158 static void b43_write_beacon_template(struct b43_wldev *dev,
1160 u16 shm_size_offset, u8 rate)
1165 B43_WARN_ON(!dev->cached_beacon);
1166 len = min((size_t) dev->cached_beacon->len,
1167 0x200 - sizeof(struct b43_plcp_hdr6));
1168 data = (const u8 *)(dev->cached_beacon->data);
1169 b43_write_template_common(dev, data,
1170 len, ram_offset, shm_size_offset, rate);
1173 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1174 u16 shm_offset, u16 size, u8 rate)
1176 struct b43_plcp_hdr4 plcp;
1181 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1182 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1183 dev->wl->if_id, size,
1184 B43_RATE_TO_BASE100KBPS(rate));
1185 /* Write PLCP in two parts and timing for packet transfer */
1186 tmp = le32_to_cpu(plcp.data);
1187 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1188 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1189 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1192 /* Instead of using custom probe response template, this function
1193 * just patches custom beacon template by:
1194 * 1) Changing packet type
1195 * 2) Patching duration field
1198 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1199 u16 * dest_size, u8 rate)
1203 u16 src_size, elem_size, src_pos, dest_pos;
1205 struct ieee80211_hdr *hdr;
1207 B43_WARN_ON(!dev->cached_beacon);
1208 src_size = dev->cached_beacon->len;
1209 src_data = (const u8 *)dev->cached_beacon->data;
1211 if (unlikely(src_size < 0x24)) {
1212 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1216 dest_data = kmalloc(src_size, GFP_ATOMIC);
1217 if (unlikely(!dest_data))
1220 /* 0x24 is offset of first variable-len Information-Element
1223 memcpy(dest_data, src_data, 0x24);
1224 src_pos = dest_pos = 0x24;
1225 for (; src_pos < src_size - 2; src_pos += elem_size) {
1226 elem_size = src_data[src_pos + 1] + 2;
1227 if (src_data[src_pos] != 0x05) { /* TIM */
1228 memcpy(dest_data + dest_pos, src_data + src_pos,
1230 dest_pos += elem_size;
1233 *dest_size = dest_pos;
1234 hdr = (struct ieee80211_hdr *)dest_data;
1236 /* Set the frame control. */
1237 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1238 IEEE80211_STYPE_PROBE_RESP);
1239 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1240 dev->wl->if_id, *dest_size,
1241 B43_RATE_TO_BASE100KBPS(rate));
1242 hdr->duration_id = dur;
1247 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1249 u16 shm_size_offset, u8 rate)
1251 u8 *probe_resp_data;
1254 B43_WARN_ON(!dev->cached_beacon);
1255 size = dev->cached_beacon->len;
1256 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1257 if (unlikely(!probe_resp_data))
1260 /* Looks like PLCP headers plus packet timings are stored for
1261 * all possible basic rates
1263 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1264 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1265 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1266 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1268 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1269 b43_write_template_common(dev, probe_resp_data,
1270 size, ram_offset, shm_size_offset, rate);
1271 kfree(probe_resp_data);
1274 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1275 struct sk_buff *beacon)
1277 if (dev->cached_beacon)
1278 kfree_skb(dev->cached_beacon);
1279 dev->cached_beacon = beacon;
1284 static void b43_update_templates(struct b43_wldev *dev)
1288 B43_WARN_ON(!dev->cached_beacon);
1290 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1291 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1292 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1294 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1296 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1299 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1303 err = b43_refresh_cached_beacon(dev, beacon);
1306 b43_update_templates(dev);
1309 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1314 len = min((u16) ssid_len, (u16) 0x100);
1315 for (i = 0; i < len; i += sizeof(u32)) {
1316 tmp = (u32) (ssid[i + 0]);
1318 tmp |= (u32) (ssid[i + 1]) << 8;
1320 tmp |= (u32) (ssid[i + 2]) << 16;
1322 tmp |= (u32) (ssid[i + 3]) << 24;
1323 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1325 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1328 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1331 if (dev->dev->id.revision >= 3) {
1332 b43_write32(dev, 0x188, (beacon_int << 16));
1334 b43_write16(dev, 0x606, (beacon_int >> 6));
1335 b43_write16(dev, 0x610, beacon_int);
1337 b43_time_unlock(dev);
1340 static void handle_irq_beacon(struct b43_wldev *dev)
1344 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1347 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1348 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1350 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1351 /* ACK beacon IRQ. */
1352 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1353 dev->irq_savedstate |= B43_IRQ_BEACON;
1354 if (dev->cached_beacon)
1355 kfree_skb(dev->cached_beacon);
1356 dev->cached_beacon = NULL;
1359 if (!(status & 0x1)) {
1360 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1362 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1364 if (!(status & 0x2)) {
1365 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1367 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1371 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1376 /* Interrupt handler bottom-half */
1377 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1380 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1381 u32 merged_dma_reason = 0;
1383 unsigned long flags;
1385 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1387 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1389 reason = dev->irq_reason;
1390 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1391 dma_reason[i] = dev->dma_reason[i];
1392 merged_dma_reason |= dma_reason[i];
1395 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1396 b43err(dev->wl, "MAC transmission error\n");
1398 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1399 b43err(dev->wl, "PHY transmission error\n");
1401 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1402 atomic_set(&dev->phy.txerr_cnt,
1403 B43_PHY_TX_BADNESS_LIMIT);
1404 b43err(dev->wl, "Too many PHY TX errors, "
1405 "restarting the controller\n");
1406 b43_controller_restart(dev, "PHY TX errors");
1410 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1411 B43_DMAIRQ_NONFATALMASK))) {
1412 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1413 b43err(dev->wl, "Fatal DMA error: "
1414 "0x%08X, 0x%08X, 0x%08X, "
1415 "0x%08X, 0x%08X, 0x%08X\n",
1416 dma_reason[0], dma_reason[1],
1417 dma_reason[2], dma_reason[3],
1418 dma_reason[4], dma_reason[5]);
1419 b43_controller_restart(dev, "DMA error");
1421 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1424 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1425 b43err(dev->wl, "DMA error: "
1426 "0x%08X, 0x%08X, 0x%08X, "
1427 "0x%08X, 0x%08X, 0x%08X\n",
1428 dma_reason[0], dma_reason[1],
1429 dma_reason[2], dma_reason[3],
1430 dma_reason[4], dma_reason[5]);
1434 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1435 handle_irq_ucode_debug(dev);
1436 if (reason & B43_IRQ_TBTT_INDI)
1437 handle_irq_tbtt_indication(dev);
1438 if (reason & B43_IRQ_ATIM_END)
1439 handle_irq_atim_end(dev);
1440 if (reason & B43_IRQ_BEACON)
1441 handle_irq_beacon(dev);
1442 if (reason & B43_IRQ_PMQ)
1443 handle_irq_pmq(dev);
1444 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1446 if (reason & B43_IRQ_NOISESAMPLE_OK)
1447 handle_irq_noise(dev);
1449 /* Check the DMA reason registers for received data. */
1450 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1451 if (b43_using_pio(dev))
1452 b43_pio_rx(dev->pio.queue0);
1454 b43_dma_rx(dev->dma.rx_ring0);
1456 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1457 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1458 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1459 if (b43_using_pio(dev))
1460 b43_pio_rx(dev->pio.queue3);
1462 b43_dma_rx(dev->dma.rx_ring3);
1464 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1465 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1467 if (reason & B43_IRQ_TX_OK)
1468 handle_irq_transmit_status(dev);
1470 b43_interrupt_enable(dev, dev->irq_savedstate);
1472 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1475 static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1479 rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1480 if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1481 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1483 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1486 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1488 if (b43_using_pio(dev) &&
1489 (dev->dev->id.revision < 3) &&
1490 (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1491 /* Apply a PIO specific workaround to the dma_reasons */
1492 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1493 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1494 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1495 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1498 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1500 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1501 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1502 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1503 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1504 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1505 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1508 /* Interrupt handler top-half */
1509 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1511 irqreturn_t ret = IRQ_NONE;
1512 struct b43_wldev *dev = dev_id;
1518 spin_lock(&dev->wl->irq_lock);
1520 if (b43_status(dev) < B43_STAT_STARTED)
1522 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1523 if (reason == 0xffffffff) /* shared IRQ */
1526 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1530 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1532 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1534 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1536 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1538 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1540 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1543 b43_interrupt_ack(dev, reason);
1544 /* disable all IRQs. They are enabled again in the bottom half. */
1545 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1546 /* save the reason code and call our bottom half. */
1547 dev->irq_reason = reason;
1548 tasklet_schedule(&dev->isr_tasklet);
1551 spin_unlock(&dev->wl->irq_lock);
1556 static void b43_release_firmware(struct b43_wldev *dev)
1558 release_firmware(dev->fw.ucode);
1559 dev->fw.ucode = NULL;
1560 release_firmware(dev->fw.pcm);
1562 release_firmware(dev->fw.initvals);
1563 dev->fw.initvals = NULL;
1564 release_firmware(dev->fw.initvals_band);
1565 dev->fw.initvals_band = NULL;
1568 static void b43_print_fw_helptext(struct b43_wl *wl)
1570 b43err(wl, "You must go to "
1571 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1572 "and download the correct firmware (version 4).\n");
1575 static int do_request_fw(struct b43_wldev *dev,
1577 const struct firmware **fw)
1579 char path[sizeof(modparam_fwpostfix) + 32];
1580 struct b43_fw_header *hdr;
1587 snprintf(path, ARRAY_SIZE(path),
1589 modparam_fwpostfix, name);
1590 err = request_firmware(fw, path, dev->dev->dev);
1592 b43err(dev->wl, "Firmware file \"%s\" not found "
1593 "or load failed.\n", path);
1596 if ((*fw)->size < sizeof(struct b43_fw_header))
1598 hdr = (struct b43_fw_header *)((*fw)->data);
1599 switch (hdr->type) {
1600 case B43_FW_TYPE_UCODE:
1601 case B43_FW_TYPE_PCM:
1602 size = be32_to_cpu(hdr->size);
1603 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1606 case B43_FW_TYPE_IV:
1617 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1621 static int b43_request_firmware(struct b43_wldev *dev)
1623 struct b43_firmware *fw = &dev->fw;
1624 const u8 rev = dev->dev->id.revision;
1625 const char *filename;
1629 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1631 if ((rev >= 5) && (rev <= 10))
1632 filename = "ucode5";
1633 else if ((rev >= 11) && (rev <= 12))
1634 filename = "ucode11";
1636 filename = "ucode13";
1639 err = do_request_fw(dev, filename, &fw->ucode);
1644 if ((rev >= 5) && (rev <= 10))
1650 err = do_request_fw(dev, filename, &fw->pcm);
1654 if (!fw->initvals) {
1655 switch (dev->phy.type) {
1657 if ((rev >= 5) && (rev <= 10)) {
1658 if (tmshigh & B43_TMSHIGH_GPHY)
1659 filename = "a0g1initvals5";
1661 filename = "a0g0initvals5";
1663 goto err_no_initvals;
1666 if ((rev >= 5) && (rev <= 10))
1667 filename = "b0g0initvals5";
1669 filename = "lp0initvals13";
1671 goto err_no_initvals;
1674 goto err_no_initvals;
1676 err = do_request_fw(dev, filename, &fw->initvals);
1680 if (!fw->initvals_band) {
1681 switch (dev->phy.type) {
1683 if ((rev >= 5) && (rev <= 10)) {
1684 if (tmshigh & B43_TMSHIGH_GPHY)
1685 filename = "a0g1bsinitvals5";
1687 filename = "a0g0bsinitvals5";
1688 } else if (rev >= 11)
1691 goto err_no_initvals;
1694 if ((rev >= 5) && (rev <= 10))
1695 filename = "b0g0bsinitvals5";
1699 goto err_no_initvals;
1702 goto err_no_initvals;
1704 err = do_request_fw(dev, filename, &fw->initvals_band);
1712 b43_print_fw_helptext(dev->wl);
1717 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1722 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1727 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1728 "core rev %u\n", dev->phy.type, rev);
1732 b43_release_firmware(dev);
1736 static int b43_upload_microcode(struct b43_wldev *dev)
1738 const size_t hdr_len = sizeof(struct b43_fw_header);
1740 unsigned int i, len;
1741 u16 fwrev, fwpatch, fwdate, fwtime;
1745 /* Upload Microcode. */
1746 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1747 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1748 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1749 for (i = 0; i < len; i++) {
1750 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1755 /* Upload PCM data. */
1756 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1757 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1758 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1759 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1760 /* No need for autoinc bit in SHM_HW */
1761 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1762 for (i = 0; i < len; i++) {
1763 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1768 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1769 b43_write32(dev, B43_MMIO_MACCTL,
1770 B43_MACCTL_PSM_RUN |
1771 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1773 /* Wait for the microcode to load and respond */
1776 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1777 if (tmp == B43_IRQ_MAC_SUSPENDED)
1781 b43err(dev->wl, "Microcode not responding\n");
1782 b43_print_fw_helptext(dev->wl);
1788 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1790 /* Get and check the revisions. */
1791 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1792 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1793 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1794 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1796 if (fwrev <= 0x128) {
1797 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1798 "binary drivers older than version 4.x is unsupported. "
1799 "You must upgrade your firmware files.\n");
1800 b43_print_fw_helptext(dev->wl);
1801 b43_write32(dev, B43_MMIO_MACCTL, 0);
1805 b43dbg(dev->wl, "Loading firmware version %u.%u "
1806 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1808 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1809 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1811 dev->fw.rev = fwrev;
1812 dev->fw.patch = fwpatch;
1818 static int b43_write_initvals(struct b43_wldev *dev,
1819 const struct b43_iv *ivals,
1823 const struct b43_iv *iv;
1828 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1830 for (i = 0; i < count; i++) {
1831 if (array_size < sizeof(iv->offset_size))
1833 array_size -= sizeof(iv->offset_size);
1834 offset = be16_to_cpu(iv->offset_size);
1835 bit32 = !!(offset & B43_IV_32BIT);
1836 offset &= B43_IV_OFFSET_MASK;
1837 if (offset >= 0x1000)
1842 if (array_size < sizeof(iv->data.d32))
1844 array_size -= sizeof(iv->data.d32);
1846 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1847 b43_write32(dev, offset, value);
1849 iv = (const struct b43_iv *)((const uint8_t *)iv +
1855 if (array_size < sizeof(iv->data.d16))
1857 array_size -= sizeof(iv->data.d16);
1859 value = be16_to_cpu(iv->data.d16);
1860 b43_write16(dev, offset, value);
1862 iv = (const struct b43_iv *)((const uint8_t *)iv +
1873 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1874 b43_print_fw_helptext(dev->wl);
1879 static int b43_upload_initvals(struct b43_wldev *dev)
1881 const size_t hdr_len = sizeof(struct b43_fw_header);
1882 const struct b43_fw_header *hdr;
1883 struct b43_firmware *fw = &dev->fw;
1884 const struct b43_iv *ivals;
1888 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1889 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1890 count = be32_to_cpu(hdr->size);
1891 err = b43_write_initvals(dev, ivals, count,
1892 fw->initvals->size - hdr_len);
1895 if (fw->initvals_band) {
1896 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1897 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1898 count = be32_to_cpu(hdr->size);
1899 err = b43_write_initvals(dev, ivals, count,
1900 fw->initvals_band->size - hdr_len);
1909 /* Initialize the GPIOs
1910 * http://bcm-specs.sipsolutions.net/GPIO
1912 static int b43_gpio_init(struct b43_wldev *dev)
1914 struct ssb_bus *bus = dev->dev->bus;
1915 struct ssb_device *gpiodev, *pcidev = NULL;
1918 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1919 & ~B43_MACCTL_GPOUTSMSK);
1921 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1926 if (dev->dev->bus->chip_id == 0x4301) {
1930 if (0 /* FIXME: conditional unknown */ ) {
1931 b43_write16(dev, B43_MMIO_GPIO_MASK,
1932 b43_read16(dev, B43_MMIO_GPIO_MASK)
1937 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1938 b43_write16(dev, B43_MMIO_GPIO_MASK,
1939 b43_read16(dev, B43_MMIO_GPIO_MASK)
1944 if (dev->dev->id.revision >= 2)
1945 mask |= 0x0010; /* FIXME: This is redundant. */
1947 #ifdef CONFIG_SSB_DRIVER_PCICORE
1948 pcidev = bus->pcicore.dev;
1950 gpiodev = bus->chipco.dev ? : pcidev;
1953 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1954 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1960 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1961 static void b43_gpio_cleanup(struct b43_wldev *dev)
1963 struct ssb_bus *bus = dev->dev->bus;
1964 struct ssb_device *gpiodev, *pcidev = NULL;
1966 #ifdef CONFIG_SSB_DRIVER_PCICORE
1967 pcidev = bus->pcicore.dev;
1969 gpiodev = bus->chipco.dev ? : pcidev;
1972 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1975 /* http://bcm-specs.sipsolutions.net/EnableMac */
1976 void b43_mac_enable(struct b43_wldev *dev)
1978 dev->mac_suspended--;
1979 B43_WARN_ON(dev->mac_suspended < 0);
1980 B43_WARN_ON(irqs_disabled());
1981 if (dev->mac_suspended == 0) {
1982 b43_write32(dev, B43_MMIO_MACCTL,
1983 b43_read32(dev, B43_MMIO_MACCTL)
1984 | B43_MACCTL_ENABLED);
1985 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1986 B43_IRQ_MAC_SUSPENDED);
1988 b43_read32(dev, B43_MMIO_MACCTL);
1989 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1990 b43_power_saving_ctl_bits(dev, 0);
1992 /* Re-enable IRQs. */
1993 spin_lock_irq(&dev->wl->irq_lock);
1994 b43_interrupt_enable(dev, dev->irq_savedstate);
1995 spin_unlock_irq(&dev->wl->irq_lock);
1999 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2000 void b43_mac_suspend(struct b43_wldev *dev)
2006 B43_WARN_ON(irqs_disabled());
2007 B43_WARN_ON(dev->mac_suspended < 0);
2009 if (dev->mac_suspended == 0) {
2010 /* Mask IRQs before suspending MAC. Otherwise
2011 * the MAC stays busy and won't suspend. */
2012 spin_lock_irq(&dev->wl->irq_lock);
2013 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2014 spin_unlock_irq(&dev->wl->irq_lock);
2015 b43_synchronize_irq(dev);
2016 dev->irq_savedstate = tmp;
2018 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2019 b43_write32(dev, B43_MMIO_MACCTL,
2020 b43_read32(dev, B43_MMIO_MACCTL)
2021 & ~B43_MACCTL_ENABLED);
2022 /* force pci to flush the write */
2023 b43_read32(dev, B43_MMIO_MACCTL);
2024 for (i = 40; i; i--) {
2025 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2026 if (tmp & B43_IRQ_MAC_SUSPENDED)
2030 b43err(dev->wl, "MAC suspend failed\n");
2033 dev->mac_suspended++;
2036 static void b43_adjust_opmode(struct b43_wldev *dev)
2038 struct b43_wl *wl = dev->wl;
2042 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2043 /* Reset status to STA infrastructure mode. */
2044 ctl &= ~B43_MACCTL_AP;
2045 ctl &= ~B43_MACCTL_KEEP_CTL;
2046 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2047 ctl &= ~B43_MACCTL_KEEP_BAD;
2048 ctl &= ~B43_MACCTL_PROMISC;
2049 ctl &= ~B43_MACCTL_BEACPROMISC;
2050 ctl |= B43_MACCTL_INFRA;
2052 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2053 ctl |= B43_MACCTL_AP;
2054 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2055 ctl &= ~B43_MACCTL_INFRA;
2057 if (wl->filter_flags & FIF_CONTROL)
2058 ctl |= B43_MACCTL_KEEP_CTL;
2059 if (wl->filter_flags & FIF_FCSFAIL)
2060 ctl |= B43_MACCTL_KEEP_BAD;
2061 if (wl->filter_flags & FIF_PLCPFAIL)
2062 ctl |= B43_MACCTL_KEEP_BADPLCP;
2063 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2064 ctl |= B43_MACCTL_PROMISC;
2065 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2066 ctl |= B43_MACCTL_BEACPROMISC;
2068 /* Workaround: On old hardware the HW-MAC-address-filter
2069 * doesn't work properly, so always run promisc in filter
2070 * it in software. */
2071 if (dev->dev->id.revision <= 4)
2072 ctl |= B43_MACCTL_PROMISC;
2074 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2077 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2078 if (dev->dev->bus->chip_id == 0x4306 &&
2079 dev->dev->bus->chip_rev == 3)
2084 b43_write16(dev, 0x612, cfp_pretbtt);
2087 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2093 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2096 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2098 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2099 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2102 static void b43_rate_memory_init(struct b43_wldev *dev)
2104 switch (dev->phy.type) {
2107 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2108 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2109 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2110 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2111 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2112 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2113 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2114 if (dev->phy.type == B43_PHYTYPE_A)
2118 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2119 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2120 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2121 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2128 /* Set the TX-Antenna for management frames sent by firmware. */
2129 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2136 ant |= B43_TX4_PHY_ANT0;
2139 ant |= B43_TX4_PHY_ANT1;
2141 case B43_ANTENNA_AUTO:
2142 ant |= B43_TX4_PHY_ANTLAST;
2148 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2151 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2152 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2153 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2155 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2156 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2157 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2158 /* For Probe Resposes */
2159 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2160 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2161 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2164 /* This is the opposite of b43_chip_init() */
2165 static void b43_chip_exit(struct b43_wldev *dev)
2167 b43_radio_turn_off(dev, 1);
2168 b43_gpio_cleanup(dev);
2169 /* firmware is released later */
2172 /* Initialize the chip
2173 * http://bcm-specs.sipsolutions.net/ChipInit
2175 static int b43_chip_init(struct b43_wldev *dev)
2177 struct b43_phy *phy = &dev->phy;
2182 b43_write32(dev, B43_MMIO_MACCTL,
2183 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2185 err = b43_request_firmware(dev);
2188 err = b43_upload_microcode(dev);
2190 goto out; /* firmware is released later */
2192 err = b43_gpio_init(dev);
2194 goto out; /* firmware is released later */
2196 err = b43_upload_initvals(dev);
2198 goto err_gpio_clean;
2199 b43_radio_turn_on(dev);
2201 b43_write16(dev, 0x03E6, 0x0000);
2202 err = b43_phy_init(dev);
2206 /* Select initial Interference Mitigation. */
2207 tmp = phy->interfmode;
2208 phy->interfmode = B43_INTERFMODE_NONE;
2209 b43_radio_set_interference_mitigation(dev, tmp);
2211 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2212 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2214 if (phy->type == B43_PHYTYPE_B) {
2215 value16 = b43_read16(dev, 0x005E);
2217 b43_write16(dev, 0x005E, value16);
2219 b43_write32(dev, 0x0100, 0x01000000);
2220 if (dev->dev->id.revision < 5)
2221 b43_write32(dev, 0x010C, 0x01000000);
2223 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2224 & ~B43_MACCTL_INFRA);
2225 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2226 | B43_MACCTL_INFRA);
2228 if (b43_using_pio(dev)) {
2229 b43_write32(dev, 0x0210, 0x00000100);
2230 b43_write32(dev, 0x0230, 0x00000100);
2231 b43_write32(dev, 0x0250, 0x00000100);
2232 b43_write32(dev, 0x0270, 0x00000100);
2233 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2236 /* Probe Response Timeout value */
2237 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2238 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2240 /* Initially set the wireless operation mode. */
2241 b43_adjust_opmode(dev);
2243 if (dev->dev->id.revision < 3) {
2244 b43_write16(dev, 0x060E, 0x0000);
2245 b43_write16(dev, 0x0610, 0x8000);
2246 b43_write16(dev, 0x0604, 0x0000);
2247 b43_write16(dev, 0x0606, 0x0200);
2249 b43_write32(dev, 0x0188, 0x80000000);
2250 b43_write32(dev, 0x018C, 0x02000000);
2252 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2253 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2254 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2255 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2256 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2257 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2258 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2260 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2261 value32 |= 0x00100000;
2262 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2264 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2265 dev->dev->bus->chipco.fast_pwrup_delay);
2268 b43dbg(dev->wl, "Chip initialized\n");
2273 b43_radio_turn_off(dev, 1);
2275 b43_gpio_cleanup(dev);
2279 static void b43_periodic_every120sec(struct b43_wldev *dev)
2281 struct b43_phy *phy = &dev->phy;
2283 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2286 b43_mac_suspend(dev);
2287 b43_lo_g_measure(dev);
2288 b43_mac_enable(dev);
2289 if (b43_has_hardware_pctl(phy))
2290 b43_lo_g_ctl_mark_all_unused(dev);
2293 static void b43_periodic_every60sec(struct b43_wldev *dev)
2295 struct b43_phy *phy = &dev->phy;
2297 if (!b43_has_hardware_pctl(phy))
2298 b43_lo_g_ctl_mark_all_unused(dev);
2299 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2300 b43_mac_suspend(dev);
2301 b43_calc_nrssi_slope(dev);
2302 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2303 u8 old_chan = phy->channel;
2305 /* VCO Calibration */
2307 b43_radio_selectchannel(dev, 1, 0);
2309 b43_radio_selectchannel(dev, 13, 0);
2310 b43_radio_selectchannel(dev, old_chan, 0);
2312 b43_mac_enable(dev);
2316 static void b43_periodic_every30sec(struct b43_wldev *dev)
2318 /* Update device statistics. */
2319 b43_calculate_link_quality(dev);
2322 static void b43_periodic_every15sec(struct b43_wldev *dev)
2324 struct b43_phy *phy = &dev->phy;
2326 if (phy->type == B43_PHYTYPE_G) {
2327 //TODO: update_aci_moving_average
2328 if (phy->aci_enable && phy->aci_wlan_automatic) {
2329 b43_mac_suspend(dev);
2330 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2331 if (0 /*TODO: bunch of conditions */ ) {
2332 b43_radio_set_interference_mitigation
2333 (dev, B43_INTERFMODE_MANUALWLAN);
2335 } else if (1 /*TODO*/) {
2337 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2338 b43_radio_set_interference_mitigation(dev,
2339 B43_INTERFMODE_NONE);
2343 b43_mac_enable(dev);
2344 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2346 //TODO: implement rev1 workaround
2349 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2350 //TODO for APHY (temperature?)
2352 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2356 static void do_periodic_work(struct b43_wldev *dev)
2360 state = dev->periodic_state;
2362 b43_periodic_every120sec(dev);
2364 b43_periodic_every60sec(dev);
2366 b43_periodic_every30sec(dev);
2367 b43_periodic_every15sec(dev);
2370 /* Periodic work locking policy:
2371 * The whole periodic work handler is protected by
2372 * wl->mutex. If another lock is needed somewhere in the
2373 * pwork callchain, it's aquired in-place, where it's needed.
2375 static void b43_periodic_work_handler(struct work_struct *work)
2377 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2378 periodic_work.work);
2379 struct b43_wl *wl = dev->wl;
2380 unsigned long delay;
2382 mutex_lock(&wl->mutex);
2384 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2386 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2389 do_periodic_work(dev);
2391 dev->periodic_state++;
2393 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2394 delay = msecs_to_jiffies(50);
2396 delay = round_jiffies_relative(HZ * 15);
2397 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2399 mutex_unlock(&wl->mutex);
2402 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2404 struct delayed_work *work = &dev->periodic_work;
2406 dev->periodic_state = 0;
2407 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2408 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2411 /* Validate access to the chip (SHM) */
2412 static int b43_validate_chipaccess(struct b43_wldev *dev)
2417 shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2418 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2419 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2421 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2422 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2424 b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2426 value = b43_read32(dev, B43_MMIO_MACCTL);
2427 if ((value | B43_MACCTL_GMODE) !=
2428 (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2431 value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2437 b43err(dev->wl, "Failed to validate the chipaccess\n");
2441 static void b43_security_init(struct b43_wldev *dev)
2443 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2444 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2445 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2446 /* KTP is a word address, but we address SHM bytewise.
2447 * So multiply by two.
2450 if (dev->dev->id.revision >= 5) {
2451 /* Number of RCMTA address slots */
2452 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2454 b43_clear_keys(dev);
2457 static int b43_rng_read(struct hwrng *rng, u32 * data)
2459 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2460 unsigned long flags;
2462 /* Don't take wl->mutex here, as it could deadlock with
2463 * hwrng internal locking. It's not needed to take
2464 * wl->mutex here, anyway. */
2466 spin_lock_irqsave(&wl->irq_lock, flags);
2467 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2468 spin_unlock_irqrestore(&wl->irq_lock, flags);
2470 return (sizeof(u16));
2473 static void b43_rng_exit(struct b43_wl *wl)
2475 if (wl->rng_initialized)
2476 hwrng_unregister(&wl->rng);
2479 static int b43_rng_init(struct b43_wl *wl)
2483 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2484 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2485 wl->rng.name = wl->rng_name;
2486 wl->rng.data_read = b43_rng_read;
2487 wl->rng.priv = (unsigned long)wl;
2488 wl->rng_initialized = 1;
2489 err = hwrng_register(&wl->rng);
2491 wl->rng_initialized = 0;
2492 b43err(wl, "Failed to register the random "
2493 "number generator (%d)\n", err);
2499 static int b43_op_tx(struct ieee80211_hw *hw,
2500 struct sk_buff *skb,
2501 struct ieee80211_tx_control *ctl)
2503 struct b43_wl *wl = hw_to_b43_wl(hw);
2504 struct b43_wldev *dev = wl->current_dev;
2506 unsigned long flags;
2510 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2512 /* DMA-TX is done without a global lock. */
2513 if (b43_using_pio(dev)) {
2514 spin_lock_irqsave(&wl->irq_lock, flags);
2515 err = b43_pio_tx(dev, skb, ctl);
2516 spin_unlock_irqrestore(&wl->irq_lock, flags);
2518 err = b43_dma_tx(dev, skb, ctl);
2521 return NETDEV_TX_BUSY;
2522 return NETDEV_TX_OK;
2525 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2527 const struct ieee80211_tx_queue_params *params)
2532 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2533 struct ieee80211_tx_queue_stats *stats)
2535 struct b43_wl *wl = hw_to_b43_wl(hw);
2536 struct b43_wldev *dev = wl->current_dev;
2537 unsigned long flags;
2542 spin_lock_irqsave(&wl->irq_lock, flags);
2543 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2544 if (b43_using_pio(dev))
2545 b43_pio_get_tx_stats(dev, stats);
2547 b43_dma_get_tx_stats(dev, stats);
2550 spin_unlock_irqrestore(&wl->irq_lock, flags);
2555 static int b43_op_get_stats(struct ieee80211_hw *hw,
2556 struct ieee80211_low_level_stats *stats)
2558 struct b43_wl *wl = hw_to_b43_wl(hw);
2559 unsigned long flags;
2561 spin_lock_irqsave(&wl->irq_lock, flags);
2562 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2563 spin_unlock_irqrestore(&wl->irq_lock, flags);
2568 static const char *phymode_to_string(unsigned int phymode)
2583 static int find_wldev_for_phymode(struct b43_wl *wl,
2584 unsigned int phymode,
2585 struct b43_wldev **dev, bool * gmode)
2587 struct b43_wldev *d;
2589 list_for_each_entry(d, &wl->devlist, list) {
2590 if (d->phy.possible_phymodes & phymode) {
2591 /* Ok, this device supports the PHY-mode.
2592 * Now figure out how the gmode bit has to be
2593 * set to support it. */
2594 if (phymode == B43_PHYMODE_A)
2607 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2609 struct ssb_device *sdev = dev->dev;
2612 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2613 tmslow &= ~B43_TMSLOW_GMODE;
2614 tmslow |= B43_TMSLOW_PHYRESET;
2615 tmslow |= SSB_TMSLOW_FGC;
2616 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2619 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2620 tmslow &= ~SSB_TMSLOW_FGC;
2621 tmslow |= B43_TMSLOW_PHYRESET;
2622 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2626 /* Expects wl->mutex locked */
2627 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2629 struct b43_wldev *up_dev;
2630 struct b43_wldev *down_dev;
2635 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2637 b43err(wl, "Could not find a device for %s-PHY mode\n",
2638 phymode_to_string(new_mode));
2641 if ((up_dev == wl->current_dev) &&
2642 (!!wl->current_dev->phy.gmode == !!gmode)) {
2643 /* This device is already running. */
2646 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2647 phymode_to_string(new_mode));
2648 down_dev = wl->current_dev;
2650 prev_status = b43_status(down_dev);
2651 /* Shutdown the currently running core. */
2652 if (prev_status >= B43_STAT_STARTED)
2653 b43_wireless_core_stop(down_dev);
2654 if (prev_status >= B43_STAT_INITIALIZED)
2655 b43_wireless_core_exit(down_dev);
2657 if (down_dev != up_dev) {
2658 /* We switch to a different core, so we put PHY into
2659 * RESET on the old core. */
2660 b43_put_phy_into_reset(down_dev);
2663 /* Now start the new core. */
2664 up_dev->phy.gmode = gmode;
2665 if (prev_status >= B43_STAT_INITIALIZED) {
2666 err = b43_wireless_core_init(up_dev);
2668 b43err(wl, "Fatal: Could not initialize device for "
2669 "newly selected %s-PHY mode\n",
2670 phymode_to_string(new_mode));
2674 if (prev_status >= B43_STAT_STARTED) {
2675 err = b43_wireless_core_start(up_dev);
2677 b43err(wl, "Fatal: Coult not start device for "
2678 "newly selected %s-PHY mode\n",
2679 phymode_to_string(new_mode));
2680 b43_wireless_core_exit(up_dev);
2684 B43_WARN_ON(b43_status(up_dev) != prev_status);
2686 wl->current_dev = up_dev;
2690 /* Whoops, failed to init the new core. No core is operating now. */
2691 wl->current_dev = NULL;
2695 /* Check if the use of the antenna that ieee80211 told us to
2696 * use is possible. This will fall back to DEFAULT.
2697 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2698 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2703 if (antenna_nr == 0) {
2704 /* Zero means "use default antenna". That's always OK. */
2708 /* Get the mask of available antennas. */
2710 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2712 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2714 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2715 /* This antenna is not available. Fall back to default. */
2722 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2724 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2726 case 0: /* default/diversity */
2727 return B43_ANTENNA_DEFAULT;
2728 case 1: /* Antenna 0 */
2729 return B43_ANTENNA0;
2730 case 2: /* Antenna 1 */
2731 return B43_ANTENNA1;
2733 return B43_ANTENNA_DEFAULT;
2737 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2739 struct b43_wl *wl = hw_to_b43_wl(hw);
2740 struct b43_wldev *dev;
2741 struct b43_phy *phy;
2742 unsigned long flags;
2743 unsigned int new_phymode = 0xFFFF;
2748 mutex_lock(&wl->mutex);
2750 /* Switch the PHY mode (if necessary). */
2751 switch (conf->phymode) {
2752 case MODE_IEEE80211A:
2753 new_phymode = B43_PHYMODE_A;
2755 case MODE_IEEE80211B:
2756 new_phymode = B43_PHYMODE_B;
2758 case MODE_IEEE80211G:
2759 new_phymode = B43_PHYMODE_G;
2764 err = b43_switch_phymode(wl, new_phymode);
2766 goto out_unlock_mutex;
2767 dev = wl->current_dev;
2770 /* Disable IRQs while reconfiguring the device.
2771 * This makes it possible to drop the spinlock throughout
2772 * the reconfiguration process. */
2773 spin_lock_irqsave(&wl->irq_lock, flags);
2774 if (b43_status(dev) < B43_STAT_STARTED) {
2775 spin_unlock_irqrestore(&wl->irq_lock, flags);
2776 goto out_unlock_mutex;
2778 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2779 spin_unlock_irqrestore(&wl->irq_lock, flags);
2780 b43_synchronize_irq(dev);
2782 /* Switch to the requested channel.
2783 * The firmware takes care of races with the TX handler. */
2784 if (conf->channel_val != phy->channel)
2785 b43_radio_selectchannel(dev, conf->channel_val, 0);
2787 /* Enable/Disable ShortSlot timing. */
2788 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2790 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2791 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2792 b43_short_slot_timing_enable(dev);
2794 b43_short_slot_timing_disable(dev);
2797 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2799 /* Adjust the desired TX power level. */
2800 if (conf->power_level != 0) {
2801 if (conf->power_level != phy->power_level) {
2802 phy->power_level = conf->power_level;
2803 b43_phy_xmitpower(dev);
2807 /* Antennas for RX and management frame TX. */
2808 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2809 b43_mgmtframe_txantenna(dev, antenna);
2810 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2811 b43_set_rx_antenna(dev, antenna);
2813 /* Update templates for AP mode. */
2814 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2815 b43_set_beacon_int(dev, conf->beacon_int);
2817 if (!!conf->radio_enabled != phy->radio_on) {
2818 if (conf->radio_enabled) {
2819 b43_radio_turn_on(dev);
2820 b43info(dev->wl, "Radio turned on by software\n");
2821 if (!dev->radio_hw_enable) {
2822 b43info(dev->wl, "The hardware RF-kill button "
2823 "still turns the radio physically off. "
2824 "Press the button to turn it on.\n");
2827 b43_radio_turn_off(dev, 0);
2828 b43info(dev->wl, "Radio turned off by software\n");
2832 spin_lock_irqsave(&wl->irq_lock, flags);
2833 b43_interrupt_enable(dev, savedirqs);
2835 spin_unlock_irqrestore(&wl->irq_lock, flags);
2837 mutex_unlock(&wl->mutex);
2842 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2843 const u8 *local_addr, const u8 *addr,
2844 struct ieee80211_key_conf *key)
2846 struct b43_wl *wl = hw_to_b43_wl(hw);
2847 struct b43_wldev *dev;
2848 unsigned long flags;
2852 DECLARE_MAC_BUF(mac);
2854 if (modparam_nohwcrypt)
2855 return -ENOSPC; /* User disabled HW-crypto */
2857 mutex_lock(&wl->mutex);
2858 spin_lock_irqsave(&wl->irq_lock, flags);
2860 dev = wl->current_dev;
2862 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2868 if (key->keylen == 5)
2869 algorithm = B43_SEC_ALGO_WEP40;
2871 algorithm = B43_SEC_ALGO_WEP104;
2874 algorithm = B43_SEC_ALGO_TKIP;
2877 algorithm = B43_SEC_ALGO_AES;
2883 index = (u8) (key->keyidx);
2889 if (algorithm == B43_SEC_ALGO_TKIP) {
2890 /* FIXME: No TKIP hardware encryption for now. */
2895 if (is_broadcast_ether_addr(addr)) {
2896 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2897 err = b43_key_write(dev, index, algorithm,
2898 key->key, key->keylen, NULL, key);
2901 * either pairwise key or address is 00:00:00:00:00:00
2902 * for transmit-only keys
2904 err = b43_key_write(dev, -1, algorithm,
2905 key->key, key->keylen, addr, key);
2910 if (algorithm == B43_SEC_ALGO_WEP40 ||
2911 algorithm == B43_SEC_ALGO_WEP104) {
2912 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2915 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2917 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2920 err = b43_key_clear(dev, key->hw_key_idx);
2929 spin_unlock_irqrestore(&wl->irq_lock, flags);
2930 mutex_unlock(&wl->mutex);
2932 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2934 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2935 print_mac(mac, addr));
2940 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2941 unsigned int changed, unsigned int *fflags,
2942 int mc_count, struct dev_addr_list *mc_list)
2944 struct b43_wl *wl = hw_to_b43_wl(hw);
2945 struct b43_wldev *dev = wl->current_dev;
2946 unsigned long flags;
2953 spin_lock_irqsave(&wl->irq_lock, flags);
2954 *fflags &= FIF_PROMISC_IN_BSS |
2960 FIF_BCN_PRBRESP_PROMISC;
2962 changed &= FIF_PROMISC_IN_BSS |
2968 FIF_BCN_PRBRESP_PROMISC;
2970 wl->filter_flags = *fflags;
2972 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2973 b43_adjust_opmode(dev);
2974 spin_unlock_irqrestore(&wl->irq_lock, flags);
2977 static int b43_op_config_interface(struct ieee80211_hw *hw,
2979 struct ieee80211_if_conf *conf)
2981 struct b43_wl *wl = hw_to_b43_wl(hw);
2982 struct b43_wldev *dev = wl->current_dev;
2983 unsigned long flags;
2987 mutex_lock(&wl->mutex);
2988 spin_lock_irqsave(&wl->irq_lock, flags);
2989 B43_WARN_ON(wl->if_id != if_id);
2991 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2993 memset(wl->bssid, 0, ETH_ALEN);
2994 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2995 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2996 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2997 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2999 b43_refresh_templates(dev, conf->beacon);
3001 b43_write_mac_bssid_templates(dev);
3003 spin_unlock_irqrestore(&wl->irq_lock, flags);
3004 mutex_unlock(&wl->mutex);
3009 /* Locking: wl->mutex */
3010 static void b43_wireless_core_stop(struct b43_wldev *dev)
3012 struct b43_wl *wl = dev->wl;
3013 unsigned long flags;
3015 if (b43_status(dev) < B43_STAT_STARTED)
3018 /* Disable and sync interrupts. We must do this before than
3019 * setting the status to INITIALIZED, as the interrupt handler
3020 * won't care about IRQs then. */
3021 spin_lock_irqsave(&wl->irq_lock, flags);
3022 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3023 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3024 spin_unlock_irqrestore(&wl->irq_lock, flags);
3025 b43_synchronize_irq(dev);
3027 b43_set_status(dev, B43_STAT_INITIALIZED);
3029 mutex_unlock(&wl->mutex);
3030 /* Must unlock as it would otherwise deadlock. No races here.
3031 * Cancel the possibly running self-rearming periodic work. */
3032 cancel_delayed_work_sync(&dev->periodic_work);
3033 mutex_lock(&wl->mutex);
3035 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3037 b43_mac_suspend(dev);
3038 free_irq(dev->dev->irq, dev);
3039 b43dbg(wl, "Wireless interface stopped\n");
3042 /* Locking: wl->mutex */
3043 static int b43_wireless_core_start(struct b43_wldev *dev)
3047 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3049 drain_txstatus_queue(dev);
3050 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3051 IRQF_SHARED, KBUILD_MODNAME, dev);
3053 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3057 /* We are ready to run. */
3058 b43_set_status(dev, B43_STAT_STARTED);
3060 /* Start data flow (TX/RX). */
3061 b43_mac_enable(dev);
3062 b43_interrupt_enable(dev, dev->irq_savedstate);
3063 ieee80211_start_queues(dev->wl->hw);
3065 /* Start maintainance work */
3066 b43_periodic_tasks_setup(dev);
3068 b43dbg(dev->wl, "Wireless interface started\n");
3073 /* Get PHY and RADIO versioning numbers */
3074 static int b43_phy_versioning(struct b43_wldev *dev)
3076 struct b43_phy *phy = &dev->phy;
3084 int unsupported = 0;
3086 /* Get PHY versioning */
3087 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3088 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3089 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3090 phy_rev = (tmp & B43_PHYVER_VERSION);
3097 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3109 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3110 "(Analog %u, Type %u, Revision %u)\n",
3111 analog_type, phy_type, phy_rev);
3114 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3115 analog_type, phy_type, phy_rev);
3117 /* Get RADIO versioning */
3118 if (dev->dev->bus->chip_id == 0x4317) {
3119 if (dev->dev->bus->chip_rev == 0)
3121 else if (dev->dev->bus->chip_rev == 1)
3126 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3127 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3129 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3130 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3132 radio_manuf = (tmp & 0x00000FFF);
3133 radio_ver = (tmp & 0x0FFFF000) >> 12;
3134 radio_rev = (tmp & 0xF0000000) >> 28;
3137 if (radio_ver != 0x2060)
3141 if (radio_manuf != 0x17F)
3145 if ((radio_ver & 0xFFF0) != 0x2050)
3149 if (radio_ver != 0x2050)
3156 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3157 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3158 radio_manuf, radio_ver, radio_rev);
3161 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3162 radio_manuf, radio_ver, radio_rev);
3164 phy->radio_manuf = radio_manuf;
3165 phy->radio_ver = radio_ver;
3166 phy->radio_rev = radio_rev;
3168 phy->analog = analog_type;
3169 phy->type = phy_type;
3175 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3176 struct b43_phy *phy)
3178 struct b43_txpower_lo_control *lo;
3181 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3182 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3187 phy->aci_enable = 0;
3188 phy->aci_wlan_automatic = 0;
3189 phy->aci_hw_rssi = 0;
3191 phy->radio_off_context.valid = 0;
3193 lo = phy->lo_control;
3195 memset(lo, 0, sizeof(*(phy->lo_control)));
3199 phy->max_lb_gain = 0;
3200 phy->trsw_rx_gain = 0;
3201 phy->txpwr_offset = 0;
3204 phy->nrssislope = 0;
3205 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3206 phy->nrssi[i] = -1000;
3207 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3208 phy->nrssi_lt[i] = i;
3210 phy->lofcal = 0xFFFF;
3211 phy->initval = 0xFFFF;
3213 spin_lock_init(&phy->lock);
3214 phy->interfmode = B43_INTERFMODE_NONE;
3215 phy->channel = 0xFF;
3217 phy->hardware_power_control = !!modparam_hwpctl;
3219 /* PHY TX errors counter. */
3220 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3222 /* OFDM-table address caching. */
3223 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3226 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3229 dev->reg124_set_0x4 = 0;
3230 /* Assume the radio is enabled. If it's not enabled, the state will
3231 * immediately get fixed on the first periodic work run. */
3232 dev->radio_hw_enable = 1;
3235 memset(&dev->stats, 0, sizeof(dev->stats));
3237 setup_struct_phy_for_init(dev, &dev->phy);
3239 /* IRQ related flags */
3240 dev->irq_reason = 0;
3241 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3242 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3244 dev->mac_suspended = 1;
3246 /* Noise calculation context */
3247 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3250 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3252 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3255 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3257 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3260 hf = b43_hf_read(dev);
3261 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3262 hf |= B43_HF_BTCOEXALT;
3264 hf |= B43_HF_BTCOEX;
3265 b43_hf_write(dev, hf);
3269 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3273 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3275 #ifdef CONFIG_SSB_DRIVER_PCICORE
3276 struct ssb_bus *bus = dev->dev->bus;
3279 if (bus->pcicore.dev &&
3280 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3281 bus->pcicore.dev->id.revision <= 5) {
3282 /* IMCFGLO timeouts workaround. */
3283 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3284 tmp &= ~SSB_IMCFGLO_REQTO;
3285 tmp &= ~SSB_IMCFGLO_SERTO;
3286 switch (bus->bustype) {
3287 case SSB_BUSTYPE_PCI:
3288 case SSB_BUSTYPE_PCMCIA:
3291 case SSB_BUSTYPE_SSB:
3295 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3297 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3300 /* Write the short and long frame retry limit values. */
3301 static void b43_set_retry_limits(struct b43_wldev *dev,
3302 unsigned int short_retry,
3303 unsigned int long_retry)
3305 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3306 * the chip-internal counter. */
3307 short_retry = min(short_retry, (unsigned int)0xF);
3308 long_retry = min(long_retry, (unsigned int)0xF);
3310 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3312 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3316 /* Shutdown a wireless core */
3317 /* Locking: wl->mutex */
3318 static void b43_wireless_core_exit(struct b43_wldev *dev)
3320 struct b43_phy *phy = &dev->phy;
3322 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3323 if (b43_status(dev) != B43_STAT_INITIALIZED)
3325 b43_set_status(dev, B43_STAT_UNINIT);
3328 b43_rng_exit(dev->wl);
3332 b43_radio_turn_off(dev, 1);
3333 b43_switch_analog(dev, 0);
3334 if (phy->dyn_tssi_tbl)
3335 kfree(phy->tssi2dbm);
3336 kfree(phy->lo_control);
3337 phy->lo_control = NULL;
3338 ssb_device_disable(dev->dev, 0);
3339 ssb_bus_may_powerdown(dev->dev->bus);
3342 /* Initialize a wireless core */
3343 static int b43_wireless_core_init(struct b43_wldev *dev)
3345 struct b43_wl *wl = dev->wl;
3346 struct ssb_bus *bus = dev->dev->bus;
3347 struct ssb_sprom *sprom = &bus->sprom;
3348 struct b43_phy *phy = &dev->phy;
3352 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3354 err = ssb_bus_powerup(bus, 0);
3357 if (!ssb_device_is_enabled(dev->dev)) {
3358 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3359 b43_wireless_core_reset(dev, tmp);
3362 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3364 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3365 if (!phy->lo_control) {
3370 setup_struct_wldev_for_init(dev);
3372 err = b43_phy_init_tssi2dbm_table(dev);
3374 goto err_kfree_lo_control;
3376 /* Enable IRQ routing to this device. */
3377 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3379 b43_imcfglo_timeouts_workaround(dev);
3380 b43_bluetooth_coext_disable(dev);
3381 b43_phy_early_init(dev);
3382 err = b43_chip_init(dev);
3384 goto err_kfree_tssitbl;
3385 b43_shm_write16(dev, B43_SHM_SHARED,
3386 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3387 hf = b43_hf_read(dev);
3388 if (phy->type == B43_PHYTYPE_G) {
3392 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3393 hf |= B43_HF_OFDMPABOOST;
3394 } else if (phy->type == B43_PHYTYPE_B) {
3396 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3399 b43_hf_write(dev, hf);
3401 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3402 B43_DEFAULT_LONG_RETRY_LIMIT);
3403 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3404 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3406 /* Disable sending probe responses from firmware.
3407 * Setting the MaxTime to one usec will always trigger
3408 * a timeout, so we never send any probe resp.
3409 * A timeout of zero is infinite. */
3410 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3412 b43_rate_memory_init(dev);
3414 /* Minimum Contention Window */
3415 if (phy->type == B43_PHYTYPE_B) {
3416 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3418 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3420 /* Maximum Contention Window */
3421 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3424 if (b43_using_pio(dev)) {
3425 err = b43_pio_init(dev);
3427 err = b43_dma_init(dev);
3431 } while (err == -EAGAIN);
3437 b43_write16(dev, 0x0612, 0x0050);
3438 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3439 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3442 b43_bluetooth_coext_enable(dev);
3444 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3445 memset(wl->bssid, 0, ETH_ALEN);
3446 memset(wl->mac_addr, 0, ETH_ALEN);
3447 b43_upload_card_macaddress(dev);
3448 b43_security_init(dev);
3451 b43_set_status(dev, B43_STAT_INITIALIZED);
3460 if (phy->dyn_tssi_tbl)
3461 kfree(phy->tssi2dbm);
3462 err_kfree_lo_control:
3463 kfree(phy->lo_control);
3464 phy->lo_control = NULL;
3466 ssb_bus_may_powerdown(bus);
3467 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3471 static int b43_op_add_interface(struct ieee80211_hw *hw,
3472 struct ieee80211_if_init_conf *conf)
3474 struct b43_wl *wl = hw_to_b43_wl(hw);
3475 struct b43_wldev *dev;
3476 unsigned long flags;
3477 int err = -EOPNOTSUPP;
3479 /* TODO: allow WDS/AP devices to coexist */
3481 if (conf->type != IEEE80211_IF_TYPE_AP &&
3482 conf->type != IEEE80211_IF_TYPE_STA &&
3483 conf->type != IEEE80211_IF_TYPE_WDS &&
3484 conf->type != IEEE80211_IF_TYPE_IBSS)
3487 mutex_lock(&wl->mutex);
3489 goto out_mutex_unlock;
3491 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3493 dev = wl->current_dev;
3495 wl->if_id = conf->if_id;
3496 wl->if_type = conf->type;
3497 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3499 spin_lock_irqsave(&wl->irq_lock, flags);
3500 b43_adjust_opmode(dev);
3501 b43_upload_card_macaddress(dev);
3502 spin_unlock_irqrestore(&wl->irq_lock, flags);
3506 mutex_unlock(&wl->mutex);
3511 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3512 struct ieee80211_if_init_conf *conf)
3514 struct b43_wl *wl = hw_to_b43_wl(hw);
3515 struct b43_wldev *dev = wl->current_dev;
3516 unsigned long flags;
3518 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3520 mutex_lock(&wl->mutex);
3522 B43_WARN_ON(!wl->operating);
3523 B43_WARN_ON(wl->if_id != conf->if_id);
3527 spin_lock_irqsave(&wl->irq_lock, flags);
3528 b43_adjust_opmode(dev);
3529 memset(wl->mac_addr, 0, ETH_ALEN);
3530 b43_upload_card_macaddress(dev);
3531 spin_unlock_irqrestore(&wl->irq_lock, flags);
3533 mutex_unlock(&wl->mutex);
3536 static int b43_op_start(struct ieee80211_hw *hw)
3538 struct b43_wl *wl = hw_to_b43_wl(hw);
3539 struct b43_wldev *dev = wl->current_dev;
3543 /* First register RFkill.
3544 * LEDs that are registered later depend on it. */
3545 b43_rfkill_init(dev);
3547 mutex_lock(&wl->mutex);
3549 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3550 err = b43_wireless_core_init(dev);
3552 goto out_mutex_unlock;
3556 if (b43_status(dev) < B43_STAT_STARTED) {
3557 err = b43_wireless_core_start(dev);
3560 b43_wireless_core_exit(dev);
3561 goto out_mutex_unlock;
3566 mutex_unlock(&wl->mutex);
3571 static void b43_op_stop(struct ieee80211_hw *hw)
3573 struct b43_wl *wl = hw_to_b43_wl(hw);
3574 struct b43_wldev *dev = wl->current_dev;
3576 b43_rfkill_exit(dev);
3578 mutex_lock(&wl->mutex);
3579 if (b43_status(dev) >= B43_STAT_STARTED)
3580 b43_wireless_core_stop(dev);
3581 b43_wireless_core_exit(dev);
3582 mutex_unlock(&wl->mutex);
3585 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3586 u32 short_retry_limit, u32 long_retry_limit)
3588 struct b43_wl *wl = hw_to_b43_wl(hw);
3589 struct b43_wldev *dev;
3592 mutex_lock(&wl->mutex);
3593 dev = wl->current_dev;
3594 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3598 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3600 mutex_unlock(&wl->mutex);
3605 static const struct ieee80211_ops b43_hw_ops = {
3607 .conf_tx = b43_op_conf_tx,
3608 .add_interface = b43_op_add_interface,
3609 .remove_interface = b43_op_remove_interface,
3610 .config = b43_op_config,
3611 .config_interface = b43_op_config_interface,
3612 .configure_filter = b43_op_configure_filter,
3613 .set_key = b43_op_set_key,
3614 .get_stats = b43_op_get_stats,
3615 .get_tx_stats = b43_op_get_tx_stats,
3616 .start = b43_op_start,
3617 .stop = b43_op_stop,
3618 .set_retry_limit = b43_op_set_retry_limit,
3621 /* Hard-reset the chip. Do not call this directly.
3622 * Use b43_controller_restart()
3624 static void b43_chip_reset(struct work_struct *work)
3626 struct b43_wldev *dev =
3627 container_of(work, struct b43_wldev, restart_work);
3628 struct b43_wl *wl = dev->wl;
3632 mutex_lock(&wl->mutex);
3634 prev_status = b43_status(dev);
3635 /* Bring the device down... */
3636 if (prev_status >= B43_STAT_STARTED)
3637 b43_wireless_core_stop(dev);
3638 if (prev_status >= B43_STAT_INITIALIZED)
3639 b43_wireless_core_exit(dev);
3641 /* ...and up again. */
3642 if (prev_status >= B43_STAT_INITIALIZED) {
3643 err = b43_wireless_core_init(dev);
3647 if (prev_status >= B43_STAT_STARTED) {
3648 err = b43_wireless_core_start(dev);
3650 b43_wireless_core_exit(dev);
3655 mutex_unlock(&wl->mutex);
3657 b43err(wl, "Controller restart FAILED\n");
3659 b43info(wl, "Controller restarted\n");
3662 static int b43_setup_modes(struct b43_wldev *dev,
3663 int have_aphy, int have_bphy, int have_gphy)
3665 struct ieee80211_hw *hw = dev->wl->hw;
3666 struct ieee80211_hw_mode *mode;
3667 struct b43_phy *phy = &dev->phy;
3671 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3674 phy->possible_phymodes = 0;
3677 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3678 mode = &phy->hwmodes[cnt];
3680 mode->mode = MODE_IEEE80211A;
3681 mode->num_channels = b43_a_chantable_size;
3682 mode->channels = b43_a_chantable;
3683 mode->num_rates = b43_a_ratetable_size;
3684 mode->rates = b43_a_ratetable;
3685 err = ieee80211_register_hwmode(hw, mode);
3689 phy->possible_phymodes |= B43_PHYMODE_A;
3694 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3695 mode = &phy->hwmodes[cnt];
3697 mode->mode = MODE_IEEE80211B;
3698 mode->num_channels = b43_bg_chantable_size;
3699 mode->channels = b43_bg_chantable;
3700 mode->num_rates = b43_b_ratetable_size;
3701 mode->rates = b43_b_ratetable;
3702 err = ieee80211_register_hwmode(hw, mode);
3706 phy->possible_phymodes |= B43_PHYMODE_B;
3711 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3712 mode = &phy->hwmodes[cnt];
3714 mode->mode = MODE_IEEE80211G;
3715 mode->num_channels = b43_bg_chantable_size;
3716 mode->channels = b43_bg_chantable;
3717 mode->num_rates = b43_g_ratetable_size;
3718 mode->rates = b43_g_ratetable;
3719 err = ieee80211_register_hwmode(hw, mode);
3723 phy->possible_phymodes |= B43_PHYMODE_G;
3733 static void b43_wireless_core_detach(struct b43_wldev *dev)
3735 /* We release firmware that late to not be required to re-request
3736 * is all the time when we reinit the core. */
3737 b43_release_firmware(dev);
3740 static int b43_wireless_core_attach(struct b43_wldev *dev)
3742 struct b43_wl *wl = dev->wl;
3743 struct ssb_bus *bus = dev->dev->bus;
3744 struct pci_dev *pdev = bus->host_pci;
3746 int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3749 /* Do NOT do any device initialization here.
3750 * Do it in wireless_core_init() instead.
3751 * This function is for gathering basic information about the HW, only.
3752 * Also some structs may be set up here. But most likely you want to have
3753 * that in core_init(), too.
3756 err = ssb_bus_powerup(bus, 0);
3758 b43err(wl, "Bus powerup failed\n");
3761 /* Get the PHY type. */
3762 if (dev->dev->id.revision >= 5) {
3765 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3766 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3767 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3768 if (!have_aphy && !have_gphy)
3770 } else if (dev->dev->id.revision == 4) {
3776 dev->phy.gmode = (have_gphy || have_bphy);
3777 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3778 b43_wireless_core_reset(dev, tmp);
3780 err = b43_phy_versioning(dev);
3783 /* Check if this device supports multiband. */
3785 (pdev->device != 0x4312 &&
3786 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3787 /* No multiband support. */
3791 switch (dev->phy.type) {
3805 dev->phy.gmode = (have_gphy || have_bphy);
3806 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3807 b43_wireless_core_reset(dev, tmp);
3809 err = b43_validate_chipaccess(dev);
3812 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3816 /* Now set some default "current_dev" */
3817 if (!wl->current_dev)
3818 wl->current_dev = dev;
3819 INIT_WORK(&dev->restart_work, b43_chip_reset);
3821 b43_radio_turn_off(dev, 1);
3822 b43_switch_analog(dev, 0);
3823 ssb_device_disable(dev->dev, 0);
3824 ssb_bus_may_powerdown(bus);
3830 ssb_bus_may_powerdown(bus);
3834 static void b43_one_core_detach(struct ssb_device *dev)
3836 struct b43_wldev *wldev;
3839 wldev = ssb_get_drvdata(dev);
3841 cancel_work_sync(&wldev->restart_work);
3842 b43_debugfs_remove_device(wldev);
3843 b43_wireless_core_detach(wldev);
3844 list_del(&wldev->list);
3846 ssb_set_drvdata(dev, NULL);
3850 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3852 struct b43_wldev *wldev;
3853 struct pci_dev *pdev;
3856 if (!list_empty(&wl->devlist)) {
3857 /* We are not the first core on this chip. */
3858 pdev = dev->bus->host_pci;
3859 /* Only special chips support more than one wireless
3860 * core, although some of the other chips have more than
3861 * one wireless core as well. Check for this and
3865 ((pdev->device != 0x4321) &&
3866 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3867 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3872 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3878 b43_set_status(wldev, B43_STAT_UNINIT);
3879 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3880 tasklet_init(&wldev->isr_tasklet,
3881 (void (*)(unsigned long))b43_interrupt_tasklet,
3882 (unsigned long)wldev);
3884 wldev->__using_pio = 1;
3885 INIT_LIST_HEAD(&wldev->list);
3887 err = b43_wireless_core_attach(wldev);
3889 goto err_kfree_wldev;
3891 list_add(&wldev->list, &wl->devlist);
3893 ssb_set_drvdata(dev, wldev);
3894 b43_debugfs_add_device(wldev);
3904 static void b43_sprom_fixup(struct ssb_bus *bus)
3906 /* boardflags workarounds */
3907 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3908 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3909 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3910 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3911 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3912 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3915 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3917 struct ieee80211_hw *hw = wl->hw;
3919 ssb_set_devtypedata(dev, NULL);
3920 ieee80211_free_hw(hw);
3923 static int b43_wireless_init(struct ssb_device *dev)
3925 struct ssb_sprom *sprom = &dev->bus->sprom;
3926 struct ieee80211_hw *hw;
3930 b43_sprom_fixup(dev->bus);
3932 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3934 b43err(NULL, "Could not allocate ieee80211 device\n");
3939 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3940 IEEE80211_HW_RX_INCLUDES_FCS;
3941 hw->max_signal = 100;
3942 hw->max_rssi = -110;
3943 hw->max_noise = -110;
3944 hw->queues = 1; /* FIXME: hardware has more queues */
3945 SET_IEEE80211_DEV(hw, dev->dev);
3946 if (is_valid_ether_addr(sprom->et1mac))
3947 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3949 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3951 /* Get and initialize struct b43_wl */
3952 wl = hw_to_b43_wl(hw);
3953 memset(wl, 0, sizeof(*wl));
3955 spin_lock_init(&wl->irq_lock);
3956 spin_lock_init(&wl->leds_lock);
3957 mutex_init(&wl->mutex);
3958 INIT_LIST_HEAD(&wl->devlist);
3960 ssb_set_devtypedata(dev, wl);
3961 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3967 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3973 wl = ssb_get_devtypedata(dev);
3975 /* Probing the first core. Must setup common struct b43_wl */
3977 err = b43_wireless_init(dev);
3980 wl = ssb_get_devtypedata(dev);
3983 err = b43_one_core_attach(dev, wl);
3985 goto err_wireless_exit;
3988 err = ieee80211_register_hw(wl->hw);
3990 goto err_one_core_detach;
3996 err_one_core_detach:
3997 b43_one_core_detach(dev);
4000 b43_wireless_exit(dev, wl);
4004 static void b43_remove(struct ssb_device *dev)
4006 struct b43_wl *wl = ssb_get_devtypedata(dev);
4007 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4010 if (wl->current_dev == wldev)
4011 ieee80211_unregister_hw(wl->hw);
4013 b43_one_core_detach(dev);
4015 if (list_empty(&wl->devlist)) {
4016 /* Last core on the chip unregistered.
4017 * We can destroy common struct b43_wl.
4019 b43_wireless_exit(dev, wl);
4023 /* Perform a hardware reset. This can be called from any context. */
4024 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4026 /* Must avoid requeueing, if we are in shutdown. */
4027 if (b43_status(dev) < B43_STAT_INITIALIZED)
4029 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4030 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4035 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4037 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4038 struct b43_wl *wl = wldev->wl;
4040 b43dbg(wl, "Suspending...\n");
4042 mutex_lock(&wl->mutex);
4043 wldev->suspend_init_status = b43_status(wldev);
4044 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4045 b43_wireless_core_stop(wldev);
4046 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4047 b43_wireless_core_exit(wldev);
4048 mutex_unlock(&wl->mutex);
4050 b43dbg(wl, "Device suspended.\n");
4055 static int b43_resume(struct ssb_device *dev)
4057 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4058 struct b43_wl *wl = wldev->wl;
4061 b43dbg(wl, "Resuming...\n");
4063 mutex_lock(&wl->mutex);
4064 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4065 err = b43_wireless_core_init(wldev);
4067 b43err(wl, "Resume failed at core init\n");
4071 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4072 err = b43_wireless_core_start(wldev);
4074 b43_wireless_core_exit(wldev);
4075 b43err(wl, "Resume failed at core start\n");
4079 mutex_unlock(&wl->mutex);
4081 b43dbg(wl, "Device resumed.\n");
4086 #else /* CONFIG_PM */
4087 # define b43_suspend NULL
4088 # define b43_resume NULL
4089 #endif /* CONFIG_PM */
4091 static struct ssb_driver b43_ssb_driver = {
4092 .name = KBUILD_MODNAME,
4093 .id_table = b43_ssb_tbl,
4095 .remove = b43_remove,
4096 .suspend = b43_suspend,
4097 .resume = b43_resume,
4100 static int __init b43_init(void)
4105 err = b43_pcmcia_init();
4108 err = ssb_driver_register(&b43_ssb_driver);
4110 goto err_pcmcia_exit;
4121 static void __exit b43_exit(void)
4123 ssb_driver_unregister(&b43_ssb_driver);
4128 module_init(b43_init)
4129 module_exit(b43_exit)