3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
56 MODULE_AUTHOR("Martin Langer");
57 MODULE_AUTHOR("Stefano Brivio");
58 MODULE_AUTHOR("Michael Buesch");
59 MODULE_LICENSE("GPL");
61 extern char *nvram_get(char *name);
63 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
64 static int modparam_pio;
65 module_param_named(pio, modparam_pio, int, 0444);
66 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
67 #elif defined(CONFIG_B43_DMA)
68 # define modparam_pio 0
69 #elif defined(CONFIG_B43_PIO)
70 # define modparam_pio 1
73 static int modparam_bad_frames_preempt;
74 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
75 MODULE_PARM_DESC(bad_frames_preempt,
76 "enable(1) / disable(0) Bad Frames Preemption");
78 static int modparam_short_retry = B43_DEFAULT_SHORT_RETRY_LIMIT;
79 module_param_named(short_retry, modparam_short_retry, int, 0444);
80 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
82 static int modparam_long_retry = B43_DEFAULT_LONG_RETRY_LIMIT;
83 module_param_named(long_retry, modparam_long_retry, int, 0444);
84 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
86 static char modparam_fwpostfix[16];
87 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
88 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
90 static int modparam_hwpctl;
91 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
92 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
94 static int modparam_nohwcrypt;
95 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
96 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
98 static const struct ssb_device_id b43_ssb_tbl[] = {
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
107 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
109 /* Channel and ratetables are shared for all devices.
110 * They can't be const, because ieee80211 puts some precalculated
111 * data in there. This data is the same for all devices, so we don't
112 * get concurrency issues */
113 #define RATETAB_ENT(_rateid, _flags) \
115 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
120 static struct ieee80211_rate __b43_ratetable[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
135 #define b43_a_ratetable (__b43_ratetable + 4)
136 #define b43_a_ratetable_size 8
137 #define b43_b_ratetable (__b43_ratetable + 0)
138 #define b43_b_ratetable_size 4
139 #define b43_g_ratetable (__b43_ratetable + 0)
140 #define b43_g_ratetable_size 12
142 #define CHANTAB_ENT(_chanid, _freq) \
147 .flag = IEEE80211_CHAN_W_SCAN | \
148 IEEE80211_CHAN_W_ACTIVE_SCAN | \
149 IEEE80211_CHAN_W_IBSS, \
150 .power_level = 0xFF, \
151 .antenna_max = 0xFF, \
153 static struct ieee80211_channel b43_bg_chantable[] = {
154 CHANTAB_ENT(1, 2412),
155 CHANTAB_ENT(2, 2417),
156 CHANTAB_ENT(3, 2422),
157 CHANTAB_ENT(4, 2427),
158 CHANTAB_ENT(5, 2432),
159 CHANTAB_ENT(6, 2437),
160 CHANTAB_ENT(7, 2442),
161 CHANTAB_ENT(8, 2447),
162 CHANTAB_ENT(9, 2452),
163 CHANTAB_ENT(10, 2457),
164 CHANTAB_ENT(11, 2462),
165 CHANTAB_ENT(12, 2467),
166 CHANTAB_ENT(13, 2472),
167 CHANTAB_ENT(14, 2484),
170 #define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable)
171 static struct ieee80211_channel b43_a_chantable[] = {
172 CHANTAB_ENT(36, 5180),
173 CHANTAB_ENT(40, 5200),
174 CHANTAB_ENT(44, 5220),
175 CHANTAB_ENT(48, 5240),
176 CHANTAB_ENT(52, 5260),
177 CHANTAB_ENT(56, 5280),
178 CHANTAB_ENT(60, 5300),
179 CHANTAB_ENT(64, 5320),
180 CHANTAB_ENT(149, 5745),
181 CHANTAB_ENT(153, 5765),
182 CHANTAB_ENT(157, 5785),
183 CHANTAB_ENT(161, 5805),
184 CHANTAB_ENT(165, 5825),
187 #define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable)
189 static void b43_wireless_core_exit(struct b43_wldev *dev);
190 static int b43_wireless_core_init(struct b43_wldev *dev);
191 static void b43_wireless_core_stop(struct b43_wldev *dev);
192 static int b43_wireless_core_start(struct b43_wldev *dev);
194 static int b43_ratelimit(struct b43_wl *wl)
196 if (!wl || !wl->current_dev)
198 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
200 /* We are up and running.
201 * Ratelimit the messages to avoid DoS over the net. */
202 return net_ratelimit();
205 void b43info(struct b43_wl *wl, const char *fmt, ...)
209 if (!b43_ratelimit(wl))
212 printk(KERN_INFO "b43-%s: ",
213 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
218 void b43err(struct b43_wl *wl, const char *fmt, ...)
222 if (!b43_ratelimit(wl))
225 printk(KERN_ERR "b43-%s ERROR: ",
226 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
231 void b43warn(struct b43_wl *wl, const char *fmt, ...)
235 if (!b43_ratelimit(wl))
238 printk(KERN_WARNING "b43-%s warning: ",
239 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
245 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
250 printk(KERN_DEBUG "b43-%s debug: ",
251 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
257 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
261 B43_WARN_ON(offset % 4 != 0);
263 macctl = b43_read32(dev, B43_MMIO_MACCTL);
264 if (macctl & B43_MACCTL_BE)
267 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
269 b43_write32(dev, B43_MMIO_RAM_DATA, val);
273 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
277 /* "offset" is the WORD offset. */
282 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
285 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
289 if (routing == B43_SHM_SHARED) {
290 B43_WARN_ON(offset & 0x0001);
291 if (offset & 0x0003) {
292 /* Unaligned access */
293 b43_shm_control_word(dev, routing, offset >> 2);
294 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
296 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
297 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
303 b43_shm_control_word(dev, routing, offset);
304 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
309 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
313 if (routing == B43_SHM_SHARED) {
314 B43_WARN_ON(offset & 0x0001);
315 if (offset & 0x0003) {
316 /* Unaligned access */
317 b43_shm_control_word(dev, routing, offset >> 2);
318 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
324 b43_shm_control_word(dev, routing, offset);
325 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
330 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
332 if (routing == B43_SHM_SHARED) {
333 B43_WARN_ON(offset & 0x0001);
334 if (offset & 0x0003) {
335 /* Unaligned access */
336 b43_shm_control_word(dev, routing, offset >> 2);
338 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
339 (value >> 16) & 0xffff);
341 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
343 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
348 b43_shm_control_word(dev, routing, offset);
350 b43_write32(dev, B43_MMIO_SHM_DATA, value);
353 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
355 if (routing == B43_SHM_SHARED) {
356 B43_WARN_ON(offset & 0x0001);
357 if (offset & 0x0003) {
358 /* Unaligned access */
359 b43_shm_control_word(dev, routing, offset >> 2);
361 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
366 b43_shm_control_word(dev, routing, offset);
368 b43_write16(dev, B43_MMIO_SHM_DATA, value);
372 u32 b43_hf_read(struct b43_wldev * dev)
376 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
378 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
383 /* Write HostFlags */
384 void b43_hf_write(struct b43_wldev *dev, u32 value)
386 b43_shm_write16(dev, B43_SHM_SHARED,
387 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
388 b43_shm_write16(dev, B43_SHM_SHARED,
389 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
392 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
394 /* We need to be careful. As we read the TSF from multiple
395 * registers, we should take care of register overflows.
396 * In theory, the whole tsf read process should be atomic.
397 * We try to be atomic here, by restaring the read process,
398 * if any of the high registers changed (overflew).
400 if (dev->dev->id.revision >= 3) {
401 u32 low, high, high2;
404 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
405 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
406 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
407 } while (unlikely(high != high2));
415 u16 test1, test2, test3;
418 v3 = b43_read16(dev, B43_MMIO_TSF_3);
419 v2 = b43_read16(dev, B43_MMIO_TSF_2);
420 v1 = b43_read16(dev, B43_MMIO_TSF_1);
421 v0 = b43_read16(dev, B43_MMIO_TSF_0);
423 test3 = b43_read16(dev, B43_MMIO_TSF_3);
424 test2 = b43_read16(dev, B43_MMIO_TSF_2);
425 test1 = b43_read16(dev, B43_MMIO_TSF_1);
426 } while (v3 != test3 || v2 != test2 || v1 != test1);
440 static void b43_time_lock(struct b43_wldev *dev)
444 macctl = b43_read32(dev, B43_MMIO_MACCTL);
445 macctl |= B43_MACCTL_TBTTHOLD;
446 b43_write32(dev, B43_MMIO_MACCTL, macctl);
447 /* Commit the write */
448 b43_read32(dev, B43_MMIO_MACCTL);
451 static void b43_time_unlock(struct b43_wldev *dev)
455 macctl = b43_read32(dev, B43_MMIO_MACCTL);
456 macctl &= ~B43_MACCTL_TBTTHOLD;
457 b43_write32(dev, B43_MMIO_MACCTL, macctl);
458 /* Commit the write */
459 b43_read32(dev, B43_MMIO_MACCTL);
462 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
464 /* Be careful with the in-progress timer.
465 * First zero out the low register, so we have a full
466 * register-overflow duration to complete the operation.
468 if (dev->dev->id.revision >= 3) {
469 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
470 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
472 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
474 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
476 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
478 u16 v0 = (tsf & 0x000000000000FFFFULL);
479 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
480 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
481 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
483 b43_write16(dev, B43_MMIO_TSF_0, 0);
485 b43_write16(dev, B43_MMIO_TSF_3, v3);
487 b43_write16(dev, B43_MMIO_TSF_2, v2);
489 b43_write16(dev, B43_MMIO_TSF_1, v1);
491 b43_write16(dev, B43_MMIO_TSF_0, v0);
495 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
498 b43_tsf_write_locked(dev, tsf);
499 b43_time_unlock(dev);
503 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
505 static const u8 zero_addr[ETH_ALEN] = { 0 };
512 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
516 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
519 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
522 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
525 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
529 u8 mac_bssid[ETH_ALEN * 2];
533 bssid = dev->wl->bssid;
534 mac = dev->wl->mac_addr;
536 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
538 memcpy(mac_bssid, mac, ETH_ALEN);
539 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
541 /* Write our MAC address and BSSID to template ram */
542 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
543 tmp = (u32) (mac_bssid[i + 0]);
544 tmp |= (u32) (mac_bssid[i + 1]) << 8;
545 tmp |= (u32) (mac_bssid[i + 2]) << 16;
546 tmp |= (u32) (mac_bssid[i + 3]) << 24;
547 b43_ram_write(dev, 0x20 + i, tmp);
551 static void b43_upload_card_macaddress(struct b43_wldev *dev)
553 b43_write_mac_bssid_templates(dev);
554 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
557 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
559 /* slot_time is in usec. */
560 if (dev->phy.type != B43_PHYTYPE_G)
562 b43_write16(dev, 0x684, 510 + slot_time);
563 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
566 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
568 b43_set_slot_time(dev, 9);
572 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
574 b43_set_slot_time(dev, 20);
578 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
579 * Returns the _previously_ enabled IRQ mask.
581 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
585 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
586 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
591 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
592 * Returns the _previously_ enabled IRQ mask.
594 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
598 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
599 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
604 /* Synchronize IRQ top- and bottom-half.
605 * IRQs must be masked before calling this.
606 * This must not be called with the irq_lock held.
608 static void b43_synchronize_irq(struct b43_wldev *dev)
610 synchronize_irq(dev->dev->irq);
611 tasklet_kill(&dev->isr_tasklet);
614 /* DummyTransmission function, as documented on
615 * http://bcm-specs.sipsolutions.net/DummyTransmission
617 void b43_dummy_transmission(struct b43_wldev *dev)
619 struct b43_phy *phy = &dev->phy;
620 unsigned int i, max_loop;
633 buffer[0] = 0x000201CC;
638 buffer[0] = 0x000B846E;
645 for (i = 0; i < 5; i++)
646 b43_ram_write(dev, i * 4, buffer[i]);
649 b43_read32(dev, B43_MMIO_MACCTL);
651 b43_write16(dev, 0x0568, 0x0000);
652 b43_write16(dev, 0x07C0, 0x0000);
653 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
654 b43_write16(dev, 0x050C, value);
655 b43_write16(dev, 0x0508, 0x0000);
656 b43_write16(dev, 0x050A, 0x0000);
657 b43_write16(dev, 0x054C, 0x0000);
658 b43_write16(dev, 0x056A, 0x0014);
659 b43_write16(dev, 0x0568, 0x0826);
660 b43_write16(dev, 0x0500, 0x0000);
661 b43_write16(dev, 0x0502, 0x0030);
663 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
664 b43_radio_write16(dev, 0x0051, 0x0017);
665 for (i = 0x00; i < max_loop; i++) {
666 value = b43_read16(dev, 0x050E);
671 for (i = 0x00; i < 0x0A; i++) {
672 value = b43_read16(dev, 0x050E);
677 for (i = 0x00; i < 0x0A; i++) {
678 value = b43_read16(dev, 0x0690);
679 if (!(value & 0x0100))
683 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
684 b43_radio_write16(dev, 0x0051, 0x0037);
687 static void key_write(struct b43_wldev *dev,
688 u8 index, u8 algorithm, const u8 * key)
695 /* Key index/algo block */
696 kidx = b43_kidx_to_fw(dev, index);
697 value = ((kidx << 4) | algorithm);
698 b43_shm_write16(dev, B43_SHM_SHARED,
699 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
701 /* Write the key to the Key Table Pointer offset */
702 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
703 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
705 value |= (u16) (key[i + 1]) << 8;
706 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
710 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
712 u32 addrtmp[2] = { 0, 0, };
713 u8 per_sta_keys_start = 8;
715 if (b43_new_kidx_api(dev))
716 per_sta_keys_start = 4;
718 B43_WARN_ON(index < per_sta_keys_start);
719 /* We have two default TX keys and possibly two default RX keys.
720 * Physical mac 0 is mapped to physical key 4 or 8, depending
721 * on the firmware version.
722 * So we must adjust the index here.
724 index -= per_sta_keys_start;
727 addrtmp[0] = addr[0];
728 addrtmp[0] |= ((u32) (addr[1]) << 8);
729 addrtmp[0] |= ((u32) (addr[2]) << 16);
730 addrtmp[0] |= ((u32) (addr[3]) << 24);
731 addrtmp[1] = addr[4];
732 addrtmp[1] |= ((u32) (addr[5]) << 8);
735 if (dev->dev->id.revision >= 5) {
736 /* Receive match transmitter address mechanism */
737 b43_shm_write32(dev, B43_SHM_RCMTA,
738 (index * 2) + 0, addrtmp[0]);
739 b43_shm_write16(dev, B43_SHM_RCMTA,
740 (index * 2) + 1, addrtmp[1]);
742 /* RXE (Receive Engine) and
743 * PSM (Programmable State Machine) mechanism
746 /* TODO write to RCM 16, 19, 22 and 25 */
748 b43_shm_write32(dev, B43_SHM_SHARED,
749 B43_SHM_SH_PSM + (index * 6) + 0,
751 b43_shm_write16(dev, B43_SHM_SHARED,
752 B43_SHM_SH_PSM + (index * 6) + 4,
758 static void do_key_write(struct b43_wldev *dev,
759 u8 index, u8 algorithm,
760 const u8 * key, size_t key_len, const u8 * mac_addr)
762 u8 buf[B43_SEC_KEYSIZE] = { 0, };
763 u8 per_sta_keys_start = 8;
765 if (b43_new_kidx_api(dev))
766 per_sta_keys_start = 4;
768 B43_WARN_ON(index >= dev->max_nr_keys);
769 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
771 if (index >= per_sta_keys_start)
772 keymac_write(dev, index, NULL); /* First zero out mac. */
774 memcpy(buf, key, key_len);
775 key_write(dev, index, algorithm, buf);
776 if (index >= per_sta_keys_start)
777 keymac_write(dev, index, mac_addr);
779 dev->key[index].algorithm = algorithm;
782 static int b43_key_write(struct b43_wldev *dev,
783 int index, u8 algorithm,
784 const u8 * key, size_t key_len,
786 struct ieee80211_key_conf *keyconf)
791 if (key_len > B43_SEC_KEYSIZE)
793 for (i = 0; i < dev->max_nr_keys; i++) {
794 /* Check that we don't already have this key. */
795 B43_WARN_ON(dev->key[i].keyconf == keyconf);
798 /* Either pairwise key or address is 00:00:00:00:00:00
799 * for transmit-only keys. Search the index. */
800 if (b43_new_kidx_api(dev))
804 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
805 if (!dev->key[i].keyconf) {
812 b43err(dev->wl, "Out of hardware key memory\n");
816 B43_WARN_ON(index > 3);
818 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
819 if ((index <= 3) && !b43_new_kidx_api(dev)) {
821 B43_WARN_ON(mac_addr);
822 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
824 keyconf->hw_key_idx = index;
825 dev->key[index].keyconf = keyconf;
830 static int b43_key_clear(struct b43_wldev *dev, int index)
832 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
834 do_key_write(dev, index, B43_SEC_ALGO_NONE,
835 NULL, B43_SEC_KEYSIZE, NULL);
836 if ((index <= 3) && !b43_new_kidx_api(dev)) {
837 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
838 NULL, B43_SEC_KEYSIZE, NULL);
840 dev->key[index].keyconf = NULL;
845 static void b43_clear_keys(struct b43_wldev *dev)
849 for (i = 0; i < dev->max_nr_keys; i++)
850 b43_key_clear(dev, i);
853 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
861 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
862 (ps_flags & B43_PS_DISABLED));
863 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
865 if (ps_flags & B43_PS_ENABLED) {
867 } else if (ps_flags & B43_PS_DISABLED) {
870 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
871 // and thus is not an AP and we are associated, set bit 25
873 if (ps_flags & B43_PS_AWAKE) {
875 } else if (ps_flags & B43_PS_ASLEEP) {
878 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
879 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
880 // successful, set bit26
883 /* FIXME: For now we force awake-on and hwps-off */
887 macctl = b43_read32(dev, B43_MMIO_MACCTL);
889 macctl |= B43_MACCTL_HWPS;
891 macctl &= ~B43_MACCTL_HWPS;
893 macctl |= B43_MACCTL_AWAKE;
895 macctl &= ~B43_MACCTL_AWAKE;
896 b43_write32(dev, B43_MMIO_MACCTL, macctl);
898 b43_read32(dev, B43_MMIO_MACCTL);
899 if (awake && dev->dev->id.revision >= 5) {
900 /* Wait for the microcode to wake up. */
901 for (i = 0; i < 100; i++) {
902 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
903 B43_SHM_SH_UCODESTAT);
904 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
911 /* Turn the Analog ON/OFF */
912 static void b43_switch_analog(struct b43_wldev *dev, int on)
914 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
917 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
922 flags |= B43_TMSLOW_PHYCLKEN;
923 flags |= B43_TMSLOW_PHYRESET;
924 ssb_device_enable(dev->dev, flags);
925 msleep(2); /* Wait for the PLL to turn on. */
927 /* Now take the PHY out of Reset again */
928 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
929 tmslow |= SSB_TMSLOW_FGC;
930 tmslow &= ~B43_TMSLOW_PHYRESET;
931 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
932 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
934 tmslow &= ~SSB_TMSLOW_FGC;
935 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
936 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
940 b43_switch_analog(dev, 1);
942 macctl = b43_read32(dev, B43_MMIO_MACCTL);
943 macctl &= ~B43_MACCTL_GMODE;
944 if (flags & B43_TMSLOW_GMODE)
945 macctl |= B43_MACCTL_GMODE;
946 macctl |= B43_MACCTL_IHR_ENABLED;
947 b43_write32(dev, B43_MMIO_MACCTL, macctl);
950 static void handle_irq_transmit_status(struct b43_wldev *dev)
954 struct b43_txstatus stat;
957 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
958 if (!(v0 & 0x00000001))
960 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
962 stat.cookie = (v0 >> 16);
963 stat.seq = (v1 & 0x0000FFFF);
964 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
965 tmp = (v0 & 0x0000FFFF);
966 stat.frame_count = ((tmp & 0xF000) >> 12);
967 stat.rts_count = ((tmp & 0x0F00) >> 8);
968 stat.supp_reason = ((tmp & 0x001C) >> 2);
969 stat.pm_indicated = !!(tmp & 0x0080);
970 stat.intermediate = !!(tmp & 0x0040);
971 stat.for_ampdu = !!(tmp & 0x0020);
972 stat.acked = !!(tmp & 0x0002);
974 b43_handle_txstatus(dev, &stat);
978 static void drain_txstatus_queue(struct b43_wldev *dev)
982 if (dev->dev->id.revision < 5)
984 /* Read all entries from the microcode TXstatus FIFO
985 * and throw them away.
988 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
989 if (!(dummy & 0x00000001))
991 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
995 static u32 b43_jssi_read(struct b43_wldev *dev)
999 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1001 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1006 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1008 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1009 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1012 static void b43_generate_noise_sample(struct b43_wldev *dev)
1014 b43_jssi_write(dev, 0x7F7F7F7F);
1015 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1016 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1018 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1021 static void b43_calculate_link_quality(struct b43_wldev *dev)
1023 /* Top half of Link Quality calculation. */
1025 if (dev->noisecalc.calculation_running)
1027 dev->noisecalc.channel_at_start = dev->phy.channel;
1028 dev->noisecalc.calculation_running = 1;
1029 dev->noisecalc.nr_samples = 0;
1031 b43_generate_noise_sample(dev);
1034 static void handle_irq_noise(struct b43_wldev *dev)
1036 struct b43_phy *phy = &dev->phy;
1042 /* Bottom half of Link Quality calculation. */
1044 B43_WARN_ON(!dev->noisecalc.calculation_running);
1045 if (dev->noisecalc.channel_at_start != phy->channel)
1046 goto drop_calculation;
1047 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1048 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1049 noise[2] == 0x7F || noise[3] == 0x7F)
1052 /* Get the noise samples. */
1053 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1054 i = dev->noisecalc.nr_samples;
1055 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1056 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1057 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1058 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1059 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1060 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1061 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1062 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1063 dev->noisecalc.nr_samples++;
1064 if (dev->noisecalc.nr_samples == 8) {
1065 /* Calculate the Link Quality by the noise samples. */
1067 for (i = 0; i < 8; i++) {
1068 for (j = 0; j < 4; j++)
1069 average += dev->noisecalc.samples[i][j];
1075 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1076 tmp = (tmp / 128) & 0x1F;
1086 dev->stats.link_noise = average;
1088 dev->noisecalc.calculation_running = 0;
1092 b43_generate_noise_sample(dev);
1095 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1097 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1100 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1101 b43_power_saving_ctl_bits(dev, 0);
1103 dev->reg124_set_0x4 = 0;
1104 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1105 dev->reg124_set_0x4 = 1;
1108 static void handle_irq_atim_end(struct b43_wldev *dev)
1110 if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1112 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1113 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1117 static void handle_irq_pmq(struct b43_wldev *dev)
1124 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1125 if (!(tmp & 0x00000008))
1128 /* 16bit write is odd, but correct. */
1129 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1132 static void b43_write_template_common(struct b43_wldev *dev,
1133 const u8 * data, u16 size,
1135 u16 shm_size_offset, u8 rate)
1138 struct b43_plcp_hdr4 plcp;
1141 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1142 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1143 ram_offset += sizeof(u32);
1144 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1145 * So leave the first two bytes of the next write blank.
1147 tmp = (u32) (data[0]) << 16;
1148 tmp |= (u32) (data[1]) << 24;
1149 b43_ram_write(dev, ram_offset, tmp);
1150 ram_offset += sizeof(u32);
1151 for (i = 2; i < size; i += sizeof(u32)) {
1152 tmp = (u32) (data[i + 0]);
1154 tmp |= (u32) (data[i + 1]) << 8;
1156 tmp |= (u32) (data[i + 2]) << 16;
1158 tmp |= (u32) (data[i + 3]) << 24;
1159 b43_ram_write(dev, ram_offset + i - 2, tmp);
1161 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1162 size + sizeof(struct b43_plcp_hdr6));
1165 static void b43_write_beacon_template(struct b43_wldev *dev,
1167 u16 shm_size_offset, u8 rate)
1172 B43_WARN_ON(!dev->cached_beacon);
1173 len = min((size_t) dev->cached_beacon->len,
1174 0x200 - sizeof(struct b43_plcp_hdr6));
1175 data = (const u8 *)(dev->cached_beacon->data);
1176 b43_write_template_common(dev, data,
1177 len, ram_offset, shm_size_offset, rate);
1180 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1181 u16 shm_offset, u16 size, u8 rate)
1183 struct b43_plcp_hdr4 plcp;
1188 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1189 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1190 dev->wl->if_id, size,
1191 B43_RATE_TO_BASE100KBPS(rate));
1192 /* Write PLCP in two parts and timing for packet transfer */
1193 tmp = le32_to_cpu(plcp.data);
1194 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1195 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1196 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1199 /* Instead of using custom probe response template, this function
1200 * just patches custom beacon template by:
1201 * 1) Changing packet type
1202 * 2) Patching duration field
1205 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1206 u16 * dest_size, u8 rate)
1210 u16 src_size, elem_size, src_pos, dest_pos;
1212 struct ieee80211_hdr *hdr;
1214 B43_WARN_ON(!dev->cached_beacon);
1215 src_size = dev->cached_beacon->len;
1216 src_data = (const u8 *)dev->cached_beacon->data;
1218 if (unlikely(src_size < 0x24)) {
1219 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1223 dest_data = kmalloc(src_size, GFP_ATOMIC);
1224 if (unlikely(!dest_data))
1227 /* 0x24 is offset of first variable-len Information-Element
1230 memcpy(dest_data, src_data, 0x24);
1231 src_pos = dest_pos = 0x24;
1232 for (; src_pos < src_size - 2; src_pos += elem_size) {
1233 elem_size = src_data[src_pos + 1] + 2;
1234 if (src_data[src_pos] != 0x05) { /* TIM */
1235 memcpy(dest_data + dest_pos, src_data + src_pos,
1237 dest_pos += elem_size;
1240 *dest_size = dest_pos;
1241 hdr = (struct ieee80211_hdr *)dest_data;
1243 /* Set the frame control. */
1244 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1245 IEEE80211_STYPE_PROBE_RESP);
1246 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1247 dev->wl->if_id, *dest_size,
1248 B43_RATE_TO_BASE100KBPS(rate));
1249 hdr->duration_id = dur;
1254 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1256 u16 shm_size_offset, u8 rate)
1258 u8 *probe_resp_data;
1261 B43_WARN_ON(!dev->cached_beacon);
1262 size = dev->cached_beacon->len;
1263 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1264 if (unlikely(!probe_resp_data))
1267 /* Looks like PLCP headers plus packet timings are stored for
1268 * all possible basic rates
1270 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1271 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1272 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1273 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1275 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1276 b43_write_template_common(dev, probe_resp_data,
1277 size, ram_offset, shm_size_offset, rate);
1278 kfree(probe_resp_data);
1281 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1282 struct sk_buff *beacon)
1284 if (dev->cached_beacon)
1285 kfree_skb(dev->cached_beacon);
1286 dev->cached_beacon = beacon;
1291 static void b43_update_templates(struct b43_wldev *dev)
1295 B43_WARN_ON(!dev->cached_beacon);
1297 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1298 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1299 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1301 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1303 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1306 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1310 err = b43_refresh_cached_beacon(dev, beacon);
1313 b43_update_templates(dev);
1316 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1321 len = min((u16) ssid_len, (u16) 0x100);
1322 for (i = 0; i < len; i += sizeof(u32)) {
1323 tmp = (u32) (ssid[i + 0]);
1325 tmp |= (u32) (ssid[i + 1]) << 8;
1327 tmp |= (u32) (ssid[i + 2]) << 16;
1329 tmp |= (u32) (ssid[i + 3]) << 24;
1330 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1332 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1335 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1338 if (dev->dev->id.revision >= 3) {
1339 b43_write32(dev, 0x188, (beacon_int << 16));
1341 b43_write16(dev, 0x606, (beacon_int >> 6));
1342 b43_write16(dev, 0x610, beacon_int);
1344 b43_time_unlock(dev);
1347 static void handle_irq_beacon(struct b43_wldev *dev)
1351 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1354 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1355 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1357 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1358 /* ACK beacon IRQ. */
1359 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1360 dev->irq_savedstate |= B43_IRQ_BEACON;
1361 if (dev->cached_beacon)
1362 kfree_skb(dev->cached_beacon);
1363 dev->cached_beacon = NULL;
1366 if (!(status & 0x1)) {
1367 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1369 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1371 if (!(status & 0x2)) {
1372 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1374 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1378 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1383 /* Interrupt handler bottom-half */
1384 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1387 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1388 u32 merged_dma_reason = 0;
1390 unsigned long flags;
1392 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1394 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1396 reason = dev->irq_reason;
1397 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1398 dma_reason[i] = dev->dma_reason[i];
1399 merged_dma_reason |= dma_reason[i];
1402 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1403 b43err(dev->wl, "MAC transmission error\n");
1405 if (unlikely(reason & B43_IRQ_PHY_TXERR))
1406 b43err(dev->wl, "PHY transmission error\n");
1408 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1409 B43_DMAIRQ_NONFATALMASK))) {
1410 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1411 b43err(dev->wl, "Fatal DMA error: "
1412 "0x%08X, 0x%08X, 0x%08X, "
1413 "0x%08X, 0x%08X, 0x%08X\n",
1414 dma_reason[0], dma_reason[1],
1415 dma_reason[2], dma_reason[3],
1416 dma_reason[4], dma_reason[5]);
1417 b43_controller_restart(dev, "DMA error");
1419 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1422 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1423 b43err(dev->wl, "DMA error: "
1424 "0x%08X, 0x%08X, 0x%08X, "
1425 "0x%08X, 0x%08X, 0x%08X\n",
1426 dma_reason[0], dma_reason[1],
1427 dma_reason[2], dma_reason[3],
1428 dma_reason[4], dma_reason[5]);
1432 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1433 handle_irq_ucode_debug(dev);
1434 if (reason & B43_IRQ_TBTT_INDI)
1435 handle_irq_tbtt_indication(dev);
1436 if (reason & B43_IRQ_ATIM_END)
1437 handle_irq_atim_end(dev);
1438 if (reason & B43_IRQ_BEACON)
1439 handle_irq_beacon(dev);
1440 if (reason & B43_IRQ_PMQ)
1441 handle_irq_pmq(dev);
1442 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1444 if (reason & B43_IRQ_NOISESAMPLE_OK)
1445 handle_irq_noise(dev);
1447 /* Check the DMA reason registers for received data. */
1448 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1449 if (b43_using_pio(dev))
1450 b43_pio_rx(dev->pio.queue0);
1452 b43_dma_rx(dev->dma.rx_ring0);
1454 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1455 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1456 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1457 if (b43_using_pio(dev))
1458 b43_pio_rx(dev->pio.queue3);
1460 b43_dma_rx(dev->dma.rx_ring3);
1462 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1463 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1465 if (reason & B43_IRQ_TX_OK)
1466 handle_irq_transmit_status(dev);
1468 b43_interrupt_enable(dev, dev->irq_savedstate);
1470 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1473 static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1477 rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1478 if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1479 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1481 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1484 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1486 if (b43_using_pio(dev) &&
1487 (dev->dev->id.revision < 3) &&
1488 (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1489 /* Apply a PIO specific workaround to the dma_reasons */
1490 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1491 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1492 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1493 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1496 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1498 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1499 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1500 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1501 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1502 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1503 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1506 /* Interrupt handler top-half */
1507 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1509 irqreturn_t ret = IRQ_NONE;
1510 struct b43_wldev *dev = dev_id;
1516 spin_lock(&dev->wl->irq_lock);
1518 if (b43_status(dev) < B43_STAT_STARTED)
1520 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1521 if (reason == 0xffffffff) /* shared IRQ */
1524 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1528 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1530 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1532 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1534 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1536 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1538 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1541 b43_interrupt_ack(dev, reason);
1542 /* disable all IRQs. They are enabled again in the bottom half. */
1543 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1544 /* save the reason code and call our bottom half. */
1545 dev->irq_reason = reason;
1546 tasklet_schedule(&dev->isr_tasklet);
1549 spin_unlock(&dev->wl->irq_lock);
1554 static void b43_release_firmware(struct b43_wldev *dev)
1556 release_firmware(dev->fw.ucode);
1557 dev->fw.ucode = NULL;
1558 release_firmware(dev->fw.pcm);
1560 release_firmware(dev->fw.initvals);
1561 dev->fw.initvals = NULL;
1562 release_firmware(dev->fw.initvals_band);
1563 dev->fw.initvals_band = NULL;
1566 static void b43_print_fw_helptext(struct b43_wl *wl)
1568 b43err(wl, "You must go to "
1569 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1570 "and download the correct firmware (version 4).\n");
1573 static int do_request_fw(struct b43_wldev *dev,
1575 const struct firmware **fw)
1577 char path[sizeof(modparam_fwpostfix) + 32];
1578 struct b43_fw_header *hdr;
1585 snprintf(path, ARRAY_SIZE(path),
1587 modparam_fwpostfix, name);
1588 err = request_firmware(fw, path, dev->dev->dev);
1590 b43err(dev->wl, "Firmware file \"%s\" not found "
1591 "or load failed.\n", path);
1594 if ((*fw)->size < sizeof(struct b43_fw_header))
1596 hdr = (struct b43_fw_header *)((*fw)->data);
1597 switch (hdr->type) {
1598 case B43_FW_TYPE_UCODE:
1599 case B43_FW_TYPE_PCM:
1600 size = be32_to_cpu(hdr->size);
1601 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1604 case B43_FW_TYPE_IV:
1615 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1619 static int b43_request_firmware(struct b43_wldev *dev)
1621 struct b43_firmware *fw = &dev->fw;
1622 const u8 rev = dev->dev->id.revision;
1623 const char *filename;
1627 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1629 if ((rev >= 5) && (rev <= 10))
1630 filename = "ucode5";
1631 else if ((rev >= 11) && (rev <= 12))
1632 filename = "ucode11";
1634 filename = "ucode13";
1637 err = do_request_fw(dev, filename, &fw->ucode);
1642 if ((rev >= 5) && (rev <= 10))
1648 err = do_request_fw(dev, filename, &fw->pcm);
1652 if (!fw->initvals) {
1653 switch (dev->phy.type) {
1655 if ((rev >= 5) && (rev <= 10)) {
1656 if (tmshigh & B43_TMSHIGH_GPHY)
1657 filename = "a0g1initvals5";
1659 filename = "a0g0initvals5";
1661 goto err_no_initvals;
1664 if ((rev >= 5) && (rev <= 10))
1665 filename = "b0g0initvals5";
1667 filename = "lp0initvals13";
1669 goto err_no_initvals;
1672 goto err_no_initvals;
1674 err = do_request_fw(dev, filename, &fw->initvals);
1678 if (!fw->initvals_band) {
1679 switch (dev->phy.type) {
1681 if ((rev >= 5) && (rev <= 10)) {
1682 if (tmshigh & B43_TMSHIGH_GPHY)
1683 filename = "a0g1bsinitvals5";
1685 filename = "a0g0bsinitvals5";
1686 } else if (rev >= 11)
1689 goto err_no_initvals;
1692 if ((rev >= 5) && (rev <= 10))
1693 filename = "b0g0bsinitvals5";
1697 goto err_no_initvals;
1700 goto err_no_initvals;
1702 err = do_request_fw(dev, filename, &fw->initvals_band);
1710 b43_print_fw_helptext(dev->wl);
1715 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1720 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1725 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1726 "core rev %u\n", dev->phy.type, rev);
1730 b43_release_firmware(dev);
1734 static int b43_upload_microcode(struct b43_wldev *dev)
1736 const size_t hdr_len = sizeof(struct b43_fw_header);
1738 unsigned int i, len;
1739 u16 fwrev, fwpatch, fwdate, fwtime;
1743 /* Upload Microcode. */
1744 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1745 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1746 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1747 for (i = 0; i < len; i++) {
1748 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1753 /* Upload PCM data. */
1754 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1755 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1756 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1757 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1758 /* No need for autoinc bit in SHM_HW */
1759 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1760 for (i = 0; i < len; i++) {
1761 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1766 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1767 b43_write32(dev, B43_MMIO_MACCTL,
1768 B43_MACCTL_PSM_RUN |
1769 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1771 /* Wait for the microcode to load and respond */
1774 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1775 if (tmp == B43_IRQ_MAC_SUSPENDED)
1779 b43err(dev->wl, "Microcode not responding\n");
1780 b43_print_fw_helptext(dev->wl);
1786 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1788 /* Get and check the revisions. */
1789 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1790 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1791 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1792 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1794 if (fwrev <= 0x128) {
1795 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1796 "binary drivers older than version 4.x is unsupported. "
1797 "You must upgrade your firmware files.\n");
1798 b43_print_fw_helptext(dev->wl);
1799 b43_write32(dev, B43_MMIO_MACCTL, 0);
1803 b43dbg(dev->wl, "Loading firmware version %u.%u "
1804 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1806 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1807 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1809 dev->fw.rev = fwrev;
1810 dev->fw.patch = fwpatch;
1816 static int b43_write_initvals(struct b43_wldev *dev,
1817 const struct b43_iv *ivals,
1821 const struct b43_iv *iv;
1826 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1828 for (i = 0; i < count; i++) {
1829 if (array_size < sizeof(iv->offset_size))
1831 array_size -= sizeof(iv->offset_size);
1832 offset = be16_to_cpu(iv->offset_size);
1833 bit32 = !!(offset & B43_IV_32BIT);
1834 offset &= B43_IV_OFFSET_MASK;
1835 if (offset >= 0x1000)
1840 if (array_size < sizeof(iv->data.d32))
1842 array_size -= sizeof(iv->data.d32);
1844 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1845 b43_write32(dev, offset, value);
1847 iv = (const struct b43_iv *)((const uint8_t *)iv +
1853 if (array_size < sizeof(iv->data.d16))
1855 array_size -= sizeof(iv->data.d16);
1857 value = be16_to_cpu(iv->data.d16);
1858 b43_write16(dev, offset, value);
1860 iv = (const struct b43_iv *)((const uint8_t *)iv +
1871 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1872 b43_print_fw_helptext(dev->wl);
1877 static int b43_upload_initvals(struct b43_wldev *dev)
1879 const size_t hdr_len = sizeof(struct b43_fw_header);
1880 const struct b43_fw_header *hdr;
1881 struct b43_firmware *fw = &dev->fw;
1882 const struct b43_iv *ivals;
1886 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1887 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1888 count = be32_to_cpu(hdr->size);
1889 err = b43_write_initvals(dev, ivals, count,
1890 fw->initvals->size - hdr_len);
1893 if (fw->initvals_band) {
1894 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1895 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1896 count = be32_to_cpu(hdr->size);
1897 err = b43_write_initvals(dev, ivals, count,
1898 fw->initvals_band->size - hdr_len);
1907 /* Initialize the GPIOs
1908 * http://bcm-specs.sipsolutions.net/GPIO
1910 static int b43_gpio_init(struct b43_wldev *dev)
1912 struct ssb_bus *bus = dev->dev->bus;
1913 struct ssb_device *gpiodev, *pcidev = NULL;
1916 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1917 & ~B43_MACCTL_GPOUTSMSK);
1919 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1924 if (dev->dev->bus->chip_id == 0x4301) {
1928 if (0 /* FIXME: conditional unknown */ ) {
1929 b43_write16(dev, B43_MMIO_GPIO_MASK,
1930 b43_read16(dev, B43_MMIO_GPIO_MASK)
1935 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) {
1936 b43_write16(dev, B43_MMIO_GPIO_MASK,
1937 b43_read16(dev, B43_MMIO_GPIO_MASK)
1942 if (dev->dev->id.revision >= 2)
1943 mask |= 0x0010; /* FIXME: This is redundant. */
1945 #ifdef CONFIG_SSB_DRIVER_PCICORE
1946 pcidev = bus->pcicore.dev;
1948 gpiodev = bus->chipco.dev ? : pcidev;
1951 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1952 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1958 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1959 static void b43_gpio_cleanup(struct b43_wldev *dev)
1961 struct ssb_bus *bus = dev->dev->bus;
1962 struct ssb_device *gpiodev, *pcidev = NULL;
1964 #ifdef CONFIG_SSB_DRIVER_PCICORE
1965 pcidev = bus->pcicore.dev;
1967 gpiodev = bus->chipco.dev ? : pcidev;
1970 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1973 /* http://bcm-specs.sipsolutions.net/EnableMac */
1974 void b43_mac_enable(struct b43_wldev *dev)
1976 dev->mac_suspended--;
1977 B43_WARN_ON(dev->mac_suspended < 0);
1978 B43_WARN_ON(irqs_disabled());
1979 if (dev->mac_suspended == 0) {
1980 b43_write32(dev, B43_MMIO_MACCTL,
1981 b43_read32(dev, B43_MMIO_MACCTL)
1982 | B43_MACCTL_ENABLED);
1983 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1984 B43_IRQ_MAC_SUSPENDED);
1986 b43_read32(dev, B43_MMIO_MACCTL);
1987 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1988 b43_power_saving_ctl_bits(dev, 0);
1990 /* Re-enable IRQs. */
1991 spin_lock_irq(&dev->wl->irq_lock);
1992 b43_interrupt_enable(dev, dev->irq_savedstate);
1993 spin_unlock_irq(&dev->wl->irq_lock);
1997 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1998 void b43_mac_suspend(struct b43_wldev *dev)
2004 B43_WARN_ON(irqs_disabled());
2005 B43_WARN_ON(dev->mac_suspended < 0);
2007 if (dev->mac_suspended == 0) {
2008 /* Mask IRQs before suspending MAC. Otherwise
2009 * the MAC stays busy and won't suspend. */
2010 spin_lock_irq(&dev->wl->irq_lock);
2011 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2012 spin_unlock_irq(&dev->wl->irq_lock);
2013 b43_synchronize_irq(dev);
2014 dev->irq_savedstate = tmp;
2016 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2017 b43_write32(dev, B43_MMIO_MACCTL,
2018 b43_read32(dev, B43_MMIO_MACCTL)
2019 & ~B43_MACCTL_ENABLED);
2020 /* force pci to flush the write */
2021 b43_read32(dev, B43_MMIO_MACCTL);
2022 for (i = 40; i; i--) {
2023 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2024 if (tmp & B43_IRQ_MAC_SUSPENDED)
2028 b43err(dev->wl, "MAC suspend failed\n");
2031 dev->mac_suspended++;
2034 static void b43_adjust_opmode(struct b43_wldev *dev)
2036 struct b43_wl *wl = dev->wl;
2040 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2041 /* Reset status to STA infrastructure mode. */
2042 ctl &= ~B43_MACCTL_AP;
2043 ctl &= ~B43_MACCTL_KEEP_CTL;
2044 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2045 ctl &= ~B43_MACCTL_KEEP_BAD;
2046 ctl &= ~B43_MACCTL_PROMISC;
2047 ctl &= ~B43_MACCTL_BEACPROMISC;
2048 ctl |= B43_MACCTL_INFRA;
2050 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2051 ctl |= B43_MACCTL_AP;
2052 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2053 ctl &= ~B43_MACCTL_INFRA;
2055 if (wl->filter_flags & FIF_CONTROL)
2056 ctl |= B43_MACCTL_KEEP_CTL;
2057 if (wl->filter_flags & FIF_FCSFAIL)
2058 ctl |= B43_MACCTL_KEEP_BAD;
2059 if (wl->filter_flags & FIF_PLCPFAIL)
2060 ctl |= B43_MACCTL_KEEP_BADPLCP;
2061 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2062 ctl |= B43_MACCTL_PROMISC;
2063 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2064 ctl |= B43_MACCTL_BEACPROMISC;
2066 /* Workaround: On old hardware the HW-MAC-address-filter
2067 * doesn't work properly, so always run promisc in filter
2068 * it in software. */
2069 if (dev->dev->id.revision <= 4)
2070 ctl |= B43_MACCTL_PROMISC;
2072 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2075 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2076 if (dev->dev->bus->chip_id == 0x4306 &&
2077 dev->dev->bus->chip_rev == 3)
2082 b43_write16(dev, 0x612, cfp_pretbtt);
2085 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2091 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2094 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2096 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2097 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2100 static void b43_rate_memory_init(struct b43_wldev *dev)
2102 switch (dev->phy.type) {
2105 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2106 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2107 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2108 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2109 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2110 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2111 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2112 if (dev->phy.type == B43_PHYTYPE_A)
2116 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2117 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2118 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2119 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2126 /* Set the TX-Antenna for management frames sent by firmware. */
2127 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2134 ant |= B43_TX4_PHY_ANT0;
2137 ant |= B43_TX4_PHY_ANT1;
2139 case B43_ANTENNA_AUTO:
2140 ant |= B43_TX4_PHY_ANTLAST;
2146 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2149 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2150 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2151 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2153 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2154 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2155 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2156 /* For Probe Resposes */
2157 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2158 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2159 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2162 /* This is the opposite of b43_chip_init() */
2163 static void b43_chip_exit(struct b43_wldev *dev)
2165 b43_radio_turn_off(dev, 1);
2166 b43_gpio_cleanup(dev);
2167 /* firmware is released later */
2170 /* Initialize the chip
2171 * http://bcm-specs.sipsolutions.net/ChipInit
2173 static int b43_chip_init(struct b43_wldev *dev)
2175 struct b43_phy *phy = &dev->phy;
2180 b43_write32(dev, B43_MMIO_MACCTL,
2181 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2183 err = b43_request_firmware(dev);
2186 err = b43_upload_microcode(dev);
2188 goto out; /* firmware is released later */
2190 err = b43_gpio_init(dev);
2192 goto out; /* firmware is released later */
2194 err = b43_upload_initvals(dev);
2196 goto err_gpio_clean;
2197 b43_radio_turn_on(dev);
2199 b43_write16(dev, 0x03E6, 0x0000);
2200 err = b43_phy_init(dev);
2204 /* Select initial Interference Mitigation. */
2205 tmp = phy->interfmode;
2206 phy->interfmode = B43_INTERFMODE_NONE;
2207 b43_radio_set_interference_mitigation(dev, tmp);
2209 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2210 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2212 if (phy->type == B43_PHYTYPE_B) {
2213 value16 = b43_read16(dev, 0x005E);
2215 b43_write16(dev, 0x005E, value16);
2217 b43_write32(dev, 0x0100, 0x01000000);
2218 if (dev->dev->id.revision < 5)
2219 b43_write32(dev, 0x010C, 0x01000000);
2221 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2222 & ~B43_MACCTL_INFRA);
2223 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2224 | B43_MACCTL_INFRA);
2226 if (b43_using_pio(dev)) {
2227 b43_write32(dev, 0x0210, 0x00000100);
2228 b43_write32(dev, 0x0230, 0x00000100);
2229 b43_write32(dev, 0x0250, 0x00000100);
2230 b43_write32(dev, 0x0270, 0x00000100);
2231 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2234 /* Probe Response Timeout value */
2235 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2236 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2238 /* Initially set the wireless operation mode. */
2239 b43_adjust_opmode(dev);
2241 if (dev->dev->id.revision < 3) {
2242 b43_write16(dev, 0x060E, 0x0000);
2243 b43_write16(dev, 0x0610, 0x8000);
2244 b43_write16(dev, 0x0604, 0x0000);
2245 b43_write16(dev, 0x0606, 0x0200);
2247 b43_write32(dev, 0x0188, 0x80000000);
2248 b43_write32(dev, 0x018C, 0x02000000);
2250 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2251 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2252 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2253 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2254 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2255 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2256 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2258 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2259 value32 |= 0x00100000;
2260 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2262 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2263 dev->dev->bus->chipco.fast_pwrup_delay);
2266 b43dbg(dev->wl, "Chip initialized\n");
2271 b43_radio_turn_off(dev, 1);
2273 b43_gpio_cleanup(dev);
2277 static void b43_periodic_every120sec(struct b43_wldev *dev)
2279 struct b43_phy *phy = &dev->phy;
2281 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2284 b43_mac_suspend(dev);
2285 b43_lo_g_measure(dev);
2286 b43_mac_enable(dev);
2287 if (b43_has_hardware_pctl(phy))
2288 b43_lo_g_ctl_mark_all_unused(dev);
2291 static void b43_periodic_every60sec(struct b43_wldev *dev)
2293 struct b43_phy *phy = &dev->phy;
2295 if (!b43_has_hardware_pctl(phy))
2296 b43_lo_g_ctl_mark_all_unused(dev);
2297 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
2298 b43_mac_suspend(dev);
2299 b43_calc_nrssi_slope(dev);
2300 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2301 u8 old_chan = phy->channel;
2303 /* VCO Calibration */
2305 b43_radio_selectchannel(dev, 1, 0);
2307 b43_radio_selectchannel(dev, 13, 0);
2308 b43_radio_selectchannel(dev, old_chan, 0);
2310 b43_mac_enable(dev);
2314 static void b43_periodic_every30sec(struct b43_wldev *dev)
2316 /* Update device statistics. */
2317 b43_calculate_link_quality(dev);
2320 static void b43_periodic_every15sec(struct b43_wldev *dev)
2322 struct b43_phy *phy = &dev->phy;
2324 if (phy->type == B43_PHYTYPE_G) {
2325 //TODO: update_aci_moving_average
2326 if (phy->aci_enable && phy->aci_wlan_automatic) {
2327 b43_mac_suspend(dev);
2328 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2329 if (0 /*TODO: bunch of conditions */ ) {
2330 b43_radio_set_interference_mitigation
2331 (dev, B43_INTERFMODE_MANUALWLAN);
2333 } else if (1 /*TODO*/) {
2335 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2336 b43_radio_set_interference_mitigation(dev,
2337 B43_INTERFMODE_NONE);
2341 b43_mac_enable(dev);
2342 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2344 //TODO: implement rev1 workaround
2347 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2348 //TODO for APHY (temperature?)
2351 static void do_periodic_work(struct b43_wldev *dev)
2355 state = dev->periodic_state;
2357 b43_periodic_every120sec(dev);
2359 b43_periodic_every60sec(dev);
2361 b43_periodic_every30sec(dev);
2362 b43_periodic_every15sec(dev);
2365 /* Periodic work locking policy:
2366 * The whole periodic work handler is protected by
2367 * wl->mutex. If another lock is needed somewhere in the
2368 * pwork callchain, it's aquired in-place, where it's needed.
2370 static void b43_periodic_work_handler(struct work_struct *work)
2372 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2373 periodic_work.work);
2374 struct b43_wl *wl = dev->wl;
2375 unsigned long delay;
2377 mutex_lock(&wl->mutex);
2379 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2381 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2384 do_periodic_work(dev);
2386 dev->periodic_state++;
2388 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2389 delay = msecs_to_jiffies(50);
2391 delay = round_jiffies_relative(HZ * 15);
2392 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2394 mutex_unlock(&wl->mutex);
2397 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2399 struct delayed_work *work = &dev->periodic_work;
2401 dev->periodic_state = 0;
2402 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2403 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2406 /* Validate access to the chip (SHM) */
2407 static int b43_validate_chipaccess(struct b43_wldev *dev)
2412 shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2413 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2414 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2416 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2417 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2419 b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2421 value = b43_read32(dev, B43_MMIO_MACCTL);
2422 if ((value | B43_MACCTL_GMODE) !=
2423 (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2426 value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2432 b43err(dev->wl, "Failed to validate the chipaccess\n");
2436 static void b43_security_init(struct b43_wldev *dev)
2438 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2439 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2440 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2441 /* KTP is a word address, but we address SHM bytewise.
2442 * So multiply by two.
2445 if (dev->dev->id.revision >= 5) {
2446 /* Number of RCMTA address slots */
2447 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2449 b43_clear_keys(dev);
2452 static int b43_rng_read(struct hwrng *rng, u32 * data)
2454 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2455 unsigned long flags;
2457 /* Don't take wl->mutex here, as it could deadlock with
2458 * hwrng internal locking. It's not needed to take
2459 * wl->mutex here, anyway. */
2461 spin_lock_irqsave(&wl->irq_lock, flags);
2462 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2463 spin_unlock_irqrestore(&wl->irq_lock, flags);
2465 return (sizeof(u16));
2468 static void b43_rng_exit(struct b43_wl *wl)
2470 if (wl->rng_initialized)
2471 hwrng_unregister(&wl->rng);
2474 static int b43_rng_init(struct b43_wl *wl)
2478 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2479 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2480 wl->rng.name = wl->rng_name;
2481 wl->rng.data_read = b43_rng_read;
2482 wl->rng.priv = (unsigned long)wl;
2483 wl->rng_initialized = 1;
2484 err = hwrng_register(&wl->rng);
2486 wl->rng_initialized = 0;
2487 b43err(wl, "Failed to register the random "
2488 "number generator (%d)\n", err);
2494 static int b43_tx(struct ieee80211_hw *hw,
2495 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2497 struct b43_wl *wl = hw_to_b43_wl(hw);
2498 struct b43_wldev *dev = wl->current_dev;
2500 unsigned long flags;
2504 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2506 /* DMA-TX is done without a global lock. */
2507 if (b43_using_pio(dev)) {
2508 spin_lock_irqsave(&wl->irq_lock, flags);
2509 err = b43_pio_tx(dev, skb, ctl);
2510 spin_unlock_irqrestore(&wl->irq_lock, flags);
2512 err = b43_dma_tx(dev, skb, ctl);
2515 return NETDEV_TX_BUSY;
2516 return NETDEV_TX_OK;
2519 static int b43_conf_tx(struct ieee80211_hw *hw,
2521 const struct ieee80211_tx_queue_params *params)
2526 static int b43_get_tx_stats(struct ieee80211_hw *hw,
2527 struct ieee80211_tx_queue_stats *stats)
2529 struct b43_wl *wl = hw_to_b43_wl(hw);
2530 struct b43_wldev *dev = wl->current_dev;
2531 unsigned long flags;
2536 spin_lock_irqsave(&wl->irq_lock, flags);
2537 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2538 if (b43_using_pio(dev))
2539 b43_pio_get_tx_stats(dev, stats);
2541 b43_dma_get_tx_stats(dev, stats);
2544 spin_unlock_irqrestore(&wl->irq_lock, flags);
2549 static int b43_get_stats(struct ieee80211_hw *hw,
2550 struct ieee80211_low_level_stats *stats)
2552 struct b43_wl *wl = hw_to_b43_wl(hw);
2553 unsigned long flags;
2555 spin_lock_irqsave(&wl->irq_lock, flags);
2556 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2557 spin_unlock_irqrestore(&wl->irq_lock, flags);
2562 static const char *phymode_to_string(unsigned int phymode)
2577 static int find_wldev_for_phymode(struct b43_wl *wl,
2578 unsigned int phymode,
2579 struct b43_wldev **dev, bool * gmode)
2581 struct b43_wldev *d;
2583 list_for_each_entry(d, &wl->devlist, list) {
2584 if (d->phy.possible_phymodes & phymode) {
2585 /* Ok, this device supports the PHY-mode.
2586 * Now figure out how the gmode bit has to be
2587 * set to support it. */
2588 if (phymode == B43_PHYMODE_A)
2601 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2603 struct ssb_device *sdev = dev->dev;
2606 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2607 tmslow &= ~B43_TMSLOW_GMODE;
2608 tmslow |= B43_TMSLOW_PHYRESET;
2609 tmslow |= SSB_TMSLOW_FGC;
2610 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2613 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2614 tmslow &= ~SSB_TMSLOW_FGC;
2615 tmslow |= B43_TMSLOW_PHYRESET;
2616 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2620 /* Expects wl->mutex locked */
2621 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2623 struct b43_wldev *up_dev;
2624 struct b43_wldev *down_dev;
2629 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2631 b43err(wl, "Could not find a device for %s-PHY mode\n",
2632 phymode_to_string(new_mode));
2635 if ((up_dev == wl->current_dev) &&
2636 (!!wl->current_dev->phy.gmode == !!gmode)) {
2637 /* This device is already running. */
2640 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2641 phymode_to_string(new_mode));
2642 down_dev = wl->current_dev;
2644 prev_status = b43_status(down_dev);
2645 /* Shutdown the currently running core. */
2646 if (prev_status >= B43_STAT_STARTED)
2647 b43_wireless_core_stop(down_dev);
2648 if (prev_status >= B43_STAT_INITIALIZED)
2649 b43_wireless_core_exit(down_dev);
2651 if (down_dev != up_dev) {
2652 /* We switch to a different core, so we put PHY into
2653 * RESET on the old core. */
2654 b43_put_phy_into_reset(down_dev);
2657 /* Now start the new core. */
2658 up_dev->phy.gmode = gmode;
2659 if (prev_status >= B43_STAT_INITIALIZED) {
2660 err = b43_wireless_core_init(up_dev);
2662 b43err(wl, "Fatal: Could not initialize device for "
2663 "newly selected %s-PHY mode\n",
2664 phymode_to_string(new_mode));
2668 if (prev_status >= B43_STAT_STARTED) {
2669 err = b43_wireless_core_start(up_dev);
2671 b43err(wl, "Fatal: Coult not start device for "
2672 "newly selected %s-PHY mode\n",
2673 phymode_to_string(new_mode));
2674 b43_wireless_core_exit(up_dev);
2678 B43_WARN_ON(b43_status(up_dev) != prev_status);
2680 wl->current_dev = up_dev;
2684 /* Whoops, failed to init the new core. No core is operating now. */
2685 wl->current_dev = NULL;
2689 static int b43_antenna_from_ieee80211(u8 antenna)
2692 case 0: /* default/diversity */
2693 return B43_ANTENNA_DEFAULT;
2694 case 1: /* Antenna 0 */
2695 return B43_ANTENNA0;
2696 case 2: /* Antenna 1 */
2697 return B43_ANTENNA1;
2699 return B43_ANTENNA_DEFAULT;
2703 static int b43_dev_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2705 struct b43_wl *wl = hw_to_b43_wl(hw);
2706 struct b43_wldev *dev;
2707 struct b43_phy *phy;
2708 unsigned long flags;
2709 unsigned int new_phymode = 0xFFFF;
2715 antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
2716 antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
2718 mutex_lock(&wl->mutex);
2720 /* Switch the PHY mode (if necessary). */
2721 switch (conf->phymode) {
2722 case MODE_IEEE80211A:
2723 new_phymode = B43_PHYMODE_A;
2725 case MODE_IEEE80211B:
2726 new_phymode = B43_PHYMODE_B;
2728 case MODE_IEEE80211G:
2729 new_phymode = B43_PHYMODE_G;
2734 err = b43_switch_phymode(wl, new_phymode);
2736 goto out_unlock_mutex;
2737 dev = wl->current_dev;
2740 /* Disable IRQs while reconfiguring the device.
2741 * This makes it possible to drop the spinlock throughout
2742 * the reconfiguration process. */
2743 spin_lock_irqsave(&wl->irq_lock, flags);
2744 if (b43_status(dev) < B43_STAT_STARTED) {
2745 spin_unlock_irqrestore(&wl->irq_lock, flags);
2746 goto out_unlock_mutex;
2748 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2749 spin_unlock_irqrestore(&wl->irq_lock, flags);
2750 b43_synchronize_irq(dev);
2752 /* Switch to the requested channel.
2753 * The firmware takes care of races with the TX handler. */
2754 if (conf->channel_val != phy->channel)
2755 b43_radio_selectchannel(dev, conf->channel_val, 0);
2757 /* Enable/Disable ShortSlot timing. */
2758 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2760 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2761 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2762 b43_short_slot_timing_enable(dev);
2764 b43_short_slot_timing_disable(dev);
2767 /* Adjust the desired TX power level. */
2768 if (conf->power_level != 0) {
2769 if (conf->power_level != phy->power_level) {
2770 phy->power_level = conf->power_level;
2771 b43_phy_xmitpower(dev);
2775 /* Antennas for RX and management frame TX. */
2776 b43_mgmtframe_txantenna(dev, antenna_tx);
2777 b43_set_rx_antenna(dev, antenna_rx);
2779 /* Update templates for AP mode. */
2780 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2781 b43_set_beacon_int(dev, conf->beacon_int);
2783 if (!!conf->radio_enabled != phy->radio_on) {
2784 if (conf->radio_enabled) {
2785 b43_radio_turn_on(dev);
2786 b43info(dev->wl, "Radio turned on by software\n");
2787 if (!dev->radio_hw_enable) {
2788 b43info(dev->wl, "The hardware RF-kill button "
2789 "still turns the radio physically off. "
2790 "Press the button to turn it on.\n");
2793 b43_radio_turn_off(dev, 0);
2794 b43info(dev->wl, "Radio turned off by software\n");
2798 spin_lock_irqsave(&wl->irq_lock, flags);
2799 b43_interrupt_enable(dev, savedirqs);
2801 spin_unlock_irqrestore(&wl->irq_lock, flags);
2803 mutex_unlock(&wl->mutex);
2808 static int b43_dev_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2809 const u8 *local_addr, const u8 *addr,
2810 struct ieee80211_key_conf *key)
2812 struct b43_wl *wl = hw_to_b43_wl(hw);
2813 struct b43_wldev *dev = wl->current_dev;
2814 unsigned long flags;
2818 DECLARE_MAC_BUF(mac);
2820 if (modparam_nohwcrypt)
2821 return -ENOSPC; /* User disabled HW-crypto */
2827 if (key->keylen == 5)
2828 algorithm = B43_SEC_ALGO_WEP40;
2830 algorithm = B43_SEC_ALGO_WEP104;
2833 algorithm = B43_SEC_ALGO_TKIP;
2836 algorithm = B43_SEC_ALGO_AES;
2843 index = (u8) (key->keyidx);
2847 mutex_lock(&wl->mutex);
2848 spin_lock_irqsave(&wl->irq_lock, flags);
2850 if (b43_status(dev) < B43_STAT_INITIALIZED) {
2857 if (algorithm == B43_SEC_ALGO_TKIP) {
2858 /* FIXME: No TKIP hardware encryption for now. */
2863 if (is_broadcast_ether_addr(addr)) {
2864 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2865 err = b43_key_write(dev, index, algorithm,
2866 key->key, key->keylen, NULL, key);
2869 * either pairwise key or address is 00:00:00:00:00:00
2870 * for transmit-only keys
2872 err = b43_key_write(dev, -1, algorithm,
2873 key->key, key->keylen, addr, key);
2878 if (algorithm == B43_SEC_ALGO_WEP40 ||
2879 algorithm == B43_SEC_ALGO_WEP104) {
2880 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2883 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2885 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2888 err = b43_key_clear(dev, key->hw_key_idx);
2897 spin_unlock_irqrestore(&wl->irq_lock, flags);
2898 mutex_unlock(&wl->mutex);
2901 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2903 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2904 print_mac(mac, addr));
2909 static void b43_configure_filter(struct ieee80211_hw *hw,
2910 unsigned int changed, unsigned int *fflags,
2911 int mc_count, struct dev_addr_list *mc_list)
2913 struct b43_wl *wl = hw_to_b43_wl(hw);
2914 struct b43_wldev *dev = wl->current_dev;
2915 unsigned long flags;
2922 spin_lock_irqsave(&wl->irq_lock, flags);
2923 *fflags &= FIF_PROMISC_IN_BSS |
2929 FIF_BCN_PRBRESP_PROMISC;
2931 changed &= FIF_PROMISC_IN_BSS |
2937 FIF_BCN_PRBRESP_PROMISC;
2939 wl->filter_flags = *fflags;
2941 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2942 b43_adjust_opmode(dev);
2943 spin_unlock_irqrestore(&wl->irq_lock, flags);
2946 static int b43_config_interface(struct ieee80211_hw *hw,
2947 int if_id, struct ieee80211_if_conf *conf)
2949 struct b43_wl *wl = hw_to_b43_wl(hw);
2950 struct b43_wldev *dev = wl->current_dev;
2951 unsigned long flags;
2955 mutex_lock(&wl->mutex);
2956 spin_lock_irqsave(&wl->irq_lock, flags);
2957 B43_WARN_ON(wl->if_id != if_id);
2959 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2961 memset(wl->bssid, 0, ETH_ALEN);
2962 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2963 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2964 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2965 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2967 b43_refresh_templates(dev, conf->beacon);
2969 b43_write_mac_bssid_templates(dev);
2971 spin_unlock_irqrestore(&wl->irq_lock, flags);
2972 mutex_unlock(&wl->mutex);
2977 /* Locking: wl->mutex */
2978 static void b43_wireless_core_stop(struct b43_wldev *dev)
2980 struct b43_wl *wl = dev->wl;
2981 unsigned long flags;
2983 if (b43_status(dev) < B43_STAT_STARTED)
2986 /* Disable and sync interrupts. We must do this before than
2987 * setting the status to INITIALIZED, as the interrupt handler
2988 * won't care about IRQs then. */
2989 spin_lock_irqsave(&wl->irq_lock, flags);
2990 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
2991 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
2992 spin_unlock_irqrestore(&wl->irq_lock, flags);
2993 b43_synchronize_irq(dev);
2995 b43_set_status(dev, B43_STAT_INITIALIZED);
2997 mutex_unlock(&wl->mutex);
2998 /* Must unlock as it would otherwise deadlock. No races here.
2999 * Cancel the possibly running self-rearming periodic work. */
3000 cancel_delayed_work_sync(&dev->periodic_work);
3001 mutex_lock(&wl->mutex);
3003 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3005 b43_mac_suspend(dev);
3006 free_irq(dev->dev->irq, dev);
3007 b43dbg(wl, "Wireless interface stopped\n");
3010 /* Locking: wl->mutex */
3011 static int b43_wireless_core_start(struct b43_wldev *dev)
3015 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3017 drain_txstatus_queue(dev);
3018 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3019 IRQF_SHARED, KBUILD_MODNAME, dev);
3021 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3025 /* We are ready to run. */
3026 b43_set_status(dev, B43_STAT_STARTED);
3028 /* Start data flow (TX/RX). */
3029 b43_mac_enable(dev);
3030 b43_interrupt_enable(dev, dev->irq_savedstate);
3031 ieee80211_start_queues(dev->wl->hw);
3033 /* Start maintainance work */
3034 b43_periodic_tasks_setup(dev);
3036 b43dbg(dev->wl, "Wireless interface started\n");
3041 /* Get PHY and RADIO versioning numbers */
3042 static int b43_phy_versioning(struct b43_wldev *dev)
3044 struct b43_phy *phy = &dev->phy;
3052 int unsupported = 0;
3054 /* Get PHY versioning */
3055 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3056 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3057 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3058 phy_rev = (tmp & B43_PHYVER_VERSION);
3065 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3077 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3078 "(Analog %u, Type %u, Revision %u)\n",
3079 analog_type, phy_type, phy_rev);
3082 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3083 analog_type, phy_type, phy_rev);
3085 /* Get RADIO versioning */
3086 if (dev->dev->bus->chip_id == 0x4317) {
3087 if (dev->dev->bus->chip_rev == 0)
3089 else if (dev->dev->bus->chip_rev == 1)
3094 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3095 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3097 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3098 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3100 radio_manuf = (tmp & 0x00000FFF);
3101 radio_ver = (tmp & 0x0FFFF000) >> 12;
3102 radio_rev = (tmp & 0xF0000000) >> 28;
3105 if (radio_ver != 0x2060)
3109 if (radio_manuf != 0x17F)
3113 if ((radio_ver & 0xFFF0) != 0x2050)
3117 if (radio_ver != 0x2050)
3124 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3125 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3126 radio_manuf, radio_ver, radio_rev);
3129 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3130 radio_manuf, radio_ver, radio_rev);
3132 phy->radio_manuf = radio_manuf;
3133 phy->radio_ver = radio_ver;
3134 phy->radio_rev = radio_rev;
3136 phy->analog = analog_type;
3137 phy->type = phy_type;
3143 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3144 struct b43_phy *phy)
3146 struct b43_txpower_lo_control *lo;
3149 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3150 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3155 phy->aci_enable = 0;
3156 phy->aci_wlan_automatic = 0;
3157 phy->aci_hw_rssi = 0;
3159 phy->radio_off_context.valid = 0;
3161 lo = phy->lo_control;
3163 memset(lo, 0, sizeof(*(phy->lo_control)));
3167 phy->max_lb_gain = 0;
3168 phy->trsw_rx_gain = 0;
3169 phy->txpwr_offset = 0;
3172 phy->nrssislope = 0;
3173 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3174 phy->nrssi[i] = -1000;
3175 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3176 phy->nrssi_lt[i] = i;
3178 phy->lofcal = 0xFFFF;
3179 phy->initval = 0xFFFF;
3181 spin_lock_init(&phy->lock);
3182 phy->interfmode = B43_INTERFMODE_NONE;
3183 phy->channel = 0xFF;
3185 phy->hardware_power_control = !!modparam_hwpctl;
3188 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3191 dev->reg124_set_0x4 = 0;
3192 /* Assume the radio is enabled. If it's not enabled, the state will
3193 * immediately get fixed on the first periodic work run. */
3194 dev->radio_hw_enable = 1;
3197 memset(&dev->stats, 0, sizeof(dev->stats));
3199 setup_struct_phy_for_init(dev, &dev->phy);
3201 /* IRQ related flags */
3202 dev->irq_reason = 0;
3203 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3204 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3206 dev->mac_suspended = 1;
3208 /* Noise calculation context */
3209 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3212 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3214 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3217 if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST))
3219 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3222 hf = b43_hf_read(dev);
3223 if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD)
3224 hf |= B43_HF_BTCOEXALT;
3226 hf |= B43_HF_BTCOEX;
3227 b43_hf_write(dev, hf);
3231 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3235 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3237 #ifdef CONFIG_SSB_DRIVER_PCICORE
3238 struct ssb_bus *bus = dev->dev->bus;
3241 if (bus->pcicore.dev &&
3242 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3243 bus->pcicore.dev->id.revision <= 5) {
3244 /* IMCFGLO timeouts workaround. */
3245 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3246 tmp &= ~SSB_IMCFGLO_REQTO;
3247 tmp &= ~SSB_IMCFGLO_SERTO;
3248 switch (bus->bustype) {
3249 case SSB_BUSTYPE_PCI:
3250 case SSB_BUSTYPE_PCMCIA:
3253 case SSB_BUSTYPE_SSB:
3257 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3259 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3262 /* Shutdown a wireless core */
3263 /* Locking: wl->mutex */
3264 static void b43_wireless_core_exit(struct b43_wldev *dev)
3266 struct b43_phy *phy = &dev->phy;
3268 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3269 if (b43_status(dev) != B43_STAT_INITIALIZED)
3271 b43_set_status(dev, B43_STAT_UNINIT);
3274 b43_rng_exit(dev->wl);
3278 b43_radio_turn_off(dev, 1);
3279 b43_switch_analog(dev, 0);
3280 if (phy->dyn_tssi_tbl)
3281 kfree(phy->tssi2dbm);
3282 kfree(phy->lo_control);
3283 phy->lo_control = NULL;
3284 ssb_device_disable(dev->dev, 0);
3285 ssb_bus_may_powerdown(dev->dev->bus);
3288 /* Initialize a wireless core */
3289 static int b43_wireless_core_init(struct b43_wldev *dev)
3291 struct b43_wl *wl = dev->wl;
3292 struct ssb_bus *bus = dev->dev->bus;
3293 struct ssb_sprom *sprom = &bus->sprom;
3294 struct b43_phy *phy = &dev->phy;
3298 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3300 err = ssb_bus_powerup(bus, 0);
3303 if (!ssb_device_is_enabled(dev->dev)) {
3304 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3305 b43_wireless_core_reset(dev, tmp);
3308 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3310 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3311 if (!phy->lo_control) {
3316 setup_struct_wldev_for_init(dev);
3318 err = b43_phy_init_tssi2dbm_table(dev);
3320 goto err_kfree_lo_control;
3322 /* Enable IRQ routing to this device. */
3323 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3325 b43_imcfglo_timeouts_workaround(dev);
3326 b43_bluetooth_coext_disable(dev);
3327 b43_phy_early_init(dev);
3328 err = b43_chip_init(dev);
3330 goto err_kfree_tssitbl;
3331 b43_shm_write16(dev, B43_SHM_SHARED,
3332 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3333 hf = b43_hf_read(dev);
3334 if (phy->type == B43_PHYTYPE_G) {
3338 if (sprom->r1.boardflags_lo & B43_BFL_PACTRL)
3339 hf |= B43_HF_OFDMPABOOST;
3340 } else if (phy->type == B43_PHYTYPE_B) {
3342 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3345 b43_hf_write(dev, hf);
3347 /* Short/Long Retry Limit.
3348 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3349 * the chip-internal counter.
3351 tmp = limit_value(modparam_short_retry, 0, 0xF);
3352 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, tmp);
3353 tmp = limit_value(modparam_long_retry, 0, 0xF);
3354 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, tmp);
3356 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3357 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3359 /* Disable sending probe responses from firmware.
3360 * Setting the MaxTime to one usec will always trigger
3361 * a timeout, so we never send any probe resp.
3362 * A timeout of zero is infinite. */
3363 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3365 b43_rate_memory_init(dev);
3367 /* Minimum Contention Window */
3368 if (phy->type == B43_PHYTYPE_B) {
3369 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3371 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3373 /* Maximum Contention Window */
3374 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3377 if (b43_using_pio(dev)) {
3378 err = b43_pio_init(dev);
3380 err = b43_dma_init(dev);
3384 } while (err == -EAGAIN);
3390 b43_write16(dev, 0x0612, 0x0050);
3391 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3392 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3395 b43_bluetooth_coext_enable(dev);
3397 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3398 memset(wl->bssid, 0, ETH_ALEN);
3399 memset(wl->mac_addr, 0, ETH_ALEN);
3400 b43_upload_card_macaddress(dev);
3401 b43_security_init(dev);
3404 b43_set_status(dev, B43_STAT_INITIALIZED);
3413 if (phy->dyn_tssi_tbl)
3414 kfree(phy->tssi2dbm);
3415 err_kfree_lo_control:
3416 kfree(phy->lo_control);
3417 phy->lo_control = NULL;
3419 ssb_bus_may_powerdown(bus);
3420 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3424 static int b43_add_interface(struct ieee80211_hw *hw,
3425 struct ieee80211_if_init_conf *conf)
3427 struct b43_wl *wl = hw_to_b43_wl(hw);
3428 struct b43_wldev *dev;
3429 unsigned long flags;
3430 int err = -EOPNOTSUPP;
3432 /* TODO: allow WDS/AP devices to coexist */
3434 if (conf->type != IEEE80211_IF_TYPE_AP &&
3435 conf->type != IEEE80211_IF_TYPE_STA &&
3436 conf->type != IEEE80211_IF_TYPE_WDS &&
3437 conf->type != IEEE80211_IF_TYPE_IBSS)
3440 mutex_lock(&wl->mutex);
3442 goto out_mutex_unlock;
3444 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3446 dev = wl->current_dev;
3448 wl->if_id = conf->if_id;
3449 wl->if_type = conf->type;
3450 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3452 spin_lock_irqsave(&wl->irq_lock, flags);
3453 b43_adjust_opmode(dev);
3454 b43_upload_card_macaddress(dev);
3455 spin_unlock_irqrestore(&wl->irq_lock, flags);
3459 mutex_unlock(&wl->mutex);
3464 static void b43_remove_interface(struct ieee80211_hw *hw,
3465 struct ieee80211_if_init_conf *conf)
3467 struct b43_wl *wl = hw_to_b43_wl(hw);
3468 struct b43_wldev *dev = wl->current_dev;
3469 unsigned long flags;
3471 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3473 mutex_lock(&wl->mutex);
3475 B43_WARN_ON(!wl->operating);
3476 B43_WARN_ON(wl->if_id != conf->if_id);
3480 spin_lock_irqsave(&wl->irq_lock, flags);
3481 b43_adjust_opmode(dev);
3482 memset(wl->mac_addr, 0, ETH_ALEN);
3483 b43_upload_card_macaddress(dev);
3484 spin_unlock_irqrestore(&wl->irq_lock, flags);
3486 mutex_unlock(&wl->mutex);
3489 static int b43_start(struct ieee80211_hw *hw)
3491 struct b43_wl *wl = hw_to_b43_wl(hw);
3492 struct b43_wldev *dev = wl->current_dev;
3496 /* First register RFkill.
3497 * LEDs that are registered later depend on it. */
3498 b43_rfkill_init(dev);
3500 mutex_lock(&wl->mutex);
3502 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3503 err = b43_wireless_core_init(dev);
3505 goto out_mutex_unlock;
3509 if (b43_status(dev) < B43_STAT_STARTED) {
3510 err = b43_wireless_core_start(dev);
3513 b43_wireless_core_exit(dev);
3514 goto out_mutex_unlock;
3519 mutex_unlock(&wl->mutex);
3524 static void b43_stop(struct ieee80211_hw *hw)
3526 struct b43_wl *wl = hw_to_b43_wl(hw);
3527 struct b43_wldev *dev = wl->current_dev;
3529 b43_rfkill_exit(dev);
3531 mutex_lock(&wl->mutex);
3532 if (b43_status(dev) >= B43_STAT_STARTED)
3533 b43_wireless_core_stop(dev);
3534 b43_wireless_core_exit(dev);
3535 mutex_unlock(&wl->mutex);
3538 static const struct ieee80211_ops b43_hw_ops = {
3540 .conf_tx = b43_conf_tx,
3541 .add_interface = b43_add_interface,
3542 .remove_interface = b43_remove_interface,
3543 .config = b43_dev_config,
3544 .config_interface = b43_config_interface,
3545 .configure_filter = b43_configure_filter,
3546 .set_key = b43_dev_set_key,
3547 .get_stats = b43_get_stats,
3548 .get_tx_stats = b43_get_tx_stats,
3553 /* Hard-reset the chip. Do not call this directly.
3554 * Use b43_controller_restart()
3556 static void b43_chip_reset(struct work_struct *work)
3558 struct b43_wldev *dev =
3559 container_of(work, struct b43_wldev, restart_work);
3560 struct b43_wl *wl = dev->wl;
3564 mutex_lock(&wl->mutex);
3566 prev_status = b43_status(dev);
3567 /* Bring the device down... */
3568 if (prev_status >= B43_STAT_STARTED)
3569 b43_wireless_core_stop(dev);
3570 if (prev_status >= B43_STAT_INITIALIZED)
3571 b43_wireless_core_exit(dev);
3573 /* ...and up again. */
3574 if (prev_status >= B43_STAT_INITIALIZED) {
3575 err = b43_wireless_core_init(dev);
3579 if (prev_status >= B43_STAT_STARTED) {
3580 err = b43_wireless_core_start(dev);
3582 b43_wireless_core_exit(dev);
3587 mutex_unlock(&wl->mutex);
3589 b43err(wl, "Controller restart FAILED\n");
3591 b43info(wl, "Controller restarted\n");
3594 static int b43_setup_modes(struct b43_wldev *dev,
3595 int have_aphy, int have_bphy, int have_gphy)
3597 struct ieee80211_hw *hw = dev->wl->hw;
3598 struct ieee80211_hw_mode *mode;
3599 struct b43_phy *phy = &dev->phy;
3603 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3606 phy->possible_phymodes = 0;
3609 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3610 mode = &phy->hwmodes[cnt];
3612 mode->mode = MODE_IEEE80211A;
3613 mode->num_channels = b43_a_chantable_size;
3614 mode->channels = b43_a_chantable;
3615 mode->num_rates = b43_a_ratetable_size;
3616 mode->rates = b43_a_ratetable;
3617 err = ieee80211_register_hwmode(hw, mode);
3621 phy->possible_phymodes |= B43_PHYMODE_A;
3626 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3627 mode = &phy->hwmodes[cnt];
3629 mode->mode = MODE_IEEE80211B;
3630 mode->num_channels = b43_bg_chantable_size;
3631 mode->channels = b43_bg_chantable;
3632 mode->num_rates = b43_b_ratetable_size;
3633 mode->rates = b43_b_ratetable;
3634 err = ieee80211_register_hwmode(hw, mode);
3638 phy->possible_phymodes |= B43_PHYMODE_B;
3643 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3644 mode = &phy->hwmodes[cnt];
3646 mode->mode = MODE_IEEE80211G;
3647 mode->num_channels = b43_bg_chantable_size;
3648 mode->channels = b43_bg_chantable;
3649 mode->num_rates = b43_g_ratetable_size;
3650 mode->rates = b43_g_ratetable;
3651 err = ieee80211_register_hwmode(hw, mode);
3655 phy->possible_phymodes |= B43_PHYMODE_G;
3665 static void b43_wireless_core_detach(struct b43_wldev *dev)
3667 /* We release firmware that late to not be required to re-request
3668 * is all the time when we reinit the core. */
3669 b43_release_firmware(dev);
3672 static int b43_wireless_core_attach(struct b43_wldev *dev)
3674 struct b43_wl *wl = dev->wl;
3675 struct ssb_bus *bus = dev->dev->bus;
3676 struct pci_dev *pdev = bus->host_pci;
3678 int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3681 /* Do NOT do any device initialization here.
3682 * Do it in wireless_core_init() instead.
3683 * This function is for gathering basic information about the HW, only.
3684 * Also some structs may be set up here. But most likely you want to have
3685 * that in core_init(), too.
3688 err = ssb_bus_powerup(bus, 0);
3690 b43err(wl, "Bus powerup failed\n");
3693 /* Get the PHY type. */
3694 if (dev->dev->id.revision >= 5) {
3697 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3698 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3699 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3700 if (!have_aphy && !have_gphy)
3702 } else if (dev->dev->id.revision == 4) {
3708 dev->phy.gmode = (have_gphy || have_bphy);
3709 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3710 b43_wireless_core_reset(dev, tmp);
3712 err = b43_phy_versioning(dev);
3715 /* Check if this device supports multiband. */
3717 (pdev->device != 0x4312 &&
3718 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3719 /* No multiband support. */
3723 switch (dev->phy.type) {
3737 dev->phy.gmode = (have_gphy || have_bphy);
3738 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3739 b43_wireless_core_reset(dev, tmp);
3741 err = b43_validate_chipaccess(dev);
3744 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3748 /* Now set some default "current_dev" */
3749 if (!wl->current_dev)
3750 wl->current_dev = dev;
3751 INIT_WORK(&dev->restart_work, b43_chip_reset);
3753 b43_radio_turn_off(dev, 1);
3754 b43_switch_analog(dev, 0);
3755 ssb_device_disable(dev->dev, 0);
3756 ssb_bus_may_powerdown(bus);
3762 ssb_bus_may_powerdown(bus);
3766 static void b43_one_core_detach(struct ssb_device *dev)
3768 struct b43_wldev *wldev;
3771 wldev = ssb_get_drvdata(dev);
3773 cancel_work_sync(&wldev->restart_work);
3774 b43_debugfs_remove_device(wldev);
3775 b43_wireless_core_detach(wldev);
3776 list_del(&wldev->list);
3778 ssb_set_drvdata(dev, NULL);
3782 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3784 struct b43_wldev *wldev;
3785 struct pci_dev *pdev;
3788 if (!list_empty(&wl->devlist)) {
3789 /* We are not the first core on this chip. */
3790 pdev = dev->bus->host_pci;
3791 /* Only special chips support more than one wireless
3792 * core, although some of the other chips have more than
3793 * one wireless core as well. Check for this and
3797 ((pdev->device != 0x4321) &&
3798 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3799 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3804 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3810 b43_set_status(wldev, B43_STAT_UNINIT);
3811 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3812 tasklet_init(&wldev->isr_tasklet,
3813 (void (*)(unsigned long))b43_interrupt_tasklet,
3814 (unsigned long)wldev);
3816 wldev->__using_pio = 1;
3817 INIT_LIST_HEAD(&wldev->list);
3819 err = b43_wireless_core_attach(wldev);
3821 goto err_kfree_wldev;
3823 list_add(&wldev->list, &wl->devlist);
3825 ssb_set_drvdata(dev, wldev);
3826 b43_debugfs_add_device(wldev);
3836 static void b43_sprom_fixup(struct ssb_bus *bus)
3838 /* boardflags workarounds */
3839 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3840 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3841 bus->sprom.r1.boardflags_lo |= B43_BFL_BTCOEXIST;
3842 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3843 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3844 bus->sprom.r1.boardflags_lo |= B43_BFL_PACTRL;
3846 /* Handle case when gain is not set in sprom */
3847 if (bus->sprom.r1.antenna_gain_a == 0xFF)
3848 bus->sprom.r1.antenna_gain_a = 2;
3849 if (bus->sprom.r1.antenna_gain_bg == 0xFF)
3850 bus->sprom.r1.antenna_gain_bg = 2;
3852 /* Convert Antennagain values to Q5.2 */
3853 bus->sprom.r1.antenna_gain_a <<= 2;
3854 bus->sprom.r1.antenna_gain_bg <<= 2;
3857 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3859 struct ieee80211_hw *hw = wl->hw;
3861 ssb_set_devtypedata(dev, NULL);
3862 ieee80211_free_hw(hw);
3865 static int b43_wireless_init(struct ssb_device *dev)
3867 struct ssb_sprom *sprom = &dev->bus->sprom;
3868 struct ieee80211_hw *hw;
3872 b43_sprom_fixup(dev->bus);
3874 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3876 b43err(NULL, "Could not allocate ieee80211 device\n");
3881 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
3882 hw->max_signal = 100;
3883 hw->max_rssi = -110;
3884 hw->max_noise = -110;
3885 hw->queues = 1; /* FIXME: hardware has more queues */
3886 SET_IEEE80211_DEV(hw, dev->dev);
3887 if (is_valid_ether_addr(sprom->r1.et1mac))
3888 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
3890 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
3892 /* Get and initialize struct b43_wl */
3893 wl = hw_to_b43_wl(hw);
3894 memset(wl, 0, sizeof(*wl));
3896 spin_lock_init(&wl->irq_lock);
3897 spin_lock_init(&wl->leds_lock);
3898 mutex_init(&wl->mutex);
3899 INIT_LIST_HEAD(&wl->devlist);
3901 ssb_set_devtypedata(dev, wl);
3902 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3908 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3914 wl = ssb_get_devtypedata(dev);
3916 /* Probing the first core. Must setup common struct b43_wl */
3918 err = b43_wireless_init(dev);
3921 wl = ssb_get_devtypedata(dev);
3924 err = b43_one_core_attach(dev, wl);
3926 goto err_wireless_exit;
3929 err = ieee80211_register_hw(wl->hw);
3931 goto err_one_core_detach;
3937 err_one_core_detach:
3938 b43_one_core_detach(dev);
3941 b43_wireless_exit(dev, wl);
3945 static void b43_remove(struct ssb_device *dev)
3947 struct b43_wl *wl = ssb_get_devtypedata(dev);
3948 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3951 if (wl->current_dev == wldev)
3952 ieee80211_unregister_hw(wl->hw);
3954 b43_one_core_detach(dev);
3956 if (list_empty(&wl->devlist)) {
3957 /* Last core on the chip unregistered.
3958 * We can destroy common struct b43_wl.
3960 b43_wireless_exit(dev, wl);
3964 /* Perform a hardware reset. This can be called from any context. */
3965 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3967 /* Must avoid requeueing, if we are in shutdown. */
3968 if (b43_status(dev) < B43_STAT_INITIALIZED)
3970 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3971 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3976 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
3978 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3979 struct b43_wl *wl = wldev->wl;
3981 b43dbg(wl, "Suspending...\n");
3983 mutex_lock(&wl->mutex);
3984 wldev->suspend_init_status = b43_status(wldev);
3985 if (wldev->suspend_init_status >= B43_STAT_STARTED)
3986 b43_wireless_core_stop(wldev);
3987 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
3988 b43_wireless_core_exit(wldev);
3989 mutex_unlock(&wl->mutex);
3991 b43dbg(wl, "Device suspended.\n");
3996 static int b43_resume(struct ssb_device *dev)
3998 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3999 struct b43_wl *wl = wldev->wl;
4002 b43dbg(wl, "Resuming...\n");
4004 mutex_lock(&wl->mutex);
4005 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4006 err = b43_wireless_core_init(wldev);
4008 b43err(wl, "Resume failed at core init\n");
4012 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4013 err = b43_wireless_core_start(wldev);
4015 b43_wireless_core_exit(wldev);
4016 b43err(wl, "Resume failed at core start\n");
4020 mutex_unlock(&wl->mutex);
4022 b43dbg(wl, "Device resumed.\n");
4027 #else /* CONFIG_PM */
4028 # define b43_suspend NULL
4029 # define b43_resume NULL
4030 #endif /* CONFIG_PM */
4032 static struct ssb_driver b43_ssb_driver = {
4033 .name = KBUILD_MODNAME,
4034 .id_table = b43_ssb_tbl,
4036 .remove = b43_remove,
4037 .suspend = b43_suspend,
4038 .resume = b43_resume,
4041 static int __init b43_init(void)
4046 err = b43_pcmcia_init();
4049 err = ssb_driver_register(&b43_ssb_driver);
4051 goto err_pcmcia_exit;
4062 static void __exit b43_exit(void)
4064 ssb_driver_unregister(&b43_ssb_driver);
4069 module_init(b43_init)
4070 module_exit(b43_exit)