3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/moduleparam.h>
37 #include <linux/if_arp.h>
38 #include <linux/etherdevice.h>
39 #include <linux/firmware.h>
40 #include <linux/wireless.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
61 #include <linux/mmc/sdio_func.h>
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_LICENSE("GPL");
70 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
112 static int b43_modparam_pio = B43_PIO_DEFAULT;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
116 #ifdef CONFIG_B43_BCMA
117 static const struct bcma_device_id b43_bcma_tbl[] = {
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
123 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
126 #ifdef CONFIG_B43_SSB
127 static const struct ssb_device_id b43_ssb_tbl[] = {
128 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
130 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
140 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
143 /* Channel and ratetables are shared for all devices.
144 * They can't be const, because ieee80211 puts some precalculated
145 * data in there. This data is the same for all devices, so we don't
146 * get concurrency issues */
147 #define RATETAB_ENT(_rateid, _flags) \
149 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
150 .hw_value = (_rateid), \
155 * NOTE: When changing this, sync with xmit.c's
156 * b43_plcp_get_bitrate_idx_* functions!
158 static struct ieee80211_rate __b43_ratetable[] = {
159 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
160 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
161 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
162 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
163 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
164 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
165 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
166 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
173 #define b43_a_ratetable (__b43_ratetable + 4)
174 #define b43_a_ratetable_size 8
175 #define b43_b_ratetable (__b43_ratetable + 0)
176 #define b43_b_ratetable_size 4
177 #define b43_g_ratetable (__b43_ratetable + 0)
178 #define b43_g_ratetable_size 12
180 #define CHAN4G(_channel, _freq, _flags) { \
181 .band = IEEE80211_BAND_2GHZ, \
182 .center_freq = (_freq), \
183 .hw_value = (_channel), \
185 .max_antenna_gain = 0, \
188 static struct ieee80211_channel b43_2ghz_chantable[] = {
206 #define CHAN5G(_channel, _flags) { \
207 .band = IEEE80211_BAND_5GHZ, \
208 .center_freq = 5000 + (5 * (_channel)), \
209 .hw_value = (_channel), \
211 .max_antenna_gain = 0, \
214 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
215 CHAN5G(32, 0), CHAN5G(34, 0),
216 CHAN5G(36, 0), CHAN5G(38, 0),
217 CHAN5G(40, 0), CHAN5G(42, 0),
218 CHAN5G(44, 0), CHAN5G(46, 0),
219 CHAN5G(48, 0), CHAN5G(50, 0),
220 CHAN5G(52, 0), CHAN5G(54, 0),
221 CHAN5G(56, 0), CHAN5G(58, 0),
222 CHAN5G(60, 0), CHAN5G(62, 0),
223 CHAN5G(64, 0), CHAN5G(66, 0),
224 CHAN5G(68, 0), CHAN5G(70, 0),
225 CHAN5G(72, 0), CHAN5G(74, 0),
226 CHAN5G(76, 0), CHAN5G(78, 0),
227 CHAN5G(80, 0), CHAN5G(82, 0),
228 CHAN5G(84, 0), CHAN5G(86, 0),
229 CHAN5G(88, 0), CHAN5G(90, 0),
230 CHAN5G(92, 0), CHAN5G(94, 0),
231 CHAN5G(96, 0), CHAN5G(98, 0),
232 CHAN5G(100, 0), CHAN5G(102, 0),
233 CHAN5G(104, 0), CHAN5G(106, 0),
234 CHAN5G(108, 0), CHAN5G(110, 0),
235 CHAN5G(112, 0), CHAN5G(114, 0),
236 CHAN5G(116, 0), CHAN5G(118, 0),
237 CHAN5G(120, 0), CHAN5G(122, 0),
238 CHAN5G(124, 0), CHAN5G(126, 0),
239 CHAN5G(128, 0), CHAN5G(130, 0),
240 CHAN5G(132, 0), CHAN5G(134, 0),
241 CHAN5G(136, 0), CHAN5G(138, 0),
242 CHAN5G(140, 0), CHAN5G(142, 0),
243 CHAN5G(144, 0), CHAN5G(145, 0),
244 CHAN5G(146, 0), CHAN5G(147, 0),
245 CHAN5G(148, 0), CHAN5G(149, 0),
246 CHAN5G(150, 0), CHAN5G(151, 0),
247 CHAN5G(152, 0), CHAN5G(153, 0),
248 CHAN5G(154, 0), CHAN5G(155, 0),
249 CHAN5G(156, 0), CHAN5G(157, 0),
250 CHAN5G(158, 0), CHAN5G(159, 0),
251 CHAN5G(160, 0), CHAN5G(161, 0),
252 CHAN5G(162, 0), CHAN5G(163, 0),
253 CHAN5G(164, 0), CHAN5G(165, 0),
254 CHAN5G(166, 0), CHAN5G(168, 0),
255 CHAN5G(170, 0), CHAN5G(172, 0),
256 CHAN5G(174, 0), CHAN5G(176, 0),
257 CHAN5G(178, 0), CHAN5G(180, 0),
258 CHAN5G(182, 0), CHAN5G(184, 0),
259 CHAN5G(186, 0), CHAN5G(188, 0),
260 CHAN5G(190, 0), CHAN5G(192, 0),
261 CHAN5G(194, 0), CHAN5G(196, 0),
262 CHAN5G(198, 0), CHAN5G(200, 0),
263 CHAN5G(202, 0), CHAN5G(204, 0),
264 CHAN5G(206, 0), CHAN5G(208, 0),
265 CHAN5G(210, 0), CHAN5G(212, 0),
266 CHAN5G(214, 0), CHAN5G(216, 0),
267 CHAN5G(218, 0), CHAN5G(220, 0),
268 CHAN5G(222, 0), CHAN5G(224, 0),
269 CHAN5G(226, 0), CHAN5G(228, 0),
272 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
273 CHAN5G(34, 0), CHAN5G(36, 0),
274 CHAN5G(38, 0), CHAN5G(40, 0),
275 CHAN5G(42, 0), CHAN5G(44, 0),
276 CHAN5G(46, 0), CHAN5G(48, 0),
277 CHAN5G(52, 0), CHAN5G(56, 0),
278 CHAN5G(60, 0), CHAN5G(64, 0),
279 CHAN5G(100, 0), CHAN5G(104, 0),
280 CHAN5G(108, 0), CHAN5G(112, 0),
281 CHAN5G(116, 0), CHAN5G(120, 0),
282 CHAN5G(124, 0), CHAN5G(128, 0),
283 CHAN5G(132, 0), CHAN5G(136, 0),
284 CHAN5G(140, 0), CHAN5G(149, 0),
285 CHAN5G(153, 0), CHAN5G(157, 0),
286 CHAN5G(161, 0), CHAN5G(165, 0),
287 CHAN5G(184, 0), CHAN5G(188, 0),
288 CHAN5G(192, 0), CHAN5G(196, 0),
289 CHAN5G(200, 0), CHAN5G(204, 0),
290 CHAN5G(208, 0), CHAN5G(212, 0),
295 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
296 .band = IEEE80211_BAND_5GHZ,
297 .channels = b43_5ghz_nphy_chantable,
298 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
299 .bitrates = b43_a_ratetable,
300 .n_bitrates = b43_a_ratetable_size,
303 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
304 .band = IEEE80211_BAND_5GHZ,
305 .channels = b43_5ghz_aphy_chantable,
306 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
307 .bitrates = b43_a_ratetable,
308 .n_bitrates = b43_a_ratetable_size,
311 static struct ieee80211_supported_band b43_band_2GHz = {
312 .band = IEEE80211_BAND_2GHZ,
313 .channels = b43_2ghz_chantable,
314 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
315 .bitrates = b43_g_ratetable,
316 .n_bitrates = b43_g_ratetable_size,
319 static void b43_wireless_core_exit(struct b43_wldev *dev);
320 static int b43_wireless_core_init(struct b43_wldev *dev);
321 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
322 static int b43_wireless_core_start(struct b43_wldev *dev);
324 static int b43_ratelimit(struct b43_wl *wl)
326 if (!wl || !wl->current_dev)
328 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
330 /* We are up and running.
331 * Ratelimit the messages to avoid DoS over the net. */
332 return net_ratelimit();
335 void b43info(struct b43_wl *wl, const char *fmt, ...)
337 struct va_format vaf;
340 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
342 if (!b43_ratelimit(wl))
350 printk(KERN_INFO "b43-%s: %pV",
351 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
356 void b43err(struct b43_wl *wl, const char *fmt, ...)
358 struct va_format vaf;
361 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
363 if (!b43_ratelimit(wl))
371 printk(KERN_ERR "b43-%s ERROR: %pV",
372 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
377 void b43warn(struct b43_wl *wl, const char *fmt, ...)
379 struct va_format vaf;
382 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
384 if (!b43_ratelimit(wl))
392 printk(KERN_WARNING "b43-%s warning: %pV",
393 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
398 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
400 struct va_format vaf;
403 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
411 printk(KERN_DEBUG "b43-%s debug: %pV",
412 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
417 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
421 B43_WARN_ON(offset % 4 != 0);
423 macctl = b43_read32(dev, B43_MMIO_MACCTL);
424 if (macctl & B43_MACCTL_BE)
427 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
429 b43_write32(dev, B43_MMIO_RAM_DATA, val);
432 static inline void b43_shm_control_word(struct b43_wldev *dev,
433 u16 routing, u16 offset)
437 /* "offset" is the WORD offset. */
441 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
444 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
448 if (routing == B43_SHM_SHARED) {
449 B43_WARN_ON(offset & 0x0001);
450 if (offset & 0x0003) {
451 /* Unaligned access */
452 b43_shm_control_word(dev, routing, offset >> 2);
453 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
454 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
455 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
461 b43_shm_control_word(dev, routing, offset);
462 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
467 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
471 if (routing == B43_SHM_SHARED) {
472 B43_WARN_ON(offset & 0x0001);
473 if (offset & 0x0003) {
474 /* Unaligned access */
475 b43_shm_control_word(dev, routing, offset >> 2);
476 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
482 b43_shm_control_word(dev, routing, offset);
483 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
488 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
490 if (routing == B43_SHM_SHARED) {
491 B43_WARN_ON(offset & 0x0001);
492 if (offset & 0x0003) {
493 /* Unaligned access */
494 b43_shm_control_word(dev, routing, offset >> 2);
495 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
497 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
498 b43_write16(dev, B43_MMIO_SHM_DATA,
499 (value >> 16) & 0xFFFF);
504 b43_shm_control_word(dev, routing, offset);
505 b43_write32(dev, B43_MMIO_SHM_DATA, value);
508 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
510 if (routing == B43_SHM_SHARED) {
511 B43_WARN_ON(offset & 0x0001);
512 if (offset & 0x0003) {
513 /* Unaligned access */
514 b43_shm_control_word(dev, routing, offset >> 2);
515 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
520 b43_shm_control_word(dev, routing, offset);
521 b43_write16(dev, B43_MMIO_SHM_DATA, value);
525 u64 b43_hf_read(struct b43_wldev *dev)
529 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
531 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
533 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
538 /* Write HostFlags */
539 void b43_hf_write(struct b43_wldev *dev, u64 value)
543 lo = (value & 0x00000000FFFFULL);
544 mi = (value & 0x0000FFFF0000ULL) >> 16;
545 hi = (value & 0xFFFF00000000ULL) >> 32;
546 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
547 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
548 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
551 /* Read the firmware capabilities bitmask (Opensource firmware only) */
552 static u16 b43_fwcapa_read(struct b43_wldev *dev)
554 B43_WARN_ON(!dev->fw.opensource);
555 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
558 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
562 B43_WARN_ON(dev->dev->core_rev < 3);
564 /* The hardware guarantees us an atomic read, if we
565 * read the low register first. */
566 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
567 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
574 static void b43_time_lock(struct b43_wldev *dev)
578 macctl = b43_read32(dev, B43_MMIO_MACCTL);
579 macctl |= B43_MACCTL_TBTTHOLD;
580 b43_write32(dev, B43_MMIO_MACCTL, macctl);
581 /* Commit the write */
582 b43_read32(dev, B43_MMIO_MACCTL);
585 static void b43_time_unlock(struct b43_wldev *dev)
589 macctl = b43_read32(dev, B43_MMIO_MACCTL);
590 macctl &= ~B43_MACCTL_TBTTHOLD;
591 b43_write32(dev, B43_MMIO_MACCTL, macctl);
592 /* Commit the write */
593 b43_read32(dev, B43_MMIO_MACCTL);
596 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
600 B43_WARN_ON(dev->dev->core_rev < 3);
604 /* The hardware guarantees us an atomic write, if we
605 * write the low register first. */
606 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
608 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
612 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
615 b43_tsf_write_locked(dev, tsf);
616 b43_time_unlock(dev);
620 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
622 static const u8 zero_addr[ETH_ALEN] = { 0 };
629 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
633 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
636 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
639 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
642 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
646 u8 mac_bssid[ETH_ALEN * 2];
650 bssid = dev->wl->bssid;
651 mac = dev->wl->mac_addr;
653 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
655 memcpy(mac_bssid, mac, ETH_ALEN);
656 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
658 /* Write our MAC address and BSSID to template ram */
659 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
660 tmp = (u32) (mac_bssid[i + 0]);
661 tmp |= (u32) (mac_bssid[i + 1]) << 8;
662 tmp |= (u32) (mac_bssid[i + 2]) << 16;
663 tmp |= (u32) (mac_bssid[i + 3]) << 24;
664 b43_ram_write(dev, 0x20 + i, tmp);
668 static void b43_upload_card_macaddress(struct b43_wldev *dev)
670 b43_write_mac_bssid_templates(dev);
671 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
674 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
676 /* slot_time is in usec. */
677 /* This test used to exit for all but a G PHY. */
678 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
680 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
681 /* Shared memory location 0x0010 is the slot time and should be
682 * set to slot_time; however, this register is initially 0 and changing
683 * the value adversely affects the transmit rate for BCM4311
684 * devices. Until this behavior is unterstood, delete this step
686 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
690 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
692 b43_set_slot_time(dev, 9);
695 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
697 b43_set_slot_time(dev, 20);
700 /* DummyTransmission function, as documented on
701 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
703 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
705 struct b43_phy *phy = &dev->phy;
706 unsigned int i, max_loop;
718 buffer[0] = 0x000201CC;
721 buffer[0] = 0x000B846E;
724 for (i = 0; i < 5; i++)
725 b43_ram_write(dev, i * 4, buffer[i]);
727 b43_write16(dev, 0x0568, 0x0000);
728 if (dev->dev->core_rev < 11)
729 b43_write16(dev, 0x07C0, 0x0000);
731 b43_write16(dev, 0x07C0, 0x0100);
732 value = (ofdm ? 0x41 : 0x40);
733 b43_write16(dev, 0x050C, value);
734 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
735 b43_write16(dev, 0x0514, 0x1A02);
736 b43_write16(dev, 0x0508, 0x0000);
737 b43_write16(dev, 0x050A, 0x0000);
738 b43_write16(dev, 0x054C, 0x0000);
739 b43_write16(dev, 0x056A, 0x0014);
740 b43_write16(dev, 0x0568, 0x0826);
741 b43_write16(dev, 0x0500, 0x0000);
742 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
748 b43_write16(dev, 0x0502, 0x00D0);
751 b43_write16(dev, 0x0502, 0x0050);
754 b43_write16(dev, 0x0502, 0x0030);
757 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
758 b43_radio_write16(dev, 0x0051, 0x0017);
759 for (i = 0x00; i < max_loop; i++) {
760 value = b43_read16(dev, 0x050E);
765 for (i = 0x00; i < 0x0A; i++) {
766 value = b43_read16(dev, 0x050E);
771 for (i = 0x00; i < 0x19; i++) {
772 value = b43_read16(dev, 0x0690);
773 if (!(value & 0x0100))
777 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
778 b43_radio_write16(dev, 0x0051, 0x0037);
781 static void key_write(struct b43_wldev *dev,
782 u8 index, u8 algorithm, const u8 *key)
789 /* Key index/algo block */
790 kidx = b43_kidx_to_fw(dev, index);
791 value = ((kidx << 4) | algorithm);
792 b43_shm_write16(dev, B43_SHM_SHARED,
793 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
795 /* Write the key to the Key Table Pointer offset */
796 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
797 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
799 value |= (u16) (key[i + 1]) << 8;
800 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
804 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
806 u32 addrtmp[2] = { 0, 0, };
807 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
809 if (b43_new_kidx_api(dev))
810 pairwise_keys_start = B43_NR_GROUP_KEYS;
812 B43_WARN_ON(index < pairwise_keys_start);
813 /* We have four default TX keys and possibly four default RX keys.
814 * Physical mac 0 is mapped to physical key 4 or 8, depending
815 * on the firmware version.
816 * So we must adjust the index here.
818 index -= pairwise_keys_start;
819 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
822 addrtmp[0] = addr[0];
823 addrtmp[0] |= ((u32) (addr[1]) << 8);
824 addrtmp[0] |= ((u32) (addr[2]) << 16);
825 addrtmp[0] |= ((u32) (addr[3]) << 24);
826 addrtmp[1] = addr[4];
827 addrtmp[1] |= ((u32) (addr[5]) << 8);
830 /* Receive match transmitter address (RCMTA) mechanism */
831 b43_shm_write32(dev, B43_SHM_RCMTA,
832 (index * 2) + 0, addrtmp[0]);
833 b43_shm_write16(dev, B43_SHM_RCMTA,
834 (index * 2) + 1, addrtmp[1]);
837 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
838 * When a packet is received, the iv32 is checked.
839 * - if it doesn't the packet is returned without modification (and software
840 * decryption can be done). That's what happen when iv16 wrap.
841 * - if it does, the rc4 key is computed, and decryption is tried.
842 * Either it will success and B43_RX_MAC_DEC is returned,
843 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
844 * and the packet is not usable (it got modified by the ucode).
845 * So in order to never have B43_RX_MAC_DECERR, we should provide
846 * a iv32 and phase1key that match. Because we drop packets in case of
847 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
848 * packets will be lost without higher layer knowing (ie no resync possible
851 * NOTE : this should support 50 key like RCMTA because
852 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
854 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
859 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
861 if (!modparam_hwtkip)
864 if (b43_new_kidx_api(dev))
865 pairwise_keys_start = B43_NR_GROUP_KEYS;
867 B43_WARN_ON(index < pairwise_keys_start);
868 /* We have four default TX keys and possibly four default RX keys.
869 * Physical mac 0 is mapped to physical key 4 or 8, depending
870 * on the firmware version.
871 * So we must adjust the index here.
873 index -= pairwise_keys_start;
874 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
876 if (b43_debug(dev, B43_DBG_KEYS)) {
877 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
880 /* Write the key to the RX tkip shared mem */
881 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
882 for (i = 0; i < 10; i += 2) {
883 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
884 phase1key ? phase1key[i / 2] : 0);
886 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
887 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
890 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
891 struct ieee80211_vif *vif,
892 struct ieee80211_key_conf *keyconf,
893 struct ieee80211_sta *sta,
894 u32 iv32, u16 *phase1key)
896 struct b43_wl *wl = hw_to_b43_wl(hw);
897 struct b43_wldev *dev;
898 int index = keyconf->hw_key_idx;
900 if (B43_WARN_ON(!modparam_hwtkip))
903 /* This is only called from the RX path through mac80211, where
904 * our mutex is already locked. */
905 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
906 dev = wl->current_dev;
907 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
909 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
911 rx_tkip_phase1_write(dev, index, iv32, phase1key);
912 /* only pairwise TKIP keys are supported right now */
915 keymac_write(dev, index, sta->addr);
918 static void do_key_write(struct b43_wldev *dev,
919 u8 index, u8 algorithm,
920 const u8 *key, size_t key_len, const u8 *mac_addr)
922 u8 buf[B43_SEC_KEYSIZE] = { 0, };
923 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
925 if (b43_new_kidx_api(dev))
926 pairwise_keys_start = B43_NR_GROUP_KEYS;
928 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
929 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
931 if (index >= pairwise_keys_start)
932 keymac_write(dev, index, NULL); /* First zero out mac. */
933 if (algorithm == B43_SEC_ALGO_TKIP) {
935 * We should provide an initial iv32, phase1key pair.
936 * We could start with iv32=0 and compute the corresponding
937 * phase1key, but this means calling ieee80211_get_tkip_key
938 * with a fake skb (or export other tkip function).
939 * Because we are lazy we hope iv32 won't start with
940 * 0xffffffff and let's b43_op_update_tkip_key provide a
943 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
944 } else if (index >= pairwise_keys_start) /* clear it */
945 rx_tkip_phase1_write(dev, index, 0, NULL);
947 memcpy(buf, key, key_len);
948 key_write(dev, index, algorithm, buf);
949 if (index >= pairwise_keys_start)
950 keymac_write(dev, index, mac_addr);
952 dev->key[index].algorithm = algorithm;
955 static int b43_key_write(struct b43_wldev *dev,
956 int index, u8 algorithm,
957 const u8 *key, size_t key_len,
959 struct ieee80211_key_conf *keyconf)
962 int pairwise_keys_start;
964 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
965 * - Temporal Encryption Key (128 bits)
966 * - Temporal Authenticator Tx MIC Key (64 bits)
967 * - Temporal Authenticator Rx MIC Key (64 bits)
969 * Hardware only store TEK
971 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
973 if (key_len > B43_SEC_KEYSIZE)
975 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
976 /* Check that we don't already have this key. */
977 B43_WARN_ON(dev->key[i].keyconf == keyconf);
980 /* Pairwise key. Get an empty slot for the key. */
981 if (b43_new_kidx_api(dev))
982 pairwise_keys_start = B43_NR_GROUP_KEYS;
984 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
985 for (i = pairwise_keys_start;
986 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
988 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
989 if (!dev->key[i].keyconf) {
996 b43warn(dev->wl, "Out of hardware key memory\n");
1000 B43_WARN_ON(index > 3);
1002 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1003 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1004 /* Default RX key */
1005 B43_WARN_ON(mac_addr);
1006 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1008 keyconf->hw_key_idx = index;
1009 dev->key[index].keyconf = keyconf;
1014 static int b43_key_clear(struct b43_wldev *dev, int index)
1016 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1018 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1019 NULL, B43_SEC_KEYSIZE, NULL);
1020 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1021 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1022 NULL, B43_SEC_KEYSIZE, NULL);
1024 dev->key[index].keyconf = NULL;
1029 static void b43_clear_keys(struct b43_wldev *dev)
1033 if (b43_new_kidx_api(dev))
1034 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1036 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1037 for (i = 0; i < count; i++)
1038 b43_key_clear(dev, i);
1041 static void b43_dump_keymemory(struct b43_wldev *dev)
1043 unsigned int i, index, count, offset, pairwise_keys_start;
1049 struct b43_key *key;
1051 if (!b43_debug(dev, B43_DBG_KEYS))
1054 hf = b43_hf_read(dev);
1055 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1056 !!(hf & B43_HF_USEDEFKEYS));
1057 if (b43_new_kidx_api(dev)) {
1058 pairwise_keys_start = B43_NR_GROUP_KEYS;
1059 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1061 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1062 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1064 for (index = 0; index < count; index++) {
1065 key = &(dev->key[index]);
1066 printk(KERN_DEBUG "Key slot %02u: %s",
1067 index, (key->keyconf == NULL) ? " " : "*");
1068 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1069 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1070 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1071 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1074 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1075 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1076 printk(" Algo: %04X/%02X", algo, key->algorithm);
1078 if (index >= pairwise_keys_start) {
1079 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1081 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1082 for (i = 0; i < 14; i += 2) {
1083 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1084 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1087 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1088 ((index - pairwise_keys_start) * 2) + 0);
1089 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1090 ((index - pairwise_keys_start) * 2) + 1);
1091 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1092 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1093 printk(" MAC: %pM", mac);
1095 printk(" DEFAULT KEY");
1100 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1108 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1109 (ps_flags & B43_PS_DISABLED));
1110 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1112 if (ps_flags & B43_PS_ENABLED) {
1114 } else if (ps_flags & B43_PS_DISABLED) {
1117 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1118 // and thus is not an AP and we are associated, set bit 25
1120 if (ps_flags & B43_PS_AWAKE) {
1122 } else if (ps_flags & B43_PS_ASLEEP) {
1125 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1126 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1127 // successful, set bit26
1130 /* FIXME: For now we force awake-on and hwps-off */
1134 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1136 macctl |= B43_MACCTL_HWPS;
1138 macctl &= ~B43_MACCTL_HWPS;
1140 macctl |= B43_MACCTL_AWAKE;
1142 macctl &= ~B43_MACCTL_AWAKE;
1143 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1145 b43_read32(dev, B43_MMIO_MACCTL);
1146 if (awake && dev->dev->core_rev >= 5) {
1147 /* Wait for the microcode to wake up. */
1148 for (i = 0; i < 100; i++) {
1149 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1150 B43_SHM_SH_UCODESTAT);
1151 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1158 #ifdef CONFIG_B43_BCMA
1159 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1164 flags = B43_BCMA_IOCTL_GMODE;
1165 flags |= B43_BCMA_IOCTL_PHY_CLKEN;
1166 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1167 b43_device_enable(dev, flags);
1169 /* TODO: reset PHY */
1173 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1175 struct ssb_device *sdev = dev->dev->sdev;
1180 flags |= B43_TMSLOW_GMODE;
1181 flags |= B43_TMSLOW_PHYCLKEN;
1182 flags |= B43_TMSLOW_PHYRESET;
1183 if (dev->phy.type == B43_PHYTYPE_N)
1184 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1185 b43_device_enable(dev, flags);
1186 msleep(2); /* Wait for the PLL to turn on. */
1188 /* Now take the PHY out of Reset again */
1189 tmslow = ssb_read32(sdev, SSB_TMSLOW);
1190 tmslow |= SSB_TMSLOW_FGC;
1191 tmslow &= ~B43_TMSLOW_PHYRESET;
1192 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1193 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1195 tmslow &= ~SSB_TMSLOW_FGC;
1196 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1197 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1201 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1205 switch (dev->dev->bus_type) {
1206 #ifdef CONFIG_B43_BCMA
1208 b43_bcma_wireless_core_reset(dev, gmode);
1211 #ifdef CONFIG_B43_SSB
1213 b43_ssb_wireless_core_reset(dev, gmode);
1218 /* Turn Analog ON, but only if we already know the PHY-type.
1219 * This protects against very early setup where we don't know the
1220 * PHY-type, yet. wireless_core_reset will be called once again later,
1221 * when we know the PHY-type. */
1223 dev->phy.ops->switch_analog(dev, 1);
1225 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1226 macctl &= ~B43_MACCTL_GMODE;
1228 macctl |= B43_MACCTL_GMODE;
1229 macctl |= B43_MACCTL_IHR_ENABLED;
1230 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1233 static void handle_irq_transmit_status(struct b43_wldev *dev)
1237 struct b43_txstatus stat;
1240 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1241 if (!(v0 & 0x00000001))
1243 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1245 stat.cookie = (v0 >> 16);
1246 stat.seq = (v1 & 0x0000FFFF);
1247 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1248 tmp = (v0 & 0x0000FFFF);
1249 stat.frame_count = ((tmp & 0xF000) >> 12);
1250 stat.rts_count = ((tmp & 0x0F00) >> 8);
1251 stat.supp_reason = ((tmp & 0x001C) >> 2);
1252 stat.pm_indicated = !!(tmp & 0x0080);
1253 stat.intermediate = !!(tmp & 0x0040);
1254 stat.for_ampdu = !!(tmp & 0x0020);
1255 stat.acked = !!(tmp & 0x0002);
1257 b43_handle_txstatus(dev, &stat);
1261 static void drain_txstatus_queue(struct b43_wldev *dev)
1265 if (dev->dev->core_rev < 5)
1267 /* Read all entries from the microcode TXstatus FIFO
1268 * and throw them away.
1271 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1272 if (!(dummy & 0x00000001))
1274 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1278 static u32 b43_jssi_read(struct b43_wldev *dev)
1282 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1284 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1289 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1291 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1292 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1295 static void b43_generate_noise_sample(struct b43_wldev *dev)
1297 b43_jssi_write(dev, 0x7F7F7F7F);
1298 b43_write32(dev, B43_MMIO_MACCMD,
1299 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1302 static void b43_calculate_link_quality(struct b43_wldev *dev)
1304 /* Top half of Link Quality calculation. */
1306 if (dev->phy.type != B43_PHYTYPE_G)
1308 if (dev->noisecalc.calculation_running)
1310 dev->noisecalc.calculation_running = 1;
1311 dev->noisecalc.nr_samples = 0;
1313 b43_generate_noise_sample(dev);
1316 static void handle_irq_noise(struct b43_wldev *dev)
1318 struct b43_phy_g *phy = dev->phy.g;
1324 /* Bottom half of Link Quality calculation. */
1326 if (dev->phy.type != B43_PHYTYPE_G)
1329 /* Possible race condition: It might be possible that the user
1330 * changed to a different channel in the meantime since we
1331 * started the calculation. We ignore that fact, since it's
1332 * not really that much of a problem. The background noise is
1333 * an estimation only anyway. Slightly wrong results will get damped
1334 * by the averaging of the 8 sample rounds. Additionally the
1335 * value is shortlived. So it will be replaced by the next noise
1336 * calculation round soon. */
1338 B43_WARN_ON(!dev->noisecalc.calculation_running);
1339 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1340 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1341 noise[2] == 0x7F || noise[3] == 0x7F)
1344 /* Get the noise samples. */
1345 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1346 i = dev->noisecalc.nr_samples;
1347 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1348 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1349 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1350 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1351 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1352 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1353 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1354 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1355 dev->noisecalc.nr_samples++;
1356 if (dev->noisecalc.nr_samples == 8) {
1357 /* Calculate the Link Quality by the noise samples. */
1359 for (i = 0; i < 8; i++) {
1360 for (j = 0; j < 4; j++)
1361 average += dev->noisecalc.samples[i][j];
1367 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1368 tmp = (tmp / 128) & 0x1F;
1378 dev->stats.link_noise = average;
1379 dev->noisecalc.calculation_running = 0;
1383 b43_generate_noise_sample(dev);
1386 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1388 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1391 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1392 b43_power_saving_ctl_bits(dev, 0);
1394 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1398 static void handle_irq_atim_end(struct b43_wldev *dev)
1400 if (dev->dfq_valid) {
1401 b43_write32(dev, B43_MMIO_MACCMD,
1402 b43_read32(dev, B43_MMIO_MACCMD)
1403 | B43_MACCMD_DFQ_VALID);
1408 static void handle_irq_pmq(struct b43_wldev *dev)
1415 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1416 if (!(tmp & 0x00000008))
1419 /* 16bit write is odd, but correct. */
1420 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1423 static void b43_write_template_common(struct b43_wldev *dev,
1424 const u8 *data, u16 size,
1426 u16 shm_size_offset, u8 rate)
1429 struct b43_plcp_hdr4 plcp;
1432 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1433 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1434 ram_offset += sizeof(u32);
1435 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1436 * So leave the first two bytes of the next write blank.
1438 tmp = (u32) (data[0]) << 16;
1439 tmp |= (u32) (data[1]) << 24;
1440 b43_ram_write(dev, ram_offset, tmp);
1441 ram_offset += sizeof(u32);
1442 for (i = 2; i < size; i += sizeof(u32)) {
1443 tmp = (u32) (data[i + 0]);
1445 tmp |= (u32) (data[i + 1]) << 8;
1447 tmp |= (u32) (data[i + 2]) << 16;
1449 tmp |= (u32) (data[i + 3]) << 24;
1450 b43_ram_write(dev, ram_offset + i - 2, tmp);
1452 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1453 size + sizeof(struct b43_plcp_hdr6));
1456 /* Check if the use of the antenna that ieee80211 told us to
1457 * use is possible. This will fall back to DEFAULT.
1458 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1459 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1464 if (antenna_nr == 0) {
1465 /* Zero means "use default antenna". That's always OK. */
1469 /* Get the mask of available antennas. */
1471 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1473 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1475 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1476 /* This antenna is not available. Fall back to default. */
1483 /* Convert a b43 antenna number value to the PHY TX control value. */
1484 static u16 b43_antenna_to_phyctl(int antenna)
1488 return B43_TXH_PHY_ANT0;
1490 return B43_TXH_PHY_ANT1;
1492 return B43_TXH_PHY_ANT2;
1494 return B43_TXH_PHY_ANT3;
1495 case B43_ANTENNA_AUTO0:
1496 case B43_ANTENNA_AUTO1:
1497 return B43_TXH_PHY_ANT01AUTO;
1503 static void b43_write_beacon_template(struct b43_wldev *dev,
1505 u16 shm_size_offset)
1507 unsigned int i, len, variable_len;
1508 const struct ieee80211_mgmt *bcn;
1514 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1516 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1517 len = min((size_t) dev->wl->current_beacon->len,
1518 0x200 - sizeof(struct b43_plcp_hdr6));
1519 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1521 b43_write_template_common(dev, (const u8 *)bcn,
1522 len, ram_offset, shm_size_offset, rate);
1524 /* Write the PHY TX control parameters. */
1525 antenna = B43_ANTENNA_DEFAULT;
1526 antenna = b43_antenna_to_phyctl(antenna);
1527 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1528 /* We can't send beacons with short preamble. Would get PHY errors. */
1529 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1530 ctl &= ~B43_TXH_PHY_ANT;
1531 ctl &= ~B43_TXH_PHY_ENC;
1533 if (b43_is_cck_rate(rate))
1534 ctl |= B43_TXH_PHY_ENC_CCK;
1536 ctl |= B43_TXH_PHY_ENC_OFDM;
1537 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1539 /* Find the position of the TIM and the DTIM_period value
1540 * and write them to SHM. */
1541 ie = bcn->u.beacon.variable;
1542 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1543 for (i = 0; i < variable_len - 2; ) {
1544 uint8_t ie_id, ie_len;
1551 /* This is the TIM Information Element */
1553 /* Check whether the ie_len is in the beacon data range. */
1554 if (variable_len < ie_len + 2 + i)
1556 /* A valid TIM is at least 4 bytes long. */
1561 tim_position = sizeof(struct b43_plcp_hdr6);
1562 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1565 dtim_period = ie[i + 3];
1567 b43_shm_write16(dev, B43_SHM_SHARED,
1568 B43_SHM_SH_TIMBPOS, tim_position);
1569 b43_shm_write16(dev, B43_SHM_SHARED,
1570 B43_SHM_SH_DTIMPER, dtim_period);
1577 * If ucode wants to modify TIM do it behind the beacon, this
1578 * will happen, for example, when doing mesh networking.
1580 b43_shm_write16(dev, B43_SHM_SHARED,
1582 len + sizeof(struct b43_plcp_hdr6));
1583 b43_shm_write16(dev, B43_SHM_SHARED,
1584 B43_SHM_SH_DTIMPER, 0);
1586 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1589 static void b43_upload_beacon0(struct b43_wldev *dev)
1591 struct b43_wl *wl = dev->wl;
1593 if (wl->beacon0_uploaded)
1595 b43_write_beacon_template(dev, 0x68, 0x18);
1596 wl->beacon0_uploaded = 1;
1599 static void b43_upload_beacon1(struct b43_wldev *dev)
1601 struct b43_wl *wl = dev->wl;
1603 if (wl->beacon1_uploaded)
1605 b43_write_beacon_template(dev, 0x468, 0x1A);
1606 wl->beacon1_uploaded = 1;
1609 static void handle_irq_beacon(struct b43_wldev *dev)
1611 struct b43_wl *wl = dev->wl;
1612 u32 cmd, beacon0_valid, beacon1_valid;
1614 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1615 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1618 /* This is the bottom half of the asynchronous beacon update. */
1620 /* Ignore interrupt in the future. */
1621 dev->irq_mask &= ~B43_IRQ_BEACON;
1623 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1624 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1625 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1627 /* Schedule interrupt manually, if busy. */
1628 if (beacon0_valid && beacon1_valid) {
1629 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1630 dev->irq_mask |= B43_IRQ_BEACON;
1634 if (unlikely(wl->beacon_templates_virgin)) {
1635 /* We never uploaded a beacon before.
1636 * Upload both templates now, but only mark one valid. */
1637 wl->beacon_templates_virgin = 0;
1638 b43_upload_beacon0(dev);
1639 b43_upload_beacon1(dev);
1640 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1641 cmd |= B43_MACCMD_BEACON0_VALID;
1642 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1644 if (!beacon0_valid) {
1645 b43_upload_beacon0(dev);
1646 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1647 cmd |= B43_MACCMD_BEACON0_VALID;
1648 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1649 } else if (!beacon1_valid) {
1650 b43_upload_beacon1(dev);
1651 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1652 cmd |= B43_MACCMD_BEACON1_VALID;
1653 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1658 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1660 u32 old_irq_mask = dev->irq_mask;
1662 /* update beacon right away or defer to irq */
1663 handle_irq_beacon(dev);
1664 if (old_irq_mask != dev->irq_mask) {
1665 /* The handler updated the IRQ mask. */
1666 B43_WARN_ON(!dev->irq_mask);
1667 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1668 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1670 /* Device interrupts are currently disabled. That means
1671 * we just ran the hardirq handler and scheduled the
1672 * IRQ thread. The thread will write the IRQ mask when
1673 * it finished, so there's nothing to do here. Writing
1674 * the mask _here_ would incorrectly re-enable IRQs. */
1679 static void b43_beacon_update_trigger_work(struct work_struct *work)
1681 struct b43_wl *wl = container_of(work, struct b43_wl,
1682 beacon_update_trigger);
1683 struct b43_wldev *dev;
1685 mutex_lock(&wl->mutex);
1686 dev = wl->current_dev;
1687 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1688 if (b43_bus_host_is_sdio(dev->dev)) {
1689 /* wl->mutex is enough. */
1690 b43_do_beacon_update_trigger_work(dev);
1693 spin_lock_irq(&wl->hardirq_lock);
1694 b43_do_beacon_update_trigger_work(dev);
1696 spin_unlock_irq(&wl->hardirq_lock);
1699 mutex_unlock(&wl->mutex);
1702 /* Asynchronously update the packet templates in template RAM.
1703 * Locking: Requires wl->mutex to be locked. */
1704 static void b43_update_templates(struct b43_wl *wl)
1706 struct sk_buff *beacon;
1708 /* This is the top half of the ansynchronous beacon update.
1709 * The bottom half is the beacon IRQ.
1710 * Beacon update must be asynchronous to avoid sending an
1711 * invalid beacon. This can happen for example, if the firmware
1712 * transmits a beacon while we are updating it. */
1714 /* We could modify the existing beacon and set the aid bit in
1715 * the TIM field, but that would probably require resizing and
1716 * moving of data within the beacon template.
1717 * Simply request a new beacon and let mac80211 do the hard work. */
1718 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1719 if (unlikely(!beacon))
1722 if (wl->current_beacon)
1723 dev_kfree_skb_any(wl->current_beacon);
1724 wl->current_beacon = beacon;
1725 wl->beacon0_uploaded = 0;
1726 wl->beacon1_uploaded = 0;
1727 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1730 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1733 if (dev->dev->core_rev >= 3) {
1734 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1735 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1737 b43_write16(dev, 0x606, (beacon_int >> 6));
1738 b43_write16(dev, 0x610, beacon_int);
1740 b43_time_unlock(dev);
1741 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1744 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1748 /* Read the register that contains the reason code for the panic. */
1749 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1750 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1754 b43dbg(dev->wl, "The panic reason is unknown.\n");
1756 case B43_FWPANIC_DIE:
1757 /* Do not restart the controller or firmware.
1758 * The device is nonfunctional from now on.
1759 * Restarting would result in this panic to trigger again,
1760 * so we avoid that recursion. */
1762 case B43_FWPANIC_RESTART:
1763 b43_controller_restart(dev, "Microcode panic");
1768 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1770 unsigned int i, cnt;
1771 u16 reason, marker_id, marker_line;
1774 /* The proprietary firmware doesn't have this IRQ. */
1775 if (!dev->fw.opensource)
1778 /* Read the register that contains the reason code for this IRQ. */
1779 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1782 case B43_DEBUGIRQ_PANIC:
1783 b43_handle_firmware_panic(dev);
1785 case B43_DEBUGIRQ_DUMP_SHM:
1787 break; /* Only with driver debugging enabled. */
1788 buf = kmalloc(4096, GFP_ATOMIC);
1790 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1793 for (i = 0; i < 4096; i += 2) {
1794 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1795 buf[i / 2] = cpu_to_le16(tmp);
1797 b43info(dev->wl, "Shared memory dump:\n");
1798 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1799 16, 2, buf, 4096, 1);
1802 case B43_DEBUGIRQ_DUMP_REGS:
1804 break; /* Only with driver debugging enabled. */
1805 b43info(dev->wl, "Microcode register dump:\n");
1806 for (i = 0, cnt = 0; i < 64; i++) {
1807 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1810 printk("r%02u: 0x%04X ", i, tmp);
1819 case B43_DEBUGIRQ_MARKER:
1821 break; /* Only with driver debugging enabled. */
1822 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1824 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1825 B43_MARKER_LINE_REG);
1826 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1827 "at line number %u\n",
1828 marker_id, marker_line);
1831 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1835 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1836 b43_shm_write16(dev, B43_SHM_SCRATCH,
1837 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1840 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1843 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1844 u32 merged_dma_reason = 0;
1847 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1850 reason = dev->irq_reason;
1851 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1852 dma_reason[i] = dev->dma_reason[i];
1853 merged_dma_reason |= dma_reason[i];
1856 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1857 b43err(dev->wl, "MAC transmission error\n");
1859 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1860 b43err(dev->wl, "PHY transmission error\n");
1862 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1863 atomic_set(&dev->phy.txerr_cnt,
1864 B43_PHY_TX_BADNESS_LIMIT);
1865 b43err(dev->wl, "Too many PHY TX errors, "
1866 "restarting the controller\n");
1867 b43_controller_restart(dev, "PHY TX errors");
1871 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1872 B43_DMAIRQ_NONFATALMASK))) {
1873 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1874 b43err(dev->wl, "Fatal DMA error: "
1875 "0x%08X, 0x%08X, 0x%08X, "
1876 "0x%08X, 0x%08X, 0x%08X\n",
1877 dma_reason[0], dma_reason[1],
1878 dma_reason[2], dma_reason[3],
1879 dma_reason[4], dma_reason[5]);
1880 b43err(dev->wl, "This device does not support DMA "
1881 "on your system. It will now be switched to PIO.\n");
1882 /* Fall back to PIO transfers if we get fatal DMA errors! */
1884 b43_controller_restart(dev, "DMA error");
1887 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1888 b43err(dev->wl, "DMA error: "
1889 "0x%08X, 0x%08X, 0x%08X, "
1890 "0x%08X, 0x%08X, 0x%08X\n",
1891 dma_reason[0], dma_reason[1],
1892 dma_reason[2], dma_reason[3],
1893 dma_reason[4], dma_reason[5]);
1897 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1898 handle_irq_ucode_debug(dev);
1899 if (reason & B43_IRQ_TBTT_INDI)
1900 handle_irq_tbtt_indication(dev);
1901 if (reason & B43_IRQ_ATIM_END)
1902 handle_irq_atim_end(dev);
1903 if (reason & B43_IRQ_BEACON)
1904 handle_irq_beacon(dev);
1905 if (reason & B43_IRQ_PMQ)
1906 handle_irq_pmq(dev);
1907 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1909 if (reason & B43_IRQ_NOISESAMPLE_OK)
1910 handle_irq_noise(dev);
1912 /* Check the DMA reason registers for received data. */
1913 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1914 if (b43_using_pio_transfers(dev))
1915 b43_pio_rx(dev->pio.rx_queue);
1917 b43_dma_rx(dev->dma.rx_ring);
1919 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1920 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1921 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1922 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1923 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1925 if (reason & B43_IRQ_TX_OK)
1926 handle_irq_transmit_status(dev);
1928 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1929 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1932 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1934 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1935 if (reason & (1 << i))
1936 dev->irq_bit_count[i]++;
1942 /* Interrupt thread handler. Handles device interrupts in thread context. */
1943 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1945 struct b43_wldev *dev = dev_id;
1947 mutex_lock(&dev->wl->mutex);
1948 b43_do_interrupt_thread(dev);
1950 mutex_unlock(&dev->wl->mutex);
1955 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1959 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1960 * On SDIO, this runs under wl->mutex. */
1962 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1963 if (reason == 0xffffffff) /* shared IRQ */
1965 reason &= dev->irq_mask;
1969 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1971 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1973 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1975 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1977 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1980 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1984 /* ACK the interrupt. */
1985 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1986 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1987 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1988 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1989 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1990 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1992 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1995 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1996 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1997 /* Save the reason bitmasks for the IRQ thread handler. */
1998 dev->irq_reason = reason;
2000 return IRQ_WAKE_THREAD;
2003 /* Interrupt handler top-half. This runs with interrupts disabled. */
2004 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2006 struct b43_wldev *dev = dev_id;
2009 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2012 spin_lock(&dev->wl->hardirq_lock);
2013 ret = b43_do_interrupt(dev);
2015 spin_unlock(&dev->wl->hardirq_lock);
2020 /* SDIO interrupt handler. This runs in process context. */
2021 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2023 struct b43_wl *wl = dev->wl;
2026 mutex_lock(&wl->mutex);
2028 ret = b43_do_interrupt(dev);
2029 if (ret == IRQ_WAKE_THREAD)
2030 b43_do_interrupt_thread(dev);
2032 mutex_unlock(&wl->mutex);
2035 void b43_do_release_fw(struct b43_firmware_file *fw)
2037 release_firmware(fw->data);
2039 fw->filename = NULL;
2042 static void b43_release_firmware(struct b43_wldev *dev)
2044 b43_do_release_fw(&dev->fw.ucode);
2045 b43_do_release_fw(&dev->fw.pcm);
2046 b43_do_release_fw(&dev->fw.initvals);
2047 b43_do_release_fw(&dev->fw.initvals_band);
2050 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2054 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2055 "and download the correct firmware for this driver version. " \
2056 "Please carefully read all instructions on this website.\n";
2064 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2066 struct b43_firmware_file *fw)
2068 const struct firmware *blob;
2069 struct b43_fw_header *hdr;
2074 /* Don't fetch anything. Free possibly cached firmware. */
2075 /* FIXME: We should probably keep it anyway, to save some headache
2076 * on suspend/resume with multiband devices. */
2077 b43_do_release_fw(fw);
2081 if ((fw->type == ctx->req_type) &&
2082 (strcmp(fw->filename, name) == 0))
2083 return 0; /* Already have this fw. */
2084 /* Free the cached firmware first. */
2085 /* FIXME: We should probably do this later after we successfully
2086 * got the new fw. This could reduce headache with multiband devices.
2087 * We could also redesign this to cache the firmware for all possible
2088 * bands all the time. */
2089 b43_do_release_fw(fw);
2092 switch (ctx->req_type) {
2093 case B43_FWTYPE_PROPRIETARY:
2094 snprintf(ctx->fwname, sizeof(ctx->fwname),
2096 modparam_fwpostfix, name);
2098 case B43_FWTYPE_OPENSOURCE:
2099 snprintf(ctx->fwname, sizeof(ctx->fwname),
2101 modparam_fwpostfix, name);
2107 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2108 if (err == -ENOENT) {
2109 snprintf(ctx->errors[ctx->req_type],
2110 sizeof(ctx->errors[ctx->req_type]),
2111 "Firmware file \"%s\" not found\n", ctx->fwname);
2114 snprintf(ctx->errors[ctx->req_type],
2115 sizeof(ctx->errors[ctx->req_type]),
2116 "Firmware file \"%s\" request failed (err=%d)\n",
2120 if (blob->size < sizeof(struct b43_fw_header))
2122 hdr = (struct b43_fw_header *)(blob->data);
2123 switch (hdr->type) {
2124 case B43_FW_TYPE_UCODE:
2125 case B43_FW_TYPE_PCM:
2126 size = be32_to_cpu(hdr->size);
2127 if (size != blob->size - sizeof(struct b43_fw_header))
2130 case B43_FW_TYPE_IV:
2139 fw->filename = name;
2140 fw->type = ctx->req_type;
2145 snprintf(ctx->errors[ctx->req_type],
2146 sizeof(ctx->errors[ctx->req_type]),
2147 "Firmware file \"%s\" format error.\n", ctx->fwname);
2148 release_firmware(blob);
2153 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2155 struct b43_wldev *dev = ctx->dev;
2156 struct b43_firmware *fw = &ctx->dev->fw;
2157 const u8 rev = ctx->dev->dev->core_rev;
2158 const char *filename;
2163 if ((rev >= 5) && (rev <= 10)) {
2164 filename = "ucode5";
2165 } else if ((rev >= 11) && (rev <= 12)) {
2166 filename = "ucode11";
2167 } else if (rev == 13) {
2168 filename = "ucode13";
2169 } else if (rev == 14) {
2170 filename = "ucode14";
2171 } else if (rev == 15) {
2172 filename = "ucode15";
2174 switch (dev->phy.type) {
2177 filename = "ucode16_mimo";
2185 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2190 if ((rev >= 5) && (rev <= 10))
2196 fw->pcm_request_failed = 0;
2197 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2198 if (err == -ENOENT) {
2199 /* We did not find a PCM file? Not fatal, but
2200 * core rev <= 10 must do without hwcrypto then. */
2201 fw->pcm_request_failed = 1;
2206 switch (dev->phy.type) {
2208 if ((rev >= 5) && (rev <= 10)) {
2209 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2210 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2211 filename = "a0g1initvals5";
2213 filename = "a0g0initvals5";
2215 goto err_no_initvals;
2218 if ((rev >= 5) && (rev <= 10))
2219 filename = "b0g0initvals5";
2221 filename = "b0g0initvals13";
2223 goto err_no_initvals;
2227 filename = "n0initvals16";
2228 else if ((rev >= 11) && (rev <= 12))
2229 filename = "n0initvals11";
2231 goto err_no_initvals;
2233 case B43_PHYTYPE_LP:
2235 filename = "lp0initvals13";
2237 filename = "lp0initvals14";
2239 filename = "lp0initvals15";
2241 goto err_no_initvals;
2244 goto err_no_initvals;
2246 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2250 /* Get bandswitch initvals */
2251 switch (dev->phy.type) {
2253 if ((rev >= 5) && (rev <= 10)) {
2254 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2255 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2256 filename = "a0g1bsinitvals5";
2258 filename = "a0g0bsinitvals5";
2259 } else if (rev >= 11)
2262 goto err_no_initvals;
2265 if ((rev >= 5) && (rev <= 10))
2266 filename = "b0g0bsinitvals5";
2270 goto err_no_initvals;
2274 filename = "n0bsinitvals16";
2275 else if ((rev >= 11) && (rev <= 12))
2276 filename = "n0bsinitvals11";
2278 goto err_no_initvals;
2280 case B43_PHYTYPE_LP:
2282 filename = "lp0bsinitvals13";
2284 filename = "lp0bsinitvals14";
2286 filename = "lp0bsinitvals15";
2288 goto err_no_initvals;
2291 goto err_no_initvals;
2293 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2300 err = ctx->fatal_failure = -EOPNOTSUPP;
2301 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2302 "is required for your device (wl-core rev %u)\n", rev);
2306 err = ctx->fatal_failure = -EOPNOTSUPP;
2307 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2308 "is required for your device (wl-core rev %u)\n", rev);
2312 err = ctx->fatal_failure = -EOPNOTSUPP;
2313 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2314 "is required for your device (wl-core rev %u)\n", rev);
2318 /* We failed to load this firmware image. The error message
2319 * already is in ctx->errors. Return and let our caller decide
2324 b43_release_firmware(dev);
2328 static int b43_request_firmware(struct b43_wldev *dev)
2330 struct b43_request_fw_context *ctx;
2335 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2340 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2341 err = b43_try_request_fw(ctx);
2343 goto out; /* Successfully loaded it. */
2344 err = ctx->fatal_failure;
2348 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2349 err = b43_try_request_fw(ctx);
2351 goto out; /* Successfully loaded it. */
2352 err = ctx->fatal_failure;
2356 /* Could not find a usable firmware. Print the errors. */
2357 for (i = 0; i < B43_NR_FWTYPES; i++) {
2358 errmsg = ctx->errors[i];
2360 b43err(dev->wl, errmsg);
2362 b43_print_fw_helptext(dev->wl, 1);
2370 static int b43_upload_microcode(struct b43_wldev *dev)
2372 struct wiphy *wiphy = dev->wl->hw->wiphy;
2373 const size_t hdr_len = sizeof(struct b43_fw_header);
2375 unsigned int i, len;
2376 u16 fwrev, fwpatch, fwdate, fwtime;
2380 /* Jump the microcode PSM to offset 0 */
2381 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2382 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2383 macctl |= B43_MACCTL_PSM_JMP0;
2384 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2385 /* Zero out all microcode PSM registers and shared memory. */
2386 for (i = 0; i < 64; i++)
2387 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2388 for (i = 0; i < 4096; i += 2)
2389 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2391 /* Upload Microcode. */
2392 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2393 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2394 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2395 for (i = 0; i < len; i++) {
2396 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2400 if (dev->fw.pcm.data) {
2401 /* Upload PCM data. */
2402 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2403 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2404 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2405 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2406 /* No need for autoinc bit in SHM_HW */
2407 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2408 for (i = 0; i < len; i++) {
2409 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2414 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2416 /* Start the microcode PSM */
2417 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2418 macctl &= ~B43_MACCTL_PSM_JMP0;
2419 macctl |= B43_MACCTL_PSM_RUN;
2420 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2422 /* Wait for the microcode to load and respond */
2425 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2426 if (tmp == B43_IRQ_MAC_SUSPENDED)
2430 b43err(dev->wl, "Microcode not responding\n");
2431 b43_print_fw_helptext(dev->wl, 1);
2437 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2439 /* Get and check the revisions. */
2440 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2441 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2442 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2443 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2445 if (fwrev <= 0x128) {
2446 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2447 "binary drivers older than version 4.x is unsupported. "
2448 "You must upgrade your firmware files.\n");
2449 b43_print_fw_helptext(dev->wl, 1);
2453 dev->fw.rev = fwrev;
2454 dev->fw.patch = fwpatch;
2455 dev->fw.opensource = (fwdate == 0xFFFF);
2457 /* Default to use-all-queues. */
2458 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2459 dev->qos_enabled = !!modparam_qos;
2460 /* Default to firmware/hardware crypto acceleration. */
2461 dev->hwcrypto_enabled = 1;
2463 if (dev->fw.opensource) {
2466 /* Patchlevel info is encoded in the "time" field. */
2467 dev->fw.patch = fwtime;
2468 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2469 dev->fw.rev, dev->fw.patch);
2471 fwcapa = b43_fwcapa_read(dev);
2472 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2473 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2474 /* Disable hardware crypto and fall back to software crypto. */
2475 dev->hwcrypto_enabled = 0;
2477 if (!(fwcapa & B43_FWCAPA_QOS)) {
2478 b43info(dev->wl, "QoS not supported by firmware\n");
2479 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2480 * ieee80211_unregister to make sure the networking core can
2481 * properly free possible resources. */
2482 dev->wl->hw->queues = 1;
2483 dev->qos_enabled = 0;
2486 b43info(dev->wl, "Loading firmware version %u.%u "
2487 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2489 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2490 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2491 if (dev->fw.pcm_request_failed) {
2492 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2493 "Hardware accelerated cryptography is disabled.\n");
2494 b43_print_fw_helptext(dev->wl, 0);
2498 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2499 dev->fw.rev, dev->fw.patch);
2500 wiphy->hw_version = dev->dev->core_id;
2502 if (b43_is_old_txhdr_format(dev)) {
2503 /* We're over the deadline, but we keep support for old fw
2504 * until it turns out to be in major conflict with something new. */
2505 b43warn(dev->wl, "You are using an old firmware image. "
2506 "Support for old firmware will be removed soon "
2507 "(official deadline was July 2008).\n");
2508 b43_print_fw_helptext(dev->wl, 0);
2514 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2515 macctl &= ~B43_MACCTL_PSM_RUN;
2516 macctl |= B43_MACCTL_PSM_JMP0;
2517 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2522 static int b43_write_initvals(struct b43_wldev *dev,
2523 const struct b43_iv *ivals,
2527 const struct b43_iv *iv;
2532 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2534 for (i = 0; i < count; i++) {
2535 if (array_size < sizeof(iv->offset_size))
2537 array_size -= sizeof(iv->offset_size);
2538 offset = be16_to_cpu(iv->offset_size);
2539 bit32 = !!(offset & B43_IV_32BIT);
2540 offset &= B43_IV_OFFSET_MASK;
2541 if (offset >= 0x1000)
2546 if (array_size < sizeof(iv->data.d32))
2548 array_size -= sizeof(iv->data.d32);
2550 value = get_unaligned_be32(&iv->data.d32);
2551 b43_write32(dev, offset, value);
2553 iv = (const struct b43_iv *)((const uint8_t *)iv +
2559 if (array_size < sizeof(iv->data.d16))
2561 array_size -= sizeof(iv->data.d16);
2563 value = be16_to_cpu(iv->data.d16);
2564 b43_write16(dev, offset, value);
2566 iv = (const struct b43_iv *)((const uint8_t *)iv +
2577 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2578 b43_print_fw_helptext(dev->wl, 1);
2583 static int b43_upload_initvals(struct b43_wldev *dev)
2585 const size_t hdr_len = sizeof(struct b43_fw_header);
2586 const struct b43_fw_header *hdr;
2587 struct b43_firmware *fw = &dev->fw;
2588 const struct b43_iv *ivals;
2592 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2593 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2594 count = be32_to_cpu(hdr->size);
2595 err = b43_write_initvals(dev, ivals, count,
2596 fw->initvals.data->size - hdr_len);
2599 if (fw->initvals_band.data) {
2600 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2601 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2602 count = be32_to_cpu(hdr->size);
2603 err = b43_write_initvals(dev, ivals, count,
2604 fw->initvals_band.data->size - hdr_len);
2613 /* Initialize the GPIOs
2614 * http://bcm-specs.sipsolutions.net/GPIO
2616 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2618 struct ssb_bus *bus = dev->dev->sdev->bus;
2620 #ifdef CONFIG_SSB_DRIVER_PCICORE
2621 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2623 return bus->chipco.dev;
2627 static int b43_gpio_init(struct b43_wldev *dev)
2629 struct ssb_device *gpiodev;
2632 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2633 & ~B43_MACCTL_GPOUTSMSK);
2635 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2640 if (dev->dev->chip_id == 0x4301) {
2644 if (0 /* FIXME: conditional unknown */ ) {
2645 b43_write16(dev, B43_MMIO_GPIO_MASK,
2646 b43_read16(dev, B43_MMIO_GPIO_MASK)
2651 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2652 b43_write16(dev, B43_MMIO_GPIO_MASK,
2653 b43_read16(dev, B43_MMIO_GPIO_MASK)
2658 if (dev->dev->core_rev >= 2)
2659 mask |= 0x0010; /* FIXME: This is redundant. */
2661 switch (dev->dev->bus_type) {
2662 #ifdef CONFIG_B43_BCMA
2664 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2665 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2666 BCMA_CC_GPIOCTL) & mask) | set);
2669 #ifdef CONFIG_B43_SSB
2671 gpiodev = b43_ssb_gpio_dev(dev);
2673 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2674 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2683 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2684 static void b43_gpio_cleanup(struct b43_wldev *dev)
2686 struct ssb_device *gpiodev;
2688 switch (dev->dev->bus_type) {
2689 #ifdef CONFIG_B43_BCMA
2691 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2695 #ifdef CONFIG_B43_SSB
2697 gpiodev = b43_ssb_gpio_dev(dev);
2699 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2705 /* http://bcm-specs.sipsolutions.net/EnableMac */
2706 void b43_mac_enable(struct b43_wldev *dev)
2708 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2711 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2712 B43_SHM_SH_UCODESTAT);
2713 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2714 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2715 b43err(dev->wl, "b43_mac_enable(): The firmware "
2716 "should be suspended, but current state is %u\n",
2721 dev->mac_suspended--;
2722 B43_WARN_ON(dev->mac_suspended < 0);
2723 if (dev->mac_suspended == 0) {
2724 b43_write32(dev, B43_MMIO_MACCTL,
2725 b43_read32(dev, B43_MMIO_MACCTL)
2726 | B43_MACCTL_ENABLED);
2727 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2728 B43_IRQ_MAC_SUSPENDED);
2730 b43_read32(dev, B43_MMIO_MACCTL);
2731 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2732 b43_power_saving_ctl_bits(dev, 0);
2736 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2737 void b43_mac_suspend(struct b43_wldev *dev)
2743 B43_WARN_ON(dev->mac_suspended < 0);
2745 if (dev->mac_suspended == 0) {
2746 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2747 b43_write32(dev, B43_MMIO_MACCTL,
2748 b43_read32(dev, B43_MMIO_MACCTL)
2749 & ~B43_MACCTL_ENABLED);
2750 /* force pci to flush the write */
2751 b43_read32(dev, B43_MMIO_MACCTL);
2752 for (i = 35; i; i--) {
2753 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2754 if (tmp & B43_IRQ_MAC_SUSPENDED)
2758 /* Hm, it seems this will take some time. Use msleep(). */
2759 for (i = 40; i; i--) {
2760 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2761 if (tmp & B43_IRQ_MAC_SUSPENDED)
2765 b43err(dev->wl, "MAC suspend failed\n");
2768 dev->mac_suspended++;
2771 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2772 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2776 switch (dev->dev->bus_type) {
2777 #ifdef CONFIG_B43_BCMA
2779 tmp = bcma_read32(dev->dev->bdev, BCMA_IOCTL);
2781 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2783 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2784 bcma_write32(dev->dev->bdev, BCMA_IOCTL, tmp);
2787 #ifdef CONFIG_B43_SSB
2789 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2791 tmp |= B43_TMSLOW_MACPHYCLKEN;
2793 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2794 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2800 static void b43_adjust_opmode(struct b43_wldev *dev)
2802 struct b43_wl *wl = dev->wl;
2806 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2807 /* Reset status to STA infrastructure mode. */
2808 ctl &= ~B43_MACCTL_AP;
2809 ctl &= ~B43_MACCTL_KEEP_CTL;
2810 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2811 ctl &= ~B43_MACCTL_KEEP_BAD;
2812 ctl &= ~B43_MACCTL_PROMISC;
2813 ctl &= ~B43_MACCTL_BEACPROMISC;
2814 ctl |= B43_MACCTL_INFRA;
2816 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2817 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2818 ctl |= B43_MACCTL_AP;
2819 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2820 ctl &= ~B43_MACCTL_INFRA;
2822 if (wl->filter_flags & FIF_CONTROL)
2823 ctl |= B43_MACCTL_KEEP_CTL;
2824 if (wl->filter_flags & FIF_FCSFAIL)
2825 ctl |= B43_MACCTL_KEEP_BAD;
2826 if (wl->filter_flags & FIF_PLCPFAIL)
2827 ctl |= B43_MACCTL_KEEP_BADPLCP;
2828 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2829 ctl |= B43_MACCTL_PROMISC;
2830 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2831 ctl |= B43_MACCTL_BEACPROMISC;
2833 /* Workaround: On old hardware the HW-MAC-address-filter
2834 * doesn't work properly, so always run promisc in filter
2835 * it in software. */
2836 if (dev->dev->core_rev <= 4)
2837 ctl |= B43_MACCTL_PROMISC;
2839 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2842 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2843 if (dev->dev->chip_id == 0x4306 &&
2844 dev->dev->chip_rev == 3)
2849 b43_write16(dev, 0x612, cfp_pretbtt);
2851 /* FIXME: We don't currently implement the PMQ mechanism,
2852 * so always disable it. If we want to implement PMQ,
2853 * we need to enable it here (clear DISCPMQ) in AP mode.
2855 if (0 /* ctl & B43_MACCTL_AP */) {
2856 b43_write32(dev, B43_MMIO_MACCTL,
2857 b43_read32(dev, B43_MMIO_MACCTL)
2858 & ~B43_MACCTL_DISCPMQ);
2860 b43_write32(dev, B43_MMIO_MACCTL,
2861 b43_read32(dev, B43_MMIO_MACCTL)
2862 | B43_MACCTL_DISCPMQ);
2866 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2872 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2875 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2877 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2878 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2881 static void b43_rate_memory_init(struct b43_wldev *dev)
2883 switch (dev->phy.type) {
2887 case B43_PHYTYPE_LP:
2888 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2889 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2890 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2891 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2892 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2893 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2894 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2895 if (dev->phy.type == B43_PHYTYPE_A)
2899 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2900 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2901 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2902 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2909 /* Set the default values for the PHY TX Control Words. */
2910 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2914 ctl |= B43_TXH_PHY_ENC_CCK;
2915 ctl |= B43_TXH_PHY_ANT01AUTO;
2916 ctl |= B43_TXH_PHY_TXPWR;
2918 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2919 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2920 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2923 /* Set the TX-Antenna for management frames sent by firmware. */
2924 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2929 ant = b43_antenna_to_phyctl(antenna);
2932 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2933 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2934 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2935 /* For Probe Resposes */
2936 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2937 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2938 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2941 /* This is the opposite of b43_chip_init() */
2942 static void b43_chip_exit(struct b43_wldev *dev)
2945 b43_gpio_cleanup(dev);
2946 /* firmware is released later */
2949 /* Initialize the chip
2950 * http://bcm-specs.sipsolutions.net/ChipInit
2952 static int b43_chip_init(struct b43_wldev *dev)
2954 struct b43_phy *phy = &dev->phy;
2959 /* Initialize the MAC control */
2960 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2962 macctl |= B43_MACCTL_GMODE;
2963 macctl |= B43_MACCTL_INFRA;
2964 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2966 err = b43_request_firmware(dev);
2969 err = b43_upload_microcode(dev);
2971 goto out; /* firmware is released later */
2973 err = b43_gpio_init(dev);
2975 goto out; /* firmware is released later */
2977 err = b43_upload_initvals(dev);
2979 goto err_gpio_clean;
2981 /* Turn the Analog on and initialize the PHY. */
2982 phy->ops->switch_analog(dev, 1);
2983 err = b43_phy_init(dev);
2985 goto err_gpio_clean;
2987 /* Disable Interference Mitigation. */
2988 if (phy->ops->interf_mitigation)
2989 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2991 /* Select the antennae */
2992 if (phy->ops->set_rx_antenna)
2993 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2994 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2996 if (phy->type == B43_PHYTYPE_B) {
2997 value16 = b43_read16(dev, 0x005E);
2999 b43_write16(dev, 0x005E, value16);
3001 b43_write32(dev, 0x0100, 0x01000000);
3002 if (dev->dev->core_rev < 5)
3003 b43_write32(dev, 0x010C, 0x01000000);
3005 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3006 & ~B43_MACCTL_INFRA);
3007 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3008 | B43_MACCTL_INFRA);
3010 /* Probe Response Timeout value */
3011 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3012 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3014 /* Initially set the wireless operation mode. */
3015 b43_adjust_opmode(dev);
3017 if (dev->dev->core_rev < 3) {
3018 b43_write16(dev, 0x060E, 0x0000);
3019 b43_write16(dev, 0x0610, 0x8000);
3020 b43_write16(dev, 0x0604, 0x0000);
3021 b43_write16(dev, 0x0606, 0x0200);
3023 b43_write32(dev, 0x0188, 0x80000000);
3024 b43_write32(dev, 0x018C, 0x02000000);
3026 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3027 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3028 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3029 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3030 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3031 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3032 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3034 b43_mac_phy_clock_set(dev, true);
3036 switch (dev->dev->bus_type) {
3037 #ifdef CONFIG_B43_BCMA
3039 /* FIXME: 0xE74 is quite common, but should be read from CC */
3040 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3043 #ifdef CONFIG_B43_SSB
3045 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3046 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3052 b43dbg(dev->wl, "Chip initialized\n");
3057 b43_gpio_cleanup(dev);
3061 static void b43_periodic_every60sec(struct b43_wldev *dev)
3063 const struct b43_phy_operations *ops = dev->phy.ops;
3065 if (ops->pwork_60sec)
3066 ops->pwork_60sec(dev);
3068 /* Force check the TX power emission now. */
3069 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3072 static void b43_periodic_every30sec(struct b43_wldev *dev)
3074 /* Update device statistics. */
3075 b43_calculate_link_quality(dev);
3078 static void b43_periodic_every15sec(struct b43_wldev *dev)
3080 struct b43_phy *phy = &dev->phy;
3083 if (dev->fw.opensource) {
3084 /* Check if the firmware is still alive.
3085 * It will reset the watchdog counter to 0 in its idle loop. */
3086 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3087 if (unlikely(wdr)) {
3088 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3089 b43_controller_restart(dev, "Firmware watchdog");
3092 b43_shm_write16(dev, B43_SHM_SCRATCH,
3093 B43_WATCHDOG_REG, 1);
3097 if (phy->ops->pwork_15sec)
3098 phy->ops->pwork_15sec(dev);
3100 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3104 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3107 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3108 dev->irq_count / 15,
3110 dev->rx_count / 15);
3114 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3115 if (dev->irq_bit_count[i]) {
3116 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3117 dev->irq_bit_count[i] / 15, i, (1 << i));
3118 dev->irq_bit_count[i] = 0;
3125 static void do_periodic_work(struct b43_wldev *dev)
3129 state = dev->periodic_state;
3131 b43_periodic_every60sec(dev);
3133 b43_periodic_every30sec(dev);
3134 b43_periodic_every15sec(dev);
3137 /* Periodic work locking policy:
3138 * The whole periodic work handler is protected by
3139 * wl->mutex. If another lock is needed somewhere in the
3140 * pwork callchain, it's acquired in-place, where it's needed.
3142 static void b43_periodic_work_handler(struct work_struct *work)
3144 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3145 periodic_work.work);
3146 struct b43_wl *wl = dev->wl;
3147 unsigned long delay;
3149 mutex_lock(&wl->mutex);
3151 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3153 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3156 do_periodic_work(dev);
3158 dev->periodic_state++;
3160 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3161 delay = msecs_to_jiffies(50);
3163 delay = round_jiffies_relative(HZ * 15);
3164 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3166 mutex_unlock(&wl->mutex);
3169 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3171 struct delayed_work *work = &dev->periodic_work;
3173 dev->periodic_state = 0;
3174 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3175 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3178 /* Check if communication with the device works correctly. */
3179 static int b43_validate_chipaccess(struct b43_wldev *dev)
3181 u32 v, backup0, backup4;
3183 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3184 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3186 /* Check for read/write and endianness problems. */
3187 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3188 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3190 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3191 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3194 /* Check if unaligned 32bit SHM_SHARED access works properly.
3195 * However, don't bail out on failure, because it's noncritical. */
3196 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3197 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3198 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3199 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3200 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3201 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3202 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3203 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3204 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3205 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3206 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3207 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3209 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3210 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3212 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3213 /* The 32bit register shadows the two 16bit registers
3214 * with update sideeffects. Validate this. */
3215 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3216 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3217 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3219 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3222 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3224 v = b43_read32(dev, B43_MMIO_MACCTL);
3225 v |= B43_MACCTL_GMODE;
3226 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3231 b43err(dev->wl, "Failed to validate the chipaccess\n");
3235 static void b43_security_init(struct b43_wldev *dev)
3237 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3238 /* KTP is a word address, but we address SHM bytewise.
3239 * So multiply by two.
3242 /* Number of RCMTA address slots */
3243 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3244 /* Clear the key memory. */
3245 b43_clear_keys(dev);
3248 #ifdef CONFIG_B43_HWRNG
3249 static int b43_rng_read(struct hwrng *rng, u32 *data)
3251 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3252 struct b43_wldev *dev;
3253 int count = -ENODEV;
3255 mutex_lock(&wl->mutex);
3256 dev = wl->current_dev;
3257 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3258 *data = b43_read16(dev, B43_MMIO_RNG);
3259 count = sizeof(u16);
3261 mutex_unlock(&wl->mutex);
3265 #endif /* CONFIG_B43_HWRNG */
3267 static void b43_rng_exit(struct b43_wl *wl)
3269 #ifdef CONFIG_B43_HWRNG
3270 if (wl->rng_initialized)
3271 hwrng_unregister(&wl->rng);
3272 #endif /* CONFIG_B43_HWRNG */
3275 static int b43_rng_init(struct b43_wl *wl)
3279 #ifdef CONFIG_B43_HWRNG
3280 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3281 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3282 wl->rng.name = wl->rng_name;
3283 wl->rng.data_read = b43_rng_read;
3284 wl->rng.priv = (unsigned long)wl;
3285 wl->rng_initialized = 1;
3286 err = hwrng_register(&wl->rng);
3288 wl->rng_initialized = 0;
3289 b43err(wl, "Failed to register the random "
3290 "number generator (%d)\n", err);
3292 #endif /* CONFIG_B43_HWRNG */
3297 static void b43_tx_work(struct work_struct *work)
3299 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3300 struct b43_wldev *dev;
3301 struct sk_buff *skb;
3304 mutex_lock(&wl->mutex);
3305 dev = wl->current_dev;
3306 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3307 mutex_unlock(&wl->mutex);
3311 while (skb_queue_len(&wl->tx_queue)) {
3312 skb = skb_dequeue(&wl->tx_queue);
3314 if (b43_using_pio_transfers(dev))
3315 err = b43_pio_tx(dev, skb);
3317 err = b43_dma_tx(dev, skb);
3319 dev_kfree_skb(skb); /* Drop it */
3325 mutex_unlock(&wl->mutex);
3328 static void b43_op_tx(struct ieee80211_hw *hw,
3329 struct sk_buff *skb)
3331 struct b43_wl *wl = hw_to_b43_wl(hw);
3333 if (unlikely(skb->len < 2 + 2 + 6)) {
3334 /* Too short, this can't be a valid frame. */
3335 dev_kfree_skb_any(skb);
3338 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3340 skb_queue_tail(&wl->tx_queue, skb);
3341 ieee80211_queue_work(wl->hw, &wl->tx_work);
3344 static void b43_qos_params_upload(struct b43_wldev *dev,
3345 const struct ieee80211_tx_queue_params *p,
3348 u16 params[B43_NR_QOSPARAMS];
3352 if (!dev->qos_enabled)
3355 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3357 memset(¶ms, 0, sizeof(params));
3359 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3360 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3361 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3362 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3363 params[B43_QOSPARAM_AIFS] = p->aifs;
3364 params[B43_QOSPARAM_BSLOTS] = bslots;
3365 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3367 for (i = 0; i < ARRAY_SIZE(params); i++) {
3368 if (i == B43_QOSPARAM_STATUS) {
3369 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3370 shm_offset + (i * 2));
3371 /* Mark the parameters as updated. */
3373 b43_shm_write16(dev, B43_SHM_SHARED,
3374 shm_offset + (i * 2),
3377 b43_shm_write16(dev, B43_SHM_SHARED,
3378 shm_offset + (i * 2),
3384 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3385 static const u16 b43_qos_shm_offsets[] = {
3386 /* [mac80211-queue-nr] = SHM_OFFSET, */
3387 [0] = B43_QOS_VOICE,
3388 [1] = B43_QOS_VIDEO,
3389 [2] = B43_QOS_BESTEFFORT,
3390 [3] = B43_QOS_BACKGROUND,
3393 /* Update all QOS parameters in hardware. */
3394 static void b43_qos_upload_all(struct b43_wldev *dev)
3396 struct b43_wl *wl = dev->wl;
3397 struct b43_qos_params *params;
3400 if (!dev->qos_enabled)
3403 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3404 ARRAY_SIZE(wl->qos_params));
3406 b43_mac_suspend(dev);
3407 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3408 params = &(wl->qos_params[i]);
3409 b43_qos_params_upload(dev, &(params->p),
3410 b43_qos_shm_offsets[i]);
3412 b43_mac_enable(dev);
3415 static void b43_qos_clear(struct b43_wl *wl)
3417 struct b43_qos_params *params;
3420 /* Initialize QoS parameters to sane defaults. */
3422 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3423 ARRAY_SIZE(wl->qos_params));
3425 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3426 params = &(wl->qos_params[i]);
3428 switch (b43_qos_shm_offsets[i]) {
3432 params->p.cw_min = 0x0001;
3433 params->p.cw_max = 0x0001;
3438 params->p.cw_min = 0x0001;
3439 params->p.cw_max = 0x0001;
3441 case B43_QOS_BESTEFFORT:
3444 params->p.cw_min = 0x0001;
3445 params->p.cw_max = 0x03FF;
3447 case B43_QOS_BACKGROUND:
3450 params->p.cw_min = 0x0001;
3451 params->p.cw_max = 0x03FF;
3459 /* Initialize the core's QOS capabilities */
3460 static void b43_qos_init(struct b43_wldev *dev)
3462 if (!dev->qos_enabled) {
3463 /* Disable QOS support. */
3464 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3465 b43_write16(dev, B43_MMIO_IFSCTL,
3466 b43_read16(dev, B43_MMIO_IFSCTL)
3467 & ~B43_MMIO_IFSCTL_USE_EDCF);
3468 b43dbg(dev->wl, "QoS disabled\n");
3472 /* Upload the current QOS parameters. */
3473 b43_qos_upload_all(dev);
3475 /* Enable QOS support. */
3476 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3477 b43_write16(dev, B43_MMIO_IFSCTL,
3478 b43_read16(dev, B43_MMIO_IFSCTL)
3479 | B43_MMIO_IFSCTL_USE_EDCF);
3480 b43dbg(dev->wl, "QoS enabled\n");
3483 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3484 const struct ieee80211_tx_queue_params *params)
3486 struct b43_wl *wl = hw_to_b43_wl(hw);
3487 struct b43_wldev *dev;
3488 unsigned int queue = (unsigned int)_queue;
3491 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3492 /* Queue not available or don't support setting
3493 * params on this queue. Return success to not
3494 * confuse mac80211. */
3497 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3498 ARRAY_SIZE(wl->qos_params));
3500 mutex_lock(&wl->mutex);
3501 dev = wl->current_dev;
3502 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3505 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3506 b43_mac_suspend(dev);
3507 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3508 b43_qos_shm_offsets[queue]);
3509 b43_mac_enable(dev);
3513 mutex_unlock(&wl->mutex);
3518 static int b43_op_get_stats(struct ieee80211_hw *hw,
3519 struct ieee80211_low_level_stats *stats)
3521 struct b43_wl *wl = hw_to_b43_wl(hw);
3523 mutex_lock(&wl->mutex);
3524 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3525 mutex_unlock(&wl->mutex);
3530 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3532 struct b43_wl *wl = hw_to_b43_wl(hw);
3533 struct b43_wldev *dev;
3536 mutex_lock(&wl->mutex);
3537 dev = wl->current_dev;
3539 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3540 b43_tsf_read(dev, &tsf);
3544 mutex_unlock(&wl->mutex);
3549 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3551 struct b43_wl *wl = hw_to_b43_wl(hw);
3552 struct b43_wldev *dev;
3554 mutex_lock(&wl->mutex);
3555 dev = wl->current_dev;
3557 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3558 b43_tsf_write(dev, tsf);
3560 mutex_unlock(&wl->mutex);
3563 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3567 switch (dev->dev->bus_type) {
3568 #ifdef CONFIG_B43_BCMA
3571 "Putting PHY into reset not supported on BCMA\n");
3574 #ifdef CONFIG_B43_SSB
3576 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3577 tmp &= ~B43_TMSLOW_GMODE;
3578 tmp |= B43_TMSLOW_PHYRESET;
3579 tmp |= SSB_TMSLOW_FGC;
3580 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3583 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3584 tmp &= ~SSB_TMSLOW_FGC;
3585 tmp |= B43_TMSLOW_PHYRESET;
3586 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3594 static const char *band_to_string(enum ieee80211_band band)
3597 case IEEE80211_BAND_5GHZ:
3599 case IEEE80211_BAND_2GHZ:
3608 /* Expects wl->mutex locked */
3609 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3611 struct b43_wldev *up_dev = NULL;
3612 struct b43_wldev *down_dev;
3613 struct b43_wldev *d;
3615 bool uninitialized_var(gmode);
3618 /* Find a device and PHY which supports the band. */
3619 list_for_each_entry(d, &wl->devlist, list) {
3620 switch (chan->band) {
3621 case IEEE80211_BAND_5GHZ:
3622 if (d->phy.supports_5ghz) {
3627 case IEEE80211_BAND_2GHZ:
3628 if (d->phy.supports_2ghz) {
3641 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3642 band_to_string(chan->band));
3645 if ((up_dev == wl->current_dev) &&
3646 (!!wl->current_dev->phy.gmode == !!gmode)) {
3647 /* This device is already running. */
3650 b43dbg(wl, "Switching to %s-GHz band\n",
3651 band_to_string(chan->band));
3652 down_dev = wl->current_dev;
3654 prev_status = b43_status(down_dev);
3655 /* Shutdown the currently running core. */
3656 if (prev_status >= B43_STAT_STARTED)
3657 down_dev = b43_wireless_core_stop(down_dev);
3658 if (prev_status >= B43_STAT_INITIALIZED)
3659 b43_wireless_core_exit(down_dev);
3661 if (down_dev != up_dev) {
3662 /* We switch to a different core, so we put PHY into
3663 * RESET on the old core. */
3664 b43_put_phy_into_reset(down_dev);
3667 /* Now start the new core. */
3668 up_dev->phy.gmode = gmode;
3669 if (prev_status >= B43_STAT_INITIALIZED) {
3670 err = b43_wireless_core_init(up_dev);
3672 b43err(wl, "Fatal: Could not initialize device for "
3673 "selected %s-GHz band\n",
3674 band_to_string(chan->band));
3678 if (prev_status >= B43_STAT_STARTED) {
3679 err = b43_wireless_core_start(up_dev);
3681 b43err(wl, "Fatal: Coult not start device for "
3682 "selected %s-GHz band\n",
3683 band_to_string(chan->band));
3684 b43_wireless_core_exit(up_dev);
3688 B43_WARN_ON(b43_status(up_dev) != prev_status);
3690 wl->current_dev = up_dev;
3694 /* Whoops, failed to init the new core. No core is operating now. */
3695 wl->current_dev = NULL;
3699 /* Write the short and long frame retry limit values. */
3700 static void b43_set_retry_limits(struct b43_wldev *dev,
3701 unsigned int short_retry,
3702 unsigned int long_retry)
3704 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3705 * the chip-internal counter. */
3706 short_retry = min(short_retry, (unsigned int)0xF);
3707 long_retry = min(long_retry, (unsigned int)0xF);
3709 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3711 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3715 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3717 struct b43_wl *wl = hw_to_b43_wl(hw);
3718 struct b43_wldev *dev;
3719 struct b43_phy *phy;
3720 struct ieee80211_conf *conf = &hw->conf;
3724 mutex_lock(&wl->mutex);
3726 /* Switch the band (if necessary). This might change the active core. */
3727 err = b43_switch_band(wl, conf->channel);
3729 goto out_unlock_mutex;
3730 dev = wl->current_dev;
3733 if (conf_is_ht(conf))
3735 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3737 phy->is_40mhz = false;
3739 b43_mac_suspend(dev);
3741 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3742 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3743 conf->long_frame_max_tx_count);
3744 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3746 goto out_mac_enable;
3748 /* Switch to the requested channel.
3749 * The firmware takes care of races with the TX handler. */
3750 if (conf->channel->hw_value != phy->channel)
3751 b43_switch_channel(dev, conf->channel->hw_value);
3753 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3755 /* Adjust the desired TX power level. */
3756 if (conf->power_level != 0) {
3757 if (conf->power_level != phy->desired_txpower) {
3758 phy->desired_txpower = conf->power_level;
3759 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3760 B43_TXPWR_IGNORE_TSSI);
3764 /* Antennas for RX and management frame TX. */
3765 antenna = B43_ANTENNA_DEFAULT;
3766 b43_mgmtframe_txantenna(dev, antenna);
3767 antenna = B43_ANTENNA_DEFAULT;
3768 if (phy->ops->set_rx_antenna)
3769 phy->ops->set_rx_antenna(dev, antenna);
3771 if (wl->radio_enabled != phy->radio_on) {
3772 if (wl->radio_enabled) {
3773 b43_software_rfkill(dev, false);
3774 b43info(dev->wl, "Radio turned on by software\n");
3775 if (!dev->radio_hw_enable) {
3776 b43info(dev->wl, "The hardware RF-kill button "
3777 "still turns the radio physically off. "
3778 "Press the button to turn it on.\n");
3781 b43_software_rfkill(dev, true);
3782 b43info(dev->wl, "Radio turned off by software\n");
3787 b43_mac_enable(dev);
3789 mutex_unlock(&wl->mutex);
3794 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3796 struct ieee80211_supported_band *sband =
3797 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3798 struct ieee80211_rate *rate;
3800 u16 basic, direct, offset, basic_offset, rateptr;
3802 for (i = 0; i < sband->n_bitrates; i++) {
3803 rate = &sband->bitrates[i];
3805 if (b43_is_cck_rate(rate->hw_value)) {
3806 direct = B43_SHM_SH_CCKDIRECT;
3807 basic = B43_SHM_SH_CCKBASIC;
3808 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3811 direct = B43_SHM_SH_OFDMDIRECT;
3812 basic = B43_SHM_SH_OFDMBASIC;
3813 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3817 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3819 if (b43_is_cck_rate(rate->hw_value)) {
3820 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3821 basic_offset &= 0xF;
3823 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3824 basic_offset &= 0xF;
3828 * Get the pointer that we need to point to
3829 * from the direct map
3831 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3832 direct + 2 * basic_offset);
3833 /* and write it to the basic map */
3834 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3839 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3840 struct ieee80211_vif *vif,
3841 struct ieee80211_bss_conf *conf,
3844 struct b43_wl *wl = hw_to_b43_wl(hw);
3845 struct b43_wldev *dev;
3847 mutex_lock(&wl->mutex);
3849 dev = wl->current_dev;
3850 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3851 goto out_unlock_mutex;
3853 B43_WARN_ON(wl->vif != vif);
3855 if (changed & BSS_CHANGED_BSSID) {
3857 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3859 memset(wl->bssid, 0, ETH_ALEN);
3862 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3863 if (changed & BSS_CHANGED_BEACON &&
3864 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3865 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3866 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3867 b43_update_templates(wl);
3869 if (changed & BSS_CHANGED_BSSID)
3870 b43_write_mac_bssid_templates(dev);
3873 b43_mac_suspend(dev);
3875 /* Update templates for AP/mesh mode. */
3876 if (changed & BSS_CHANGED_BEACON_INT &&
3877 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3878 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3879 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3880 b43_set_beacon_int(dev, conf->beacon_int);
3882 if (changed & BSS_CHANGED_BASIC_RATES)
3883 b43_update_basic_rates(dev, conf->basic_rates);
3885 if (changed & BSS_CHANGED_ERP_SLOT) {
3886 if (conf->use_short_slot)
3887 b43_short_slot_timing_enable(dev);
3889 b43_short_slot_timing_disable(dev);
3892 b43_mac_enable(dev);
3894 mutex_unlock(&wl->mutex);
3897 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3898 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3899 struct ieee80211_key_conf *key)
3901 struct b43_wl *wl = hw_to_b43_wl(hw);
3902 struct b43_wldev *dev;
3906 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3908 if (modparam_nohwcrypt)
3909 return -ENOSPC; /* User disabled HW-crypto */
3911 mutex_lock(&wl->mutex);
3913 dev = wl->current_dev;
3915 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3918 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3919 /* We don't have firmware for the crypto engine.
3920 * Must use software-crypto. */
3926 switch (key->cipher) {
3927 case WLAN_CIPHER_SUITE_WEP40:
3928 algorithm = B43_SEC_ALGO_WEP40;
3930 case WLAN_CIPHER_SUITE_WEP104:
3931 algorithm = B43_SEC_ALGO_WEP104;
3933 case WLAN_CIPHER_SUITE_TKIP:
3934 algorithm = B43_SEC_ALGO_TKIP;
3936 case WLAN_CIPHER_SUITE_CCMP:
3937 algorithm = B43_SEC_ALGO_AES;
3943 index = (u8) (key->keyidx);
3949 if (algorithm == B43_SEC_ALGO_TKIP &&
3950 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3951 !modparam_hwtkip)) {
3952 /* We support only pairwise key */
3957 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3958 if (WARN_ON(!sta)) {
3962 /* Pairwise key with an assigned MAC address. */
3963 err = b43_key_write(dev, -1, algorithm,
3964 key->key, key->keylen,
3968 err = b43_key_write(dev, index, algorithm,
3969 key->key, key->keylen, NULL, key);
3974 if (algorithm == B43_SEC_ALGO_WEP40 ||
3975 algorithm == B43_SEC_ALGO_WEP104) {
3976 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3979 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3981 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3982 if (algorithm == B43_SEC_ALGO_TKIP)
3983 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3986 err = b43_key_clear(dev, key->hw_key_idx);
3997 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3999 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4000 sta ? sta->addr : bcast_addr);
4001 b43_dump_keymemory(dev);
4003 mutex_unlock(&wl->mutex);
4008 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4009 unsigned int changed, unsigned int *fflags,
4012 struct b43_wl *wl = hw_to_b43_wl(hw);
4013 struct b43_wldev *dev;
4015 mutex_lock(&wl->mutex);
4016 dev = wl->current_dev;
4022 *fflags &= FIF_PROMISC_IN_BSS |
4028 FIF_BCN_PRBRESP_PROMISC;
4030 changed &= FIF_PROMISC_IN_BSS |
4036 FIF_BCN_PRBRESP_PROMISC;
4038 wl->filter_flags = *fflags;
4040 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4041 b43_adjust_opmode(dev);
4044 mutex_unlock(&wl->mutex);
4047 /* Locking: wl->mutex
4048 * Returns the current dev. This might be different from the passed in dev,
4049 * because the core might be gone away while we unlocked the mutex. */
4050 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4052 struct b43_wl *wl = dev->wl;
4053 struct b43_wldev *orig_dev;
4057 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4060 /* Cancel work. Unlock to avoid deadlocks. */
4061 mutex_unlock(&wl->mutex);
4062 cancel_delayed_work_sync(&dev->periodic_work);
4063 cancel_work_sync(&wl->tx_work);
4064 mutex_lock(&wl->mutex);
4065 dev = wl->current_dev;
4066 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4067 /* Whoops, aliens ate up the device while we were unlocked. */
4071 /* Disable interrupts on the device. */
4072 b43_set_status(dev, B43_STAT_INITIALIZED);
4073 if (b43_bus_host_is_sdio(dev->dev)) {
4074 /* wl->mutex is locked. That is enough. */
4075 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4076 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4078 spin_lock_irq(&wl->hardirq_lock);
4079 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4080 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4081 spin_unlock_irq(&wl->hardirq_lock);
4083 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4085 mutex_unlock(&wl->mutex);
4086 if (b43_bus_host_is_sdio(dev->dev)) {
4087 b43_sdio_free_irq(dev);
4089 synchronize_irq(dev->dev->irq);
4090 free_irq(dev->dev->irq, dev);
4092 mutex_lock(&wl->mutex);
4093 dev = wl->current_dev;
4096 if (dev != orig_dev) {
4097 if (b43_status(dev) >= B43_STAT_STARTED)
4101 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4102 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4104 /* Drain the TX queue */
4105 while (skb_queue_len(&wl->tx_queue))
4106 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
4108 b43_mac_suspend(dev);
4110 b43dbg(wl, "Wireless interface stopped\n");
4115 /* Locking: wl->mutex */
4116 static int b43_wireless_core_start(struct b43_wldev *dev)
4120 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4122 drain_txstatus_queue(dev);
4123 if (b43_bus_host_is_sdio(dev->dev)) {
4124 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4126 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4130 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4131 b43_interrupt_thread_handler,
4132 IRQF_SHARED, KBUILD_MODNAME, dev);
4134 b43err(dev->wl, "Cannot request IRQ-%d\n",
4140 /* We are ready to run. */
4141 ieee80211_wake_queues(dev->wl->hw);
4142 b43_set_status(dev, B43_STAT_STARTED);
4144 /* Start data flow (TX/RX). */
4145 b43_mac_enable(dev);
4146 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4148 /* Start maintenance work */
4149 b43_periodic_tasks_setup(dev);
4153 b43dbg(dev->wl, "Wireless interface started\n");
4158 /* Get PHY and RADIO versioning numbers */
4159 static int b43_phy_versioning(struct b43_wldev *dev)
4161 struct b43_phy *phy = &dev->phy;
4169 int unsupported = 0;
4171 /* Get PHY versioning */
4172 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4173 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4174 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4175 phy_rev = (tmp & B43_PHYVER_VERSION);
4182 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4190 #ifdef CONFIG_B43_PHY_N
4196 #ifdef CONFIG_B43_PHY_LP
4197 case B43_PHYTYPE_LP:
4202 #ifdef CONFIG_B43_PHY_HT
4203 case B43_PHYTYPE_HT:
4212 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4213 "(Analog %u, Type %u, Revision %u)\n",
4214 analog_type, phy_type, phy_rev);
4217 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4218 analog_type, phy_type, phy_rev);
4220 /* Get RADIO versioning */
4221 if (dev->dev->core_rev >= 24) {
4224 for (tmp = 0; tmp < 3; tmp++) {
4225 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4226 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4229 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4230 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4232 radio_manuf = 0x17F;
4233 radio_ver = (radio24[2] << 8) | radio24[1];
4234 radio_rev = (radio24[0] & 0xF);
4236 if (dev->dev->chip_id == 0x4317) {
4237 if (dev->dev->chip_rev == 0)
4239 else if (dev->dev->chip_rev == 1)
4244 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4246 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4247 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4249 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4252 radio_manuf = (tmp & 0x00000FFF);
4253 radio_ver = (tmp & 0x0FFFF000) >> 12;
4254 radio_rev = (tmp & 0xF0000000) >> 28;
4257 if (radio_manuf != 0x17F /* Broadcom */)
4261 if (radio_ver != 0x2060)
4265 if (radio_manuf != 0x17F)
4269 if ((radio_ver & 0xFFF0) != 0x2050)
4273 if (radio_ver != 0x2050)
4277 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4280 case B43_PHYTYPE_LP:
4281 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4284 case B43_PHYTYPE_HT:
4285 if (radio_ver != 0x2059)
4292 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4293 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4294 radio_manuf, radio_ver, radio_rev);
4297 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4298 radio_manuf, radio_ver, radio_rev);
4300 phy->radio_manuf = radio_manuf;
4301 phy->radio_ver = radio_ver;
4302 phy->radio_rev = radio_rev;
4304 phy->analog = analog_type;
4305 phy->type = phy_type;
4311 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4312 struct b43_phy *phy)
4314 phy->hardware_power_control = !!modparam_hwpctl;
4315 phy->next_txpwr_check_time = jiffies;
4316 /* PHY TX errors counter. */
4317 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4320 phy->phy_locked = 0;
4321 phy->radio_locked = 0;
4325 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4329 /* Assume the radio is enabled. If it's not enabled, the state will
4330 * immediately get fixed on the first periodic work run. */
4331 dev->radio_hw_enable = 1;
4334 memset(&dev->stats, 0, sizeof(dev->stats));
4336 setup_struct_phy_for_init(dev, &dev->phy);
4338 /* IRQ related flags */
4339 dev->irq_reason = 0;
4340 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4341 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4342 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4343 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4345 dev->mac_suspended = 1;
4347 /* Noise calculation context */
4348 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4351 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4353 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4356 if (!modparam_btcoex)
4358 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4360 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4363 hf = b43_hf_read(dev);
4364 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4365 hf |= B43_HF_BTCOEXALT;
4367 hf |= B43_HF_BTCOEX;
4368 b43_hf_write(dev, hf);
4371 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4373 if (!modparam_btcoex)
4378 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4380 struct ssb_bus *bus;
4383 if (dev->dev->bus_type != B43_BUS_SSB)
4386 bus = dev->dev->sdev->bus;
4388 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4389 (bus->chip_id == 0x4312)) {
4390 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4391 tmp &= ~SSB_IMCFGLO_REQTO;
4392 tmp &= ~SSB_IMCFGLO_SERTO;
4394 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4395 ssb_commit_settings(bus);
4399 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4403 /* The time value is in microseconds. */
4404 if (dev->phy.type == B43_PHYTYPE_A)
4408 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4410 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4411 pu_delay = max(pu_delay, (u16)2400);
4413 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4416 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4417 static void b43_set_pretbtt(struct b43_wldev *dev)
4421 /* The time value is in microseconds. */
4422 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4425 if (dev->phy.type == B43_PHYTYPE_A)
4430 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4431 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4434 /* Shutdown a wireless core */
4435 /* Locking: wl->mutex */
4436 static void b43_wireless_core_exit(struct b43_wldev *dev)
4440 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4441 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4444 /* Unregister HW RNG driver */
4445 b43_rng_exit(dev->wl);
4447 b43_set_status(dev, B43_STAT_UNINIT);
4449 /* Stop the microcode PSM. */
4450 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4451 macctl &= ~B43_MACCTL_PSM_RUN;
4452 macctl |= B43_MACCTL_PSM_JMP0;
4453 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4458 dev->phy.ops->switch_analog(dev, 0);
4459 if (dev->wl->current_beacon) {
4460 dev_kfree_skb_any(dev->wl->current_beacon);
4461 dev->wl->current_beacon = NULL;
4464 b43_device_disable(dev, 0);
4465 b43_bus_may_powerdown(dev);
4468 /* Initialize a wireless core */
4469 static int b43_wireless_core_init(struct b43_wldev *dev)
4471 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4472 struct b43_phy *phy = &dev->phy;
4476 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4478 err = b43_bus_powerup(dev, 0);
4481 if (!b43_device_is_enabled(dev))
4482 b43_wireless_core_reset(dev, phy->gmode);
4484 /* Reset all data structures. */
4485 setup_struct_wldev_for_init(dev);
4486 phy->ops->prepare_structs(dev);
4488 /* Enable IRQ routing to this device. */
4489 switch (dev->dev->bus_type) {
4490 #ifdef CONFIG_B43_BCMA
4492 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4493 dev->dev->bdev, true);
4496 #ifdef CONFIG_B43_SSB
4498 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4504 b43_imcfglo_timeouts_workaround(dev);
4505 b43_bluetooth_coext_disable(dev);
4506 if (phy->ops->prepare_hardware) {
4507 err = phy->ops->prepare_hardware(dev);
4511 err = b43_chip_init(dev);
4514 b43_shm_write16(dev, B43_SHM_SHARED,
4515 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4516 hf = b43_hf_read(dev);
4517 if (phy->type == B43_PHYTYPE_G) {
4521 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4522 hf |= B43_HF_OFDMPABOOST;
4524 if (phy->radio_ver == 0x2050) {
4525 if (phy->radio_rev == 6)
4526 hf |= B43_HF_4318TSSI;
4527 if (phy->radio_rev < 6)
4528 hf |= B43_HF_VCORECALC;
4530 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4531 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4532 #ifdef CONFIG_SSB_DRIVER_PCICORE
4533 if (dev->dev->bus_type == B43_BUS_SSB &&
4534 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4535 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4536 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4538 hf &= ~B43_HF_SKCFPUP;
4539 b43_hf_write(dev, hf);
4541 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4542 B43_DEFAULT_LONG_RETRY_LIMIT);
4543 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4544 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4546 /* Disable sending probe responses from firmware.
4547 * Setting the MaxTime to one usec will always trigger
4548 * a timeout, so we never send any probe resp.
4549 * A timeout of zero is infinite. */
4550 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4552 b43_rate_memory_init(dev);
4553 b43_set_phytxctl_defaults(dev);
4555 /* Minimum Contention Window */
4556 if (phy->type == B43_PHYTYPE_B)
4557 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4559 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4560 /* Maximum Contention Window */
4561 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4563 if (b43_bus_host_is_pcmcia(dev->dev) ||
4564 b43_bus_host_is_sdio(dev->dev) ||
4566 dev->__using_pio_transfers = 1;
4567 err = b43_pio_init(dev);
4569 dev->__using_pio_transfers = 0;
4570 err = b43_dma_init(dev);
4575 b43_set_synth_pu_delay(dev, 1);
4576 b43_bluetooth_coext_enable(dev);
4578 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4579 b43_upload_card_macaddress(dev);
4580 b43_security_init(dev);
4582 ieee80211_wake_queues(dev->wl->hw);
4584 b43_set_status(dev, B43_STAT_INITIALIZED);
4586 /* Register HW RNG driver */
4587 b43_rng_init(dev->wl);
4595 b43_bus_may_powerdown(dev);
4596 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4600 static int b43_op_add_interface(struct ieee80211_hw *hw,
4601 struct ieee80211_vif *vif)
4603 struct b43_wl *wl = hw_to_b43_wl(hw);
4604 struct b43_wldev *dev;
4605 int err = -EOPNOTSUPP;
4607 /* TODO: allow WDS/AP devices to coexist */
4609 if (vif->type != NL80211_IFTYPE_AP &&
4610 vif->type != NL80211_IFTYPE_MESH_POINT &&
4611 vif->type != NL80211_IFTYPE_STATION &&
4612 vif->type != NL80211_IFTYPE_WDS &&
4613 vif->type != NL80211_IFTYPE_ADHOC)
4616 mutex_lock(&wl->mutex);
4618 goto out_mutex_unlock;
4620 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4622 dev = wl->current_dev;
4625 wl->if_type = vif->type;
4626 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4628 b43_adjust_opmode(dev);
4629 b43_set_pretbtt(dev);
4630 b43_set_synth_pu_delay(dev, 0);
4631 b43_upload_card_macaddress(dev);
4635 mutex_unlock(&wl->mutex);
4640 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4641 struct ieee80211_vif *vif)
4643 struct b43_wl *wl = hw_to_b43_wl(hw);
4644 struct b43_wldev *dev = wl->current_dev;
4646 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4648 mutex_lock(&wl->mutex);
4650 B43_WARN_ON(!wl->operating);
4651 B43_WARN_ON(wl->vif != vif);
4656 b43_adjust_opmode(dev);
4657 memset(wl->mac_addr, 0, ETH_ALEN);
4658 b43_upload_card_macaddress(dev);
4660 mutex_unlock(&wl->mutex);
4663 static int b43_op_start(struct ieee80211_hw *hw)
4665 struct b43_wl *wl = hw_to_b43_wl(hw);
4666 struct b43_wldev *dev = wl->current_dev;
4670 /* Kill all old instance specific information to make sure
4671 * the card won't use it in the short timeframe between start
4672 * and mac80211 reconfiguring it. */
4673 memset(wl->bssid, 0, ETH_ALEN);
4674 memset(wl->mac_addr, 0, ETH_ALEN);
4675 wl->filter_flags = 0;
4676 wl->radiotap_enabled = 0;
4678 wl->beacon0_uploaded = 0;
4679 wl->beacon1_uploaded = 0;
4680 wl->beacon_templates_virgin = 1;
4681 wl->radio_enabled = 1;
4683 mutex_lock(&wl->mutex);
4685 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4686 err = b43_wireless_core_init(dev);
4688 goto out_mutex_unlock;
4692 if (b43_status(dev) < B43_STAT_STARTED) {
4693 err = b43_wireless_core_start(dev);
4696 b43_wireless_core_exit(dev);
4697 goto out_mutex_unlock;
4701 /* XXX: only do if device doesn't support rfkill irq */
4702 wiphy_rfkill_start_polling(hw->wiphy);
4705 mutex_unlock(&wl->mutex);
4710 static void b43_op_stop(struct ieee80211_hw *hw)
4712 struct b43_wl *wl = hw_to_b43_wl(hw);
4713 struct b43_wldev *dev = wl->current_dev;
4715 cancel_work_sync(&(wl->beacon_update_trigger));
4717 mutex_lock(&wl->mutex);
4718 if (b43_status(dev) >= B43_STAT_STARTED) {
4719 dev = b43_wireless_core_stop(dev);
4723 b43_wireless_core_exit(dev);
4724 wl->radio_enabled = 0;
4727 mutex_unlock(&wl->mutex);
4729 cancel_work_sync(&(wl->txpower_adjust_work));
4732 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4733 struct ieee80211_sta *sta, bool set)
4735 struct b43_wl *wl = hw_to_b43_wl(hw);
4737 /* FIXME: add locking */
4738 b43_update_templates(wl);
4743 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4744 struct ieee80211_vif *vif,
4745 enum sta_notify_cmd notify_cmd,
4746 struct ieee80211_sta *sta)
4748 struct b43_wl *wl = hw_to_b43_wl(hw);
4750 B43_WARN_ON(!vif || wl->vif != vif);
4753 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4755 struct b43_wl *wl = hw_to_b43_wl(hw);
4756 struct b43_wldev *dev;
4758 mutex_lock(&wl->mutex);
4759 dev = wl->current_dev;
4760 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4761 /* Disable CFP update during scan on other channels. */
4762 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4764 mutex_unlock(&wl->mutex);
4767 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4769 struct b43_wl *wl = hw_to_b43_wl(hw);
4770 struct b43_wldev *dev;
4772 mutex_lock(&wl->mutex);
4773 dev = wl->current_dev;
4774 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4775 /* Re-enable CFP update. */
4776 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4778 mutex_unlock(&wl->mutex);
4781 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4782 struct survey_info *survey)
4784 struct b43_wl *wl = hw_to_b43_wl(hw);
4785 struct b43_wldev *dev = wl->current_dev;
4786 struct ieee80211_conf *conf = &hw->conf;
4791 survey->channel = conf->channel;
4792 survey->filled = SURVEY_INFO_NOISE_DBM;
4793 survey->noise = dev->stats.link_noise;
4798 static const struct ieee80211_ops b43_hw_ops = {
4800 .conf_tx = b43_op_conf_tx,
4801 .add_interface = b43_op_add_interface,
4802 .remove_interface = b43_op_remove_interface,
4803 .config = b43_op_config,
4804 .bss_info_changed = b43_op_bss_info_changed,
4805 .configure_filter = b43_op_configure_filter,
4806 .set_key = b43_op_set_key,
4807 .update_tkip_key = b43_op_update_tkip_key,
4808 .get_stats = b43_op_get_stats,
4809 .get_tsf = b43_op_get_tsf,
4810 .set_tsf = b43_op_set_tsf,
4811 .start = b43_op_start,
4812 .stop = b43_op_stop,
4813 .set_tim = b43_op_beacon_set_tim,
4814 .sta_notify = b43_op_sta_notify,
4815 .sw_scan_start = b43_op_sw_scan_start_notifier,
4816 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4817 .get_survey = b43_op_get_survey,
4818 .rfkill_poll = b43_rfkill_poll,
4821 /* Hard-reset the chip. Do not call this directly.
4822 * Use b43_controller_restart()
4824 static void b43_chip_reset(struct work_struct *work)
4826 struct b43_wldev *dev =
4827 container_of(work, struct b43_wldev, restart_work);
4828 struct b43_wl *wl = dev->wl;
4832 mutex_lock(&wl->mutex);
4834 prev_status = b43_status(dev);
4835 /* Bring the device down... */
4836 if (prev_status >= B43_STAT_STARTED) {
4837 dev = b43_wireless_core_stop(dev);
4843 if (prev_status >= B43_STAT_INITIALIZED)
4844 b43_wireless_core_exit(dev);
4846 /* ...and up again. */
4847 if (prev_status >= B43_STAT_INITIALIZED) {
4848 err = b43_wireless_core_init(dev);
4852 if (prev_status >= B43_STAT_STARTED) {
4853 err = b43_wireless_core_start(dev);
4855 b43_wireless_core_exit(dev);
4861 wl->current_dev = NULL; /* Failed to init the dev. */
4862 mutex_unlock(&wl->mutex);
4864 b43err(wl, "Controller restart FAILED\n");
4866 b43info(wl, "Controller restarted\n");
4869 static int b43_setup_bands(struct b43_wldev *dev,
4870 bool have_2ghz_phy, bool have_5ghz_phy)
4872 struct ieee80211_hw *hw = dev->wl->hw;
4875 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4876 if (dev->phy.type == B43_PHYTYPE_N) {
4878 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4881 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4884 dev->phy.supports_2ghz = have_2ghz_phy;
4885 dev->phy.supports_5ghz = have_5ghz_phy;
4890 static void b43_wireless_core_detach(struct b43_wldev *dev)
4892 /* We release firmware that late to not be required to re-request
4893 * is all the time when we reinit the core. */
4894 b43_release_firmware(dev);
4898 static int b43_wireless_core_attach(struct b43_wldev *dev)
4900 struct b43_wl *wl = dev->wl;
4901 struct pci_dev *pdev = NULL;
4903 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4905 /* Do NOT do any device initialization here.
4906 * Do it in wireless_core_init() instead.
4907 * This function is for gathering basic information about the HW, only.
4908 * Also some structs may be set up here. But most likely you want to have
4909 * that in core_init(), too.
4912 #ifdef CONFIG_B43_SSB
4913 if (dev->dev->bus_type == B43_BUS_SSB &&
4914 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
4915 pdev = dev->dev->sdev->bus->host_pci;
4918 err = b43_bus_powerup(dev, 0);
4920 b43err(wl, "Bus powerup failed\n");
4924 /* Get the PHY type. */
4925 switch (dev->dev->bus_type) {
4926 #ifdef CONFIG_B43_BCMA
4933 #ifdef CONFIG_B43_SSB
4935 if (dev->dev->core_rev >= 5) {
4936 u32 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
4937 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4938 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4945 dev->phy.gmode = have_2ghz_phy;
4946 dev->phy.radio_on = 1;
4947 b43_wireless_core_reset(dev, dev->phy.gmode);
4949 err = b43_phy_versioning(dev);
4952 /* Check if this device supports multiband. */
4954 (pdev->device != 0x4312 &&
4955 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4956 /* No multiband support. */
4959 switch (dev->phy.type) {
4963 case B43_PHYTYPE_LP: //FIXME not always!
4964 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
4975 if (dev->phy.type == B43_PHYTYPE_A) {
4977 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4981 if (1 /* disable A-PHY */) {
4982 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4983 if (dev->phy.type != B43_PHYTYPE_N &&
4984 dev->phy.type != B43_PHYTYPE_LP) {
4990 err = b43_phy_allocate(dev);
4994 dev->phy.gmode = have_2ghz_phy;
4995 b43_wireless_core_reset(dev, dev->phy.gmode);
4997 err = b43_validate_chipaccess(dev);
5000 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5004 /* Now set some default "current_dev" */
5005 if (!wl->current_dev)
5006 wl->current_dev = dev;
5007 INIT_WORK(&dev->restart_work, b43_chip_reset);
5009 dev->phy.ops->switch_analog(dev, 0);
5010 b43_device_disable(dev, 0);
5011 b43_bus_may_powerdown(dev);
5019 b43_bus_may_powerdown(dev);
5023 static void b43_one_core_detach(struct b43_bus_dev *dev)
5025 struct b43_wldev *wldev;
5028 /* Do not cancel ieee80211-workqueue based work here.
5029 * See comment in b43_remove(). */
5031 wldev = b43_bus_get_wldev(dev);
5033 b43_debugfs_remove_device(wldev);
5034 b43_wireless_core_detach(wldev);
5035 list_del(&wldev->list);
5037 b43_bus_set_wldev(dev, NULL);
5041 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5043 struct b43_wldev *wldev;
5046 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5050 wldev->use_pio = b43_modparam_pio;
5053 b43_set_status(wldev, B43_STAT_UNINIT);
5054 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5055 INIT_LIST_HEAD(&wldev->list);
5057 err = b43_wireless_core_attach(wldev);
5059 goto err_kfree_wldev;
5061 list_add(&wldev->list, &wl->devlist);
5063 b43_bus_set_wldev(dev, wldev);
5064 b43_debugfs_add_device(wldev);
5074 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5075 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5076 (pdev->device == _device) && \
5077 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5078 (pdev->subsystem_device == _subdevice) )
5080 static void b43_sprom_fixup(struct ssb_bus *bus)
5082 struct pci_dev *pdev;
5084 /* boardflags workarounds */
5085 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5086 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
5087 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5088 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5089 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
5090 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5091 if (bus->bustype == SSB_BUSTYPE_PCI) {
5092 pdev = bus->host_pci;
5093 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5094 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5095 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5096 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5097 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5098 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5099 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5100 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5104 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5106 struct ieee80211_hw *hw = wl->hw;
5108 ssb_set_devtypedata(dev->sdev, NULL);
5109 ieee80211_free_hw(hw);
5112 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5114 struct ssb_sprom *sprom = dev->bus_sprom;
5115 struct ieee80211_hw *hw;
5118 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5120 b43err(NULL, "Could not allocate ieee80211 device\n");
5121 return ERR_PTR(-ENOMEM);
5123 wl = hw_to_b43_wl(hw);
5126 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5127 IEEE80211_HW_SIGNAL_DBM;
5129 hw->wiphy->interface_modes =
5130 BIT(NL80211_IFTYPE_AP) |
5131 BIT(NL80211_IFTYPE_MESH_POINT) |
5132 BIT(NL80211_IFTYPE_STATION) |
5133 BIT(NL80211_IFTYPE_WDS) |
5134 BIT(NL80211_IFTYPE_ADHOC);
5136 hw->queues = modparam_qos ? 4 : 1;
5137 wl->mac80211_initially_registered_queues = hw->queues;
5139 SET_IEEE80211_DEV(hw, dev->dev);
5140 if (is_valid_ether_addr(sprom->et1mac))
5141 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5143 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5145 /* Initialize struct b43_wl */
5147 mutex_init(&wl->mutex);
5148 spin_lock_init(&wl->hardirq_lock);
5149 INIT_LIST_HEAD(&wl->devlist);
5150 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5151 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5152 INIT_WORK(&wl->tx_work, b43_tx_work);
5153 skb_queue_head_init(&wl->tx_queue);
5155 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
5156 dev->chip_id, dev->core_rev);
5160 #ifdef CONFIG_B43_BCMA
5161 static int b43_bcma_probe(struct bcma_device *core)
5163 struct b43_bus_dev *dev;
5165 dev = b43_bus_dev_bcma_init(core);
5169 b43err(NULL, "BCMA is not supported yet!");
5174 static void b43_bcma_remove(struct bcma_device *core)
5179 static struct bcma_driver b43_bcma_driver = {
5180 .name = KBUILD_MODNAME,
5181 .id_table = b43_bcma_tbl,
5182 .probe = b43_bcma_probe,
5183 .remove = b43_bcma_remove,
5187 #ifdef CONFIG_B43_SSB
5189 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5191 struct b43_bus_dev *dev;
5196 dev = b43_bus_dev_ssb_init(sdev);
5200 wl = ssb_get_devtypedata(sdev);
5202 /* Probing the first core. Must setup common struct b43_wl */
5204 b43_sprom_fixup(sdev->bus);
5205 wl = b43_wireless_init(dev);
5210 ssb_set_devtypedata(sdev, wl);
5211 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5213 err = b43_one_core_attach(dev, wl);
5215 goto err_wireless_exit;
5218 err = ieee80211_register_hw(wl->hw);
5220 goto err_one_core_detach;
5221 b43_leds_register(wl->current_dev);
5227 err_one_core_detach:
5228 b43_one_core_detach(dev);
5231 b43_wireless_exit(dev, wl);
5235 static void b43_ssb_remove(struct ssb_device *sdev)
5237 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5238 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5240 /* We must cancel any work here before unregistering from ieee80211,
5241 * as the ieee80211 unreg will destroy the workqueue. */
5242 cancel_work_sync(&wldev->restart_work);
5245 if (wl->current_dev == wldev) {
5246 /* Restore the queues count before unregistering, because firmware detect
5247 * might have modified it. Restoring is important, so the networking
5248 * stack can properly free resources. */
5249 wl->hw->queues = wl->mac80211_initially_registered_queues;
5250 b43_leds_stop(wldev);
5251 ieee80211_unregister_hw(wl->hw);
5254 b43_one_core_detach(wldev->dev);
5256 if (list_empty(&wl->devlist)) {
5257 b43_leds_unregister(wl);
5258 /* Last core on the chip unregistered.
5259 * We can destroy common struct b43_wl.
5261 b43_wireless_exit(wldev->dev, wl);
5265 static struct ssb_driver b43_ssb_driver = {
5266 .name = KBUILD_MODNAME,
5267 .id_table = b43_ssb_tbl,
5268 .probe = b43_ssb_probe,
5269 .remove = b43_ssb_remove,
5271 #endif /* CONFIG_B43_SSB */
5273 /* Perform a hardware reset. This can be called from any context. */
5274 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5276 /* Must avoid requeueing, if we are in shutdown. */
5277 if (b43_status(dev) < B43_STAT_INITIALIZED)
5279 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5280 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5283 static void b43_print_driverinfo(void)
5285 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5286 *feat_leds = "", *feat_sdio = "";
5288 #ifdef CONFIG_B43_PCI_AUTOSELECT
5291 #ifdef CONFIG_B43_PCMCIA
5294 #ifdef CONFIG_B43_PHY_N
5297 #ifdef CONFIG_B43_LEDS
5300 #ifdef CONFIG_B43_SDIO
5303 printk(KERN_INFO "Broadcom 43xx driver loaded "
5304 "[ Features: %s%s%s%s%s, Firmware-ID: "
5305 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5306 feat_pci, feat_pcmcia, feat_nphy,
5307 feat_leds, feat_sdio);
5310 static int __init b43_init(void)
5315 err = b43_pcmcia_init();
5318 err = b43_sdio_init();
5320 goto err_pcmcia_exit;
5321 #ifdef CONFIG_B43_BCMA
5322 err = bcma_driver_register(&b43_bcma_driver);
5326 #ifdef CONFIG_B43_SSB
5327 err = ssb_driver_register(&b43_ssb_driver);
5329 goto err_bcma_driver_exit;
5331 b43_print_driverinfo();
5335 #ifdef CONFIG_B43_SSB
5336 err_bcma_driver_exit:
5338 #ifdef CONFIG_B43_BCMA
5339 bcma_driver_unregister(&b43_bcma_driver);
5350 static void __exit b43_exit(void)
5352 #ifdef CONFIG_B43_SSB
5353 ssb_driver_unregister(&b43_ssb_driver);
5355 #ifdef CONFIG_B43_BCMA
5356 bcma_driver_unregister(&b43_bcma_driver);
5363 module_init(b43_init)
5364 module_exit(b43_exit)