drivers/net/wireless/b43/main.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "sysfs.h"
  50 #include "xmit.h"
  51 #include "lo.h"
  52 #include "pcmcia.h"
  53
  54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  55 MODULE_AUTHOR("Martin Langer");
  56 MODULE_AUTHOR("Stefano Brivio");
  57 MODULE_AUTHOR("Michael Buesch");
  58 MODULE_LICENSE("GPL");
  59
  60
  61 static int modparam_bad_frames_preempt;
  62 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  63 MODULE_PARM_DESC(bad_frames_preempt,
  64                  "enable(1) / disable(0) Bad Frames Preemption");
  65
  66 static char modparam_fwpostfix[16];
  67 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  68 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  69
  70 static int modparam_hwpctl;
  71 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  72 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  73
  74 static int modparam_nohwcrypt;
  75 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  77
  78 static const struct ssb_device_id b43_ssb_tbl[] = {
  79         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  80         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  81         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  82         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  83         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  84         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
  85         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  86         SSB_DEVTABLE_END
  87 };
  88
  89 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
  90
  91 /* Channel and ratetables are shared for all devices.
  92  * They can't be const, because ieee80211 puts some precalculated
  93  * data in there. This data is the same for all devices, so we don't
  94  * get concurrency issues */
  95 #define RATETAB_ENT(_rateid, _flags) \
  96         {                                                       \
  97                 .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
  98                 .val    = (_rateid),                            \
  99                 .val2   = (_rateid),                            \
 100                 .flags  = (_flags),                             \
 101         }
 102 static struct ieee80211_rate __b43_ratetable[] = {
 103         RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
 104         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
 105         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
 106         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
 107         RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
 108         RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
 109         RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
 110         RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
 111         RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
 112         RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
 113         RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
 114         RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
 115 };
 116
 117 #define b43_a_ratetable         (__b43_ratetable + 4)
 118 #define b43_a_ratetable_size    8
 119 #define b43_b_ratetable         (__b43_ratetable + 0)
 120 #define b43_b_ratetable_size    4
 121 #define b43_g_ratetable         (__b43_ratetable + 0)
 122 #define b43_g_ratetable_size    12
 123
 124 #define CHANTAB_ENT(_chanid, _freq) \
 125         {                                                       \
 126                 .chan   = (_chanid),                            \
 127                 .freq   = (_freq),                              \
 128                 .val    = (_chanid),                            \
 129                 .flag   = IEEE80211_CHAN_W_SCAN |               \
 130                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
 131                           IEEE80211_CHAN_W_IBSS,                \
 132                 .power_level    = 0xFF,                         \
 133                 .antenna_max    = 0xFF,                         \
 134         }
 135 static struct ieee80211_channel b43_2ghz_chantable[] = {
 136         CHANTAB_ENT(1, 2412),
 137         CHANTAB_ENT(2, 2417),
 138         CHANTAB_ENT(3, 2422),
 139         CHANTAB_ENT(4, 2427),
 140         CHANTAB_ENT(5, 2432),
 141         CHANTAB_ENT(6, 2437),
 142         CHANTAB_ENT(7, 2442),
 143         CHANTAB_ENT(8, 2447),
 144         CHANTAB_ENT(9, 2452),
 145         CHANTAB_ENT(10, 2457),
 146         CHANTAB_ENT(11, 2462),
 147         CHANTAB_ENT(12, 2467),
 148         CHANTAB_ENT(13, 2472),
 149         CHANTAB_ENT(14, 2484),
 150 };
 151 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
 152
 153 #if 0
 154 static struct ieee80211_channel b43_5ghz_chantable[] = {
 155         CHANTAB_ENT(36, 5180),
 156         CHANTAB_ENT(40, 5200),
 157         CHANTAB_ENT(44, 5220),
 158         CHANTAB_ENT(48, 5240),
 159         CHANTAB_ENT(52, 5260),
 160         CHANTAB_ENT(56, 5280),
 161         CHANTAB_ENT(60, 5300),
 162         CHANTAB_ENT(64, 5320),
 163         CHANTAB_ENT(149, 5745),
 164         CHANTAB_ENT(153, 5765),
 165         CHANTAB_ENT(157, 5785),
 166         CHANTAB_ENT(161, 5805),
 167         CHANTAB_ENT(165, 5825),
 168 };
 169 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
 170 #endif
 171
 172 static void b43_wireless_core_exit(struct b43_wldev *dev);
 173 static int b43_wireless_core_init(struct b43_wldev *dev);
 174 static void b43_wireless_core_stop(struct b43_wldev *dev);
 175 static int b43_wireless_core_start(struct b43_wldev *dev);
 176
 177 static int b43_ratelimit(struct b43_wl *wl)
 178 {
 179         if (!wl || !wl->current_dev)
 180                 return 1;
 181         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 182                 return 1;
 183         /* We are up and running.
 184          * Ratelimit the messages to avoid DoS over the net. */
 185         return net_ratelimit();
 186 }
 187
 188 void b43info(struct b43_wl *wl, const char *fmt, ...)
 189 {
 190         va_list args;
 191
 192         if (!b43_ratelimit(wl))
 193                 return;
 194         va_start(args, fmt);
 195         printk(KERN_INFO "b43-%s: ",
 196                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 197         vprintk(fmt, args);
 198         va_end(args);
 199 }
 200
 201 void b43err(struct b43_wl *wl, const char *fmt, ...)
 202 {
 203         va_list args;
 204
 205         if (!b43_ratelimit(wl))
 206                 return;
 207         va_start(args, fmt);
 208         printk(KERN_ERR "b43-%s ERROR: ",
 209                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 210         vprintk(fmt, args);
 211         va_end(args);
 212 }
 213
 214 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 215 {
 216         va_list args;
 217
 218         if (!b43_ratelimit(wl))
 219                 return;
 220         va_start(args, fmt);
 221         printk(KERN_WARNING "b43-%s warning: ",
 222                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 223         vprintk(fmt, args);
 224         va_end(args);
 225 }
 226
 227 #if B43_DEBUG
 228 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 229 {
 230         va_list args;
 231
 232         va_start(args, fmt);
 233         printk(KERN_DEBUG "b43-%s debug: ",
 234                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 235         vprintk(fmt, args);
 236         va_end(args);
 237 }
 238 #endif /* DEBUG */
 239
 240 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 241 {
 242         u32 macctl;
 243
 244         B43_WARN_ON(offset % 4 != 0);
 245
 246         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 247         if (macctl & B43_MACCTL_BE)
 248                 val = swab32(val);
 249
 250         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 251         mmiowb();
 252         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 253 }
 254
 255 static inline void b43_shm_control_word(struct b43_wldev *dev,
 256                                         u16 routing, u16 offset)
 257 {
 258         u32 control;
 259
 260         /* "offset" is the WORD offset. */
 261         control = routing;
 262         control <<= 16;
 263         control |= offset;
 264         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 265 }
 266
 267 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 268 {
 269         struct b43_wl *wl = dev->wl;
 270         unsigned long flags;
 271         u32 ret;
 272
 273         spin_lock_irqsave(&wl->shm_lock, flags);
 274         if (routing == B43_SHM_SHARED) {
 275                 B43_WARN_ON(offset & 0x0001);
 276                 if (offset & 0x0003) {
 277                         /* Unaligned access */
 278                         b43_shm_control_word(dev, routing, offset >> 2);
 279                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 280                         ret <<= 16;
 281                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 282                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 283
 284                         goto out;
 285                 }
 286                 offset >>= 2;
 287         }
 288         b43_shm_control_word(dev, routing, offset);
 289         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 290 out:
 291         spin_unlock_irqrestore(&wl->shm_lock, flags);
 292
 293         return ret;
 294 }
 295
 296 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 297 {
 298         struct b43_wl *wl = dev->wl;
 299         unsigned long flags;
 300         u16 ret;
 301
 302         spin_lock_irqsave(&wl->shm_lock, flags);
 303         if (routing == B43_SHM_SHARED) {
 304                 B43_WARN_ON(offset & 0x0001);
 305                 if (offset & 0x0003) {
 306                         /* Unaligned access */
 307                         b43_shm_control_word(dev, routing, offset >> 2);
 308                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 309
 310                         goto out;
 311                 }
 312                 offset >>= 2;
 313         }
 314         b43_shm_control_word(dev, routing, offset);
 315         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 316 out:
 317         spin_unlock_irqrestore(&wl->shm_lock, flags);
 318
 319         return ret;
 320 }
 321
 322 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 323 {
 324         struct b43_wl *wl = dev->wl;
 325         unsigned long flags;
 326
 327         spin_lock_irqsave(&wl->shm_lock, flags);
 328         if (routing == B43_SHM_SHARED) {
 329                 B43_WARN_ON(offset & 0x0001);
 330                 if (offset & 0x0003) {
 331                         /* Unaligned access */
 332                         b43_shm_control_word(dev, routing, offset >> 2);
 333                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 334                                     (value >> 16) & 0xffff);
 335                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 336                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 337                         goto out;
 338                 }
 339                 offset >>= 2;
 340         }
 341         b43_shm_control_word(dev, routing, offset);
 342         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 343 out:
 344         spin_unlock_irqrestore(&wl->shm_lock, flags);
 345 }
 346
 347 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 348 {
 349         struct b43_wl *wl = dev->wl;
 350         unsigned long flags;
 351
 352         spin_lock_irqsave(&wl->shm_lock, flags);
 353         if (routing == B43_SHM_SHARED) {
 354                 B43_WARN_ON(offset & 0x0001);
 355                 if (offset & 0x0003) {
 356                         /* Unaligned access */
 357                         b43_shm_control_word(dev, routing, offset >> 2);
 358                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 359                         goto out;
 360                 }
 361                 offset >>= 2;
 362         }
 363         b43_shm_control_word(dev, routing, offset);
 364         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 365 out:
 366         spin_unlock_irqrestore(&wl->shm_lock, flags);
 367 }
 368
 369 /* Read HostFlags */
 370 u32 b43_hf_read(struct b43_wldev * dev)
 371 {
 372         u32 ret;
 373
 374         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 375         ret <<= 16;
 376         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 377
 378         return ret;
 379 }
 380
 381 /* Write HostFlags */
 382 void b43_hf_write(struct b43_wldev *dev, u32 value)
 383 {
 384         b43_shm_write16(dev, B43_SHM_SHARED,
 385                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 386         b43_shm_write16(dev, B43_SHM_SHARED,
 387                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 388 }
 389
 390 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 391 {
 392         /* We need to be careful. As we read the TSF from multiple
 393          * registers, we should take care of register overflows.
 394          * In theory, the whole tsf read process should be atomic.
 395          * We try to be atomic here, by restaring the read process,
 396          * if any of the high registers changed (overflew).
 397          */
 398         if (dev->dev->id.revision >= 3) {
 399                 u32 low, high, high2;
 400
 401                 do {
 402                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 403                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 404                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 405                 } while (unlikely(high != high2));
 406
 407                 *tsf = high;
 408                 *tsf <<= 32;
 409                 *tsf |= low;
 410         } else {
 411                 u64 tmp;
 412                 u16 v0, v1, v2, v3;
 413                 u16 test1, test2, test3;
 414
 415                 do {
 416                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 417                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 418                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 419                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 420
 421                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 422                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 423                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 424                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 425
 426                 *tsf = v3;
 427                 *tsf <<= 48;
 428                 tmp = v2;
 429                 tmp <<= 32;
 430                 *tsf |= tmp;
 431                 tmp = v1;
 432                 tmp <<= 16;
 433                 *tsf |= tmp;
 434                 *tsf |= v0;
 435         }
 436 }
 437
 438 static void b43_time_lock(struct b43_wldev *dev)
 439 {
 440         u32 macctl;
 441
 442         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 443         macctl |= B43_MACCTL_TBTTHOLD;
 444         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 445         /* Commit the write */
 446         b43_read32(dev, B43_MMIO_MACCTL);
 447 }
 448
 449 static void b43_time_unlock(struct b43_wldev *dev)
 450 {
 451         u32 macctl;
 452
 453         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 454         macctl &= ~B43_MACCTL_TBTTHOLD;
 455         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 456         /* Commit the write */
 457         b43_read32(dev, B43_MMIO_MACCTL);
 458 }
 459
 460 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 461 {
 462         /* Be careful with the in-progress timer.
 463          * First zero out the low register, so we have a full
 464          * register-overflow duration to complete the operation.
 465          */
 466         if (dev->dev->id.revision >= 3) {
 467                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 468                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 469
 470                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 471                 mmiowb();
 472                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 473                 mmiowb();
 474                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 475         } else {
 476                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 477                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 478                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 479                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 480
 481                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 482                 mmiowb();
 483                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 484                 mmiowb();
 485                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 486                 mmiowb();
 487                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 488                 mmiowb();
 489                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 490         }
 491 }
 492
 493 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 494 {
 495         b43_time_lock(dev);
 496         b43_tsf_write_locked(dev, tsf);
 497         b43_time_unlock(dev);
 498 }
 499
 500 static
 501 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 502 {
 503         static const u8 zero_addr[ETH_ALEN] = { 0 };
 504         u16 data;
 505
 506         if (!mac)
 507                 mac = zero_addr;
 508
 509         offset |= 0x0020;
 510         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 511
 512         data = mac[0];
 513         data |= mac[1] << 8;
 514         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 515         data = mac[2];
 516         data |= mac[3] << 8;
 517         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 518         data = mac[4];
 519         data |= mac[5] << 8;
 520         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 521 }
 522
 523 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 524 {
 525         const u8 *mac;
 526         const u8 *bssid;
 527         u8 mac_bssid[ETH_ALEN * 2];
 528         int i;
 529         u32 tmp;
 530
 531         bssid = dev->wl->bssid;
 532         mac = dev->wl->mac_addr;
 533
 534         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 535
 536         memcpy(mac_bssid, mac, ETH_ALEN);
 537         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 538
 539         /* Write our MAC address and BSSID to template ram */
 540         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 541                 tmp = (u32) (mac_bssid[i + 0]);
 542                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 543                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 544                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 545                 b43_ram_write(dev, 0x20 + i, tmp);
 546         }
 547 }
 548
 549 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 550 {
 551         b43_write_mac_bssid_templates(dev);
 552         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 553 }
 554
 555 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 556 {
 557         /* slot_time is in usec. */
 558         if (dev->phy.type != B43_PHYTYPE_G)
 559                 return;
 560         b43_write16(dev, 0x684, 510 + slot_time);
 561         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 562 }
 563
 564 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 565 {
 566         b43_set_slot_time(dev, 9);
 567         dev->short_slot = 1;
 568 }
 569
 570 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 571 {
 572         b43_set_slot_time(dev, 20);
 573         dev->short_slot = 0;
 574 }
 575
 576 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 577  * Returns the _previously_ enabled IRQ mask.
 578  */
 579 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 580 {
 581         u32 old_mask;
 582
 583         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 584         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 585
 586         return old_mask;
 587 }
 588
 589 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 590  * Returns the _previously_ enabled IRQ mask.
 591  */
 592 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 593 {
 594         u32 old_mask;
 595
 596         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 597         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 598
 599         return old_mask;
 600 }
 601
 602 /* Synchronize IRQ top- and bottom-half.
 603  * IRQs must be masked before calling this.
 604  * This must not be called with the irq_lock held.
 605  */
 606 static void b43_synchronize_irq(struct b43_wldev *dev)
 607 {
 608         synchronize_irq(dev->dev->irq);
 609         tasklet_kill(&dev->isr_tasklet);
 610 }
 611
 612 /* DummyTransmission function, as documented on
 613  * http://bcm-specs.sipsolutions.net/DummyTransmission
 614  */
 615 void b43_dummy_transmission(struct b43_wldev *dev)
 616 {
 617         struct b43_phy *phy = &dev->phy;
 618         unsigned int i, max_loop;
 619         u16 value;
 620         u32 buffer[5] = {
 621                 0x00000000,
 622                 0x00D40000,
 623                 0x00000000,
 624                 0x01000000,
 625                 0x00000000,
 626         };
 627
 628         switch (phy->type) {
 629         case B43_PHYTYPE_A:
 630                 max_loop = 0x1E;
 631                 buffer[0] = 0x000201CC;
 632                 break;
 633         case B43_PHYTYPE_B:
 634         case B43_PHYTYPE_G:
 635                 max_loop = 0xFA;
 636                 buffer[0] = 0x000B846E;
 637                 break;
 638         default:
 639                 B43_WARN_ON(1);
 640                 return;
 641         }
 642
 643         for (i = 0; i < 5; i++)
 644                 b43_ram_write(dev, i * 4, buffer[i]);
 645
 646         /* Commit writes */
 647         b43_read32(dev, B43_MMIO_MACCTL);
 648
 649         b43_write16(dev, 0x0568, 0x0000);
 650         b43_write16(dev, 0x07C0, 0x0000);
 651         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 652         b43_write16(dev, 0x050C, value);
 653         b43_write16(dev, 0x0508, 0x0000);
 654         b43_write16(dev, 0x050A, 0x0000);
 655         b43_write16(dev, 0x054C, 0x0000);
 656         b43_write16(dev, 0x056A, 0x0014);
 657         b43_write16(dev, 0x0568, 0x0826);
 658         b43_write16(dev, 0x0500, 0x0000);
 659         b43_write16(dev, 0x0502, 0x0030);
 660
 661         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 662                 b43_radio_write16(dev, 0x0051, 0x0017);
 663         for (i = 0x00; i < max_loop; i++) {
 664                 value = b43_read16(dev, 0x050E);
 665                 if (value & 0x0080)
 666                         break;
 667                 udelay(10);
 668         }
 669         for (i = 0x00; i < 0x0A; i++) {
 670                 value = b43_read16(dev, 0x050E);
 671                 if (value & 0x0400)
 672                         break;
 673                 udelay(10);
 674         }
 675         for (i = 0x00; i < 0x0A; i++) {
 676                 value = b43_read16(dev, 0x0690);
 677                 if (!(value & 0x0100))
 678                         break;
 679                 udelay(10);
 680         }
 681         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 682                 b43_radio_write16(dev, 0x0051, 0x0037);
 683 }
 684
 685 static void key_write(struct b43_wldev *dev,
 686                       u8 index, u8 algorithm, const u8 * key)
 687 {
 688         unsigned int i;
 689         u32 offset;
 690         u16 value;
 691         u16 kidx;
 692
 693         /* Key index/algo block */
 694         kidx = b43_kidx_to_fw(dev, index);
 695         value = ((kidx << 4) | algorithm);
 696         b43_shm_write16(dev, B43_SHM_SHARED,
 697                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 698
 699         /* Write the key to the Key Table Pointer offset */
 700         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 701         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 702                 value = key[i];
 703                 value |= (u16) (key[i + 1]) << 8;
 704                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 705         }
 706 }
 707
 708 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 709 {
 710         u32 addrtmp[2] = { 0, 0, };
 711         u8 per_sta_keys_start = 8;
 712
 713         if (b43_new_kidx_api(dev))
 714                 per_sta_keys_start = 4;
 715
 716         B43_WARN_ON(index < per_sta_keys_start);
 717         /* We have two default TX keys and possibly two default RX keys.
 718          * Physical mac 0 is mapped to physical key 4 or 8, depending
 719          * on the firmware version.
 720          * So we must adjust the index here.
 721          */
 722         index -= per_sta_keys_start;
 723
 724         if (addr) {
 725                 addrtmp[0] = addr[0];
 726                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 727                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 728                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 729                 addrtmp[1] = addr[4];
 730                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 731         }
 732
 733         if (dev->dev->id.revision >= 5) {
 734                 /* Receive match transmitter address mechanism */
 735                 b43_shm_write32(dev, B43_SHM_RCMTA,
 736                                 (index * 2) + 0, addrtmp[0]);
 737                 b43_shm_write16(dev, B43_SHM_RCMTA,
 738                                 (index * 2) + 1, addrtmp[1]);
 739         } else {
 740                 /* RXE (Receive Engine) and
 741                  * PSM (Programmable State Machine) mechanism
 742                  */
 743                 if (index < 8) {
 744                         /* TODO write to RCM 16, 19, 22 and 25 */
 745                 } else {
 746                         b43_shm_write32(dev, B43_SHM_SHARED,
 747                                         B43_SHM_SH_PSM + (index * 6) + 0,
 748                                         addrtmp[0]);
 749                         b43_shm_write16(dev, B43_SHM_SHARED,
 750                                         B43_SHM_SH_PSM + (index * 6) + 4,
 751                                         addrtmp[1]);
 752                 }
 753         }
 754 }
 755
 756 static void do_key_write(struct b43_wldev *dev,
 757                          u8 index, u8 algorithm,
 758                          const u8 * key, size_t key_len, const u8 * mac_addr)
 759 {
 760         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 761         u8 per_sta_keys_start = 8;
 762
 763         if (b43_new_kidx_api(dev))
 764                 per_sta_keys_start = 4;
 765
 766         B43_WARN_ON(index >= dev->max_nr_keys);
 767         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 768
 769         if (index >= per_sta_keys_start)
 770                 keymac_write(dev, index, NULL); /* First zero out mac. */
 771         if (key)
 772                 memcpy(buf, key, key_len);
 773         key_write(dev, index, algorithm, buf);
 774         if (index >= per_sta_keys_start)
 775                 keymac_write(dev, index, mac_addr);
 776
 777         dev->key[index].algorithm = algorithm;
 778 }
 779
 780 static int b43_key_write(struct b43_wldev *dev,
 781                          int index, u8 algorithm,
 782                          const u8 * key, size_t key_len,
 783                          const u8 * mac_addr,
 784                          struct ieee80211_key_conf *keyconf)
 785 {
 786         int i;
 787         int sta_keys_start;
 788
 789         if (key_len > B43_SEC_KEYSIZE)
 790                 return -EINVAL;
 791         for (i = 0; i < dev->max_nr_keys; i++) {
 792                 /* Check that we don't already have this key. */
 793                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 794         }
 795         if (index < 0) {
 796                 /* Either pairwise key or address is 00:00:00:00:00:00
 797                  * for transmit-only keys. Search the index. */
 798                 if (b43_new_kidx_api(dev))
 799                         sta_keys_start = 4;
 800                 else
 801                         sta_keys_start = 8;
 802                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 803                         if (!dev->key[i].keyconf) {
 804                                 /* found empty */
 805                                 index = i;
 806                                 break;
 807                         }
 808                 }
 809                 if (index < 0) {
 810                         b43err(dev->wl, "Out of hardware key memory\n");
 811                         return -ENOSPC;
 812                 }
 813         } else
 814                 B43_WARN_ON(index > 3);
 815
 816         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 817         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 818                 /* Default RX key */
 819                 B43_WARN_ON(mac_addr);
 820                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 821         }
 822         keyconf->hw_key_idx = index;
 823         dev->key[index].keyconf = keyconf;
 824
 825         return 0;
 826 }
 827
 828 static int b43_key_clear(struct b43_wldev *dev, int index)
 829 {
 830         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 831                 return -EINVAL;
 832         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 833                      NULL, B43_SEC_KEYSIZE, NULL);
 834         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 835                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 836                              NULL, B43_SEC_KEYSIZE, NULL);
 837         }
 838         dev->key[index].keyconf = NULL;
 839
 840         return 0;
 841 }
 842
 843 static void b43_clear_keys(struct b43_wldev *dev)
 844 {
 845         int i;
 846
 847         for (i = 0; i < dev->max_nr_keys; i++)
 848                 b43_key_clear(dev, i);
 849 }
 850
 851 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 852 {
 853         u32 macctl;
 854         u16 ucstat;
 855         bool hwps;
 856         bool awake;
 857         int i;
 858
 859         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 860                     (ps_flags & B43_PS_DISABLED));
 861         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 862
 863         if (ps_flags & B43_PS_ENABLED) {
 864                 hwps = 1;
 865         } else if (ps_flags & B43_PS_DISABLED) {
 866                 hwps = 0;
 867         } else {
 868                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 869                 //      and thus is not an AP and we are associated, set bit 25
 870         }
 871         if (ps_flags & B43_PS_AWAKE) {
 872                 awake = 1;
 873         } else if (ps_flags & B43_PS_ASLEEP) {
 874                 awake = 0;
 875         } else {
 876                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 877                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 878                 //      successful, set bit26
 879         }
 880
 881 /* FIXME: For now we force awake-on and hwps-off */
 882         hwps = 0;
 883         awake = 1;
 884
 885         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 886         if (hwps)
 887                 macctl |= B43_MACCTL_HWPS;
 888         else
 889                 macctl &= ~B43_MACCTL_HWPS;
 890         if (awake)
 891                 macctl |= B43_MACCTL_AWAKE;
 892         else
 893                 macctl &= ~B43_MACCTL_AWAKE;
 894         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 895         /* Commit write */
 896         b43_read32(dev, B43_MMIO_MACCTL);
 897         if (awake && dev->dev->id.revision >= 5) {
 898                 /* Wait for the microcode to wake up. */
 899                 for (i = 0; i < 100; i++) {
 900                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 901                                                 B43_SHM_SH_UCODESTAT);
 902                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 903                                 break;
 904                         udelay(10);
 905                 }
 906         }
 907 }
 908
 909 /* Turn the Analog ON/OFF */
 910 static void b43_switch_analog(struct b43_wldev *dev, int on)
 911 {
 912         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 913 }
 914
 915 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 916 {
 917         u32 tmslow;
 918         u32 macctl;
 919
 920         flags |= B43_TMSLOW_PHYCLKEN;
 921         flags |= B43_TMSLOW_PHYRESET;
 922         ssb_device_enable(dev->dev, flags);
 923         msleep(2);              /* Wait for the PLL to turn on. */
 924
 925         /* Now take the PHY out of Reset again */
 926         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 927         tmslow |= SSB_TMSLOW_FGC;
 928         tmslow &= ~B43_TMSLOW_PHYRESET;
 929         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 930         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 931         msleep(1);
 932         tmslow &= ~SSB_TMSLOW_FGC;
 933         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 934         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 935         msleep(1);
 936
 937         /* Turn Analog ON */
 938         b43_switch_analog(dev, 1);
 939
 940         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 941         macctl &= ~B43_MACCTL_GMODE;
 942         if (flags & B43_TMSLOW_GMODE)
 943                 macctl |= B43_MACCTL_GMODE;
 944         macctl |= B43_MACCTL_IHR_ENABLED;
 945         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 946 }
 947
 948 static void handle_irq_transmit_status(struct b43_wldev *dev)
 949 {
 950         u32 v0, v1;
 951         u16 tmp;
 952         struct b43_txstatus stat;
 953
 954         while (1) {
 955                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 956                 if (!(v0 & 0x00000001))
 957                         break;
 958                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 959
 960                 stat.cookie = (v0 >> 16);
 961                 stat.seq = (v1 & 0x0000FFFF);
 962                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 963                 tmp = (v0 & 0x0000FFFF);
 964                 stat.frame_count = ((tmp & 0xF000) >> 12);
 965                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 966                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 967                 stat.pm_indicated = !!(tmp & 0x0080);
 968                 stat.intermediate = !!(tmp & 0x0040);
 969                 stat.for_ampdu = !!(tmp & 0x0020);
 970                 stat.acked = !!(tmp & 0x0002);
 971
 972                 b43_handle_txstatus(dev, &stat);
 973         }
 974 }
 975
 976 static void drain_txstatus_queue(struct b43_wldev *dev)
 977 {
 978         u32 dummy;
 979
 980         if (dev->dev->id.revision < 5)
 981                 return;
 982         /* Read all entries from the microcode TXstatus FIFO
 983          * and throw them away.
 984          */
 985         while (1) {
 986                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 987                 if (!(dummy & 0x00000001))
 988                         break;
 989                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 990         }
 991 }
 992
 993 static u32 b43_jssi_read(struct b43_wldev *dev)
 994 {
 995         u32 val = 0;
 996
 997         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
 998         val <<= 16;
 999         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1000
1001         return val;
1002 }
1003
1004 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1005 {
1006         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1007         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1008 }
1009
1010 static void b43_generate_noise_sample(struct b43_wldev *dev)
1011 {
1012         b43_jssi_write(dev, 0x7F7F7F7F);
1013         b43_write32(dev, B43_MMIO_MACCMD,
1014                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1015         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1016 }
1017
1018 static void b43_calculate_link_quality(struct b43_wldev *dev)
1019 {
1020         /* Top half of Link Quality calculation. */
1021
1022         if (dev->noisecalc.calculation_running)
1023                 return;
1024         dev->noisecalc.channel_at_start = dev->phy.channel;
1025         dev->noisecalc.calculation_running = 1;
1026         dev->noisecalc.nr_samples = 0;
1027
1028         b43_generate_noise_sample(dev);
1029 }
1030
1031 static void handle_irq_noise(struct b43_wldev *dev)
1032 {
1033         struct b43_phy *phy = &dev->phy;
1034         u16 tmp;
1035         u8 noise[4];
1036         u8 i, j;
1037         s32 average;
1038
1039         /* Bottom half of Link Quality calculation. */
1040
1041         B43_WARN_ON(!dev->noisecalc.calculation_running);
1042         if (dev->noisecalc.channel_at_start != phy->channel)
1043                 goto drop_calculation;
1044         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1045         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1046             noise[2] == 0x7F || noise[3] == 0x7F)
1047                 goto generate_new;
1048
1049         /* Get the noise samples. */
1050         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1051         i = dev->noisecalc.nr_samples;
1052         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1053         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1054         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1055         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1056         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1057         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1058         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1059         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1060         dev->noisecalc.nr_samples++;
1061         if (dev->noisecalc.nr_samples == 8) {
1062                 /* Calculate the Link Quality by the noise samples. */
1063                 average = 0;
1064                 for (i = 0; i < 8; i++) {
1065                         for (j = 0; j < 4; j++)
1066                                 average += dev->noisecalc.samples[i][j];
1067                 }
1068                 average /= (8 * 4);
1069                 average *= 125;
1070                 average += 64;
1071                 average /= 128;
1072                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1073                 tmp = (tmp / 128) & 0x1F;
1074                 if (tmp >= 8)
1075                         average += 2;
1076                 else
1077                         average -= 25;
1078                 if (tmp == 8)
1079                         average -= 72;
1080                 else
1081                         average -= 48;
1082
1083                 dev->stats.link_noise = average;
1084               drop_calculation:
1085                 dev->noisecalc.calculation_running = 0;
1086                 return;
1087         }
1088       generate_new:
1089         b43_generate_noise_sample(dev);
1090 }
1091
1092 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1093 {
1094         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1095                 ///TODO: PS TBTT
1096         } else {
1097                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1098                         b43_power_saving_ctl_bits(dev, 0);
1099         }
1100         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1101                 dev->dfq_valid = 1;
1102 }
1103
1104 static void handle_irq_atim_end(struct b43_wldev *dev)
1105 {
1106         if (dev->dfq_valid) {
1107                 b43_write32(dev, B43_MMIO_MACCMD,
1108                             b43_read32(dev, B43_MMIO_MACCMD)
1109                             | B43_MACCMD_DFQ_VALID);
1110                 dev->dfq_valid = 0;
1111         }
1112 }
1113
1114 static void handle_irq_pmq(struct b43_wldev *dev)
1115 {
1116         u32 tmp;
1117
1118         //TODO: AP mode.
1119
1120         while (1) {
1121                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1122                 if (!(tmp & 0x00000008))
1123                         break;
1124         }
1125         /* 16bit write is odd, but correct. */
1126         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1127 }
1128
1129 static void b43_write_template_common(struct b43_wldev *dev,
1130                                       const u8 * data, u16 size,
1131                                       u16 ram_offset,
1132                                       u16 shm_size_offset, u8 rate)
1133 {
1134         u32 i, tmp;
1135         struct b43_plcp_hdr4 plcp;
1136
1137         plcp.data = 0;
1138         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1139         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1140         ram_offset += sizeof(u32);
1141         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1142          * So leave the first two bytes of the next write blank.
1143          */
1144         tmp = (u32) (data[0]) << 16;
1145         tmp |= (u32) (data[1]) << 24;
1146         b43_ram_write(dev, ram_offset, tmp);
1147         ram_offset += sizeof(u32);
1148         for (i = 2; i < size; i += sizeof(u32)) {
1149                 tmp = (u32) (data[i + 0]);
1150                 if (i + 1 < size)
1151                         tmp |= (u32) (data[i + 1]) << 8;
1152                 if (i + 2 < size)
1153                         tmp |= (u32) (data[i + 2]) << 16;
1154                 if (i + 3 < size)
1155                         tmp |= (u32) (data[i + 3]) << 24;
1156                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1157         }
1158         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1159                         size + sizeof(struct b43_plcp_hdr6));
1160 }
1161
1162 static void b43_write_beacon_template(struct b43_wldev *dev,
1163                                       u16 ram_offset,
1164                                       u16 shm_size_offset, u8 rate)
1165 {
1166         unsigned int i, len, variable_len;
1167         const struct ieee80211_mgmt *bcn;
1168         const u8 *ie;
1169         bool tim_found = 0;
1170
1171         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1172         len = min((size_t) dev->wl->current_beacon->len,
1173                   0x200 - sizeof(struct b43_plcp_hdr6));
1174
1175         b43_write_template_common(dev, (const u8 *)bcn,
1176                                   len, ram_offset, shm_size_offset, rate);
1177
1178         /* Find the position of the TIM and the DTIM_period value
1179          * and write them to SHM. */
1180         ie = bcn->u.beacon.variable;
1181         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1182         for (i = 0; i < variable_len - 2; ) {
1183                 uint8_t ie_id, ie_len;
1184
1185                 ie_id = ie[i];
1186                 ie_len = ie[i + 1];
1187                 if (ie_id == 5) {
1188                         u16 tim_position;
1189                         u16 dtim_period;
1190                         /* This is the TIM Information Element */
1191
1192                         /* Check whether the ie_len is in the beacon data range. */
1193                         if (variable_len < ie_len + 2 + i)
1194                                 break;
1195                         /* A valid TIM is at least 4 bytes long. */
1196                         if (ie_len < 4)
1197                                 break;
1198                         tim_found = 1;
1199
1200                         tim_position = sizeof(struct b43_plcp_hdr6);
1201                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1202                         tim_position += i;
1203
1204                         dtim_period = ie[i + 3];
1205
1206                         b43_shm_write16(dev, B43_SHM_SHARED,
1207                                         B43_SHM_SH_TIMBPOS, tim_position);
1208                         b43_shm_write16(dev, B43_SHM_SHARED,
1209                                         B43_SHM_SH_DTIMPER, dtim_period);
1210                         break;
1211                 }
1212                 i += ie_len + 2;
1213         }
1214         if (!tim_found) {
1215                 b43warn(dev->wl, "Did not find a valid TIM IE in "
1216                         "the beacon template packet. AP or IBSS operation "
1217                         "may be broken.\n");
1218         }
1219 }
1220
1221 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1222                                       u16 shm_offset, u16 size, u8 rate)
1223 {
1224         struct b43_plcp_hdr4 plcp;
1225         u32 tmp;
1226         __le16 dur;
1227
1228         plcp.data = 0;
1229         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1230         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1231                                                dev->wl->vif, size,
1232                                                B43_RATE_TO_BASE100KBPS(rate));
1233         /* Write PLCP in two parts and timing for packet transfer */
1234         tmp = le32_to_cpu(plcp.data);
1235         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1236         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1237         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1238 }
1239
1240 /* Instead of using custom probe response template, this function
1241  * just patches custom beacon template by:
1242  * 1) Changing packet type
1243  * 2) Patching duration field
1244  * 3) Stripping TIM
1245  */
1246 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1247                                           u16 *dest_size, u8 rate)
1248 {
1249         const u8 *src_data;
1250         u8 *dest_data;
1251         u16 src_size, elem_size, src_pos, dest_pos;
1252         __le16 dur;
1253         struct ieee80211_hdr *hdr;
1254         size_t ie_start;
1255
1256         src_size = dev->wl->current_beacon->len;
1257         src_data = (const u8 *)dev->wl->current_beacon->data;
1258
1259         /* Get the start offset of the variable IEs in the packet. */
1260         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1261         B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1262
1263         if (B43_WARN_ON(src_size < ie_start))
1264                 return NULL;
1265
1266         dest_data = kmalloc(src_size, GFP_ATOMIC);
1267         if (unlikely(!dest_data))
1268                 return NULL;
1269
1270         /* Copy the static data and all Information Elements, except the TIM. */
1271         memcpy(dest_data, src_data, ie_start);
1272         src_pos = ie_start;
1273         dest_pos = ie_start;
1274         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1275                 elem_size = src_data[src_pos + 1] + 2;
1276                 if (src_data[src_pos] == 5) {
1277                         /* This is the TIM. */
1278                         continue;
1279                 }
1280                 memcpy(dest_data + dest_pos, src_data + src_pos,
1281                        elem_size);
1282                 dest_pos += elem_size;
1283         }
1284         *dest_size = dest_pos;
1285         hdr = (struct ieee80211_hdr *)dest_data;
1286
1287         /* Set the frame control. */
1288         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1289                                          IEEE80211_STYPE_PROBE_RESP);
1290         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1291                                                dev->wl->vif, *dest_size,
1292                                                B43_RATE_TO_BASE100KBPS(rate));
1293         hdr->duration_id = dur;
1294
1295         return dest_data;
1296 }
1297
1298 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1299                                           u16 ram_offset,
1300                                           u16 shm_size_offset, u8 rate)
1301 {
1302         const u8 *probe_resp_data;
1303         u16 size;
1304
1305         size = dev->wl->current_beacon->len;
1306         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1307         if (unlikely(!probe_resp_data))
1308                 return;
1309
1310         /* Looks like PLCP headers plus packet timings are stored for
1311          * all possible basic rates
1312          */
1313         b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1314         b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1315         b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1316         b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1317
1318         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1319         b43_write_template_common(dev, probe_resp_data,
1320                                   size, ram_offset, shm_size_offset, rate);
1321         kfree(probe_resp_data);
1322 }
1323
1324 /* Asynchronously update the packet templates in template RAM.
1325  * Locking: Requires wl->irq_lock to be locked. */
1326 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1327 {
1328         /* This is the top half of the ansynchronous beacon update.
1329          * The bottom half is the beacon IRQ.
1330          * Beacon update must be asynchronous to avoid sending an
1331          * invalid beacon. This can happen for example, if the firmware
1332          * transmits a beacon while we are updating it. */
1333
1334         if (wl->current_beacon)
1335                 dev_kfree_skb_any(wl->current_beacon);
1336         wl->current_beacon = beacon;
1337         wl->beacon0_uploaded = 0;
1338         wl->beacon1_uploaded = 0;
1339 }
1340
1341 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1342 {
1343         u32 tmp;
1344         u16 i, len;
1345
1346         len = min((u16) ssid_len, (u16) 0x100);
1347         for (i = 0; i < len; i += sizeof(u32)) {
1348                 tmp = (u32) (ssid[i + 0]);
1349                 if (i + 1 < len)
1350                         tmp |= (u32) (ssid[i + 1]) << 8;
1351                 if (i + 2 < len)
1352                         tmp |= (u32) (ssid[i + 2]) << 16;
1353                 if (i + 3 < len)
1354                         tmp |= (u32) (ssid[i + 3]) << 24;
1355                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1356         }
1357         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1358 }
1359
1360 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1361 {
1362         b43_time_lock(dev);
1363         if (dev->dev->id.revision >= 3) {
1364                 b43_write32(dev, 0x188, (beacon_int << 16));
1365         } else {
1366                 b43_write16(dev, 0x606, (beacon_int >> 6));
1367                 b43_write16(dev, 0x610, beacon_int);
1368         }
1369         b43_time_unlock(dev);
1370 }
1371
1372 static void handle_irq_beacon(struct b43_wldev *dev)
1373 {
1374         struct b43_wl *wl = dev->wl;
1375         u32 cmd;
1376
1377         if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1378                 return;
1379
1380         /* This is the bottom half of the asynchronous beacon update. */
1381
1382         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1383         if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1384                 if (!wl->beacon0_uploaded) {
1385                         b43_write_beacon_template(dev, 0x68, 0x18,
1386                                                   B43_CCK_RATE_1MB);
1387                         b43_write_probe_resp_template(dev, 0x268, 0x4A,
1388                                                       B43_CCK_RATE_11MB);
1389                         wl->beacon0_uploaded = 1;
1390                 }
1391                 cmd |= B43_MACCMD_BEACON0_VALID;
1392         }
1393         if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1394                 if (!wl->beacon1_uploaded) {
1395                         b43_write_beacon_template(dev, 0x468, 0x1A,
1396                                                   B43_CCK_RATE_1MB);
1397                         wl->beacon1_uploaded = 1;
1398                 }
1399                 cmd |= B43_MACCMD_BEACON1_VALID;
1400         }
1401         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1402 }
1403
1404 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1405 {
1406         //TODO
1407 }
1408
1409 /* Interrupt handler bottom-half */
1410 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1411 {
1412         u32 reason;
1413         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1414         u32 merged_dma_reason = 0;
1415         int i;
1416         unsigned long flags;
1417
1418         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1419
1420         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1421
1422         reason = dev->irq_reason;
1423         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1424                 dma_reason[i] = dev->dma_reason[i];
1425                 merged_dma_reason |= dma_reason[i];
1426         }
1427
1428         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1429                 b43err(dev->wl, "MAC transmission error\n");
1430
1431         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1432                 b43err(dev->wl, "PHY transmission error\n");
1433                 rmb();
1434                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1435                         atomic_set(&dev->phy.txerr_cnt,
1436                                    B43_PHY_TX_BADNESS_LIMIT);
1437                         b43err(dev->wl, "Too many PHY TX errors, "
1438                                         "restarting the controller\n");
1439                         b43_controller_restart(dev, "PHY TX errors");
1440                 }
1441         }
1442
1443         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1444                                           B43_DMAIRQ_NONFATALMASK))) {
1445                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1446                         b43err(dev->wl, "Fatal DMA error: "
1447                                "0x%08X, 0x%08X, 0x%08X, "
1448                                "0x%08X, 0x%08X, 0x%08X\n",
1449                                dma_reason[0], dma_reason[1],
1450                                dma_reason[2], dma_reason[3],
1451                                dma_reason[4], dma_reason[5]);
1452                         b43_controller_restart(dev, "DMA error");
1453                         mmiowb();
1454                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1455                         return;
1456                 }
1457                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1458                         b43err(dev->wl, "DMA error: "
1459                                "0x%08X, 0x%08X, 0x%08X, "
1460                                "0x%08X, 0x%08X, 0x%08X\n",
1461                                dma_reason[0], dma_reason[1],
1462                                dma_reason[2], dma_reason[3],
1463                                dma_reason[4], dma_reason[5]);
1464                 }
1465         }
1466
1467         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1468                 handle_irq_ucode_debug(dev);
1469         if (reason & B43_IRQ_TBTT_INDI)
1470                 handle_irq_tbtt_indication(dev);
1471         if (reason & B43_IRQ_ATIM_END)
1472                 handle_irq_atim_end(dev);
1473         if (reason & B43_IRQ_BEACON)
1474                 handle_irq_beacon(dev);
1475         if (reason & B43_IRQ_PMQ)
1476                 handle_irq_pmq(dev);
1477         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1478                 ;/* TODO */
1479         if (reason & B43_IRQ_NOISESAMPLE_OK)
1480                 handle_irq_noise(dev);
1481
1482         /* Check the DMA reason registers for received data. */
1483         if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1484                 b43_dma_rx(dev->dma.rx_ring0);
1485         if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1486                 b43_dma_rx(dev->dma.rx_ring3);
1487         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1488         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1489         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1490         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1491
1492         if (reason & B43_IRQ_TX_OK)
1493                 handle_irq_transmit_status(dev);
1494
1495         b43_interrupt_enable(dev, dev->irq_savedstate);
1496         mmiowb();
1497         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1498 }
1499
1500 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1501 {
1502         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1503
1504         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1505         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1506         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1507         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1508         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1509         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1510 }
1511
1512 /* Interrupt handler top-half */
1513 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1514 {
1515         irqreturn_t ret = IRQ_NONE;
1516         struct b43_wldev *dev = dev_id;
1517         u32 reason;
1518
1519         if (!dev)
1520                 return IRQ_NONE;
1521
1522         spin_lock(&dev->wl->irq_lock);
1523
1524         if (b43_status(dev) < B43_STAT_STARTED)
1525                 goto out;
1526         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1527         if (reason == 0xffffffff)       /* shared IRQ */
1528                 goto out;
1529         ret = IRQ_HANDLED;
1530         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1531         if (!reason)
1532                 goto out;
1533
1534         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1535             & 0x0001DC00;
1536         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1537             & 0x0000DC00;
1538         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1539             & 0x0000DC00;
1540         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1541             & 0x0001DC00;
1542         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1543             & 0x0000DC00;
1544         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1545             & 0x0000DC00;
1546
1547         b43_interrupt_ack(dev, reason);
1548         /* disable all IRQs. They are enabled again in the bottom half. */
1549         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1550         /* save the reason code and call our bottom half. */
1551         dev->irq_reason = reason;
1552         tasklet_schedule(&dev->isr_tasklet);
1553       out:
1554         mmiowb();
1555         spin_unlock(&dev->wl->irq_lock);
1556
1557         return ret;
1558 }
1559
1560 static void b43_release_firmware(struct b43_wldev *dev)
1561 {
1562         release_firmware(dev->fw.ucode);
1563         dev->fw.ucode = NULL;
1564         release_firmware(dev->fw.pcm);
1565         dev->fw.pcm = NULL;
1566         release_firmware(dev->fw.initvals);
1567         dev->fw.initvals = NULL;
1568         release_firmware(dev->fw.initvals_band);
1569         dev->fw.initvals_band = NULL;
1570 }
1571
1572 static void b43_print_fw_helptext(struct b43_wl *wl)
1573 {
1574         b43err(wl, "You must go to "
1575                "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1576                "and download the correct firmware (version 4).\n");
1577 }
1578
1579 static int do_request_fw(struct b43_wldev *dev,
1580                          const char *name,
1581                          const struct firmware **fw)
1582 {
1583         char path[sizeof(modparam_fwpostfix) + 32];
1584         struct b43_fw_header *hdr;
1585         u32 size;
1586         int err;
1587
1588         if (!name)
1589                 return 0;
1590
1591         snprintf(path, ARRAY_SIZE(path),
1592                  "b43%s/%s.fw",
1593                  modparam_fwpostfix, name);
1594         err = request_firmware(fw, path, dev->dev->dev);
1595         if (err) {
1596                 b43err(dev->wl, "Firmware file \"%s\" not found "
1597                        "or load failed.\n", path);
1598                 return err;
1599         }
1600         if ((*fw)->size < sizeof(struct b43_fw_header))
1601                 goto err_format;
1602         hdr = (struct b43_fw_header *)((*fw)->data);
1603         switch (hdr->type) {
1604         case B43_FW_TYPE_UCODE:
1605         case B43_FW_TYPE_PCM:
1606                 size = be32_to_cpu(hdr->size);
1607                 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1608                         goto err_format;
1609                 /* fallthrough */
1610         case B43_FW_TYPE_IV:
1611                 if (hdr->ver != 1)
1612                         goto err_format;
1613                 break;
1614         default:
1615                 goto err_format;
1616         }
1617
1618         return err;
1619
1620 err_format:
1621         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1622         return -EPROTO;
1623 }
1624
1625 static int b43_request_firmware(struct b43_wldev *dev)
1626 {
1627         struct b43_firmware *fw = &dev->fw;
1628         const u8 rev = dev->dev->id.revision;
1629         const char *filename;
1630         u32 tmshigh;
1631         int err;
1632
1633         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1634         if (!fw->ucode) {
1635                 if ((rev >= 5) && (rev <= 10))
1636                         filename = "ucode5";
1637                 else if ((rev >= 11) && (rev <= 12))
1638                         filename = "ucode11";
1639                 else if (rev >= 13)
1640                         filename = "ucode13";
1641                 else
1642                         goto err_no_ucode;
1643                 err = do_request_fw(dev, filename, &fw->ucode);
1644                 if (err)
1645                         goto err_load;
1646         }
1647         if (!fw->pcm) {
1648                 if ((rev >= 5) && (rev <= 10))
1649                         filename = "pcm5";
1650                 else if (rev >= 11)
1651                         filename = NULL;
1652                 else
1653                         goto err_no_pcm;
1654                 err = do_request_fw(dev, filename, &fw->pcm);
1655                 if (err)
1656                         goto err_load;
1657         }
1658         if (!fw->initvals) {
1659                 switch (dev->phy.type) {
1660                 case B43_PHYTYPE_A:
1661                         if ((rev >= 5) && (rev <= 10)) {
1662                                 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1663                                         filename = "a0g1initvals5";
1664                                 else
1665                                         filename = "a0g0initvals5";
1666                         } else
1667                                 goto err_no_initvals;
1668                         break;
1669                 case B43_PHYTYPE_G:
1670                         if ((rev >= 5) && (rev <= 10))
1671                                 filename = "b0g0initvals5";
1672                         else if (rev >= 13)
1673                                 filename = "lp0initvals13";
1674                         else
1675                                 goto err_no_initvals;
1676                         break;
1677                 default:
1678                         goto err_no_initvals;
1679                 }
1680                 err = do_request_fw(dev, filename, &fw->initvals);
1681                 if (err)
1682                         goto err_load;
1683         }
1684         if (!fw->initvals_band) {
1685                 switch (dev->phy.type) {
1686                 case B43_PHYTYPE_A:
1687                         if ((rev >= 5) && (rev <= 10)) {
1688                                 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1689                                         filename = "a0g1bsinitvals5";
1690                                 else
1691                                         filename = "a0g0bsinitvals5";
1692                         } else if (rev >= 11)
1693                                 filename = NULL;
1694                         else
1695                                 goto err_no_initvals;
1696                         break;
1697                 case B43_PHYTYPE_G:
1698                         if ((rev >= 5) && (rev <= 10))
1699                                 filename = "b0g0bsinitvals5";
1700                         else if (rev >= 11)
1701                                 filename = NULL;
1702                         else
1703                                 goto err_no_initvals;
1704                         break;
1705                 default:
1706                         goto err_no_initvals;
1707                 }
1708                 err = do_request_fw(dev, filename, &fw->initvals_band);
1709                 if (err)
1710                         goto err_load;
1711         }
1712
1713         return 0;
1714
1715 err_load:
1716         b43_print_fw_helptext(dev->wl);
1717         goto error;
1718
1719 err_no_ucode:
1720         err = -ENODEV;
1721         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1722         goto error;
1723
1724 err_no_pcm:
1725         err = -ENODEV;
1726         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1727         goto error;
1728
1729 err_no_initvals:
1730         err = -ENODEV;
1731         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1732                "core rev %u\n", dev->phy.type, rev);
1733         goto error;
1734
1735 error:
1736         b43_release_firmware(dev);
1737         return err;
1738 }
1739
1740 static int b43_upload_microcode(struct b43_wldev *dev)
1741 {
1742         const size_t hdr_len = sizeof(struct b43_fw_header);
1743         const __be32 *data;
1744         unsigned int i, len;
1745         u16 fwrev, fwpatch, fwdate, fwtime;
1746         u32 tmp;
1747         int err = 0;
1748
1749         /* Upload Microcode. */
1750         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1751         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1752         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1753         for (i = 0; i < len; i++) {
1754                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1755                 udelay(10);
1756         }
1757
1758         if (dev->fw.pcm) {
1759                 /* Upload PCM data. */
1760                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1761                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1762                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1763                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1764                 /* No need for autoinc bit in SHM_HW */
1765                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1766                 for (i = 0; i < len; i++) {
1767                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1768                         udelay(10);
1769                 }
1770         }
1771
1772         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1773         b43_write32(dev, B43_MMIO_MACCTL,
1774                     B43_MACCTL_PSM_RUN |
1775                     B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1776
1777         /* Wait for the microcode to load and respond */
1778         i = 0;
1779         while (1) {
1780                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1781                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1782                         break;
1783                 i++;
1784                 if (i >= 50) {
1785                         b43err(dev->wl, "Microcode not responding\n");
1786                         b43_print_fw_helptext(dev->wl);
1787                         err = -ENODEV;
1788                         goto out;
1789                 }
1790                 udelay(10);
1791         }
1792         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1793
1794         /* Get and check the revisions. */
1795         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1796         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1797         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1798         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1799
1800         if (fwrev <= 0x128) {
1801                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1802                        "binary drivers older than version 4.x is unsupported. "
1803                        "You must upgrade your firmware files.\n");
1804                 b43_print_fw_helptext(dev->wl);
1805                 b43_write32(dev, B43_MMIO_MACCTL, 0);
1806                 err = -EOPNOTSUPP;
1807                 goto out;
1808         }
1809         b43dbg(dev->wl, "Loading firmware version %u.%u "
1810                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1811                fwrev, fwpatch,
1812                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1813                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1814
1815         dev->fw.rev = fwrev;
1816         dev->fw.patch = fwpatch;
1817
1818       out:
1819         return err;
1820 }
1821
1822 static int b43_write_initvals(struct b43_wldev *dev,
1823                               const struct b43_iv *ivals,
1824                               size_t count,
1825                               size_t array_size)
1826 {
1827         const struct b43_iv *iv;
1828         u16 offset;
1829         size_t i;
1830         bool bit32;
1831
1832         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1833         iv = ivals;
1834         for (i = 0; i < count; i++) {
1835                 if (array_size < sizeof(iv->offset_size))
1836                         goto err_format;
1837                 array_size -= sizeof(iv->offset_size);
1838                 offset = be16_to_cpu(iv->offset_size);
1839                 bit32 = !!(offset & B43_IV_32BIT);
1840                 offset &= B43_IV_OFFSET_MASK;
1841                 if (offset >= 0x1000)
1842                         goto err_format;
1843                 if (bit32) {
1844                         u32 value;
1845
1846                         if (array_size < sizeof(iv->data.d32))
1847                                 goto err_format;
1848                         array_size -= sizeof(iv->data.d32);
1849
1850                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1851                         b43_write32(dev, offset, value);
1852
1853                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1854                                                         sizeof(__be16) +
1855                                                         sizeof(__be32));
1856                 } else {
1857                         u16 value;
1858
1859                         if (array_size < sizeof(iv->data.d16))
1860                                 goto err_format;
1861                         array_size -= sizeof(iv->data.d16);
1862
1863                         value = be16_to_cpu(iv->data.d16);
1864                         b43_write16(dev, offset, value);
1865
1866                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1867                                                         sizeof(__be16) +
1868                                                         sizeof(__be16));
1869                 }
1870         }
1871         if (array_size)
1872                 goto err_format;
1873
1874         return 0;
1875
1876 err_format:
1877         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1878         b43_print_fw_helptext(dev->wl);
1879
1880         return -EPROTO;
1881 }
1882
1883 static int b43_upload_initvals(struct b43_wldev *dev)
1884 {
1885         const size_t hdr_len = sizeof(struct b43_fw_header);
1886         const struct b43_fw_header *hdr;
1887         struct b43_firmware *fw = &dev->fw;
1888         const struct b43_iv *ivals;
1889         size_t count;
1890         int err;
1891
1892         hdr = (const struct b43_fw_header *)(fw->initvals->data);
1893         ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1894         count = be32_to_cpu(hdr->size);
1895         err = b43_write_initvals(dev, ivals, count,
1896                                  fw->initvals->size - hdr_len);
1897         if (err)
1898                 goto out;
1899         if (fw->initvals_band) {
1900                 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1901                 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1902                 count = be32_to_cpu(hdr->size);
1903                 err = b43_write_initvals(dev, ivals, count,
1904                                          fw->initvals_band->size - hdr_len);
1905                 if (err)
1906                         goto out;
1907         }
1908 out:
1909
1910         return err;
1911 }
1912
1913 /* Initialize the GPIOs
1914  * http://bcm-specs.sipsolutions.net/GPIO
1915  */
1916 static int b43_gpio_init(struct b43_wldev *dev)
1917 {
1918         struct ssb_bus *bus = dev->dev->bus;
1919         struct ssb_device *gpiodev, *pcidev = NULL;
1920         u32 mask, set;
1921
1922         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1923                     & ~B43_MACCTL_GPOUTSMSK);
1924
1925         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1926                     | 0x000F);
1927
1928         mask = 0x0000001F;
1929         set = 0x0000000F;
1930         if (dev->dev->bus->chip_id == 0x4301) {
1931                 mask |= 0x0060;
1932                 set |= 0x0060;
1933         }
1934         if (0 /* FIXME: conditional unknown */ ) {
1935                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1936                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1937                             | 0x0100);
1938                 mask |= 0x0180;
1939                 set |= 0x0180;
1940         }
1941         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1942                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1943                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1944                             | 0x0200);
1945                 mask |= 0x0200;
1946                 set |= 0x0200;
1947         }
1948         if (dev->dev->id.revision >= 2)
1949                 mask |= 0x0010; /* FIXME: This is redundant. */
1950
1951 #ifdef CONFIG_SSB_DRIVER_PCICORE
1952         pcidev = bus->pcicore.dev;
1953 #endif
1954         gpiodev = bus->chipco.dev ? : pcidev;
1955         if (!gpiodev)
1956                 return 0;
1957         ssb_write32(gpiodev, B43_GPIO_CONTROL,
1958                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1959                      & mask) | set);
1960
1961         return 0;
1962 }
1963
1964 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1965 static void b43_gpio_cleanup(struct b43_wldev *dev)
1966 {
1967         struct ssb_bus *bus = dev->dev->bus;
1968         struct ssb_device *gpiodev, *pcidev = NULL;
1969
1970 #ifdef CONFIG_SSB_DRIVER_PCICORE
1971         pcidev = bus->pcicore.dev;
1972 #endif
1973         gpiodev = bus->chipco.dev ? : pcidev;
1974         if (!gpiodev)
1975                 return;
1976         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1977 }
1978
1979 /* http://bcm-specs.sipsolutions.net/EnableMac */
1980 void b43_mac_enable(struct b43_wldev *dev)
1981 {
1982         dev->mac_suspended--;
1983         B43_WARN_ON(dev->mac_suspended < 0);
1984         B43_WARN_ON(irqs_disabled());
1985         if (dev->mac_suspended == 0) {
1986                 b43_write32(dev, B43_MMIO_MACCTL,
1987                             b43_read32(dev, B43_MMIO_MACCTL)
1988                             | B43_MACCTL_ENABLED);
1989                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1990                             B43_IRQ_MAC_SUSPENDED);
1991                 /* Commit writes */
1992                 b43_read32(dev, B43_MMIO_MACCTL);
1993                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1994                 b43_power_saving_ctl_bits(dev, 0);
1995
1996                 /* Re-enable IRQs. */
1997                 spin_lock_irq(&dev->wl->irq_lock);
1998                 b43_interrupt_enable(dev, dev->irq_savedstate);
1999                 spin_unlock_irq(&dev->wl->irq_lock);
2000         }
2001 }
2002
2003 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2004 void b43_mac_suspend(struct b43_wldev *dev)
2005 {
2006         int i;
2007         u32 tmp;
2008
2009         might_sleep();
2010         B43_WARN_ON(irqs_disabled());
2011         B43_WARN_ON(dev->mac_suspended < 0);
2012
2013         if (dev->mac_suspended == 0) {
2014                 /* Mask IRQs before suspending MAC. Otherwise
2015                  * the MAC stays busy and won't suspend. */
2016                 spin_lock_irq(&dev->wl->irq_lock);
2017                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2018                 spin_unlock_irq(&dev->wl->irq_lock);
2019                 b43_synchronize_irq(dev);
2020                 dev->irq_savedstate = tmp;
2021
2022                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2023                 b43_write32(dev, B43_MMIO_MACCTL,
2024                             b43_read32(dev, B43_MMIO_MACCTL)
2025                             & ~B43_MACCTL_ENABLED);
2026                 /* force pci to flush the write */
2027                 b43_read32(dev, B43_MMIO_MACCTL);
2028                 for (i = 40; i; i--) {
2029                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2030                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2031                                 goto out;
2032                         msleep(1);
2033                 }
2034                 b43err(dev->wl, "MAC suspend failed\n");
2035         }
2036 out:
2037         dev->mac_suspended++;
2038 }
2039
2040 static void b43_adjust_opmode(struct b43_wldev *dev)
2041 {
2042         struct b43_wl *wl = dev->wl;
2043         u32 ctl;
2044         u16 cfp_pretbtt;
2045
2046         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2047         /* Reset status to STA infrastructure mode. */
2048         ctl &= ~B43_MACCTL_AP;
2049         ctl &= ~B43_MACCTL_KEEP_CTL;
2050         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2051         ctl &= ~B43_MACCTL_KEEP_BAD;
2052         ctl &= ~B43_MACCTL_PROMISC;
2053         ctl &= ~B43_MACCTL_BEACPROMISC;
2054         ctl |= B43_MACCTL_INFRA;
2055
2056         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2057                 ctl |= B43_MACCTL_AP;
2058         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2059                 ctl &= ~B43_MACCTL_INFRA;
2060
2061         if (wl->filter_flags & FIF_CONTROL)
2062                 ctl |= B43_MACCTL_KEEP_CTL;
2063         if (wl->filter_flags & FIF_FCSFAIL)
2064                 ctl |= B43_MACCTL_KEEP_BAD;
2065         if (wl->filter_flags & FIF_PLCPFAIL)
2066                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2067         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2068                 ctl |= B43_MACCTL_PROMISC;
2069         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2070                 ctl |= B43_MACCTL_BEACPROMISC;
2071
2072         /* Workaround: On old hardware the HW-MAC-address-filter
2073          * doesn't work properly, so always run promisc in filter
2074          * it in software. */
2075         if (dev->dev->id.revision <= 4)
2076                 ctl |= B43_MACCTL_PROMISC;
2077
2078         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2079
2080         cfp_pretbtt = 2;
2081         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2082                 if (dev->dev->bus->chip_id == 0x4306 &&
2083                     dev->dev->bus->chip_rev == 3)
2084                         cfp_pretbtt = 100;
2085                 else
2086                         cfp_pretbtt = 50;
2087         }
2088         b43_write16(dev, 0x612, cfp_pretbtt);
2089 }
2090
2091 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2092 {
2093         u16 offset;
2094
2095         if (is_ofdm) {
2096                 offset = 0x480;
2097                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2098         } else {
2099                 offset = 0x4C0;
2100                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2101         }
2102         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2103                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2104 }
2105
2106 static void b43_rate_memory_init(struct b43_wldev *dev)
2107 {
2108         switch (dev->phy.type) {
2109         case B43_PHYTYPE_A:
2110         case B43_PHYTYPE_G:
2111                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2112                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2113                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2114                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2115                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2116                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2117                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2118                 if (dev->phy.type == B43_PHYTYPE_A)
2119                         break;
2120                 /* fallthrough */
2121         case B43_PHYTYPE_B:
2122                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2123                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2124                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2125                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2126                 break;
2127         default:
2128                 B43_WARN_ON(1);
2129         }
2130 }
2131
2132 /* Set the TX-Antenna for management frames sent by firmware. */
2133 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2134 {
2135         u16 ant = 0;
2136         u16 tmp;
2137
2138         switch (antenna) {
2139         case B43_ANTENNA0:
2140                 ant |= B43_TX4_PHY_ANT0;
2141                 break;
2142         case B43_ANTENNA1:
2143                 ant |= B43_TX4_PHY_ANT1;
2144                 break;
2145         case B43_ANTENNA_AUTO:
2146                 ant |= B43_TX4_PHY_ANTLAST;
2147                 break;
2148         default:
2149                 B43_WARN_ON(1);
2150         }
2151
2152         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2153
2154         /* For Beacons */
2155         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2156         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2157         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2158         /* For ACK/CTS */
2159         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2160         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2161         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2162         /* For Probe Resposes */
2163         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2164         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2165         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2166 }
2167
2168 /* This is the opposite of b43_chip_init() */
2169 static void b43_chip_exit(struct b43_wldev *dev)
2170 {
2171         b43_radio_turn_off(dev, 1);
2172         b43_gpio_cleanup(dev);
2173         /* firmware is released later */
2174 }
2175
2176 /* Initialize the chip
2177  * http://bcm-specs.sipsolutions.net/ChipInit
2178  */
2179 static int b43_chip_init(struct b43_wldev *dev)
2180 {
2181         struct b43_phy *phy = &dev->phy;
2182         int err, tmp;
2183         u32 value32;
2184         u16 value16;
2185
2186         b43_write32(dev, B43_MMIO_MACCTL,
2187                     B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2188
2189         err = b43_request_firmware(dev);
2190         if (err)
2191                 goto out;
2192         err = b43_upload_microcode(dev);
2193         if (err)
2194                 goto out;       /* firmware is released later */
2195
2196         err = b43_gpio_init(dev);
2197         if (err)
2198                 goto out;       /* firmware is released later */
2199
2200         err = b43_upload_initvals(dev);
2201         if (err)
2202                 goto err_gpio_clean;
2203         b43_radio_turn_on(dev);
2204
2205         b43_write16(dev, 0x03E6, 0x0000);
2206         err = b43_phy_init(dev);
2207         if (err)
2208                 goto err_radio_off;
2209
2210         /* Select initial Interference Mitigation. */
2211         tmp = phy->interfmode;
2212         phy->interfmode = B43_INTERFMODE_NONE;
2213         b43_radio_set_interference_mitigation(dev, tmp);
2214
2215         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2216         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2217
2218         if (phy->type == B43_PHYTYPE_B) {
2219                 value16 = b43_read16(dev, 0x005E);
2220                 value16 |= 0x0004;
2221                 b43_write16(dev, 0x005E, value16);
2222         }
2223         b43_write32(dev, 0x0100, 0x01000000);
2224         if (dev->dev->id.revision < 5)
2225                 b43_write32(dev, 0x010C, 0x01000000);
2226
2227         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2228                     & ~B43_MACCTL_INFRA);
2229         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2230                     | B43_MACCTL_INFRA);
2231
2232         /* Probe Response Timeout value */
2233         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2234         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2235
2236         /* Initially set the wireless operation mode. */
2237         b43_adjust_opmode(dev);
2238
2239         if (dev->dev->id.revision < 3) {
2240                 b43_write16(dev, 0x060E, 0x0000);
2241                 b43_write16(dev, 0x0610, 0x8000);
2242                 b43_write16(dev, 0x0604, 0x0000);
2243                 b43_write16(dev, 0x0606, 0x0200);
2244         } else {
2245                 b43_write32(dev, 0x0188, 0x80000000);
2246                 b43_write32(dev, 0x018C, 0x02000000);
2247         }
2248         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2249         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2250         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2251         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2252         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2253         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2254         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2255
2256         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2257         value32 |= 0x00100000;
2258         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2259
2260         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2261                     dev->dev->bus->chipco.fast_pwrup_delay);
2262
2263         err = 0;
2264         b43dbg(dev->wl, "Chip initialized\n");
2265 out:
2266         return err;
2267
2268 err_radio_off:
2269         b43_radio_turn_off(dev, 1);
2270 err_gpio_clean:
2271         b43_gpio_cleanup(dev);
2272         return err;
2273 }
2274
2275 static void b43_periodic_every120sec(struct b43_wldev *dev)
2276 {
2277         struct b43_phy *phy = &dev->phy;
2278
2279         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2280                 return;
2281
2282         b43_mac_suspend(dev);
2283         b43_lo_g_measure(dev);
2284         b43_mac_enable(dev);
2285         if (b43_has_hardware_pctl(phy))
2286                 b43_lo_g_ctl_mark_all_unused(dev);
2287 }
2288
2289 static void b43_periodic_every60sec(struct b43_wldev *dev)
2290 {
2291         struct b43_phy *phy = &dev->phy;
2292
2293         if (!b43_has_hardware_pctl(phy))
2294                 b43_lo_g_ctl_mark_all_unused(dev);
2295         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2296                 b43_mac_suspend(dev);
2297                 b43_calc_nrssi_slope(dev);
2298                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2299                         u8 old_chan = phy->channel;
2300
2301                         /* VCO Calibration */
2302                         if (old_chan >= 8)
2303                                 b43_radio_selectchannel(dev, 1, 0);
2304                         else
2305                                 b43_radio_selectchannel(dev, 13, 0);
2306                         b43_radio_selectchannel(dev, old_chan, 0);
2307                 }
2308                 b43_mac_enable(dev);
2309         }
2310 }
2311
2312 static void b43_periodic_every30sec(struct b43_wldev *dev)
2313 {
2314         /* Update device statistics. */
2315         b43_calculate_link_quality(dev);
2316 }
2317
2318 static void b43_periodic_every15sec(struct b43_wldev *dev)
2319 {
2320         struct b43_phy *phy = &dev->phy;
2321
2322         if (phy->type == B43_PHYTYPE_G) {
2323                 //TODO: update_aci_moving_average
2324                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2325                         b43_mac_suspend(dev);
2326                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2327                                 if (0 /*TODO: bunch of conditions */ ) {
2328                                         b43_radio_set_interference_mitigation
2329                                             (dev, B43_INTERFMODE_MANUALWLAN);
2330                                 }
2331                         } else if (1 /*TODO*/) {
2332                                 /*
2333                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2334                                    b43_radio_set_interference_mitigation(dev,
2335                                    B43_INTERFMODE_NONE);
2336                                    }
2337                                  */
2338                         }
2339                         b43_mac_enable(dev);
2340                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2341                            phy->rev == 1) {
2342                         //TODO: implement rev1 workaround
2343                 }
2344         }
2345         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2346         //TODO for APHY (temperature?)
2347
2348         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2349         wmb();
2350 }
2351
2352 static void do_periodic_work(struct b43_wldev *dev)
2353 {
2354         unsigned int state;
2355
2356         state = dev->periodic_state;
2357         if (state % 8 == 0)
2358                 b43_periodic_every120sec(dev);
2359         if (state % 4 == 0)
2360                 b43_periodic_every60sec(dev);
2361         if (state % 2 == 0)
2362                 b43_periodic_every30sec(dev);
2363         b43_periodic_every15sec(dev);
2364 }
2365
2366 /* Periodic work locking policy:
2367  *      The whole periodic work handler is protected by
2368  *      wl->mutex. If another lock is needed somewhere in the
2369  *      pwork callchain, it's aquired in-place, where it's needed.
2370  */
2371 static void b43_periodic_work_handler(struct work_struct *work)
2372 {
2373         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2374                                              periodic_work.work);
2375         struct b43_wl *wl = dev->wl;
2376         unsigned long delay;
2377
2378         mutex_lock(&wl->mutex);
2379
2380         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2381                 goto out;
2382         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2383                 goto out_requeue;
2384
2385         do_periodic_work(dev);
2386
2387         dev->periodic_state++;
2388 out_requeue:
2389         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2390                 delay = msecs_to_jiffies(50);
2391         else
2392                 delay = round_jiffies_relative(HZ * 15);
2393         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2394 out:
2395         mutex_unlock(&wl->mutex);
2396 }
2397
2398 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2399 {
2400         struct delayed_work *work = &dev->periodic_work;
2401
2402         dev->periodic_state = 0;
2403         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2404         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2405 }
2406
2407 /* Check if communication with the device works correctly. */
2408 static int b43_validate_chipaccess(struct b43_wldev *dev)
2409 {
2410         u32 v, backup;
2411
2412         backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2413
2414         /* Check for read/write and endianness problems. */
2415         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2416         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2417                 goto error;
2418         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2419         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2420                 goto error;
2421
2422         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2423
2424         if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2425                 /* The 32bit register shadows the two 16bit registers
2426                  * with update sideeffects. Validate this. */
2427                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2428                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2429                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2430                         goto error;
2431                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2432                         goto error;
2433         }
2434         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2435
2436         v = b43_read32(dev, B43_MMIO_MACCTL);
2437         v |= B43_MACCTL_GMODE;
2438         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2439                 goto error;
2440
2441         return 0;
2442 error:
2443         b43err(dev->wl, "Failed to validate the chipaccess\n");
2444         return -ENODEV;
2445 }
2446
2447 static void b43_security_init(struct b43_wldev *dev)
2448 {
2449         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2450         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2451         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2452         /* KTP is a word address, but we address SHM bytewise.
2453          * So multiply by two.
2454          */
2455         dev->ktp *= 2;
2456         if (dev->dev->id.revision >= 5) {
2457                 /* Number of RCMTA address slots */
2458                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2459         }
2460         b43_clear_keys(dev);
2461 }
2462
2463 static int b43_rng_read(struct hwrng *rng, u32 * data)
2464 {
2465         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2466         unsigned long flags;
2467
2468         /* Don't take wl->mutex here, as it could deadlock with
2469          * hwrng internal locking. It's not needed to take
2470          * wl->mutex here, anyway. */
2471
2472         spin_lock_irqsave(&wl->irq_lock, flags);
2473         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2474         spin_unlock_irqrestore(&wl->irq_lock, flags);
2475
2476         return (sizeof(u16));
2477 }
2478
2479 static void b43_rng_exit(struct b43_wl *wl)
2480 {
2481         if (wl->rng_initialized)
2482                 hwrng_unregister(&wl->rng);
2483 }
2484
2485 static int b43_rng_init(struct b43_wl *wl)
2486 {
2487         int err;
2488
2489         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2490                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2491         wl->rng.name = wl->rng_name;
2492         wl->rng.data_read = b43_rng_read;
2493         wl->rng.priv = (unsigned long)wl;
2494         wl->rng_initialized = 1;
2495         err = hwrng_register(&wl->rng);
2496         if (err) {
2497                 wl->rng_initialized = 0;
2498                 b43err(wl, "Failed to register the random "
2499                        "number generator (%d)\n", err);
2500         }
2501
2502         return err;
2503 }
2504
2505 static int b43_op_tx(struct ieee80211_hw *hw,
2506                      struct sk_buff *skb,
2507                      struct ieee80211_tx_control *ctl)
2508 {
2509         struct b43_wl *wl = hw_to_b43_wl(hw);
2510         struct b43_wldev *dev = wl->current_dev;
2511         int err = -ENODEV;
2512
2513         if (unlikely(!dev))
2514                 goto out;
2515         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2516                 goto out;
2517         /* DMA-TX is done without a global lock. */
2518         err = b43_dma_tx(dev, skb, ctl);
2519 out:
2520         if (unlikely(err))
2521                 return NETDEV_TX_BUSY;
2522         return NETDEV_TX_OK;
2523 }
2524
2525 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2526                           int queue,
2527                           const struct ieee80211_tx_queue_params *params)
2528 {
2529         return 0;
2530 }
2531
2532 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2533                                struct ieee80211_tx_queue_stats *stats)
2534 {
2535         struct b43_wl *wl = hw_to_b43_wl(hw);
2536         struct b43_wldev *dev = wl->current_dev;
2537         unsigned long flags;
2538         int err = -ENODEV;
2539
2540         if (!dev)
2541                 goto out;
2542         spin_lock_irqsave(&wl->irq_lock, flags);
2543         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2544                 b43_dma_get_tx_stats(dev, stats);
2545                 err = 0;
2546         }
2547         spin_unlock_irqrestore(&wl->irq_lock, flags);
2548 out:
2549         return err;
2550 }
2551
2552 static int b43_op_get_stats(struct ieee80211_hw *hw,
2553                             struct ieee80211_low_level_stats *stats)
2554 {
2555         struct b43_wl *wl = hw_to_b43_wl(hw);
2556         unsigned long flags;
2557
2558         spin_lock_irqsave(&wl->irq_lock, flags);
2559         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2560         spin_unlock_irqrestore(&wl->irq_lock, flags);
2561
2562         return 0;
2563 }
2564
2565 static const char *phymode_to_string(unsigned int phymode)
2566 {
2567         switch (phymode) {
2568         case B43_PHYMODE_A:
2569                 return "A";
2570         case B43_PHYMODE_B:
2571                 return "B";
2572         case B43_PHYMODE_G:
2573                 return "G";
2574         default:
2575                 B43_WARN_ON(1);
2576         }
2577         return "";
2578 }
2579
2580 static int find_wldev_for_phymode(struct b43_wl *wl,
2581                                   unsigned int phymode,
2582                                   struct b43_wldev **dev, bool * gmode)
2583 {
2584         struct b43_wldev *d;
2585
2586         list_for_each_entry(d, &wl->devlist, list) {
2587                 if (d->phy.possible_phymodes & phymode) {
2588                         /* Ok, this device supports the PHY-mode.
2589                          * Now figure out how the gmode bit has to be
2590                          * set to support it. */
2591                         if (phymode == B43_PHYMODE_A)
2592                                 *gmode = 0;
2593                         else
2594                                 *gmode = 1;
2595                         *dev = d;
2596
2597                         return 0;
2598                 }
2599         }
2600
2601         return -ESRCH;
2602 }
2603
2604 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2605 {
2606         struct ssb_device *sdev = dev->dev;
2607         u32 tmslow;
2608
2609         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2610         tmslow &= ~B43_TMSLOW_GMODE;
2611         tmslow |= B43_TMSLOW_PHYRESET;
2612         tmslow |= SSB_TMSLOW_FGC;
2613         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2614         msleep(1);
2615
2616         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2617         tmslow &= ~SSB_TMSLOW_FGC;
2618         tmslow |= B43_TMSLOW_PHYRESET;
2619         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2620         msleep(1);
2621 }
2622
2623 /* Expects wl->mutex locked */
2624 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2625 {
2626         struct b43_wldev *up_dev;
2627         struct b43_wldev *down_dev;
2628         int err;
2629         bool gmode = 0;
2630         int prev_status;
2631
2632         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2633         if (err) {
2634                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2635                        phymode_to_string(new_mode));
2636                 return err;
2637         }
2638         if ((up_dev == wl->current_dev) &&
2639             (!!wl->current_dev->phy.gmode == !!gmode)) {
2640                 /* This device is already running. */
2641                 return 0;
2642         }
2643         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2644                phymode_to_string(new_mode));
2645         down_dev = wl->current_dev;
2646
2647         prev_status = b43_status(down_dev);
2648         /* Shutdown the currently running core. */
2649         if (prev_status >= B43_STAT_STARTED)
2650                 b43_wireless_core_stop(down_dev);
2651         if (prev_status >= B43_STAT_INITIALIZED)
2652                 b43_wireless_core_exit(down_dev);
2653
2654         if (down_dev != up_dev) {
2655                 /* We switch to a different core, so we put PHY into
2656                  * RESET on the old core. */
2657                 b43_put_phy_into_reset(down_dev);
2658         }
2659
2660         /* Now start the new core. */
2661         up_dev->phy.gmode = gmode;
2662         if (prev_status >= B43_STAT_INITIALIZED) {
2663                 err = b43_wireless_core_init(up_dev);
2664                 if (err) {
2665                         b43err(wl, "Fatal: Could not initialize device for "
2666                                "newly selected %s-PHY mode\n",
2667                                phymode_to_string(new_mode));
2668                         goto init_failure;
2669                 }
2670         }
2671         if (prev_status >= B43_STAT_STARTED) {
2672                 err = b43_wireless_core_start(up_dev);
2673                 if (err) {
2674                         b43err(wl, "Fatal: Coult not start device for "
2675                                "newly selected %s-PHY mode\n",
2676                                phymode_to_string(new_mode));
2677                         b43_wireless_core_exit(up_dev);
2678                         goto init_failure;
2679                 }
2680         }
2681         B43_WARN_ON(b43_status(up_dev) != prev_status);
2682
2683         wl->current_dev = up_dev;
2684
2685         return 0;
2686       init_failure:
2687         /* Whoops, failed to init the new core. No core is operating now. */
2688         wl->current_dev = NULL;
2689         return err;
2690 }
2691
2692 /* Check if the use of the antenna that ieee80211 told us to
2693  * use is possible. This will fall back to DEFAULT.
2694  * "antenna_nr" is the antenna identifier we got from ieee80211. */
2695 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2696                                   u8 antenna_nr)
2697 {
2698         u8 antenna_mask;
2699
2700         if (antenna_nr == 0) {
2701                 /* Zero means "use default antenna". That's always OK. */
2702                 return 0;
2703         }
2704
2705         /* Get the mask of available antennas. */
2706         if (dev->phy.gmode)
2707                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2708         else
2709                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2710
2711         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2712                 /* This antenna is not available. Fall back to default. */
2713                 return 0;
2714         }
2715
2716         return antenna_nr;
2717 }
2718
2719 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2720 {
2721         antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2722         switch (antenna) {
2723         case 0:         /* default/diversity */
2724                 return B43_ANTENNA_DEFAULT;
2725         case 1:         /* Antenna 0 */
2726                 return B43_ANTENNA0;
2727         case 2:         /* Antenna 1 */
2728                 return B43_ANTENNA1;
2729         default:
2730                 return B43_ANTENNA_DEFAULT;
2731         }
2732 }
2733
2734 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2735 {
2736         struct b43_wl *wl = hw_to_b43_wl(hw);
2737         struct b43_wldev *dev;
2738         struct b43_phy *phy;
2739         unsigned long flags;
2740         unsigned int new_phymode = 0xFFFF;
2741         int antenna;
2742         int err = 0;
2743         u32 savedirqs;
2744
2745         mutex_lock(&wl->mutex);
2746
2747         /* Switch the PHY mode (if necessary). */
2748         switch (conf->phymode) {
2749         case MODE_IEEE80211A:
2750                 new_phymode = B43_PHYMODE_A;
2751                 break;
2752         case MODE_IEEE80211B:
2753                 new_phymode = B43_PHYMODE_B;
2754                 break;
2755         case MODE_IEEE80211G:
2756                 new_phymode = B43_PHYMODE_G;
2757                 break;
2758         default:
2759                 B43_WARN_ON(1);
2760         }
2761         err = b43_switch_phymode(wl, new_phymode);
2762         if (err)
2763                 goto out_unlock_mutex;
2764         dev = wl->current_dev;
2765         phy = &dev->phy;
2766
2767         /* Disable IRQs while reconfiguring the device.
2768          * This makes it possible to drop the spinlock throughout
2769          * the reconfiguration process. */
2770         spin_lock_irqsave(&wl->irq_lock, flags);
2771         if (b43_status(dev) < B43_STAT_STARTED) {
2772                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2773                 goto out_unlock_mutex;
2774         }
2775         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2776         spin_unlock_irqrestore(&wl->irq_lock, flags);
2777         b43_synchronize_irq(dev);
2778
2779         /* Switch to the requested channel.
2780          * The firmware takes care of races with the TX handler. */
2781         if (conf->channel_val != phy->channel)
2782                 b43_radio_selectchannel(dev, conf->channel_val, 0);
2783
2784         /* Enable/Disable ShortSlot timing. */
2785         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2786             dev->short_slot) {
2787                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2788                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2789                         b43_short_slot_timing_enable(dev);
2790                 else
2791                         b43_short_slot_timing_disable(dev);
2792         }
2793
2794         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2795
2796         /* Adjust the desired TX power level. */
2797         if (conf->power_level != 0) {
2798                 if (conf->power_level != phy->power_level) {
2799                         phy->power_level = conf->power_level;
2800                         b43_phy_xmitpower(dev);
2801                 }
2802         }
2803
2804         /* Antennas for RX and management frame TX. */
2805         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2806         b43_mgmtframe_txantenna(dev, antenna);
2807         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2808         b43_set_rx_antenna(dev, antenna);
2809
2810         /* Update templates for AP mode. */
2811         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2812                 b43_set_beacon_int(dev, conf->beacon_int);
2813
2814         if (!!conf->radio_enabled != phy->radio_on) {
2815                 if (conf->radio_enabled) {
2816                         b43_radio_turn_on(dev);
2817                         b43info(dev->wl, "Radio turned on by software\n");
2818                         if (!dev->radio_hw_enable) {
2819                                 b43info(dev->wl, "The hardware RF-kill button "
2820                                         "still turns the radio physically off. "
2821                                         "Press the button to turn it on.\n");
2822                         }
2823                 } else {
2824                         b43_radio_turn_off(dev, 0);
2825                         b43info(dev->wl, "Radio turned off by software\n");
2826                 }
2827         }
2828
2829         spin_lock_irqsave(&wl->irq_lock, flags);
2830         b43_interrupt_enable(dev, savedirqs);
2831         mmiowb();
2832         spin_unlock_irqrestore(&wl->irq_lock, flags);
2833       out_unlock_mutex:
2834         mutex_unlock(&wl->mutex);
2835
2836         return err;
2837 }
2838
2839 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2840                            const u8 *local_addr, const u8 *addr,
2841                            struct ieee80211_key_conf *key)
2842 {
2843         struct b43_wl *wl = hw_to_b43_wl(hw);
2844         struct b43_wldev *dev;
2845         unsigned long flags;
2846         u8 algorithm;
2847         u8 index;
2848         int err;
2849         DECLARE_MAC_BUF(mac);
2850
2851         if (modparam_nohwcrypt)
2852                 return -ENOSPC; /* User disabled HW-crypto */
2853
2854         mutex_lock(&wl->mutex);
2855         spin_lock_irqsave(&wl->irq_lock, flags);
2856
2857         dev = wl->current_dev;
2858         err = -ENODEV;
2859         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2860                 goto out_unlock;
2861
2862         err = -EINVAL;
2863         switch (key->alg) {
2864         case ALG_WEP:
2865                 if (key->keylen == 5)
2866                         algorithm = B43_SEC_ALGO_WEP40;
2867                 else
2868                         algorithm = B43_SEC_ALGO_WEP104;
2869                 break;
2870         case ALG_TKIP:
2871                 algorithm = B43_SEC_ALGO_TKIP;
2872                 break;
2873         case ALG_CCMP:
2874                 algorithm = B43_SEC_ALGO_AES;
2875                 break;
2876         default:
2877                 B43_WARN_ON(1);
2878                 goto out_unlock;
2879         }
2880         index = (u8) (key->keyidx);
2881         if (index > 3)
2882                 goto out_unlock;
2883
2884         switch (cmd) {
2885         case SET_KEY:
2886                 if (algorithm == B43_SEC_ALGO_TKIP) {
2887                         /* FIXME: No TKIP hardware encryption for now. */
2888                         err = -EOPNOTSUPP;
2889                         goto out_unlock;
2890                 }
2891
2892                 if (is_broadcast_ether_addr(addr)) {
2893                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2894                         err = b43_key_write(dev, index, algorithm,
2895                                             key->key, key->keylen, NULL, key);
2896                 } else {
2897                         /*
2898                          * either pairwise key or address is 00:00:00:00:00:00
2899                          * for transmit-only keys
2900                          */
2901                         err = b43_key_write(dev, -1, algorithm,
2902                                             key->key, key->keylen, addr, key);
2903                 }
2904                 if (err)
2905                         goto out_unlock;
2906
2907                 if (algorithm == B43_SEC_ALGO_WEP40 ||
2908                     algorithm == B43_SEC_ALGO_WEP104) {
2909                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2910                 } else {
2911                         b43_hf_write(dev,
2912                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2913                 }
2914                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2915                 break;
2916         case DISABLE_KEY: {
2917                 err = b43_key_clear(dev, key->hw_key_idx);
2918                 if (err)
2919                         goto out_unlock;
2920                 break;
2921         }
2922         default:
2923                 B43_WARN_ON(1);
2924         }
2925 out_unlock:
2926         spin_unlock_irqrestore(&wl->irq_lock, flags);
2927         mutex_unlock(&wl->mutex);
2928         if (!err) {
2929                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2930                        "mac: %s\n",
2931                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2932                        print_mac(mac, addr));
2933         }
2934         return err;
2935 }
2936
2937 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2938                                     unsigned int changed, unsigned int *fflags,
2939                                     int mc_count, struct dev_addr_list *mc_list)
2940 {
2941         struct b43_wl *wl = hw_to_b43_wl(hw);
2942         struct b43_wldev *dev = wl->current_dev;
2943         unsigned long flags;
2944
2945         if (!dev) {
2946                 *fflags = 0;
2947                 return;
2948         }
2949
2950         spin_lock_irqsave(&wl->irq_lock, flags);
2951         *fflags &= FIF_PROMISC_IN_BSS |
2952                   FIF_ALLMULTI |
2953                   FIF_FCSFAIL |
2954                   FIF_PLCPFAIL |
2955                   FIF_CONTROL |
2956                   FIF_OTHER_BSS |
2957                   FIF_BCN_PRBRESP_PROMISC;
2958
2959         changed &= FIF_PROMISC_IN_BSS |
2960                    FIF_ALLMULTI |
2961                    FIF_FCSFAIL |
2962                    FIF_PLCPFAIL |
2963                    FIF_CONTROL |
2964                    FIF_OTHER_BSS |
2965                    FIF_BCN_PRBRESP_PROMISC;
2966
2967         wl->filter_flags = *fflags;
2968
2969         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2970                 b43_adjust_opmode(dev);
2971         spin_unlock_irqrestore(&wl->irq_lock, flags);
2972 }
2973
2974 static int b43_op_config_interface(struct ieee80211_hw *hw,
2975                                    struct ieee80211_vif *vif,
2976                                    struct ieee80211_if_conf *conf)
2977 {
2978         struct b43_wl *wl = hw_to_b43_wl(hw);
2979         struct b43_wldev *dev = wl->current_dev;
2980         unsigned long flags;
2981
2982         if (!dev)
2983                 return -ENODEV;
2984         mutex_lock(&wl->mutex);
2985         spin_lock_irqsave(&wl->irq_lock, flags);
2986         B43_WARN_ON(wl->vif != vif);
2987         if (conf->bssid)
2988                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2989         else
2990                 memset(wl->bssid, 0, ETH_ALEN);
2991         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2992                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2993                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2994                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2995                         if (conf->beacon)
2996                                 b43_update_templates(wl, conf->beacon);
2997                 }
2998                 b43_write_mac_bssid_templates(dev);
2999         }
3000         spin_unlock_irqrestore(&wl->irq_lock, flags);
3001         mutex_unlock(&wl->mutex);
3002
3003         return 0;
3004 }
3005
3006 /* Locking: wl->mutex */
3007 static void b43_wireless_core_stop(struct b43_wldev *dev)
3008 {
3009         struct b43_wl *wl = dev->wl;
3010         unsigned long flags;
3011
3012         if (b43_status(dev) < B43_STAT_STARTED)
3013                 return;
3014
3015         /* Disable and sync interrupts. We must do this before than
3016          * setting the status to INITIALIZED, as the interrupt handler
3017          * won't care about IRQs then. */
3018         spin_lock_irqsave(&wl->irq_lock, flags);
3019         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3020         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3021         spin_unlock_irqrestore(&wl->irq_lock, flags);
3022         b43_synchronize_irq(dev);
3023
3024         b43_set_status(dev, B43_STAT_INITIALIZED);
3025
3026         mutex_unlock(&wl->mutex);
3027         /* Must unlock as it would otherwise deadlock. No races here.
3028          * Cancel the possibly running self-rearming periodic work. */
3029         cancel_delayed_work_sync(&dev->periodic_work);
3030         mutex_lock(&wl->mutex);
3031
3032         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
3033
3034         b43_mac_suspend(dev);
3035         free_irq(dev->dev->irq, dev);
3036         b43dbg(wl, "Wireless interface stopped\n");
3037 }
3038
3039 /* Locking: wl->mutex */
3040 static int b43_wireless_core_start(struct b43_wldev *dev)
3041 {
3042         int err;
3043
3044         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3045
3046         drain_txstatus_queue(dev);
3047         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3048                           IRQF_SHARED, KBUILD_MODNAME, dev);
3049         if (err) {
3050                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3051                 goto out;
3052         }
3053
3054         /* We are ready to run. */
3055         b43_set_status(dev, B43_STAT_STARTED);
3056
3057         /* Start data flow (TX/RX). */
3058         b43_mac_enable(dev);
3059         b43_interrupt_enable(dev, dev->irq_savedstate);
3060         ieee80211_start_queues(dev->wl->hw);
3061
3062         /* Start maintainance work */
3063         b43_periodic_tasks_setup(dev);
3064
3065         b43dbg(dev->wl, "Wireless interface started\n");
3066       out:
3067         return err;
3068 }
3069
3070 /* Get PHY and RADIO versioning numbers */
3071 static int b43_phy_versioning(struct b43_wldev *dev)
3072 {
3073         struct b43_phy *phy = &dev->phy;
3074         u32 tmp;
3075         u8 analog_type;
3076         u8 phy_type;
3077         u8 phy_rev;
3078         u16 radio_manuf;
3079         u16 radio_ver;
3080         u16 radio_rev;
3081         int unsupported = 0;
3082
3083         /* Get PHY versioning */
3084         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3085         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3086         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3087         phy_rev = (tmp & B43_PHYVER_VERSION);
3088         switch (phy_type) {
3089         case B43_PHYTYPE_A:
3090                 if (phy_rev >= 4)
3091                         unsupported = 1;
3092                 break;
3093         case B43_PHYTYPE_B:
3094                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3095                     && phy_rev != 7)
3096                         unsupported = 1;
3097                 break;
3098         case B43_PHYTYPE_G:
3099                 if (phy_rev > 9)
3100                         unsupported = 1;
3101                 break;
3102 #ifdef CONFIG_B43_NPHY
3103         case B43_PHYTYPE_N:
3104                 if (phy_rev > 1)
3105                         unsupported = 1;
3106                 break;
3107 #endif
3108         default:
3109                 unsupported = 1;
3110         };
3111         if (unsupported) {
3112                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3113                        "(Analog %u, Type %u, Revision %u)\n",
3114                        analog_type, phy_type, phy_rev);
3115                 return -EOPNOTSUPP;
3116         }
3117         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3118                analog_type, phy_type, phy_rev);
3119
3120         /* Get RADIO versioning */
3121         if (dev->dev->bus->chip_id == 0x4317) {
3122                 if (dev->dev->bus->chip_rev == 0)
3123                         tmp = 0x3205017F;
3124                 else if (dev->dev->bus->chip_rev == 1)
3125                         tmp = 0x4205017F;
3126                 else
3127                         tmp = 0x5205017F;
3128         } else {
3129                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3130                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3131                 tmp <<= 16;
3132                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3133                 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3134         }
3135         radio_manuf = (tmp & 0x00000FFF);
3136         radio_ver = (tmp & 0x0FFFF000) >> 12;
3137         radio_rev = (tmp & 0xF0000000) >> 28;
3138         if (radio_manuf != 0x17F /* Broadcom */)
3139                 unsupported = 1;
3140         switch (phy_type) {
3141         case B43_PHYTYPE_A:
3142                 if (radio_ver != 0x2060)
3143                         unsupported = 1;
3144                 if (radio_rev != 1)
3145                         unsupported = 1;
3146                 if (radio_manuf != 0x17F)
3147                         unsupported = 1;
3148                 break;
3149         case B43_PHYTYPE_B:
3150                 if ((radio_ver & 0xFFF0) != 0x2050)
3151                         unsupported = 1;
3152                 break;
3153         case B43_PHYTYPE_G:
3154                 if (radio_ver != 0x2050)
3155                         unsupported = 1;
3156                 break;
3157         case B43_PHYTYPE_N:
3158                 if (radio_ver != 5)
3159                         unsupported = 1;
3160                 break;
3161         default:
3162                 B43_WARN_ON(1);
3163         }
3164         if (unsupported) {
3165                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3166                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3167                        radio_manuf, radio_ver, radio_rev);
3168                 return -EOPNOTSUPP;
3169         }
3170         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3171                radio_manuf, radio_ver, radio_rev);
3172
3173         phy->radio_manuf = radio_manuf;
3174         phy->radio_ver = radio_ver;
3175         phy->radio_rev = radio_rev;
3176
3177         phy->analog = analog_type;
3178         phy->type = phy_type;
3179         phy->rev = phy_rev;
3180
3181         return 0;
3182 }
3183
3184 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3185                                       struct b43_phy *phy)
3186 {
3187         struct b43_txpower_lo_control *lo;
3188         int i;
3189
3190         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3191         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3192
3193         phy->aci_enable = 0;
3194         phy->aci_wlan_automatic = 0;
3195         phy->aci_hw_rssi = 0;
3196
3197         phy->radio_off_context.valid = 0;
3198
3199         lo = phy->lo_control;
3200         if (lo) {
3201                 memset(lo, 0, sizeof(*(phy->lo_control)));
3202                 lo->rebuild = 1;
3203                 lo->tx_bias = 0xFF;
3204         }
3205         phy->max_lb_gain = 0;
3206         phy->trsw_rx_gain = 0;
3207         phy->txpwr_offset = 0;
3208
3209         /* NRSSI */
3210         phy->nrssislope = 0;
3211         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3212                 phy->nrssi[i] = -1000;
3213         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3214                 phy->nrssi_lt[i] = i;
3215
3216         phy->lofcal = 0xFFFF;
3217         phy->initval = 0xFFFF;
3218
3219         phy->interfmode = B43_INTERFMODE_NONE;
3220         phy->channel = 0xFF;
3221
3222         phy->hardware_power_control = !!modparam_hwpctl;
3223
3224         /* PHY TX errors counter. */
3225         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3226
3227         /* OFDM-table address caching. */
3228         phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3229 }
3230
3231 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3232 {
3233         dev->dfq_valid = 0;
3234
3235         /* Assume the radio is enabled. If it's not enabled, the state will
3236          * immediately get fixed on the first periodic work run. */
3237         dev->radio_hw_enable = 1;
3238
3239         /* Stats */
3240         memset(&dev->stats, 0, sizeof(dev->stats));
3241
3242         setup_struct_phy_for_init(dev, &dev->phy);
3243
3244         /* IRQ related flags */
3245         dev->irq_reason = 0;
3246         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3247         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3248
3249         dev->mac_suspended = 1;
3250
3251         /* Noise calculation context */
3252         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3253 }
3254
3255 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3256 {
3257         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3258         u32 hf;
3259
3260         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3261                 return;
3262         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3263                 return;
3264
3265         hf = b43_hf_read(dev);
3266         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3267                 hf |= B43_HF_BTCOEXALT;
3268         else
3269                 hf |= B43_HF_BTCOEX;
3270         b43_hf_write(dev, hf);
3271         //TODO
3272 }
3273
3274 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3275 {                               //TODO
3276 }
3277
3278 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3279 {
3280 #ifdef CONFIG_SSB_DRIVER_PCICORE
3281         struct ssb_bus *bus = dev->dev->bus;
3282         u32 tmp;
3283
3284         if (bus->pcicore.dev &&
3285             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3286             bus->pcicore.dev->id.revision <= 5) {
3287                 /* IMCFGLO timeouts workaround. */
3288                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3289                 tmp &= ~SSB_IMCFGLO_REQTO;
3290                 tmp &= ~SSB_IMCFGLO_SERTO;
3291                 switch (bus->bustype) {
3292                 case SSB_BUSTYPE_PCI:
3293                 case SSB_BUSTYPE_PCMCIA:
3294                         tmp |= 0x32;
3295                         break;
3296                 case SSB_BUSTYPE_SSB:
3297                         tmp |= 0x53;
3298                         break;
3299                 }
3300                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3301         }
3302 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3303 }
3304
3305 /* Write the short and long frame retry limit values. */
3306 static void b43_set_retry_limits(struct b43_wldev *dev,
3307                                  unsigned int short_retry,
3308                                  unsigned int long_retry)
3309 {
3310         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3311          * the chip-internal counter. */
3312         short_retry = min(short_retry, (unsigned int)0xF);
3313         long_retry = min(long_retry, (unsigned int)0xF);
3314
3315         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3316                         short_retry);
3317         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3318                         long_retry);
3319 }
3320
3321 /* Shutdown a wireless core */
3322 /* Locking: wl->mutex */
3323 static void b43_wireless_core_exit(struct b43_wldev *dev)
3324 {
3325         struct b43_phy *phy = &dev->phy;
3326
3327         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3328         if (b43_status(dev) != B43_STAT_INITIALIZED)
3329                 return;
3330         b43_set_status(dev, B43_STAT_UNINIT);
3331
3332         b43_leds_exit(dev);
3333         b43_rng_exit(dev->wl);
3334         b43_dma_free(dev);
3335         b43_chip_exit(dev);
3336         b43_radio_turn_off(dev, 1);
3337         b43_switch_analog(dev, 0);
3338         if (phy->dyn_tssi_tbl)
3339                 kfree(phy->tssi2dbm);
3340         kfree(phy->lo_control);
3341         phy->lo_control = NULL;
3342         if (dev->wl->current_beacon) {
3343                 dev_kfree_skb_any(dev->wl->current_beacon);
3344                 dev->wl->current_beacon = NULL;
3345         }
3346
3347         ssb_device_disable(dev->dev, 0);
3348         ssb_bus_may_powerdown(dev->dev->bus);
3349 }
3350
3351 /* Initialize a wireless core */
3352 static int b43_wireless_core_init(struct b43_wldev *dev)
3353 {
3354         struct b43_wl *wl = dev->wl;
3355         struct ssb_bus *bus = dev->dev->bus;
3356         struct ssb_sprom *sprom = &bus->sprom;
3357         struct b43_phy *phy = &dev->phy;
3358         int err;
3359         u32 hf, tmp;
3360
3361         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3362
3363         err = ssb_bus_powerup(bus, 0);
3364         if (err)
3365                 goto out;
3366         if (!ssb_device_is_enabled(dev->dev)) {
3367                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3368                 b43_wireless_core_reset(dev, tmp);
3369         }
3370
3371         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3372                 phy->lo_control =
3373                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3374                 if (!phy->lo_control) {
3375                         err = -ENOMEM;
3376                         goto err_busdown;
3377                 }
3378         }
3379         setup_struct_wldev_for_init(dev);
3380
3381         err = b43_phy_init_tssi2dbm_table(dev);
3382         if (err)
3383                 goto err_kfree_lo_control;
3384
3385         /* Enable IRQ routing to this device. */
3386         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3387
3388         b43_imcfglo_timeouts_workaround(dev);
3389         b43_bluetooth_coext_disable(dev);
3390         b43_phy_early_init(dev);
3391         err = b43_chip_init(dev);
3392         if (err)
3393                 goto err_kfree_tssitbl;
3394         b43_shm_write16(dev, B43_SHM_SHARED,
3395                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3396         hf = b43_hf_read(dev);
3397         if (phy->type == B43_PHYTYPE_G) {
3398                 hf |= B43_HF_SYMW;
3399                 if (phy->rev == 1)
3400                         hf |= B43_HF_GDCW;
3401                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3402                         hf |= B43_HF_OFDMPABOOST;
3403         } else if (phy->type == B43_PHYTYPE_B) {
3404                 hf |= B43_HF_SYMW;
3405                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3406                         hf &= ~B43_HF_GDCW;
3407         }
3408         b43_hf_write(dev, hf);
3409
3410         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3411                              B43_DEFAULT_LONG_RETRY_LIMIT);
3412         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3413         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3414
3415         /* Disable sending probe responses from firmware.
3416          * Setting the MaxTime to one usec will always trigger
3417          * a timeout, so we never send any probe resp.
3418          * A timeout of zero is infinite. */
3419         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3420
3421         b43_rate_memory_init(dev);
3422
3423         /* Minimum Contention Window */
3424         if (phy->type == B43_PHYTYPE_B) {
3425                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3426         } else {
3427                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3428         }
3429         /* Maximum Contention Window */
3430         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3431
3432         err = b43_dma_init(dev);
3433         if (err)
3434                 goto err_chip_exit;
3435         b43_qos_init(dev);
3436
3437 //FIXME
3438 #if 1
3439         b43_write16(dev, 0x0612, 0x0050);
3440         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3441         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3442 #endif
3443
3444         b43_bluetooth_coext_enable(dev);
3445
3446         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3447         memset(wl->bssid, 0, ETH_ALEN);
3448         memset(wl->mac_addr, 0, ETH_ALEN);
3449         b43_upload_card_macaddress(dev);
3450         b43_security_init(dev);
3451         b43_rng_init(wl);
3452
3453         b43_set_status(dev, B43_STAT_INITIALIZED);
3454
3455         b43_leds_init(dev);
3456 out:
3457         return err;
3458
3459       err_chip_exit:
3460         b43_chip_exit(dev);
3461       err_kfree_tssitbl:
3462         if (phy->dyn_tssi_tbl)
3463                 kfree(phy->tssi2dbm);
3464       err_kfree_lo_control:
3465         kfree(phy->lo_control);
3466         phy->lo_control = NULL;
3467       err_busdown:
3468         ssb_bus_may_powerdown(bus);
3469         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3470         return err;
3471 }
3472
3473 static int b43_op_add_interface(struct ieee80211_hw *hw,
3474                                 struct ieee80211_if_init_conf *conf)
3475 {
3476         struct b43_wl *wl = hw_to_b43_wl(hw);
3477         struct b43_wldev *dev;
3478         unsigned long flags;
3479         int err = -EOPNOTSUPP;
3480
3481         /* TODO: allow WDS/AP devices to coexist */
3482
3483         if (conf->type != IEEE80211_IF_TYPE_AP &&
3484             conf->type != IEEE80211_IF_TYPE_STA &&
3485             conf->type != IEEE80211_IF_TYPE_WDS &&
3486             conf->type != IEEE80211_IF_TYPE_IBSS)
3487                 return -EOPNOTSUPP;
3488
3489         mutex_lock(&wl->mutex);
3490         if (wl->operating)
3491                 goto out_mutex_unlock;
3492
3493         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3494
3495         dev = wl->current_dev;
3496         wl->operating = 1;
3497         wl->vif = conf->vif;
3498         wl->if_type = conf->type;
3499         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3500
3501         spin_lock_irqsave(&wl->irq_lock, flags);
3502         b43_adjust_opmode(dev);
3503         b43_upload_card_macaddress(dev);
3504         spin_unlock_irqrestore(&wl->irq_lock, flags);
3505
3506         err = 0;
3507  out_mutex_unlock:
3508         mutex_unlock(&wl->mutex);
3509
3510         return err;
3511 }
3512
3513 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3514                                     struct ieee80211_if_init_conf *conf)
3515 {
3516         struct b43_wl *wl = hw_to_b43_wl(hw);
3517         struct b43_wldev *dev = wl->current_dev;
3518         unsigned long flags;
3519
3520         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3521
3522         mutex_lock(&wl->mutex);
3523
3524         B43_WARN_ON(!wl->operating);
3525         B43_WARN_ON(wl->vif != conf->vif);
3526         wl->vif = NULL;
3527
3528         wl->operating = 0;
3529
3530         spin_lock_irqsave(&wl->irq_lock, flags);
3531         b43_adjust_opmode(dev);
3532         memset(wl->mac_addr, 0, ETH_ALEN);
3533         b43_upload_card_macaddress(dev);
3534         spin_unlock_irqrestore(&wl->irq_lock, flags);
3535
3536         mutex_unlock(&wl->mutex);
3537 }
3538
3539 static int b43_op_start(struct ieee80211_hw *hw)
3540 {
3541         struct b43_wl *wl = hw_to_b43_wl(hw);
3542         struct b43_wldev *dev = wl->current_dev;
3543         int did_init = 0;
3544         int err = 0;
3545
3546         /* First register RFkill.
3547          * LEDs that are registered later depend on it. */
3548         b43_rfkill_init(dev);
3549
3550         mutex_lock(&wl->mutex);
3551
3552         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3553                 err = b43_wireless_core_init(dev);
3554                 if (err)
3555                         goto out_mutex_unlock;
3556                 did_init = 1;
3557         }
3558
3559         if (b43_status(dev) < B43_STAT_STARTED) {
3560                 err = b43_wireless_core_start(dev);
3561                 if (err) {
3562                         if (did_init)
3563                                 b43_wireless_core_exit(dev);
3564                         goto out_mutex_unlock;
3565                 }
3566         }
3567
3568  out_mutex_unlock:
3569         mutex_unlock(&wl->mutex);
3570
3571         return err;
3572 }
3573
3574 static void b43_op_stop(struct ieee80211_hw *hw)
3575 {
3576         struct b43_wl *wl = hw_to_b43_wl(hw);
3577         struct b43_wldev *dev = wl->current_dev;
3578
3579         b43_rfkill_exit(dev);
3580
3581         mutex_lock(&wl->mutex);
3582         if (b43_status(dev) >= B43_STAT_STARTED)
3583                 b43_wireless_core_stop(dev);
3584         b43_wireless_core_exit(dev);
3585         mutex_unlock(&wl->mutex);
3586 }
3587
3588 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3589                                   u32 short_retry_limit, u32 long_retry_limit)
3590 {
3591         struct b43_wl *wl = hw_to_b43_wl(hw);
3592         struct b43_wldev *dev;
3593         int err = 0;
3594
3595         mutex_lock(&wl->mutex);
3596         dev = wl->current_dev;
3597         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3598                 err = -ENODEV;
3599                 goto out_unlock;
3600         }
3601         b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3602 out_unlock:
3603         mutex_unlock(&wl->mutex);
3604
3605         return err;
3606 }
3607
3608 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3609 {
3610         struct b43_wl *wl = hw_to_b43_wl(hw);
3611         struct sk_buff *beacon;
3612         unsigned long flags;
3613
3614         /* We could modify the existing beacon and set the aid bit in
3615          * the TIM field, but that would probably require resizing and
3616          * moving of data within the beacon template.
3617          * Simply request a new beacon and let mac80211 do the hard work. */
3618         beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3619         if (unlikely(!beacon))
3620                 return -ENOMEM;
3621         spin_lock_irqsave(&wl->irq_lock, flags);
3622         b43_update_templates(wl, beacon);
3623         spin_unlock_irqrestore(&wl->irq_lock, flags);
3624
3625         return 0;
3626 }
3627
3628 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3629                                      struct sk_buff *beacon,
3630                                      struct ieee80211_tx_control *ctl)
3631 {
3632         struct b43_wl *wl = hw_to_b43_wl(hw);
3633         unsigned long flags;
3634
3635         spin_lock_irqsave(&wl->irq_lock, flags);
3636         b43_update_templates(wl, beacon);
3637         spin_unlock_irqrestore(&wl->irq_lock, flags);
3638
3639         return 0;
3640 }
3641
3642 static const struct ieee80211_ops b43_hw_ops = {
3643         .tx                     = b43_op_tx,
3644         .conf_tx                = b43_op_conf_tx,
3645         .add_interface          = b43_op_add_interface,
3646         .remove_interface       = b43_op_remove_interface,
3647         .config                 = b43_op_config,
3648         .config_interface       = b43_op_config_interface,
3649         .configure_filter       = b43_op_configure_filter,
3650         .set_key                = b43_op_set_key,
3651         .get_stats              = b43_op_get_stats,
3652         .get_tx_stats           = b43_op_get_tx_stats,
3653         .start                  = b43_op_start,
3654         .stop                   = b43_op_stop,
3655         .set_retry_limit        = b43_op_set_retry_limit,
3656         .set_tim                = b43_op_beacon_set_tim,
3657         .beacon_update          = b43_op_ibss_beacon_update,
3658 };
3659
3660 /* Hard-reset the chip. Do not call this directly.
3661  * Use b43_controller_restart()
3662  */
3663 static void b43_chip_reset(struct work_struct *work)
3664 {
3665         struct b43_wldev *dev =
3666             container_of(work, struct b43_wldev, restart_work);
3667         struct b43_wl *wl = dev->wl;
3668         int err = 0;
3669         int prev_status;
3670
3671         mutex_lock(&wl->mutex);
3672
3673         prev_status = b43_status(dev);
3674         /* Bring the device down... */
3675         if (prev_status >= B43_STAT_STARTED)
3676                 b43_wireless_core_stop(dev);
3677         if (prev_status >= B43_STAT_INITIALIZED)
3678                 b43_wireless_core_exit(dev);
3679
3680         /* ...and up again. */
3681         if (prev_status >= B43_STAT_INITIALIZED) {
3682                 err = b43_wireless_core_init(dev);
3683                 if (err)
3684                         goto out;
3685         }
3686         if (prev_status >= B43_STAT_STARTED) {
3687                 err = b43_wireless_core_start(dev);
3688                 if (err) {
3689                         b43_wireless_core_exit(dev);
3690                         goto out;
3691                 }
3692         }
3693       out:
3694         mutex_unlock(&wl->mutex);
3695         if (err)
3696                 b43err(wl, "Controller restart FAILED\n");
3697         else
3698                 b43info(wl, "Controller restarted\n");
3699 }
3700
3701 static int b43_setup_modes(struct b43_wldev *dev,
3702                            bool have_2ghz_phy, bool have_5ghz_phy)
3703 {
3704         struct ieee80211_hw *hw = dev->wl->hw;
3705         struct ieee80211_hw_mode *mode;
3706         struct b43_phy *phy = &dev->phy;
3707         int err;
3708
3709         /* XXX: This function will go away soon, when mac80211
3710          *      band stuff is rewritten. So this is just a hack.
3711          *      For now we always claim GPHY mode, as there is no
3712          *      support for NPHY and APHY in the device, yet.
3713          *      This assumption is OK, as any B, N or A PHY will already
3714          *      have died a horrible sanity check death earlier. */
3715
3716         mode = &phy->hwmodes[0];
3717         mode->mode = MODE_IEEE80211G;
3718         mode->num_channels = b43_2ghz_chantable_size;
3719         mode->channels = b43_2ghz_chantable;
3720         mode->num_rates = b43_g_ratetable_size;
3721         mode->rates = b43_g_ratetable;
3722         err = ieee80211_register_hwmode(hw, mode);
3723         if (err)
3724                 return err;
3725         phy->possible_phymodes |= B43_PHYMODE_G;
3726
3727         return 0;
3728 }
3729
3730 static void b43_wireless_core_detach(struct b43_wldev *dev)
3731 {
3732         /* We release firmware that late to not be required to re-request
3733          * is all the time when we reinit the core. */
3734         b43_release_firmware(dev);
3735 }
3736
3737 static int b43_wireless_core_attach(struct b43_wldev *dev)
3738 {
3739         struct b43_wl *wl = dev->wl;
3740         struct ssb_bus *bus = dev->dev->bus;
3741         struct pci_dev *pdev = bus->host_pci;
3742         int err;
3743         bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3744         u32 tmp;
3745
3746         /* Do NOT do any device initialization here.
3747          * Do it in wireless_core_init() instead.
3748          * This function is for gathering basic information about the HW, only.
3749          * Also some structs may be set up here. But most likely you want to have
3750          * that in core_init(), too.
3751          */
3752
3753         err = ssb_bus_powerup(bus, 0);
3754         if (err) {
3755                 b43err(wl, "Bus powerup failed\n");
3756                 goto out;
3757         }
3758         /* Get the PHY type. */
3759         if (dev->dev->id.revision >= 5) {
3760                 u32 tmshigh;
3761
3762                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3763                 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3764                 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3765         } else
3766                 B43_WARN_ON(1);
3767
3768         dev->phy.gmode = have_2ghz_phy;
3769         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3770         b43_wireless_core_reset(dev, tmp);
3771
3772         err = b43_phy_versioning(dev);
3773         if (err)
3774                 goto err_powerdown;
3775         /* Check if this device supports multiband. */
3776         if (!pdev ||
3777             (pdev->device != 0x4312 &&
3778              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3779                 /* No multiband support. */
3780                 have_2ghz_phy = 0;
3781                 have_5ghz_phy = 0;
3782                 switch (dev->phy.type) {
3783                 case B43_PHYTYPE_A:
3784                         have_5ghz_phy = 1;
3785                         break;
3786                 case B43_PHYTYPE_G:
3787                 case B43_PHYTYPE_N:
3788                         have_2ghz_phy = 1;
3789                         break;
3790                 default:
3791                         B43_WARN_ON(1);
3792                 }
3793         }
3794         if (dev->phy.type == B43_PHYTYPE_A) {
3795                 /* FIXME */
3796                 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3797                 err = -EOPNOTSUPP;
3798                 goto err_powerdown;
3799         }
3800         dev->phy.gmode = have_2ghz_phy;
3801         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3802         b43_wireless_core_reset(dev, tmp);
3803
3804         err = b43_validate_chipaccess(dev);
3805         if (err)
3806                 goto err_powerdown;
3807         err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3808         if (err)
3809                 goto err_powerdown;
3810
3811         /* Now set some default "current_dev" */
3812         if (!wl->current_dev)
3813                 wl->current_dev = dev;
3814         INIT_WORK(&dev->restart_work, b43_chip_reset);
3815
3816         b43_radio_turn_off(dev, 1);
3817         b43_switch_analog(dev, 0);
3818         ssb_device_disable(dev->dev, 0);
3819         ssb_bus_may_powerdown(bus);
3820
3821 out:
3822         return err;
3823
3824 err_powerdown:
3825         ssb_bus_may_powerdown(bus);
3826         return err;
3827 }
3828
3829 static void b43_one_core_detach(struct ssb_device *dev)
3830 {
3831         struct b43_wldev *wldev;
3832         struct b43_wl *wl;
3833
3834         wldev = ssb_get_drvdata(dev);
3835         wl = wldev->wl;
3836         cancel_work_sync(&wldev->restart_work);
3837         b43_debugfs_remove_device(wldev);
3838         b43_wireless_core_detach(wldev);
3839         list_del(&wldev->list);
3840         wl->nr_devs--;
3841         ssb_set_drvdata(dev, NULL);
3842         kfree(wldev);
3843 }
3844
3845 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3846 {
3847         struct b43_wldev *wldev;
3848         struct pci_dev *pdev;
3849         int err = -ENOMEM;
3850
3851         if (!list_empty(&wl->devlist)) {
3852                 /* We are not the first core on this chip. */
3853                 pdev = dev->bus->host_pci;
3854                 /* Only special chips support more than one wireless
3855                  * core, although some of the other chips have more than
3856                  * one wireless core as well. Check for this and
3857                  * bail out early.
3858                  */
3859                 if (!pdev ||
3860                     ((pdev->device != 0x4321) &&
3861                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3862                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3863                         return -ENODEV;
3864                 }
3865         }
3866
3867         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3868         if (!wldev)
3869                 goto out;
3870
3871         wldev->dev = dev;
3872         wldev->wl = wl;
3873         b43_set_status(wldev, B43_STAT_UNINIT);
3874         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3875         tasklet_init(&wldev->isr_tasklet,
3876                      (void (*)(unsigned long))b43_interrupt_tasklet,
3877                      (unsigned long)wldev);
3878         INIT_LIST_HEAD(&wldev->list);
3879
3880         err = b43_wireless_core_attach(wldev);
3881         if (err)
3882                 goto err_kfree_wldev;
3883
3884         list_add(&wldev->list, &wl->devlist);
3885         wl->nr_devs++;
3886         ssb_set_drvdata(dev, wldev);
3887         b43_debugfs_add_device(wldev);
3888
3889       out:
3890         return err;
3891
3892       err_kfree_wldev:
3893         kfree(wldev);
3894         return err;
3895 }
3896
3897 static void b43_sprom_fixup(struct ssb_bus *bus)
3898 {
3899         /* boardflags workarounds */
3900         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3901             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3902                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3903         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3904             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3905                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3906 }
3907
3908 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3909 {
3910         struct ieee80211_hw *hw = wl->hw;
3911
3912         ssb_set_devtypedata(dev, NULL);
3913         ieee80211_free_hw(hw);
3914 }
3915
3916 static int b43_wireless_init(struct ssb_device *dev)
3917 {
3918         struct ssb_sprom *sprom = &dev->bus->sprom;
3919         struct ieee80211_hw *hw;
3920         struct b43_wl *wl;
3921         int err = -ENOMEM;
3922
3923         b43_sprom_fixup(dev->bus);
3924
3925         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3926         if (!hw) {
3927                 b43err(NULL, "Could not allocate ieee80211 device\n");
3928                 goto out;
3929         }
3930
3931         /* fill hw info */
3932         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3933                     IEEE80211_HW_RX_INCLUDES_FCS;
3934         hw->max_signal = 100;
3935         hw->max_rssi = -110;
3936         hw->max_noise = -110;
3937         hw->queues = 1;         /* FIXME: hardware has more queues */
3938         SET_IEEE80211_DEV(hw, dev->dev);
3939         if (is_valid_ether_addr(sprom->et1mac))
3940                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3941         else
3942                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3943
3944         /* Get and initialize struct b43_wl */
3945         wl = hw_to_b43_wl(hw);
3946         memset(wl, 0, sizeof(*wl));
3947         wl->hw = hw;
3948         spin_lock_init(&wl->irq_lock);
3949         spin_lock_init(&wl->leds_lock);
3950         spin_lock_init(&wl->shm_lock);
3951         mutex_init(&wl->mutex);
3952         INIT_LIST_HEAD(&wl->devlist);
3953
3954         ssb_set_devtypedata(dev, wl);
3955         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3956         err = 0;
3957       out:
3958         return err;
3959 }
3960
3961 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3962 {
3963         struct b43_wl *wl;
3964         int err;
3965         int first = 0;
3966
3967         wl = ssb_get_devtypedata(dev);
3968         if (!wl) {
3969                 /* Probing the first core. Must setup common struct b43_wl */
3970                 first = 1;
3971                 err = b43_wireless_init(dev);
3972                 if (err)
3973                         goto out;
3974                 wl = ssb_get_devtypedata(dev);
3975                 B43_WARN_ON(!wl);
3976         }
3977         err = b43_one_core_attach(dev, wl);
3978         if (err)
3979                 goto err_wireless_exit;
3980
3981         if (first) {
3982                 err = ieee80211_register_hw(wl->hw);
3983                 if (err)
3984                         goto err_one_core_detach;
3985         }
3986
3987       out:
3988         return err;
3989
3990       err_one_core_detach:
3991         b43_one_core_detach(dev);
3992       err_wireless_exit:
3993         if (first)
3994                 b43_wireless_exit(dev, wl);
3995         return err;
3996 }
3997
3998 static void b43_remove(struct ssb_device *dev)
3999 {
4000         struct b43_wl *wl = ssb_get_devtypedata(dev);
4001         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4002
4003         B43_WARN_ON(!wl);
4004         if (wl->current_dev == wldev)
4005                 ieee80211_unregister_hw(wl->hw);
4006
4007         b43_one_core_detach(dev);
4008
4009         if (list_empty(&wl->devlist)) {
4010                 /* Last core on the chip unregistered.
4011                  * We can destroy common struct b43_wl.
4012                  */
4013                 b43_wireless_exit(dev, wl);
4014         }
4015 }
4016
4017 /* Perform a hardware reset. This can be called from any context. */
4018 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4019 {
4020         /* Must avoid requeueing, if we are in shutdown. */
4021         if (b43_status(dev) < B43_STAT_INITIALIZED)
4022                 return;
4023         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4024         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4025 }
4026
4027 #ifdef CONFIG_PM
4028
4029 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4030 {
4031         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4032         struct b43_wl *wl = wldev->wl;
4033
4034         b43dbg(wl, "Suspending...\n");
4035
4036         mutex_lock(&wl->mutex);
4037         wldev->suspend_init_status = b43_status(wldev);
4038         if (wldev->suspend_init_status >= B43_STAT_STARTED)
4039                 b43_wireless_core_stop(wldev);
4040         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4041                 b43_wireless_core_exit(wldev);
4042         mutex_unlock(&wl->mutex);
4043
4044         b43dbg(wl, "Device suspended.\n");
4045
4046         return 0;
4047 }
4048
4049 static int b43_resume(struct ssb_device *dev)
4050 {
4051         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4052         struct b43_wl *wl = wldev->wl;
4053         int err = 0;
4054
4055         b43dbg(wl, "Resuming...\n");
4056
4057         mutex_lock(&wl->mutex);
4058         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4059                 err = b43_wireless_core_init(wldev);
4060                 if (err) {
4061                         b43err(wl, "Resume failed at core init\n");
4062                         goto out;
4063                 }
4064         }
4065         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4066                 err = b43_wireless_core_start(wldev);
4067                 if (err) {
4068                         b43_wireless_core_exit(wldev);
4069                         b43err(wl, "Resume failed at core start\n");
4070                         goto out;
4071                 }
4072         }
4073         mutex_unlock(&wl->mutex);
4074
4075         b43dbg(wl, "Device resumed.\n");
4076       out:
4077         return err;
4078 }
4079
4080 #else /* CONFIG_PM */
4081 # define b43_suspend    NULL
4082 # define b43_resume     NULL
4083 #endif /* CONFIG_PM */
4084
4085 static struct ssb_driver b43_ssb_driver = {
4086         .name           = KBUILD_MODNAME,
4087         .id_table       = b43_ssb_tbl,
4088         .probe          = b43_probe,
4089         .remove         = b43_remove,
4090         .suspend        = b43_suspend,
4091         .resume         = b43_resume,
4092 };
4093
4094 static int __init b43_init(void)
4095 {
4096         int err;
4097
4098         b43_debugfs_init();
4099         err = b43_pcmcia_init();
4100         if (err)
4101                 goto err_dfs_exit;
4102         err = ssb_driver_register(&b43_ssb_driver);
4103         if (err)
4104                 goto err_pcmcia_exit;
4105
4106         return err;
4107
4108 err_pcmcia_exit:
4109         b43_pcmcia_exit();
4110 err_dfs_exit:
4111         b43_debugfs_exit();
4112         return err;
4113 }
4114
4115 static void __exit b43_exit(void)
4116 {
4117         ssb_driver_unregister(&b43_ssb_driver);
4118         b43_pcmcia_exit();
4119         b43_debugfs_exit();
4120 }
4121
4122 module_init(b43_init)
4123 module_exit(b43_exit)