3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/moduleparam.h>
37 #include <linux/if_arp.h>
38 #include <linux/etherdevice.h>
39 #include <linux/firmware.h>
40 #include <linux/wireless.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
61 #include <linux/mmc/sdio_func.h>
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_LICENSE("GPL");
70 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode5.fw");
76 MODULE_FIRMWARE("b43/ucode9.fw");
78 static int modparam_bad_frames_preempt;
79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt,
81 "enable(1) / disable(0) Bad Frames Preemption");
83 static char modparam_fwpostfix[16];
84 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
85 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87 static int modparam_hwpctl;
88 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
89 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91 static int modparam_nohwcrypt;
92 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
93 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95 static int modparam_hwtkip;
96 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
97 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99 static int modparam_qos = 1;
100 module_param_named(qos, modparam_qos, int, 0444);
101 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103 static int modparam_btcoex = 1;
104 module_param_named(btcoex, modparam_btcoex, int, 0444);
105 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
107 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
108 module_param_named(verbose, b43_modparam_verbose, int, 0644);
109 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111 static int b43_modparam_pio = B43_PIO_DEFAULT;
112 module_param_named(pio, b43_modparam_pio, int, 0644);
113 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
115 static const struct ssb_device_id b43_ssb_tbl[] = {
116 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
117 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
118 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
119 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
123 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
124 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
125 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
129 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
131 /* Channel and ratetables are shared for all devices.
132 * They can't be const, because ieee80211 puts some precalculated
133 * data in there. This data is the same for all devices, so we don't
134 * get concurrency issues */
135 #define RATETAB_ENT(_rateid, _flags) \
137 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
138 .hw_value = (_rateid), \
143 * NOTE: When changing this, sync with xmit.c's
144 * b43_plcp_get_bitrate_idx_* functions!
146 static struct ieee80211_rate __b43_ratetable[] = {
147 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
148 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
149 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
150 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
151 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
152 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
153 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
154 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
155 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
156 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
157 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
158 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
161 #define b43_a_ratetable (__b43_ratetable + 4)
162 #define b43_a_ratetable_size 8
163 #define b43_b_ratetable (__b43_ratetable + 0)
164 #define b43_b_ratetable_size 4
165 #define b43_g_ratetable (__b43_ratetable + 0)
166 #define b43_g_ratetable_size 12
168 #define CHAN4G(_channel, _freq, _flags) { \
169 .band = IEEE80211_BAND_2GHZ, \
170 .center_freq = (_freq), \
171 .hw_value = (_channel), \
173 .max_antenna_gain = 0, \
176 static struct ieee80211_channel b43_2ghz_chantable[] = {
194 #define CHAN5G(_channel, _flags) { \
195 .band = IEEE80211_BAND_5GHZ, \
196 .center_freq = 5000 + (5 * (_channel)), \
197 .hw_value = (_channel), \
199 .max_antenna_gain = 0, \
202 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
203 CHAN5G(32, 0), CHAN5G(34, 0),
204 CHAN5G(36, 0), CHAN5G(38, 0),
205 CHAN5G(40, 0), CHAN5G(42, 0),
206 CHAN5G(44, 0), CHAN5G(46, 0),
207 CHAN5G(48, 0), CHAN5G(50, 0),
208 CHAN5G(52, 0), CHAN5G(54, 0),
209 CHAN5G(56, 0), CHAN5G(58, 0),
210 CHAN5G(60, 0), CHAN5G(62, 0),
211 CHAN5G(64, 0), CHAN5G(66, 0),
212 CHAN5G(68, 0), CHAN5G(70, 0),
213 CHAN5G(72, 0), CHAN5G(74, 0),
214 CHAN5G(76, 0), CHAN5G(78, 0),
215 CHAN5G(80, 0), CHAN5G(82, 0),
216 CHAN5G(84, 0), CHAN5G(86, 0),
217 CHAN5G(88, 0), CHAN5G(90, 0),
218 CHAN5G(92, 0), CHAN5G(94, 0),
219 CHAN5G(96, 0), CHAN5G(98, 0),
220 CHAN5G(100, 0), CHAN5G(102, 0),
221 CHAN5G(104, 0), CHAN5G(106, 0),
222 CHAN5G(108, 0), CHAN5G(110, 0),
223 CHAN5G(112, 0), CHAN5G(114, 0),
224 CHAN5G(116, 0), CHAN5G(118, 0),
225 CHAN5G(120, 0), CHAN5G(122, 0),
226 CHAN5G(124, 0), CHAN5G(126, 0),
227 CHAN5G(128, 0), CHAN5G(130, 0),
228 CHAN5G(132, 0), CHAN5G(134, 0),
229 CHAN5G(136, 0), CHAN5G(138, 0),
230 CHAN5G(140, 0), CHAN5G(142, 0),
231 CHAN5G(144, 0), CHAN5G(145, 0),
232 CHAN5G(146, 0), CHAN5G(147, 0),
233 CHAN5G(148, 0), CHAN5G(149, 0),
234 CHAN5G(150, 0), CHAN5G(151, 0),
235 CHAN5G(152, 0), CHAN5G(153, 0),
236 CHAN5G(154, 0), CHAN5G(155, 0),
237 CHAN5G(156, 0), CHAN5G(157, 0),
238 CHAN5G(158, 0), CHAN5G(159, 0),
239 CHAN5G(160, 0), CHAN5G(161, 0),
240 CHAN5G(162, 0), CHAN5G(163, 0),
241 CHAN5G(164, 0), CHAN5G(165, 0),
242 CHAN5G(166, 0), CHAN5G(168, 0),
243 CHAN5G(170, 0), CHAN5G(172, 0),
244 CHAN5G(174, 0), CHAN5G(176, 0),
245 CHAN5G(178, 0), CHAN5G(180, 0),
246 CHAN5G(182, 0), CHAN5G(184, 0),
247 CHAN5G(186, 0), CHAN5G(188, 0),
248 CHAN5G(190, 0), CHAN5G(192, 0),
249 CHAN5G(194, 0), CHAN5G(196, 0),
250 CHAN5G(198, 0), CHAN5G(200, 0),
251 CHAN5G(202, 0), CHAN5G(204, 0),
252 CHAN5G(206, 0), CHAN5G(208, 0),
253 CHAN5G(210, 0), CHAN5G(212, 0),
254 CHAN5G(214, 0), CHAN5G(216, 0),
255 CHAN5G(218, 0), CHAN5G(220, 0),
256 CHAN5G(222, 0), CHAN5G(224, 0),
257 CHAN5G(226, 0), CHAN5G(228, 0),
260 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
261 CHAN5G(34, 0), CHAN5G(36, 0),
262 CHAN5G(38, 0), CHAN5G(40, 0),
263 CHAN5G(42, 0), CHAN5G(44, 0),
264 CHAN5G(46, 0), CHAN5G(48, 0),
265 CHAN5G(52, 0), CHAN5G(56, 0),
266 CHAN5G(60, 0), CHAN5G(64, 0),
267 CHAN5G(100, 0), CHAN5G(104, 0),
268 CHAN5G(108, 0), CHAN5G(112, 0),
269 CHAN5G(116, 0), CHAN5G(120, 0),
270 CHAN5G(124, 0), CHAN5G(128, 0),
271 CHAN5G(132, 0), CHAN5G(136, 0),
272 CHAN5G(140, 0), CHAN5G(149, 0),
273 CHAN5G(153, 0), CHAN5G(157, 0),
274 CHAN5G(161, 0), CHAN5G(165, 0),
275 CHAN5G(184, 0), CHAN5G(188, 0),
276 CHAN5G(192, 0), CHAN5G(196, 0),
277 CHAN5G(200, 0), CHAN5G(204, 0),
278 CHAN5G(208, 0), CHAN5G(212, 0),
283 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
284 .band = IEEE80211_BAND_5GHZ,
285 .channels = b43_5ghz_nphy_chantable,
286 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
287 .bitrates = b43_a_ratetable,
288 .n_bitrates = b43_a_ratetable_size,
291 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
292 .band = IEEE80211_BAND_5GHZ,
293 .channels = b43_5ghz_aphy_chantable,
294 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
295 .bitrates = b43_a_ratetable,
296 .n_bitrates = b43_a_ratetable_size,
299 static struct ieee80211_supported_band b43_band_2GHz = {
300 .band = IEEE80211_BAND_2GHZ,
301 .channels = b43_2ghz_chantable,
302 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
303 .bitrates = b43_g_ratetable,
304 .n_bitrates = b43_g_ratetable_size,
307 static void b43_wireless_core_exit(struct b43_wldev *dev);
308 static int b43_wireless_core_init(struct b43_wldev *dev);
309 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
310 static int b43_wireless_core_start(struct b43_wldev *dev);
312 static int b43_ratelimit(struct b43_wl *wl)
314 if (!wl || !wl->current_dev)
316 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
318 /* We are up and running.
319 * Ratelimit the messages to avoid DoS over the net. */
320 return net_ratelimit();
323 void b43info(struct b43_wl *wl, const char *fmt, ...)
325 struct va_format vaf;
328 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
330 if (!b43_ratelimit(wl))
338 printk(KERN_INFO "b43-%s: %pV",
339 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
344 void b43err(struct b43_wl *wl, const char *fmt, ...)
346 struct va_format vaf;
349 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
351 if (!b43_ratelimit(wl))
359 printk(KERN_ERR "b43-%s ERROR: %pV",
360 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
365 void b43warn(struct b43_wl *wl, const char *fmt, ...)
367 struct va_format vaf;
370 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
372 if (!b43_ratelimit(wl))
380 printk(KERN_WARNING "b43-%s warning: %pV",
381 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
386 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
388 struct va_format vaf;
391 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
399 printk(KERN_DEBUG "b43-%s debug: %pV",
400 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
405 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
409 B43_WARN_ON(offset % 4 != 0);
411 macctl = b43_read32(dev, B43_MMIO_MACCTL);
412 if (macctl & B43_MACCTL_BE)
415 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
417 b43_write32(dev, B43_MMIO_RAM_DATA, val);
420 static inline void b43_shm_control_word(struct b43_wldev *dev,
421 u16 routing, u16 offset)
425 /* "offset" is the WORD offset. */
429 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
432 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
436 if (routing == B43_SHM_SHARED) {
437 B43_WARN_ON(offset & 0x0001);
438 if (offset & 0x0003) {
439 /* Unaligned access */
440 b43_shm_control_word(dev, routing, offset >> 2);
441 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
442 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
443 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
449 b43_shm_control_word(dev, routing, offset);
450 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
455 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
459 if (routing == B43_SHM_SHARED) {
460 B43_WARN_ON(offset & 0x0001);
461 if (offset & 0x0003) {
462 /* Unaligned access */
463 b43_shm_control_word(dev, routing, offset >> 2);
464 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
470 b43_shm_control_word(dev, routing, offset);
471 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
476 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
485 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
486 b43_write16(dev, B43_MMIO_SHM_DATA,
487 (value >> 16) & 0xFFFF);
492 b43_shm_control_word(dev, routing, offset);
493 b43_write32(dev, B43_MMIO_SHM_DATA, value);
496 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
498 if (routing == B43_SHM_SHARED) {
499 B43_WARN_ON(offset & 0x0001);
500 if (offset & 0x0003) {
501 /* Unaligned access */
502 b43_shm_control_word(dev, routing, offset >> 2);
503 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
508 b43_shm_control_word(dev, routing, offset);
509 b43_write16(dev, B43_MMIO_SHM_DATA, value);
513 u64 b43_hf_read(struct b43_wldev *dev)
517 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
519 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
521 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
526 /* Write HostFlags */
527 void b43_hf_write(struct b43_wldev *dev, u64 value)
531 lo = (value & 0x00000000FFFFULL);
532 mi = (value & 0x0000FFFF0000ULL) >> 16;
533 hi = (value & 0xFFFF00000000ULL) >> 32;
534 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
535 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
536 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
539 /* Read the firmware capabilities bitmask (Opensource firmware only) */
540 static u16 b43_fwcapa_read(struct b43_wldev *dev)
542 B43_WARN_ON(!dev->fw.opensource);
543 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
546 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
550 B43_WARN_ON(dev->sdev->id.revision < 3);
552 /* The hardware guarantees us an atomic read, if we
553 * read the low register first. */
554 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
555 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
562 static void b43_time_lock(struct b43_wldev *dev)
566 macctl = b43_read32(dev, B43_MMIO_MACCTL);
567 macctl |= B43_MACCTL_TBTTHOLD;
568 b43_write32(dev, B43_MMIO_MACCTL, macctl);
569 /* Commit the write */
570 b43_read32(dev, B43_MMIO_MACCTL);
573 static void b43_time_unlock(struct b43_wldev *dev)
577 macctl = b43_read32(dev, B43_MMIO_MACCTL);
578 macctl &= ~B43_MACCTL_TBTTHOLD;
579 b43_write32(dev, B43_MMIO_MACCTL, macctl);
580 /* Commit the write */
581 b43_read32(dev, B43_MMIO_MACCTL);
584 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
588 B43_WARN_ON(dev->sdev->id.revision < 3);
592 /* The hardware guarantees us an atomic write, if we
593 * write the low register first. */
594 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
596 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
600 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
603 b43_tsf_write_locked(dev, tsf);
604 b43_time_unlock(dev);
608 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
610 static const u8 zero_addr[ETH_ALEN] = { 0 };
617 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
621 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
624 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
627 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
630 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
634 u8 mac_bssid[ETH_ALEN * 2];
638 bssid = dev->wl->bssid;
639 mac = dev->wl->mac_addr;
641 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
643 memcpy(mac_bssid, mac, ETH_ALEN);
644 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
646 /* Write our MAC address and BSSID to template ram */
647 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
648 tmp = (u32) (mac_bssid[i + 0]);
649 tmp |= (u32) (mac_bssid[i + 1]) << 8;
650 tmp |= (u32) (mac_bssid[i + 2]) << 16;
651 tmp |= (u32) (mac_bssid[i + 3]) << 24;
652 b43_ram_write(dev, 0x20 + i, tmp);
656 static void b43_upload_card_macaddress(struct b43_wldev *dev)
658 b43_write_mac_bssid_templates(dev);
659 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
662 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
664 /* slot_time is in usec. */
665 /* This test used to exit for all but a G PHY. */
666 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
668 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
669 /* Shared memory location 0x0010 is the slot time and should be
670 * set to slot_time; however, this register is initially 0 and changing
671 * the value adversely affects the transmit rate for BCM4311
672 * devices. Until this behavior is unterstood, delete this step
674 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
678 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
680 b43_set_slot_time(dev, 9);
683 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
685 b43_set_slot_time(dev, 20);
688 /* DummyTransmission function, as documented on
689 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
691 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
693 struct b43_phy *phy = &dev->phy;
694 unsigned int i, max_loop;
706 buffer[0] = 0x000201CC;
709 buffer[0] = 0x000B846E;
712 for (i = 0; i < 5; i++)
713 b43_ram_write(dev, i * 4, buffer[i]);
715 b43_write16(dev, 0x0568, 0x0000);
716 if (dev->sdev->id.revision < 11)
717 b43_write16(dev, 0x07C0, 0x0000);
719 b43_write16(dev, 0x07C0, 0x0100);
720 value = (ofdm ? 0x41 : 0x40);
721 b43_write16(dev, 0x050C, value);
722 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
723 b43_write16(dev, 0x0514, 0x1A02);
724 b43_write16(dev, 0x0508, 0x0000);
725 b43_write16(dev, 0x050A, 0x0000);
726 b43_write16(dev, 0x054C, 0x0000);
727 b43_write16(dev, 0x056A, 0x0014);
728 b43_write16(dev, 0x0568, 0x0826);
729 b43_write16(dev, 0x0500, 0x0000);
730 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
736 b43_write16(dev, 0x0502, 0x00D0);
739 b43_write16(dev, 0x0502, 0x0050);
742 b43_write16(dev, 0x0502, 0x0030);
745 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
746 b43_radio_write16(dev, 0x0051, 0x0017);
747 for (i = 0x00; i < max_loop; i++) {
748 value = b43_read16(dev, 0x050E);
753 for (i = 0x00; i < 0x0A; i++) {
754 value = b43_read16(dev, 0x050E);
759 for (i = 0x00; i < 0x19; i++) {
760 value = b43_read16(dev, 0x0690);
761 if (!(value & 0x0100))
765 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
766 b43_radio_write16(dev, 0x0051, 0x0037);
769 static void key_write(struct b43_wldev *dev,
770 u8 index, u8 algorithm, const u8 *key)
777 /* Key index/algo block */
778 kidx = b43_kidx_to_fw(dev, index);
779 value = ((kidx << 4) | algorithm);
780 b43_shm_write16(dev, B43_SHM_SHARED,
781 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
783 /* Write the key to the Key Table Pointer offset */
784 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
785 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
787 value |= (u16) (key[i + 1]) << 8;
788 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
792 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
794 u32 addrtmp[2] = { 0, 0, };
795 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
797 if (b43_new_kidx_api(dev))
798 pairwise_keys_start = B43_NR_GROUP_KEYS;
800 B43_WARN_ON(index < pairwise_keys_start);
801 /* We have four default TX keys and possibly four default RX keys.
802 * Physical mac 0 is mapped to physical key 4 or 8, depending
803 * on the firmware version.
804 * So we must adjust the index here.
806 index -= pairwise_keys_start;
807 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
810 addrtmp[0] = addr[0];
811 addrtmp[0] |= ((u32) (addr[1]) << 8);
812 addrtmp[0] |= ((u32) (addr[2]) << 16);
813 addrtmp[0] |= ((u32) (addr[3]) << 24);
814 addrtmp[1] = addr[4];
815 addrtmp[1] |= ((u32) (addr[5]) << 8);
818 /* Receive match transmitter address (RCMTA) mechanism */
819 b43_shm_write32(dev, B43_SHM_RCMTA,
820 (index * 2) + 0, addrtmp[0]);
821 b43_shm_write16(dev, B43_SHM_RCMTA,
822 (index * 2) + 1, addrtmp[1]);
825 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
826 * When a packet is received, the iv32 is checked.
827 * - if it doesn't the packet is returned without modification (and software
828 * decryption can be done). That's what happen when iv16 wrap.
829 * - if it does, the rc4 key is computed, and decryption is tried.
830 * Either it will success and B43_RX_MAC_DEC is returned,
831 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
832 * and the packet is not usable (it got modified by the ucode).
833 * So in order to never have B43_RX_MAC_DECERR, we should provide
834 * a iv32 and phase1key that match. Because we drop packets in case of
835 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
836 * packets will be lost without higher layer knowing (ie no resync possible
839 * NOTE : this should support 50 key like RCMTA because
840 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
842 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
847 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
849 if (!modparam_hwtkip)
852 if (b43_new_kidx_api(dev))
853 pairwise_keys_start = B43_NR_GROUP_KEYS;
855 B43_WARN_ON(index < pairwise_keys_start);
856 /* We have four default TX keys and possibly four default RX keys.
857 * Physical mac 0 is mapped to physical key 4 or 8, depending
858 * on the firmware version.
859 * So we must adjust the index here.
861 index -= pairwise_keys_start;
862 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
864 if (b43_debug(dev, B43_DBG_KEYS)) {
865 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
868 /* Write the key to the RX tkip shared mem */
869 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
870 for (i = 0; i < 10; i += 2) {
871 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
872 phase1key ? phase1key[i / 2] : 0);
874 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
875 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
878 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
879 struct ieee80211_vif *vif,
880 struct ieee80211_key_conf *keyconf,
881 struct ieee80211_sta *sta,
882 u32 iv32, u16 *phase1key)
884 struct b43_wl *wl = hw_to_b43_wl(hw);
885 struct b43_wldev *dev;
886 int index = keyconf->hw_key_idx;
888 if (B43_WARN_ON(!modparam_hwtkip))
891 /* This is only called from the RX path through mac80211, where
892 * our mutex is already locked. */
893 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
894 dev = wl->current_dev;
895 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
897 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
899 rx_tkip_phase1_write(dev, index, iv32, phase1key);
900 /* only pairwise TKIP keys are supported right now */
903 keymac_write(dev, index, sta->addr);
906 static void do_key_write(struct b43_wldev *dev,
907 u8 index, u8 algorithm,
908 const u8 *key, size_t key_len, const u8 *mac_addr)
910 u8 buf[B43_SEC_KEYSIZE] = { 0, };
911 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
913 if (b43_new_kidx_api(dev))
914 pairwise_keys_start = B43_NR_GROUP_KEYS;
916 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
917 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
919 if (index >= pairwise_keys_start)
920 keymac_write(dev, index, NULL); /* First zero out mac. */
921 if (algorithm == B43_SEC_ALGO_TKIP) {
923 * We should provide an initial iv32, phase1key pair.
924 * We could start with iv32=0 and compute the corresponding
925 * phase1key, but this means calling ieee80211_get_tkip_key
926 * with a fake skb (or export other tkip function).
927 * Because we are lazy we hope iv32 won't start with
928 * 0xffffffff and let's b43_op_update_tkip_key provide a
931 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
932 } else if (index >= pairwise_keys_start) /* clear it */
933 rx_tkip_phase1_write(dev, index, 0, NULL);
935 memcpy(buf, key, key_len);
936 key_write(dev, index, algorithm, buf);
937 if (index >= pairwise_keys_start)
938 keymac_write(dev, index, mac_addr);
940 dev->key[index].algorithm = algorithm;
943 static int b43_key_write(struct b43_wldev *dev,
944 int index, u8 algorithm,
945 const u8 *key, size_t key_len,
947 struct ieee80211_key_conf *keyconf)
950 int pairwise_keys_start;
952 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
953 * - Temporal Encryption Key (128 bits)
954 * - Temporal Authenticator Tx MIC Key (64 bits)
955 * - Temporal Authenticator Rx MIC Key (64 bits)
957 * Hardware only store TEK
959 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
961 if (key_len > B43_SEC_KEYSIZE)
963 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
964 /* Check that we don't already have this key. */
965 B43_WARN_ON(dev->key[i].keyconf == keyconf);
968 /* Pairwise key. Get an empty slot for the key. */
969 if (b43_new_kidx_api(dev))
970 pairwise_keys_start = B43_NR_GROUP_KEYS;
972 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
973 for (i = pairwise_keys_start;
974 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
976 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
977 if (!dev->key[i].keyconf) {
984 b43warn(dev->wl, "Out of hardware key memory\n");
988 B43_WARN_ON(index > 3);
990 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
991 if ((index <= 3) && !b43_new_kidx_api(dev)) {
993 B43_WARN_ON(mac_addr);
994 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
996 keyconf->hw_key_idx = index;
997 dev->key[index].keyconf = keyconf;
1002 static int b43_key_clear(struct b43_wldev *dev, int index)
1004 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1006 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1007 NULL, B43_SEC_KEYSIZE, NULL);
1008 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1009 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1010 NULL, B43_SEC_KEYSIZE, NULL);
1012 dev->key[index].keyconf = NULL;
1017 static void b43_clear_keys(struct b43_wldev *dev)
1021 if (b43_new_kidx_api(dev))
1022 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1024 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1025 for (i = 0; i < count; i++)
1026 b43_key_clear(dev, i);
1029 static void b43_dump_keymemory(struct b43_wldev *dev)
1031 unsigned int i, index, count, offset, pairwise_keys_start;
1037 struct b43_key *key;
1039 if (!b43_debug(dev, B43_DBG_KEYS))
1042 hf = b43_hf_read(dev);
1043 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1044 !!(hf & B43_HF_USEDEFKEYS));
1045 if (b43_new_kidx_api(dev)) {
1046 pairwise_keys_start = B43_NR_GROUP_KEYS;
1047 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1049 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1050 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1052 for (index = 0; index < count; index++) {
1053 key = &(dev->key[index]);
1054 printk(KERN_DEBUG "Key slot %02u: %s",
1055 index, (key->keyconf == NULL) ? " " : "*");
1056 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1057 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1058 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1059 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1062 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1063 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1064 printk(" Algo: %04X/%02X", algo, key->algorithm);
1066 if (index >= pairwise_keys_start) {
1067 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1069 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1070 for (i = 0; i < 14; i += 2) {
1071 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1072 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1075 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1076 ((index - pairwise_keys_start) * 2) + 0);
1077 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1078 ((index - pairwise_keys_start) * 2) + 1);
1079 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1080 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1081 printk(" MAC: %pM", mac);
1083 printk(" DEFAULT KEY");
1088 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1096 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1097 (ps_flags & B43_PS_DISABLED));
1098 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1100 if (ps_flags & B43_PS_ENABLED) {
1102 } else if (ps_flags & B43_PS_DISABLED) {
1105 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1106 // and thus is not an AP and we are associated, set bit 25
1108 if (ps_flags & B43_PS_AWAKE) {
1110 } else if (ps_flags & B43_PS_ASLEEP) {
1113 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1114 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1115 // successful, set bit26
1118 /* FIXME: For now we force awake-on and hwps-off */
1122 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1124 macctl |= B43_MACCTL_HWPS;
1126 macctl &= ~B43_MACCTL_HWPS;
1128 macctl |= B43_MACCTL_AWAKE;
1130 macctl &= ~B43_MACCTL_AWAKE;
1131 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1133 b43_read32(dev, B43_MMIO_MACCTL);
1134 if (awake && dev->sdev->id.revision >= 5) {
1135 /* Wait for the microcode to wake up. */
1136 for (i = 0; i < 100; i++) {
1137 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1138 B43_SHM_SH_UCODESTAT);
1139 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1146 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1150 flags |= B43_TMSLOW_PHYCLKEN;
1151 flags |= B43_TMSLOW_PHYRESET;
1152 if (dev->phy.type == B43_PHYTYPE_N)
1153 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1154 ssb_device_enable(dev->sdev, flags);
1155 msleep(2); /* Wait for the PLL to turn on. */
1157 /* Now take the PHY out of Reset again */
1158 tmslow = ssb_read32(dev->sdev, SSB_TMSLOW);
1159 tmslow |= SSB_TMSLOW_FGC;
1160 tmslow &= ~B43_TMSLOW_PHYRESET;
1161 ssb_write32(dev->sdev, SSB_TMSLOW, tmslow);
1162 ssb_read32(dev->sdev, SSB_TMSLOW); /* flush */
1164 tmslow &= ~SSB_TMSLOW_FGC;
1165 ssb_write32(dev->sdev, SSB_TMSLOW, tmslow);
1166 ssb_read32(dev->sdev, SSB_TMSLOW); /* flush */
1170 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1174 b43_ssb_wireless_core_reset(dev, flags);
1176 /* Turn Analog ON, but only if we already know the PHY-type.
1177 * This protects against very early setup where we don't know the
1178 * PHY-type, yet. wireless_core_reset will be called once again later,
1179 * when we know the PHY-type. */
1181 dev->phy.ops->switch_analog(dev, 1);
1183 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1184 macctl &= ~B43_MACCTL_GMODE;
1185 if (flags & B43_TMSLOW_GMODE)
1186 macctl |= B43_MACCTL_GMODE;
1187 macctl |= B43_MACCTL_IHR_ENABLED;
1188 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1191 static void handle_irq_transmit_status(struct b43_wldev *dev)
1195 struct b43_txstatus stat;
1198 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1199 if (!(v0 & 0x00000001))
1201 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1203 stat.cookie = (v0 >> 16);
1204 stat.seq = (v1 & 0x0000FFFF);
1205 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1206 tmp = (v0 & 0x0000FFFF);
1207 stat.frame_count = ((tmp & 0xF000) >> 12);
1208 stat.rts_count = ((tmp & 0x0F00) >> 8);
1209 stat.supp_reason = ((tmp & 0x001C) >> 2);
1210 stat.pm_indicated = !!(tmp & 0x0080);
1211 stat.intermediate = !!(tmp & 0x0040);
1212 stat.for_ampdu = !!(tmp & 0x0020);
1213 stat.acked = !!(tmp & 0x0002);
1215 b43_handle_txstatus(dev, &stat);
1219 static void drain_txstatus_queue(struct b43_wldev *dev)
1223 if (dev->sdev->id.revision < 5)
1225 /* Read all entries from the microcode TXstatus FIFO
1226 * and throw them away.
1229 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1230 if (!(dummy & 0x00000001))
1232 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1236 static u32 b43_jssi_read(struct b43_wldev *dev)
1240 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1242 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1247 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1249 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1250 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1253 static void b43_generate_noise_sample(struct b43_wldev *dev)
1255 b43_jssi_write(dev, 0x7F7F7F7F);
1256 b43_write32(dev, B43_MMIO_MACCMD,
1257 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1260 static void b43_calculate_link_quality(struct b43_wldev *dev)
1262 /* Top half of Link Quality calculation. */
1264 if (dev->phy.type != B43_PHYTYPE_G)
1266 if (dev->noisecalc.calculation_running)
1268 dev->noisecalc.calculation_running = 1;
1269 dev->noisecalc.nr_samples = 0;
1271 b43_generate_noise_sample(dev);
1274 static void handle_irq_noise(struct b43_wldev *dev)
1276 struct b43_phy_g *phy = dev->phy.g;
1282 /* Bottom half of Link Quality calculation. */
1284 if (dev->phy.type != B43_PHYTYPE_G)
1287 /* Possible race condition: It might be possible that the user
1288 * changed to a different channel in the meantime since we
1289 * started the calculation. We ignore that fact, since it's
1290 * not really that much of a problem. The background noise is
1291 * an estimation only anyway. Slightly wrong results will get damped
1292 * by the averaging of the 8 sample rounds. Additionally the
1293 * value is shortlived. So it will be replaced by the next noise
1294 * calculation round soon. */
1296 B43_WARN_ON(!dev->noisecalc.calculation_running);
1297 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1298 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1299 noise[2] == 0x7F || noise[3] == 0x7F)
1302 /* Get the noise samples. */
1303 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1304 i = dev->noisecalc.nr_samples;
1305 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1306 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1307 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1308 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1309 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1310 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1311 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1312 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1313 dev->noisecalc.nr_samples++;
1314 if (dev->noisecalc.nr_samples == 8) {
1315 /* Calculate the Link Quality by the noise samples. */
1317 for (i = 0; i < 8; i++) {
1318 for (j = 0; j < 4; j++)
1319 average += dev->noisecalc.samples[i][j];
1325 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1326 tmp = (tmp / 128) & 0x1F;
1336 dev->stats.link_noise = average;
1337 dev->noisecalc.calculation_running = 0;
1341 b43_generate_noise_sample(dev);
1344 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1346 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1349 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1350 b43_power_saving_ctl_bits(dev, 0);
1352 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1356 static void handle_irq_atim_end(struct b43_wldev *dev)
1358 if (dev->dfq_valid) {
1359 b43_write32(dev, B43_MMIO_MACCMD,
1360 b43_read32(dev, B43_MMIO_MACCMD)
1361 | B43_MACCMD_DFQ_VALID);
1366 static void handle_irq_pmq(struct b43_wldev *dev)
1373 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1374 if (!(tmp & 0x00000008))
1377 /* 16bit write is odd, but correct. */
1378 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1381 static void b43_write_template_common(struct b43_wldev *dev,
1382 const u8 *data, u16 size,
1384 u16 shm_size_offset, u8 rate)
1387 struct b43_plcp_hdr4 plcp;
1390 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1391 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1392 ram_offset += sizeof(u32);
1393 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1394 * So leave the first two bytes of the next write blank.
1396 tmp = (u32) (data[0]) << 16;
1397 tmp |= (u32) (data[1]) << 24;
1398 b43_ram_write(dev, ram_offset, tmp);
1399 ram_offset += sizeof(u32);
1400 for (i = 2; i < size; i += sizeof(u32)) {
1401 tmp = (u32) (data[i + 0]);
1403 tmp |= (u32) (data[i + 1]) << 8;
1405 tmp |= (u32) (data[i + 2]) << 16;
1407 tmp |= (u32) (data[i + 3]) << 24;
1408 b43_ram_write(dev, ram_offset + i - 2, tmp);
1410 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1411 size + sizeof(struct b43_plcp_hdr6));
1414 /* Check if the use of the antenna that ieee80211 told us to
1415 * use is possible. This will fall back to DEFAULT.
1416 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1417 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1422 if (antenna_nr == 0) {
1423 /* Zero means "use default antenna". That's always OK. */
1427 /* Get the mask of available antennas. */
1429 antenna_mask = dev->sdev->bus->sprom.ant_available_bg;
1431 antenna_mask = dev->sdev->bus->sprom.ant_available_a;
1433 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1434 /* This antenna is not available. Fall back to default. */
1441 /* Convert a b43 antenna number value to the PHY TX control value. */
1442 static u16 b43_antenna_to_phyctl(int antenna)
1446 return B43_TXH_PHY_ANT0;
1448 return B43_TXH_PHY_ANT1;
1450 return B43_TXH_PHY_ANT2;
1452 return B43_TXH_PHY_ANT3;
1453 case B43_ANTENNA_AUTO0:
1454 case B43_ANTENNA_AUTO1:
1455 return B43_TXH_PHY_ANT01AUTO;
1461 static void b43_write_beacon_template(struct b43_wldev *dev,
1463 u16 shm_size_offset)
1465 unsigned int i, len, variable_len;
1466 const struct ieee80211_mgmt *bcn;
1472 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1474 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1475 len = min((size_t) dev->wl->current_beacon->len,
1476 0x200 - sizeof(struct b43_plcp_hdr6));
1477 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1479 b43_write_template_common(dev, (const u8 *)bcn,
1480 len, ram_offset, shm_size_offset, rate);
1482 /* Write the PHY TX control parameters. */
1483 antenna = B43_ANTENNA_DEFAULT;
1484 antenna = b43_antenna_to_phyctl(antenna);
1485 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1486 /* We can't send beacons with short preamble. Would get PHY errors. */
1487 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1488 ctl &= ~B43_TXH_PHY_ANT;
1489 ctl &= ~B43_TXH_PHY_ENC;
1491 if (b43_is_cck_rate(rate))
1492 ctl |= B43_TXH_PHY_ENC_CCK;
1494 ctl |= B43_TXH_PHY_ENC_OFDM;
1495 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1497 /* Find the position of the TIM and the DTIM_period value
1498 * and write them to SHM. */
1499 ie = bcn->u.beacon.variable;
1500 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1501 for (i = 0; i < variable_len - 2; ) {
1502 uint8_t ie_id, ie_len;
1509 /* This is the TIM Information Element */
1511 /* Check whether the ie_len is in the beacon data range. */
1512 if (variable_len < ie_len + 2 + i)
1514 /* A valid TIM is at least 4 bytes long. */
1519 tim_position = sizeof(struct b43_plcp_hdr6);
1520 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1523 dtim_period = ie[i + 3];
1525 b43_shm_write16(dev, B43_SHM_SHARED,
1526 B43_SHM_SH_TIMBPOS, tim_position);
1527 b43_shm_write16(dev, B43_SHM_SHARED,
1528 B43_SHM_SH_DTIMPER, dtim_period);
1535 * If ucode wants to modify TIM do it behind the beacon, this
1536 * will happen, for example, when doing mesh networking.
1538 b43_shm_write16(dev, B43_SHM_SHARED,
1540 len + sizeof(struct b43_plcp_hdr6));
1541 b43_shm_write16(dev, B43_SHM_SHARED,
1542 B43_SHM_SH_DTIMPER, 0);
1544 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1547 static void b43_upload_beacon0(struct b43_wldev *dev)
1549 struct b43_wl *wl = dev->wl;
1551 if (wl->beacon0_uploaded)
1553 b43_write_beacon_template(dev, 0x68, 0x18);
1554 wl->beacon0_uploaded = 1;
1557 static void b43_upload_beacon1(struct b43_wldev *dev)
1559 struct b43_wl *wl = dev->wl;
1561 if (wl->beacon1_uploaded)
1563 b43_write_beacon_template(dev, 0x468, 0x1A);
1564 wl->beacon1_uploaded = 1;
1567 static void handle_irq_beacon(struct b43_wldev *dev)
1569 struct b43_wl *wl = dev->wl;
1570 u32 cmd, beacon0_valid, beacon1_valid;
1572 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1573 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1576 /* This is the bottom half of the asynchronous beacon update. */
1578 /* Ignore interrupt in the future. */
1579 dev->irq_mask &= ~B43_IRQ_BEACON;
1581 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1582 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1583 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1585 /* Schedule interrupt manually, if busy. */
1586 if (beacon0_valid && beacon1_valid) {
1587 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1588 dev->irq_mask |= B43_IRQ_BEACON;
1592 if (unlikely(wl->beacon_templates_virgin)) {
1593 /* We never uploaded a beacon before.
1594 * Upload both templates now, but only mark one valid. */
1595 wl->beacon_templates_virgin = 0;
1596 b43_upload_beacon0(dev);
1597 b43_upload_beacon1(dev);
1598 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1599 cmd |= B43_MACCMD_BEACON0_VALID;
1600 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1602 if (!beacon0_valid) {
1603 b43_upload_beacon0(dev);
1604 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1605 cmd |= B43_MACCMD_BEACON0_VALID;
1606 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1607 } else if (!beacon1_valid) {
1608 b43_upload_beacon1(dev);
1609 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1610 cmd |= B43_MACCMD_BEACON1_VALID;
1611 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1616 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1618 u32 old_irq_mask = dev->irq_mask;
1620 /* update beacon right away or defer to irq */
1621 handle_irq_beacon(dev);
1622 if (old_irq_mask != dev->irq_mask) {
1623 /* The handler updated the IRQ mask. */
1624 B43_WARN_ON(!dev->irq_mask);
1625 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1626 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1628 /* Device interrupts are currently disabled. That means
1629 * we just ran the hardirq handler and scheduled the
1630 * IRQ thread. The thread will write the IRQ mask when
1631 * it finished, so there's nothing to do here. Writing
1632 * the mask _here_ would incorrectly re-enable IRQs. */
1637 static void b43_beacon_update_trigger_work(struct work_struct *work)
1639 struct b43_wl *wl = container_of(work, struct b43_wl,
1640 beacon_update_trigger);
1641 struct b43_wldev *dev;
1643 mutex_lock(&wl->mutex);
1644 dev = wl->current_dev;
1645 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1646 if (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) {
1647 /* wl->mutex is enough. */
1648 b43_do_beacon_update_trigger_work(dev);
1651 spin_lock_irq(&wl->hardirq_lock);
1652 b43_do_beacon_update_trigger_work(dev);
1654 spin_unlock_irq(&wl->hardirq_lock);
1657 mutex_unlock(&wl->mutex);
1660 /* Asynchronously update the packet templates in template RAM.
1661 * Locking: Requires wl->mutex to be locked. */
1662 static void b43_update_templates(struct b43_wl *wl)
1664 struct sk_buff *beacon;
1666 /* This is the top half of the ansynchronous beacon update.
1667 * The bottom half is the beacon IRQ.
1668 * Beacon update must be asynchronous to avoid sending an
1669 * invalid beacon. This can happen for example, if the firmware
1670 * transmits a beacon while we are updating it. */
1672 /* We could modify the existing beacon and set the aid bit in
1673 * the TIM field, but that would probably require resizing and
1674 * moving of data within the beacon template.
1675 * Simply request a new beacon and let mac80211 do the hard work. */
1676 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1677 if (unlikely(!beacon))
1680 if (wl->current_beacon)
1681 dev_kfree_skb_any(wl->current_beacon);
1682 wl->current_beacon = beacon;
1683 wl->beacon0_uploaded = 0;
1684 wl->beacon1_uploaded = 0;
1685 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1688 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1691 if (dev->sdev->id.revision >= 3) {
1692 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1693 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1695 b43_write16(dev, 0x606, (beacon_int >> 6));
1696 b43_write16(dev, 0x610, beacon_int);
1698 b43_time_unlock(dev);
1699 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1702 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1706 /* Read the register that contains the reason code for the panic. */
1707 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1708 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1712 b43dbg(dev->wl, "The panic reason is unknown.\n");
1714 case B43_FWPANIC_DIE:
1715 /* Do not restart the controller or firmware.
1716 * The device is nonfunctional from now on.
1717 * Restarting would result in this panic to trigger again,
1718 * so we avoid that recursion. */
1720 case B43_FWPANIC_RESTART:
1721 b43_controller_restart(dev, "Microcode panic");
1726 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1728 unsigned int i, cnt;
1729 u16 reason, marker_id, marker_line;
1732 /* The proprietary firmware doesn't have this IRQ. */
1733 if (!dev->fw.opensource)
1736 /* Read the register that contains the reason code for this IRQ. */
1737 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1740 case B43_DEBUGIRQ_PANIC:
1741 b43_handle_firmware_panic(dev);
1743 case B43_DEBUGIRQ_DUMP_SHM:
1745 break; /* Only with driver debugging enabled. */
1746 buf = kmalloc(4096, GFP_ATOMIC);
1748 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1751 for (i = 0; i < 4096; i += 2) {
1752 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1753 buf[i / 2] = cpu_to_le16(tmp);
1755 b43info(dev->wl, "Shared memory dump:\n");
1756 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1757 16, 2, buf, 4096, 1);
1760 case B43_DEBUGIRQ_DUMP_REGS:
1762 break; /* Only with driver debugging enabled. */
1763 b43info(dev->wl, "Microcode register dump:\n");
1764 for (i = 0, cnt = 0; i < 64; i++) {
1765 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1768 printk("r%02u: 0x%04X ", i, tmp);
1777 case B43_DEBUGIRQ_MARKER:
1779 break; /* Only with driver debugging enabled. */
1780 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1782 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1783 B43_MARKER_LINE_REG);
1784 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1785 "at line number %u\n",
1786 marker_id, marker_line);
1789 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1793 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1794 b43_shm_write16(dev, B43_SHM_SCRATCH,
1795 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1798 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1801 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1802 u32 merged_dma_reason = 0;
1805 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1808 reason = dev->irq_reason;
1809 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1810 dma_reason[i] = dev->dma_reason[i];
1811 merged_dma_reason |= dma_reason[i];
1814 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1815 b43err(dev->wl, "MAC transmission error\n");
1817 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1818 b43err(dev->wl, "PHY transmission error\n");
1820 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1821 atomic_set(&dev->phy.txerr_cnt,
1822 B43_PHY_TX_BADNESS_LIMIT);
1823 b43err(dev->wl, "Too many PHY TX errors, "
1824 "restarting the controller\n");
1825 b43_controller_restart(dev, "PHY TX errors");
1829 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1830 B43_DMAIRQ_NONFATALMASK))) {
1831 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1832 b43err(dev->wl, "Fatal DMA error: "
1833 "0x%08X, 0x%08X, 0x%08X, "
1834 "0x%08X, 0x%08X, 0x%08X\n",
1835 dma_reason[0], dma_reason[1],
1836 dma_reason[2], dma_reason[3],
1837 dma_reason[4], dma_reason[5]);
1838 b43err(dev->wl, "This device does not support DMA "
1839 "on your system. It will now be switched to PIO.\n");
1840 /* Fall back to PIO transfers if we get fatal DMA errors! */
1842 b43_controller_restart(dev, "DMA error");
1845 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1846 b43err(dev->wl, "DMA error: "
1847 "0x%08X, 0x%08X, 0x%08X, "
1848 "0x%08X, 0x%08X, 0x%08X\n",
1849 dma_reason[0], dma_reason[1],
1850 dma_reason[2], dma_reason[3],
1851 dma_reason[4], dma_reason[5]);
1855 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1856 handle_irq_ucode_debug(dev);
1857 if (reason & B43_IRQ_TBTT_INDI)
1858 handle_irq_tbtt_indication(dev);
1859 if (reason & B43_IRQ_ATIM_END)
1860 handle_irq_atim_end(dev);
1861 if (reason & B43_IRQ_BEACON)
1862 handle_irq_beacon(dev);
1863 if (reason & B43_IRQ_PMQ)
1864 handle_irq_pmq(dev);
1865 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1867 if (reason & B43_IRQ_NOISESAMPLE_OK)
1868 handle_irq_noise(dev);
1870 /* Check the DMA reason registers for received data. */
1871 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1872 if (b43_using_pio_transfers(dev))
1873 b43_pio_rx(dev->pio.rx_queue);
1875 b43_dma_rx(dev->dma.rx_ring);
1877 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1878 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1879 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1880 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1881 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1883 if (reason & B43_IRQ_TX_OK)
1884 handle_irq_transmit_status(dev);
1886 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1887 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1890 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1892 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1893 if (reason & (1 << i))
1894 dev->irq_bit_count[i]++;
1900 /* Interrupt thread handler. Handles device interrupts in thread context. */
1901 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1903 struct b43_wldev *dev = dev_id;
1905 mutex_lock(&dev->wl->mutex);
1906 b43_do_interrupt_thread(dev);
1908 mutex_unlock(&dev->wl->mutex);
1913 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1917 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1918 * On SDIO, this runs under wl->mutex. */
1920 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1921 if (reason == 0xffffffff) /* shared IRQ */
1923 reason &= dev->irq_mask;
1927 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1929 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1931 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1933 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1935 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1938 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1942 /* ACK the interrupt. */
1943 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1944 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1945 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1946 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1947 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1948 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1950 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1953 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1954 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1955 /* Save the reason bitmasks for the IRQ thread handler. */
1956 dev->irq_reason = reason;
1958 return IRQ_WAKE_THREAD;
1961 /* Interrupt handler top-half. This runs with interrupts disabled. */
1962 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1964 struct b43_wldev *dev = dev_id;
1967 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1970 spin_lock(&dev->wl->hardirq_lock);
1971 ret = b43_do_interrupt(dev);
1973 spin_unlock(&dev->wl->hardirq_lock);
1978 /* SDIO interrupt handler. This runs in process context. */
1979 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
1981 struct b43_wl *wl = dev->wl;
1984 mutex_lock(&wl->mutex);
1986 ret = b43_do_interrupt(dev);
1987 if (ret == IRQ_WAKE_THREAD)
1988 b43_do_interrupt_thread(dev);
1990 mutex_unlock(&wl->mutex);
1993 void b43_do_release_fw(struct b43_firmware_file *fw)
1995 release_firmware(fw->data);
1997 fw->filename = NULL;
2000 static void b43_release_firmware(struct b43_wldev *dev)
2002 b43_do_release_fw(&dev->fw.ucode);
2003 b43_do_release_fw(&dev->fw.pcm);
2004 b43_do_release_fw(&dev->fw.initvals);
2005 b43_do_release_fw(&dev->fw.initvals_band);
2008 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2012 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2013 "and download the correct firmware for this driver version. " \
2014 "Please carefully read all instructions on this website.\n";
2022 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2024 struct b43_firmware_file *fw)
2026 const struct firmware *blob;
2027 struct b43_fw_header *hdr;
2032 /* Don't fetch anything. Free possibly cached firmware. */
2033 /* FIXME: We should probably keep it anyway, to save some headache
2034 * on suspend/resume with multiband devices. */
2035 b43_do_release_fw(fw);
2039 if ((fw->type == ctx->req_type) &&
2040 (strcmp(fw->filename, name) == 0))
2041 return 0; /* Already have this fw. */
2042 /* Free the cached firmware first. */
2043 /* FIXME: We should probably do this later after we successfully
2044 * got the new fw. This could reduce headache with multiband devices.
2045 * We could also redesign this to cache the firmware for all possible
2046 * bands all the time. */
2047 b43_do_release_fw(fw);
2050 switch (ctx->req_type) {
2051 case B43_FWTYPE_PROPRIETARY:
2052 snprintf(ctx->fwname, sizeof(ctx->fwname),
2054 modparam_fwpostfix, name);
2056 case B43_FWTYPE_OPENSOURCE:
2057 snprintf(ctx->fwname, sizeof(ctx->fwname),
2059 modparam_fwpostfix, name);
2065 err = request_firmware(&blob, ctx->fwname, ctx->dev->sdev->dev);
2066 if (err == -ENOENT) {
2067 snprintf(ctx->errors[ctx->req_type],
2068 sizeof(ctx->errors[ctx->req_type]),
2069 "Firmware file \"%s\" not found\n", ctx->fwname);
2072 snprintf(ctx->errors[ctx->req_type],
2073 sizeof(ctx->errors[ctx->req_type]),
2074 "Firmware file \"%s\" request failed (err=%d)\n",
2078 if (blob->size < sizeof(struct b43_fw_header))
2080 hdr = (struct b43_fw_header *)(blob->data);
2081 switch (hdr->type) {
2082 case B43_FW_TYPE_UCODE:
2083 case B43_FW_TYPE_PCM:
2084 size = be32_to_cpu(hdr->size);
2085 if (size != blob->size - sizeof(struct b43_fw_header))
2088 case B43_FW_TYPE_IV:
2097 fw->filename = name;
2098 fw->type = ctx->req_type;
2103 snprintf(ctx->errors[ctx->req_type],
2104 sizeof(ctx->errors[ctx->req_type]),
2105 "Firmware file \"%s\" format error.\n", ctx->fwname);
2106 release_firmware(blob);
2111 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2113 struct b43_wldev *dev = ctx->dev;
2114 struct b43_firmware *fw = &ctx->dev->fw;
2115 const u8 rev = ctx->dev->sdev->id.revision;
2116 const char *filename;
2121 tmshigh = ssb_read32(dev->sdev, SSB_TMSHIGH);
2122 if ((rev >= 5) && (rev <= 10))
2123 filename = "ucode5";
2124 else if ((rev >= 11) && (rev <= 12))
2125 filename = "ucode11";
2127 filename = "ucode13";
2129 filename = "ucode14";
2131 filename = "ucode15";
2132 else if ((rev >= 16) && (rev <= 20))
2133 filename = "ucode16_mimo";
2136 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2141 if ((rev >= 5) && (rev <= 10))
2147 fw->pcm_request_failed = 0;
2148 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2149 if (err == -ENOENT) {
2150 /* We did not find a PCM file? Not fatal, but
2151 * core rev <= 10 must do without hwcrypto then. */
2152 fw->pcm_request_failed = 1;
2157 switch (dev->phy.type) {
2159 if ((rev >= 5) && (rev <= 10)) {
2160 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2161 filename = "a0g1initvals5";
2163 filename = "a0g0initvals5";
2165 goto err_no_initvals;
2168 if ((rev >= 5) && (rev <= 10))
2169 filename = "b0g0initvals5";
2171 filename = "b0g0initvals13";
2173 goto err_no_initvals;
2177 filename = "n0initvals16";
2178 else if ((rev >= 11) && (rev <= 12))
2179 filename = "n0initvals11";
2181 goto err_no_initvals;
2183 case B43_PHYTYPE_LP:
2185 filename = "lp0initvals13";
2187 filename = "lp0initvals14";
2189 filename = "lp0initvals15";
2191 goto err_no_initvals;
2194 goto err_no_initvals;
2196 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2200 /* Get bandswitch initvals */
2201 switch (dev->phy.type) {
2203 if ((rev >= 5) && (rev <= 10)) {
2204 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2205 filename = "a0g1bsinitvals5";
2207 filename = "a0g0bsinitvals5";
2208 } else if (rev >= 11)
2211 goto err_no_initvals;
2214 if ((rev >= 5) && (rev <= 10))
2215 filename = "b0g0bsinitvals5";
2219 goto err_no_initvals;
2223 filename = "n0bsinitvals16";
2224 else if ((rev >= 11) && (rev <= 12))
2225 filename = "n0bsinitvals11";
2227 goto err_no_initvals;
2229 case B43_PHYTYPE_LP:
2231 filename = "lp0bsinitvals13";
2233 filename = "lp0bsinitvals14";
2235 filename = "lp0bsinitvals15";
2237 goto err_no_initvals;
2240 goto err_no_initvals;
2242 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2249 err = ctx->fatal_failure = -EOPNOTSUPP;
2250 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2251 "is required for your device (wl-core rev %u)\n", rev);
2255 err = ctx->fatal_failure = -EOPNOTSUPP;
2256 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2257 "is required for your device (wl-core rev %u)\n", rev);
2261 err = ctx->fatal_failure = -EOPNOTSUPP;
2262 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2263 "is required for your device (wl-core rev %u)\n", rev);
2267 /* We failed to load this firmware image. The error message
2268 * already is in ctx->errors. Return and let our caller decide
2273 b43_release_firmware(dev);
2277 static int b43_request_firmware(struct b43_wldev *dev)
2279 struct b43_request_fw_context *ctx;
2284 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2289 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2290 err = b43_try_request_fw(ctx);
2292 goto out; /* Successfully loaded it. */
2293 err = ctx->fatal_failure;
2297 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2298 err = b43_try_request_fw(ctx);
2300 goto out; /* Successfully loaded it. */
2301 err = ctx->fatal_failure;
2305 /* Could not find a usable firmware. Print the errors. */
2306 for (i = 0; i < B43_NR_FWTYPES; i++) {
2307 errmsg = ctx->errors[i];
2309 b43err(dev->wl, errmsg);
2311 b43_print_fw_helptext(dev->wl, 1);
2319 static int b43_upload_microcode(struct b43_wldev *dev)
2321 struct wiphy *wiphy = dev->wl->hw->wiphy;
2322 const size_t hdr_len = sizeof(struct b43_fw_header);
2324 unsigned int i, len;
2325 u16 fwrev, fwpatch, fwdate, fwtime;
2329 /* Jump the microcode PSM to offset 0 */
2330 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2331 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2332 macctl |= B43_MACCTL_PSM_JMP0;
2333 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2334 /* Zero out all microcode PSM registers and shared memory. */
2335 for (i = 0; i < 64; i++)
2336 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2337 for (i = 0; i < 4096; i += 2)
2338 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2340 /* Upload Microcode. */
2341 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2342 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2343 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2344 for (i = 0; i < len; i++) {
2345 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2349 if (dev->fw.pcm.data) {
2350 /* Upload PCM data. */
2351 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2352 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2353 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2354 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2355 /* No need for autoinc bit in SHM_HW */
2356 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2357 for (i = 0; i < len; i++) {
2358 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2363 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2365 /* Start the microcode PSM */
2366 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2367 macctl &= ~B43_MACCTL_PSM_JMP0;
2368 macctl |= B43_MACCTL_PSM_RUN;
2369 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2371 /* Wait for the microcode to load and respond */
2374 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2375 if (tmp == B43_IRQ_MAC_SUSPENDED)
2379 b43err(dev->wl, "Microcode not responding\n");
2380 b43_print_fw_helptext(dev->wl, 1);
2386 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2388 /* Get and check the revisions. */
2389 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2390 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2391 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2392 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2394 if (fwrev <= 0x128) {
2395 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2396 "binary drivers older than version 4.x is unsupported. "
2397 "You must upgrade your firmware files.\n");
2398 b43_print_fw_helptext(dev->wl, 1);
2402 dev->fw.rev = fwrev;
2403 dev->fw.patch = fwpatch;
2404 dev->fw.opensource = (fwdate == 0xFFFF);
2406 /* Default to use-all-queues. */
2407 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2408 dev->qos_enabled = !!modparam_qos;
2409 /* Default to firmware/hardware crypto acceleration. */
2410 dev->hwcrypto_enabled = 1;
2412 if (dev->fw.opensource) {
2415 /* Patchlevel info is encoded in the "time" field. */
2416 dev->fw.patch = fwtime;
2417 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2418 dev->fw.rev, dev->fw.patch);
2420 fwcapa = b43_fwcapa_read(dev);
2421 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2422 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2423 /* Disable hardware crypto and fall back to software crypto. */
2424 dev->hwcrypto_enabled = 0;
2426 if (!(fwcapa & B43_FWCAPA_QOS)) {
2427 b43info(dev->wl, "QoS not supported by firmware\n");
2428 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2429 * ieee80211_unregister to make sure the networking core can
2430 * properly free possible resources. */
2431 dev->wl->hw->queues = 1;
2432 dev->qos_enabled = 0;
2435 b43info(dev->wl, "Loading firmware version %u.%u "
2436 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2438 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2439 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2440 if (dev->fw.pcm_request_failed) {
2441 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2442 "Hardware accelerated cryptography is disabled.\n");
2443 b43_print_fw_helptext(dev->wl, 0);
2447 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2448 dev->fw.rev, dev->fw.patch);
2449 wiphy->hw_version = dev->sdev->id.coreid;
2451 if (b43_is_old_txhdr_format(dev)) {
2452 /* We're over the deadline, but we keep support for old fw
2453 * until it turns out to be in major conflict with something new. */
2454 b43warn(dev->wl, "You are using an old firmware image. "
2455 "Support for old firmware will be removed soon "
2456 "(official deadline was July 2008).\n");
2457 b43_print_fw_helptext(dev->wl, 0);
2463 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2464 macctl &= ~B43_MACCTL_PSM_RUN;
2465 macctl |= B43_MACCTL_PSM_JMP0;
2466 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2471 static int b43_write_initvals(struct b43_wldev *dev,
2472 const struct b43_iv *ivals,
2476 const struct b43_iv *iv;
2481 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2483 for (i = 0; i < count; i++) {
2484 if (array_size < sizeof(iv->offset_size))
2486 array_size -= sizeof(iv->offset_size);
2487 offset = be16_to_cpu(iv->offset_size);
2488 bit32 = !!(offset & B43_IV_32BIT);
2489 offset &= B43_IV_OFFSET_MASK;
2490 if (offset >= 0x1000)
2495 if (array_size < sizeof(iv->data.d32))
2497 array_size -= sizeof(iv->data.d32);
2499 value = get_unaligned_be32(&iv->data.d32);
2500 b43_write32(dev, offset, value);
2502 iv = (const struct b43_iv *)((const uint8_t *)iv +
2508 if (array_size < sizeof(iv->data.d16))
2510 array_size -= sizeof(iv->data.d16);
2512 value = be16_to_cpu(iv->data.d16);
2513 b43_write16(dev, offset, value);
2515 iv = (const struct b43_iv *)((const uint8_t *)iv +
2526 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2527 b43_print_fw_helptext(dev->wl, 1);
2532 static int b43_upload_initvals(struct b43_wldev *dev)
2534 const size_t hdr_len = sizeof(struct b43_fw_header);
2535 const struct b43_fw_header *hdr;
2536 struct b43_firmware *fw = &dev->fw;
2537 const struct b43_iv *ivals;
2541 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2542 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2543 count = be32_to_cpu(hdr->size);
2544 err = b43_write_initvals(dev, ivals, count,
2545 fw->initvals.data->size - hdr_len);
2548 if (fw->initvals_band.data) {
2549 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2550 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2551 count = be32_to_cpu(hdr->size);
2552 err = b43_write_initvals(dev, ivals, count,
2553 fw->initvals_band.data->size - hdr_len);
2562 /* Initialize the GPIOs
2563 * http://bcm-specs.sipsolutions.net/GPIO
2565 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2567 struct ssb_bus *bus = dev->sdev->bus;
2569 #ifdef CONFIG_SSB_DRIVER_PCICORE
2570 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2572 return bus->chipco.dev;
2576 static int b43_gpio_init(struct b43_wldev *dev)
2578 struct ssb_device *gpiodev;
2581 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2582 & ~B43_MACCTL_GPOUTSMSK);
2584 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2589 if (dev->sdev->bus->chip_id == 0x4301) {
2593 if (0 /* FIXME: conditional unknown */ ) {
2594 b43_write16(dev, B43_MMIO_GPIO_MASK,
2595 b43_read16(dev, B43_MMIO_GPIO_MASK)
2600 if (dev->sdev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2601 b43_write16(dev, B43_MMIO_GPIO_MASK,
2602 b43_read16(dev, B43_MMIO_GPIO_MASK)
2607 if (dev->sdev->id.revision >= 2)
2608 mask |= 0x0010; /* FIXME: This is redundant. */
2610 gpiodev = b43_ssb_gpio_dev(dev);
2612 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2613 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2619 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2620 static void b43_gpio_cleanup(struct b43_wldev *dev)
2622 struct ssb_device *gpiodev;
2624 gpiodev = b43_ssb_gpio_dev(dev);
2626 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2629 /* http://bcm-specs.sipsolutions.net/EnableMac */
2630 void b43_mac_enable(struct b43_wldev *dev)
2632 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2635 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2636 B43_SHM_SH_UCODESTAT);
2637 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2638 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2639 b43err(dev->wl, "b43_mac_enable(): The firmware "
2640 "should be suspended, but current state is %u\n",
2645 dev->mac_suspended--;
2646 B43_WARN_ON(dev->mac_suspended < 0);
2647 if (dev->mac_suspended == 0) {
2648 b43_write32(dev, B43_MMIO_MACCTL,
2649 b43_read32(dev, B43_MMIO_MACCTL)
2650 | B43_MACCTL_ENABLED);
2651 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2652 B43_IRQ_MAC_SUSPENDED);
2654 b43_read32(dev, B43_MMIO_MACCTL);
2655 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2656 b43_power_saving_ctl_bits(dev, 0);
2660 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2661 void b43_mac_suspend(struct b43_wldev *dev)
2667 B43_WARN_ON(dev->mac_suspended < 0);
2669 if (dev->mac_suspended == 0) {
2670 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2671 b43_write32(dev, B43_MMIO_MACCTL,
2672 b43_read32(dev, B43_MMIO_MACCTL)
2673 & ~B43_MACCTL_ENABLED);
2674 /* force pci to flush the write */
2675 b43_read32(dev, B43_MMIO_MACCTL);
2676 for (i = 35; i; i--) {
2677 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2678 if (tmp & B43_IRQ_MAC_SUSPENDED)
2682 /* Hm, it seems this will take some time. Use msleep(). */
2683 for (i = 40; i; i--) {
2684 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2685 if (tmp & B43_IRQ_MAC_SUSPENDED)
2689 b43err(dev->wl, "MAC suspend failed\n");
2692 dev->mac_suspended++;
2695 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2696 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2698 u32 tmslow = ssb_read32(dev->sdev, SSB_TMSLOW);
2700 tmslow |= B43_TMSLOW_MACPHYCLKEN;
2702 tmslow &= ~B43_TMSLOW_MACPHYCLKEN;
2703 ssb_write32(dev->sdev, SSB_TMSLOW, tmslow);
2706 static void b43_adjust_opmode(struct b43_wldev *dev)
2708 struct b43_wl *wl = dev->wl;
2712 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2713 /* Reset status to STA infrastructure mode. */
2714 ctl &= ~B43_MACCTL_AP;
2715 ctl &= ~B43_MACCTL_KEEP_CTL;
2716 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2717 ctl &= ~B43_MACCTL_KEEP_BAD;
2718 ctl &= ~B43_MACCTL_PROMISC;
2719 ctl &= ~B43_MACCTL_BEACPROMISC;
2720 ctl |= B43_MACCTL_INFRA;
2722 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2723 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2724 ctl |= B43_MACCTL_AP;
2725 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2726 ctl &= ~B43_MACCTL_INFRA;
2728 if (wl->filter_flags & FIF_CONTROL)
2729 ctl |= B43_MACCTL_KEEP_CTL;
2730 if (wl->filter_flags & FIF_FCSFAIL)
2731 ctl |= B43_MACCTL_KEEP_BAD;
2732 if (wl->filter_flags & FIF_PLCPFAIL)
2733 ctl |= B43_MACCTL_KEEP_BADPLCP;
2734 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2735 ctl |= B43_MACCTL_PROMISC;
2736 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2737 ctl |= B43_MACCTL_BEACPROMISC;
2739 /* Workaround: On old hardware the HW-MAC-address-filter
2740 * doesn't work properly, so always run promisc in filter
2741 * it in software. */
2742 if (dev->sdev->id.revision <= 4)
2743 ctl |= B43_MACCTL_PROMISC;
2745 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2748 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2749 if (dev->sdev->bus->chip_id == 0x4306 &&
2750 dev->sdev->bus->chip_rev == 3)
2755 b43_write16(dev, 0x612, cfp_pretbtt);
2757 /* FIXME: We don't currently implement the PMQ mechanism,
2758 * so always disable it. If we want to implement PMQ,
2759 * we need to enable it here (clear DISCPMQ) in AP mode.
2761 if (0 /* ctl & B43_MACCTL_AP */) {
2762 b43_write32(dev, B43_MMIO_MACCTL,
2763 b43_read32(dev, B43_MMIO_MACCTL)
2764 & ~B43_MACCTL_DISCPMQ);
2766 b43_write32(dev, B43_MMIO_MACCTL,
2767 b43_read32(dev, B43_MMIO_MACCTL)
2768 | B43_MACCTL_DISCPMQ);
2772 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2778 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2781 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2783 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2784 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2787 static void b43_rate_memory_init(struct b43_wldev *dev)
2789 switch (dev->phy.type) {
2793 case B43_PHYTYPE_LP:
2794 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2795 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2796 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2797 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2798 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2799 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2800 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2801 if (dev->phy.type == B43_PHYTYPE_A)
2805 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2806 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2807 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2808 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2815 /* Set the default values for the PHY TX Control Words. */
2816 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2820 ctl |= B43_TXH_PHY_ENC_CCK;
2821 ctl |= B43_TXH_PHY_ANT01AUTO;
2822 ctl |= B43_TXH_PHY_TXPWR;
2824 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2825 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2826 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2829 /* Set the TX-Antenna for management frames sent by firmware. */
2830 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2835 ant = b43_antenna_to_phyctl(antenna);
2838 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2839 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2840 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2841 /* For Probe Resposes */
2842 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2843 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2844 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2847 /* This is the opposite of b43_chip_init() */
2848 static void b43_chip_exit(struct b43_wldev *dev)
2851 b43_gpio_cleanup(dev);
2852 /* firmware is released later */
2855 /* Initialize the chip
2856 * http://bcm-specs.sipsolutions.net/ChipInit
2858 static int b43_chip_init(struct b43_wldev *dev)
2860 struct b43_phy *phy = &dev->phy;
2865 /* Initialize the MAC control */
2866 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2868 macctl |= B43_MACCTL_GMODE;
2869 macctl |= B43_MACCTL_INFRA;
2870 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2872 err = b43_request_firmware(dev);
2875 err = b43_upload_microcode(dev);
2877 goto out; /* firmware is released later */
2879 err = b43_gpio_init(dev);
2881 goto out; /* firmware is released later */
2883 err = b43_upload_initvals(dev);
2885 goto err_gpio_clean;
2887 /* Turn the Analog on and initialize the PHY. */
2888 phy->ops->switch_analog(dev, 1);
2889 err = b43_phy_init(dev);
2891 goto err_gpio_clean;
2893 /* Disable Interference Mitigation. */
2894 if (phy->ops->interf_mitigation)
2895 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2897 /* Select the antennae */
2898 if (phy->ops->set_rx_antenna)
2899 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2900 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2902 if (phy->type == B43_PHYTYPE_B) {
2903 value16 = b43_read16(dev, 0x005E);
2905 b43_write16(dev, 0x005E, value16);
2907 b43_write32(dev, 0x0100, 0x01000000);
2908 if (dev->sdev->id.revision < 5)
2909 b43_write32(dev, 0x010C, 0x01000000);
2911 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2912 & ~B43_MACCTL_INFRA);
2913 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2914 | B43_MACCTL_INFRA);
2916 /* Probe Response Timeout value */
2917 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2918 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2920 /* Initially set the wireless operation mode. */
2921 b43_adjust_opmode(dev);
2923 if (dev->sdev->id.revision < 3) {
2924 b43_write16(dev, 0x060E, 0x0000);
2925 b43_write16(dev, 0x0610, 0x8000);
2926 b43_write16(dev, 0x0604, 0x0000);
2927 b43_write16(dev, 0x0606, 0x0200);
2929 b43_write32(dev, 0x0188, 0x80000000);
2930 b43_write32(dev, 0x018C, 0x02000000);
2932 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2933 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2934 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2935 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2936 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2937 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2938 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2940 b43_mac_phy_clock_set(dev, true);
2942 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2943 dev->sdev->bus->chipco.fast_pwrup_delay);
2946 b43dbg(dev->wl, "Chip initialized\n");
2951 b43_gpio_cleanup(dev);
2955 static void b43_periodic_every60sec(struct b43_wldev *dev)
2957 const struct b43_phy_operations *ops = dev->phy.ops;
2959 if (ops->pwork_60sec)
2960 ops->pwork_60sec(dev);
2962 /* Force check the TX power emission now. */
2963 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2966 static void b43_periodic_every30sec(struct b43_wldev *dev)
2968 /* Update device statistics. */
2969 b43_calculate_link_quality(dev);
2972 static void b43_periodic_every15sec(struct b43_wldev *dev)
2974 struct b43_phy *phy = &dev->phy;
2977 if (dev->fw.opensource) {
2978 /* Check if the firmware is still alive.
2979 * It will reset the watchdog counter to 0 in its idle loop. */
2980 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2981 if (unlikely(wdr)) {
2982 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2983 b43_controller_restart(dev, "Firmware watchdog");
2986 b43_shm_write16(dev, B43_SHM_SCRATCH,
2987 B43_WATCHDOG_REG, 1);
2991 if (phy->ops->pwork_15sec)
2992 phy->ops->pwork_15sec(dev);
2994 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2998 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3001 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3002 dev->irq_count / 15,
3004 dev->rx_count / 15);
3008 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3009 if (dev->irq_bit_count[i]) {
3010 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3011 dev->irq_bit_count[i] / 15, i, (1 << i));
3012 dev->irq_bit_count[i] = 0;
3019 static void do_periodic_work(struct b43_wldev *dev)
3023 state = dev->periodic_state;
3025 b43_periodic_every60sec(dev);
3027 b43_periodic_every30sec(dev);
3028 b43_periodic_every15sec(dev);
3031 /* Periodic work locking policy:
3032 * The whole periodic work handler is protected by
3033 * wl->mutex. If another lock is needed somewhere in the
3034 * pwork callchain, it's acquired in-place, where it's needed.
3036 static void b43_periodic_work_handler(struct work_struct *work)
3038 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3039 periodic_work.work);
3040 struct b43_wl *wl = dev->wl;
3041 unsigned long delay;
3043 mutex_lock(&wl->mutex);
3045 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3047 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3050 do_periodic_work(dev);
3052 dev->periodic_state++;
3054 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3055 delay = msecs_to_jiffies(50);
3057 delay = round_jiffies_relative(HZ * 15);
3058 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3060 mutex_unlock(&wl->mutex);
3063 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3065 struct delayed_work *work = &dev->periodic_work;
3067 dev->periodic_state = 0;
3068 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3069 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3072 /* Check if communication with the device works correctly. */
3073 static int b43_validate_chipaccess(struct b43_wldev *dev)
3075 u32 v, backup0, backup4;
3077 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3078 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3080 /* Check for read/write and endianness problems. */
3081 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3082 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3084 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3085 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3088 /* Check if unaligned 32bit SHM_SHARED access works properly.
3089 * However, don't bail out on failure, because it's noncritical. */
3090 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3091 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3092 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3093 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3094 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3095 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3096 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3097 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3098 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3099 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3100 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3101 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3103 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3104 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3106 if ((dev->sdev->id.revision >= 3) && (dev->sdev->id.revision <= 10)) {
3107 /* The 32bit register shadows the two 16bit registers
3108 * with update sideeffects. Validate this. */
3109 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3110 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3111 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3113 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3116 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3118 v = b43_read32(dev, B43_MMIO_MACCTL);
3119 v |= B43_MACCTL_GMODE;
3120 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3125 b43err(dev->wl, "Failed to validate the chipaccess\n");
3129 static void b43_security_init(struct b43_wldev *dev)
3131 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3132 /* KTP is a word address, but we address SHM bytewise.
3133 * So multiply by two.
3136 /* Number of RCMTA address slots */
3137 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3138 /* Clear the key memory. */
3139 b43_clear_keys(dev);
3142 #ifdef CONFIG_B43_HWRNG
3143 static int b43_rng_read(struct hwrng *rng, u32 *data)
3145 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3146 struct b43_wldev *dev;
3147 int count = -ENODEV;
3149 mutex_lock(&wl->mutex);
3150 dev = wl->current_dev;
3151 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3152 *data = b43_read16(dev, B43_MMIO_RNG);
3153 count = sizeof(u16);
3155 mutex_unlock(&wl->mutex);
3159 #endif /* CONFIG_B43_HWRNG */
3161 static void b43_rng_exit(struct b43_wl *wl)
3163 #ifdef CONFIG_B43_HWRNG
3164 if (wl->rng_initialized)
3165 hwrng_unregister(&wl->rng);
3166 #endif /* CONFIG_B43_HWRNG */
3169 static int b43_rng_init(struct b43_wl *wl)
3173 #ifdef CONFIG_B43_HWRNG
3174 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3175 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3176 wl->rng.name = wl->rng_name;
3177 wl->rng.data_read = b43_rng_read;
3178 wl->rng.priv = (unsigned long)wl;
3179 wl->rng_initialized = 1;
3180 err = hwrng_register(&wl->rng);
3182 wl->rng_initialized = 0;
3183 b43err(wl, "Failed to register the random "
3184 "number generator (%d)\n", err);
3186 #endif /* CONFIG_B43_HWRNG */
3191 static void b43_tx_work(struct work_struct *work)
3193 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3194 struct b43_wldev *dev;
3195 struct sk_buff *skb;
3198 mutex_lock(&wl->mutex);
3199 dev = wl->current_dev;
3200 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3201 mutex_unlock(&wl->mutex);
3205 while (skb_queue_len(&wl->tx_queue)) {
3206 skb = skb_dequeue(&wl->tx_queue);
3208 if (b43_using_pio_transfers(dev))
3209 err = b43_pio_tx(dev, skb);
3211 err = b43_dma_tx(dev, skb);
3213 dev_kfree_skb(skb); /* Drop it */
3219 mutex_unlock(&wl->mutex);
3222 static void b43_op_tx(struct ieee80211_hw *hw,
3223 struct sk_buff *skb)
3225 struct b43_wl *wl = hw_to_b43_wl(hw);
3227 if (unlikely(skb->len < 2 + 2 + 6)) {
3228 /* Too short, this can't be a valid frame. */
3229 dev_kfree_skb_any(skb);
3232 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3234 skb_queue_tail(&wl->tx_queue, skb);
3235 ieee80211_queue_work(wl->hw, &wl->tx_work);
3238 static void b43_qos_params_upload(struct b43_wldev *dev,
3239 const struct ieee80211_tx_queue_params *p,
3242 u16 params[B43_NR_QOSPARAMS];
3246 if (!dev->qos_enabled)
3249 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3251 memset(¶ms, 0, sizeof(params));
3253 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3254 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3255 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3256 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3257 params[B43_QOSPARAM_AIFS] = p->aifs;
3258 params[B43_QOSPARAM_BSLOTS] = bslots;
3259 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3261 for (i = 0; i < ARRAY_SIZE(params); i++) {
3262 if (i == B43_QOSPARAM_STATUS) {
3263 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3264 shm_offset + (i * 2));
3265 /* Mark the parameters as updated. */
3267 b43_shm_write16(dev, B43_SHM_SHARED,
3268 shm_offset + (i * 2),
3271 b43_shm_write16(dev, B43_SHM_SHARED,
3272 shm_offset + (i * 2),
3278 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3279 static const u16 b43_qos_shm_offsets[] = {
3280 /* [mac80211-queue-nr] = SHM_OFFSET, */
3281 [0] = B43_QOS_VOICE,
3282 [1] = B43_QOS_VIDEO,
3283 [2] = B43_QOS_BESTEFFORT,
3284 [3] = B43_QOS_BACKGROUND,
3287 /* Update all QOS parameters in hardware. */
3288 static void b43_qos_upload_all(struct b43_wldev *dev)
3290 struct b43_wl *wl = dev->wl;
3291 struct b43_qos_params *params;
3294 if (!dev->qos_enabled)
3297 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3298 ARRAY_SIZE(wl->qos_params));
3300 b43_mac_suspend(dev);
3301 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3302 params = &(wl->qos_params[i]);
3303 b43_qos_params_upload(dev, &(params->p),
3304 b43_qos_shm_offsets[i]);
3306 b43_mac_enable(dev);
3309 static void b43_qos_clear(struct b43_wl *wl)
3311 struct b43_qos_params *params;
3314 /* Initialize QoS parameters to sane defaults. */
3316 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3317 ARRAY_SIZE(wl->qos_params));
3319 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3320 params = &(wl->qos_params[i]);
3322 switch (b43_qos_shm_offsets[i]) {
3326 params->p.cw_min = 0x0001;
3327 params->p.cw_max = 0x0001;
3332 params->p.cw_min = 0x0001;
3333 params->p.cw_max = 0x0001;
3335 case B43_QOS_BESTEFFORT:
3338 params->p.cw_min = 0x0001;
3339 params->p.cw_max = 0x03FF;
3341 case B43_QOS_BACKGROUND:
3344 params->p.cw_min = 0x0001;
3345 params->p.cw_max = 0x03FF;
3353 /* Initialize the core's QOS capabilities */
3354 static void b43_qos_init(struct b43_wldev *dev)
3356 if (!dev->qos_enabled) {
3357 /* Disable QOS support. */
3358 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3359 b43_write16(dev, B43_MMIO_IFSCTL,
3360 b43_read16(dev, B43_MMIO_IFSCTL)
3361 & ~B43_MMIO_IFSCTL_USE_EDCF);
3362 b43dbg(dev->wl, "QoS disabled\n");
3366 /* Upload the current QOS parameters. */
3367 b43_qos_upload_all(dev);
3369 /* Enable QOS support. */
3370 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3371 b43_write16(dev, B43_MMIO_IFSCTL,
3372 b43_read16(dev, B43_MMIO_IFSCTL)
3373 | B43_MMIO_IFSCTL_USE_EDCF);
3374 b43dbg(dev->wl, "QoS enabled\n");
3377 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3378 const struct ieee80211_tx_queue_params *params)
3380 struct b43_wl *wl = hw_to_b43_wl(hw);
3381 struct b43_wldev *dev;
3382 unsigned int queue = (unsigned int)_queue;
3385 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3386 /* Queue not available or don't support setting
3387 * params on this queue. Return success to not
3388 * confuse mac80211. */
3391 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3392 ARRAY_SIZE(wl->qos_params));
3394 mutex_lock(&wl->mutex);
3395 dev = wl->current_dev;
3396 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3399 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3400 b43_mac_suspend(dev);
3401 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3402 b43_qos_shm_offsets[queue]);
3403 b43_mac_enable(dev);
3407 mutex_unlock(&wl->mutex);
3412 static int b43_op_get_stats(struct ieee80211_hw *hw,
3413 struct ieee80211_low_level_stats *stats)
3415 struct b43_wl *wl = hw_to_b43_wl(hw);
3417 mutex_lock(&wl->mutex);
3418 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3419 mutex_unlock(&wl->mutex);
3424 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3426 struct b43_wl *wl = hw_to_b43_wl(hw);
3427 struct b43_wldev *dev;
3430 mutex_lock(&wl->mutex);
3431 dev = wl->current_dev;
3433 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3434 b43_tsf_read(dev, &tsf);
3438 mutex_unlock(&wl->mutex);
3443 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3445 struct b43_wl *wl = hw_to_b43_wl(hw);
3446 struct b43_wldev *dev;
3448 mutex_lock(&wl->mutex);
3449 dev = wl->current_dev;
3451 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3452 b43_tsf_write(dev, tsf);
3454 mutex_unlock(&wl->mutex);
3457 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3459 struct ssb_device *sdev = dev->sdev;
3462 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3463 tmslow &= ~B43_TMSLOW_GMODE;
3464 tmslow |= B43_TMSLOW_PHYRESET;
3465 tmslow |= SSB_TMSLOW_FGC;
3466 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3469 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3470 tmslow &= ~SSB_TMSLOW_FGC;
3471 tmslow |= B43_TMSLOW_PHYRESET;
3472 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3476 static const char *band_to_string(enum ieee80211_band band)
3479 case IEEE80211_BAND_5GHZ:
3481 case IEEE80211_BAND_2GHZ:
3490 /* Expects wl->mutex locked */
3491 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3493 struct b43_wldev *up_dev = NULL;
3494 struct b43_wldev *down_dev;
3495 struct b43_wldev *d;
3497 bool uninitialized_var(gmode);
3500 /* Find a device and PHY which supports the band. */
3501 list_for_each_entry(d, &wl->devlist, list) {
3502 switch (chan->band) {
3503 case IEEE80211_BAND_5GHZ:
3504 if (d->phy.supports_5ghz) {
3509 case IEEE80211_BAND_2GHZ:
3510 if (d->phy.supports_2ghz) {
3523 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3524 band_to_string(chan->band));
3527 if ((up_dev == wl->current_dev) &&
3528 (!!wl->current_dev->phy.gmode == !!gmode)) {
3529 /* This device is already running. */
3532 b43dbg(wl, "Switching to %s-GHz band\n",
3533 band_to_string(chan->band));
3534 down_dev = wl->current_dev;
3536 prev_status = b43_status(down_dev);
3537 /* Shutdown the currently running core. */
3538 if (prev_status >= B43_STAT_STARTED)
3539 down_dev = b43_wireless_core_stop(down_dev);
3540 if (prev_status >= B43_STAT_INITIALIZED)
3541 b43_wireless_core_exit(down_dev);
3543 if (down_dev != up_dev) {
3544 /* We switch to a different core, so we put PHY into
3545 * RESET on the old core. */
3546 b43_put_phy_into_reset(down_dev);
3549 /* Now start the new core. */
3550 up_dev->phy.gmode = gmode;
3551 if (prev_status >= B43_STAT_INITIALIZED) {
3552 err = b43_wireless_core_init(up_dev);
3554 b43err(wl, "Fatal: Could not initialize device for "
3555 "selected %s-GHz band\n",
3556 band_to_string(chan->band));
3560 if (prev_status >= B43_STAT_STARTED) {
3561 err = b43_wireless_core_start(up_dev);
3563 b43err(wl, "Fatal: Coult not start device for "
3564 "selected %s-GHz band\n",
3565 band_to_string(chan->band));
3566 b43_wireless_core_exit(up_dev);
3570 B43_WARN_ON(b43_status(up_dev) != prev_status);
3572 wl->current_dev = up_dev;
3576 /* Whoops, failed to init the new core. No core is operating now. */
3577 wl->current_dev = NULL;
3581 /* Write the short and long frame retry limit values. */
3582 static void b43_set_retry_limits(struct b43_wldev *dev,
3583 unsigned int short_retry,
3584 unsigned int long_retry)
3586 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3587 * the chip-internal counter. */
3588 short_retry = min(short_retry, (unsigned int)0xF);
3589 long_retry = min(long_retry, (unsigned int)0xF);
3591 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3593 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3597 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3599 struct b43_wl *wl = hw_to_b43_wl(hw);
3600 struct b43_wldev *dev;
3601 struct b43_phy *phy;
3602 struct ieee80211_conf *conf = &hw->conf;
3606 mutex_lock(&wl->mutex);
3608 /* Switch the band (if necessary). This might change the active core. */
3609 err = b43_switch_band(wl, conf->channel);
3611 goto out_unlock_mutex;
3612 dev = wl->current_dev;
3615 if (conf_is_ht(conf))
3617 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3619 phy->is_40mhz = false;
3621 b43_mac_suspend(dev);
3623 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3624 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3625 conf->long_frame_max_tx_count);
3626 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3628 goto out_mac_enable;
3630 /* Switch to the requested channel.
3631 * The firmware takes care of races with the TX handler. */
3632 if (conf->channel->hw_value != phy->channel)
3633 b43_switch_channel(dev, conf->channel->hw_value);
3635 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3637 /* Adjust the desired TX power level. */
3638 if (conf->power_level != 0) {
3639 if (conf->power_level != phy->desired_txpower) {
3640 phy->desired_txpower = conf->power_level;
3641 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3642 B43_TXPWR_IGNORE_TSSI);
3646 /* Antennas for RX and management frame TX. */
3647 antenna = B43_ANTENNA_DEFAULT;
3648 b43_mgmtframe_txantenna(dev, antenna);
3649 antenna = B43_ANTENNA_DEFAULT;
3650 if (phy->ops->set_rx_antenna)
3651 phy->ops->set_rx_antenna(dev, antenna);
3653 if (wl->radio_enabled != phy->radio_on) {
3654 if (wl->radio_enabled) {
3655 b43_software_rfkill(dev, false);
3656 b43info(dev->wl, "Radio turned on by software\n");
3657 if (!dev->radio_hw_enable) {
3658 b43info(dev->wl, "The hardware RF-kill button "
3659 "still turns the radio physically off. "
3660 "Press the button to turn it on.\n");
3663 b43_software_rfkill(dev, true);
3664 b43info(dev->wl, "Radio turned off by software\n");
3669 b43_mac_enable(dev);
3671 mutex_unlock(&wl->mutex);
3676 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3678 struct ieee80211_supported_band *sband =
3679 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3680 struct ieee80211_rate *rate;
3682 u16 basic, direct, offset, basic_offset, rateptr;
3684 for (i = 0; i < sband->n_bitrates; i++) {
3685 rate = &sband->bitrates[i];
3687 if (b43_is_cck_rate(rate->hw_value)) {
3688 direct = B43_SHM_SH_CCKDIRECT;
3689 basic = B43_SHM_SH_CCKBASIC;
3690 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3693 direct = B43_SHM_SH_OFDMDIRECT;
3694 basic = B43_SHM_SH_OFDMBASIC;
3695 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3699 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3701 if (b43_is_cck_rate(rate->hw_value)) {
3702 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3703 basic_offset &= 0xF;
3705 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3706 basic_offset &= 0xF;
3710 * Get the pointer that we need to point to
3711 * from the direct map
3713 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3714 direct + 2 * basic_offset);
3715 /* and write it to the basic map */
3716 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3721 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3722 struct ieee80211_vif *vif,
3723 struct ieee80211_bss_conf *conf,
3726 struct b43_wl *wl = hw_to_b43_wl(hw);
3727 struct b43_wldev *dev;
3729 mutex_lock(&wl->mutex);
3731 dev = wl->current_dev;
3732 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3733 goto out_unlock_mutex;
3735 B43_WARN_ON(wl->vif != vif);
3737 if (changed & BSS_CHANGED_BSSID) {
3739 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3741 memset(wl->bssid, 0, ETH_ALEN);
3744 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3745 if (changed & BSS_CHANGED_BEACON &&
3746 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3747 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3748 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3749 b43_update_templates(wl);
3751 if (changed & BSS_CHANGED_BSSID)
3752 b43_write_mac_bssid_templates(dev);
3755 b43_mac_suspend(dev);
3757 /* Update templates for AP/mesh mode. */
3758 if (changed & BSS_CHANGED_BEACON_INT &&
3759 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3760 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3761 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3762 b43_set_beacon_int(dev, conf->beacon_int);
3764 if (changed & BSS_CHANGED_BASIC_RATES)
3765 b43_update_basic_rates(dev, conf->basic_rates);
3767 if (changed & BSS_CHANGED_ERP_SLOT) {
3768 if (conf->use_short_slot)
3769 b43_short_slot_timing_enable(dev);
3771 b43_short_slot_timing_disable(dev);
3774 b43_mac_enable(dev);
3776 mutex_unlock(&wl->mutex);
3779 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3780 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3781 struct ieee80211_key_conf *key)
3783 struct b43_wl *wl = hw_to_b43_wl(hw);
3784 struct b43_wldev *dev;
3788 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3790 if (modparam_nohwcrypt)
3791 return -ENOSPC; /* User disabled HW-crypto */
3793 mutex_lock(&wl->mutex);
3795 dev = wl->current_dev;
3797 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3800 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3801 /* We don't have firmware for the crypto engine.
3802 * Must use software-crypto. */
3808 switch (key->cipher) {
3809 case WLAN_CIPHER_SUITE_WEP40:
3810 algorithm = B43_SEC_ALGO_WEP40;
3812 case WLAN_CIPHER_SUITE_WEP104:
3813 algorithm = B43_SEC_ALGO_WEP104;
3815 case WLAN_CIPHER_SUITE_TKIP:
3816 algorithm = B43_SEC_ALGO_TKIP;
3818 case WLAN_CIPHER_SUITE_CCMP:
3819 algorithm = B43_SEC_ALGO_AES;
3825 index = (u8) (key->keyidx);
3831 if (algorithm == B43_SEC_ALGO_TKIP &&
3832 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3833 !modparam_hwtkip)) {
3834 /* We support only pairwise key */
3839 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3840 if (WARN_ON(!sta)) {
3844 /* Pairwise key with an assigned MAC address. */
3845 err = b43_key_write(dev, -1, algorithm,
3846 key->key, key->keylen,
3850 err = b43_key_write(dev, index, algorithm,
3851 key->key, key->keylen, NULL, key);
3856 if (algorithm == B43_SEC_ALGO_WEP40 ||
3857 algorithm == B43_SEC_ALGO_WEP104) {
3858 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3861 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3863 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3864 if (algorithm == B43_SEC_ALGO_TKIP)
3865 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3868 err = b43_key_clear(dev, key->hw_key_idx);
3879 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3881 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3882 sta ? sta->addr : bcast_addr);
3883 b43_dump_keymemory(dev);
3885 mutex_unlock(&wl->mutex);
3890 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3891 unsigned int changed, unsigned int *fflags,
3894 struct b43_wl *wl = hw_to_b43_wl(hw);
3895 struct b43_wldev *dev;
3897 mutex_lock(&wl->mutex);
3898 dev = wl->current_dev;
3904 *fflags &= FIF_PROMISC_IN_BSS |
3910 FIF_BCN_PRBRESP_PROMISC;
3912 changed &= FIF_PROMISC_IN_BSS |
3918 FIF_BCN_PRBRESP_PROMISC;
3920 wl->filter_flags = *fflags;
3922 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3923 b43_adjust_opmode(dev);
3926 mutex_unlock(&wl->mutex);
3929 /* Locking: wl->mutex
3930 * Returns the current dev. This might be different from the passed in dev,
3931 * because the core might be gone away while we unlocked the mutex. */
3932 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
3934 struct b43_wl *wl = dev->wl;
3935 struct b43_wldev *orig_dev;
3939 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3942 /* Cancel work. Unlock to avoid deadlocks. */
3943 mutex_unlock(&wl->mutex);
3944 cancel_delayed_work_sync(&dev->periodic_work);
3945 cancel_work_sync(&wl->tx_work);
3946 mutex_lock(&wl->mutex);
3947 dev = wl->current_dev;
3948 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3949 /* Whoops, aliens ate up the device while we were unlocked. */
3953 /* Disable interrupts on the device. */
3954 b43_set_status(dev, B43_STAT_INITIALIZED);
3955 if (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) {
3956 /* wl->mutex is locked. That is enough. */
3957 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3958 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3960 spin_lock_irq(&wl->hardirq_lock);
3961 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3962 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3963 spin_unlock_irq(&wl->hardirq_lock);
3965 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
3967 mutex_unlock(&wl->mutex);
3968 if (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) {
3969 b43_sdio_free_irq(dev);
3971 synchronize_irq(dev->sdev->irq);
3972 free_irq(dev->sdev->irq, dev);
3974 mutex_lock(&wl->mutex);
3975 dev = wl->current_dev;
3978 if (dev != orig_dev) {
3979 if (b43_status(dev) >= B43_STAT_STARTED)
3983 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
3984 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
3986 /* Drain the TX queue */
3987 while (skb_queue_len(&wl->tx_queue))
3988 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3990 b43_mac_suspend(dev);
3992 b43dbg(wl, "Wireless interface stopped\n");
3997 /* Locking: wl->mutex */
3998 static int b43_wireless_core_start(struct b43_wldev *dev)
4002 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4004 drain_txstatus_queue(dev);
4005 if (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) {
4006 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4008 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4012 err = request_threaded_irq(dev->sdev->irq, b43_interrupt_handler,
4013 b43_interrupt_thread_handler,
4014 IRQF_SHARED, KBUILD_MODNAME, dev);
4016 b43err(dev->wl, "Cannot request IRQ-%d\n",
4022 /* We are ready to run. */
4023 ieee80211_wake_queues(dev->wl->hw);
4024 b43_set_status(dev, B43_STAT_STARTED);
4026 /* Start data flow (TX/RX). */
4027 b43_mac_enable(dev);
4028 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4030 /* Start maintainance work */
4031 b43_periodic_tasks_setup(dev);
4035 b43dbg(dev->wl, "Wireless interface started\n");
4040 /* Get PHY and RADIO versioning numbers */
4041 static int b43_phy_versioning(struct b43_wldev *dev)
4043 struct b43_phy *phy = &dev->phy;
4051 int unsupported = 0;
4053 /* Get PHY versioning */
4054 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4055 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4056 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4057 phy_rev = (tmp & B43_PHYVER_VERSION);
4064 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4072 #ifdef CONFIG_B43_PHY_N
4078 #ifdef CONFIG_B43_PHY_LP
4079 case B43_PHYTYPE_LP:
4088 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4089 "(Analog %u, Type %u, Revision %u)\n",
4090 analog_type, phy_type, phy_rev);
4093 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4094 analog_type, phy_type, phy_rev);
4096 /* Get RADIO versioning */
4097 if (dev->sdev->bus->chip_id == 0x4317) {
4098 if (dev->sdev->bus->chip_rev == 0)
4100 else if (dev->sdev->bus->chip_rev == 1)
4105 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4106 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4107 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4108 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4110 radio_manuf = (tmp & 0x00000FFF);
4111 radio_ver = (tmp & 0x0FFFF000) >> 12;
4112 radio_rev = (tmp & 0xF0000000) >> 28;
4113 if (radio_manuf != 0x17F /* Broadcom */)
4117 if (radio_ver != 0x2060)
4121 if (radio_manuf != 0x17F)
4125 if ((radio_ver & 0xFFF0) != 0x2050)
4129 if (radio_ver != 0x2050)
4133 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4136 case B43_PHYTYPE_LP:
4137 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4144 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4145 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4146 radio_manuf, radio_ver, radio_rev);
4149 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4150 radio_manuf, radio_ver, radio_rev);
4152 phy->radio_manuf = radio_manuf;
4153 phy->radio_ver = radio_ver;
4154 phy->radio_rev = radio_rev;
4156 phy->analog = analog_type;
4157 phy->type = phy_type;
4163 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4164 struct b43_phy *phy)
4166 phy->hardware_power_control = !!modparam_hwpctl;
4167 phy->next_txpwr_check_time = jiffies;
4168 /* PHY TX errors counter. */
4169 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4172 phy->phy_locked = 0;
4173 phy->radio_locked = 0;
4177 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4181 /* Assume the radio is enabled. If it's not enabled, the state will
4182 * immediately get fixed on the first periodic work run. */
4183 dev->radio_hw_enable = 1;
4186 memset(&dev->stats, 0, sizeof(dev->stats));
4188 setup_struct_phy_for_init(dev, &dev->phy);
4190 /* IRQ related flags */
4191 dev->irq_reason = 0;
4192 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4193 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4194 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4195 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4197 dev->mac_suspended = 1;
4199 /* Noise calculation context */
4200 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4203 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4205 struct ssb_sprom *sprom = &dev->sdev->bus->sprom;
4208 if (!modparam_btcoex)
4210 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4212 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4215 hf = b43_hf_read(dev);
4216 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4217 hf |= B43_HF_BTCOEXALT;
4219 hf |= B43_HF_BTCOEX;
4220 b43_hf_write(dev, hf);
4223 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4225 if (!modparam_btcoex)
4230 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4232 struct ssb_bus *bus = dev->sdev->bus;
4235 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4236 (bus->chip_id == 0x4312)) {
4237 tmp = ssb_read32(dev->sdev, SSB_IMCFGLO);
4238 tmp &= ~SSB_IMCFGLO_REQTO;
4239 tmp &= ~SSB_IMCFGLO_SERTO;
4241 ssb_write32(dev->sdev, SSB_IMCFGLO, tmp);
4242 ssb_commit_settings(bus);
4246 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4250 /* The time value is in microseconds. */
4251 if (dev->phy.type == B43_PHYTYPE_A)
4255 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4257 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4258 pu_delay = max(pu_delay, (u16)2400);
4260 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4263 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4264 static void b43_set_pretbtt(struct b43_wldev *dev)
4268 /* The time value is in microseconds. */
4269 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4272 if (dev->phy.type == B43_PHYTYPE_A)
4277 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4278 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4281 /* Shutdown a wireless core */
4282 /* Locking: wl->mutex */
4283 static void b43_wireless_core_exit(struct b43_wldev *dev)
4287 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4288 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4291 /* Unregister HW RNG driver */
4292 b43_rng_exit(dev->wl);
4294 b43_set_status(dev, B43_STAT_UNINIT);
4296 /* Stop the microcode PSM. */
4297 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4298 macctl &= ~B43_MACCTL_PSM_RUN;
4299 macctl |= B43_MACCTL_PSM_JMP0;
4300 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4305 dev->phy.ops->switch_analog(dev, 0);
4306 if (dev->wl->current_beacon) {
4307 dev_kfree_skb_any(dev->wl->current_beacon);
4308 dev->wl->current_beacon = NULL;
4311 ssb_device_disable(dev->sdev, 0);
4312 ssb_bus_may_powerdown(dev->sdev->bus);
4315 /* Initialize a wireless core */
4316 static int b43_wireless_core_init(struct b43_wldev *dev)
4318 struct ssb_bus *bus = dev->sdev->bus;
4319 struct ssb_sprom *sprom = &bus->sprom;
4320 struct b43_phy *phy = &dev->phy;
4325 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4327 err = ssb_bus_powerup(bus, 0);
4330 if (!ssb_device_is_enabled(dev->sdev)) {
4331 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4332 b43_wireless_core_reset(dev, tmp);
4335 /* Reset all data structures. */
4336 setup_struct_wldev_for_init(dev);
4337 phy->ops->prepare_structs(dev);
4339 /* Enable IRQ routing to this device. */
4340 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->sdev);
4342 b43_imcfglo_timeouts_workaround(dev);
4343 b43_bluetooth_coext_disable(dev);
4344 if (phy->ops->prepare_hardware) {
4345 err = phy->ops->prepare_hardware(dev);
4349 err = b43_chip_init(dev);
4352 b43_shm_write16(dev, B43_SHM_SHARED,
4353 B43_SHM_SH_WLCOREREV, dev->sdev->id.revision);
4354 hf = b43_hf_read(dev);
4355 if (phy->type == B43_PHYTYPE_G) {
4359 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4360 hf |= B43_HF_OFDMPABOOST;
4362 if (phy->radio_ver == 0x2050) {
4363 if (phy->radio_rev == 6)
4364 hf |= B43_HF_4318TSSI;
4365 if (phy->radio_rev < 6)
4366 hf |= B43_HF_VCORECALC;
4368 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4369 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4370 #ifdef CONFIG_SSB_DRIVER_PCICORE
4371 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4372 (bus->pcicore.dev->id.revision <= 10))
4373 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4375 hf &= ~B43_HF_SKCFPUP;
4376 b43_hf_write(dev, hf);
4378 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4379 B43_DEFAULT_LONG_RETRY_LIMIT);
4380 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4381 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4383 /* Disable sending probe responses from firmware.
4384 * Setting the MaxTime to one usec will always trigger
4385 * a timeout, so we never send any probe resp.
4386 * A timeout of zero is infinite. */
4387 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4389 b43_rate_memory_init(dev);
4390 b43_set_phytxctl_defaults(dev);
4392 /* Minimum Contention Window */
4393 if (phy->type == B43_PHYTYPE_B)
4394 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4396 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4397 /* Maximum Contention Window */
4398 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4400 if ((dev->sdev->bus->bustype == SSB_BUSTYPE_PCMCIA) ||
4401 (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) ||
4403 dev->__using_pio_transfers = 1;
4404 err = b43_pio_init(dev);
4406 dev->__using_pio_transfers = 0;
4407 err = b43_dma_init(dev);
4412 b43_set_synth_pu_delay(dev, 1);
4413 b43_bluetooth_coext_enable(dev);
4415 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4416 b43_upload_card_macaddress(dev);
4417 b43_security_init(dev);
4419 ieee80211_wake_queues(dev->wl->hw);
4421 b43_set_status(dev, B43_STAT_INITIALIZED);
4423 /* Register HW RNG driver */
4424 b43_rng_init(dev->wl);
4432 ssb_bus_may_powerdown(bus);
4433 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4437 static int b43_op_add_interface(struct ieee80211_hw *hw,
4438 struct ieee80211_vif *vif)
4440 struct b43_wl *wl = hw_to_b43_wl(hw);
4441 struct b43_wldev *dev;
4442 int err = -EOPNOTSUPP;
4444 /* TODO: allow WDS/AP devices to coexist */
4446 if (vif->type != NL80211_IFTYPE_AP &&
4447 vif->type != NL80211_IFTYPE_MESH_POINT &&
4448 vif->type != NL80211_IFTYPE_STATION &&
4449 vif->type != NL80211_IFTYPE_WDS &&
4450 vif->type != NL80211_IFTYPE_ADHOC)
4453 mutex_lock(&wl->mutex);
4455 goto out_mutex_unlock;
4457 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4459 dev = wl->current_dev;
4462 wl->if_type = vif->type;
4463 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4465 b43_adjust_opmode(dev);
4466 b43_set_pretbtt(dev);
4467 b43_set_synth_pu_delay(dev, 0);
4468 b43_upload_card_macaddress(dev);
4472 mutex_unlock(&wl->mutex);
4477 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4478 struct ieee80211_vif *vif)
4480 struct b43_wl *wl = hw_to_b43_wl(hw);
4481 struct b43_wldev *dev = wl->current_dev;
4483 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4485 mutex_lock(&wl->mutex);
4487 B43_WARN_ON(!wl->operating);
4488 B43_WARN_ON(wl->vif != vif);
4493 b43_adjust_opmode(dev);
4494 memset(wl->mac_addr, 0, ETH_ALEN);
4495 b43_upload_card_macaddress(dev);
4497 mutex_unlock(&wl->mutex);
4500 static int b43_op_start(struct ieee80211_hw *hw)
4502 struct b43_wl *wl = hw_to_b43_wl(hw);
4503 struct b43_wldev *dev = wl->current_dev;
4507 /* Kill all old instance specific information to make sure
4508 * the card won't use it in the short timeframe between start
4509 * and mac80211 reconfiguring it. */
4510 memset(wl->bssid, 0, ETH_ALEN);
4511 memset(wl->mac_addr, 0, ETH_ALEN);
4512 wl->filter_flags = 0;
4513 wl->radiotap_enabled = 0;
4515 wl->beacon0_uploaded = 0;
4516 wl->beacon1_uploaded = 0;
4517 wl->beacon_templates_virgin = 1;
4518 wl->radio_enabled = 1;
4520 mutex_lock(&wl->mutex);
4522 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4523 err = b43_wireless_core_init(dev);
4525 goto out_mutex_unlock;
4529 if (b43_status(dev) < B43_STAT_STARTED) {
4530 err = b43_wireless_core_start(dev);
4533 b43_wireless_core_exit(dev);
4534 goto out_mutex_unlock;
4538 /* XXX: only do if device doesn't support rfkill irq */
4539 wiphy_rfkill_start_polling(hw->wiphy);
4542 mutex_unlock(&wl->mutex);
4547 static void b43_op_stop(struct ieee80211_hw *hw)
4549 struct b43_wl *wl = hw_to_b43_wl(hw);
4550 struct b43_wldev *dev = wl->current_dev;
4552 cancel_work_sync(&(wl->beacon_update_trigger));
4554 mutex_lock(&wl->mutex);
4555 if (b43_status(dev) >= B43_STAT_STARTED) {
4556 dev = b43_wireless_core_stop(dev);
4560 b43_wireless_core_exit(dev);
4561 wl->radio_enabled = 0;
4564 mutex_unlock(&wl->mutex);
4566 cancel_work_sync(&(wl->txpower_adjust_work));
4569 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4570 struct ieee80211_sta *sta, bool set)
4572 struct b43_wl *wl = hw_to_b43_wl(hw);
4574 /* FIXME: add locking */
4575 b43_update_templates(wl);
4580 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4581 struct ieee80211_vif *vif,
4582 enum sta_notify_cmd notify_cmd,
4583 struct ieee80211_sta *sta)
4585 struct b43_wl *wl = hw_to_b43_wl(hw);
4587 B43_WARN_ON(!vif || wl->vif != vif);
4590 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4592 struct b43_wl *wl = hw_to_b43_wl(hw);
4593 struct b43_wldev *dev;
4595 mutex_lock(&wl->mutex);
4596 dev = wl->current_dev;
4597 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4598 /* Disable CFP update during scan on other channels. */
4599 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4601 mutex_unlock(&wl->mutex);
4604 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4606 struct b43_wl *wl = hw_to_b43_wl(hw);
4607 struct b43_wldev *dev;
4609 mutex_lock(&wl->mutex);
4610 dev = wl->current_dev;
4611 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4612 /* Re-enable CFP update. */
4613 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4615 mutex_unlock(&wl->mutex);
4618 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4619 struct survey_info *survey)
4621 struct b43_wl *wl = hw_to_b43_wl(hw);
4622 struct b43_wldev *dev = wl->current_dev;
4623 struct ieee80211_conf *conf = &hw->conf;
4628 survey->channel = conf->channel;
4629 survey->filled = SURVEY_INFO_NOISE_DBM;
4630 survey->noise = dev->stats.link_noise;
4635 static const struct ieee80211_ops b43_hw_ops = {
4637 .conf_tx = b43_op_conf_tx,
4638 .add_interface = b43_op_add_interface,
4639 .remove_interface = b43_op_remove_interface,
4640 .config = b43_op_config,
4641 .bss_info_changed = b43_op_bss_info_changed,
4642 .configure_filter = b43_op_configure_filter,
4643 .set_key = b43_op_set_key,
4644 .update_tkip_key = b43_op_update_tkip_key,
4645 .get_stats = b43_op_get_stats,
4646 .get_tsf = b43_op_get_tsf,
4647 .set_tsf = b43_op_set_tsf,
4648 .start = b43_op_start,
4649 .stop = b43_op_stop,
4650 .set_tim = b43_op_beacon_set_tim,
4651 .sta_notify = b43_op_sta_notify,
4652 .sw_scan_start = b43_op_sw_scan_start_notifier,
4653 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4654 .get_survey = b43_op_get_survey,
4655 .rfkill_poll = b43_rfkill_poll,
4658 /* Hard-reset the chip. Do not call this directly.
4659 * Use b43_controller_restart()
4661 static void b43_chip_reset(struct work_struct *work)
4663 struct b43_wldev *dev =
4664 container_of(work, struct b43_wldev, restart_work);
4665 struct b43_wl *wl = dev->wl;
4669 mutex_lock(&wl->mutex);
4671 prev_status = b43_status(dev);
4672 /* Bring the device down... */
4673 if (prev_status >= B43_STAT_STARTED) {
4674 dev = b43_wireless_core_stop(dev);
4680 if (prev_status >= B43_STAT_INITIALIZED)
4681 b43_wireless_core_exit(dev);
4683 /* ...and up again. */
4684 if (prev_status >= B43_STAT_INITIALIZED) {
4685 err = b43_wireless_core_init(dev);
4689 if (prev_status >= B43_STAT_STARTED) {
4690 err = b43_wireless_core_start(dev);
4692 b43_wireless_core_exit(dev);
4698 wl->current_dev = NULL; /* Failed to init the dev. */
4699 mutex_unlock(&wl->mutex);
4701 b43err(wl, "Controller restart FAILED\n");
4703 b43info(wl, "Controller restarted\n");
4706 static int b43_setup_bands(struct b43_wldev *dev,
4707 bool have_2ghz_phy, bool have_5ghz_phy)
4709 struct ieee80211_hw *hw = dev->wl->hw;
4712 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4713 if (dev->phy.type == B43_PHYTYPE_N) {
4715 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4718 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4721 dev->phy.supports_2ghz = have_2ghz_phy;
4722 dev->phy.supports_5ghz = have_5ghz_phy;
4727 static void b43_wireless_core_detach(struct b43_wldev *dev)
4729 /* We release firmware that late to not be required to re-request
4730 * is all the time when we reinit the core. */
4731 b43_release_firmware(dev);
4735 static int b43_wireless_core_attach(struct b43_wldev *dev)
4737 struct b43_wl *wl = dev->wl;
4738 struct ssb_bus *bus = dev->sdev->bus;
4739 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
4741 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4744 /* Do NOT do any device initialization here.
4745 * Do it in wireless_core_init() instead.
4746 * This function is for gathering basic information about the HW, only.
4747 * Also some structs may be set up here. But most likely you want to have
4748 * that in core_init(), too.
4751 err = ssb_bus_powerup(bus, 0);
4753 b43err(wl, "Bus powerup failed\n");
4756 /* Get the PHY type. */
4757 if (dev->sdev->id.revision >= 5) {
4760 tmshigh = ssb_read32(dev->sdev, SSB_TMSHIGH);
4761 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4762 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4766 dev->phy.gmode = have_2ghz_phy;
4767 dev->phy.radio_on = 1;
4768 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4769 b43_wireless_core_reset(dev, tmp);
4771 err = b43_phy_versioning(dev);
4774 /* Check if this device supports multiband. */
4776 (pdev->device != 0x4312 &&
4777 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4778 /* No multiband support. */
4781 switch (dev->phy.type) {
4785 case B43_PHYTYPE_LP: //FIXME not always!
4786 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
4797 if (dev->phy.type == B43_PHYTYPE_A) {
4799 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4803 if (1 /* disable A-PHY */) {
4804 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4805 if (dev->phy.type != B43_PHYTYPE_N &&
4806 dev->phy.type != B43_PHYTYPE_LP) {
4812 err = b43_phy_allocate(dev);
4816 dev->phy.gmode = have_2ghz_phy;
4817 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4818 b43_wireless_core_reset(dev, tmp);
4820 err = b43_validate_chipaccess(dev);
4823 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4827 /* Now set some default "current_dev" */
4828 if (!wl->current_dev)
4829 wl->current_dev = dev;
4830 INIT_WORK(&dev->restart_work, b43_chip_reset);
4832 dev->phy.ops->switch_analog(dev, 0);
4833 ssb_device_disable(dev->sdev, 0);
4834 ssb_bus_may_powerdown(bus);
4842 ssb_bus_may_powerdown(bus);
4846 static void b43_one_core_detach(struct ssb_device *dev)
4848 struct b43_wldev *wldev;
4851 /* Do not cancel ieee80211-workqueue based work here.
4852 * See comment in b43_remove(). */
4854 wldev = ssb_get_drvdata(dev);
4856 b43_debugfs_remove_device(wldev);
4857 b43_wireless_core_detach(wldev);
4858 list_del(&wldev->list);
4860 ssb_set_drvdata(dev, NULL);
4864 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4866 struct b43_wldev *wldev;
4869 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4873 wldev->use_pio = b43_modparam_pio;
4876 b43_set_status(wldev, B43_STAT_UNINIT);
4877 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4878 INIT_LIST_HEAD(&wldev->list);
4880 err = b43_wireless_core_attach(wldev);
4882 goto err_kfree_wldev;
4884 list_add(&wldev->list, &wl->devlist);
4886 ssb_set_drvdata(dev, wldev);
4887 b43_debugfs_add_device(wldev);
4897 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4898 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4899 (pdev->device == _device) && \
4900 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4901 (pdev->subsystem_device == _subdevice) )
4903 static void b43_sprom_fixup(struct ssb_bus *bus)
4905 struct pci_dev *pdev;
4907 /* boardflags workarounds */
4908 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4909 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4910 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4911 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4912 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4913 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4914 if (bus->bustype == SSB_BUSTYPE_PCI) {
4915 pdev = bus->host_pci;
4916 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4917 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4918 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4919 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4920 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4921 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4922 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4923 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4927 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4929 struct ieee80211_hw *hw = wl->hw;
4931 ssb_set_devtypedata(dev, NULL);
4932 ieee80211_free_hw(hw);
4935 static struct b43_wl *b43_wireless_init(struct ssb_device *dev)
4937 struct ssb_sprom *sprom = &dev->bus->sprom;
4938 struct ieee80211_hw *hw;
4941 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4943 b43err(NULL, "Could not allocate ieee80211 device\n");
4944 return ERR_PTR(-ENOMEM);
4946 wl = hw_to_b43_wl(hw);
4949 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4950 IEEE80211_HW_SIGNAL_DBM;
4952 hw->wiphy->interface_modes =
4953 BIT(NL80211_IFTYPE_AP) |
4954 BIT(NL80211_IFTYPE_MESH_POINT) |
4955 BIT(NL80211_IFTYPE_STATION) |
4956 BIT(NL80211_IFTYPE_WDS) |
4957 BIT(NL80211_IFTYPE_ADHOC);
4959 hw->queues = modparam_qos ? 4 : 1;
4960 wl->mac80211_initially_registered_queues = hw->queues;
4962 SET_IEEE80211_DEV(hw, dev->dev);
4963 if (is_valid_ether_addr(sprom->et1mac))
4964 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4966 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4968 /* Initialize struct b43_wl */
4970 mutex_init(&wl->mutex);
4971 spin_lock_init(&wl->hardirq_lock);
4972 INIT_LIST_HEAD(&wl->devlist);
4973 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4974 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4975 INIT_WORK(&wl->tx_work, b43_tx_work);
4976 skb_queue_head_init(&wl->tx_queue);
4978 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4979 dev->bus->chip_id, dev->id.revision);
4983 static int b43_ssb_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4989 wl = ssb_get_devtypedata(dev);
4991 /* Probing the first core. Must setup common struct b43_wl */
4993 b43_sprom_fixup(dev->bus);
4994 wl = b43_wireless_init(dev);
4999 ssb_set_devtypedata(dev, wl);
5000 B43_WARN_ON(ssb_get_devtypedata(dev) != wl);
5002 err = b43_one_core_attach(dev, wl);
5004 goto err_wireless_exit;
5007 err = ieee80211_register_hw(wl->hw);
5009 goto err_one_core_detach;
5010 b43_leds_register(wl->current_dev);
5016 err_one_core_detach:
5017 b43_one_core_detach(dev);
5020 b43_wireless_exit(dev, wl);
5024 static void b43_ssb_remove(struct ssb_device *dev)
5026 struct b43_wl *wl = ssb_get_devtypedata(dev);
5027 struct b43_wldev *wldev = ssb_get_drvdata(dev);
5029 /* We must cancel any work here before unregistering from ieee80211,
5030 * as the ieee80211 unreg will destroy the workqueue. */
5031 cancel_work_sync(&wldev->restart_work);
5034 if (wl->current_dev == wldev) {
5035 /* Restore the queues count before unregistering, because firmware detect
5036 * might have modified it. Restoring is important, so the networking
5037 * stack can properly free resources. */
5038 wl->hw->queues = wl->mac80211_initially_registered_queues;
5039 b43_leds_stop(wldev);
5040 ieee80211_unregister_hw(wl->hw);
5043 b43_one_core_detach(dev);
5045 if (list_empty(&wl->devlist)) {
5046 b43_leds_unregister(wl);
5047 /* Last core on the chip unregistered.
5048 * We can destroy common struct b43_wl.
5050 b43_wireless_exit(dev, wl);
5054 /* Perform a hardware reset. This can be called from any context. */
5055 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5057 /* Must avoid requeueing, if we are in shutdown. */
5058 if (b43_status(dev) < B43_STAT_INITIALIZED)
5060 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5061 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5064 static struct ssb_driver b43_ssb_driver = {
5065 .name = KBUILD_MODNAME,
5066 .id_table = b43_ssb_tbl,
5067 .probe = b43_ssb_probe,
5068 .remove = b43_ssb_remove,
5071 static void b43_print_driverinfo(void)
5073 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5074 *feat_leds = "", *feat_sdio = "";
5076 #ifdef CONFIG_B43_PCI_AUTOSELECT
5079 #ifdef CONFIG_B43_PCMCIA
5082 #ifdef CONFIG_B43_PHY_N
5085 #ifdef CONFIG_B43_LEDS
5088 #ifdef CONFIG_B43_SDIO
5091 printk(KERN_INFO "Broadcom 43xx driver loaded "
5092 "[ Features: %s%s%s%s%s, Firmware-ID: "
5093 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5094 feat_pci, feat_pcmcia, feat_nphy,
5095 feat_leds, feat_sdio);
5098 static int __init b43_init(void)
5103 err = b43_pcmcia_init();
5106 err = b43_sdio_init();
5108 goto err_pcmcia_exit;
5109 err = ssb_driver_register(&b43_ssb_driver);
5112 b43_print_driverinfo();
5125 static void __exit b43_exit(void)
5127 ssb_driver_unregister(&b43_ssb_driver);
5133 module_init(b43_init)
5134 module_exit(b43_exit)