3 Broadcom B43 wireless driver
5 DMA ringbuffer and descriptor allocation/management
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
41 #include <linux/slab.h>
42 #include <asm/div64.h>
45 /* Required number of TX DMA slots per TX frame.
46 * This currently is 2, because we put the header and the ieee80211 frame
47 * into separate slots. */
48 #define TX_SLOTS_PER_FRAME 2
53 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
55 struct b43_dmadesc_meta **meta)
57 struct b43_dmadesc32 *desc;
59 *meta = &(ring->meta[slot]);
60 desc = ring->descbase;
63 return (struct b43_dmadesc_generic *)desc;
66 static void op32_fill_descriptor(struct b43_dmaring *ring,
67 struct b43_dmadesc_generic *desc,
68 dma_addr_t dmaaddr, u16 bufsize,
69 int start, int end, int irq)
71 struct b43_dmadesc32 *descbase = ring->descbase;
77 slot = (int)(&(desc->dma32) - descbase);
78 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
80 addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
81 addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
82 >> SSB_DMA_TRANSLATION_SHIFT;
83 addr |= ring->dev->dma.translation;
84 ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
85 if (slot == ring->nr_slots - 1)
86 ctl |= B43_DMA32_DCTL_DTABLEEND;
88 ctl |= B43_DMA32_DCTL_FRAMESTART;
90 ctl |= B43_DMA32_DCTL_FRAMEEND;
92 ctl |= B43_DMA32_DCTL_IRQ;
93 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
94 & B43_DMA32_DCTL_ADDREXT_MASK;
96 desc->dma32.control = cpu_to_le32(ctl);
97 desc->dma32.address = cpu_to_le32(addr);
100 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
102 b43_dma_write(ring, B43_DMA32_TXINDEX,
103 (u32) (slot * sizeof(struct b43_dmadesc32)));
106 static void op32_tx_suspend(struct b43_dmaring *ring)
108 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
109 | B43_DMA32_TXSUSPEND);
112 static void op32_tx_resume(struct b43_dmaring *ring)
114 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
115 & ~B43_DMA32_TXSUSPEND);
118 static int op32_get_current_rxslot(struct b43_dmaring *ring)
122 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
123 val &= B43_DMA32_RXDPTR;
125 return (val / sizeof(struct b43_dmadesc32));
128 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
130 b43_dma_write(ring, B43_DMA32_RXINDEX,
131 (u32) (slot * sizeof(struct b43_dmadesc32)));
134 static const struct b43_dma_ops dma32_ops = {
135 .idx2desc = op32_idx2desc,
136 .fill_descriptor = op32_fill_descriptor,
137 .poke_tx = op32_poke_tx,
138 .tx_suspend = op32_tx_suspend,
139 .tx_resume = op32_tx_resume,
140 .get_current_rxslot = op32_get_current_rxslot,
141 .set_current_rxslot = op32_set_current_rxslot,
146 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
148 struct b43_dmadesc_meta **meta)
150 struct b43_dmadesc64 *desc;
152 *meta = &(ring->meta[slot]);
153 desc = ring->descbase;
154 desc = &(desc[slot]);
156 return (struct b43_dmadesc_generic *)desc;
159 static void op64_fill_descriptor(struct b43_dmaring *ring,
160 struct b43_dmadesc_generic *desc,
161 dma_addr_t dmaaddr, u16 bufsize,
162 int start, int end, int irq)
164 struct b43_dmadesc64 *descbase = ring->descbase;
166 u32 ctl0 = 0, ctl1 = 0;
170 slot = (int)(&(desc->dma64) - descbase);
171 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
173 addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
174 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176 >> SSB_DMA_TRANSLATION_SHIFT;
177 addrhi |= (ring->dev->dma.translation << 1);
178 if (slot == ring->nr_slots - 1)
179 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
181 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
183 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
185 ctl0 |= B43_DMA64_DCTL0_IRQ;
186 ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
187 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
188 & B43_DMA64_DCTL1_ADDREXT_MASK;
190 desc->dma64.control0 = cpu_to_le32(ctl0);
191 desc->dma64.control1 = cpu_to_le32(ctl1);
192 desc->dma64.address_low = cpu_to_le32(addrlo);
193 desc->dma64.address_high = cpu_to_le32(addrhi);
196 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
198 b43_dma_write(ring, B43_DMA64_TXINDEX,
199 (u32) (slot * sizeof(struct b43_dmadesc64)));
202 static void op64_tx_suspend(struct b43_dmaring *ring)
204 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
205 | B43_DMA64_TXSUSPEND);
208 static void op64_tx_resume(struct b43_dmaring *ring)
210 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
211 & ~B43_DMA64_TXSUSPEND);
214 static int op64_get_current_rxslot(struct b43_dmaring *ring)
218 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
219 val &= B43_DMA64_RXSTATDPTR;
221 return (val / sizeof(struct b43_dmadesc64));
224 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
226 b43_dma_write(ring, B43_DMA64_RXINDEX,
227 (u32) (slot * sizeof(struct b43_dmadesc64)));
230 static const struct b43_dma_ops dma64_ops = {
231 .idx2desc = op64_idx2desc,
232 .fill_descriptor = op64_fill_descriptor,
233 .poke_tx = op64_poke_tx,
234 .tx_suspend = op64_tx_suspend,
235 .tx_resume = op64_tx_resume,
236 .get_current_rxslot = op64_get_current_rxslot,
237 .set_current_rxslot = op64_set_current_rxslot,
240 static inline int free_slots(struct b43_dmaring *ring)
242 return (ring->nr_slots - ring->used_slots);
245 static inline int next_slot(struct b43_dmaring *ring, int slot)
247 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
248 if (slot == ring->nr_slots - 1)
253 static inline int prev_slot(struct b43_dmaring *ring, int slot)
255 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
257 return ring->nr_slots - 1;
261 #ifdef CONFIG_B43_DEBUG
262 static void update_max_used_slots(struct b43_dmaring *ring,
263 int current_used_slots)
265 if (current_used_slots <= ring->max_used_slots)
267 ring->max_used_slots = current_used_slots;
268 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
269 b43dbg(ring->dev->wl,
270 "max_used_slots increased to %d on %s ring %d\n",
271 ring->max_used_slots,
272 ring->tx ? "TX" : "RX", ring->index);
277 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
282 /* Request a slot for usage. */
283 static inline int request_slot(struct b43_dmaring *ring)
287 B43_WARN_ON(!ring->tx);
288 B43_WARN_ON(ring->stopped);
289 B43_WARN_ON(free_slots(ring) == 0);
291 slot = next_slot(ring, ring->current_slot);
292 ring->current_slot = slot;
295 update_max_used_slots(ring, ring->used_slots);
300 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
302 static const u16 map64[] = {
303 B43_MMIO_DMA64_BASE0,
304 B43_MMIO_DMA64_BASE1,
305 B43_MMIO_DMA64_BASE2,
306 B43_MMIO_DMA64_BASE3,
307 B43_MMIO_DMA64_BASE4,
308 B43_MMIO_DMA64_BASE5,
310 static const u16 map32[] = {
311 B43_MMIO_DMA32_BASE0,
312 B43_MMIO_DMA32_BASE1,
313 B43_MMIO_DMA32_BASE2,
314 B43_MMIO_DMA32_BASE3,
315 B43_MMIO_DMA32_BASE4,
316 B43_MMIO_DMA32_BASE5,
319 if (type == B43_DMA_64BIT) {
320 B43_WARN_ON(!(controller_idx >= 0 &&
321 controller_idx < ARRAY_SIZE(map64)));
322 return map64[controller_idx];
324 B43_WARN_ON(!(controller_idx >= 0 &&
325 controller_idx < ARRAY_SIZE(map32)));
326 return map32[controller_idx];
330 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
331 unsigned char *buf, size_t len, int tx)
336 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
337 buf, len, DMA_TO_DEVICE);
339 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
340 buf, len, DMA_FROM_DEVICE);
347 void unmap_descbuffer(struct b43_dmaring *ring,
348 dma_addr_t addr, size_t len, int tx)
351 dma_unmap_single(ring->dev->dev->dma_dev,
352 addr, len, DMA_TO_DEVICE);
354 dma_unmap_single(ring->dev->dev->dma_dev,
355 addr, len, DMA_FROM_DEVICE);
360 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
361 dma_addr_t addr, size_t len)
363 B43_WARN_ON(ring->tx);
364 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
365 addr, len, DMA_FROM_DEVICE);
369 void sync_descbuffer_for_device(struct b43_dmaring *ring,
370 dma_addr_t addr, size_t len)
372 B43_WARN_ON(ring->tx);
373 dma_sync_single_for_device(ring->dev->dev->dma_dev,
374 addr, len, DMA_FROM_DEVICE);
378 void free_descriptor_buffer(struct b43_dmaring *ring,
379 struct b43_dmadesc_meta *meta)
382 dev_kfree_skb_any(meta->skb);
387 static int alloc_ringmemory(struct b43_dmaring *ring)
389 gfp_t flags = GFP_KERNEL;
391 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
392 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
393 * has shown that 4K is sufficient for the latter as long as the buffer
394 * does not cross an 8K boundary.
396 * For unknown reasons - possibly a hardware error - the BCM4311 rev
397 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
398 * which accounts for the GFP_DMA flag below.
400 * The flags here must match the flags in free_ringmemory below!
402 if (ring->type == B43_DMA_64BIT)
404 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
406 &(ring->dmabase), flags);
407 if (!ring->descbase) {
408 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
411 memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
416 static void free_ringmemory(struct b43_dmaring *ring)
418 dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
419 ring->descbase, ring->dmabase);
422 /* Reset the RX DMA channel */
423 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
424 enum b43_dmatype type)
432 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
433 b43_write32(dev, mmio_base + offset, 0);
434 for (i = 0; i < 10; i++) {
435 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
437 value = b43_read32(dev, mmio_base + offset);
438 if (type == B43_DMA_64BIT) {
439 value &= B43_DMA64_RXSTAT;
440 if (value == B43_DMA64_RXSTAT_DISABLED) {
445 value &= B43_DMA32_RXSTATE;
446 if (value == B43_DMA32_RXSTAT_DISABLED) {
454 b43err(dev->wl, "DMA RX reset timed out\n");
461 /* Reset the TX DMA channel */
462 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
463 enum b43_dmatype type)
471 for (i = 0; i < 10; i++) {
472 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
474 value = b43_read32(dev, mmio_base + offset);
475 if (type == B43_DMA_64BIT) {
476 value &= B43_DMA64_TXSTAT;
477 if (value == B43_DMA64_TXSTAT_DISABLED ||
478 value == B43_DMA64_TXSTAT_IDLEWAIT ||
479 value == B43_DMA64_TXSTAT_STOPPED)
482 value &= B43_DMA32_TXSTATE;
483 if (value == B43_DMA32_TXSTAT_DISABLED ||
484 value == B43_DMA32_TXSTAT_IDLEWAIT ||
485 value == B43_DMA32_TXSTAT_STOPPED)
490 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
491 b43_write32(dev, mmio_base + offset, 0);
492 for (i = 0; i < 10; i++) {
493 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
495 value = b43_read32(dev, mmio_base + offset);
496 if (type == B43_DMA_64BIT) {
497 value &= B43_DMA64_TXSTAT;
498 if (value == B43_DMA64_TXSTAT_DISABLED) {
503 value &= B43_DMA32_TXSTATE;
504 if (value == B43_DMA32_TXSTAT_DISABLED) {
512 b43err(dev->wl, "DMA TX reset timed out\n");
515 /* ensure the reset is completed. */
521 /* Check if a DMA mapping address is invalid. */
522 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
524 size_t buffersize, bool dma_to_device)
526 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
529 switch (ring->type) {
531 if ((u64)addr + buffersize > (1ULL << 30))
535 if ((u64)addr + buffersize > (1ULL << 32))
539 /* Currently we can't have addresses beyond
540 * 64bit in the kernel. */
544 /* The address is OK. */
548 /* We can't support this address. Unmap it again. */
549 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
554 static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
556 unsigned char *f = skb->data + ring->frameoffset;
558 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
561 static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
563 struct b43_rxhdr_fw4 *rxhdr;
564 unsigned char *frame;
566 /* This poisons the RX buffer to detect DMA failures. */
568 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
569 rxhdr->frame_len = 0;
571 B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
572 frame = skb->data + ring->frameoffset;
573 memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
576 static int setup_rx_descbuffer(struct b43_dmaring *ring,
577 struct b43_dmadesc_generic *desc,
578 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
583 B43_WARN_ON(ring->tx);
585 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
588 b43_poison_rx_buffer(ring, skb);
589 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
590 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
591 /* ugh. try to realloc in zone_dma */
592 gfp_flags |= GFP_DMA;
594 dev_kfree_skb_any(skb);
596 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
599 b43_poison_rx_buffer(ring, skb);
600 dmaaddr = map_descbuffer(ring, skb->data,
601 ring->rx_buffersize, 0);
602 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
603 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
604 dev_kfree_skb_any(skb);
610 meta->dmaaddr = dmaaddr;
611 ring->ops->fill_descriptor(ring, desc, dmaaddr,
612 ring->rx_buffersize, 0, 0, 0);
617 /* Allocate the initial descbuffers.
618 * This is used for an RX ring only.
620 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
622 int i, err = -ENOMEM;
623 struct b43_dmadesc_generic *desc;
624 struct b43_dmadesc_meta *meta;
626 for (i = 0; i < ring->nr_slots; i++) {
627 desc = ring->ops->idx2desc(ring, i, &meta);
629 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
631 b43err(ring->dev->wl,
632 "Failed to allocate initial descbuffers\n");
637 ring->used_slots = ring->nr_slots;
643 for (i--; i >= 0; i--) {
644 desc = ring->ops->idx2desc(ring, i, &meta);
646 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
647 dev_kfree_skb(meta->skb);
652 /* Do initial setup of the DMA controller.
653 * Reset the controller, write the ring busaddress
654 * and switch the "enable" bit on.
656 static int dmacontroller_setup(struct b43_dmaring *ring)
661 u32 trans = ring->dev->dma.translation;
664 if (ring->type == B43_DMA_64BIT) {
665 u64 ringbase = (u64) (ring->dmabase);
667 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
668 >> SSB_DMA_TRANSLATION_SHIFT;
669 value = B43_DMA64_TXENABLE;
670 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
671 & B43_DMA64_TXADDREXT_MASK;
672 b43_dma_write(ring, B43_DMA64_TXCTL, value);
673 b43_dma_write(ring, B43_DMA64_TXRINGLO,
674 (ringbase & 0xFFFFFFFF));
675 b43_dma_write(ring, B43_DMA64_TXRINGHI,
677 ~SSB_DMA_TRANSLATION_MASK)
680 u32 ringbase = (u32) (ring->dmabase);
682 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
683 >> SSB_DMA_TRANSLATION_SHIFT;
684 value = B43_DMA32_TXENABLE;
685 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
686 & B43_DMA32_TXADDREXT_MASK;
687 b43_dma_write(ring, B43_DMA32_TXCTL, value);
688 b43_dma_write(ring, B43_DMA32_TXRING,
689 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
693 err = alloc_initial_descbuffers(ring);
696 if (ring->type == B43_DMA_64BIT) {
697 u64 ringbase = (u64) (ring->dmabase);
699 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
700 >> SSB_DMA_TRANSLATION_SHIFT;
701 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
702 value |= B43_DMA64_RXENABLE;
703 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
704 & B43_DMA64_RXADDREXT_MASK;
705 b43_dma_write(ring, B43_DMA64_RXCTL, value);
706 b43_dma_write(ring, B43_DMA64_RXRINGLO,
707 (ringbase & 0xFFFFFFFF));
708 b43_dma_write(ring, B43_DMA64_RXRINGHI,
710 ~SSB_DMA_TRANSLATION_MASK)
712 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
713 sizeof(struct b43_dmadesc64));
715 u32 ringbase = (u32) (ring->dmabase);
717 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
718 >> SSB_DMA_TRANSLATION_SHIFT;
719 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
720 value |= B43_DMA32_RXENABLE;
721 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
722 & B43_DMA32_RXADDREXT_MASK;
723 b43_dma_write(ring, B43_DMA32_RXCTL, value);
724 b43_dma_write(ring, B43_DMA32_RXRING,
725 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
727 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
728 sizeof(struct b43_dmadesc32));
736 /* Shutdown the DMA controller. */
737 static void dmacontroller_cleanup(struct b43_dmaring *ring)
740 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
742 if (ring->type == B43_DMA_64BIT) {
743 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
744 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
746 b43_dma_write(ring, B43_DMA32_TXRING, 0);
748 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
750 if (ring->type == B43_DMA_64BIT) {
751 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
752 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
754 b43_dma_write(ring, B43_DMA32_RXRING, 0);
758 static void free_all_descbuffers(struct b43_dmaring *ring)
760 struct b43_dmadesc_meta *meta;
763 if (!ring->used_slots)
765 for (i = 0; i < ring->nr_slots; i++) {
766 /* get meta - ignore returned value */
767 ring->ops->idx2desc(ring, i, &meta);
769 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
770 B43_WARN_ON(!ring->tx);
774 unmap_descbuffer(ring, meta->dmaaddr,
777 unmap_descbuffer(ring, meta->dmaaddr,
778 ring->rx_buffersize, 0);
780 free_descriptor_buffer(ring, meta);
784 static u64 supported_dma_mask(struct b43_wldev *dev)
789 tmp = b43_read32(dev, SSB_TMSHIGH);
790 if (tmp & SSB_TMSHIGH_DMA64)
791 return DMA_BIT_MASK(64);
792 mmio_base = b43_dmacontroller_base(0, 0);
793 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
794 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
795 if (tmp & B43_DMA32_TXADDREXT_MASK)
796 return DMA_BIT_MASK(32);
798 return DMA_BIT_MASK(30);
801 static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
803 if (dmamask == DMA_BIT_MASK(30))
804 return B43_DMA_30BIT;
805 if (dmamask == DMA_BIT_MASK(32))
806 return B43_DMA_32BIT;
807 if (dmamask == DMA_BIT_MASK(64))
808 return B43_DMA_64BIT;
810 return B43_DMA_30BIT;
813 /* Main initialization function. */
815 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
816 int controller_index,
818 enum b43_dmatype type)
820 struct b43_dmaring *ring;
824 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
828 ring->nr_slots = B43_RXRING_SLOTS;
830 ring->nr_slots = B43_TXRING_SLOTS;
832 ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
836 for (i = 0; i < ring->nr_slots; i++)
837 ring->meta->skb = B43_DMA_PTR_POISON;
841 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
842 ring->index = controller_index;
843 if (type == B43_DMA_64BIT)
844 ring->ops = &dma64_ops;
846 ring->ops = &dma32_ops;
849 ring->current_slot = -1;
851 if (ring->index == 0) {
852 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
853 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
857 #ifdef CONFIG_B43_DEBUG
858 ring->last_injected_overflow = jiffies;
862 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
863 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
865 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
868 if (!ring->txhdr_cache)
871 /* test for ability to dma to txhdr_cache */
872 dma_test = dma_map_single(dev->dev->dma_dev,
877 if (b43_dma_mapping_error(ring, dma_test,
878 b43_txhdr_size(dev), 1)) {
880 kfree(ring->txhdr_cache);
881 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
883 GFP_KERNEL | GFP_DMA);
884 if (!ring->txhdr_cache)
887 dma_test = dma_map_single(dev->dev->dma_dev,
892 if (b43_dma_mapping_error(ring, dma_test,
893 b43_txhdr_size(dev), 1)) {
896 "TXHDR DMA allocation failed\n");
897 goto err_kfree_txhdr_cache;
901 dma_unmap_single(dev->dev->dma_dev,
902 dma_test, b43_txhdr_size(dev),
906 err = alloc_ringmemory(ring);
908 goto err_kfree_txhdr_cache;
909 err = dmacontroller_setup(ring);
911 goto err_free_ringmemory;
917 free_ringmemory(ring);
918 err_kfree_txhdr_cache:
919 kfree(ring->txhdr_cache);
928 #define divide(a, b) ({ \
934 #define modulo(a, b) ({ \
939 /* Main cleanup function. */
940 static void b43_destroy_dmaring(struct b43_dmaring *ring,
941 const char *ringname)
946 #ifdef CONFIG_B43_DEBUG
948 /* Print some statistics. */
949 u64 failed_packets = ring->nr_failed_tx_packets;
950 u64 succeed_packets = ring->nr_succeed_tx_packets;
951 u64 nr_packets = failed_packets + succeed_packets;
952 u64 permille_failed = 0, average_tries = 0;
955 permille_failed = divide(failed_packets * 1000, nr_packets);
957 average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
959 b43dbg(ring->dev->wl, "DMA-%u %s: "
960 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
961 "Average tries %llu.%02llu\n",
962 (unsigned int)(ring->type), ringname,
963 ring->max_used_slots,
965 (unsigned long long)failed_packets,
966 (unsigned long long)nr_packets,
967 (unsigned long long)divide(permille_failed, 10),
968 (unsigned long long)modulo(permille_failed, 10),
969 (unsigned long long)divide(average_tries, 100),
970 (unsigned long long)modulo(average_tries, 100));
974 /* Device IRQs are disabled prior entering this function,
975 * so no need to take care of concurrency with rx handler stuff.
977 dmacontroller_cleanup(ring);
978 free_all_descbuffers(ring);
979 free_ringmemory(ring);
981 kfree(ring->txhdr_cache);
986 #define destroy_ring(dma, ring) do { \
987 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
988 (dma)->ring = NULL; \
991 void b43_dma_free(struct b43_wldev *dev)
995 if (b43_using_pio_transfers(dev))
999 destroy_ring(dma, rx_ring);
1000 destroy_ring(dma, tx_ring_AC_BK);
1001 destroy_ring(dma, tx_ring_AC_BE);
1002 destroy_ring(dma, tx_ring_AC_VI);
1003 destroy_ring(dma, tx_ring_AC_VO);
1004 destroy_ring(dma, tx_ring_mcast);
1007 static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1009 u64 orig_mask = mask;
1013 /* Try to set the DMA mask. If it fails, try falling back to a
1014 * lower mask, as we can always also support a lower one. */
1016 err = dma_set_mask(dev->dev->dma_dev, mask);
1018 err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
1022 if (mask == DMA_BIT_MASK(64)) {
1023 mask = DMA_BIT_MASK(32);
1027 if (mask == DMA_BIT_MASK(32)) {
1028 mask = DMA_BIT_MASK(30);
1032 b43err(dev->wl, "The machine/kernel does not support "
1033 "the required %u-bit DMA mask\n",
1034 (unsigned int)dma_mask_to_engine_type(orig_mask));
1038 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1039 (unsigned int)dma_mask_to_engine_type(orig_mask),
1040 (unsigned int)dma_mask_to_engine_type(mask));
1046 int b43_dma_init(struct b43_wldev *dev)
1048 struct b43_dma *dma = &dev->dma;
1051 enum b43_dmatype type;
1053 dmamask = supported_dma_mask(dev);
1054 type = dma_mask_to_engine_type(dmamask);
1055 err = b43_dma_set_mask(dev, dmamask);
1059 switch (dev->dev->bus_type) {
1060 #ifdef CONFIG_B43_SSB
1062 dma->translation = ssb_dma_translation(dev->dev->sdev);
1068 /* setup TX DMA channels. */
1069 dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1070 if (!dma->tx_ring_AC_BK)
1073 dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1074 if (!dma->tx_ring_AC_BE)
1075 goto err_destroy_bk;
1077 dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1078 if (!dma->tx_ring_AC_VI)
1079 goto err_destroy_be;
1081 dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1082 if (!dma->tx_ring_AC_VO)
1083 goto err_destroy_vi;
1085 dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1086 if (!dma->tx_ring_mcast)
1087 goto err_destroy_vo;
1089 /* setup RX DMA channel. */
1090 dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1092 goto err_destroy_mcast;
1094 /* No support for the TX status DMA ring. */
1095 B43_WARN_ON(dev->dev->core_rev < 5);
1097 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1098 (unsigned int)type);
1104 destroy_ring(dma, tx_ring_mcast);
1106 destroy_ring(dma, tx_ring_AC_VO);
1108 destroy_ring(dma, tx_ring_AC_VI);
1110 destroy_ring(dma, tx_ring_AC_BE);
1112 destroy_ring(dma, tx_ring_AC_BK);
1116 /* Generate a cookie for the TX header. */
1117 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1121 /* Use the upper 4 bits of the cookie as
1122 * DMA controller ID and store the slot number
1123 * in the lower 12 bits.
1124 * Note that the cookie must never be 0, as this
1125 * is a special value used in RX path.
1126 * It can also not be 0xFFFF because that is special
1127 * for multicast frames.
1129 cookie = (((u16)ring->index + 1) << 12);
1130 B43_WARN_ON(slot & ~0x0FFF);
1131 cookie |= (u16)slot;
1136 /* Inspect a cookie and find out to which controller/slot it belongs. */
1138 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1140 struct b43_dma *dma = &dev->dma;
1141 struct b43_dmaring *ring = NULL;
1143 switch (cookie & 0xF000) {
1145 ring = dma->tx_ring_AC_BK;
1148 ring = dma->tx_ring_AC_BE;
1151 ring = dma->tx_ring_AC_VI;
1154 ring = dma->tx_ring_AC_VO;
1157 ring = dma->tx_ring_mcast;
1160 *slot = (cookie & 0x0FFF);
1161 if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1162 b43dbg(dev->wl, "TX-status contains "
1163 "invalid cookie: 0x%04X\n", cookie);
1170 static int dma_tx_fragment(struct b43_dmaring *ring,
1171 struct sk_buff *skb)
1173 const struct b43_dma_ops *ops = ring->ops;
1174 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1175 struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
1177 int slot, old_top_slot, old_used_slots;
1179 struct b43_dmadesc_generic *desc;
1180 struct b43_dmadesc_meta *meta;
1181 struct b43_dmadesc_meta *meta_hdr;
1183 size_t hdrsize = b43_txhdr_size(ring->dev);
1185 /* Important note: If the number of used DMA slots per TX frame
1186 * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1187 * the file has to be updated, too!
1190 old_top_slot = ring->current_slot;
1191 old_used_slots = ring->used_slots;
1193 /* Get a slot for the header. */
1194 slot = request_slot(ring);
1195 desc = ops->idx2desc(ring, slot, &meta_hdr);
1196 memset(meta_hdr, 0, sizeof(*meta_hdr));
1198 header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
1199 cookie = generate_cookie(ring, slot);
1200 err = b43_generate_txhdr(ring->dev, header,
1202 if (unlikely(err)) {
1203 ring->current_slot = old_top_slot;
1204 ring->used_slots = old_used_slots;
1208 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1210 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1211 ring->current_slot = old_top_slot;
1212 ring->used_slots = old_used_slots;
1215 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1218 /* Get a slot for the payload. */
1219 slot = request_slot(ring);
1220 desc = ops->idx2desc(ring, slot, &meta);
1221 memset(meta, 0, sizeof(*meta));
1224 meta->is_last_fragment = 1;
1225 priv_info->bouncebuffer = NULL;
1227 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1228 /* create a bounce buffer in zone_dma on mapping failure. */
1229 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1230 priv_info->bouncebuffer = kmemdup(skb->data, skb->len,
1231 GFP_ATOMIC | GFP_DMA);
1232 if (!priv_info->bouncebuffer) {
1233 ring->current_slot = old_top_slot;
1234 ring->used_slots = old_used_slots;
1239 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
1240 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1241 kfree(priv_info->bouncebuffer);
1242 priv_info->bouncebuffer = NULL;
1243 ring->current_slot = old_top_slot;
1244 ring->used_slots = old_used_slots;
1250 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1252 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1253 /* Tell the firmware about the cookie of the last
1254 * mcast frame, so it can clear the more-data bit in it. */
1255 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1256 B43_SHM_SH_MCASTCOOKIE, cookie);
1258 /* Now transfer the whole frame. */
1260 ops->poke_tx(ring, next_slot(ring, slot));
1264 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1269 static inline int should_inject_overflow(struct b43_dmaring *ring)
1271 #ifdef CONFIG_B43_DEBUG
1272 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1273 /* Check if we should inject another ringbuffer overflow
1274 * to test handling of this situation in the stack. */
1275 unsigned long next_overflow;
1277 next_overflow = ring->last_injected_overflow + HZ;
1278 if (time_after(jiffies, next_overflow)) {
1279 ring->last_injected_overflow = jiffies;
1280 b43dbg(ring->dev->wl,
1281 "Injecting TX ring overflow on "
1282 "DMA controller %d\n", ring->index);
1286 #endif /* CONFIG_B43_DEBUG */
1290 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1291 static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1294 struct b43_dmaring *ring;
1296 if (dev->qos_enabled) {
1297 /* 0 = highest priority */
1298 switch (queue_prio) {
1303 ring = dev->dma.tx_ring_AC_VO;
1306 ring = dev->dma.tx_ring_AC_VI;
1309 ring = dev->dma.tx_ring_AC_BE;
1312 ring = dev->dma.tx_ring_AC_BK;
1316 ring = dev->dma.tx_ring_AC_BE;
1321 int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1323 struct b43_dmaring *ring;
1324 struct ieee80211_hdr *hdr;
1326 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1328 hdr = (struct ieee80211_hdr *)skb->data;
1329 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1330 /* The multicast ring will be sent after the DTIM */
1331 ring = dev->dma.tx_ring_mcast;
1332 /* Set the more-data bit. Ucode will clear it on
1333 * the last frame for us. */
1334 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1336 /* Decide by priority where to put this frame. */
1337 ring = select_ring_by_priority(
1338 dev, skb_get_queue_mapping(skb));
1341 B43_WARN_ON(!ring->tx);
1343 if (unlikely(ring->stopped)) {
1344 /* We get here only because of a bug in mac80211.
1345 * Because of a race, one packet may be queued after
1346 * the queue is stopped, thus we got called when we shouldn't.
1347 * For now, just refuse the transmit. */
1348 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1349 b43err(dev->wl, "Packet after queue stopped\n");
1354 if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1355 /* If we get here, we have a real error with the queue
1356 * full, but queues not stopped. */
1357 b43err(dev->wl, "DMA queue overflow\n");
1362 /* Assign the queue number to the ring (if not already done before)
1363 * so TX status handling can use it. The queue to ring mapping is
1364 * static, so we don't need to store it per frame. */
1365 ring->queue_prio = skb_get_queue_mapping(skb);
1367 err = dma_tx_fragment(ring, skb);
1368 if (unlikely(err == -ENOKEY)) {
1369 /* Drop this packet, as we don't have the encryption key
1370 * anymore and must not transmit it unencrypted. */
1371 dev_kfree_skb_any(skb);
1375 if (unlikely(err)) {
1376 b43err(dev->wl, "DMA tx mapping failure\n");
1379 if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
1380 should_inject_overflow(ring)) {
1381 /* This TX ring is full. */
1382 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1384 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1385 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1393 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1394 const struct b43_txstatus *status)
1396 const struct b43_dma_ops *ops;
1397 struct b43_dmaring *ring;
1398 struct b43_dmadesc_meta *meta;
1399 int slot, firstused;
1402 ring = parse_cookie(dev, status->cookie, &slot);
1403 if (unlikely(!ring))
1405 B43_WARN_ON(!ring->tx);
1407 /* Sanity check: TX packets are processed in-order on one ring.
1408 * Check if the slot deduced from the cookie really is the first
1410 firstused = ring->current_slot - ring->used_slots + 1;
1412 firstused = ring->nr_slots + firstused;
1413 if (unlikely(slot != firstused)) {
1414 /* This possibly is a firmware bug and will result in
1415 * malfunction, memory leaks and/or stall of DMA functionality. */
1416 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1417 "Expected %d, but got %d\n",
1418 ring->index, firstused, slot);
1424 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
1425 /* get meta - ignore returned value */
1426 ops->idx2desc(ring, slot, &meta);
1428 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1429 b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1431 slot, firstused, ring->index);
1435 struct b43_private_tx_info *priv_info =
1436 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1438 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1439 kfree(priv_info->bouncebuffer);
1440 priv_info->bouncebuffer = NULL;
1442 unmap_descbuffer(ring, meta->dmaaddr,
1443 b43_txhdr_size(dev), 1);
1446 if (meta->is_last_fragment) {
1447 struct ieee80211_tx_info *info;
1449 if (unlikely(!meta->skb)) {
1450 /* This is a scatter-gather fragment of a frame, so
1451 * the skb pointer must not be NULL. */
1452 b43dbg(dev->wl, "TX status unexpected NULL skb "
1453 "at slot %d (first=%d) on ring %d\n",
1454 slot, firstused, ring->index);
1458 info = IEEE80211_SKB_CB(meta->skb);
1461 * Call back to inform the ieee80211 subsystem about
1462 * the status of the transmission.
1464 frame_succeed = b43_fill_txstatus_report(dev, info, status);
1465 #ifdef CONFIG_B43_DEBUG
1467 ring->nr_succeed_tx_packets++;
1469 ring->nr_failed_tx_packets++;
1470 ring->nr_total_packet_tries += status->frame_count;
1472 ieee80211_tx_status(dev->wl->hw, meta->skb);
1474 /* skb will be freed by ieee80211_tx_status().
1475 * Poison our pointer. */
1476 meta->skb = B43_DMA_PTR_POISON;
1478 /* No need to call free_descriptor_buffer here, as
1479 * this is only the txhdr, which is not allocated.
1481 if (unlikely(meta->skb)) {
1482 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1483 "at slot %d (first=%d) on ring %d\n",
1484 slot, firstused, ring->index);
1489 /* Everything unmapped and free'd. So it's not used anymore. */
1492 if (meta->is_last_fragment) {
1493 /* This is the last scatter-gather
1494 * fragment of the frame. We are done. */
1497 slot = next_slot(ring, slot);
1499 if (ring->stopped) {
1500 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
1501 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1503 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1504 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1509 static void dma_rx(struct b43_dmaring *ring, int *slot)
1511 const struct b43_dma_ops *ops = ring->ops;
1512 struct b43_dmadesc_generic *desc;
1513 struct b43_dmadesc_meta *meta;
1514 struct b43_rxhdr_fw4 *rxhdr;
1515 struct sk_buff *skb;
1520 desc = ops->idx2desc(ring, *slot, &meta);
1522 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1525 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1526 len = le16_to_cpu(rxhdr->frame_len);
1533 len = le16_to_cpu(rxhdr->frame_len);
1534 } while (len == 0 && i++ < 5);
1535 if (unlikely(len == 0)) {
1536 dmaaddr = meta->dmaaddr;
1537 goto drop_recycle_buffer;
1540 if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1541 /* Something went wrong with the DMA.
1542 * The device did not touch the buffer and did not overwrite the poison. */
1543 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
1544 dmaaddr = meta->dmaaddr;
1545 goto drop_recycle_buffer;
1547 if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) {
1548 /* The data did not fit into one descriptor buffer
1549 * and is split over multiple buffers.
1550 * This should never happen, as we try to allocate buffers
1551 * big enough. So simply ignore this packet.
1557 desc = ops->idx2desc(ring, *slot, &meta);
1558 /* recycle the descriptor buffer. */
1559 b43_poison_rx_buffer(ring, meta->skb);
1560 sync_descbuffer_for_device(ring, meta->dmaaddr,
1561 ring->rx_buffersize);
1562 *slot = next_slot(ring, *slot);
1564 tmp -= ring->rx_buffersize;
1568 b43err(ring->dev->wl, "DMA RX buffer too small "
1569 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1570 len, ring->rx_buffersize, cnt);
1574 dmaaddr = meta->dmaaddr;
1575 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1576 if (unlikely(err)) {
1577 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1578 goto drop_recycle_buffer;
1581 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1582 skb_put(skb, len + ring->frameoffset);
1583 skb_pull(skb, ring->frameoffset);
1585 b43_rx(ring->dev, skb, rxhdr);
1589 drop_recycle_buffer:
1590 /* Poison and recycle the RX buffer. */
1591 b43_poison_rx_buffer(ring, skb);
1592 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1595 void b43_dma_rx(struct b43_dmaring *ring)
1597 const struct b43_dma_ops *ops = ring->ops;
1598 int slot, current_slot;
1601 B43_WARN_ON(ring->tx);
1602 current_slot = ops->get_current_rxslot(ring);
1603 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1605 slot = ring->current_slot;
1606 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1607 dma_rx(ring, &slot);
1608 update_max_used_slots(ring, ++used_slots);
1611 ops->set_current_rxslot(ring, slot);
1612 ring->current_slot = slot;
1615 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1617 B43_WARN_ON(!ring->tx);
1618 ring->ops->tx_suspend(ring);
1621 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1623 B43_WARN_ON(!ring->tx);
1624 ring->ops->tx_resume(ring);
1627 void b43_dma_tx_suspend(struct b43_wldev *dev)
1629 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1630 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1631 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1632 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1633 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1634 b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1637 void b43_dma_tx_resume(struct b43_wldev *dev)
1639 b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1640 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1641 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1642 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1643 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1644 b43_power_saving_ctl_bits(dev, 0);
1647 static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1648 u16 mmio_base, bool enable)
1652 if (type == B43_DMA_64BIT) {
1653 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1654 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1656 ctl |= B43_DMA64_RXDIRECTFIFO;
1657 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1659 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1660 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1662 ctl |= B43_DMA32_RXDIRECTFIFO;
1663 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1667 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1668 * This is called from PIO code, so DMA structures are not available. */
1669 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1670 unsigned int engine_index, bool enable)
1672 enum b43_dmatype type;
1675 type = dma_mask_to_engine_type(supported_dma_mask(dev));
1677 mmio_base = b43_dmacontroller_base(type, engine_index);
1678 direct_fifo_rx(dev, type, mmio_base, enable);