drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  38         { 0 }
  39 };
  40
  41 static void ath_detach(struct ath_softc *sc);
  42
  43 /* return bus cachesize in 4B word units */
  44
  45 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  46 {
  47         u8 u8tmp;
  48
  49         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  50         *csz = (int)u8tmp;
  51
  52         /*
  53          * This check was put in to avoid "unplesant" consequences if
  54          * the bootrom has not fully initialized all PCI devices.
  55          * Sometimes the cache line size register is not set
  56          */
  57
  58         if (*csz == 0)
  59                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  60 }
  61
  62 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
  63 {
  64         if (!sc->sc_curaid)
  65                 sc->cur_rate_table = sc->hw_rate_table[mode];
  66         /*
  67          * All protection frames are transmited at 2Mb/s for
  68          * 11g, otherwise at 1Mb/s.
  69          * XXX select protection rate index from rate table.
  70          */
  71         sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
  72 }
  73
  74 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
  75 {
  76         if (chan->chanmode == CHANNEL_A)
  77                 return ATH9K_MODE_11A;
  78         else if (chan->chanmode == CHANNEL_G)
  79                 return ATH9K_MODE_11G;
  80         else if (chan->chanmode == CHANNEL_B)
  81                 return ATH9K_MODE_11B;
  82         else if (chan->chanmode == CHANNEL_A_HT20)
  83                 return ATH9K_MODE_11NA_HT20;
  84         else if (chan->chanmode == CHANNEL_G_HT20)
  85                 return ATH9K_MODE_11NG_HT20;
  86         else if (chan->chanmode == CHANNEL_A_HT40PLUS)
  87                 return ATH9K_MODE_11NA_HT40PLUS;
  88         else if (chan->chanmode == CHANNEL_A_HT40MINUS)
  89                 return ATH9K_MODE_11NA_HT40MINUS;
  90         else if (chan->chanmode == CHANNEL_G_HT40PLUS)
  91                 return ATH9K_MODE_11NG_HT40PLUS;
  92         else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  93                 return ATH9K_MODE_11NG_HT40MINUS;
  94
  95         WARN_ON(1); /* should not get here */
  96
  97         return ATH9K_MODE_11B;
  98 }
  99
 100 static void ath_update_txpow(struct ath_softc *sc)
 101 {
 102         struct ath_hal *ah = sc->sc_ah;
 103         u32 txpow;
 104
 105         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 106                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 107                 /* read back in case value is clamped */
 108                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 109                 sc->sc_curtxpow = txpow;
 110         }
 111 }
 112
 113 static u8 parse_mpdudensity(u8 mpdudensity)
 114 {
 115         /*
 116          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 117          *   0 for no restriction
 118          *   1 for 1/4 us
 119          *   2 for 1/2 us
 120          *   3 for 1 us
 121          *   4 for 2 us
 122          *   5 for 4 us
 123          *   6 for 8 us
 124          *   7 for 16 us
 125          */
 126         switch (mpdudensity) {
 127         case 0:
 128                 return 0;
 129         case 1:
 130         case 2:
 131         case 3:
 132                 /* Our lower layer calculations limit our precision to
 133                    1 microsecond */
 134                 return 1;
 135         case 4:
 136                 return 2;
 137         case 5:
 138                 return 4;
 139         case 6:
 140                 return 8;
 141         case 7:
 142                 return 16;
 143         default:
 144                 return 0;
 145         }
 146 }
 147
 148 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 149 {
 150         struct ath_rate_table *rate_table = NULL;
 151         struct ieee80211_supported_band *sband;
 152         struct ieee80211_rate *rate;
 153         int i, maxrates;
 154
 155         switch (band) {
 156         case IEEE80211_BAND_2GHZ:
 157                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 158                 break;
 159         case IEEE80211_BAND_5GHZ:
 160                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 161                 break;
 162         default:
 163                 break;
 164         }
 165
 166         if (rate_table == NULL)
 167                 return;
 168
 169         sband = &sc->sbands[band];
 170         rate = sc->rates[band];
 171
 172         if (rate_table->rate_cnt > ATH_RATE_MAX)
 173                 maxrates = ATH_RATE_MAX;
 174         else
 175                 maxrates = rate_table->rate_cnt;
 176
 177         for (i = 0; i < maxrates; i++) {
 178                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 179                 rate[i].hw_value = rate_table->info[i].ratecode;
 180                 sband->n_bitrates++;
 181                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 182                         rate[i].bitrate / 10, rate[i].hw_value);
 183         }
 184 }
 185
 186 static int ath_setup_channels(struct ath_softc *sc)
 187 {
 188         struct ath_hal *ah = sc->sc_ah;
 189         int nchan, i, a = 0, b = 0;
 190         u8 regclassids[ATH_REGCLASSIDS_MAX];
 191         u32 nregclass = 0;
 192         struct ieee80211_supported_band *band_2ghz;
 193         struct ieee80211_supported_band *band_5ghz;
 194         struct ieee80211_channel *chan_2ghz;
 195         struct ieee80211_channel *chan_5ghz;
 196         struct ath9k_channel *c;
 197
 198         /* Fill in ah->ah_channels */
 199         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 200                                       regclassids, ATH_REGCLASSIDS_MAX,
 201                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 202                 u32 rd = ah->ah_currentRD;
 203                 DPRINTF(sc, ATH_DBG_FATAL,
 204                         "Unable to collect channel list; "
 205                         "regdomain likely %u country code %u\n",
 206                         rd, CTRY_DEFAULT);
 207                 return -EINVAL;
 208         }
 209
 210         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 211         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 212         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 213         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 214
 215         for (i = 0; i < nchan; i++) {
 216                 c = &ah->ah_channels[i];
 217                 if (IS_CHAN_2GHZ(c)) {
 218                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 219                         chan_2ghz[a].center_freq = c->channel;
 220                         chan_2ghz[a].max_power = c->maxTxPower;
 221
 222                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 223                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 224                         if (c->channelFlags & CHANNEL_PASSIVE)
 225                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 226
 227                         band_2ghz->n_channels = ++a;
 228
 229                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 230                                 "channelFlags: 0x%x\n",
 231                                 c->channel, c->channelFlags);
 232                 } else if (IS_CHAN_5GHZ(c)) {
 233                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 234                         chan_5ghz[b].center_freq = c->channel;
 235                         chan_5ghz[b].max_power = c->maxTxPower;
 236
 237                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 238                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 239                         if (c->channelFlags & CHANNEL_PASSIVE)
 240                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 241
 242                         band_5ghz->n_channels = ++b;
 243
 244                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 245                                 "channelFlags: 0x%x\n",
 246                                 c->channel, c->channelFlags);
 247                 }
 248         }
 249
 250         return 0;
 251 }
 252
 253 /*
 254  * Set/change channels.  If the channel is really being changed, it's done
 255  * by reseting the chip.  To accomplish this we must first cleanup any pending
 256  * DMA, then restart stuff.
 257 */
 258 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 259 {
 260         struct ath_hal *ah = sc->sc_ah;
 261         bool fastcc = true, stopped;
 262
 263         if (sc->sc_flags & SC_OP_INVALID)
 264                 return -EIO;
 265
 266         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 267             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 268             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 269             (sc->sc_flags & SC_OP_FULL_RESET)) {
 270                 int status;
 271                 /*
 272                  * This is only performed if the channel settings have
 273                  * actually changed.
 274                  *
 275                  * To switch channels clear any pending DMA operations;
 276                  * wait long enough for the RX fifo to drain, reset the
 277                  * hardware at the new frequency, and then re-enable
 278                  * the relevant bits of the h/w.
 279                  */
 280                 ath9k_hw_set_interrupts(ah, 0);
 281                 ath_draintxq(sc, false);
 282                 stopped = ath_stoprecv(sc);
 283
 284                 /* XXX: do not flush receive queue here. We don't want
 285                  * to flush data frames already in queue because of
 286                  * changing channel. */
 287
 288                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 289                         fastcc = false;
 290
 291                 DPRINTF(sc, ATH_DBG_CONFIG,
 292                         "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
 293                         sc->sc_ah->ah_curchan->channel,
 294                         hchan->channel, hchan->channelFlags, sc->tx_chan_width);
 295
 296                 spin_lock_bh(&sc->sc_resetlock);
 297                 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
 298                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 299                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 300                         DPRINTF(sc, ATH_DBG_FATAL,
 301                                 "Unable to reset channel %u (%uMhz) "
 302                                 "flags 0x%x hal status %u\n",
 303                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 304                                                   hchan->channelFlags),
 305                                 hchan->channel, hchan->channelFlags, status);
 306                         spin_unlock_bh(&sc->sc_resetlock);
 307                         return -EIO;
 308                 }
 309                 spin_unlock_bh(&sc->sc_resetlock);
 310
 311                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 312                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 313
 314                 if (ath_startrecv(sc) != 0) {
 315                         DPRINTF(sc, ATH_DBG_FATAL,
 316                                 "Unable to restart recv logic\n");
 317                         return -EIO;
 318                 }
 319
 320                 ath_setcurmode(sc, ath_chan2mode(hchan));
 321                 ath_update_txpow(sc);
 322                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 323         }
 324         return 0;
 325 }
 326
 327 /*
 328  *  This routine performs the periodic noise floor calibration function
 329  *  that is used to adjust and optimize the chip performance.  This
 330  *  takes environmental changes (location, temperature) into account.
 331  *  When the task is complete, it reschedules itself depending on the
 332  *  appropriate interval that was calculated.
 333  */
 334 static void ath_ani_calibrate(unsigned long data)
 335 {
 336         struct ath_softc *sc;
 337         struct ath_hal *ah;
 338         bool longcal = false;
 339         bool shortcal = false;
 340         bool aniflag = false;
 341         unsigned int timestamp = jiffies_to_msecs(jiffies);
 342         u32 cal_interval;
 343
 344         sc = (struct ath_softc *)data;
 345         ah = sc->sc_ah;
 346
 347         /*
 348         * don't calibrate when we're scanning.
 349         * we are most likely not on our home channel.
 350         */
 351         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 352                 return;
 353
 354         /* Long calibration runs independently of short calibration. */
 355         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 356                 longcal = true;
 357                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 358                 sc->sc_ani.sc_longcal_timer = timestamp;
 359         }
 360
 361         /* Short calibration applies only while sc_caldone is false */
 362         if (!sc->sc_ani.sc_caldone) {
 363                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 364                     ATH_SHORT_CALINTERVAL) {
 365                         shortcal = true;
 366                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 367                         sc->sc_ani.sc_shortcal_timer = timestamp;
 368                         sc->sc_ani.sc_resetcal_timer = timestamp;
 369                 }
 370         } else {
 371                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 372                     ATH_RESTART_CALINTERVAL) {
 373                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 374                                                 &sc->sc_ani.sc_caldone);
 375                         if (sc->sc_ani.sc_caldone)
 376                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 377                 }
 378         }
 379
 380         /* Verify whether we must check ANI */
 381         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 382            ATH_ANI_POLLINTERVAL) {
 383                 aniflag = true;
 384                 sc->sc_ani.sc_checkani_timer = timestamp;
 385         }
 386
 387         /* Skip all processing if there's nothing to do. */
 388         if (longcal || shortcal || aniflag) {
 389                 /* Call ANI routine if necessary */
 390                 if (aniflag)
 391                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 392                                              ah->ah_curchan);
 393
 394                 /* Perform calibration if necessary */
 395                 if (longcal || shortcal) {
 396                         bool iscaldone = false;
 397
 398                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 399                                                sc->sc_rx_chainmask, longcal,
 400                                                &iscaldone)) {
 401                                 if (longcal)
 402                                         sc->sc_ani.sc_noise_floor =
 403                                                 ath9k_hw_getchan_noise(ah,
 404                                                                ah->ah_curchan);
 405
 406                                 DPRINTF(sc, ATH_DBG_ANI,
 407                                         "calibrate chan %u/%x nf: %d\n",
 408                                         ah->ah_curchan->channel,
 409                                         ah->ah_curchan->channelFlags,
 410                                         sc->sc_ani.sc_noise_floor);
 411                         } else {
 412                                 DPRINTF(sc, ATH_DBG_ANY,
 413                                         "calibrate chan %u/%x failed\n",
 414                                         ah->ah_curchan->channel,
 415                                         ah->ah_curchan->channelFlags);
 416                         }
 417                         sc->sc_ani.sc_caldone = iscaldone;
 418                 }
 419         }
 420
 421         /*
 422         * Set timer interval based on previous results.
 423         * The interval must be the shortest necessary to satisfy ANI,
 424         * short calibration and long calibration.
 425         */
 426         cal_interval = ATH_LONG_CALINTERVAL;
 427         if (sc->sc_ah->ah_config.enable_ani)
 428                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 429         if (!sc->sc_ani.sc_caldone)
 430                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 431
 432         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 433 }
 434
 435 /*
 436  * Update tx/rx chainmask. For legacy association,
 437  * hard code chainmask to 1x1, for 11n association, use
 438  * the chainmask configuration.
 439  */
 440 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 441 {
 442         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 443         if (is_ht) {
 444                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 445                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 446         } else {
 447                 sc->sc_tx_chainmask = 1;
 448                 sc->sc_rx_chainmask = 1;
 449         }
 450
 451         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 452                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 453 }
 454
 455 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 456 {
 457         struct ath_node *an;
 458
 459         an = (struct ath_node *)sta->drv_priv;
 460
 461         if (sc->sc_flags & SC_OP_TXAGGR)
 462                 ath_tx_node_init(sc, an);
 463
 464         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 465                              sta->ht_cap.ampdu_factor);
 466         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 467 }
 468
 469 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 470 {
 471         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 472
 473         if (sc->sc_flags & SC_OP_TXAGGR)
 474                 ath_tx_node_cleanup(sc, an);
 475 }
 476
 477 static void ath9k_tasklet(unsigned long data)
 478 {
 479         struct ath_softc *sc = (struct ath_softc *)data;
 480         u32 status = sc->sc_intrstatus;
 481
 482         if (status & ATH9K_INT_FATAL) {
 483                 /* need a chip reset */
 484                 ath_reset(sc, false);
 485                 return;
 486         } else {
 487
 488                 if (status &
 489                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 490                         spin_lock_bh(&sc->rx.rxflushlock);
 491                         ath_rx_tasklet(sc, 0);
 492                         spin_unlock_bh(&sc->rx.rxflushlock);
 493                 }
 494                 /* XXX: optimize this */
 495                 if (status & ATH9K_INT_TX)
 496                         ath_tx_tasklet(sc);
 497         }
 498
 499         /* re-enable hardware interrupt */
 500         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 501 }
 502
 503 static irqreturn_t ath_isr(int irq, void *dev)
 504 {
 505         struct ath_softc *sc = dev;
 506         struct ath_hal *ah = sc->sc_ah;
 507         enum ath9k_int status;
 508         bool sched = false;
 509
 510         do {
 511                 if (sc->sc_flags & SC_OP_INVALID) {
 512                         /*
 513                          * The hardware is not ready/present, don't
 514                          * touch anything. Note this can happen early
 515                          * on if the IRQ is shared.
 516                          */
 517                         return IRQ_NONE;
 518                 }
 519                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 520                         return IRQ_NONE;
 521                 }
 522
 523                 /*
 524                  * Figure out the reason(s) for the interrupt.  Note
 525                  * that the hal returns a pseudo-ISR that may include
 526                  * bits we haven't explicitly enabled so we mask the
 527                  * value to insure we only process bits we requested.
 528                  */
 529                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 530
 531                 status &= sc->sc_imask; /* discard unasked-for bits */
 532
 533                 /*
 534                  * If there are no status bits set, then this interrupt was not
 535                  * for me (should have been caught above).
 536                  */
 537                 if (!status)
 538                         return IRQ_NONE;
 539
 540                 sc->sc_intrstatus = status;
 541
 542                 if (status & ATH9K_INT_FATAL) {
 543                         /* need a chip reset */
 544                         sched = true;
 545                 } else if (status & ATH9K_INT_RXORN) {
 546                         /* need a chip reset */
 547                         sched = true;
 548                 } else {
 549                         if (status & ATH9K_INT_SWBA) {
 550                                 /* schedule a tasklet for beacon handling */
 551                                 tasklet_schedule(&sc->bcon_tasklet);
 552                         }
 553                         if (status & ATH9K_INT_RXEOL) {
 554                                 /*
 555                                  * NB: the hardware should re-read the link when
 556                                  *     RXE bit is written, but it doesn't work
 557                                  *     at least on older hardware revs.
 558                                  */
 559                                 sched = true;
 560                         }
 561
 562                         if (status & ATH9K_INT_TXURN)
 563                                 /* bump tx trigger level */
 564                                 ath9k_hw_updatetxtriglevel(ah, true);
 565                         /* XXX: optimize this */
 566                         if (status & ATH9K_INT_RX)
 567                                 sched = true;
 568                         if (status & ATH9K_INT_TX)
 569                                 sched = true;
 570                         if (status & ATH9K_INT_BMISS)
 571                                 sched = true;
 572                         /* carrier sense timeout */
 573                         if (status & ATH9K_INT_CST)
 574                                 sched = true;
 575                         if (status & ATH9K_INT_MIB) {
 576                                 /*
 577                                  * Disable interrupts until we service the MIB
 578                                  * interrupt; otherwise it will continue to
 579                                  * fire.
 580                                  */
 581                                 ath9k_hw_set_interrupts(ah, 0);
 582                                 /*
 583                                  * Let the hal handle the event. We assume
 584                                  * it will clear whatever condition caused
 585                                  * the interrupt.
 586                                  */
 587                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 588                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 589                         }
 590                         if (status & ATH9K_INT_TIM_TIMER) {
 591                                 if (!(ah->ah_caps.hw_caps &
 592                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 593                                         /* Clear RxAbort bit so that we can
 594                                          * receive frames */
 595                                         ath9k_hw_setrxabort(ah, 0);
 596                                         sched = true;
 597                                 }
 598                         }
 599                 }
 600         } while (0);
 601
 602         ath_debug_stat_interrupt(sc, status);
 603
 604         if (sched) {
 605                 /* turn off every interrupt except SWBA */
 606                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 607                 tasklet_schedule(&sc->intr_tq);
 608         }
 609
 610         return IRQ_HANDLED;
 611 }
 612
 613 static int ath_get_channel(struct ath_softc *sc,
 614                            struct ieee80211_channel *chan)
 615 {
 616         int i;
 617
 618         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 619                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 620                         return i;
 621         }
 622
 623         return -1;
 624 }
 625
 626 /* ext_chan_offset: (-1, 0, 1) (below, none, above) */
 627
 628 static u32 ath_get_extchanmode(struct ath_softc *sc,
 629                                struct ieee80211_channel *chan,
 630                                int ext_chan_offset,
 631                                enum ath9k_ht_macmode tx_chan_width)
 632 {
 633         u32 chanmode = 0;
 634
 635         switch (chan->band) {
 636         case IEEE80211_BAND_2GHZ:
 637                 if ((ext_chan_offset == 0) &&
 638                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 639                         chanmode = CHANNEL_G_HT20;
 640                 if ((ext_chan_offset == 1) &&
 641                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 642                         chanmode = CHANNEL_G_HT40PLUS;
 643                 if ((ext_chan_offset == -1) &&
 644                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 645                         chanmode = CHANNEL_G_HT40MINUS;
 646                 break;
 647         case IEEE80211_BAND_5GHZ:
 648                 if ((ext_chan_offset == 0) &&
 649                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 650                         chanmode = CHANNEL_A_HT20;
 651                 if ((ext_chan_offset == 1) &&
 652                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 653                         chanmode = CHANNEL_A_HT40PLUS;
 654                 if ((ext_chan_offset == -1) &&
 655                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 656                         chanmode = CHANNEL_A_HT40MINUS;
 657                 break;
 658         default:
 659                 break;
 660         }
 661
 662         return chanmode;
 663 }
 664
 665 static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
 666 {
 667         ath9k_hw_keyreset(sc->sc_ah, keyix);
 668         if (freeslot)
 669                 clear_bit(keyix, sc->sc_keymap);
 670 }
 671
 672 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 673                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 674 {
 675         bool status;
 676
 677         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 678                 keyix, hk, mac, false);
 679
 680         return status != false;
 681 }
 682
 683 static int ath_setkey_tkip(struct ath_softc *sc,
 684                            struct ieee80211_key_conf *key,
 685                            struct ath9k_keyval *hk,
 686                            const u8 *addr)
 687 {
 688         u8 *key_rxmic = NULL;
 689         u8 *key_txmic = NULL;
 690
 691         key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 692         key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 693
 694         if (addr == NULL) {
 695                 /* Group key installation */
 696                 memcpy(hk->kv_mic,  key_rxmic, sizeof(hk->kv_mic));
 697                 return ath_keyset(sc, key->keyidx, hk, addr);
 698         }
 699         if (!sc->sc_splitmic) {
 700                 /*
 701                  * data key goes at first index,
 702                  * the hal handles the MIC keys at index+64.
 703                  */
 704                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 705                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 706                 return ath_keyset(sc, key->keyidx, hk, addr);
 707         }
 708         /*
 709          * TX key goes at first index, RX key at +32.
 710          * The hal handles the MIC keys at index+64.
 711          */
 712         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 713         if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
 714                 /* Txmic entry failed. No need to proceed further */
 715                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 716                         "Setting TX MIC Key Failed\n");
 717                 return 0;
 718         }
 719
 720         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 721         /* XXX delete tx key on failure? */
 722         return ath_keyset(sc, key->keyidx+32, hk, addr);
 723 }
 724
 725 static int ath_key_config(struct ath_softc *sc,
 726                           const u8 *addr,
 727                           struct ieee80211_key_conf *key)
 728 {
 729         struct ieee80211_vif *vif;
 730         struct ath9k_keyval hk;
 731         const u8 *mac = NULL;
 732         int ret = 0;
 733         enum nl80211_iftype opmode;
 734
 735         memset(&hk, 0, sizeof(hk));
 736
 737         switch (key->alg) {
 738         case ALG_WEP:
 739                 hk.kv_type = ATH9K_CIPHER_WEP;
 740                 break;
 741         case ALG_TKIP:
 742                 hk.kv_type = ATH9K_CIPHER_TKIP;
 743                 break;
 744         case ALG_CCMP:
 745                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 746                 break;
 747         default:
 748                 return -EINVAL;
 749         }
 750
 751         hk.kv_len  = key->keylen;
 752         memcpy(hk.kv_val, key->key, key->keylen);
 753
 754         if (!sc->sc_vaps[0])
 755                 return -EIO;
 756
 757         vif = sc->sc_vaps[0];
 758         opmode = vif->type;
 759
 760         /*
 761          *  Strategy:
 762          *   For STA mc tx, we will not setup a key at
 763          *   all since we never tx mc.
 764          *
 765          *   For STA mc rx, we will use the keyID.
 766          *
 767          *   For ADHOC mc tx, we will use the keyID, and no macaddr.
 768          *
 769          *   For ADHOC mc rx, we will alloc a slot and plumb the mac of
 770          *   the peer node.
 771          *   BUT we will plumb a cleartext key so that we can do
 772          *   per-Sta default key table lookup in software.
 773          */
 774         if (is_broadcast_ether_addr(addr)) {
 775                 switch (opmode) {
 776                 case NL80211_IFTYPE_STATION:
 777                         /* default key:  could be group WPA key
 778                          * or could be static WEP key */
 779                         mac = NULL;
 780                         break;
 781                 case NL80211_IFTYPE_ADHOC:
 782                         break;
 783                 case NL80211_IFTYPE_AP:
 784                         break;
 785                 default:
 786                         ASSERT(0);
 787                         break;
 788                 }
 789         } else {
 790                 mac = addr;
 791         }
 792
 793         if (key->alg == ALG_TKIP)
 794                 ret = ath_setkey_tkip(sc, key, &hk, mac);
 795         else
 796                 ret = ath_keyset(sc, key->keyidx, &hk, mac);
 797
 798         if (!ret)
 799                 return -EIO;
 800
 801         return 0;
 802 }
 803
 804 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 805 {
 806         int freeslot;
 807
 808         freeslot = (key->keyidx >= 4) ? 1 : 0;
 809         ath_key_reset(sc, key->keyidx, freeslot);
 810 }
 811
 812 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 813 {
 814 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 815 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 816
 817         ht_info->ht_supported = true;
 818         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 819                        IEEE80211_HT_CAP_SM_PS |
 820                        IEEE80211_HT_CAP_SGI_40 |
 821                        IEEE80211_HT_CAP_DSSSCCK40;
 822
 823         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 824         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 825         /* set up supported mcs set */
 826         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 827         ht_info->mcs.rx_mask[0] = 0xff;
 828         ht_info->mcs.rx_mask[1] = 0xff;
 829         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 830 }
 831
 832 static void ath9k_ht_conf(struct ath_softc *sc,
 833                           struct ieee80211_bss_conf *bss_conf)
 834 {
 835         if (sc->hw->conf.ht.enabled) {
 836                 if (bss_conf->ht.width_40_ok)
 837                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
 838                 else
 839                         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
 840
 841                 ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width);
 842
 843                 DPRINTF(sc, ATH_DBG_CONFIG,
 844                         "BSS Changed HT, chanwidth: %d\n", sc->tx_chan_width);
 845         }
 846 }
 847
 848 static inline int ath_sec_offset(u8 ext_offset)
 849 {
 850         if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE)
 851                 return 0;
 852         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
 853                 return 1;
 854         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
 855                 return -1;
 856
 857         return 0;
 858 }
 859
 860 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 861                                  struct ieee80211_vif *vif,
 862                                  struct ieee80211_bss_conf *bss_conf)
 863 {
 864         struct ieee80211_hw *hw = sc->hw;
 865         struct ieee80211_channel *curchan = hw->conf.channel;
 866         struct ath_vap *avp = (void *)vif->drv_priv;
 867         int pos;
 868
 869         if (bss_conf->assoc) {
 870                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d\n", bss_conf->aid);
 871
 872                 /* New association, store aid */
 873                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 874                         sc->sc_curaid = bss_conf->aid;
 875                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 876                                                sc->sc_curaid);
 877                 }
 878
 879                 /* Configure the beacon */
 880                 ath_beacon_config(sc, 0);
 881                 sc->sc_flags |= SC_OP_BEACONS;
 882
 883                 /* Reset rssi stats */
 884                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 885                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 886                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 887                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 888
 889                 /* Update chainmask */
 890                 ath_update_chainmask(sc, hw->conf.ht.enabled);
 891
 892                 DPRINTF(sc, ATH_DBG_CONFIG,
 893                         "bssid %pM aid 0x%x\n",
 894                         sc->sc_curbssid, sc->sc_curaid);
 895
 896                 pos = ath_get_channel(sc, curchan);
 897                 if (pos == -1) {
 898                         DPRINTF(sc, ATH_DBG_FATAL,
 899                                 "Invalid channel: %d\n", curchan->center_freq);
 900                         return;
 901                 }
 902
 903                 if (hw->conf.ht.enabled) {
 904                         int offset =
 905                                 ath_sec_offset(bss_conf->ht.secondary_channel_offset);
 906                         sc->tx_chan_width = (bss_conf->ht.width_40_ok) ?
 907                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
 908
 909                         sc->sc_ah->ah_channels[pos].chanmode =
 910                                 ath_get_extchanmode(sc, curchan,
 911                                                     offset, sc->tx_chan_width);
 912                 } else {
 913                         sc->sc_ah->ah_channels[pos].chanmode =
 914                                 (curchan->band == IEEE80211_BAND_2GHZ) ?
 915                                 CHANNEL_G : CHANNEL_A;
 916                 }
 917
 918                 /* set h/w channel */
 919                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
 920                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel: %d\n",
 921                                 curchan->center_freq);
 922
 923                 /* Start ANI */
 924                 mod_timer(&sc->sc_ani.timer,
 925                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 926
 927         } else {
 928                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 929                 sc->sc_curaid = 0;
 930         }
 931 }
 932
 933 /********************************/
 934 /*       LED functions          */
 935 /********************************/
 936
 937 static void ath_led_brightness(struct led_classdev *led_cdev,
 938                                enum led_brightness brightness)
 939 {
 940         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 941         struct ath_softc *sc = led->sc;
 942
 943         switch (brightness) {
 944         case LED_OFF:
 945                 if (led->led_type == ATH_LED_ASSOC ||
 946                     led->led_type == ATH_LED_RADIO)
 947                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 948                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 949                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 950                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 951                 break;
 952         case LED_FULL:
 953                 if (led->led_type == ATH_LED_ASSOC)
 954                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 955                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 956                 break;
 957         default:
 958                 break;
 959         }
 960 }
 961
 962 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 963                             char *trigger)
 964 {
 965         int ret;
 966
 967         led->sc = sc;
 968         led->led_cdev.name = led->name;
 969         led->led_cdev.default_trigger = trigger;
 970         led->led_cdev.brightness_set = ath_led_brightness;
 971
 972         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 973         if (ret)
 974                 DPRINTF(sc, ATH_DBG_FATAL,
 975                         "Failed to register led:%s", led->name);
 976         else
 977                 led->registered = 1;
 978         return ret;
 979 }
 980
 981 static void ath_unregister_led(struct ath_led *led)
 982 {
 983         if (led->registered) {
 984                 led_classdev_unregister(&led->led_cdev);
 985                 led->registered = 0;
 986         }
 987 }
 988
 989 static void ath_deinit_leds(struct ath_softc *sc)
 990 {
 991         ath_unregister_led(&sc->assoc_led);
 992         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 993         ath_unregister_led(&sc->tx_led);
 994         ath_unregister_led(&sc->rx_led);
 995         ath_unregister_led(&sc->radio_led);
 996         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 997 }
 998
 999 static void ath_init_leds(struct ath_softc *sc)
1000 {
1001         char *trigger;
1002         int ret;
1003
1004         /* Configure gpio 1 for output */
1005         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1006                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1007         /* LED off, active low */
1008         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1009
1010         trigger = ieee80211_get_radio_led_name(sc->hw);
1011         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1012                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1013         ret = ath_register_led(sc, &sc->radio_led, trigger);
1014         sc->radio_led.led_type = ATH_LED_RADIO;
1015         if (ret)
1016                 goto fail;
1017
1018         trigger = ieee80211_get_assoc_led_name(sc->hw);
1019         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1020                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1021         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1022         sc->assoc_led.led_type = ATH_LED_ASSOC;
1023         if (ret)
1024                 goto fail;
1025
1026         trigger = ieee80211_get_tx_led_name(sc->hw);
1027         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1028                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1029         ret = ath_register_led(sc, &sc->tx_led, trigger);
1030         sc->tx_led.led_type = ATH_LED_TX;
1031         if (ret)
1032                 goto fail;
1033
1034         trigger = ieee80211_get_rx_led_name(sc->hw);
1035         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1036                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1037         ret = ath_register_led(sc, &sc->rx_led, trigger);
1038         sc->rx_led.led_type = ATH_LED_RX;
1039         if (ret)
1040                 goto fail;
1041
1042         return;
1043
1044 fail:
1045         ath_deinit_leds(sc);
1046 }
1047
1048 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1049
1050 /*******************/
1051 /*      Rfkill     */
1052 /*******************/
1053
1054 static void ath_radio_enable(struct ath_softc *sc)
1055 {
1056         struct ath_hal *ah = sc->sc_ah;
1057         int status;
1058
1059         spin_lock_bh(&sc->sc_resetlock);
1060         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1061                             sc->tx_chan_width,
1062                             sc->sc_tx_chainmask,
1063                             sc->sc_rx_chainmask,
1064                             sc->sc_ht_extprotspacing,
1065                             false, &status)) {
1066                 DPRINTF(sc, ATH_DBG_FATAL,
1067                         "Unable to reset channel %u (%uMhz) "
1068                         "flags 0x%x hal status %u\n",
1069                         ath9k_hw_mhz2ieee(ah,
1070                                           ah->ah_curchan->channel,
1071                                           ah->ah_curchan->channelFlags),
1072                         ah->ah_curchan->channel,
1073                         ah->ah_curchan->channelFlags, status);
1074         }
1075         spin_unlock_bh(&sc->sc_resetlock);
1076
1077         ath_update_txpow(sc);
1078         if (ath_startrecv(sc) != 0) {
1079                 DPRINTF(sc, ATH_DBG_FATAL,
1080                         "Unable to restart recv logic\n");
1081                 return;
1082         }
1083
1084         if (sc->sc_flags & SC_OP_BEACONS)
1085                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1086
1087         /* Re-Enable  interrupts */
1088         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1089
1090         /* Enable LED */
1091         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1092                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1093         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1094
1095         ieee80211_wake_queues(sc->hw);
1096 }
1097
1098 static void ath_radio_disable(struct ath_softc *sc)
1099 {
1100         struct ath_hal *ah = sc->sc_ah;
1101         int status;
1102
1103
1104         ieee80211_stop_queues(sc->hw);
1105
1106         /* Disable LED */
1107         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1108         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1109
1110         /* Disable interrupts */
1111         ath9k_hw_set_interrupts(ah, 0);
1112
1113         ath_draintxq(sc, false);        /* clear pending tx frames */
1114         ath_stoprecv(sc);               /* turn off frame recv */
1115         ath_flushrecv(sc);              /* flush recv queue */
1116
1117         spin_lock_bh(&sc->sc_resetlock);
1118         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1119                             sc->tx_chan_width,
1120                             sc->sc_tx_chainmask,
1121                             sc->sc_rx_chainmask,
1122                             sc->sc_ht_extprotspacing,
1123                             false, &status)) {
1124                 DPRINTF(sc, ATH_DBG_FATAL,
1125                         "Unable to reset channel %u (%uMhz) "
1126                         "flags 0x%x hal status %u\n",
1127                         ath9k_hw_mhz2ieee(ah,
1128                                 ah->ah_curchan->channel,
1129                                 ah->ah_curchan->channelFlags),
1130                         ah->ah_curchan->channel,
1131                         ah->ah_curchan->channelFlags, status);
1132         }
1133         spin_unlock_bh(&sc->sc_resetlock);
1134
1135         ath9k_hw_phy_disable(ah);
1136         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1137 }
1138
1139 static bool ath_is_rfkill_set(struct ath_softc *sc)
1140 {
1141         struct ath_hal *ah = sc->sc_ah;
1142
1143         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1144                                   ah->ah_rfkill_polarity;
1145 }
1146
1147 /* h/w rfkill poll function */
1148 static void ath_rfkill_poll(struct work_struct *work)
1149 {
1150         struct ath_softc *sc = container_of(work, struct ath_softc,
1151                                             rf_kill.rfkill_poll.work);
1152         bool radio_on;
1153
1154         if (sc->sc_flags & SC_OP_INVALID)
1155                 return;
1156
1157         radio_on = !ath_is_rfkill_set(sc);
1158
1159         /*
1160          * enable/disable radio only when there is a
1161          * state change in RF switch
1162          */
1163         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1164                 enum rfkill_state state;
1165
1166                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1167                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1168                                 : RFKILL_STATE_HARD_BLOCKED;
1169                 } else if (radio_on) {
1170                         ath_radio_enable(sc);
1171                         state = RFKILL_STATE_UNBLOCKED;
1172                 } else {
1173                         ath_radio_disable(sc);
1174                         state = RFKILL_STATE_HARD_BLOCKED;
1175                 }
1176
1177                 if (state == RFKILL_STATE_HARD_BLOCKED)
1178                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1179                 else
1180                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1181
1182                 rfkill_force_state(sc->rf_kill.rfkill, state);
1183         }
1184
1185         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1186                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1187 }
1188
1189 /* s/w rfkill handler */
1190 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1191 {
1192         struct ath_softc *sc = data;
1193
1194         switch (state) {
1195         case RFKILL_STATE_SOFT_BLOCKED:
1196                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1197                     SC_OP_RFKILL_SW_BLOCKED)))
1198                         ath_radio_disable(sc);
1199                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1200                 return 0;
1201         case RFKILL_STATE_UNBLOCKED:
1202                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1203                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1204                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1205                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1206                                         "radio as it is disabled by h/w\n");
1207                                 return -EPERM;
1208                         }
1209                         ath_radio_enable(sc);
1210                 }
1211                 return 0;
1212         default:
1213                 return -EINVAL;
1214         }
1215 }
1216
1217 /* Init s/w rfkill */
1218 static int ath_init_sw_rfkill(struct ath_softc *sc)
1219 {
1220         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1221                                              RFKILL_TYPE_WLAN);
1222         if (!sc->rf_kill.rfkill) {
1223                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1224                 return -ENOMEM;
1225         }
1226
1227         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1228                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1229         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1230         sc->rf_kill.rfkill->data = sc;
1231         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1232         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1233         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1234
1235         return 0;
1236 }
1237
1238 /* Deinitialize rfkill */
1239 static void ath_deinit_rfkill(struct ath_softc *sc)
1240 {
1241         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1242                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1243
1244         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1245                 rfkill_unregister(sc->rf_kill.rfkill);
1246                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1247                 sc->rf_kill.rfkill = NULL;
1248         }
1249 }
1250
1251 static int ath_start_rfkill_poll(struct ath_softc *sc)
1252 {
1253         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1254                 queue_delayed_work(sc->hw->workqueue,
1255                                    &sc->rf_kill.rfkill_poll, 0);
1256
1257         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1258                 if (rfkill_register(sc->rf_kill.rfkill)) {
1259                         DPRINTF(sc, ATH_DBG_FATAL,
1260                                 "Unable to register rfkill\n");
1261                         rfkill_free(sc->rf_kill.rfkill);
1262
1263                         /* Deinitialize the device */
1264                         ath_detach(sc);
1265                         if (sc->pdev->irq)
1266                                 free_irq(sc->pdev->irq, sc);
1267                         pci_iounmap(sc->pdev, sc->mem);
1268                         pci_release_region(sc->pdev, 0);
1269                         pci_disable_device(sc->pdev);
1270                         ieee80211_free_hw(sc->hw);
1271                         return -EIO;
1272                 } else {
1273                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1274                 }
1275         }
1276
1277         return 0;
1278 }
1279 #endif /* CONFIG_RFKILL */
1280
1281 static void ath_detach(struct ath_softc *sc)
1282 {
1283         struct ieee80211_hw *hw = sc->hw;
1284         int i = 0;
1285
1286         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1287
1288 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1289         ath_deinit_rfkill(sc);
1290 #endif
1291         ath_deinit_leds(sc);
1292
1293         ieee80211_unregister_hw(hw);
1294
1295         ath_rate_control_unregister();
1296
1297         ath_rx_cleanup(sc);
1298         ath_tx_cleanup(sc);
1299
1300         tasklet_kill(&sc->intr_tq);
1301         tasklet_kill(&sc->bcon_tasklet);
1302
1303         if (!(sc->sc_flags & SC_OP_INVALID))
1304                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1305
1306         /* cleanup tx queues */
1307         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1308                 if (ATH_TXQ_SETUP(sc, i))
1309                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1310
1311         ath9k_hw_detach(sc->sc_ah);
1312         ath9k_exit_debug(sc);
1313 }
1314
1315 static int ath_init(u16 devid, struct ath_softc *sc)
1316 {
1317         struct ath_hal *ah = NULL;
1318         int status;
1319         int error = 0, i;
1320         int csz = 0;
1321
1322         /* XXX: hardware will not be ready until ath_open() being called */
1323         sc->sc_flags |= SC_OP_INVALID;
1324
1325         if (ath9k_init_debug(sc) < 0)
1326                 printk(KERN_ERR "Unable to create debugfs files\n");
1327
1328         spin_lock_init(&sc->sc_resetlock);
1329         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1330         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1331                      (unsigned long)sc);
1332
1333         /*
1334          * Cache line size is used to size and align various
1335          * structures used to communicate with the hardware.
1336          */
1337         bus_read_cachesize(sc, &csz);
1338         /* XXX assert csz is non-zero */
1339         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1340
1341         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1342         if (ah == NULL) {
1343                 DPRINTF(sc, ATH_DBG_FATAL,
1344                         "Unable to attach hardware; HAL status %u\n", status);
1345                 error = -ENXIO;
1346                 goto bad;
1347         }
1348         sc->sc_ah = ah;
1349
1350         /* Get the hardware key cache size. */
1351         sc->sc_keymax = ah->ah_caps.keycache_size;
1352         if (sc->sc_keymax > ATH_KEYMAX) {
1353                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1354                         "Warning, using only %u entries in %u key cache\n",
1355                         ATH_KEYMAX, sc->sc_keymax);
1356                 sc->sc_keymax = ATH_KEYMAX;
1357         }
1358
1359         /*
1360          * Reset the key cache since some parts do not
1361          * reset the contents on initial power up.
1362          */
1363         for (i = 0; i < sc->sc_keymax; i++)
1364                 ath9k_hw_keyreset(ah, (u16) i);
1365         /*
1366          * Mark key cache slots associated with global keys
1367          * as in use.  If we knew TKIP was not to be used we
1368          * could leave the +32, +64, and +32+64 slots free.
1369          * XXX only for splitmic.
1370          */
1371         for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1372                 set_bit(i, sc->sc_keymap);
1373                 set_bit(i + 32, sc->sc_keymap);
1374                 set_bit(i + 64, sc->sc_keymap);
1375                 set_bit(i + 32 + 64, sc->sc_keymap);
1376         }
1377
1378         /* Collect the channel list using the default country code */
1379
1380         error = ath_setup_channels(sc);
1381         if (error)
1382                 goto bad;
1383
1384         /* default to MONITOR mode */
1385         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1386
1387
1388         /* Setup rate tables */
1389
1390         ath_rate_attach(sc);
1391         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1392         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1393
1394         /*
1395          * Allocate hardware transmit queues: one queue for
1396          * beacon frames and one data queue for each QoS
1397          * priority.  Note that the hal handles reseting
1398          * these queues at the needed time.
1399          */
1400         sc->beacon.beaconq = ath_beaconq_setup(ah);
1401         if (sc->beacon.beaconq == -1) {
1402                 DPRINTF(sc, ATH_DBG_FATAL,
1403                         "Unable to setup a beacon xmit queue\n");
1404                 error = -EIO;
1405                 goto bad2;
1406         }
1407         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1408         if (sc->beacon.cabq == NULL) {
1409                 DPRINTF(sc, ATH_DBG_FATAL,
1410                         "Unable to setup CAB xmit queue\n");
1411                 error = -EIO;
1412                 goto bad2;
1413         }
1414
1415         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1416         ath_cabq_update(sc);
1417
1418         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1419                 sc->tx.hwq_map[i] = -1;
1420
1421         /* Setup data queues */
1422         /* NB: ensure BK queue is the lowest priority h/w queue */
1423         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1424                 DPRINTF(sc, ATH_DBG_FATAL,
1425                         "Unable to setup xmit queue for BK traffic\n");
1426                 error = -EIO;
1427                 goto bad2;
1428         }
1429
1430         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1431                 DPRINTF(sc, ATH_DBG_FATAL,
1432                         "Unable to setup xmit queue for BE traffic\n");
1433                 error = -EIO;
1434                 goto bad2;
1435         }
1436         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1437                 DPRINTF(sc, ATH_DBG_FATAL,
1438                         "Unable to setup xmit queue for VI traffic\n");
1439                 error = -EIO;
1440                 goto bad2;
1441         }
1442         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1443                 DPRINTF(sc, ATH_DBG_FATAL,
1444                         "Unable to setup xmit queue for VO traffic\n");
1445                 error = -EIO;
1446                 goto bad2;
1447         }
1448
1449         /* Initializes the noise floor to a reasonable default value.
1450          * Later on this will be updated during ANI processing. */
1451
1452         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1453         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1454
1455         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1456                                    ATH9K_CIPHER_TKIP, NULL)) {
1457                 /*
1458                  * Whether we should enable h/w TKIP MIC.
1459                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1460                  * report WMM capable, so it's always safe to turn on
1461                  * TKIP MIC in this case.
1462                  */
1463                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1464                                        0, 1, NULL);
1465         }
1466
1467         /*
1468          * Check whether the separate key cache entries
1469          * are required to handle both tx+rx MIC keys.
1470          * With split mic keys the number of stations is limited
1471          * to 27 otherwise 59.
1472          */
1473         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1474                                    ATH9K_CIPHER_TKIP, NULL)
1475             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1476                                       ATH9K_CIPHER_MIC, NULL)
1477             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1478                                       0, NULL))
1479                 sc->sc_splitmic = 1;
1480
1481         /* turn on mcast key search if possible */
1482         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1483                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1484                                              1, NULL);
1485
1486         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1487         sc->sc_config.txpowlimit_override = 0;
1488
1489         /* 11n Capabilities */
1490         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1491                 sc->sc_flags |= SC_OP_TXAGGR;
1492                 sc->sc_flags |= SC_OP_RXAGGR;
1493         }
1494
1495         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1496         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1497
1498         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1499         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1500
1501         ath9k_hw_getmac(ah, sc->sc_myaddr);
1502         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1503                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1504                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1505                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1506         }
1507
1508         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1509
1510         /* initialize beacon slots */
1511         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1512                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1513
1514         /* save MISC configurations */
1515         sc->sc_config.swBeaconProcess = 1;
1516
1517         /* setup channels and rates */
1518
1519         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1520                 sc->channels[IEEE80211_BAND_2GHZ];
1521         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1522                 sc->rates[IEEE80211_BAND_2GHZ];
1523         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1524
1525         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1526                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1527                         sc->channels[IEEE80211_BAND_5GHZ];
1528                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1529                         sc->rates[IEEE80211_BAND_5GHZ];
1530                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1531         }
1532
1533         return 0;
1534 bad2:
1535         /* cleanup tx queues */
1536         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1537                 if (ATH_TXQ_SETUP(sc, i))
1538                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1539 bad:
1540         if (ah)
1541                 ath9k_hw_detach(ah);
1542
1543         return error;
1544 }
1545
1546 static int ath_attach(u16 devid, struct ath_softc *sc)
1547 {
1548         struct ieee80211_hw *hw = sc->hw;
1549         int error = 0;
1550
1551         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1552
1553         error = ath_init(devid, sc);
1554         if (error != 0)
1555                 return error;
1556
1557         /* get mac address from hardware and set in mac80211 */
1558
1559         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1560
1561         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1562                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1563                 IEEE80211_HW_SIGNAL_DBM |
1564                 IEEE80211_HW_AMPDU_AGGREGATION;
1565
1566         hw->wiphy->interface_modes =
1567                 BIT(NL80211_IFTYPE_AP) |
1568                 BIT(NL80211_IFTYPE_STATION) |
1569                 BIT(NL80211_IFTYPE_ADHOC);
1570
1571         hw->queues = 4;
1572         hw->max_rates = 4;
1573         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1574         hw->sta_data_size = sizeof(struct ath_node);
1575         hw->vif_data_size = sizeof(struct ath_vap);
1576
1577         /* Register rate control */
1578         hw->rate_control_algorithm = "ath9k_rate_control";
1579         error = ath_rate_control_register();
1580         if (error != 0) {
1581                 DPRINTF(sc, ATH_DBG_FATAL,
1582                         "Unable to register rate control algorithm: %d\n", error);
1583                 ath_rate_control_unregister();
1584                 goto bad;
1585         }
1586
1587         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1588                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1589                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1590                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1591         }
1592
1593         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1594         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1595                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1596                         &sc->sbands[IEEE80211_BAND_5GHZ];
1597
1598         /* initialize tx/rx engine */
1599         error = ath_tx_init(sc, ATH_TXBUF);
1600         if (error != 0)
1601                 goto detach;
1602
1603         error = ath_rx_init(sc, ATH_RXBUF);
1604         if (error != 0)
1605                 goto detach;
1606
1607 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1608         /* Initialze h/w Rfkill */
1609         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1610                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1611
1612         /* Initialize s/w rfkill */
1613         if (ath_init_sw_rfkill(sc))
1614                 goto detach;
1615 #endif
1616
1617         error = ieee80211_register_hw(hw);
1618         if (error != 0) {
1619                 ath_rate_control_unregister();
1620                 goto bad;
1621         }
1622
1623         /* Initialize LED control */
1624         ath_init_leds(sc);
1625
1626         return 0;
1627 detach:
1628         ath_detach(sc);
1629 bad:
1630         return error;
1631 }
1632
1633 int ath_reset(struct ath_softc *sc, bool retry_tx)
1634 {
1635         struct ath_hal *ah = sc->sc_ah;
1636         int status;
1637         int error = 0;
1638
1639         ath9k_hw_set_interrupts(ah, 0);
1640         ath_draintxq(sc, retry_tx);
1641         ath_stoprecv(sc);
1642         ath_flushrecv(sc);
1643
1644         spin_lock_bh(&sc->sc_resetlock);
1645         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1646                             sc->tx_chan_width,
1647                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1648                             sc->sc_ht_extprotspacing, false, &status)) {
1649                 DPRINTF(sc, ATH_DBG_FATAL,
1650                         "Unable to reset hardware; hal status %u\n", status);
1651                 error = -EIO;
1652         }
1653         spin_unlock_bh(&sc->sc_resetlock);
1654
1655         if (ath_startrecv(sc) != 0)
1656                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1657
1658         /*
1659          * We may be doing a reset in response to a request
1660          * that changes the channel so update any state that
1661          * might change as a result.
1662          */
1663         ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1664
1665         ath_update_txpow(sc);
1666
1667         if (sc->sc_flags & SC_OP_BEACONS)
1668                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1669
1670         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1671
1672         if (retry_tx) {
1673                 int i;
1674                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1675                         if (ATH_TXQ_SETUP(sc, i)) {
1676                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1677                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1678                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1679                         }
1680                 }
1681         }
1682
1683         return error;
1684 }
1685
1686 /*
1687  *  This function will allocate both the DMA descriptor structure, and the
1688  *  buffers it contains.  These are used to contain the descriptors used
1689  *  by the system.
1690 */
1691 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1692                       struct list_head *head, const char *name,
1693                       int nbuf, int ndesc)
1694 {
1695 #define DS2PHYS(_dd, _ds)                                               \
1696         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1697 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1698 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1699
1700         struct ath_desc *ds;
1701         struct ath_buf *bf;
1702         int i, bsize, error;
1703
1704         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1705                 name, nbuf, ndesc);
1706
1707         /* ath_desc must be a multiple of DWORDs */
1708         if ((sizeof(struct ath_desc) % 4) != 0) {
1709                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1710                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1711                 error = -ENOMEM;
1712                 goto fail;
1713         }
1714
1715         dd->dd_name = name;
1716         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1717
1718         /*
1719          * Need additional DMA memory because we can't use
1720          * descriptors that cross the 4K page boundary. Assume
1721          * one skipped descriptor per 4K page.
1722          */
1723         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1724                 u32 ndesc_skipped =
1725                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1726                 u32 dma_len;
1727
1728                 while (ndesc_skipped) {
1729                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1730                         dd->dd_desc_len += dma_len;
1731
1732                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1733                 };
1734         }
1735
1736         /* allocate descriptors */
1737         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1738                               dd->dd_desc_len,
1739                               &dd->dd_desc_paddr);
1740         if (dd->dd_desc == NULL) {
1741                 error = -ENOMEM;
1742                 goto fail;
1743         }
1744         ds = dd->dd_desc;
1745         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1746                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1747                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1748
1749         /* allocate buffers */
1750         bsize = sizeof(struct ath_buf) * nbuf;
1751         bf = kmalloc(bsize, GFP_KERNEL);
1752         if (bf == NULL) {
1753                 error = -ENOMEM;
1754                 goto fail2;
1755         }
1756         memset(bf, 0, bsize);
1757         dd->dd_bufptr = bf;
1758
1759         INIT_LIST_HEAD(head);
1760         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1761                 bf->bf_desc = ds;
1762                 bf->bf_daddr = DS2PHYS(dd, ds);
1763
1764                 if (!(sc->sc_ah->ah_caps.hw_caps &
1765                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1766                         /*
1767                          * Skip descriptor addresses which can cause 4KB
1768                          * boundary crossing (addr + length) with a 32 dword
1769                          * descriptor fetch.
1770                          */
1771                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1772                                 ASSERT((caddr_t) bf->bf_desc <
1773                                        ((caddr_t) dd->dd_desc +
1774                                         dd->dd_desc_len));
1775
1776                                 ds += ndesc;
1777                                 bf->bf_desc = ds;
1778                                 bf->bf_daddr = DS2PHYS(dd, ds);
1779                         }
1780                 }
1781                 list_add_tail(&bf->list, head);
1782         }
1783         return 0;
1784 fail2:
1785         pci_free_consistent(sc->pdev,
1786                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1787 fail:
1788         memset(dd, 0, sizeof(*dd));
1789         return error;
1790 #undef ATH_DESC_4KB_BOUND_CHECK
1791 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1792 #undef DS2PHYS
1793 }
1794
1795 void ath_descdma_cleanup(struct ath_softc *sc,
1796                          struct ath_descdma *dd,
1797                          struct list_head *head)
1798 {
1799         pci_free_consistent(sc->pdev,
1800                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1801
1802         INIT_LIST_HEAD(head);
1803         kfree(dd->dd_bufptr);
1804         memset(dd, 0, sizeof(*dd));
1805 }
1806
1807 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1808 {
1809         int qnum;
1810
1811         switch (queue) {
1812         case 0:
1813                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1814                 break;
1815         case 1:
1816                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1817                 break;
1818         case 2:
1819                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1820                 break;
1821         case 3:
1822                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1823                 break;
1824         default:
1825                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1826                 break;
1827         }
1828
1829         return qnum;
1830 }
1831
1832 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1833 {
1834         int qnum;
1835
1836         switch (queue) {
1837         case ATH9K_WME_AC_VO:
1838                 qnum = 0;
1839                 break;
1840         case ATH9K_WME_AC_VI:
1841                 qnum = 1;
1842                 break;
1843         case ATH9K_WME_AC_BE:
1844                 qnum = 2;
1845                 break;
1846         case ATH9K_WME_AC_BK:
1847                 qnum = 3;
1848                 break;
1849         default:
1850                 qnum = -1;
1851                 break;
1852         }
1853
1854         return qnum;
1855 }
1856
1857 /**********************/
1858 /* mac80211 callbacks */
1859 /**********************/
1860
1861 static int ath9k_start(struct ieee80211_hw *hw)
1862 {
1863         struct ath_softc *sc = hw->priv;
1864         struct ieee80211_channel *curchan = hw->conf.channel;
1865         struct ath9k_channel *init_channel;
1866         int error = 0, pos, status;
1867
1868         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1869                 "initial channel: %d MHz\n", curchan->center_freq);
1870
1871         /* setup initial channel */
1872
1873         pos = ath_get_channel(sc, curchan);
1874         if (pos == -1) {
1875                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1876                 error = -EINVAL;
1877                 goto error;
1878         }
1879
1880         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1881         sc->sc_ah->ah_channels[pos].chanmode =
1882                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1883         init_channel = &sc->sc_ah->ah_channels[pos];
1884
1885         /* Reset SERDES registers */
1886         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1887
1888         /*
1889          * The basic interface to setting the hardware in a good
1890          * state is ``reset''.  On return the hardware is known to
1891          * be powered up and with interrupts disabled.  This must
1892          * be followed by initialization of the appropriate bits
1893          * and then setup of the interrupt mask.
1894          */
1895         spin_lock_bh(&sc->sc_resetlock);
1896         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1897                             sc->tx_chan_width,
1898                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1899                             sc->sc_ht_extprotspacing, false, &status)) {
1900                 DPRINTF(sc, ATH_DBG_FATAL,
1901                         "Unable to reset hardware; hal status %u "
1902                         "(freq %u flags 0x%x)\n", status,
1903                         init_channel->channel, init_channel->channelFlags);
1904                 error = -EIO;
1905                 spin_unlock_bh(&sc->sc_resetlock);
1906                 goto error;
1907         }
1908         spin_unlock_bh(&sc->sc_resetlock);
1909
1910         /*
1911          * This is needed only to setup initial state
1912          * but it's best done after a reset.
1913          */
1914         ath_update_txpow(sc);
1915
1916         /*
1917          * Setup the hardware after reset:
1918          * The receive engine is set going.
1919          * Frame transmit is handled entirely
1920          * in the frame output path; there's nothing to do
1921          * here except setup the interrupt mask.
1922          */
1923         if (ath_startrecv(sc) != 0) {
1924                 DPRINTF(sc, ATH_DBG_FATAL,
1925                         "Unable to start recv logic\n");
1926                 error = -EIO;
1927                 goto error;
1928         }
1929
1930         /* Setup our intr mask. */
1931         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1932                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1933                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1934
1935         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1936                 sc->sc_imask |= ATH9K_INT_GTT;
1937
1938         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1939                 sc->sc_imask |= ATH9K_INT_CST;
1940
1941         /*
1942          * Enable MIB interrupts when there are hardware phy counters.
1943          * Note we only do this (at the moment) for station mode.
1944          */
1945         if (ath9k_hw_phycounters(sc->sc_ah) &&
1946             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1947              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1948                 sc->sc_imask |= ATH9K_INT_MIB;
1949         /*
1950          * Some hardware processes the TIM IE and fires an
1951          * interrupt when the TIM bit is set.  For hardware
1952          * that does, if not overridden by configuration,
1953          * enable the TIM interrupt when operating as station.
1954          */
1955         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1956             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1957             !sc->sc_config.swBeaconProcess)
1958                 sc->sc_imask |= ATH9K_INT_TIM;
1959
1960         ath_setcurmode(sc, ath_chan2mode(init_channel));
1961
1962         sc->sc_flags &= ~SC_OP_INVALID;
1963
1964         /* Disable BMISS interrupt when we're not associated */
1965         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1966         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1967
1968         ieee80211_wake_queues(sc->hw);
1969
1970 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1971         error = ath_start_rfkill_poll(sc);
1972 #endif
1973
1974 error:
1975         return error;
1976 }
1977
1978 static int ath9k_tx(struct ieee80211_hw *hw,
1979                     struct sk_buff *skb)
1980 {
1981         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1982         struct ath_softc *sc = hw->priv;
1983         struct ath_tx_control txctl;
1984         int hdrlen, padsize;
1985
1986         memset(&txctl, 0, sizeof(struct ath_tx_control));
1987
1988         /*
1989          * As a temporary workaround, assign seq# here; this will likely need
1990          * to be cleaned up to work better with Beacon transmission and virtual
1991          * BSSes.
1992          */
1993         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1994                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1995                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1996                         sc->tx.seq_no += 0x10;
1997                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1998                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1999         }
2000
2001         /* Add the padding after the header if this is not already done */
2002         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2003         if (hdrlen & 3) {
2004                 padsize = hdrlen % 4;
2005                 if (skb_headroom(skb) < padsize)
2006                         return -1;
2007                 skb_push(skb, padsize);
2008                 memmove(skb->data, skb->data + padsize, hdrlen);
2009         }
2010
2011         /* Check if a tx queue is available */
2012
2013         txctl.txq = ath_test_get_txq(sc, skb);
2014         if (!txctl.txq)
2015                 goto exit;
2016
2017         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2018
2019         if (ath_tx_start(sc, skb, &txctl) != 0) {
2020                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2021                 goto exit;
2022         }
2023
2024         return 0;
2025 exit:
2026         dev_kfree_skb_any(skb);
2027         return 0;
2028 }
2029
2030 static void ath9k_stop(struct ieee80211_hw *hw)
2031 {
2032         struct ath_softc *sc = hw->priv;
2033
2034         if (sc->sc_flags & SC_OP_INVALID) {
2035                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2036                 return;
2037         }
2038
2039         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2040
2041         ieee80211_stop_queues(sc->hw);
2042
2043         /* make sure h/w will not generate any interrupt
2044          * before setting the invalid flag. */
2045         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2046
2047         if (!(sc->sc_flags & SC_OP_INVALID)) {
2048                 ath_draintxq(sc, false);
2049                 ath_stoprecv(sc);
2050                 ath9k_hw_phy_disable(sc->sc_ah);
2051         } else
2052                 sc->rx.rxlink = NULL;
2053
2054 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2055         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2056                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2057 #endif
2058         /* disable HAL and put h/w to sleep */
2059         ath9k_hw_disable(sc->sc_ah);
2060         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2061
2062         sc->sc_flags |= SC_OP_INVALID;
2063
2064         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2065 }
2066
2067 static int ath9k_add_interface(struct ieee80211_hw *hw,
2068                                struct ieee80211_if_init_conf *conf)
2069 {
2070         struct ath_softc *sc = hw->priv;
2071         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2072         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2073
2074         /* Support only vap for now */
2075
2076         if (sc->sc_nvaps)
2077                 return -ENOBUFS;
2078
2079         switch (conf->type) {
2080         case NL80211_IFTYPE_STATION:
2081                 ic_opmode = NL80211_IFTYPE_STATION;
2082                 break;
2083         case NL80211_IFTYPE_ADHOC:
2084                 ic_opmode = NL80211_IFTYPE_ADHOC;
2085                 break;
2086         case NL80211_IFTYPE_AP:
2087                 ic_opmode = NL80211_IFTYPE_AP;
2088                 break;
2089         default:
2090                 DPRINTF(sc, ATH_DBG_FATAL,
2091                         "Interface type %d not yet supported\n", conf->type);
2092                 return -EOPNOTSUPP;
2093         }
2094
2095         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2096
2097         /* Set the VAP opmode */
2098         avp->av_opmode = ic_opmode;
2099         avp->av_bslot = -1;
2100
2101         if (ic_opmode == NL80211_IFTYPE_AP)
2102                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2103
2104         sc->sc_vaps[0] = conf->vif;
2105         sc->sc_nvaps++;
2106
2107         /* Set the device opmode */
2108         sc->sc_ah->ah_opmode = ic_opmode;
2109
2110         if (conf->type == NL80211_IFTYPE_AP) {
2111                 /* TODO: is this a suitable place to start ANI for AP mode? */
2112                 /* Start ANI */
2113                 mod_timer(&sc->sc_ani.timer,
2114                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2115         }
2116
2117         return 0;
2118 }
2119
2120 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2121                                    struct ieee80211_if_init_conf *conf)
2122 {
2123         struct ath_softc *sc = hw->priv;
2124         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2125
2126         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2127
2128         /* Stop ANI */
2129         del_timer_sync(&sc->sc_ani.timer);
2130
2131         /* Reclaim beacon resources */
2132         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2133             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2134                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2135                 ath_beacon_return(sc, avp);
2136         }
2137
2138         sc->sc_flags &= ~SC_OP_BEACONS;
2139
2140         sc->sc_vaps[0] = NULL;
2141         sc->sc_nvaps--;
2142 }
2143
2144 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2145 {
2146         struct ath_softc *sc = hw->priv;
2147         struct ieee80211_conf *conf = &hw->conf;
2148
2149         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2150                 struct ieee80211_channel *curchan = hw->conf.channel;
2151                 int pos;
2152
2153                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2154                         curchan->center_freq);
2155
2156                 pos = ath_get_channel(sc, curchan);
2157                 if (pos == -1) {
2158                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2159                                 curchan->center_freq);
2160                         return -EINVAL;
2161                 }
2162
2163                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2164                 sc->sc_ah->ah_channels[pos].chanmode =
2165                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2166                         CHANNEL_G : CHANNEL_A;
2167
2168                 if ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) &&
2169                     (conf->ht.enabled)) {
2170                         sc->tx_chan_width = (!!conf->ht.sec_chan_offset) ?
2171                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
2172
2173                         sc->sc_ah->ah_channels[pos].chanmode =
2174                                 ath_get_extchanmode(sc, curchan,
2175                                                     conf->ht.sec_chan_offset,
2176                                                     sc->tx_chan_width);
2177                 }
2178
2179                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2180                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2181                         return -EINVAL;
2182                 }
2183         }
2184
2185         if (changed & IEEE80211_CONF_CHANGE_HT)
2186                 ath_update_chainmask(sc, conf->ht.enabled);
2187
2188         if (changed & IEEE80211_CONF_CHANGE_POWER)
2189                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2190
2191         return 0;
2192 }
2193
2194 static int ath9k_config_interface(struct ieee80211_hw *hw,
2195                                   struct ieee80211_vif *vif,
2196                                   struct ieee80211_if_conf *conf)
2197 {
2198         struct ath_softc *sc = hw->priv;
2199         struct ath_hal *ah = sc->sc_ah;
2200         struct ath_vap *avp = (void *)vif->drv_priv;
2201         u32 rfilt = 0;
2202         int error, i;
2203
2204         /* TODO: Need to decide which hw opmode to use for multi-interface
2205          * cases */
2206         if (vif->type == NL80211_IFTYPE_AP &&
2207             ah->ah_opmode != NL80211_IFTYPE_AP) {
2208                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2209                 ath9k_hw_setopmode(ah);
2210                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2211                 /* Request full reset to get hw opmode changed properly */
2212                 sc->sc_flags |= SC_OP_FULL_RESET;
2213         }
2214
2215         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2216             !is_zero_ether_addr(conf->bssid)) {
2217                 switch (vif->type) {
2218                 case NL80211_IFTYPE_STATION:
2219                 case NL80211_IFTYPE_ADHOC:
2220                         /* Set BSSID */
2221                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2222                         sc->sc_curaid = 0;
2223                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2224                                                sc->sc_curaid);
2225
2226                         /* Set aggregation protection mode parameters */
2227                         sc->sc_config.ath_aggr_prot = 0;
2228
2229                         DPRINTF(sc, ATH_DBG_CONFIG,
2230                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2231                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2232
2233                         /* need to reconfigure the beacon */
2234                         sc->sc_flags &= ~SC_OP_BEACONS ;
2235
2236                         break;
2237                 default:
2238                         break;
2239                 }
2240         }
2241
2242         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2243             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2244              (vif->type == NL80211_IFTYPE_AP))) {
2245                 /*
2246                  * Allocate and setup the beacon frame.
2247                  *
2248                  * Stop any previous beacon DMA.  This may be
2249                  * necessary, for example, when an ibss merge
2250                  * causes reconfiguration; we may be called
2251                  * with beacon transmission active.
2252                  */
2253                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2254
2255                 error = ath_beacon_alloc(sc, 0);
2256                 if (error != 0)
2257                         return error;
2258
2259                 ath_beacon_sync(sc, 0);
2260         }
2261
2262         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2263         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2264                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2265                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2266                                 ath9k_hw_keysetmac(sc->sc_ah,
2267                                                    (u16)i,
2268                                                    sc->sc_curbssid);
2269         }
2270
2271         /* Only legacy IBSS for now */
2272         if (vif->type == NL80211_IFTYPE_ADHOC)
2273                 ath_update_chainmask(sc, 0);
2274
2275         return 0;
2276 }
2277
2278 #define SUPPORTED_FILTERS                       \
2279         (FIF_PROMISC_IN_BSS |                   \
2280         FIF_ALLMULTI |                          \
2281         FIF_CONTROL |                           \
2282         FIF_OTHER_BSS |                         \
2283         FIF_BCN_PRBRESP_PROMISC |               \
2284         FIF_FCSFAIL)
2285
2286 /* FIXME: sc->sc_full_reset ? */
2287 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2288                                    unsigned int changed_flags,
2289                                    unsigned int *total_flags,
2290                                    int mc_count,
2291                                    struct dev_mc_list *mclist)
2292 {
2293         struct ath_softc *sc = hw->priv;
2294         u32 rfilt;
2295
2296         changed_flags &= SUPPORTED_FILTERS;
2297         *total_flags &= SUPPORTED_FILTERS;
2298
2299         sc->rx.rxfilter = *total_flags;
2300         rfilt = ath_calcrxfilter(sc);
2301         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2302
2303         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2304                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2305                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2306         }
2307
2308         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2309 }
2310
2311 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2312                              struct ieee80211_vif *vif,
2313                              enum sta_notify_cmd cmd,
2314                              struct ieee80211_sta *sta)
2315 {
2316         struct ath_softc *sc = hw->priv;
2317
2318         switch (cmd) {
2319         case STA_NOTIFY_ADD:
2320                 ath_node_attach(sc, sta);
2321                 break;
2322         case STA_NOTIFY_REMOVE:
2323                 ath_node_detach(sc, sta);
2324                 break;
2325         default:
2326                 break;
2327         }
2328 }
2329
2330 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2331                          u16 queue,
2332                          const struct ieee80211_tx_queue_params *params)
2333 {
2334         struct ath_softc *sc = hw->priv;
2335         struct ath9k_tx_queue_info qi;
2336         int ret = 0, qnum;
2337
2338         if (queue >= WME_NUM_AC)
2339                 return 0;
2340
2341         qi.tqi_aifs = params->aifs;
2342         qi.tqi_cwmin = params->cw_min;
2343         qi.tqi_cwmax = params->cw_max;
2344         qi.tqi_burstTime = params->txop;
2345         qnum = ath_get_hal_qnum(queue, sc);
2346
2347         DPRINTF(sc, ATH_DBG_CONFIG,
2348                 "Configure tx [queue/halq] [%d/%d],  "
2349                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2350                 queue, qnum, params->aifs, params->cw_min,
2351                 params->cw_max, params->txop);
2352
2353         ret = ath_txq_update(sc, qnum, &qi);
2354         if (ret)
2355                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2356
2357         return ret;
2358 }
2359
2360 static int ath9k_set_key(struct ieee80211_hw *hw,
2361                          enum set_key_cmd cmd,
2362                          const u8 *local_addr,
2363                          const u8 *addr,
2364                          struct ieee80211_key_conf *key)
2365 {
2366         struct ath_softc *sc = hw->priv;
2367         int ret = 0;
2368
2369         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2370
2371         switch (cmd) {
2372         case SET_KEY:
2373                 ret = ath_key_config(sc, addr, key);
2374                 if (!ret) {
2375                         set_bit(key->keyidx, sc->sc_keymap);
2376                         key->hw_key_idx = key->keyidx;
2377                         /* push IV and Michael MIC generation to stack */
2378                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2379                         if (key->alg == ALG_TKIP)
2380                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2381                 }
2382                 break;
2383         case DISABLE_KEY:
2384                 ath_key_delete(sc, key);
2385                 clear_bit(key->keyidx, sc->sc_keymap);
2386                 break;
2387         default:
2388                 ret = -EINVAL;
2389         }
2390
2391         return ret;
2392 }
2393
2394 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2395                                    struct ieee80211_vif *vif,
2396                                    struct ieee80211_bss_conf *bss_conf,
2397                                    u32 changed)
2398 {
2399         struct ath_softc *sc = hw->priv;
2400
2401         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2402                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2403                         bss_conf->use_short_preamble);
2404                 if (bss_conf->use_short_preamble)
2405                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2406                 else
2407                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2408         }
2409
2410         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2411                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2412                         bss_conf->use_cts_prot);
2413                 if (bss_conf->use_cts_prot &&
2414                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2415                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2416                 else
2417                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2418         }
2419
2420         if (changed & BSS_CHANGED_HT)
2421                 ath9k_ht_conf(sc, bss_conf);
2422
2423         if (changed & BSS_CHANGED_ASSOC) {
2424                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2425                         bss_conf->assoc);
2426                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2427         }
2428 }
2429
2430 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2431 {
2432         u64 tsf;
2433         struct ath_softc *sc = hw->priv;
2434         struct ath_hal *ah = sc->sc_ah;
2435
2436         tsf = ath9k_hw_gettsf64(ah);
2437
2438         return tsf;
2439 }
2440
2441 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2442 {
2443         struct ath_softc *sc = hw->priv;
2444         struct ath_hal *ah = sc->sc_ah;
2445
2446         ath9k_hw_reset_tsf(ah);
2447 }
2448
2449 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2450                        enum ieee80211_ampdu_mlme_action action,
2451                        struct ieee80211_sta *sta,
2452                        u16 tid, u16 *ssn)
2453 {
2454         struct ath_softc *sc = hw->priv;
2455         int ret = 0;
2456
2457         switch (action) {
2458         case IEEE80211_AMPDU_RX_START:
2459                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2460                         ret = -ENOTSUPP;
2461                 break;
2462         case IEEE80211_AMPDU_RX_STOP:
2463                 break;
2464         case IEEE80211_AMPDU_TX_START:
2465                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2466                 if (ret < 0)
2467                         DPRINTF(sc, ATH_DBG_FATAL,
2468                                 "Unable to start TX aggregation\n");
2469                 else
2470                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2471                 break;
2472         case IEEE80211_AMPDU_TX_STOP:
2473                 ret = ath_tx_aggr_stop(sc, sta, tid);
2474                 if (ret < 0)
2475                         DPRINTF(sc, ATH_DBG_FATAL,
2476                                 "Unable to stop TX aggregation\n");
2477
2478                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2479                 break;
2480         case IEEE80211_AMPDU_TX_RESUME:
2481                 ath_tx_aggr_resume(sc, sta, tid);
2482                 break;
2483         default:
2484                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2485         }
2486
2487         return ret;
2488 }
2489
2490 static struct ieee80211_ops ath9k_ops = {
2491         .tx                 = ath9k_tx,
2492         .start              = ath9k_start,
2493         .stop               = ath9k_stop,
2494         .add_interface      = ath9k_add_interface,
2495         .remove_interface   = ath9k_remove_interface,
2496         .config             = ath9k_config,
2497         .config_interface   = ath9k_config_interface,
2498         .configure_filter   = ath9k_configure_filter,
2499         .sta_notify         = ath9k_sta_notify,
2500         .conf_tx            = ath9k_conf_tx,
2501         .bss_info_changed   = ath9k_bss_info_changed,
2502         .set_key            = ath9k_set_key,
2503         .get_tsf            = ath9k_get_tsf,
2504         .reset_tsf          = ath9k_reset_tsf,
2505         .ampdu_action       = ath9k_ampdu_action,
2506 };
2507
2508 static struct {
2509         u32 version;
2510         const char * name;
2511 } ath_mac_bb_names[] = {
2512         { AR_SREV_VERSION_5416_PCI,     "5416" },
2513         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2514         { AR_SREV_VERSION_9100,         "9100" },
2515         { AR_SREV_VERSION_9160,         "9160" },
2516         { AR_SREV_VERSION_9280,         "9280" },
2517         { AR_SREV_VERSION_9285,         "9285" }
2518 };
2519
2520 static struct {
2521         u16 version;
2522         const char * name;
2523 } ath_rf_names[] = {
2524         { 0,                            "5133" },
2525         { AR_RAD5133_SREV_MAJOR,        "5133" },
2526         { AR_RAD5122_SREV_MAJOR,        "5122" },
2527         { AR_RAD2133_SREV_MAJOR,        "2133" },
2528         { AR_RAD2122_SREV_MAJOR,        "2122" }
2529 };
2530
2531 /*
2532  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2533  */
2534 static const char *
2535 ath_mac_bb_name(u32 mac_bb_version)
2536 {
2537         int i;
2538
2539         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2540                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2541                         return ath_mac_bb_names[i].name;
2542                 }
2543         }
2544
2545         return "????";
2546 }
2547
2548 /*
2549  * Return the RF name. "????" is returned if the RF is unknown.
2550  */
2551 static const char *
2552 ath_rf_name(u16 rf_version)
2553 {
2554         int i;
2555
2556         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2557                 if (ath_rf_names[i].version == rf_version) {
2558                         return ath_rf_names[i].name;
2559                 }
2560         }
2561
2562         return "????";
2563 }
2564
2565 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2566 {
2567         void __iomem *mem;
2568         struct ath_softc *sc;
2569         struct ieee80211_hw *hw;
2570         u8 csz;
2571         u32 val;
2572         int ret = 0;
2573         struct ath_hal *ah;
2574
2575         if (pci_enable_device(pdev))
2576                 return -EIO;
2577
2578         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2579
2580         if (ret) {
2581                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2582                 goto bad;
2583         }
2584
2585         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2586
2587         if (ret) {
2588                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2589                         "DMA enable failed\n");
2590                 goto bad;
2591         }
2592
2593         /*
2594          * Cache line size is used to size and align various
2595          * structures used to communicate with the hardware.
2596          */
2597         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2598         if (csz == 0) {
2599                 /*
2600                  * Linux 2.4.18 (at least) writes the cache line size
2601                  * register as a 16-bit wide register which is wrong.
2602                  * We must have this setup properly for rx buffer
2603                  * DMA to work so force a reasonable value here if it
2604                  * comes up zero.
2605                  */
2606                 csz = L1_CACHE_BYTES / sizeof(u32);
2607                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2608         }
2609         /*
2610          * The default setting of latency timer yields poor results,
2611          * set it to the value used by other systems. It may be worth
2612          * tweaking this setting more.
2613          */
2614         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2615
2616         pci_set_master(pdev);
2617
2618         /*
2619          * Disable the RETRY_TIMEOUT register (0x41) to keep
2620          * PCI Tx retries from interfering with C3 CPU state.
2621          */
2622         pci_read_config_dword(pdev, 0x40, &val);
2623         if ((val & 0x0000ff00) != 0)
2624                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2625
2626         ret = pci_request_region(pdev, 0, "ath9k");
2627         if (ret) {
2628                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2629                 ret = -ENODEV;
2630                 goto bad;
2631         }
2632
2633         mem = pci_iomap(pdev, 0, 0);
2634         if (!mem) {
2635                 printk(KERN_ERR "PCI memory map error\n") ;
2636                 ret = -EIO;
2637                 goto bad1;
2638         }
2639
2640         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2641         if (hw == NULL) {
2642                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2643                 goto bad2;
2644         }
2645
2646         SET_IEEE80211_DEV(hw, &pdev->dev);
2647         pci_set_drvdata(pdev, hw);
2648
2649         sc = hw->priv;
2650         sc->hw = hw;
2651         sc->pdev = pdev;
2652         sc->mem = mem;
2653
2654         if (ath_attach(id->device, sc) != 0) {
2655                 ret = -ENODEV;
2656                 goto bad3;
2657         }
2658
2659         /* setup interrupt service routine */
2660
2661         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2662                 printk(KERN_ERR "%s: request_irq failed\n",
2663                         wiphy_name(hw->wiphy));
2664                 ret = -EIO;
2665                 goto bad4;
2666         }
2667
2668         ah = sc->sc_ah;
2669         printk(KERN_INFO
2670                "%s: Atheros AR%s MAC/BB Rev:%x "
2671                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2672                wiphy_name(hw->wiphy),
2673                ath_mac_bb_name(ah->ah_macVersion),
2674                ah->ah_macRev,
2675                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2676                ah->ah_phyRev,
2677                (unsigned long)mem, pdev->irq);
2678
2679         return 0;
2680 bad4:
2681         ath_detach(sc);
2682 bad3:
2683         ieee80211_free_hw(hw);
2684 bad2:
2685         pci_iounmap(pdev, mem);
2686 bad1:
2687         pci_release_region(pdev, 0);
2688 bad:
2689         pci_disable_device(pdev);
2690         return ret;
2691 }
2692
2693 static void ath_pci_remove(struct pci_dev *pdev)
2694 {
2695         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2696         struct ath_softc *sc = hw->priv;
2697
2698         ath_detach(sc);
2699         if (pdev->irq)
2700                 free_irq(pdev->irq, sc);
2701         pci_iounmap(pdev, sc->mem);
2702         pci_release_region(pdev, 0);
2703         pci_disable_device(pdev);
2704         ieee80211_free_hw(hw);
2705 }
2706
2707 #ifdef CONFIG_PM
2708
2709 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2710 {
2711         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2712         struct ath_softc *sc = hw->priv;
2713
2714         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2715
2716 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2717         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2718                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2719 #endif
2720
2721         pci_save_state(pdev);
2722         pci_disable_device(pdev);
2723         pci_set_power_state(pdev, 3);
2724
2725         return 0;
2726 }
2727
2728 static int ath_pci_resume(struct pci_dev *pdev)
2729 {
2730         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2731         struct ath_softc *sc = hw->priv;
2732         u32 val;
2733         int err;
2734
2735         err = pci_enable_device(pdev);
2736         if (err)
2737                 return err;
2738         pci_restore_state(pdev);
2739         /*
2740          * Suspend/Resume resets the PCI configuration space, so we have to
2741          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2742          * PCI Tx retries from interfering with C3 CPU state
2743          */
2744         pci_read_config_dword(pdev, 0x40, &val);
2745         if ((val & 0x0000ff00) != 0)
2746                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2747
2748         /* Enable LED */
2749         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2750                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2751         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2752
2753 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2754         /*
2755          * check the h/w rfkill state on resume
2756          * and start the rfkill poll timer
2757          */
2758         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2759                 queue_delayed_work(sc->hw->workqueue,
2760                                    &sc->rf_kill.rfkill_poll, 0);
2761 #endif
2762
2763         return 0;
2764 }
2765
2766 #endif /* CONFIG_PM */
2767
2768 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2769
2770 static struct pci_driver ath_pci_driver = {
2771         .name       = "ath9k",
2772         .id_table   = ath_pci_id_table,
2773         .probe      = ath_pci_probe,
2774         .remove     = ath_pci_remove,
2775 #ifdef CONFIG_PM
2776         .suspend    = ath_pci_suspend,
2777         .resume     = ath_pci_resume,
2778 #endif /* CONFIG_PM */
2779 };
2780
2781 static int __init init_ath_pci(void)
2782 {
2783         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2784
2785         if (pci_register_driver(&ath_pci_driver) < 0) {
2786                 printk(KERN_ERR
2787                         "ath_pci: No devices found, driver not installed.\n");
2788                 pci_unregister_driver(&ath_pci_driver);
2789                 return -ENODEV;
2790         }
2791
2792         return 0;
2793 }
2794 module_init(init_ath_pci);
2795
2796 static void __exit exit_ath_pci(void)
2797 {
2798         pci_unregister_driver(&ath_pci_driver);
2799         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2800 }
2801 module_exit(exit_ath_pci);