drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20
  21 #define ATH_PCI_VERSION "0.1"
  22
  23 static char *dev_info = "ath9k";
  24
  25 MODULE_AUTHOR("Atheros Communications");
  26 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  27 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  28 MODULE_LICENSE("Dual BSD/GPL");
  29
  30 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  31         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  32         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  33         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  34         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  36         { 0 }
  37 };
  38
  39 static void ath_detach(struct ath_softc *sc);
  40
  41 /* return bus cachesize in 4B word units */
  42
  43 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  44 {
  45         u8 u8tmp;
  46
  47         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  48         *csz = (int)u8tmp;
  49
  50         /*
  51          * This check was put in to avoid "unplesant" consequences if
  52          * the bootrom has not fully initialized all PCI devices.
  53          * Sometimes the cache line size register is not set
  54          */
  55
  56         if (*csz == 0)
  57                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  58 }
  59
  60 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
  61 {
  62         sc->sc_curmode = mode;
  63         /*
  64          * All protection frames are transmited at 2Mb/s for
  65          * 11g, otherwise at 1Mb/s.
  66          * XXX select protection rate index from rate table.
  67          */
  68         sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
  69 }
  70
  71 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
  72 {
  73         if (chan->chanmode == CHANNEL_A)
  74                 return ATH9K_MODE_11A;
  75         else if (chan->chanmode == CHANNEL_G)
  76                 return ATH9K_MODE_11G;
  77         else if (chan->chanmode == CHANNEL_B)
  78                 return ATH9K_MODE_11B;
  79         else if (chan->chanmode == CHANNEL_A_HT20)
  80                 return ATH9K_MODE_11NA_HT20;
  81         else if (chan->chanmode == CHANNEL_G_HT20)
  82                 return ATH9K_MODE_11NG_HT20;
  83         else if (chan->chanmode == CHANNEL_A_HT40PLUS)
  84                 return ATH9K_MODE_11NA_HT40PLUS;
  85         else if (chan->chanmode == CHANNEL_A_HT40MINUS)
  86                 return ATH9K_MODE_11NA_HT40MINUS;
  87         else if (chan->chanmode == CHANNEL_G_HT40PLUS)
  88                 return ATH9K_MODE_11NG_HT40PLUS;
  89         else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  90                 return ATH9K_MODE_11NG_HT40MINUS;
  91
  92         WARN_ON(1); /* should not get here */
  93
  94         return ATH9K_MODE_11B;
  95 }
  96
  97 static void ath_update_txpow(struct ath_softc *sc)
  98 {
  99         struct ath_hal *ah = sc->sc_ah;
 100         u32 txpow;
 101
 102         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 103                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 104                 /* read back in case value is clamped */
 105                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 106                 sc->sc_curtxpow = txpow;
 107         }
 108 }
 109
 110 static u8 parse_mpdudensity(u8 mpdudensity)
 111 {
 112         /*
 113          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 114          *   0 for no restriction
 115          *   1 for 1/4 us
 116          *   2 for 1/2 us
 117          *   3 for 1 us
 118          *   4 for 2 us
 119          *   5 for 4 us
 120          *   6 for 8 us
 121          *   7 for 16 us
 122          */
 123         switch (mpdudensity) {
 124         case 0:
 125                 return 0;
 126         case 1:
 127         case 2:
 128         case 3:
 129                 /* Our lower layer calculations limit our precision to
 130                    1 microsecond */
 131                 return 1;
 132         case 4:
 133                 return 2;
 134         case 5:
 135                 return 4;
 136         case 6:
 137                 return 8;
 138         case 7:
 139                 return 16;
 140         default:
 141                 return 0;
 142         }
 143 }
 144
 145 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 146 {
 147         struct ath_rate_table *rate_table = NULL;
 148         struct ieee80211_supported_band *sband;
 149         struct ieee80211_rate *rate;
 150         int i, maxrates;
 151
 152         switch (band) {
 153         case IEEE80211_BAND_2GHZ:
 154                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 155                 break;
 156         case IEEE80211_BAND_5GHZ:
 157                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 158                 break;
 159         default:
 160                 break;
 161         }
 162
 163         if (rate_table == NULL)
 164                 return;
 165
 166         sband = &sc->sbands[band];
 167         rate = sc->rates[band];
 168
 169         if (rate_table->rate_cnt > ATH_RATE_MAX)
 170                 maxrates = ATH_RATE_MAX;
 171         else
 172                 maxrates = rate_table->rate_cnt;
 173
 174         for (i = 0; i < maxrates; i++) {
 175                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 176                 rate[i].hw_value = rate_table->info[i].ratecode;
 177                 sband->n_bitrates++;
 178                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Rate: %2dMbps, ratecode: %2d\n",
 179                         __func__, rate[i].bitrate / 10, rate[i].hw_value);
 180         }
 181 }
 182
 183 static int ath_setup_channels(struct ath_softc *sc)
 184 {
 185         struct ath_hal *ah = sc->sc_ah;
 186         int nchan, i, a = 0, b = 0;
 187         u8 regclassids[ATH_REGCLASSIDS_MAX];
 188         u32 nregclass = 0;
 189         struct ieee80211_supported_band *band_2ghz;
 190         struct ieee80211_supported_band *band_5ghz;
 191         struct ieee80211_channel *chan_2ghz;
 192         struct ieee80211_channel *chan_5ghz;
 193         struct ath9k_channel *c;
 194
 195         /* Fill in ah->ah_channels */
 196         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 197                                       regclassids, ATH_REGCLASSIDS_MAX,
 198                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 199                 u32 rd = ah->ah_currentRD;
 200                 DPRINTF(sc, ATH_DBG_FATAL,
 201                         "%s: unable to collect channel list; "
 202                         "regdomain likely %u country code %u\n",
 203                         __func__, rd, CTRY_DEFAULT);
 204                 return -EINVAL;
 205         }
 206
 207         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 208         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 209         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 210         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 211
 212         for (i = 0; i < nchan; i++) {
 213                 c = &ah->ah_channels[i];
 214                 if (IS_CHAN_2GHZ(c)) {
 215                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 216                         chan_2ghz[a].center_freq = c->channel;
 217                         chan_2ghz[a].max_power = c->maxTxPower;
 218
 219                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 220                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 221                         if (c->channelFlags & CHANNEL_PASSIVE)
 222                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 223
 224                         band_2ghz->n_channels = ++a;
 225
 226                         DPRINTF(sc, ATH_DBG_CONFIG, "%s: 2MHz channel: %d, "
 227                                 "channelFlags: 0x%x\n",
 228                                 __func__, c->channel, c->channelFlags);
 229                 } else if (IS_CHAN_5GHZ(c)) {
 230                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 231                         chan_5ghz[b].center_freq = c->channel;
 232                         chan_5ghz[b].max_power = c->maxTxPower;
 233
 234                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 235                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 236                         if (c->channelFlags & CHANNEL_PASSIVE)
 237                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 238
 239                         band_5ghz->n_channels = ++b;
 240
 241                         DPRINTF(sc, ATH_DBG_CONFIG, "%s: 5MHz channel: %d, "
 242                                 "channelFlags: 0x%x\n",
 243                                 __func__, c->channel, c->channelFlags);
 244                 }
 245         }
 246
 247         return 0;
 248 }
 249
 250 /*
 251  * Set/change channels.  If the channel is really being changed, it's done
 252  * by reseting the chip.  To accomplish this we must first cleanup any pending
 253  * DMA, then restart stuff.
 254 */
 255 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 256 {
 257         struct ath_hal *ah = sc->sc_ah;
 258         bool fastcc = true, stopped;
 259
 260         if (sc->sc_flags & SC_OP_INVALID)
 261                 return -EIO;
 262
 263         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 264             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 265             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 266             (sc->sc_flags & SC_OP_FULL_RESET)) {
 267                 int status;
 268                 /*
 269                  * This is only performed if the channel settings have
 270                  * actually changed.
 271                  *
 272                  * To switch channels clear any pending DMA operations;
 273                  * wait long enough for the RX fifo to drain, reset the
 274                  * hardware at the new frequency, and then re-enable
 275                  * the relevant bits of the h/w.
 276                  */
 277                 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
 278                 ath_draintxq(sc, false);        /* clear pending tx frames */
 279                 stopped = ath_stoprecv(sc);     /* turn off frame recv */
 280
 281                 /* XXX: do not flush receive queue here. We don't want
 282                  * to flush data frames already in queue because of
 283                  * changing channel. */
 284
 285                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 286                         fastcc = false;
 287
 288                 DPRINTF(sc, ATH_DBG_CONFIG,
 289                         "%s: (%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
 290                         __func__,
 291                         sc->sc_ah->ah_curchan->channel,
 292                         hchan->channel, hchan->channelFlags, sc->tx_chan_width);
 293
 294                 spin_lock_bh(&sc->sc_resetlock);
 295                 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
 296                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 297                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 298                         DPRINTF(sc, ATH_DBG_FATAL,
 299                                 "%s: unable to reset channel %u (%uMhz) "
 300                                 "flags 0x%x hal status %u\n", __func__,
 301                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 302                                                   hchan->channelFlags),
 303                                 hchan->channel, hchan->channelFlags, status);
 304                         spin_unlock_bh(&sc->sc_resetlock);
 305                         return -EIO;
 306                 }
 307                 spin_unlock_bh(&sc->sc_resetlock);
 308
 309                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 310                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 311
 312                 if (ath_startrecv(sc) != 0) {
 313                         DPRINTF(sc, ATH_DBG_FATAL,
 314                                 "%s: unable to restart recv logic\n", __func__);
 315                         return -EIO;
 316                 }
 317
 318                 ath_setcurmode(sc, ath_chan2mode(hchan));
 319                 ath_update_txpow(sc);
 320                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 321         }
 322         return 0;
 323 }
 324
 325 /*
 326  *  This routine performs the periodic noise floor calibration function
 327  *  that is used to adjust and optimize the chip performance.  This
 328  *  takes environmental changes (location, temperature) into account.
 329  *  When the task is complete, it reschedules itself depending on the
 330  *  appropriate interval that was calculated.
 331  */
 332 static void ath_ani_calibrate(unsigned long data)
 333 {
 334         struct ath_softc *sc;
 335         struct ath_hal *ah;
 336         bool longcal = false;
 337         bool shortcal = false;
 338         bool aniflag = false;
 339         unsigned int timestamp = jiffies_to_msecs(jiffies);
 340         u32 cal_interval;
 341
 342         sc = (struct ath_softc *)data;
 343         ah = sc->sc_ah;
 344
 345         /*
 346         * don't calibrate when we're scanning.
 347         * we are most likely not on our home channel.
 348         */
 349         if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)
 350                 return;
 351
 352         /* Long calibration runs independently of short calibration. */
 353         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 354                 longcal = true;
 355                 DPRINTF(sc, ATH_DBG_ANI, "%s: longcal @%lu\n",
 356                         __func__, jiffies);
 357                 sc->sc_ani.sc_longcal_timer = timestamp;
 358         }
 359
 360         /* Short calibration applies only while sc_caldone is false */
 361         if (!sc->sc_ani.sc_caldone) {
 362                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 363                     ATH_SHORT_CALINTERVAL) {
 364                         shortcal = true;
 365                         DPRINTF(sc, ATH_DBG_ANI, "%s: shortcal @%lu\n",
 366                                __func__, jiffies);
 367                         sc->sc_ani.sc_shortcal_timer = timestamp;
 368                         sc->sc_ani.sc_resetcal_timer = timestamp;
 369                 }
 370         } else {
 371                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 372                     ATH_RESTART_CALINTERVAL) {
 373                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 374                                                 &sc->sc_ani.sc_caldone);
 375                         if (sc->sc_ani.sc_caldone)
 376                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 377                 }
 378         }
 379
 380         /* Verify whether we must check ANI */
 381         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 382            ATH_ANI_POLLINTERVAL) {
 383                 aniflag = true;
 384                 sc->sc_ani.sc_checkani_timer = timestamp;
 385         }
 386
 387         /* Skip all processing if there's nothing to do. */
 388         if (longcal || shortcal || aniflag) {
 389                 /* Call ANI routine if necessary */
 390                 if (aniflag)
 391                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 392                                              ah->ah_curchan);
 393
 394                 /* Perform calibration if necessary */
 395                 if (longcal || shortcal) {
 396                         bool iscaldone = false;
 397
 398                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 399                                                sc->sc_rx_chainmask, longcal,
 400                                                &iscaldone)) {
 401                                 if (longcal)
 402                                         sc->sc_ani.sc_noise_floor =
 403                                                 ath9k_hw_getchan_noise(ah,
 404                                                                ah->ah_curchan);
 405
 406                                 DPRINTF(sc, ATH_DBG_ANI,
 407                                         "%s: calibrate chan %u/%x nf: %d\n",
 408                                          __func__,
 409                                         ah->ah_curchan->channel,
 410                                         ah->ah_curchan->channelFlags,
 411                                         sc->sc_ani.sc_noise_floor);
 412                         } else {
 413                                 DPRINTF(sc, ATH_DBG_ANY,
 414                                         "%s: calibrate chan %u/%x failed\n",
 415                                          __func__,
 416                                         ah->ah_curchan->channel,
 417                                         ah->ah_curchan->channelFlags);
 418                         }
 419                         sc->sc_ani.sc_caldone = iscaldone;
 420                 }
 421         }
 422
 423         /*
 424         * Set timer interval based on previous results.
 425         * The interval must be the shortest necessary to satisfy ANI,
 426         * short calibration and long calibration.
 427         */
 428
 429         cal_interval = ATH_ANI_POLLINTERVAL;
 430         if (!sc->sc_ani.sc_caldone)
 431                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 432
 433         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 434 }
 435
 436 /*
 437  * Update tx/rx chainmask. For legacy association,
 438  * hard code chainmask to 1x1, for 11n association, use
 439  * the chainmask configuration.
 440  */
 441 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 442 {
 443         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 444         if (is_ht) {
 445                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 446                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 447         } else {
 448                 sc->sc_tx_chainmask = 1;
 449                 sc->sc_rx_chainmask = 1;
 450         }
 451
 452         DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
 453                 __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 454 }
 455
 456 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 457 {
 458         struct ath_node *an;
 459
 460         an = (struct ath_node *)sta->drv_priv;
 461
 462         if (sc->sc_flags & SC_OP_TXAGGR)
 463                 ath_tx_node_init(sc, an);
 464
 465         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 466                              sta->ht_cap.ampdu_factor);
 467         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 468 }
 469
 470 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 471 {
 472         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 473
 474         if (sc->sc_flags & SC_OP_TXAGGR)
 475                 ath_tx_node_cleanup(sc, an);
 476 }
 477
 478 static void ath9k_tasklet(unsigned long data)
 479 {
 480         struct ath_softc *sc = (struct ath_softc *)data;
 481         u32 status = sc->sc_intrstatus;
 482
 483         if (status & ATH9K_INT_FATAL) {
 484                 /* need a chip reset */
 485                 ath_reset(sc, false);
 486                 return;
 487         } else {
 488
 489                 if (status &
 490                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 491                         spin_lock_bh(&sc->sc_rxflushlock);
 492                         ath_rx_tasklet(sc, 0);
 493                         spin_unlock_bh(&sc->sc_rxflushlock);
 494                 }
 495                 /* XXX: optimize this */
 496                 if (status & ATH9K_INT_TX)
 497                         ath_tx_tasklet(sc);
 498         }
 499
 500         /* re-enable hardware interrupt */
 501         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 502 }
 503
 504 static irqreturn_t ath_isr(int irq, void *dev)
 505 {
 506         struct ath_softc *sc = dev;
 507         struct ath_hal *ah = sc->sc_ah;
 508         enum ath9k_int status;
 509         bool sched = false;
 510
 511         do {
 512                 if (sc->sc_flags & SC_OP_INVALID) {
 513                         /*
 514                          * The hardware is not ready/present, don't
 515                          * touch anything. Note this can happen early
 516                          * on if the IRQ is shared.
 517                          */
 518                         return IRQ_NONE;
 519                 }
 520                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 521                         return IRQ_NONE;
 522                 }
 523
 524                 /*
 525                  * Figure out the reason(s) for the interrupt.  Note
 526                  * that the hal returns a pseudo-ISR that may include
 527                  * bits we haven't explicitly enabled so we mask the
 528                  * value to insure we only process bits we requested.
 529                  */
 530                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 531
 532                 status &= sc->sc_imask; /* discard unasked-for bits */
 533
 534                 /*
 535                  * If there are no status bits set, then this interrupt was not
 536                  * for me (should have been caught above).
 537                  */
 538                 if (!status)
 539                         return IRQ_NONE;
 540
 541                 sc->sc_intrstatus = status;
 542
 543                 if (status & ATH9K_INT_FATAL) {
 544                         /* need a chip reset */
 545                         sched = true;
 546                 } else if (status & ATH9K_INT_RXORN) {
 547                         /* need a chip reset */
 548                         sched = true;
 549                 } else {
 550                         if (status & ATH9K_INT_SWBA) {
 551                                 /* schedule a tasklet for beacon handling */
 552                                 tasklet_schedule(&sc->bcon_tasklet);
 553                         }
 554                         if (status & ATH9K_INT_RXEOL) {
 555                                 /*
 556                                  * NB: the hardware should re-read the link when
 557                                  *     RXE bit is written, but it doesn't work
 558                                  *     at least on older hardware revs.
 559                                  */
 560                                 sched = true;
 561                         }
 562
 563                         if (status & ATH9K_INT_TXURN)
 564                                 /* bump tx trigger level */
 565                                 ath9k_hw_updatetxtriglevel(ah, true);
 566                         /* XXX: optimize this */
 567                         if (status & ATH9K_INT_RX)
 568                                 sched = true;
 569                         if (status & ATH9K_INT_TX)
 570                                 sched = true;
 571                         if (status & ATH9K_INT_BMISS)
 572                                 sched = true;
 573                         /* carrier sense timeout */
 574                         if (status & ATH9K_INT_CST)
 575                                 sched = true;
 576                         if (status & ATH9K_INT_MIB) {
 577                                 /*
 578                                  * Disable interrupts until we service the MIB
 579                                  * interrupt; otherwise it will continue to
 580                                  * fire.
 581                                  */
 582                                 ath9k_hw_set_interrupts(ah, 0);
 583                                 /*
 584                                  * Let the hal handle the event. We assume
 585                                  * it will clear whatever condition caused
 586                                  * the interrupt.
 587                                  */
 588                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 589                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 590                         }
 591                         if (status & ATH9K_INT_TIM_TIMER) {
 592                                 if (!(ah->ah_caps.hw_caps &
 593                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 594                                         /* Clear RxAbort bit so that we can
 595                                          * receive frames */
 596                                         ath9k_hw_setrxabort(ah, 0);
 597                                         sched = true;
 598                                 }
 599                         }
 600                 }
 601         } while (0);
 602
 603         if (sched) {
 604                 /* turn off every interrupt except SWBA */
 605                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 606                 tasklet_schedule(&sc->intr_tq);
 607         }
 608
 609         return IRQ_HANDLED;
 610 }
 611
 612 static int ath_get_channel(struct ath_softc *sc,
 613                            struct ieee80211_channel *chan)
 614 {
 615         int i;
 616
 617         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 618                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 619                         return i;
 620         }
 621
 622         return -1;
 623 }
 624
 625 /* ext_chan_offset: (-1, 0, 1) (below, none, above) */
 626
 627 static u32 ath_get_extchanmode(struct ath_softc *sc,
 628                                struct ieee80211_channel *chan,
 629                                int ext_chan_offset,
 630                                enum ath9k_ht_macmode tx_chan_width)
 631 {
 632         u32 chanmode = 0;
 633
 634         switch (chan->band) {
 635         case IEEE80211_BAND_2GHZ:
 636                 if ((ext_chan_offset == 0) &&
 637                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 638                         chanmode = CHANNEL_G_HT20;
 639                 if ((ext_chan_offset == 1) &&
 640                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 641                         chanmode = CHANNEL_G_HT40PLUS;
 642                 if ((ext_chan_offset == -1) &&
 643                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 644                         chanmode = CHANNEL_G_HT40MINUS;
 645                 break;
 646         case IEEE80211_BAND_5GHZ:
 647                 if ((ext_chan_offset == 0) &&
 648                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 649                         chanmode = CHANNEL_A_HT20;
 650                 if ((ext_chan_offset == 1) &&
 651                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 652                         chanmode = CHANNEL_A_HT40PLUS;
 653                 if ((ext_chan_offset == -1) &&
 654                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 655                         chanmode = CHANNEL_A_HT40MINUS;
 656                 break;
 657         default:
 658                 break;
 659         }
 660
 661         return chanmode;
 662 }
 663
 664 static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
 665 {
 666         ath9k_hw_keyreset(sc->sc_ah, keyix);
 667         if (freeslot)
 668                 clear_bit(keyix, sc->sc_keymap);
 669 }
 670
 671 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 672                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 673 {
 674         bool status;
 675
 676         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 677                 keyix, hk, mac, false);
 678
 679         return status != false;
 680 }
 681
 682 static int ath_setkey_tkip(struct ath_softc *sc,
 683                            struct ieee80211_key_conf *key,
 684                            struct ath9k_keyval *hk,
 685                            const u8 *addr)
 686 {
 687         u8 *key_rxmic = NULL;
 688         u8 *key_txmic = NULL;
 689
 690         key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 691         key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 692
 693         if (addr == NULL) {
 694                 /* Group key installation */
 695                 memcpy(hk->kv_mic,  key_rxmic, sizeof(hk->kv_mic));
 696                 return ath_keyset(sc, key->keyidx, hk, addr);
 697         }
 698         if (!sc->sc_splitmic) {
 699                 /*
 700                  * data key goes at first index,
 701                  * the hal handles the MIC keys at index+64.
 702                  */
 703                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 704                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 705                 return ath_keyset(sc, key->keyidx, hk, addr);
 706         }
 707         /*
 708          * TX key goes at first index, RX key at +32.
 709          * The hal handles the MIC keys at index+64.
 710          */
 711         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 712         if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
 713                 /* Txmic entry failed. No need to proceed further */
 714                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 715                         "%s Setting TX MIC Key Failed\n", __func__);
 716                 return 0;
 717         }
 718
 719         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 720         /* XXX delete tx key on failure? */
 721         return ath_keyset(sc, key->keyidx+32, hk, addr);
 722 }
 723
 724 static int ath_key_config(struct ath_softc *sc,
 725                           const u8 *addr,
 726                           struct ieee80211_key_conf *key)
 727 {
 728         struct ieee80211_vif *vif;
 729         struct ath9k_keyval hk;
 730         const u8 *mac = NULL;
 731         int ret = 0;
 732         enum nl80211_iftype opmode;
 733
 734         memset(&hk, 0, sizeof(hk));
 735
 736         switch (key->alg) {
 737         case ALG_WEP:
 738                 hk.kv_type = ATH9K_CIPHER_WEP;
 739                 break;
 740         case ALG_TKIP:
 741                 hk.kv_type = ATH9K_CIPHER_TKIP;
 742                 break;
 743         case ALG_CCMP:
 744                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 745                 break;
 746         default:
 747                 return -EINVAL;
 748         }
 749
 750         hk.kv_len  = key->keylen;
 751         memcpy(hk.kv_val, key->key, key->keylen);
 752
 753         if (!sc->sc_vaps[0])
 754                 return -EIO;
 755
 756         vif = sc->sc_vaps[0];
 757         opmode = vif->type;
 758
 759         /*
 760          *  Strategy:
 761          *   For _M_STA mc tx, we will not setup a key at all since we never
 762          *   tx mc.
 763          *   _M_STA mc rx, we will use the keyID.
 764          *   for _M_IBSS mc tx, we will use the keyID, and no macaddr.
 765          *   for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
 766          *   peer node. BUT we will plumb a cleartext key so that we can do
 767          *   perSta default key table lookup in software.
 768          */
 769         if (is_broadcast_ether_addr(addr)) {
 770                 switch (opmode) {
 771                 case NL80211_IFTYPE_STATION:
 772                         /* default key:  could be group WPA key
 773                          * or could be static WEP key */
 774                         mac = NULL;
 775                         break;
 776                 case NL80211_IFTYPE_ADHOC:
 777                         break;
 778                 case NL80211_IFTYPE_AP:
 779                         break;
 780                 default:
 781                         ASSERT(0);
 782                         break;
 783                 }
 784         } else {
 785                 mac = addr;
 786         }
 787
 788         if (key->alg == ALG_TKIP)
 789                 ret = ath_setkey_tkip(sc, key, &hk, mac);
 790         else
 791                 ret = ath_keyset(sc, key->keyidx, &hk, mac);
 792
 793         if (!ret)
 794                 return -EIO;
 795
 796         return 0;
 797 }
 798
 799 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 800 {
 801         int freeslot;
 802
 803         freeslot = (key->keyidx >= 4) ? 1 : 0;
 804         ath_key_reset(sc, key->keyidx, freeslot);
 805 }
 806
 807 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 808 {
 809 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 810 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 811
 812         ht_info->ht_supported = true;
 813         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 814                        IEEE80211_HT_CAP_SM_PS |
 815                        IEEE80211_HT_CAP_SGI_40 |
 816                        IEEE80211_HT_CAP_DSSSCCK40;
 817
 818         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 819         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 820         /* set up supported mcs set */
 821         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 822         ht_info->mcs.rx_mask[0] = 0xff;
 823         ht_info->mcs.rx_mask[1] = 0xff;
 824         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 825 }
 826
 827 static void ath9k_ht_conf(struct ath_softc *sc,
 828                           struct ieee80211_bss_conf *bss_conf)
 829 {
 830         if (sc->hw->conf.ht.enabled) {
 831                 if (bss_conf->ht.width_40_ok)
 832                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
 833                 else
 834                         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
 835
 836                 ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width);
 837
 838                 DPRINTF(sc, ATH_DBG_CONFIG,
 839                         "%s: BSS Changed HT, chanwidth: %d\n",
 840                         __func__, sc->tx_chan_width);
 841         }
 842 }
 843
 844 static inline int ath_sec_offset(u8 ext_offset)
 845 {
 846         if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE)
 847                 return 0;
 848         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
 849                 return 1;
 850         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
 851                 return -1;
 852
 853         return 0;
 854 }
 855
 856 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 857                                  struct ieee80211_vif *vif,
 858                                  struct ieee80211_bss_conf *bss_conf)
 859 {
 860         struct ieee80211_hw *hw = sc->hw;
 861         struct ieee80211_channel *curchan = hw->conf.channel;
 862         struct ath_vap *avp = (void *)vif->drv_priv;
 863         int pos;
 864
 865         if (bss_conf->assoc) {
 866                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
 867                         __func__,
 868                         bss_conf->aid);
 869
 870                 /* New association, store aid */
 871                 if (avp->av_opmode == ATH9K_M_STA) {
 872                         sc->sc_curaid = bss_conf->aid;
 873                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 874                                                sc->sc_curaid);
 875                 }
 876
 877                 /* Configure the beacon */
 878                 ath_beacon_config(sc, 0);
 879                 sc->sc_flags |= SC_OP_BEACONS;
 880
 881                 /* Reset rssi stats */
 882                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 883                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 884                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 885                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 886
 887                 /* Update chainmask */
 888                 ath_update_chainmask(sc, hw->conf.ht.enabled);
 889
 890                 DPRINTF(sc, ATH_DBG_CONFIG,
 891                         "%s: bssid %pM aid 0x%x\n",
 892                         __func__,
 893                         sc->sc_curbssid, sc->sc_curaid);
 894
 895                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
 896                         __func__,
 897                         curchan->center_freq);
 898
 899                 pos = ath_get_channel(sc, curchan);
 900                 if (pos == -1) {
 901                         DPRINTF(sc, ATH_DBG_FATAL,
 902                                 "%s: Invalid channel\n", __func__);
 903                         return;
 904                 }
 905
 906                 if (hw->conf.ht.enabled) {
 907                         int offset =
 908                                 ath_sec_offset(bss_conf->ht.secondary_channel_offset);
 909                         sc->tx_chan_width = (bss_conf->ht.width_40_ok) ?
 910                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
 911
 912                         sc->sc_ah->ah_channels[pos].chanmode =
 913                                 ath_get_extchanmode(sc, curchan,
 914                                                     offset, sc->tx_chan_width);
 915                 } else {
 916                         sc->sc_ah->ah_channels[pos].chanmode =
 917                                 (curchan->band == IEEE80211_BAND_2GHZ) ?
 918                                 CHANNEL_G : CHANNEL_A;
 919                 }
 920
 921                 /* set h/w channel */
 922                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
 923                         DPRINTF(sc, ATH_DBG_FATAL,
 924                                 "%s: Unable to set channel\n", __func__);
 925                 /* Start ANI */
 926                 mod_timer(&sc->sc_ani.timer,
 927                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 928
 929         } else {
 930                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info DISSOC\n", __func__);
 931                 sc->sc_curaid = 0;
 932         }
 933 }
 934
 935 /********************************/
 936 /*       LED functions          */
 937 /********************************/
 938
 939 static void ath_led_brightness(struct led_classdev *led_cdev,
 940                                enum led_brightness brightness)
 941 {
 942         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 943         struct ath_softc *sc = led->sc;
 944
 945         switch (brightness) {
 946         case LED_OFF:
 947                 if (led->led_type == ATH_LED_ASSOC ||
 948                     led->led_type == ATH_LED_RADIO)
 949                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 950                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 951                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 952                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 953                 break;
 954         case LED_FULL:
 955                 if (led->led_type == ATH_LED_ASSOC)
 956                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 957                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 958                 break;
 959         default:
 960                 break;
 961         }
 962 }
 963
 964 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 965                             char *trigger)
 966 {
 967         int ret;
 968
 969         led->sc = sc;
 970         led->led_cdev.name = led->name;
 971         led->led_cdev.default_trigger = trigger;
 972         led->led_cdev.brightness_set = ath_led_brightness;
 973
 974         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 975         if (ret)
 976                 DPRINTF(sc, ATH_DBG_FATAL,
 977                         "Failed to register led:%s", led->name);
 978         else
 979                 led->registered = 1;
 980         return ret;
 981 }
 982
 983 static void ath_unregister_led(struct ath_led *led)
 984 {
 985         if (led->registered) {
 986                 led_classdev_unregister(&led->led_cdev);
 987                 led->registered = 0;
 988         }
 989 }
 990
 991 static void ath_deinit_leds(struct ath_softc *sc)
 992 {
 993         ath_unregister_led(&sc->assoc_led);
 994         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 995         ath_unregister_led(&sc->tx_led);
 996         ath_unregister_led(&sc->rx_led);
 997         ath_unregister_led(&sc->radio_led);
 998         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 999 }
1000
1001 static void ath_init_leds(struct ath_softc *sc)
1002 {
1003         char *trigger;
1004         int ret;
1005
1006         /* Configure gpio 1 for output */
1007         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1008                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1009         /* LED off, active low */
1010         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1011
1012         trigger = ieee80211_get_radio_led_name(sc->hw);
1013         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1014                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1015         ret = ath_register_led(sc, &sc->radio_led, trigger);
1016         sc->radio_led.led_type = ATH_LED_RADIO;
1017         if (ret)
1018                 goto fail;
1019
1020         trigger = ieee80211_get_assoc_led_name(sc->hw);
1021         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1022                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1023         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1024         sc->assoc_led.led_type = ATH_LED_ASSOC;
1025         if (ret)
1026                 goto fail;
1027
1028         trigger = ieee80211_get_tx_led_name(sc->hw);
1029         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1030                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1031         ret = ath_register_led(sc, &sc->tx_led, trigger);
1032         sc->tx_led.led_type = ATH_LED_TX;
1033         if (ret)
1034                 goto fail;
1035
1036         trigger = ieee80211_get_rx_led_name(sc->hw);
1037         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1038                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1039         ret = ath_register_led(sc, &sc->rx_led, trigger);
1040         sc->rx_led.led_type = ATH_LED_RX;
1041         if (ret)
1042                 goto fail;
1043
1044         return;
1045
1046 fail:
1047         ath_deinit_leds(sc);
1048 }
1049
1050 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1051
1052 /*******************/
1053 /*      Rfkill     */
1054 /*******************/
1055
1056 static void ath_radio_enable(struct ath_softc *sc)
1057 {
1058         struct ath_hal *ah = sc->sc_ah;
1059         int status;
1060
1061         spin_lock_bh(&sc->sc_resetlock);
1062         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1063                             sc->tx_chan_width,
1064                             sc->sc_tx_chainmask,
1065                             sc->sc_rx_chainmask,
1066                             sc->sc_ht_extprotspacing,
1067                             false, &status)) {
1068                 DPRINTF(sc, ATH_DBG_FATAL,
1069                         "%s: unable to reset channel %u (%uMhz) "
1070                         "flags 0x%x hal status %u\n", __func__,
1071                         ath9k_hw_mhz2ieee(ah,
1072                                           ah->ah_curchan->channel,
1073                                           ah->ah_curchan->channelFlags),
1074                         ah->ah_curchan->channel,
1075                         ah->ah_curchan->channelFlags, status);
1076         }
1077         spin_unlock_bh(&sc->sc_resetlock);
1078
1079         ath_update_txpow(sc);
1080         if (ath_startrecv(sc) != 0) {
1081                 DPRINTF(sc, ATH_DBG_FATAL,
1082                         "%s: unable to restart recv logic\n", __func__);
1083                 return;
1084         }
1085
1086         if (sc->sc_flags & SC_OP_BEACONS)
1087                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1088
1089         /* Re-Enable  interrupts */
1090         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1091
1092         /* Enable LED */
1093         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1094                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1095         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1096
1097         ieee80211_wake_queues(sc->hw);
1098 }
1099
1100 static void ath_radio_disable(struct ath_softc *sc)
1101 {
1102         struct ath_hal *ah = sc->sc_ah;
1103         int status;
1104
1105
1106         ieee80211_stop_queues(sc->hw);
1107
1108         /* Disable LED */
1109         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1110         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1111
1112         /* Disable interrupts */
1113         ath9k_hw_set_interrupts(ah, 0);
1114
1115         ath_draintxq(sc, false);        /* clear pending tx frames */
1116         ath_stoprecv(sc);               /* turn off frame recv */
1117         ath_flushrecv(sc);              /* flush recv queue */
1118
1119         spin_lock_bh(&sc->sc_resetlock);
1120         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1121                             sc->tx_chan_width,
1122                             sc->sc_tx_chainmask,
1123                             sc->sc_rx_chainmask,
1124                             sc->sc_ht_extprotspacing,
1125                             false, &status)) {
1126                 DPRINTF(sc, ATH_DBG_FATAL,
1127                         "%s: unable to reset channel %u (%uMhz) "
1128                         "flags 0x%x hal status %u\n", __func__,
1129                         ath9k_hw_mhz2ieee(ah,
1130                                 ah->ah_curchan->channel,
1131                                 ah->ah_curchan->channelFlags),
1132                         ah->ah_curchan->channel,
1133                         ah->ah_curchan->channelFlags, status);
1134         }
1135         spin_unlock_bh(&sc->sc_resetlock);
1136
1137         ath9k_hw_phy_disable(ah);
1138         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1139 }
1140
1141 static bool ath_is_rfkill_set(struct ath_softc *sc)
1142 {
1143         struct ath_hal *ah = sc->sc_ah;
1144
1145         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1146                                   ah->ah_rfkill_polarity;
1147 }
1148
1149 /* h/w rfkill poll function */
1150 static void ath_rfkill_poll(struct work_struct *work)
1151 {
1152         struct ath_softc *sc = container_of(work, struct ath_softc,
1153                                             rf_kill.rfkill_poll.work);
1154         bool radio_on;
1155
1156         if (sc->sc_flags & SC_OP_INVALID)
1157                 return;
1158
1159         radio_on = !ath_is_rfkill_set(sc);
1160
1161         /*
1162          * enable/disable radio only when there is a
1163          * state change in RF switch
1164          */
1165         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1166                 enum rfkill_state state;
1167
1168                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1169                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1170                                 : RFKILL_STATE_HARD_BLOCKED;
1171                 } else if (radio_on) {
1172                         ath_radio_enable(sc);
1173                         state = RFKILL_STATE_UNBLOCKED;
1174                 } else {
1175                         ath_radio_disable(sc);
1176                         state = RFKILL_STATE_HARD_BLOCKED;
1177                 }
1178
1179                 if (state == RFKILL_STATE_HARD_BLOCKED)
1180                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1181                 else
1182                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1183
1184                 rfkill_force_state(sc->rf_kill.rfkill, state);
1185         }
1186
1187         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1188                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1189 }
1190
1191 /* s/w rfkill handler */
1192 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1193 {
1194         struct ath_softc *sc = data;
1195
1196         switch (state) {
1197         case RFKILL_STATE_SOFT_BLOCKED:
1198                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1199                     SC_OP_RFKILL_SW_BLOCKED)))
1200                         ath_radio_disable(sc);
1201                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1202                 return 0;
1203         case RFKILL_STATE_UNBLOCKED:
1204                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1205                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1206                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1207                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1208                                         "radio as it is disabled by h/w \n");
1209                                 return -EPERM;
1210                         }
1211                         ath_radio_enable(sc);
1212                 }
1213                 return 0;
1214         default:
1215                 return -EINVAL;
1216         }
1217 }
1218
1219 /* Init s/w rfkill */
1220 static int ath_init_sw_rfkill(struct ath_softc *sc)
1221 {
1222         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1223                                              RFKILL_TYPE_WLAN);
1224         if (!sc->rf_kill.rfkill) {
1225                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1226                 return -ENOMEM;
1227         }
1228
1229         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1230                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1231         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1232         sc->rf_kill.rfkill->data = sc;
1233         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1234         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1235         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1236
1237         return 0;
1238 }
1239
1240 /* Deinitialize rfkill */
1241 static void ath_deinit_rfkill(struct ath_softc *sc)
1242 {
1243         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1244                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1245
1246         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1247                 rfkill_unregister(sc->rf_kill.rfkill);
1248                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1249                 sc->rf_kill.rfkill = NULL;
1250         }
1251 }
1252
1253 static int ath_start_rfkill_poll(struct ath_softc *sc)
1254 {
1255         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1256                 queue_delayed_work(sc->hw->workqueue,
1257                                    &sc->rf_kill.rfkill_poll, 0);
1258
1259         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1260                 if (rfkill_register(sc->rf_kill.rfkill)) {
1261                         DPRINTF(sc, ATH_DBG_FATAL,
1262                                 "Unable to register rfkill\n");
1263                         rfkill_free(sc->rf_kill.rfkill);
1264
1265                         /* Deinitialize the device */
1266                         ath_detach(sc);
1267                         if (sc->pdev->irq)
1268                                 free_irq(sc->pdev->irq, sc);
1269                         pci_iounmap(sc->pdev, sc->mem);
1270                         pci_release_region(sc->pdev, 0);
1271                         pci_disable_device(sc->pdev);
1272                         ieee80211_free_hw(sc->hw);
1273                         return -EIO;
1274                 } else {
1275                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1276                 }
1277         }
1278
1279         return 0;
1280 }
1281 #endif /* CONFIG_RFKILL */
1282
1283 static void ath_detach(struct ath_softc *sc)
1284 {
1285         struct ieee80211_hw *hw = sc->hw;
1286         int i = 0;
1287
1288         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
1289
1290 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1291         ath_deinit_rfkill(sc);
1292 #endif
1293         ath_deinit_leds(sc);
1294
1295         ieee80211_unregister_hw(hw);
1296
1297         ath_rate_control_unregister();
1298
1299         ath_rx_cleanup(sc);
1300         ath_tx_cleanup(sc);
1301
1302         tasklet_kill(&sc->intr_tq);
1303         tasklet_kill(&sc->bcon_tasklet);
1304
1305         if (!(sc->sc_flags & SC_OP_INVALID))
1306                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1307
1308         /* cleanup tx queues */
1309         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1310                 if (ATH_TXQ_SETUP(sc, i))
1311                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1312
1313         ath9k_hw_detach(sc->sc_ah);
1314 }
1315
1316 static int ath_init(u16 devid, struct ath_softc *sc)
1317 {
1318         struct ath_hal *ah = NULL;
1319         int status;
1320         int error = 0, i;
1321         int csz = 0;
1322
1323         /* XXX: hardware will not be ready until ath_open() being called */
1324         sc->sc_flags |= SC_OP_INVALID;
1325         sc->sc_debug = DBG_DEFAULT;
1326
1327         spin_lock_init(&sc->sc_resetlock);
1328         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1329         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1330                      (unsigned long)sc);
1331
1332         /*
1333          * Cache line size is used to size and align various
1334          * structures used to communicate with the hardware.
1335          */
1336         bus_read_cachesize(sc, &csz);
1337         /* XXX assert csz is non-zero */
1338         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1339
1340         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1341         if (ah == NULL) {
1342                 DPRINTF(sc, ATH_DBG_FATAL,
1343                         "%s: unable to attach hardware; HAL status %u\n",
1344                         __func__, status);
1345                 error = -ENXIO;
1346                 goto bad;
1347         }
1348         sc->sc_ah = ah;
1349
1350         /* Get the hardware key cache size. */
1351         sc->sc_keymax = ah->ah_caps.keycache_size;
1352         if (sc->sc_keymax > ATH_KEYMAX) {
1353                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1354                         "%s: Warning, using only %u entries in %u key cache\n",
1355                         __func__, ATH_KEYMAX, sc->sc_keymax);
1356                 sc->sc_keymax = ATH_KEYMAX;
1357         }
1358
1359         /*
1360          * Reset the key cache since some parts do not
1361          * reset the contents on initial power up.
1362          */
1363         for (i = 0; i < sc->sc_keymax; i++)
1364                 ath9k_hw_keyreset(ah, (u16) i);
1365         /*
1366          * Mark key cache slots associated with global keys
1367          * as in use.  If we knew TKIP was not to be used we
1368          * could leave the +32, +64, and +32+64 slots free.
1369          * XXX only for splitmic.
1370          */
1371         for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1372                 set_bit(i, sc->sc_keymap);
1373                 set_bit(i + 32, sc->sc_keymap);
1374                 set_bit(i + 64, sc->sc_keymap);
1375                 set_bit(i + 32 + 64, sc->sc_keymap);
1376         }
1377
1378         /* Collect the channel list using the default country code */
1379
1380         error = ath_setup_channels(sc);
1381         if (error)
1382                 goto bad;
1383
1384         /* default to MONITOR mode */
1385         sc->sc_ah->ah_opmode = ATH9K_M_MONITOR;
1386
1387         /* Setup rate tables */
1388
1389         ath_rate_attach(sc);
1390         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1391         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1392
1393         /*
1394          * Allocate hardware transmit queues: one queue for
1395          * beacon frames and one data queue for each QoS
1396          * priority.  Note that the hal handles reseting
1397          * these queues at the needed time.
1398          */
1399         sc->sc_bhalq = ath_beaconq_setup(ah);
1400         if (sc->sc_bhalq == -1) {
1401                 DPRINTF(sc, ATH_DBG_FATAL,
1402                         "%s: unable to setup a beacon xmit queue\n", __func__);
1403                 error = -EIO;
1404                 goto bad2;
1405         }
1406         sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1407         if (sc->sc_cabq == NULL) {
1408                 DPRINTF(sc, ATH_DBG_FATAL,
1409                         "%s: unable to setup CAB xmit queue\n", __func__);
1410                 error = -EIO;
1411                 goto bad2;
1412         }
1413
1414         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1415         ath_cabq_update(sc);
1416
1417         for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1418                 sc->sc_haltype2q[i] = -1;
1419
1420         /* Setup data queues */
1421         /* NB: ensure BK queue is the lowest priority h/w queue */
1422         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1423                 DPRINTF(sc, ATH_DBG_FATAL,
1424                         "%s: unable to setup xmit queue for BK traffic\n",
1425                         __func__);
1426                 error = -EIO;
1427                 goto bad2;
1428         }
1429
1430         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1431                 DPRINTF(sc, ATH_DBG_FATAL,
1432                         "%s: unable to setup xmit queue for BE traffic\n",
1433                         __func__);
1434                 error = -EIO;
1435                 goto bad2;
1436         }
1437         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1438                 DPRINTF(sc, ATH_DBG_FATAL,
1439                         "%s: unable to setup xmit queue for VI traffic\n",
1440                         __func__);
1441                 error = -EIO;
1442                 goto bad2;
1443         }
1444         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1445                 DPRINTF(sc, ATH_DBG_FATAL,
1446                         "%s: unable to setup xmit queue for VO traffic\n",
1447                         __func__);
1448                 error = -EIO;
1449                 goto bad2;
1450         }
1451
1452         /* Initializes the noise floor to a reasonable default value.
1453          * Later on this will be updated during ANI processing. */
1454
1455         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1456         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1457
1458         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1459                                    ATH9K_CIPHER_TKIP, NULL)) {
1460                 /*
1461                  * Whether we should enable h/w TKIP MIC.
1462                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1463                  * report WMM capable, so it's always safe to turn on
1464                  * TKIP MIC in this case.
1465                  */
1466                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1467                                        0, 1, NULL);
1468         }
1469
1470         /*
1471          * Check whether the separate key cache entries
1472          * are required to handle both tx+rx MIC keys.
1473          * With split mic keys the number of stations is limited
1474          * to 27 otherwise 59.
1475          */
1476         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1477                                    ATH9K_CIPHER_TKIP, NULL)
1478             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1479                                       ATH9K_CIPHER_MIC, NULL)
1480             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1481                                       0, NULL))
1482                 sc->sc_splitmic = 1;
1483
1484         /* turn on mcast key search if possible */
1485         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1486                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1487                                              1, NULL);
1488
1489         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1490         sc->sc_config.txpowlimit_override = 0;
1491
1492         /* 11n Capabilities */
1493         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1494                 sc->sc_flags |= SC_OP_TXAGGR;
1495                 sc->sc_flags |= SC_OP_RXAGGR;
1496         }
1497
1498         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1499         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1500
1501         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1502         sc->sc_defant = ath9k_hw_getdefantenna(ah);
1503
1504         ath9k_hw_getmac(ah, sc->sc_myaddr);
1505         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1506                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1507                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1508                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1509         }
1510
1511         sc->sc_slottime = ATH9K_SLOT_TIME_9;    /* default to short slot time */
1512
1513         /* initialize beacon slots */
1514         for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1515                 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1516
1517         /* save MISC configurations */
1518         sc->sc_config.swBeaconProcess = 1;
1519
1520 #ifdef CONFIG_SLOW_ANT_DIV
1521         /* range is 40 - 255, we use something in the middle */
1522         ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1523 #endif
1524
1525         /* setup channels and rates */
1526
1527         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1528                 sc->channels[IEEE80211_BAND_2GHZ];
1529         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1530                 sc->rates[IEEE80211_BAND_2GHZ];
1531         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1532
1533         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1534                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1535                         sc->channels[IEEE80211_BAND_5GHZ];
1536                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1537                         sc->rates[IEEE80211_BAND_5GHZ];
1538                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1539         }
1540
1541         return 0;
1542 bad2:
1543         /* cleanup tx queues */
1544         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1545                 if (ATH_TXQ_SETUP(sc, i))
1546                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1547 bad:
1548         if (ah)
1549                 ath9k_hw_detach(ah);
1550
1551         return error;
1552 }
1553
1554 static int ath_attach(u16 devid, struct ath_softc *sc)
1555 {
1556         struct ieee80211_hw *hw = sc->hw;
1557         int error = 0;
1558
1559         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
1560
1561         error = ath_init(devid, sc);
1562         if (error != 0)
1563                 return error;
1564
1565         /* get mac address from hardware and set in mac80211 */
1566
1567         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1568
1569         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1570                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1571                 IEEE80211_HW_SIGNAL_DBM |
1572                 IEEE80211_HW_AMPDU_AGGREGATION;
1573
1574         hw->wiphy->interface_modes =
1575                 BIT(NL80211_IFTYPE_AP) |
1576                 BIT(NL80211_IFTYPE_STATION) |
1577                 BIT(NL80211_IFTYPE_ADHOC);
1578
1579         hw->queues = 4;
1580         hw->max_rates = 4;
1581         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1582         hw->sta_data_size = sizeof(struct ath_node);
1583         hw->vif_data_size = sizeof(struct ath_vap);
1584
1585         /* Register rate control */
1586         hw->rate_control_algorithm = "ath9k_rate_control";
1587         error = ath_rate_control_register();
1588         if (error != 0) {
1589                 DPRINTF(sc, ATH_DBG_FATAL,
1590                         "%s: Unable to register rate control "
1591                         "algorithm:%d\n", __func__, error);
1592                 ath_rate_control_unregister();
1593                 goto bad;
1594         }
1595
1596         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1597                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1598                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1599                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1600         }
1601
1602         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1603         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1604                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1605                         &sc->sbands[IEEE80211_BAND_5GHZ];
1606
1607         /* initialize tx/rx engine */
1608         error = ath_tx_init(sc, ATH_TXBUF);
1609         if (error != 0)
1610                 goto detach;
1611
1612         error = ath_rx_init(sc, ATH_RXBUF);
1613         if (error != 0)
1614                 goto detach;
1615
1616 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1617         /* Initialze h/w Rfkill */
1618         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1619                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1620
1621         /* Initialize s/w rfkill */
1622         if (ath_init_sw_rfkill(sc))
1623                 goto detach;
1624 #endif
1625
1626         error = ieee80211_register_hw(hw);
1627         if (error != 0) {
1628                 ath_rate_control_unregister();
1629                 goto bad;
1630         }
1631
1632         /* Initialize LED control */
1633         ath_init_leds(sc);
1634
1635         return 0;
1636 detach:
1637         ath_detach(sc);
1638 bad:
1639         return error;
1640 }
1641
1642 int ath_reset(struct ath_softc *sc, bool retry_tx)
1643 {
1644         struct ath_hal *ah = sc->sc_ah;
1645         int status;
1646         int error = 0;
1647
1648         ath9k_hw_set_interrupts(ah, 0);
1649         ath_draintxq(sc, retry_tx);
1650         ath_stoprecv(sc);
1651         ath_flushrecv(sc);
1652
1653         spin_lock_bh(&sc->sc_resetlock);
1654         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1655                             sc->tx_chan_width,
1656                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1657                             sc->sc_ht_extprotspacing, false, &status)) {
1658                 DPRINTF(sc, ATH_DBG_FATAL,
1659                         "%s: unable to reset hardware; hal status %u\n",
1660                         __func__, status);
1661                 error = -EIO;
1662         }
1663         spin_unlock_bh(&sc->sc_resetlock);
1664
1665         if (ath_startrecv(sc) != 0)
1666                 DPRINTF(sc, ATH_DBG_FATAL,
1667                         "%s: unable to start recv logic\n", __func__);
1668
1669         /*
1670          * We may be doing a reset in response to a request
1671          * that changes the channel so update any state that
1672          * might change as a result.
1673          */
1674         ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1675
1676         ath_update_txpow(sc);
1677
1678         if (sc->sc_flags & SC_OP_BEACONS)
1679                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1680
1681         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1682
1683         if (retry_tx) {
1684                 int i;
1685                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1686                         if (ATH_TXQ_SETUP(sc, i)) {
1687                                 spin_lock_bh(&sc->sc_txq[i].axq_lock);
1688                                 ath_txq_schedule(sc, &sc->sc_txq[i]);
1689                                 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
1690                         }
1691                 }
1692         }
1693
1694         return error;
1695 }
1696
1697 /*
1698  *  This function will allocate both the DMA descriptor structure, and the
1699  *  buffers it contains.  These are used to contain the descriptors used
1700  *  by the system.
1701 */
1702 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1703                       struct list_head *head, const char *name,
1704                       int nbuf, int ndesc)
1705 {
1706 #define DS2PHYS(_dd, _ds)                                               \
1707         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1708 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1709 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1710
1711         struct ath_desc *ds;
1712         struct ath_buf *bf;
1713         int i, bsize, error;
1714
1715         DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
1716                 __func__, name, nbuf, ndesc);
1717
1718         /* ath_desc must be a multiple of DWORDs */
1719         if ((sizeof(struct ath_desc) % 4) != 0) {
1720                 DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
1721                         __func__);
1722                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1723                 error = -ENOMEM;
1724                 goto fail;
1725         }
1726
1727         dd->dd_name = name;
1728         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1729
1730         /*
1731          * Need additional DMA memory because we can't use
1732          * descriptors that cross the 4K page boundary. Assume
1733          * one skipped descriptor per 4K page.
1734          */
1735         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1736                 u32 ndesc_skipped =
1737                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1738                 u32 dma_len;
1739
1740                 while (ndesc_skipped) {
1741                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1742                         dd->dd_desc_len += dma_len;
1743
1744                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1745                 };
1746         }
1747
1748         /* allocate descriptors */
1749         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1750                               dd->dd_desc_len,
1751                               &dd->dd_desc_paddr);
1752         if (dd->dd_desc == NULL) {
1753                 error = -ENOMEM;
1754                 goto fail;
1755         }
1756         ds = dd->dd_desc;
1757         DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
1758                 __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
1759                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1760
1761         /* allocate buffers */
1762         bsize = sizeof(struct ath_buf) * nbuf;
1763         bf = kmalloc(bsize, GFP_KERNEL);
1764         if (bf == NULL) {
1765                 error = -ENOMEM;
1766                 goto fail2;
1767         }
1768         memset(bf, 0, bsize);
1769         dd->dd_bufptr = bf;
1770
1771         INIT_LIST_HEAD(head);
1772         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1773                 bf->bf_desc = ds;
1774                 bf->bf_daddr = DS2PHYS(dd, ds);
1775
1776                 if (!(sc->sc_ah->ah_caps.hw_caps &
1777                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1778                         /*
1779                          * Skip descriptor addresses which can cause 4KB
1780                          * boundary crossing (addr + length) with a 32 dword
1781                          * descriptor fetch.
1782                          */
1783                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1784                                 ASSERT((caddr_t) bf->bf_desc <
1785                                        ((caddr_t) dd->dd_desc +
1786                                         dd->dd_desc_len));
1787
1788                                 ds += ndesc;
1789                                 bf->bf_desc = ds;
1790                                 bf->bf_daddr = DS2PHYS(dd, ds);
1791                         }
1792                 }
1793                 list_add_tail(&bf->list, head);
1794         }
1795         return 0;
1796 fail2:
1797         pci_free_consistent(sc->pdev,
1798                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1799 fail:
1800         memset(dd, 0, sizeof(*dd));
1801         return error;
1802 #undef ATH_DESC_4KB_BOUND_CHECK
1803 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1804 #undef DS2PHYS
1805 }
1806
1807 void ath_descdma_cleanup(struct ath_softc *sc,
1808                          struct ath_descdma *dd,
1809                          struct list_head *head)
1810 {
1811         pci_free_consistent(sc->pdev,
1812                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1813
1814         INIT_LIST_HEAD(head);
1815         kfree(dd->dd_bufptr);
1816         memset(dd, 0, sizeof(*dd));
1817 }
1818
1819 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1820 {
1821         int qnum;
1822
1823         switch (queue) {
1824         case 0:
1825                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1826                 break;
1827         case 1:
1828                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1829                 break;
1830         case 2:
1831                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1832                 break;
1833         case 3:
1834                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1835                 break;
1836         default:
1837                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1838                 break;
1839         }
1840
1841         return qnum;
1842 }
1843
1844 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1845 {
1846         int qnum;
1847
1848         switch (queue) {
1849         case ATH9K_WME_AC_VO:
1850                 qnum = 0;
1851                 break;
1852         case ATH9K_WME_AC_VI:
1853                 qnum = 1;
1854                 break;
1855         case ATH9K_WME_AC_BE:
1856                 qnum = 2;
1857                 break;
1858         case ATH9K_WME_AC_BK:
1859                 qnum = 3;
1860                 break;
1861         default:
1862                 qnum = -1;
1863                 break;
1864         }
1865
1866         return qnum;
1867 }
1868
1869 /**********************/
1870 /* mac80211 callbacks */
1871 /**********************/
1872
1873 static int ath9k_start(struct ieee80211_hw *hw)
1874 {
1875         struct ath_softc *sc = hw->priv;
1876         struct ieee80211_channel *curchan = hw->conf.channel;
1877         struct ath9k_channel *init_channel;
1878         int error = 0, pos, status;
1879
1880         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
1881                 "initial channel: %d MHz\n", __func__, curchan->center_freq);
1882
1883         /* setup initial channel */
1884
1885         pos = ath_get_channel(sc, curchan);
1886         if (pos == -1) {
1887                 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
1888                 error = -EINVAL;
1889                 goto error;
1890         }
1891
1892         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1893         sc->sc_ah->ah_channels[pos].chanmode =
1894                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1895         init_channel = &sc->sc_ah->ah_channels[pos];
1896
1897         /* Reset SERDES registers */
1898         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1899
1900         /*
1901          * The basic interface to setting the hardware in a good
1902          * state is ``reset''.  On return the hardware is known to
1903          * be powered up and with interrupts disabled.  This must
1904          * be followed by initialization of the appropriate bits
1905          * and then setup of the interrupt mask.
1906          */
1907         spin_lock_bh(&sc->sc_resetlock);
1908         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1909                             sc->tx_chan_width,
1910                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1911                             sc->sc_ht_extprotspacing, false, &status)) {
1912                 DPRINTF(sc, ATH_DBG_FATAL,
1913                         "%s: unable to reset hardware; hal status %u "
1914                         "(freq %u flags 0x%x)\n", __func__, status,
1915                         init_channel->channel, init_channel->channelFlags);
1916                 error = -EIO;
1917                 spin_unlock_bh(&sc->sc_resetlock);
1918                 goto error;
1919         }
1920         spin_unlock_bh(&sc->sc_resetlock);
1921
1922         /*
1923          * This is needed only to setup initial state
1924          * but it's best done after a reset.
1925          */
1926         ath_update_txpow(sc);
1927
1928         /*
1929          * Setup the hardware after reset:
1930          * The receive engine is set going.
1931          * Frame transmit is handled entirely
1932          * in the frame output path; there's nothing to do
1933          * here except setup the interrupt mask.
1934          */
1935         if (ath_startrecv(sc) != 0) {
1936                 DPRINTF(sc, ATH_DBG_FATAL,
1937                         "%s: unable to start recv logic\n", __func__);
1938                 error = -EIO;
1939                 goto error;
1940         }
1941
1942         /* Setup our intr mask. */
1943         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1944                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1945                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1946
1947         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1948                 sc->sc_imask |= ATH9K_INT_GTT;
1949
1950         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1951                 sc->sc_imask |= ATH9K_INT_CST;
1952
1953         /*
1954          * Enable MIB interrupts when there are hardware phy counters.
1955          * Note we only do this (at the moment) for station mode.
1956          */
1957         if (ath9k_hw_phycounters(sc->sc_ah) &&
1958             ((sc->sc_ah->ah_opmode == ATH9K_M_STA) ||
1959              (sc->sc_ah->ah_opmode == ATH9K_M_IBSS)))
1960                 sc->sc_imask |= ATH9K_INT_MIB;
1961         /*
1962          * Some hardware processes the TIM IE and fires an
1963          * interrupt when the TIM bit is set.  For hardware
1964          * that does, if not overridden by configuration,
1965          * enable the TIM interrupt when operating as station.
1966          */
1967         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1968             (sc->sc_ah->ah_opmode == ATH9K_M_STA) &&
1969             !sc->sc_config.swBeaconProcess)
1970                 sc->sc_imask |= ATH9K_INT_TIM;
1971
1972         ath_setcurmode(sc, ath_chan2mode(init_channel));
1973
1974         sc->sc_flags &= ~SC_OP_INVALID;
1975
1976         /* Disable BMISS interrupt when we're not associated */
1977         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1978         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1979
1980         ieee80211_wake_queues(sc->hw);
1981
1982 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1983         error = ath_start_rfkill_poll(sc);
1984 #endif
1985
1986 error:
1987         return error;
1988 }
1989
1990 static int ath9k_tx(struct ieee80211_hw *hw,
1991                     struct sk_buff *skb)
1992 {
1993         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1994         struct ath_softc *sc = hw->priv;
1995         struct ath_tx_control txctl;
1996         int hdrlen, padsize;
1997
1998         memset(&txctl, 0, sizeof(struct ath_tx_control));
1999
2000         /*
2001          * As a temporary workaround, assign seq# here; this will likely need
2002          * to be cleaned up to work better with Beacon transmission and virtual
2003          * BSSes.
2004          */
2005         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2006                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2007                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2008                         sc->seq_no += 0x10;
2009                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2010                 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
2011         }
2012
2013         /* Add the padding after the header if this is not already done */
2014         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2015         if (hdrlen & 3) {
2016                 padsize = hdrlen % 4;
2017                 if (skb_headroom(skb) < padsize)
2018                         return -1;
2019                 skb_push(skb, padsize);
2020                 memmove(skb->data, skb->data + padsize, hdrlen);
2021         }
2022
2023         /* Check if a tx queue is available */
2024
2025         txctl.txq = ath_test_get_txq(sc, skb);
2026         if (!txctl.txq)
2027                 goto exit;
2028
2029         DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
2030                 __func__,
2031                 skb);
2032
2033         if (ath_tx_start(sc, skb, &txctl) != 0) {
2034                 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
2035                 goto exit;
2036         }
2037
2038         return 0;
2039 exit:
2040         dev_kfree_skb_any(skb);
2041         return 0;
2042 }
2043
2044 static void ath9k_stop(struct ieee80211_hw *hw)
2045 {
2046         struct ath_softc *sc = hw->priv;
2047
2048         if (sc->sc_flags & SC_OP_INVALID) {
2049                 DPRINTF(sc, ATH_DBG_ANY, "%s: Device not present\n", __func__);
2050                 return;
2051         }
2052
2053         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Cleaning up\n", __func__);
2054
2055         ieee80211_stop_queues(sc->hw);
2056
2057         /* make sure h/w will not generate any interrupt
2058          * before setting the invalid flag. */
2059         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2060
2061         if (!(sc->sc_flags & SC_OP_INVALID)) {
2062                 ath_draintxq(sc, false);
2063                 ath_stoprecv(sc);
2064                 ath9k_hw_phy_disable(sc->sc_ah);
2065         } else
2066                 sc->sc_rxlink = NULL;
2067
2068 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2069         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2070                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2071 #endif
2072         /* disable HAL and put h/w to sleep */
2073         ath9k_hw_disable(sc->sc_ah);
2074         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2075
2076         sc->sc_flags |= SC_OP_INVALID;
2077
2078         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
2079 }
2080
2081 static int ath9k_add_interface(struct ieee80211_hw *hw,
2082                                struct ieee80211_if_init_conf *conf)
2083 {
2084         struct ath_softc *sc = hw->priv;
2085         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2086         int ic_opmode = 0;
2087
2088         /* Support only vap for now */
2089
2090         if (sc->sc_nvaps)
2091                 return -ENOBUFS;
2092
2093         switch (conf->type) {
2094         case NL80211_IFTYPE_STATION:
2095                 ic_opmode = ATH9K_M_STA;
2096                 break;
2097         case NL80211_IFTYPE_ADHOC:
2098                 ic_opmode = ATH9K_M_IBSS;
2099                 break;
2100         case NL80211_IFTYPE_AP:
2101                 ic_opmode = ATH9K_M_HOSTAP;
2102                 break;
2103         default:
2104                 DPRINTF(sc, ATH_DBG_FATAL,
2105                         "%s: Interface type %d not yet supported\n",
2106                         __func__, conf->type);
2107                 return -EOPNOTSUPP;
2108         }
2109
2110         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
2111                 __func__,
2112                 ic_opmode);
2113
2114         /* Set the VAP opmode */
2115         avp->av_opmode = ic_opmode;
2116         avp->av_bslot = -1;
2117
2118         if (ic_opmode == ATH9K_M_HOSTAP)
2119                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2120
2121         sc->sc_vaps[0] = conf->vif;
2122         sc->sc_nvaps++;
2123
2124         /* Set the device opmode */
2125         sc->sc_ah->ah_opmode = ic_opmode;
2126
2127         if (conf->type == NL80211_IFTYPE_AP) {
2128                 /* TODO: is this a suitable place to start ANI for AP mode? */
2129                 /* Start ANI */
2130                 mod_timer(&sc->sc_ani.timer,
2131                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2132         }
2133
2134         return 0;
2135 }
2136
2137 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2138                                    struct ieee80211_if_init_conf *conf)
2139 {
2140         struct ath_softc *sc = hw->priv;
2141         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2142
2143         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
2144
2145 #ifdef CONFIG_SLOW_ANT_DIV
2146         ath_slow_ant_div_stop(&sc->sc_antdiv);
2147 #endif
2148         /* Stop ANI */
2149         del_timer_sync(&sc->sc_ani.timer);
2150
2151         /* Reclaim beacon resources */
2152         if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
2153             sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
2154                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2155                 ath_beacon_return(sc, avp);
2156         }
2157
2158         sc->sc_flags &= ~SC_OP_BEACONS;
2159
2160         sc->sc_vaps[0] = NULL;
2161         sc->sc_nvaps--;
2162 }
2163
2164 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2165 {
2166         struct ath_softc *sc = hw->priv;
2167         struct ieee80211_conf *conf = &hw->conf;
2168
2169         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2170                 struct ieee80211_channel *curchan = hw->conf.channel;
2171                 int pos;
2172
2173                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
2174                         __func__, curchan->center_freq);
2175
2176                 pos = ath_get_channel(sc, curchan);
2177                 if (pos == -1) {
2178                         DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
2179                         return -EINVAL;
2180                 }
2181
2182                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2183                 sc->sc_ah->ah_channels[pos].chanmode =
2184                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2185                         CHANNEL_G : CHANNEL_A;
2186
2187                 if ((sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) &&
2188                     (conf->ht.enabled)) {
2189                         sc->tx_chan_width = (!!conf->ht.sec_chan_offset) ?
2190                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
2191
2192                         sc->sc_ah->ah_channels[pos].chanmode =
2193                                 ath_get_extchanmode(sc, curchan,
2194                                                     conf->ht.sec_chan_offset,
2195                                                     sc->tx_chan_width);
2196                 }
2197
2198                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2199                         DPRINTF(sc, ATH_DBG_FATAL,
2200                                 "%s: Unable to set channel\n", __func__);
2201                         return -EINVAL;
2202                 }
2203         }
2204
2205         if (changed & IEEE80211_CONF_CHANGE_HT)
2206                 ath_update_chainmask(sc, conf->ht.enabled);
2207
2208         if (changed & IEEE80211_CONF_CHANGE_POWER)
2209                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2210
2211         return 0;
2212 }
2213
2214 static int ath9k_config_interface(struct ieee80211_hw *hw,
2215                                   struct ieee80211_vif *vif,
2216                                   struct ieee80211_if_conf *conf)
2217 {
2218         struct ath_softc *sc = hw->priv;
2219         struct ath_hal *ah = sc->sc_ah;
2220         struct ath_vap *avp = (void *)vif->drv_priv;
2221         u32 rfilt = 0;
2222         int error, i;
2223
2224         /* TODO: Need to decide which hw opmode to use for multi-interface
2225          * cases */
2226         if (vif->type == NL80211_IFTYPE_AP &&
2227             ah->ah_opmode != ATH9K_M_HOSTAP) {
2228                 ah->ah_opmode = ATH9K_M_HOSTAP;
2229                 ath9k_hw_setopmode(ah);
2230                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2231                 /* Request full reset to get hw opmode changed properly */
2232                 sc->sc_flags |= SC_OP_FULL_RESET;
2233         }
2234
2235         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2236             !is_zero_ether_addr(conf->bssid)) {
2237                 switch (vif->type) {
2238                 case NL80211_IFTYPE_STATION:
2239                 case NL80211_IFTYPE_ADHOC:
2240                         /* Set BSSID */
2241                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2242                         sc->sc_curaid = 0;
2243                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2244                                                sc->sc_curaid);
2245
2246                         /* Set aggregation protection mode parameters */
2247                         sc->sc_config.ath_aggr_prot = 0;
2248
2249                         DPRINTF(sc, ATH_DBG_CONFIG,
2250                                 "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
2251                                 __func__, rfilt,
2252                                 sc->sc_curbssid, sc->sc_curaid);
2253
2254                         /* need to reconfigure the beacon */
2255                         sc->sc_flags &= ~SC_OP_BEACONS ;
2256
2257                         break;
2258                 default:
2259                         break;
2260                 }
2261         }
2262
2263         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2264             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2265              (vif->type == NL80211_IFTYPE_AP))) {
2266                 /*
2267                  * Allocate and setup the beacon frame.
2268                  *
2269                  * Stop any previous beacon DMA.  This may be
2270                  * necessary, for example, when an ibss merge
2271                  * causes reconfiguration; we may be called
2272                  * with beacon transmission active.
2273                  */
2274                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2275
2276                 error = ath_beacon_alloc(sc, 0);
2277                 if (error != 0)
2278                         return error;
2279
2280                 ath_beacon_sync(sc, 0);
2281         }
2282
2283         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2284         if ((avp->av_opmode != ATH9K_M_STA)) {
2285                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2286                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2287                                 ath9k_hw_keysetmac(sc->sc_ah,
2288                                                    (u16)i,
2289                                                    sc->sc_curbssid);
2290         }
2291
2292         /* Only legacy IBSS for now */
2293         if (vif->type == NL80211_IFTYPE_ADHOC)
2294                 ath_update_chainmask(sc, 0);
2295
2296         return 0;
2297 }
2298
2299 #define SUPPORTED_FILTERS                       \
2300         (FIF_PROMISC_IN_BSS |                   \
2301         FIF_ALLMULTI |                          \
2302         FIF_CONTROL |                           \
2303         FIF_OTHER_BSS |                         \
2304         FIF_BCN_PRBRESP_PROMISC |               \
2305         FIF_FCSFAIL)
2306
2307 /* FIXME: sc->sc_full_reset ? */
2308 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2309                                    unsigned int changed_flags,
2310                                    unsigned int *total_flags,
2311                                    int mc_count,
2312                                    struct dev_mc_list *mclist)
2313 {
2314         struct ath_softc *sc = hw->priv;
2315         u32 rfilt;
2316
2317         changed_flags &= SUPPORTED_FILTERS;
2318         *total_flags &= SUPPORTED_FILTERS;
2319
2320         sc->rx_filter = *total_flags;
2321         rfilt = ath_calcrxfilter(sc);
2322         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2323
2324         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2325                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2326                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2327         }
2328
2329         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
2330                 __func__, sc->rx_filter);
2331 }
2332
2333 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2334                              struct ieee80211_vif *vif,
2335                              enum sta_notify_cmd cmd,
2336                              struct ieee80211_sta *sta)
2337 {
2338         struct ath_softc *sc = hw->priv;
2339
2340         switch (cmd) {
2341         case STA_NOTIFY_ADD:
2342                 ath_node_attach(sc, sta);
2343                 break;
2344         case STA_NOTIFY_REMOVE:
2345                 ath_node_detach(sc, sta);
2346                 break;
2347         default:
2348                 break;
2349         }
2350 }
2351
2352 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2353                          u16 queue,
2354                          const struct ieee80211_tx_queue_params *params)
2355 {
2356         struct ath_softc *sc = hw->priv;
2357         struct ath9k_tx_queue_info qi;
2358         int ret = 0, qnum;
2359
2360         if (queue >= WME_NUM_AC)
2361                 return 0;
2362
2363         qi.tqi_aifs = params->aifs;
2364         qi.tqi_cwmin = params->cw_min;
2365         qi.tqi_cwmax = params->cw_max;
2366         qi.tqi_burstTime = params->txop;
2367         qnum = ath_get_hal_qnum(queue, sc);
2368
2369         DPRINTF(sc, ATH_DBG_CONFIG,
2370                 "%s: Configure tx [queue/halq] [%d/%d],  "
2371                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2372                 __func__,
2373                 queue,
2374                 qnum,
2375                 params->aifs,
2376                 params->cw_min,
2377                 params->cw_max,
2378                 params->txop);
2379
2380         ret = ath_txq_update(sc, qnum, &qi);
2381         if (ret)
2382                 DPRINTF(sc, ATH_DBG_FATAL,
2383                         "%s: TXQ Update failed\n", __func__);
2384
2385         return ret;
2386 }
2387
2388 static int ath9k_set_key(struct ieee80211_hw *hw,
2389                          enum set_key_cmd cmd,
2390                          const u8 *local_addr,
2391                          const u8 *addr,
2392                          struct ieee80211_key_conf *key)
2393 {
2394         struct ath_softc *sc = hw->priv;
2395         int ret = 0;
2396
2397         DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
2398
2399         switch (cmd) {
2400         case SET_KEY:
2401                 ret = ath_key_config(sc, addr, key);
2402                 if (!ret) {
2403                         set_bit(key->keyidx, sc->sc_keymap);
2404                         key->hw_key_idx = key->keyidx;
2405                         /* push IV and Michael MIC generation to stack */
2406                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2407                         if (key->alg == ALG_TKIP)
2408                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2409                 }
2410                 break;
2411         case DISABLE_KEY:
2412                 ath_key_delete(sc, key);
2413                 clear_bit(key->keyidx, sc->sc_keymap);
2414                 break;
2415         default:
2416                 ret = -EINVAL;
2417         }
2418
2419         return ret;
2420 }
2421
2422 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2423                                    struct ieee80211_vif *vif,
2424                                    struct ieee80211_bss_conf *bss_conf,
2425                                    u32 changed)
2426 {
2427         struct ath_softc *sc = hw->priv;
2428
2429         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2430                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
2431                         __func__,
2432                         bss_conf->use_short_preamble);
2433                 if (bss_conf->use_short_preamble)
2434                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2435                 else
2436                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2437         }
2438
2439         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2440                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
2441                         __func__,
2442                         bss_conf->use_cts_prot);
2443                 if (bss_conf->use_cts_prot &&
2444                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2445                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2446                 else
2447                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2448         }
2449
2450         if (changed & BSS_CHANGED_HT)
2451                 ath9k_ht_conf(sc, bss_conf);
2452
2453         if (changed & BSS_CHANGED_ASSOC) {
2454                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
2455                         __func__,
2456                         bss_conf->assoc);
2457                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2458         }
2459 }
2460
2461 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2462 {
2463         u64 tsf;
2464         struct ath_softc *sc = hw->priv;
2465         struct ath_hal *ah = sc->sc_ah;
2466
2467         tsf = ath9k_hw_gettsf64(ah);
2468
2469         return tsf;
2470 }
2471
2472 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2473 {
2474         struct ath_softc *sc = hw->priv;
2475         struct ath_hal *ah = sc->sc_ah;
2476
2477         ath9k_hw_reset_tsf(ah);
2478 }
2479
2480 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2481                        enum ieee80211_ampdu_mlme_action action,
2482                        struct ieee80211_sta *sta,
2483                        u16 tid, u16 *ssn)
2484 {
2485         struct ath_softc *sc = hw->priv;
2486         int ret = 0;
2487
2488         switch (action) {
2489         case IEEE80211_AMPDU_RX_START:
2490                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2491                         ret = -ENOTSUPP;
2492                 break;
2493         case IEEE80211_AMPDU_RX_STOP:
2494                 break;
2495         case IEEE80211_AMPDU_TX_START:
2496                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2497                 if (ret < 0)
2498                         DPRINTF(sc, ATH_DBG_FATAL,
2499                                 "%s: Unable to start TX aggregation\n",
2500                                 __func__);
2501                 else
2502                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2503                 break;
2504         case IEEE80211_AMPDU_TX_STOP:
2505                 ret = ath_tx_aggr_stop(sc, sta, tid);
2506                 if (ret < 0)
2507                         DPRINTF(sc, ATH_DBG_FATAL,
2508                                 "%s: Unable to stop TX aggregation\n",
2509                                 __func__);
2510
2511                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2512                 break;
2513         case IEEE80211_AMPDU_TX_RESUME:
2514                 ath_tx_aggr_resume(sc, sta, tid);
2515                 break;
2516         default:
2517                 DPRINTF(sc, ATH_DBG_FATAL,
2518                         "%s: Unknown AMPDU action\n", __func__);
2519         }
2520
2521         return ret;
2522 }
2523
2524 static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
2525 {
2526         return -EOPNOTSUPP;
2527 }
2528
2529 static struct ieee80211_ops ath9k_ops = {
2530         .tx                 = ath9k_tx,
2531         .start              = ath9k_start,
2532         .stop               = ath9k_stop,
2533         .add_interface      = ath9k_add_interface,
2534         .remove_interface   = ath9k_remove_interface,
2535         .config             = ath9k_config,
2536         .config_interface   = ath9k_config_interface,
2537         .configure_filter   = ath9k_configure_filter,
2538         .sta_notify         = ath9k_sta_notify,
2539         .conf_tx            = ath9k_conf_tx,
2540         .bss_info_changed   = ath9k_bss_info_changed,
2541         .set_key            = ath9k_set_key,
2542         .get_tsf            = ath9k_get_tsf,
2543         .reset_tsf          = ath9k_reset_tsf,
2544         .ampdu_action       = ath9k_ampdu_action,
2545         .set_frag_threshold = ath9k_no_fragmentation,
2546 };
2547
2548 static struct {
2549         u32 version;
2550         const char * name;
2551 } ath_mac_bb_names[] = {
2552         { AR_SREV_VERSION_5416_PCI,     "5416" },
2553         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2554         { AR_SREV_VERSION_9100,         "9100" },
2555         { AR_SREV_VERSION_9160,         "9160" },
2556         { AR_SREV_VERSION_9280,         "9280" },
2557         { AR_SREV_VERSION_9285,         "9285" }
2558 };
2559
2560 static struct {
2561         u16 version;
2562         const char * name;
2563 } ath_rf_names[] = {
2564         { 0,                            "5133" },
2565         { AR_RAD5133_SREV_MAJOR,        "5133" },
2566         { AR_RAD5122_SREV_MAJOR,        "5122" },
2567         { AR_RAD2133_SREV_MAJOR,        "2133" },
2568         { AR_RAD2122_SREV_MAJOR,        "2122" }
2569 };
2570
2571 /*
2572  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2573  */
2574
2575 static const char *
2576 ath_mac_bb_name(u32 mac_bb_version)
2577 {
2578         int i;
2579
2580         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2581                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2582                         return ath_mac_bb_names[i].name;
2583                 }
2584         }
2585
2586         return "????";
2587 }
2588
2589 /*
2590  * Return the RF name. "????" is returned if the RF is unknown.
2591  */
2592
2593 static const char *
2594 ath_rf_name(u16 rf_version)
2595 {
2596         int i;
2597
2598         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2599                 if (ath_rf_names[i].version == rf_version) {
2600                         return ath_rf_names[i].name;
2601                 }
2602         }
2603
2604         return "????";
2605 }
2606
2607 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2608 {
2609         void __iomem *mem;
2610         struct ath_softc *sc;
2611         struct ieee80211_hw *hw;
2612         u8 csz;
2613         u32 val;
2614         int ret = 0;
2615         struct ath_hal *ah;
2616
2617         if (pci_enable_device(pdev))
2618                 return -EIO;
2619
2620         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2621
2622         if (ret) {
2623                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2624                 goto bad;
2625         }
2626
2627         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2628
2629         if (ret) {
2630                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2631                         "DMA enable faled\n");
2632                 goto bad;
2633         }
2634
2635         /*
2636          * Cache line size is used to size and align various
2637          * structures used to communicate with the hardware.
2638          */
2639         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2640         if (csz == 0) {
2641                 /*
2642                  * Linux 2.4.18 (at least) writes the cache line size
2643                  * register as a 16-bit wide register which is wrong.
2644                  * We must have this setup properly for rx buffer
2645                  * DMA to work so force a reasonable value here if it
2646                  * comes up zero.
2647                  */
2648                 csz = L1_CACHE_BYTES / sizeof(u32);
2649                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2650         }
2651         /*
2652          * The default setting of latency timer yields poor results,
2653          * set it to the value used by other systems. It may be worth
2654          * tweaking this setting more.
2655          */
2656         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2657
2658         pci_set_master(pdev);
2659
2660         /*
2661          * Disable the RETRY_TIMEOUT register (0x41) to keep
2662          * PCI Tx retries from interfering with C3 CPU state.
2663          */
2664         pci_read_config_dword(pdev, 0x40, &val);
2665         if ((val & 0x0000ff00) != 0)
2666                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2667
2668         ret = pci_request_region(pdev, 0, "ath9k");
2669         if (ret) {
2670                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2671                 ret = -ENODEV;
2672                 goto bad;
2673         }
2674
2675         mem = pci_iomap(pdev, 0, 0);
2676         if (!mem) {
2677                 printk(KERN_ERR "PCI memory map error\n") ;
2678                 ret = -EIO;
2679                 goto bad1;
2680         }
2681
2682         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2683         if (hw == NULL) {
2684                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2685                 goto bad2;
2686         }
2687
2688         SET_IEEE80211_DEV(hw, &pdev->dev);
2689         pci_set_drvdata(pdev, hw);
2690
2691         sc = hw->priv;
2692         sc->hw = hw;
2693         sc->pdev = pdev;
2694         sc->mem = mem;
2695
2696         if (ath_attach(id->device, sc) != 0) {
2697                 ret = -ENODEV;
2698                 goto bad3;
2699         }
2700
2701         /* setup interrupt service routine */
2702
2703         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2704                 printk(KERN_ERR "%s: request_irq failed\n",
2705                         wiphy_name(hw->wiphy));
2706                 ret = -EIO;
2707                 goto bad4;
2708         }
2709
2710         ah = sc->sc_ah;
2711         printk(KERN_INFO
2712                "%s: Atheros AR%s MAC/BB Rev:%x "
2713                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2714                wiphy_name(hw->wiphy),
2715                ath_mac_bb_name(ah->ah_macVersion),
2716                ah->ah_macRev,
2717                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2718                ah->ah_phyRev,
2719                (unsigned long)mem, pdev->irq);
2720
2721         return 0;
2722 bad4:
2723         ath_detach(sc);
2724 bad3:
2725         ieee80211_free_hw(hw);
2726 bad2:
2727         pci_iounmap(pdev, mem);
2728 bad1:
2729         pci_release_region(pdev, 0);
2730 bad:
2731         pci_disable_device(pdev);
2732         return ret;
2733 }
2734
2735 static void ath_pci_remove(struct pci_dev *pdev)
2736 {
2737         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2738         struct ath_softc *sc = hw->priv;
2739
2740         ath_detach(sc);
2741         if (pdev->irq)
2742                 free_irq(pdev->irq, sc);
2743         pci_iounmap(pdev, sc->mem);
2744         pci_release_region(pdev, 0);
2745         pci_disable_device(pdev);
2746         ieee80211_free_hw(hw);
2747 }
2748
2749 #ifdef CONFIG_PM
2750
2751 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2752 {
2753         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2754         struct ath_softc *sc = hw->priv;
2755
2756         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2757
2758 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2759         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2760                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2761 #endif
2762
2763         pci_save_state(pdev);
2764         pci_disable_device(pdev);
2765         pci_set_power_state(pdev, 3);
2766
2767         return 0;
2768 }
2769
2770 static int ath_pci_resume(struct pci_dev *pdev)
2771 {
2772         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2773         struct ath_softc *sc = hw->priv;
2774         u32 val;
2775         int err;
2776
2777         err = pci_enable_device(pdev);
2778         if (err)
2779                 return err;
2780         pci_restore_state(pdev);
2781         /*
2782          * Suspend/Resume resets the PCI configuration space, so we have to
2783          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2784          * PCI Tx retries from interfering with C3 CPU state
2785          */
2786         pci_read_config_dword(pdev, 0x40, &val);
2787         if ((val & 0x0000ff00) != 0)
2788                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2789
2790         /* Enable LED */
2791         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2792                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2793         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2794
2795 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2796         /*
2797          * check the h/w rfkill state on resume
2798          * and start the rfkill poll timer
2799          */
2800         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2801                 queue_delayed_work(sc->hw->workqueue,
2802                                    &sc->rf_kill.rfkill_poll, 0);
2803 #endif
2804
2805         return 0;
2806 }
2807
2808 #endif /* CONFIG_PM */
2809
2810 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2811
2812 static struct pci_driver ath_pci_driver = {
2813         .name       = "ath9k",
2814         .id_table   = ath_pci_id_table,
2815         .probe      = ath_pci_probe,
2816         .remove     = ath_pci_remove,
2817 #ifdef CONFIG_PM
2818         .suspend    = ath_pci_suspend,
2819         .resume     = ath_pci_resume,
2820 #endif /* CONFIG_PM */
2821 };
2822
2823 static int __init init_ath_pci(void)
2824 {
2825         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2826
2827         if (pci_register_driver(&ath_pci_driver) < 0) {
2828                 printk(KERN_ERR
2829                         "ath_pci: No devices found, driver not installed.\n");
2830                 pci_unregister_driver(&ath_pci_driver);
2831                 return -ENODEV;
2832         }
2833
2834         return 0;
2835 }
2836 module_init(init_ath_pci);
2837
2838 static void __exit exit_ath_pci(void)
2839 {
2840         pci_unregister_driver(&ath_pci_driver);
2841         printk(KERN_INFO "%s: driver unloaded\n", dev_info);
2842 }
2843 module_exit(exit_ath_pci);