drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  38         { 0 }
  39 };
  40
  41 static void ath_detach(struct ath_softc *sc);
  42
  43 /* return bus cachesize in 4B word units */
  44
  45 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  46 {
  47         u8 u8tmp;
  48
  49         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  50         *csz = (int)u8tmp;
  51
  52         /*
  53          * This check was put in to avoid "unplesant" consequences if
  54          * the bootrom has not fully initialized all PCI devices.
  55          * Sometimes the cache line size register is not set
  56          */
  57
  58         if (*csz == 0)
  59                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  60 }
  61
  62 static void ath_cache_conf_rate(struct ath_softc *sc,
  63                                 struct ieee80211_conf *conf)
  64 {
  65         switch (conf->channel->band) {
  66         case IEEE80211_BAND_2GHZ:
  67                 if (conf_is_ht20(conf))
  68                         sc->cur_rate_table =
  69                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
  70                 else if (conf_is_ht40_minus(conf))
  71                         sc->cur_rate_table =
  72                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
  73                 else if (conf_is_ht40_plus(conf))
  74                         sc->cur_rate_table =
  75                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
  76                 else
  77                         sc->cur_rate_table =
  78                           sc->hw_rate_table[ATH9K_MODE_11G];
  79                 break;
  80         case IEEE80211_BAND_5GHZ:
  81                 if (conf_is_ht20(conf))
  82                         sc->cur_rate_table =
  83                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
  84                 else if (conf_is_ht40_minus(conf))
  85                         sc->cur_rate_table =
  86                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
  87                 else if (conf_is_ht40_plus(conf))
  88                         sc->cur_rate_table =
  89                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
  90                 else
  91                         sc->cur_rate_table =
  92                           sc->hw_rate_table[ATH9K_MODE_11A];
  93                 break;
  94         default:
  95                 BUG_ON(1);
  96                 break;
  97         }
  98 }
  99
 100 static void ath_update_txpow(struct ath_softc *sc)
 101 {
 102         struct ath_hal *ah = sc->sc_ah;
 103         u32 txpow;
 104
 105         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 106                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 107                 /* read back in case value is clamped */
 108                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 109                 sc->sc_curtxpow = txpow;
 110         }
 111 }
 112
 113 static u8 parse_mpdudensity(u8 mpdudensity)
 114 {
 115         /*
 116          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 117          *   0 for no restriction
 118          *   1 for 1/4 us
 119          *   2 for 1/2 us
 120          *   3 for 1 us
 121          *   4 for 2 us
 122          *   5 for 4 us
 123          *   6 for 8 us
 124          *   7 for 16 us
 125          */
 126         switch (mpdudensity) {
 127         case 0:
 128                 return 0;
 129         case 1:
 130         case 2:
 131         case 3:
 132                 /* Our lower layer calculations limit our precision to
 133                    1 microsecond */
 134                 return 1;
 135         case 4:
 136                 return 2;
 137         case 5:
 138                 return 4;
 139         case 6:
 140                 return 8;
 141         case 7:
 142                 return 16;
 143         default:
 144                 return 0;
 145         }
 146 }
 147
 148 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 149 {
 150         struct ath_rate_table *rate_table = NULL;
 151         struct ieee80211_supported_band *sband;
 152         struct ieee80211_rate *rate;
 153         int i, maxrates;
 154
 155         switch (band) {
 156         case IEEE80211_BAND_2GHZ:
 157                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 158                 break;
 159         case IEEE80211_BAND_5GHZ:
 160                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 161                 break;
 162         default:
 163                 break;
 164         }
 165
 166         if (rate_table == NULL)
 167                 return;
 168
 169         sband = &sc->sbands[band];
 170         rate = sc->rates[band];
 171
 172         if (rate_table->rate_cnt > ATH_RATE_MAX)
 173                 maxrates = ATH_RATE_MAX;
 174         else
 175                 maxrates = rate_table->rate_cnt;
 176
 177         for (i = 0; i < maxrates; i++) {
 178                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 179                 rate[i].hw_value = rate_table->info[i].ratecode;
 180                 sband->n_bitrates++;
 181                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 182                         rate[i].bitrate / 10, rate[i].hw_value);
 183         }
 184 }
 185
 186 static int ath_setup_channels(struct ath_softc *sc)
 187 {
 188         struct ath_hal *ah = sc->sc_ah;
 189         int nchan, i, a = 0, b = 0;
 190         u8 regclassids[ATH_REGCLASSIDS_MAX];
 191         u32 nregclass = 0;
 192         struct ieee80211_supported_band *band_2ghz;
 193         struct ieee80211_supported_band *band_5ghz;
 194         struct ieee80211_channel *chan_2ghz;
 195         struct ieee80211_channel *chan_5ghz;
 196         struct ath9k_channel *c;
 197
 198         /* Fill in ah->ah_channels */
 199         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 200                                       regclassids, ATH_REGCLASSIDS_MAX,
 201                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 202                 u32 rd = ah->ah_currentRD;
 203                 DPRINTF(sc, ATH_DBG_FATAL,
 204                         "Unable to collect channel list; "
 205                         "regdomain likely %u country code %u\n",
 206                         rd, CTRY_DEFAULT);
 207                 return -EINVAL;
 208         }
 209
 210         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 211         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 212         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 213         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 214
 215         for (i = 0; i < nchan; i++) {
 216                 c = &ah->ah_channels[i];
 217                 if (IS_CHAN_2GHZ(c)) {
 218                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 219                         chan_2ghz[a].center_freq = c->channel;
 220                         chan_2ghz[a].max_power = c->maxTxPower;
 221
 222                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 223                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 224                         if (c->channelFlags & CHANNEL_PASSIVE)
 225                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 226
 227                         band_2ghz->n_channels = ++a;
 228
 229                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 230                                 "channelFlags: 0x%x\n",
 231                                 c->channel, c->channelFlags);
 232                 } else if (IS_CHAN_5GHZ(c)) {
 233                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 234                         chan_5ghz[b].center_freq = c->channel;
 235                         chan_5ghz[b].max_power = c->maxTxPower;
 236
 237                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 238                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 239                         if (c->channelFlags & CHANNEL_PASSIVE)
 240                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 241
 242                         band_5ghz->n_channels = ++b;
 243
 244                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 245                                 "channelFlags: 0x%x\n",
 246                                 c->channel, c->channelFlags);
 247                 }
 248         }
 249
 250         return 0;
 251 }
 252
 253 /*
 254  * Set/change channels.  If the channel is really being changed, it's done
 255  * by reseting the chip.  To accomplish this we must first cleanup any pending
 256  * DMA, then restart stuff.
 257 */
 258 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 259 {
 260         struct ath_hal *ah = sc->sc_ah;
 261         bool fastcc = true, stopped;
 262         struct ieee80211_hw *hw = sc->hw;
 263         struct ieee80211_channel *channel = hw->conf.channel;
 264         int r;
 265
 266         if (sc->sc_flags & SC_OP_INVALID)
 267                 return -EIO;
 268
 269         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 270             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 271             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 272             (sc->sc_flags & SC_OP_FULL_RESET)) {
 273                 /*
 274                  * This is only performed if the channel settings have
 275                  * actually changed.
 276                  *
 277                  * To switch channels clear any pending DMA operations;
 278                  * wait long enough for the RX fifo to drain, reset the
 279                  * hardware at the new frequency, and then re-enable
 280                  * the relevant bits of the h/w.
 281                  */
 282                 ath9k_hw_set_interrupts(ah, 0);
 283                 ath_draintxq(sc, false);
 284                 stopped = ath_stoprecv(sc);
 285
 286                 /* XXX: do not flush receive queue here. We don't want
 287                  * to flush data frames already in queue because of
 288                  * changing channel. */
 289
 290                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 291                         fastcc = false;
 292
 293                 DPRINTF(sc, ATH_DBG_CONFIG,
 294                         "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 295                         sc->sc_ah->ah_curchan->channel,
 296                         channel->center_freq, sc->tx_chan_width);
 297
 298                 spin_lock_bh(&sc->sc_resetlock);
 299
 300                 r = ath9k_hw_reset(ah, hchan, fastcc);
 301                 if (r) {
 302                         DPRINTF(sc, ATH_DBG_FATAL,
 303                                 "Unable to reset channel (%u Mhz) "
 304                                 "reset status %u\n",
 305                                 channel->center_freq, r);
 306                         spin_unlock_bh(&sc->sc_resetlock);
 307                         return r;
 308                 }
 309                 spin_unlock_bh(&sc->sc_resetlock);
 310
 311                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 312                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 313
 314                 if (ath_startrecv(sc) != 0) {
 315                         DPRINTF(sc, ATH_DBG_FATAL,
 316                                 "Unable to restart recv logic\n");
 317                         return -EIO;
 318                 }
 319
 320                 ath_cache_conf_rate(sc, &hw->conf);
 321                 ath_update_txpow(sc);
 322                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 323         }
 324         return 0;
 325 }
 326
 327 /*
 328  *  This routine performs the periodic noise floor calibration function
 329  *  that is used to adjust and optimize the chip performance.  This
 330  *  takes environmental changes (location, temperature) into account.
 331  *  When the task is complete, it reschedules itself depending on the
 332  *  appropriate interval that was calculated.
 333  */
 334 static void ath_ani_calibrate(unsigned long data)
 335 {
 336         struct ath_softc *sc;
 337         struct ath_hal *ah;
 338         bool longcal = false;
 339         bool shortcal = false;
 340         bool aniflag = false;
 341         unsigned int timestamp = jiffies_to_msecs(jiffies);
 342         u32 cal_interval;
 343
 344         sc = (struct ath_softc *)data;
 345         ah = sc->sc_ah;
 346
 347         /*
 348         * don't calibrate when we're scanning.
 349         * we are most likely not on our home channel.
 350         */
 351         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 352                 return;
 353
 354         /* Long calibration runs independently of short calibration. */
 355         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 356                 longcal = true;
 357                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 358                 sc->sc_ani.sc_longcal_timer = timestamp;
 359         }
 360
 361         /* Short calibration applies only while sc_caldone is false */
 362         if (!sc->sc_ani.sc_caldone) {
 363                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 364                     ATH_SHORT_CALINTERVAL) {
 365                         shortcal = true;
 366                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 367                         sc->sc_ani.sc_shortcal_timer = timestamp;
 368                         sc->sc_ani.sc_resetcal_timer = timestamp;
 369                 }
 370         } else {
 371                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 372                     ATH_RESTART_CALINTERVAL) {
 373                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 374                                                 &sc->sc_ani.sc_caldone);
 375                         if (sc->sc_ani.sc_caldone)
 376                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 377                 }
 378         }
 379
 380         /* Verify whether we must check ANI */
 381         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 382            ATH_ANI_POLLINTERVAL) {
 383                 aniflag = true;
 384                 sc->sc_ani.sc_checkani_timer = timestamp;
 385         }
 386
 387         /* Skip all processing if there's nothing to do. */
 388         if (longcal || shortcal || aniflag) {
 389                 /* Call ANI routine if necessary */
 390                 if (aniflag)
 391                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 392                                              ah->ah_curchan);
 393
 394                 /* Perform calibration if necessary */
 395                 if (longcal || shortcal) {
 396                         bool iscaldone = false;
 397
 398                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 399                                                sc->sc_rx_chainmask, longcal,
 400                                                &iscaldone)) {
 401                                 if (longcal)
 402                                         sc->sc_ani.sc_noise_floor =
 403                                                 ath9k_hw_getchan_noise(ah,
 404                                                                ah->ah_curchan);
 405
 406                                 DPRINTF(sc, ATH_DBG_ANI,
 407                                         "calibrate chan %u/%x nf: %d\n",
 408                                         ah->ah_curchan->channel,
 409                                         ah->ah_curchan->channelFlags,
 410                                         sc->sc_ani.sc_noise_floor);
 411                         } else {
 412                                 DPRINTF(sc, ATH_DBG_ANY,
 413                                         "calibrate chan %u/%x failed\n",
 414                                         ah->ah_curchan->channel,
 415                                         ah->ah_curchan->channelFlags);
 416                         }
 417                         sc->sc_ani.sc_caldone = iscaldone;
 418                 }
 419         }
 420
 421         /*
 422         * Set timer interval based on previous results.
 423         * The interval must be the shortest necessary to satisfy ANI,
 424         * short calibration and long calibration.
 425         */
 426         cal_interval = ATH_LONG_CALINTERVAL;
 427         if (sc->sc_ah->ah_config.enable_ani)
 428                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 429         if (!sc->sc_ani.sc_caldone)
 430                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 431
 432         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 433 }
 434
 435 /*
 436  * Update tx/rx chainmask. For legacy association,
 437  * hard code chainmask to 1x1, for 11n association, use
 438  * the chainmask configuration.
 439  */
 440 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 441 {
 442         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 443         if (is_ht) {
 444                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 445                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 446         } else {
 447                 sc->sc_tx_chainmask = 1;
 448                 sc->sc_rx_chainmask = 1;
 449         }
 450
 451         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 452                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 453 }
 454
 455 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 456 {
 457         struct ath_node *an;
 458
 459         an = (struct ath_node *)sta->drv_priv;
 460
 461         if (sc->sc_flags & SC_OP_TXAGGR)
 462                 ath_tx_node_init(sc, an);
 463
 464         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 465                              sta->ht_cap.ampdu_factor);
 466         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 467 }
 468
 469 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 470 {
 471         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 472
 473         if (sc->sc_flags & SC_OP_TXAGGR)
 474                 ath_tx_node_cleanup(sc, an);
 475 }
 476
 477 static void ath9k_tasklet(unsigned long data)
 478 {
 479         struct ath_softc *sc = (struct ath_softc *)data;
 480         u32 status = sc->sc_intrstatus;
 481
 482         if (status & ATH9K_INT_FATAL) {
 483                 /* need a chip reset */
 484                 ath_reset(sc, false);
 485                 return;
 486         } else {
 487
 488                 if (status &
 489                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 490                         spin_lock_bh(&sc->rx.rxflushlock);
 491                         ath_rx_tasklet(sc, 0);
 492                         spin_unlock_bh(&sc->rx.rxflushlock);
 493                 }
 494                 /* XXX: optimize this */
 495                 if (status & ATH9K_INT_TX)
 496                         ath_tx_tasklet(sc);
 497         }
 498
 499         /* re-enable hardware interrupt */
 500         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 501 }
 502
 503 static irqreturn_t ath_isr(int irq, void *dev)
 504 {
 505         struct ath_softc *sc = dev;
 506         struct ath_hal *ah = sc->sc_ah;
 507         enum ath9k_int status;
 508         bool sched = false;
 509
 510         do {
 511                 if (sc->sc_flags & SC_OP_INVALID) {
 512                         /*
 513                          * The hardware is not ready/present, don't
 514                          * touch anything. Note this can happen early
 515                          * on if the IRQ is shared.
 516                          */
 517                         return IRQ_NONE;
 518                 }
 519                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 520                         return IRQ_NONE;
 521                 }
 522
 523                 /*
 524                  * Figure out the reason(s) for the interrupt.  Note
 525                  * that the hal returns a pseudo-ISR that may include
 526                  * bits we haven't explicitly enabled so we mask the
 527                  * value to insure we only process bits we requested.
 528                  */
 529                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 530
 531                 status &= sc->sc_imask; /* discard unasked-for bits */
 532
 533                 /*
 534                  * If there are no status bits set, then this interrupt was not
 535                  * for me (should have been caught above).
 536                  */
 537                 if (!status)
 538                         return IRQ_NONE;
 539
 540                 sc->sc_intrstatus = status;
 541
 542                 if (status & ATH9K_INT_FATAL) {
 543                         /* need a chip reset */
 544                         sched = true;
 545                 } else if (status & ATH9K_INT_RXORN) {
 546                         /* need a chip reset */
 547                         sched = true;
 548                 } else {
 549                         if (status & ATH9K_INT_SWBA) {
 550                                 /* schedule a tasklet for beacon handling */
 551                                 tasklet_schedule(&sc->bcon_tasklet);
 552                         }
 553                         if (status & ATH9K_INT_RXEOL) {
 554                                 /*
 555                                  * NB: the hardware should re-read the link when
 556                                  *     RXE bit is written, but it doesn't work
 557                                  *     at least on older hardware revs.
 558                                  */
 559                                 sched = true;
 560                         }
 561
 562                         if (status & ATH9K_INT_TXURN)
 563                                 /* bump tx trigger level */
 564                                 ath9k_hw_updatetxtriglevel(ah, true);
 565                         /* XXX: optimize this */
 566                         if (status & ATH9K_INT_RX)
 567                                 sched = true;
 568                         if (status & ATH9K_INT_TX)
 569                                 sched = true;
 570                         if (status & ATH9K_INT_BMISS)
 571                                 sched = true;
 572                         /* carrier sense timeout */
 573                         if (status & ATH9K_INT_CST)
 574                                 sched = true;
 575                         if (status & ATH9K_INT_MIB) {
 576                                 /*
 577                                  * Disable interrupts until we service the MIB
 578                                  * interrupt; otherwise it will continue to
 579                                  * fire.
 580                                  */
 581                                 ath9k_hw_set_interrupts(ah, 0);
 582                                 /*
 583                                  * Let the hal handle the event. We assume
 584                                  * it will clear whatever condition caused
 585                                  * the interrupt.
 586                                  */
 587                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 588                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 589                         }
 590                         if (status & ATH9K_INT_TIM_TIMER) {
 591                                 if (!(ah->ah_caps.hw_caps &
 592                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 593                                         /* Clear RxAbort bit so that we can
 594                                          * receive frames */
 595                                         ath9k_hw_setrxabort(ah, 0);
 596                                         sched = true;
 597                                 }
 598                         }
 599                 }
 600         } while (0);
 601
 602         ath_debug_stat_interrupt(sc, status);
 603
 604         if (sched) {
 605                 /* turn off every interrupt except SWBA */
 606                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 607                 tasklet_schedule(&sc->intr_tq);
 608         }
 609
 610         return IRQ_HANDLED;
 611 }
 612
 613 static int ath_get_channel(struct ath_softc *sc,
 614                            struct ieee80211_channel *chan)
 615 {
 616         int i;
 617
 618         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 619                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 620                         return i;
 621         }
 622
 623         return -1;
 624 }
 625
 626 static u32 ath_get_extchanmode(struct ath_softc *sc,
 627                                struct ieee80211_channel *chan,
 628                                enum nl80211_channel_type channel_type)
 629 {
 630         u32 chanmode = 0;
 631
 632         switch (chan->band) {
 633         case IEEE80211_BAND_2GHZ:
 634                 switch(channel_type) {
 635                 case NL80211_CHAN_NO_HT:
 636                 case NL80211_CHAN_HT20:
 637                         chanmode = CHANNEL_G_HT20;
 638                         break;
 639                 case NL80211_CHAN_HT40PLUS:
 640                         chanmode = CHANNEL_G_HT40PLUS;
 641                         break;
 642                 case NL80211_CHAN_HT40MINUS:
 643                         chanmode = CHANNEL_G_HT40MINUS;
 644                         break;
 645                 }
 646                 break;
 647         case IEEE80211_BAND_5GHZ:
 648                 switch(channel_type) {
 649                 case NL80211_CHAN_NO_HT:
 650                 case NL80211_CHAN_HT20:
 651                         chanmode = CHANNEL_A_HT20;
 652                         break;
 653                 case NL80211_CHAN_HT40PLUS:
 654                         chanmode = CHANNEL_A_HT40PLUS;
 655                         break;
 656                 case NL80211_CHAN_HT40MINUS:
 657                         chanmode = CHANNEL_A_HT40MINUS;
 658                         break;
 659                 }
 660                 break;
 661         default:
 662                 break;
 663         }
 664
 665         return chanmode;
 666 }
 667
 668 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 669                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 670 {
 671         bool status;
 672
 673         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 674                 keyix, hk, mac, false);
 675
 676         return status != false;
 677 }
 678
 679 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 680                            struct ath9k_keyval *hk,
 681                            const u8 *addr)
 682 {
 683         const u8 *key_rxmic;
 684         const u8 *key_txmic;
 685
 686         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 687         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 688
 689         if (addr == NULL) {
 690                 /* Group key installation */
 691                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 692                 return ath_keyset(sc, keyix, hk, addr);
 693         }
 694         if (!sc->sc_splitmic) {
 695                 /*
 696                  * data key goes at first index,
 697                  * the hal handles the MIC keys at index+64.
 698                  */
 699                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 700                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 701                 return ath_keyset(sc, keyix, hk, addr);
 702         }
 703         /*
 704          * TX key goes at first index, RX key at +32.
 705          * The hal handles the MIC keys at index+64.
 706          */
 707         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 708         if (!ath_keyset(sc, keyix, hk, NULL)) {
 709                 /* Txmic entry failed. No need to proceed further */
 710                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 711                         "Setting TX MIC Key Failed\n");
 712                 return 0;
 713         }
 714
 715         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 716         /* XXX delete tx key on failure? */
 717         return ath_keyset(sc, keyix + 32, hk, addr);
 718 }
 719
 720 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 721 {
 722         int i;
 723
 724         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 725                 if (test_bit(i, sc->sc_keymap) ||
 726                     test_bit(i + 64, sc->sc_keymap))
 727                         continue; /* At least one part of TKIP key allocated */
 728                 if (sc->sc_splitmic &&
 729                     (test_bit(i + 32, sc->sc_keymap) ||
 730                      test_bit(i + 64 + 32, sc->sc_keymap)))
 731                         continue; /* At least one part of TKIP key allocated */
 732
 733                 /* Found a free slot for a TKIP key */
 734                 return i;
 735         }
 736         return -1;
 737 }
 738
 739 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 740 {
 741         int i;
 742
 743         /* First, try to find slots that would not be available for TKIP. */
 744         if (sc->sc_splitmic) {
 745                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
 746                         if (!test_bit(i, sc->sc_keymap) &&
 747                             (test_bit(i + 32, sc->sc_keymap) ||
 748                              test_bit(i + 64, sc->sc_keymap) ||
 749                              test_bit(i + 64 + 32, sc->sc_keymap)))
 750                                 return i;
 751                         if (!test_bit(i + 32, sc->sc_keymap) &&
 752                             (test_bit(i, sc->sc_keymap) ||
 753                              test_bit(i + 64, sc->sc_keymap) ||
 754                              test_bit(i + 64 + 32, sc->sc_keymap)))
 755                                 return i + 32;
 756                         if (!test_bit(i + 64, sc->sc_keymap) &&
 757                             (test_bit(i , sc->sc_keymap) ||
 758                              test_bit(i + 32, sc->sc_keymap) ||
 759                              test_bit(i + 64 + 32, sc->sc_keymap)))
 760                                 return i + 64;
 761                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
 762                             (test_bit(i, sc->sc_keymap) ||
 763                              test_bit(i + 32, sc->sc_keymap) ||
 764                              test_bit(i + 64, sc->sc_keymap)))
 765                                 return i + 64 + 32;
 766                 }
 767         } else {
 768                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 769                         if (!test_bit(i, sc->sc_keymap) &&
 770                             test_bit(i + 64, sc->sc_keymap))
 771                                 return i;
 772                         if (test_bit(i, sc->sc_keymap) &&
 773                             !test_bit(i + 64, sc->sc_keymap))
 774                                 return i + 64;
 775                 }
 776         }
 777
 778         /* No partially used TKIP slots, pick any available slot */
 779         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
 780                 /* Do not allow slots that could be needed for TKIP group keys
 781                  * to be used. This limitation could be removed if we know that
 782                  * TKIP will not be used. */
 783                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 784                         continue;
 785                 if (sc->sc_splitmic) {
 786                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 787                                 continue;
 788                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 789                                 continue;
 790                 }
 791
 792                 if (!test_bit(i, sc->sc_keymap))
 793                         return i; /* Found a free slot for a key */
 794         }
 795
 796         /* No free slot found */
 797         return -1;
 798 }
 799
 800 static int ath_key_config(struct ath_softc *sc,
 801                           const u8 *addr,
 802                           struct ieee80211_key_conf *key)
 803 {
 804         struct ath9k_keyval hk;
 805         const u8 *mac = NULL;
 806         int ret = 0;
 807         int idx;
 808
 809         memset(&hk, 0, sizeof(hk));
 810
 811         switch (key->alg) {
 812         case ALG_WEP:
 813                 hk.kv_type = ATH9K_CIPHER_WEP;
 814                 break;
 815         case ALG_TKIP:
 816                 hk.kv_type = ATH9K_CIPHER_TKIP;
 817                 break;
 818         case ALG_CCMP:
 819                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 820                 break;
 821         default:
 822                 return -EINVAL;
 823         }
 824
 825         hk.kv_len = key->keylen;
 826         memcpy(hk.kv_val, key->key, key->keylen);
 827
 828         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 829                 /* For now, use the default keys for broadcast keys. This may
 830                  * need to change with virtual interfaces. */
 831                 idx = key->keyidx;
 832         } else if (key->keyidx) {
 833                 struct ieee80211_vif *vif;
 834
 835                 mac = addr;
 836                 vif = sc->sc_vaps[0];
 837                 if (vif->type != NL80211_IFTYPE_AP) {
 838                         /* Only keyidx 0 should be used with unicast key, but
 839                          * allow this for client mode for now. */
 840                         idx = key->keyidx;
 841                 } else
 842                         return -EIO;
 843         } else {
 844                 mac = addr;
 845                 if (key->alg == ALG_TKIP)
 846                         idx = ath_reserve_key_cache_slot_tkip(sc);
 847                 else
 848                         idx = ath_reserve_key_cache_slot(sc);
 849                 if (idx < 0)
 850                         return -EIO; /* no free key cache entries */
 851         }
 852
 853         if (key->alg == ALG_TKIP)
 854                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 855         else
 856                 ret = ath_keyset(sc, idx, &hk, mac);
 857
 858         if (!ret)
 859                 return -EIO;
 860
 861         set_bit(idx, sc->sc_keymap);
 862         if (key->alg == ALG_TKIP) {
 863                 set_bit(idx + 64, sc->sc_keymap);
 864                 if (sc->sc_splitmic) {
 865                         set_bit(idx + 32, sc->sc_keymap);
 866                         set_bit(idx + 64 + 32, sc->sc_keymap);
 867                 }
 868         }
 869
 870         return idx;
 871 }
 872
 873 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 874 {
 875         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 876         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 877                 return;
 878
 879         clear_bit(key->hw_key_idx, sc->sc_keymap);
 880         if (key->alg != ALG_TKIP)
 881                 return;
 882
 883         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
 884         if (sc->sc_splitmic) {
 885                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
 886                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
 887         }
 888 }
 889
 890 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 891 {
 892 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 893 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 894
 895         ht_info->ht_supported = true;
 896         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 897                        IEEE80211_HT_CAP_SM_PS |
 898                        IEEE80211_HT_CAP_SGI_40 |
 899                        IEEE80211_HT_CAP_DSSSCCK40;
 900
 901         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 902         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 903         /* set up supported mcs set */
 904         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 905         ht_info->mcs.rx_mask[0] = 0xff;
 906         ht_info->mcs.rx_mask[1] = 0xff;
 907         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 908 }
 909
 910 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 911                                  struct ieee80211_vif *vif,
 912                                  struct ieee80211_bss_conf *bss_conf)
 913 {
 914         struct ath_vap *avp = (void *)vif->drv_priv;
 915
 916         if (bss_conf->assoc) {
 917                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 918                         bss_conf->aid, sc->sc_curbssid);
 919
 920                 /* New association, store aid */
 921                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 922                         sc->sc_curaid = bss_conf->aid;
 923                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 924                                                sc->sc_curaid);
 925                 }
 926
 927                 /* Configure the beacon */
 928                 ath_beacon_config(sc, 0);
 929                 sc->sc_flags |= SC_OP_BEACONS;
 930
 931                 /* Reset rssi stats */
 932                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 933                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 934                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 935                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 936
 937                 /* Start ANI */
 938                 mod_timer(&sc->sc_ani.timer,
 939                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 940
 941         } else {
 942                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 943                 sc->sc_curaid = 0;
 944         }
 945 }
 946
 947 /********************************/
 948 /*       LED functions          */
 949 /********************************/
 950
 951 static void ath_led_brightness(struct led_classdev *led_cdev,
 952                                enum led_brightness brightness)
 953 {
 954         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 955         struct ath_softc *sc = led->sc;
 956
 957         switch (brightness) {
 958         case LED_OFF:
 959                 if (led->led_type == ATH_LED_ASSOC ||
 960                     led->led_type == ATH_LED_RADIO)
 961                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 962                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 963                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 964                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 965                 break;
 966         case LED_FULL:
 967                 if (led->led_type == ATH_LED_ASSOC)
 968                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 969                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 970                 break;
 971         default:
 972                 break;
 973         }
 974 }
 975
 976 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 977                             char *trigger)
 978 {
 979         int ret;
 980
 981         led->sc = sc;
 982         led->led_cdev.name = led->name;
 983         led->led_cdev.default_trigger = trigger;
 984         led->led_cdev.brightness_set = ath_led_brightness;
 985
 986         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 987         if (ret)
 988                 DPRINTF(sc, ATH_DBG_FATAL,
 989                         "Failed to register led:%s", led->name);
 990         else
 991                 led->registered = 1;
 992         return ret;
 993 }
 994
 995 static void ath_unregister_led(struct ath_led *led)
 996 {
 997         if (led->registered) {
 998                 led_classdev_unregister(&led->led_cdev);
 999                 led->registered = 0;
1000         }
1001 }
1002
1003 static void ath_deinit_leds(struct ath_softc *sc)
1004 {
1005         ath_unregister_led(&sc->assoc_led);
1006         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1007         ath_unregister_led(&sc->tx_led);
1008         ath_unregister_led(&sc->rx_led);
1009         ath_unregister_led(&sc->radio_led);
1010         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1011 }
1012
1013 static void ath_init_leds(struct ath_softc *sc)
1014 {
1015         char *trigger;
1016         int ret;
1017
1018         /* Configure gpio 1 for output */
1019         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1020                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1021         /* LED off, active low */
1022         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1023
1024         trigger = ieee80211_get_radio_led_name(sc->hw);
1025         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1026                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1027         ret = ath_register_led(sc, &sc->radio_led, trigger);
1028         sc->radio_led.led_type = ATH_LED_RADIO;
1029         if (ret)
1030                 goto fail;
1031
1032         trigger = ieee80211_get_assoc_led_name(sc->hw);
1033         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1034                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1035         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1036         sc->assoc_led.led_type = ATH_LED_ASSOC;
1037         if (ret)
1038                 goto fail;
1039
1040         trigger = ieee80211_get_tx_led_name(sc->hw);
1041         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1042                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1043         ret = ath_register_led(sc, &sc->tx_led, trigger);
1044         sc->tx_led.led_type = ATH_LED_TX;
1045         if (ret)
1046                 goto fail;
1047
1048         trigger = ieee80211_get_rx_led_name(sc->hw);
1049         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1050                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1051         ret = ath_register_led(sc, &sc->rx_led, trigger);
1052         sc->rx_led.led_type = ATH_LED_RX;
1053         if (ret)
1054                 goto fail;
1055
1056         return;
1057
1058 fail:
1059         ath_deinit_leds(sc);
1060 }
1061
1062 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1063
1064 /*******************/
1065 /*      Rfkill     */
1066 /*******************/
1067
1068 static void ath_radio_enable(struct ath_softc *sc)
1069 {
1070         struct ath_hal *ah = sc->sc_ah;
1071         struct ieee80211_channel *channel = sc->hw->conf.channel;
1072         int r;
1073
1074         spin_lock_bh(&sc->sc_resetlock);
1075
1076         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1077
1078         if (r) {
1079                 DPRINTF(sc, ATH_DBG_FATAL,
1080                         "Unable to reset channel %u (%uMhz) ",
1081                         "reset status %u\n",
1082                         channel->center_freq, r);
1083         }
1084         spin_unlock_bh(&sc->sc_resetlock);
1085
1086         ath_update_txpow(sc);
1087         if (ath_startrecv(sc) != 0) {
1088                 DPRINTF(sc, ATH_DBG_FATAL,
1089                         "Unable to restart recv logic\n");
1090                 return;
1091         }
1092
1093         if (sc->sc_flags & SC_OP_BEACONS)
1094                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1095
1096         /* Re-Enable  interrupts */
1097         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1098
1099         /* Enable LED */
1100         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1101                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1102         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1103
1104         ieee80211_wake_queues(sc->hw);
1105 }
1106
1107 static void ath_radio_disable(struct ath_softc *sc)
1108 {
1109         struct ath_hal *ah = sc->sc_ah;
1110         struct ieee80211_channel *channel = sc->hw->conf.channel;
1111         int r;
1112
1113         ieee80211_stop_queues(sc->hw);
1114
1115         /* Disable LED */
1116         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1117         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1118
1119         /* Disable interrupts */
1120         ath9k_hw_set_interrupts(ah, 0);
1121
1122         ath_draintxq(sc, false);        /* clear pending tx frames */
1123         ath_stoprecv(sc);               /* turn off frame recv */
1124         ath_flushrecv(sc);              /* flush recv queue */
1125
1126         spin_lock_bh(&sc->sc_resetlock);
1127         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1128         if (r) {
1129                 DPRINTF(sc, ATH_DBG_FATAL,
1130                         "Unable to reset channel %u (%uMhz) "
1131                         "reset status %u\n",
1132                         channel->center_freq, r);
1133         }
1134         spin_unlock_bh(&sc->sc_resetlock);
1135
1136         ath9k_hw_phy_disable(ah);
1137         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1138 }
1139
1140 static bool ath_is_rfkill_set(struct ath_softc *sc)
1141 {
1142         struct ath_hal *ah = sc->sc_ah;
1143
1144         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1145                                   ah->ah_rfkill_polarity;
1146 }
1147
1148 /* h/w rfkill poll function */
1149 static void ath_rfkill_poll(struct work_struct *work)
1150 {
1151         struct ath_softc *sc = container_of(work, struct ath_softc,
1152                                             rf_kill.rfkill_poll.work);
1153         bool radio_on;
1154
1155         if (sc->sc_flags & SC_OP_INVALID)
1156                 return;
1157
1158         radio_on = !ath_is_rfkill_set(sc);
1159
1160         /*
1161          * enable/disable radio only when there is a
1162          * state change in RF switch
1163          */
1164         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1165                 enum rfkill_state state;
1166
1167                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1168                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1169                                 : RFKILL_STATE_HARD_BLOCKED;
1170                 } else if (radio_on) {
1171                         ath_radio_enable(sc);
1172                         state = RFKILL_STATE_UNBLOCKED;
1173                 } else {
1174                         ath_radio_disable(sc);
1175                         state = RFKILL_STATE_HARD_BLOCKED;
1176                 }
1177
1178                 if (state == RFKILL_STATE_HARD_BLOCKED)
1179                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1180                 else
1181                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1182
1183                 rfkill_force_state(sc->rf_kill.rfkill, state);
1184         }
1185
1186         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1187                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1188 }
1189
1190 /* s/w rfkill handler */
1191 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1192 {
1193         struct ath_softc *sc = data;
1194
1195         switch (state) {
1196         case RFKILL_STATE_SOFT_BLOCKED:
1197                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1198                     SC_OP_RFKILL_SW_BLOCKED)))
1199                         ath_radio_disable(sc);
1200                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1201                 return 0;
1202         case RFKILL_STATE_UNBLOCKED:
1203                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1204                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1205                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1206                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1207                                         "radio as it is disabled by h/w\n");
1208                                 return -EPERM;
1209                         }
1210                         ath_radio_enable(sc);
1211                 }
1212                 return 0;
1213         default:
1214                 return -EINVAL;
1215         }
1216 }
1217
1218 /* Init s/w rfkill */
1219 static int ath_init_sw_rfkill(struct ath_softc *sc)
1220 {
1221         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1222                                              RFKILL_TYPE_WLAN);
1223         if (!sc->rf_kill.rfkill) {
1224                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1225                 return -ENOMEM;
1226         }
1227
1228         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1229                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1230         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1231         sc->rf_kill.rfkill->data = sc;
1232         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1233         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1234         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1235
1236         return 0;
1237 }
1238
1239 /* Deinitialize rfkill */
1240 static void ath_deinit_rfkill(struct ath_softc *sc)
1241 {
1242         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1243                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1244
1245         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1246                 rfkill_unregister(sc->rf_kill.rfkill);
1247                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1248                 sc->rf_kill.rfkill = NULL;
1249         }
1250 }
1251
1252 static int ath_start_rfkill_poll(struct ath_softc *sc)
1253 {
1254         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1255                 queue_delayed_work(sc->hw->workqueue,
1256                                    &sc->rf_kill.rfkill_poll, 0);
1257
1258         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1259                 if (rfkill_register(sc->rf_kill.rfkill)) {
1260                         DPRINTF(sc, ATH_DBG_FATAL,
1261                                 "Unable to register rfkill\n");
1262                         rfkill_free(sc->rf_kill.rfkill);
1263
1264                         /* Deinitialize the device */
1265                         ath_detach(sc);
1266                         if (sc->pdev->irq)
1267                                 free_irq(sc->pdev->irq, sc);
1268                         pci_iounmap(sc->pdev, sc->mem);
1269                         pci_release_region(sc->pdev, 0);
1270                         pci_disable_device(sc->pdev);
1271                         ieee80211_free_hw(sc->hw);
1272                         return -EIO;
1273                 } else {
1274                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1275                 }
1276         }
1277
1278         return 0;
1279 }
1280 #endif /* CONFIG_RFKILL */
1281
1282 static void ath_detach(struct ath_softc *sc)
1283 {
1284         struct ieee80211_hw *hw = sc->hw;
1285         int i = 0;
1286
1287         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1288
1289 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1290         ath_deinit_rfkill(sc);
1291 #endif
1292         ath_deinit_leds(sc);
1293
1294         ieee80211_unregister_hw(hw);
1295         ath_rx_cleanup(sc);
1296         ath_tx_cleanup(sc);
1297
1298         tasklet_kill(&sc->intr_tq);
1299         tasklet_kill(&sc->bcon_tasklet);
1300
1301         if (!(sc->sc_flags & SC_OP_INVALID))
1302                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1303
1304         /* cleanup tx queues */
1305         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1306                 if (ATH_TXQ_SETUP(sc, i))
1307                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1308
1309         ath9k_hw_detach(sc->sc_ah);
1310         ath9k_exit_debug(sc);
1311 }
1312
1313 static int ath_init(u16 devid, struct ath_softc *sc)
1314 {
1315         struct ath_hal *ah = NULL;
1316         int status;
1317         int error = 0, i;
1318         int csz = 0;
1319
1320         /* XXX: hardware will not be ready until ath_open() being called */
1321         sc->sc_flags |= SC_OP_INVALID;
1322
1323         if (ath9k_init_debug(sc) < 0)
1324                 printk(KERN_ERR "Unable to create debugfs files\n");
1325
1326         spin_lock_init(&sc->sc_resetlock);
1327         mutex_init(&sc->mutex);
1328         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1329         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1330                      (unsigned long)sc);
1331
1332         /*
1333          * Cache line size is used to size and align various
1334          * structures used to communicate with the hardware.
1335          */
1336         bus_read_cachesize(sc, &csz);
1337         /* XXX assert csz is non-zero */
1338         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1339
1340         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1341         if (ah == NULL) {
1342                 DPRINTF(sc, ATH_DBG_FATAL,
1343                         "Unable to attach hardware; HAL status %u\n", status);
1344                 error = -ENXIO;
1345                 goto bad;
1346         }
1347         sc->sc_ah = ah;
1348
1349         /* Get the hardware key cache size. */
1350         sc->sc_keymax = ah->ah_caps.keycache_size;
1351         if (sc->sc_keymax > ATH_KEYMAX) {
1352                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1353                         "Warning, using only %u entries in %u key cache\n",
1354                         ATH_KEYMAX, sc->sc_keymax);
1355                 sc->sc_keymax = ATH_KEYMAX;
1356         }
1357
1358         /*
1359          * Reset the key cache since some parts do not
1360          * reset the contents on initial power up.
1361          */
1362         for (i = 0; i < sc->sc_keymax; i++)
1363                 ath9k_hw_keyreset(ah, (u16) i);
1364
1365         /* Collect the channel list using the default country code */
1366
1367         error = ath_setup_channels(sc);
1368         if (error)
1369                 goto bad;
1370
1371         /* default to MONITOR mode */
1372         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1373
1374
1375         /* Setup rate tables */
1376
1377         ath_rate_attach(sc);
1378         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1379         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1380
1381         /*
1382          * Allocate hardware transmit queues: one queue for
1383          * beacon frames and one data queue for each QoS
1384          * priority.  Note that the hal handles reseting
1385          * these queues at the needed time.
1386          */
1387         sc->beacon.beaconq = ath_beaconq_setup(ah);
1388         if (sc->beacon.beaconq == -1) {
1389                 DPRINTF(sc, ATH_DBG_FATAL,
1390                         "Unable to setup a beacon xmit queue\n");
1391                 error = -EIO;
1392                 goto bad2;
1393         }
1394         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1395         if (sc->beacon.cabq == NULL) {
1396                 DPRINTF(sc, ATH_DBG_FATAL,
1397                         "Unable to setup CAB xmit queue\n");
1398                 error = -EIO;
1399                 goto bad2;
1400         }
1401
1402         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1403         ath_cabq_update(sc);
1404
1405         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1406                 sc->tx.hwq_map[i] = -1;
1407
1408         /* Setup data queues */
1409         /* NB: ensure BK queue is the lowest priority h/w queue */
1410         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1411                 DPRINTF(sc, ATH_DBG_FATAL,
1412                         "Unable to setup xmit queue for BK traffic\n");
1413                 error = -EIO;
1414                 goto bad2;
1415         }
1416
1417         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1418                 DPRINTF(sc, ATH_DBG_FATAL,
1419                         "Unable to setup xmit queue for BE traffic\n");
1420                 error = -EIO;
1421                 goto bad2;
1422         }
1423         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1424                 DPRINTF(sc, ATH_DBG_FATAL,
1425                         "Unable to setup xmit queue for VI traffic\n");
1426                 error = -EIO;
1427                 goto bad2;
1428         }
1429         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1430                 DPRINTF(sc, ATH_DBG_FATAL,
1431                         "Unable to setup xmit queue for VO traffic\n");
1432                 error = -EIO;
1433                 goto bad2;
1434         }
1435
1436         /* Initializes the noise floor to a reasonable default value.
1437          * Later on this will be updated during ANI processing. */
1438
1439         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1440         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1441
1442         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1443                                    ATH9K_CIPHER_TKIP, NULL)) {
1444                 /*
1445                  * Whether we should enable h/w TKIP MIC.
1446                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1447                  * report WMM capable, so it's always safe to turn on
1448                  * TKIP MIC in this case.
1449                  */
1450                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1451                                        0, 1, NULL);
1452         }
1453
1454         /*
1455          * Check whether the separate key cache entries
1456          * are required to handle both tx+rx MIC keys.
1457          * With split mic keys the number of stations is limited
1458          * to 27 otherwise 59.
1459          */
1460         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1461                                    ATH9K_CIPHER_TKIP, NULL)
1462             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1463                                       ATH9K_CIPHER_MIC, NULL)
1464             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1465                                       0, NULL))
1466                 sc->sc_splitmic = 1;
1467
1468         /* turn on mcast key search if possible */
1469         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1470                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1471                                              1, NULL);
1472
1473         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1474         sc->sc_config.txpowlimit_override = 0;
1475
1476         /* 11n Capabilities */
1477         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1478                 sc->sc_flags |= SC_OP_TXAGGR;
1479                 sc->sc_flags |= SC_OP_RXAGGR;
1480         }
1481
1482         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1483         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1484
1485         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1486         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1487
1488         ath9k_hw_getmac(ah, sc->sc_myaddr);
1489         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1490                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1491                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1492                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1493         }
1494
1495         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1496
1497         /* initialize beacon slots */
1498         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1499                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1500
1501         /* save MISC configurations */
1502         sc->sc_config.swBeaconProcess = 1;
1503
1504         /* setup channels and rates */
1505
1506         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1507                 sc->channels[IEEE80211_BAND_2GHZ];
1508         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1509                 sc->rates[IEEE80211_BAND_2GHZ];
1510         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1511
1512         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1513                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1514                         sc->channels[IEEE80211_BAND_5GHZ];
1515                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1516                         sc->rates[IEEE80211_BAND_5GHZ];
1517                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1518         }
1519
1520         return 0;
1521 bad2:
1522         /* cleanup tx queues */
1523         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1524                 if (ATH_TXQ_SETUP(sc, i))
1525                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1526 bad:
1527         if (ah)
1528                 ath9k_hw_detach(ah);
1529
1530         return error;
1531 }
1532
1533 static int ath_attach(u16 devid, struct ath_softc *sc)
1534 {
1535         struct ieee80211_hw *hw = sc->hw;
1536         int error = 0;
1537
1538         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1539
1540         error = ath_init(devid, sc);
1541         if (error != 0)
1542                 return error;
1543
1544         /* get mac address from hardware and set in mac80211 */
1545
1546         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1547
1548         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1549                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1550                 IEEE80211_HW_SIGNAL_DBM |
1551                 IEEE80211_HW_AMPDU_AGGREGATION;
1552
1553         hw->wiphy->interface_modes =
1554                 BIT(NL80211_IFTYPE_AP) |
1555                 BIT(NL80211_IFTYPE_STATION) |
1556                 BIT(NL80211_IFTYPE_ADHOC);
1557
1558         hw->queues = 4;
1559         hw->max_rates = 4;
1560         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1561         hw->sta_data_size = sizeof(struct ath_node);
1562         hw->vif_data_size = sizeof(struct ath_vap);
1563
1564         hw->rate_control_algorithm = "ath9k_rate_control";
1565
1566         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1567                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1568                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1569                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1570         }
1571
1572         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1573         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1574                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1575                         &sc->sbands[IEEE80211_BAND_5GHZ];
1576
1577         /* initialize tx/rx engine */
1578         error = ath_tx_init(sc, ATH_TXBUF);
1579         if (error != 0)
1580                 goto detach;
1581
1582         error = ath_rx_init(sc, ATH_RXBUF);
1583         if (error != 0)
1584                 goto detach;
1585
1586 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1587         /* Initialze h/w Rfkill */
1588         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1589                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1590
1591         /* Initialize s/w rfkill */
1592         if (ath_init_sw_rfkill(sc))
1593                 goto detach;
1594 #endif
1595
1596         error = ieee80211_register_hw(hw);
1597
1598         /* Initialize LED control */
1599         ath_init_leds(sc);
1600
1601         return 0;
1602 detach:
1603         ath_detach(sc);
1604         return error;
1605 }
1606
1607 int ath_reset(struct ath_softc *sc, bool retry_tx)
1608 {
1609         struct ath_hal *ah = sc->sc_ah;
1610         struct ieee80211_hw *hw = sc->hw;
1611         int r;
1612
1613         ath9k_hw_set_interrupts(ah, 0);
1614         ath_draintxq(sc, retry_tx);
1615         ath_stoprecv(sc);
1616         ath_flushrecv(sc);
1617
1618         spin_lock_bh(&sc->sc_resetlock);
1619         r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1620         if (r)
1621                 DPRINTF(sc, ATH_DBG_FATAL,
1622                         "Unable to reset hardware; reset status %u\n", r);
1623         spin_unlock_bh(&sc->sc_resetlock);
1624
1625         if (ath_startrecv(sc) != 0)
1626                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1627
1628         /*
1629          * We may be doing a reset in response to a request
1630          * that changes the channel so update any state that
1631          * might change as a result.
1632          */
1633         ath_cache_conf_rate(sc, &hw->conf);
1634
1635         ath_update_txpow(sc);
1636
1637         if (sc->sc_flags & SC_OP_BEACONS)
1638                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1639
1640         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1641
1642         if (retry_tx) {
1643                 int i;
1644                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1645                         if (ATH_TXQ_SETUP(sc, i)) {
1646                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1647                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1648                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1649                         }
1650                 }
1651         }
1652
1653         return r;
1654 }
1655
1656 /*
1657  *  This function will allocate both the DMA descriptor structure, and the
1658  *  buffers it contains.  These are used to contain the descriptors used
1659  *  by the system.
1660 */
1661 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1662                       struct list_head *head, const char *name,
1663                       int nbuf, int ndesc)
1664 {
1665 #define DS2PHYS(_dd, _ds)                                               \
1666         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1667 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1668 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1669
1670         struct ath_desc *ds;
1671         struct ath_buf *bf;
1672         int i, bsize, error;
1673
1674         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1675                 name, nbuf, ndesc);
1676
1677         /* ath_desc must be a multiple of DWORDs */
1678         if ((sizeof(struct ath_desc) % 4) != 0) {
1679                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1680                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1681                 error = -ENOMEM;
1682                 goto fail;
1683         }
1684
1685         dd->dd_name = name;
1686         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1687
1688         /*
1689          * Need additional DMA memory because we can't use
1690          * descriptors that cross the 4K page boundary. Assume
1691          * one skipped descriptor per 4K page.
1692          */
1693         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1694                 u32 ndesc_skipped =
1695                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1696                 u32 dma_len;
1697
1698                 while (ndesc_skipped) {
1699                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1700                         dd->dd_desc_len += dma_len;
1701
1702                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1703                 };
1704         }
1705
1706         /* allocate descriptors */
1707         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1708                               dd->dd_desc_len,
1709                               &dd->dd_desc_paddr);
1710         if (dd->dd_desc == NULL) {
1711                 error = -ENOMEM;
1712                 goto fail;
1713         }
1714         ds = dd->dd_desc;
1715         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1716                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1717                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1718
1719         /* allocate buffers */
1720         bsize = sizeof(struct ath_buf) * nbuf;
1721         bf = kmalloc(bsize, GFP_KERNEL);
1722         if (bf == NULL) {
1723                 error = -ENOMEM;
1724                 goto fail2;
1725         }
1726         memset(bf, 0, bsize);
1727         dd->dd_bufptr = bf;
1728
1729         INIT_LIST_HEAD(head);
1730         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1731                 bf->bf_desc = ds;
1732                 bf->bf_daddr = DS2PHYS(dd, ds);
1733
1734                 if (!(sc->sc_ah->ah_caps.hw_caps &
1735                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1736                         /*
1737                          * Skip descriptor addresses which can cause 4KB
1738                          * boundary crossing (addr + length) with a 32 dword
1739                          * descriptor fetch.
1740                          */
1741                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1742                                 ASSERT((caddr_t) bf->bf_desc <
1743                                        ((caddr_t) dd->dd_desc +
1744                                         dd->dd_desc_len));
1745
1746                                 ds += ndesc;
1747                                 bf->bf_desc = ds;
1748                                 bf->bf_daddr = DS2PHYS(dd, ds);
1749                         }
1750                 }
1751                 list_add_tail(&bf->list, head);
1752         }
1753         return 0;
1754 fail2:
1755         pci_free_consistent(sc->pdev,
1756                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1757 fail:
1758         memset(dd, 0, sizeof(*dd));
1759         return error;
1760 #undef ATH_DESC_4KB_BOUND_CHECK
1761 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1762 #undef DS2PHYS
1763 }
1764
1765 void ath_descdma_cleanup(struct ath_softc *sc,
1766                          struct ath_descdma *dd,
1767                          struct list_head *head)
1768 {
1769         pci_free_consistent(sc->pdev,
1770                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1771
1772         INIT_LIST_HEAD(head);
1773         kfree(dd->dd_bufptr);
1774         memset(dd, 0, sizeof(*dd));
1775 }
1776
1777 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1778 {
1779         int qnum;
1780
1781         switch (queue) {
1782         case 0:
1783                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1784                 break;
1785         case 1:
1786                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1787                 break;
1788         case 2:
1789                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1790                 break;
1791         case 3:
1792                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1793                 break;
1794         default:
1795                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1796                 break;
1797         }
1798
1799         return qnum;
1800 }
1801
1802 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1803 {
1804         int qnum;
1805
1806         switch (queue) {
1807         case ATH9K_WME_AC_VO:
1808                 qnum = 0;
1809                 break;
1810         case ATH9K_WME_AC_VI:
1811                 qnum = 1;
1812                 break;
1813         case ATH9K_WME_AC_BE:
1814                 qnum = 2;
1815                 break;
1816         case ATH9K_WME_AC_BK:
1817                 qnum = 3;
1818                 break;
1819         default:
1820                 qnum = -1;
1821                 break;
1822         }
1823
1824         return qnum;
1825 }
1826
1827 /**********************/
1828 /* mac80211 callbacks */
1829 /**********************/
1830
1831 static int ath9k_start(struct ieee80211_hw *hw)
1832 {
1833         struct ath_softc *sc = hw->priv;
1834         struct ieee80211_channel *curchan = hw->conf.channel;
1835         struct ath9k_channel *init_channel;
1836         int r, pos;
1837
1838         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1839                 "initial channel: %d MHz\n", curchan->center_freq);
1840
1841         /* setup initial channel */
1842
1843         pos = ath_get_channel(sc, curchan);
1844         if (pos == -1) {
1845                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1846                 return -EINVAL;
1847         }
1848
1849         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1850         sc->sc_ah->ah_channels[pos].chanmode =
1851                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1852         init_channel = &sc->sc_ah->ah_channels[pos];
1853
1854         /* Reset SERDES registers */
1855         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1856
1857         /*
1858          * The basic interface to setting the hardware in a good
1859          * state is ``reset''.  On return the hardware is known to
1860          * be powered up and with interrupts disabled.  This must
1861          * be followed by initialization of the appropriate bits
1862          * and then setup of the interrupt mask.
1863          */
1864         spin_lock_bh(&sc->sc_resetlock);
1865         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1866         if (r) {
1867                 DPRINTF(sc, ATH_DBG_FATAL,
1868                         "Unable to reset hardware; reset status %u "
1869                         "(freq %u MHz)\n", r,
1870                         curchan->center_freq);
1871                 spin_unlock_bh(&sc->sc_resetlock);
1872                 return r;
1873         }
1874         spin_unlock_bh(&sc->sc_resetlock);
1875
1876         /*
1877          * This is needed only to setup initial state
1878          * but it's best done after a reset.
1879          */
1880         ath_update_txpow(sc);
1881
1882         /*
1883          * Setup the hardware after reset:
1884          * The receive engine is set going.
1885          * Frame transmit is handled entirely
1886          * in the frame output path; there's nothing to do
1887          * here except setup the interrupt mask.
1888          */
1889         if (ath_startrecv(sc) != 0) {
1890                 DPRINTF(sc, ATH_DBG_FATAL,
1891                         "Unable to start recv logic\n");
1892                 return -EIO;
1893         }
1894
1895         /* Setup our intr mask. */
1896         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1897                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1898                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1899
1900         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1901                 sc->sc_imask |= ATH9K_INT_GTT;
1902
1903         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1904                 sc->sc_imask |= ATH9K_INT_CST;
1905
1906         /*
1907          * Enable MIB interrupts when there are hardware phy counters.
1908          * Note we only do this (at the moment) for station mode.
1909          */
1910         if (ath9k_hw_phycounters(sc->sc_ah) &&
1911             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1912              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1913                 sc->sc_imask |= ATH9K_INT_MIB;
1914         /*
1915          * Some hardware processes the TIM IE and fires an
1916          * interrupt when the TIM bit is set.  For hardware
1917          * that does, if not overridden by configuration,
1918          * enable the TIM interrupt when operating as station.
1919          */
1920         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1921             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1922             !sc->sc_config.swBeaconProcess)
1923                 sc->sc_imask |= ATH9K_INT_TIM;
1924
1925         ath_cache_conf_rate(sc, &hw->conf);
1926
1927         sc->sc_flags &= ~SC_OP_INVALID;
1928
1929         /* Disable BMISS interrupt when we're not associated */
1930         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1931         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1932
1933         ieee80211_wake_queues(sc->hw);
1934
1935 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1936         r = ath_start_rfkill_poll(sc);
1937 #endif
1938         return r;
1939 }
1940
1941 static int ath9k_tx(struct ieee80211_hw *hw,
1942                     struct sk_buff *skb)
1943 {
1944         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1945         struct ath_softc *sc = hw->priv;
1946         struct ath_tx_control txctl;
1947         int hdrlen, padsize;
1948
1949         memset(&txctl, 0, sizeof(struct ath_tx_control));
1950
1951         /*
1952          * As a temporary workaround, assign seq# here; this will likely need
1953          * to be cleaned up to work better with Beacon transmission and virtual
1954          * BSSes.
1955          */
1956         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1957                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1958                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1959                         sc->tx.seq_no += 0x10;
1960                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1961                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1962         }
1963
1964         /* Add the padding after the header if this is not already done */
1965         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1966         if (hdrlen & 3) {
1967                 padsize = hdrlen % 4;
1968                 if (skb_headroom(skb) < padsize)
1969                         return -1;
1970                 skb_push(skb, padsize);
1971                 memmove(skb->data, skb->data + padsize, hdrlen);
1972         }
1973
1974         /* Check if a tx queue is available */
1975
1976         txctl.txq = ath_test_get_txq(sc, skb);
1977         if (!txctl.txq)
1978                 goto exit;
1979
1980         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1981
1982         if (ath_tx_start(sc, skb, &txctl) != 0) {
1983                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
1984                 goto exit;
1985         }
1986
1987         return 0;
1988 exit:
1989         dev_kfree_skb_any(skb);
1990         return 0;
1991 }
1992
1993 static void ath9k_stop(struct ieee80211_hw *hw)
1994 {
1995         struct ath_softc *sc = hw->priv;
1996
1997         if (sc->sc_flags & SC_OP_INVALID) {
1998                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
1999                 return;
2000         }
2001
2002         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2003
2004         ieee80211_stop_queues(sc->hw);
2005
2006         /* make sure h/w will not generate any interrupt
2007          * before setting the invalid flag. */
2008         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2009
2010         if (!(sc->sc_flags & SC_OP_INVALID)) {
2011                 ath_draintxq(sc, false);
2012                 ath_stoprecv(sc);
2013                 ath9k_hw_phy_disable(sc->sc_ah);
2014         } else
2015                 sc->rx.rxlink = NULL;
2016
2017 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2018         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2019                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2020 #endif
2021         /* disable HAL and put h/w to sleep */
2022         ath9k_hw_disable(sc->sc_ah);
2023         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2024
2025         sc->sc_flags |= SC_OP_INVALID;
2026
2027         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2028 }
2029
2030 static int ath9k_add_interface(struct ieee80211_hw *hw,
2031                                struct ieee80211_if_init_conf *conf)
2032 {
2033         struct ath_softc *sc = hw->priv;
2034         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2035         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2036
2037         /* Support only vap for now */
2038
2039         if (sc->sc_nvaps)
2040                 return -ENOBUFS;
2041
2042         switch (conf->type) {
2043         case NL80211_IFTYPE_STATION:
2044                 ic_opmode = NL80211_IFTYPE_STATION;
2045                 break;
2046         case NL80211_IFTYPE_ADHOC:
2047                 ic_opmode = NL80211_IFTYPE_ADHOC;
2048                 break;
2049         case NL80211_IFTYPE_AP:
2050                 ic_opmode = NL80211_IFTYPE_AP;
2051                 break;
2052         default:
2053                 DPRINTF(sc, ATH_DBG_FATAL,
2054                         "Interface type %d not yet supported\n", conf->type);
2055                 return -EOPNOTSUPP;
2056         }
2057
2058         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2059
2060         /* Set the VAP opmode */
2061         avp->av_opmode = ic_opmode;
2062         avp->av_bslot = -1;
2063
2064         if (ic_opmode == NL80211_IFTYPE_AP)
2065                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2066
2067         sc->sc_vaps[0] = conf->vif;
2068         sc->sc_nvaps++;
2069
2070         /* Set the device opmode */
2071         sc->sc_ah->ah_opmode = ic_opmode;
2072
2073         if (conf->type == NL80211_IFTYPE_AP) {
2074                 /* TODO: is this a suitable place to start ANI for AP mode? */
2075                 /* Start ANI */
2076                 mod_timer(&sc->sc_ani.timer,
2077                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2078         }
2079
2080         return 0;
2081 }
2082
2083 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2084                                    struct ieee80211_if_init_conf *conf)
2085 {
2086         struct ath_softc *sc = hw->priv;
2087         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2088
2089         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2090
2091         /* Stop ANI */
2092         del_timer_sync(&sc->sc_ani.timer);
2093
2094         /* Reclaim beacon resources */
2095         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2096             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2097                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2098                 ath_beacon_return(sc, avp);
2099         }
2100
2101         sc->sc_flags &= ~SC_OP_BEACONS;
2102
2103         sc->sc_vaps[0] = NULL;
2104         sc->sc_nvaps--;
2105 }
2106
2107 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2108 {
2109         struct ath_softc *sc = hw->priv;
2110         struct ieee80211_conf *conf = &hw->conf;
2111
2112         mutex_lock(&sc->mutex);
2113         if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2114                        IEEE80211_CONF_CHANGE_HT)) {
2115                 struct ieee80211_channel *curchan = hw->conf.channel;
2116                 int pos;
2117
2118                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2119                         curchan->center_freq);
2120
2121                 pos = ath_get_channel(sc, curchan);
2122                 if (pos == -1) {
2123                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2124                                 curchan->center_freq);
2125                         mutex_unlock(&sc->mutex);
2126                         return -EINVAL;
2127                 }
2128
2129                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2130                 sc->sc_ah->ah_channels[pos].chanmode =
2131                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2132                         CHANNEL_G : CHANNEL_A;
2133
2134                 if (conf->ht.enabled) {
2135                         if (conf->ht.channel_type == NL80211_CHAN_HT40PLUS ||
2136                             conf->ht.channel_type == NL80211_CHAN_HT40MINUS)
2137                                 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2138
2139                         sc->sc_ah->ah_channels[pos].chanmode =
2140                                 ath_get_extchanmode(sc, curchan,
2141                                                     conf->ht.channel_type);
2142                 }
2143
2144                 ath_update_chainmask(sc, conf->ht.enabled);
2145
2146                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2147                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2148                         mutex_unlock(&sc->mutex);
2149                         return -EINVAL;
2150                 }
2151         }
2152
2153         if (changed & IEEE80211_CONF_CHANGE_POWER)
2154                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2155
2156         mutex_unlock(&sc->mutex);
2157         return 0;
2158 }
2159
2160 static int ath9k_config_interface(struct ieee80211_hw *hw,
2161                                   struct ieee80211_vif *vif,
2162                                   struct ieee80211_if_conf *conf)
2163 {
2164         struct ath_softc *sc = hw->priv;
2165         struct ath_hal *ah = sc->sc_ah;
2166         struct ath_vap *avp = (void *)vif->drv_priv;
2167         u32 rfilt = 0;
2168         int error, i;
2169
2170         /* TODO: Need to decide which hw opmode to use for multi-interface
2171          * cases */
2172         if (vif->type == NL80211_IFTYPE_AP &&
2173             ah->ah_opmode != NL80211_IFTYPE_AP) {
2174                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2175                 ath9k_hw_setopmode(ah);
2176                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2177                 /* Request full reset to get hw opmode changed properly */
2178                 sc->sc_flags |= SC_OP_FULL_RESET;
2179         }
2180
2181         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2182             !is_zero_ether_addr(conf->bssid)) {
2183                 switch (vif->type) {
2184                 case NL80211_IFTYPE_STATION:
2185                 case NL80211_IFTYPE_ADHOC:
2186                         /* Set BSSID */
2187                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2188                         sc->sc_curaid = 0;
2189                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2190                                                sc->sc_curaid);
2191
2192                         /* Set aggregation protection mode parameters */
2193                         sc->sc_config.ath_aggr_prot = 0;
2194
2195                         DPRINTF(sc, ATH_DBG_CONFIG,
2196                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2197                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2198
2199                         /* need to reconfigure the beacon */
2200                         sc->sc_flags &= ~SC_OP_BEACONS ;
2201
2202                         break;
2203                 default:
2204                         break;
2205                 }
2206         }
2207
2208         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2209             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2210              (vif->type == NL80211_IFTYPE_AP))) {
2211                 /*
2212                  * Allocate and setup the beacon frame.
2213                  *
2214                  * Stop any previous beacon DMA.  This may be
2215                  * necessary, for example, when an ibss merge
2216                  * causes reconfiguration; we may be called
2217                  * with beacon transmission active.
2218                  */
2219                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2220
2221                 error = ath_beacon_alloc(sc, 0);
2222                 if (error != 0)
2223                         return error;
2224
2225                 ath_beacon_sync(sc, 0);
2226         }
2227
2228         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2229         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2230                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2231                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2232                                 ath9k_hw_keysetmac(sc->sc_ah,
2233                                                    (u16)i,
2234                                                    sc->sc_curbssid);
2235         }
2236
2237         /* Only legacy IBSS for now */
2238         if (vif->type == NL80211_IFTYPE_ADHOC)
2239                 ath_update_chainmask(sc, 0);
2240
2241         return 0;
2242 }
2243
2244 #define SUPPORTED_FILTERS                       \
2245         (FIF_PROMISC_IN_BSS |                   \
2246         FIF_ALLMULTI |                          \
2247         FIF_CONTROL |                           \
2248         FIF_OTHER_BSS |                         \
2249         FIF_BCN_PRBRESP_PROMISC |               \
2250         FIF_FCSFAIL)
2251
2252 /* FIXME: sc->sc_full_reset ? */
2253 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2254                                    unsigned int changed_flags,
2255                                    unsigned int *total_flags,
2256                                    int mc_count,
2257                                    struct dev_mc_list *mclist)
2258 {
2259         struct ath_softc *sc = hw->priv;
2260         u32 rfilt;
2261
2262         changed_flags &= SUPPORTED_FILTERS;
2263         *total_flags &= SUPPORTED_FILTERS;
2264
2265         sc->rx.rxfilter = *total_flags;
2266         rfilt = ath_calcrxfilter(sc);
2267         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2268
2269         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2270                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2271                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2272         }
2273
2274         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2275 }
2276
2277 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2278                              struct ieee80211_vif *vif,
2279                              enum sta_notify_cmd cmd,
2280                              struct ieee80211_sta *sta)
2281 {
2282         struct ath_softc *sc = hw->priv;
2283
2284         switch (cmd) {
2285         case STA_NOTIFY_ADD:
2286                 ath_node_attach(sc, sta);
2287                 break;
2288         case STA_NOTIFY_REMOVE:
2289                 ath_node_detach(sc, sta);
2290                 break;
2291         default:
2292                 break;
2293         }
2294 }
2295
2296 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2297                          u16 queue,
2298                          const struct ieee80211_tx_queue_params *params)
2299 {
2300         struct ath_softc *sc = hw->priv;
2301         struct ath9k_tx_queue_info qi;
2302         int ret = 0, qnum;
2303
2304         if (queue >= WME_NUM_AC)
2305                 return 0;
2306
2307         qi.tqi_aifs = params->aifs;
2308         qi.tqi_cwmin = params->cw_min;
2309         qi.tqi_cwmax = params->cw_max;
2310         qi.tqi_burstTime = params->txop;
2311         qnum = ath_get_hal_qnum(queue, sc);
2312
2313         DPRINTF(sc, ATH_DBG_CONFIG,
2314                 "Configure tx [queue/halq] [%d/%d],  "
2315                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2316                 queue, qnum, params->aifs, params->cw_min,
2317                 params->cw_max, params->txop);
2318
2319         ret = ath_txq_update(sc, qnum, &qi);
2320         if (ret)
2321                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2322
2323         return ret;
2324 }
2325
2326 static int ath9k_set_key(struct ieee80211_hw *hw,
2327                          enum set_key_cmd cmd,
2328                          const u8 *local_addr,
2329                          const u8 *addr,
2330                          struct ieee80211_key_conf *key)
2331 {
2332         struct ath_softc *sc = hw->priv;
2333         int ret = 0;
2334
2335         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2336
2337         switch (cmd) {
2338         case SET_KEY:
2339                 ret = ath_key_config(sc, addr, key);
2340                 if (ret >= 0) {
2341                         key->hw_key_idx = ret;
2342                         /* push IV and Michael MIC generation to stack */
2343                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2344                         if (key->alg == ALG_TKIP)
2345                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2346                         ret = 0;
2347                 }
2348                 break;
2349         case DISABLE_KEY:
2350                 ath_key_delete(sc, key);
2351                 break;
2352         default:
2353                 ret = -EINVAL;
2354         }
2355
2356         return ret;
2357 }
2358
2359 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2360                                    struct ieee80211_vif *vif,
2361                                    struct ieee80211_bss_conf *bss_conf,
2362                                    u32 changed)
2363 {
2364         struct ath_softc *sc = hw->priv;
2365
2366         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2367                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2368                         bss_conf->use_short_preamble);
2369                 if (bss_conf->use_short_preamble)
2370                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2371                 else
2372                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2373         }
2374
2375         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2376                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2377                         bss_conf->use_cts_prot);
2378                 if (bss_conf->use_cts_prot &&
2379                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2380                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2381                 else
2382                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2383         }
2384
2385         if (changed & BSS_CHANGED_ASSOC) {
2386                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2387                         bss_conf->assoc);
2388                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2389         }
2390 }
2391
2392 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2393 {
2394         u64 tsf;
2395         struct ath_softc *sc = hw->priv;
2396         struct ath_hal *ah = sc->sc_ah;
2397
2398         tsf = ath9k_hw_gettsf64(ah);
2399
2400         return tsf;
2401 }
2402
2403 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2404 {
2405         struct ath_softc *sc = hw->priv;
2406         struct ath_hal *ah = sc->sc_ah;
2407
2408         ath9k_hw_reset_tsf(ah);
2409 }
2410
2411 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2412                        enum ieee80211_ampdu_mlme_action action,
2413                        struct ieee80211_sta *sta,
2414                        u16 tid, u16 *ssn)
2415 {
2416         struct ath_softc *sc = hw->priv;
2417         int ret = 0;
2418
2419         switch (action) {
2420         case IEEE80211_AMPDU_RX_START:
2421                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2422                         ret = -ENOTSUPP;
2423                 break;
2424         case IEEE80211_AMPDU_RX_STOP:
2425                 break;
2426         case IEEE80211_AMPDU_TX_START:
2427                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2428                 if (ret < 0)
2429                         DPRINTF(sc, ATH_DBG_FATAL,
2430                                 "Unable to start TX aggregation\n");
2431                 else
2432                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2433                 break;
2434         case IEEE80211_AMPDU_TX_STOP:
2435                 ret = ath_tx_aggr_stop(sc, sta, tid);
2436                 if (ret < 0)
2437                         DPRINTF(sc, ATH_DBG_FATAL,
2438                                 "Unable to stop TX aggregation\n");
2439
2440                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2441                 break;
2442         case IEEE80211_AMPDU_TX_RESUME:
2443                 ath_tx_aggr_resume(sc, sta, tid);
2444                 break;
2445         default:
2446                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2447         }
2448
2449         return ret;
2450 }
2451
2452 static struct ieee80211_ops ath9k_ops = {
2453         .tx                 = ath9k_tx,
2454         .start              = ath9k_start,
2455         .stop               = ath9k_stop,
2456         .add_interface      = ath9k_add_interface,
2457         .remove_interface   = ath9k_remove_interface,
2458         .config             = ath9k_config,
2459         .config_interface   = ath9k_config_interface,
2460         .configure_filter   = ath9k_configure_filter,
2461         .sta_notify         = ath9k_sta_notify,
2462         .conf_tx            = ath9k_conf_tx,
2463         .bss_info_changed   = ath9k_bss_info_changed,
2464         .set_key            = ath9k_set_key,
2465         .get_tsf            = ath9k_get_tsf,
2466         .reset_tsf          = ath9k_reset_tsf,
2467         .ampdu_action       = ath9k_ampdu_action,
2468 };
2469
2470 static struct {
2471         u32 version;
2472         const char * name;
2473 } ath_mac_bb_names[] = {
2474         { AR_SREV_VERSION_5416_PCI,     "5416" },
2475         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2476         { AR_SREV_VERSION_9100,         "9100" },
2477         { AR_SREV_VERSION_9160,         "9160" },
2478         { AR_SREV_VERSION_9280,         "9280" },
2479         { AR_SREV_VERSION_9285,         "9285" }
2480 };
2481
2482 static struct {
2483         u16 version;
2484         const char * name;
2485 } ath_rf_names[] = {
2486         { 0,                            "5133" },
2487         { AR_RAD5133_SREV_MAJOR,        "5133" },
2488         { AR_RAD5122_SREV_MAJOR,        "5122" },
2489         { AR_RAD2133_SREV_MAJOR,        "2133" },
2490         { AR_RAD2122_SREV_MAJOR,        "2122" }
2491 };
2492
2493 /*
2494  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2495  */
2496 static const char *
2497 ath_mac_bb_name(u32 mac_bb_version)
2498 {
2499         int i;
2500
2501         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2502                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2503                         return ath_mac_bb_names[i].name;
2504                 }
2505         }
2506
2507         return "????";
2508 }
2509
2510 /*
2511  * Return the RF name. "????" is returned if the RF is unknown.
2512  */
2513 static const char *
2514 ath_rf_name(u16 rf_version)
2515 {
2516         int i;
2517
2518         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2519                 if (ath_rf_names[i].version == rf_version) {
2520                         return ath_rf_names[i].name;
2521                 }
2522         }
2523
2524         return "????";
2525 }
2526
2527 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2528 {
2529         void __iomem *mem;
2530         struct ath_softc *sc;
2531         struct ieee80211_hw *hw;
2532         u8 csz;
2533         u32 val;
2534         int ret = 0;
2535         struct ath_hal *ah;
2536
2537         if (pci_enable_device(pdev))
2538                 return -EIO;
2539
2540         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2541
2542         if (ret) {
2543                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2544                 goto bad;
2545         }
2546
2547         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2548
2549         if (ret) {
2550                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2551                         "DMA enable failed\n");
2552                 goto bad;
2553         }
2554
2555         /*
2556          * Cache line size is used to size and align various
2557          * structures used to communicate with the hardware.
2558          */
2559         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2560         if (csz == 0) {
2561                 /*
2562                  * Linux 2.4.18 (at least) writes the cache line size
2563                  * register as a 16-bit wide register which is wrong.
2564                  * We must have this setup properly for rx buffer
2565                  * DMA to work so force a reasonable value here if it
2566                  * comes up zero.
2567                  */
2568                 csz = L1_CACHE_BYTES / sizeof(u32);
2569                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2570         }
2571         /*
2572          * The default setting of latency timer yields poor results,
2573          * set it to the value used by other systems. It may be worth
2574          * tweaking this setting more.
2575          */
2576         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2577
2578         pci_set_master(pdev);
2579
2580         /*
2581          * Disable the RETRY_TIMEOUT register (0x41) to keep
2582          * PCI Tx retries from interfering with C3 CPU state.
2583          */
2584         pci_read_config_dword(pdev, 0x40, &val);
2585         if ((val & 0x0000ff00) != 0)
2586                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2587
2588         ret = pci_request_region(pdev, 0, "ath9k");
2589         if (ret) {
2590                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2591                 ret = -ENODEV;
2592                 goto bad;
2593         }
2594
2595         mem = pci_iomap(pdev, 0, 0);
2596         if (!mem) {
2597                 printk(KERN_ERR "PCI memory map error\n") ;
2598                 ret = -EIO;
2599                 goto bad1;
2600         }
2601
2602         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2603         if (hw == NULL) {
2604                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2605                 goto bad2;
2606         }
2607
2608         SET_IEEE80211_DEV(hw, &pdev->dev);
2609         pci_set_drvdata(pdev, hw);
2610
2611         sc = hw->priv;
2612         sc->hw = hw;
2613         sc->pdev = pdev;
2614         sc->mem = mem;
2615
2616         if (ath_attach(id->device, sc) != 0) {
2617                 ret = -ENODEV;
2618                 goto bad3;
2619         }
2620
2621         /* setup interrupt service routine */
2622
2623         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2624                 printk(KERN_ERR "%s: request_irq failed\n",
2625                         wiphy_name(hw->wiphy));
2626                 ret = -EIO;
2627                 goto bad4;
2628         }
2629
2630         ah = sc->sc_ah;
2631         printk(KERN_INFO
2632                "%s: Atheros AR%s MAC/BB Rev:%x "
2633                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2634                wiphy_name(hw->wiphy),
2635                ath_mac_bb_name(ah->ah_macVersion),
2636                ah->ah_macRev,
2637                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2638                ah->ah_phyRev,
2639                (unsigned long)mem, pdev->irq);
2640
2641         return 0;
2642 bad4:
2643         ath_detach(sc);
2644 bad3:
2645         ieee80211_free_hw(hw);
2646 bad2:
2647         pci_iounmap(pdev, mem);
2648 bad1:
2649         pci_release_region(pdev, 0);
2650 bad:
2651         pci_disable_device(pdev);
2652         return ret;
2653 }
2654
2655 static void ath_pci_remove(struct pci_dev *pdev)
2656 {
2657         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2658         struct ath_softc *sc = hw->priv;
2659
2660         ath_detach(sc);
2661         if (pdev->irq)
2662                 free_irq(pdev->irq, sc);
2663         pci_iounmap(pdev, sc->mem);
2664         pci_release_region(pdev, 0);
2665         pci_disable_device(pdev);
2666         ieee80211_free_hw(hw);
2667 }
2668
2669 #ifdef CONFIG_PM
2670
2671 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2672 {
2673         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2674         struct ath_softc *sc = hw->priv;
2675
2676         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2677
2678 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2679         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2680                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2681 #endif
2682
2683         pci_save_state(pdev);
2684         pci_disable_device(pdev);
2685         pci_set_power_state(pdev, 3);
2686
2687         return 0;
2688 }
2689
2690 static int ath_pci_resume(struct pci_dev *pdev)
2691 {
2692         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2693         struct ath_softc *sc = hw->priv;
2694         u32 val;
2695         int err;
2696
2697         err = pci_enable_device(pdev);
2698         if (err)
2699                 return err;
2700         pci_restore_state(pdev);
2701         /*
2702          * Suspend/Resume resets the PCI configuration space, so we have to
2703          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2704          * PCI Tx retries from interfering with C3 CPU state
2705          */
2706         pci_read_config_dword(pdev, 0x40, &val);
2707         if ((val & 0x0000ff00) != 0)
2708                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2709
2710         /* Enable LED */
2711         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2712                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2713         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2714
2715 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2716         /*
2717          * check the h/w rfkill state on resume
2718          * and start the rfkill poll timer
2719          */
2720         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2721                 queue_delayed_work(sc->hw->workqueue,
2722                                    &sc->rf_kill.rfkill_poll, 0);
2723 #endif
2724
2725         return 0;
2726 }
2727
2728 #endif /* CONFIG_PM */
2729
2730 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2731
2732 static struct pci_driver ath_pci_driver = {
2733         .name       = "ath9k",
2734         .id_table   = ath_pci_id_table,
2735         .probe      = ath_pci_probe,
2736         .remove     = ath_pci_remove,
2737 #ifdef CONFIG_PM
2738         .suspend    = ath_pci_suspend,
2739         .resume     = ath_pci_resume,
2740 #endif /* CONFIG_PM */
2741 };
2742
2743 static int __init init_ath_pci(void)
2744 {
2745         int error;
2746
2747         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2748
2749         /* Register rate control algorithm */
2750         error = ath_rate_control_register();
2751         if (error != 0) {
2752                 printk(KERN_ERR
2753                         "Unable to register rate control algorithm: %d\n",
2754                         error);
2755                 ath_rate_control_unregister();
2756                 return error;
2757         }
2758
2759         if (pci_register_driver(&ath_pci_driver) < 0) {
2760                 printk(KERN_ERR
2761                         "ath_pci: No devices found, driver not installed.\n");
2762                 ath_rate_control_unregister();
2763                 pci_unregister_driver(&ath_pci_driver);
2764                 return -ENODEV;
2765         }
2766
2767         return 0;
2768 }
2769 module_init(init_ath_pci);
2770
2771 static void __exit exit_ath_pci(void)
2772 {
2773         ath_rate_control_unregister();
2774         pci_unregister_driver(&ath_pci_driver);
2775         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2776 }
2777 module_exit(exit_ath_pci);