drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 static int modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  32
  33 /* We use the hw_value as an index into our private channel structure */
  34
  35 #define CHAN2G(_freq, _idx)  { \
  36         .center_freq = (_freq), \
  37         .hw_value = (_idx), \
  38         .max_power = 30, \
  39 }
  40
  41 #define CHAN5G(_freq, _idx) { \
  42         .band = IEEE80211_BAND_5GHZ, \
  43         .center_freq = (_freq), \
  44         .hw_value = (_idx), \
  45         .max_power = 30, \
  46 }
  47
  48 /* Some 2 GHz radios are actually tunable on 2312-2732
  49  * on 5 MHz steps, we support the channels which we know
  50  * we have calibration data for all cards though to make
  51  * this static */
  52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  53         CHAN2G(2412, 0), /* Channel 1 */
  54         CHAN2G(2417, 1), /* Channel 2 */
  55         CHAN2G(2422, 2), /* Channel 3 */
  56         CHAN2G(2427, 3), /* Channel 4 */
  57         CHAN2G(2432, 4), /* Channel 5 */
  58         CHAN2G(2437, 5), /* Channel 6 */
  59         CHAN2G(2442, 6), /* Channel 7 */
  60         CHAN2G(2447, 7), /* Channel 8 */
  61         CHAN2G(2452, 8), /* Channel 9 */
  62         CHAN2G(2457, 9), /* Channel 10 */
  63         CHAN2G(2462, 10), /* Channel 11 */
  64         CHAN2G(2467, 11), /* Channel 12 */
  65         CHAN2G(2472, 12), /* Channel 13 */
  66         CHAN2G(2484, 13), /* Channel 14 */
  67 };
  68
  69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  70  * on 5 MHz steps, we support the channels which we know
  71  * we have calibration data for all cards though to make
  72  * this static */
  73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  74         /* _We_ call this UNII 1 */
  75         CHAN5G(5180, 14), /* Channel 36 */
  76         CHAN5G(5200, 15), /* Channel 40 */
  77         CHAN5G(5220, 16), /* Channel 44 */
  78         CHAN5G(5240, 17), /* Channel 48 */
  79         /* _We_ call this UNII 2 */
  80         CHAN5G(5260, 18), /* Channel 52 */
  81         CHAN5G(5280, 19), /* Channel 56 */
  82         CHAN5G(5300, 20), /* Channel 60 */
  83         CHAN5G(5320, 21), /* Channel 64 */
  84         /* _We_ call this "Middle band" */
  85         CHAN5G(5500, 22), /* Channel 100 */
  86         CHAN5G(5520, 23), /* Channel 104 */
  87         CHAN5G(5540, 24), /* Channel 108 */
  88         CHAN5G(5560, 25), /* Channel 112 */
  89         CHAN5G(5580, 26), /* Channel 116 */
  90         CHAN5G(5600, 27), /* Channel 120 */
  91         CHAN5G(5620, 28), /* Channel 124 */
  92         CHAN5G(5640, 29), /* Channel 128 */
  93         CHAN5G(5660, 30), /* Channel 132 */
  94         CHAN5G(5680, 31), /* Channel 136 */
  95         CHAN5G(5700, 32), /* Channel 140 */
  96         /* _We_ call this UNII 3 */
  97         CHAN5G(5745, 33), /* Channel 149 */
  98         CHAN5G(5765, 34), /* Channel 153 */
  99         CHAN5G(5785, 35), /* Channel 157 */
 100         CHAN5G(5805, 36), /* Channel 161 */
 101         CHAN5G(5825, 37), /* Channel 165 */
 102 };
 103
 104 static void ath_cache_conf_rate(struct ath_softc *sc,
 105                                 struct ieee80211_conf *conf)
 106 {
 107         switch (conf->channel->band) {
 108         case IEEE80211_BAND_2GHZ:
 109                 if (conf_is_ht20(conf))
 110                         sc->cur_rate_table =
 111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 112                 else if (conf_is_ht40_minus(conf))
 113                         sc->cur_rate_table =
 114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 115                 else if (conf_is_ht40_plus(conf))
 116                         sc->cur_rate_table =
 117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 118                 else
 119                         sc->cur_rate_table =
 120                           sc->hw_rate_table[ATH9K_MODE_11G];
 121                 break;
 122         case IEEE80211_BAND_5GHZ:
 123                 if (conf_is_ht20(conf))
 124                         sc->cur_rate_table =
 125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 126                 else if (conf_is_ht40_minus(conf))
 127                         sc->cur_rate_table =
 128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 129                 else if (conf_is_ht40_plus(conf))
 130                         sc->cur_rate_table =
 131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 132                 else
 133                         sc->cur_rate_table =
 134                           sc->hw_rate_table[ATH9K_MODE_11A];
 135                 break;
 136         default:
 137                 BUG_ON(1);
 138                 break;
 139         }
 140 }
 141
 142 static void ath_update_txpow(struct ath_softc *sc)
 143 {
 144         struct ath_hw *ah = sc->sc_ah;
 145         u32 txpow;
 146
 147         if (sc->curtxpow != sc->config.txpowlimit) {
 148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 149                 /* read back in case value is clamped */
 150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 151                 sc->curtxpow = txpow;
 152         }
 153 }
 154
 155 static u8 parse_mpdudensity(u8 mpdudensity)
 156 {
 157         /*
 158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 159          *   0 for no restriction
 160          *   1 for 1/4 us
 161          *   2 for 1/2 us
 162          *   3 for 1 us
 163          *   4 for 2 us
 164          *   5 for 4 us
 165          *   6 for 8 us
 166          *   7 for 16 us
 167          */
 168         switch (mpdudensity) {
 169         case 0:
 170                 return 0;
 171         case 1:
 172         case 2:
 173         case 3:
 174                 /* Our lower layer calculations limit our precision to
 175                    1 microsecond */
 176                 return 1;
 177         case 4:
 178                 return 2;
 179         case 5:
 180                 return 4;
 181         case 6:
 182                 return 8;
 183         case 7:
 184                 return 16;
 185         default:
 186                 return 0;
 187         }
 188 }
 189
 190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 191 {
 192         struct ath_rate_table *rate_table = NULL;
 193         struct ieee80211_supported_band *sband;
 194         struct ieee80211_rate *rate;
 195         int i, maxrates;
 196
 197         switch (band) {
 198         case IEEE80211_BAND_2GHZ:
 199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 200                 break;
 201         case IEEE80211_BAND_5GHZ:
 202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 203                 break;
 204         default:
 205                 break;
 206         }
 207
 208         if (rate_table == NULL)
 209                 return;
 210
 211         sband = &sc->sbands[band];
 212         rate = sc->rates[band];
 213
 214         if (rate_table->rate_cnt > ATH_RATE_MAX)
 215                 maxrates = ATH_RATE_MAX;
 216         else
 217                 maxrates = rate_table->rate_cnt;
 218
 219         for (i = 0; i < maxrates; i++) {
 220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 221                 rate[i].hw_value = rate_table->info[i].ratecode;
 222                 if (rate_table->info[i].short_preamble) {
 223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 224                                 rate_table->info[i].short_preamble;
 225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 226                 }
 227                 sband->n_bitrates++;
 228
 229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 230                         rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 /*
 235  * Set/change channels.  If the channel is really being changed, it's done
 236  * by reseting the chip.  To accomplish this we must first cleanup any pending
 237  * DMA, then restart stuff.
 238 */
 239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 240                     struct ath9k_channel *hchan)
 241 {
 242         struct ath_hw *ah = sc->sc_ah;
 243         bool fastcc = true, stopped;
 244         struct ieee80211_channel *channel = hw->conf.channel;
 245         int r;
 246
 247         if (sc->sc_flags & SC_OP_INVALID)
 248                 return -EIO;
 249
 250         ath9k_ps_wakeup(sc);
 251
 252         /*
 253          * This is only performed if the channel settings have
 254          * actually changed.
 255          *
 256          * To switch channels clear any pending DMA operations;
 257          * wait long enough for the RX fifo to drain, reset the
 258          * hardware at the new frequency, and then re-enable
 259          * the relevant bits of the h/w.
 260          */
 261         ath9k_hw_set_interrupts(ah, 0);
 262         ath_drain_all_txq(sc, false);
 263         stopped = ath_stoprecv(sc);
 264
 265         /* XXX: do not flush receive queue here. We don't want
 266          * to flush data frames already in queue because of
 267          * changing channel. */
 268
 269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 270                 fastcc = false;
 271
 272         DPRINTF(sc, ATH_DBG_CONFIG,
 273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 274                 sc->sc_ah->curchan->channel,
 275                 channel->center_freq, sc->tx_chan_width);
 276
 277         spin_lock_bh(&sc->sc_resetlock);
 278
 279         r = ath9k_hw_reset(ah, hchan, fastcc);
 280         if (r) {
 281                 DPRINTF(sc, ATH_DBG_FATAL,
 282                         "Unable to reset channel (%u Mhz) "
 283                         "reset status %u\n",
 284                         channel->center_freq, r);
 285                 spin_unlock_bh(&sc->sc_resetlock);
 286                 return r;
 287         }
 288         spin_unlock_bh(&sc->sc_resetlock);
 289
 290         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 291         sc->sc_flags &= ~SC_OP_FULL_RESET;
 292
 293         if (ath_startrecv(sc) != 0) {
 294                 DPRINTF(sc, ATH_DBG_FATAL,
 295                         "Unable to restart recv logic\n");
 296                 return -EIO;
 297         }
 298
 299         ath_cache_conf_rate(sc, &hw->conf);
 300         ath_update_txpow(sc);
 301         ath9k_hw_set_interrupts(ah, sc->imask);
 302         ath9k_ps_restore(sc);
 303         return 0;
 304 }
 305
 306 /*
 307  *  This routine performs the periodic noise floor calibration function
 308  *  that is used to adjust and optimize the chip performance.  This
 309  *  takes environmental changes (location, temperature) into account.
 310  *  When the task is complete, it reschedules itself depending on the
 311  *  appropriate interval that was calculated.
 312  */
 313 static void ath_ani_calibrate(unsigned long data)
 314 {
 315         struct ath_softc *sc = (struct ath_softc *)data;
 316         struct ath_hw *ah = sc->sc_ah;
 317         bool longcal = false;
 318         bool shortcal = false;
 319         bool aniflag = false;
 320         unsigned int timestamp = jiffies_to_msecs(jiffies);
 321         u32 cal_interval, short_cal_interval;
 322
 323         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 324                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 325
 326         /*
 327         * don't calibrate when we're scanning.
 328         * we are most likely not on our home channel.
 329         */
 330         if (sc->sc_flags & SC_OP_SCANNING)
 331                 goto set_timer;
 332
 333         /* Long calibration runs independently of short calibration. */
 334         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 335                 longcal = true;
 336                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 337                 sc->ani.longcal_timer = timestamp;
 338         }
 339
 340         /* Short calibration applies only while caldone is false */
 341         if (!sc->ani.caldone) {
 342                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 343                         shortcal = true;
 344                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 345                         sc->ani.shortcal_timer = timestamp;
 346                         sc->ani.resetcal_timer = timestamp;
 347                 }
 348         } else {
 349                 if ((timestamp - sc->ani.resetcal_timer) >=
 350                     ATH_RESTART_CALINTERVAL) {
 351                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 352                         if (sc->ani.caldone)
 353                                 sc->ani.resetcal_timer = timestamp;
 354                 }
 355         }
 356
 357         /* Verify whether we must check ANI */
 358         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 359                 aniflag = true;
 360                 sc->ani.checkani_timer = timestamp;
 361         }
 362
 363         /* Skip all processing if there's nothing to do. */
 364         if (longcal || shortcal || aniflag) {
 365                 /* Call ANI routine if necessary */
 366                 if (aniflag)
 367                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 368
 369                 /* Perform calibration if necessary */
 370                 if (longcal || shortcal) {
 371                         bool iscaldone = false;
 372
 373                         if (ath9k_hw_calibrate(ah, ah->curchan,
 374                                                sc->rx_chainmask, longcal,
 375                                                &iscaldone)) {
 376                                 if (longcal)
 377                                         sc->ani.noise_floor =
 378                                                 ath9k_hw_getchan_noise(ah,
 379                                                                ah->curchan);
 380
 381                                 DPRINTF(sc, ATH_DBG_ANI,
 382                                         "calibrate chan %u/%x nf: %d\n",
 383                                         ah->curchan->channel,
 384                                         ah->curchan->channelFlags,
 385                                         sc->ani.noise_floor);
 386                         } else {
 387                                 DPRINTF(sc, ATH_DBG_ANY,
 388                                         "calibrate chan %u/%x failed\n",
 389                                         ah->curchan->channel,
 390                                         ah->curchan->channelFlags);
 391                         }
 392                         sc->ani.caldone = iscaldone;
 393                 }
 394         }
 395
 396 set_timer:
 397         /*
 398         * Set timer interval based on previous results.
 399         * The interval must be the shortest necessary to satisfy ANI,
 400         * short calibration and long calibration.
 401         */
 402         cal_interval = ATH_LONG_CALINTERVAL;
 403         if (sc->sc_ah->config.enable_ani)
 404                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 405         if (!sc->ani.caldone)
 406                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 407
 408         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 409 }
 410
 411 /*
 412  * Update tx/rx chainmask. For legacy association,
 413  * hard code chainmask to 1x1, for 11n association, use
 414  * the chainmask configuration, for bt coexistence, use
 415  * the chainmask configuration even in legacy mode.
 416  */
 417 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 418 {
 419         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 420         if (is_ht ||
 421             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 422                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 423                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 424         } else {
 425                 sc->tx_chainmask = 1;
 426                 sc->rx_chainmask = 1;
 427         }
 428
 429         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 430                 sc->tx_chainmask, sc->rx_chainmask);
 431 }
 432
 433 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 434 {
 435         struct ath_node *an;
 436
 437         an = (struct ath_node *)sta->drv_priv;
 438
 439         if (sc->sc_flags & SC_OP_TXAGGR)
 440                 ath_tx_node_init(sc, an);
 441
 442         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 443                              sta->ht_cap.ampdu_factor);
 444         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 445 }
 446
 447 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 448 {
 449         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 450
 451         if (sc->sc_flags & SC_OP_TXAGGR)
 452                 ath_tx_node_cleanup(sc, an);
 453 }
 454
 455 static void ath9k_tasklet(unsigned long data)
 456 {
 457         struct ath_softc *sc = (struct ath_softc *)data;
 458         u32 status = sc->intrstatus;
 459
 460         if (status & ATH9K_INT_FATAL) {
 461                 /* need a chip reset */
 462                 ath_reset(sc, false);
 463                 return;
 464         } else {
 465
 466                 if (status &
 467                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 468                         spin_lock_bh(&sc->rx.rxflushlock);
 469                         ath_rx_tasklet(sc, 0);
 470                         spin_unlock_bh(&sc->rx.rxflushlock);
 471                 }
 472                 /* XXX: optimize this */
 473                 if (status & ATH9K_INT_TX)
 474                         ath_tx_tasklet(sc);
 475         }
 476
 477         /* re-enable hardware interrupt */
 478         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 479 }
 480
 481 irqreturn_t ath_isr(int irq, void *dev)
 482 {
 483         struct ath_softc *sc = dev;
 484         struct ath_hw *ah = sc->sc_ah;
 485         enum ath9k_int status;
 486         bool sched = false;
 487
 488         do {
 489                 if (sc->sc_flags & SC_OP_INVALID) {
 490                         /*
 491                          * The hardware is not ready/present, don't
 492                          * touch anything. Note this can happen early
 493                          * on if the IRQ is shared.
 494                          */
 495                         return IRQ_NONE;
 496                 }
 497                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 498                         return IRQ_NONE;
 499                 }
 500
 501                 /*
 502                  * Figure out the reason(s) for the interrupt.  Note
 503                  * that the hal returns a pseudo-ISR that may include
 504                  * bits we haven't explicitly enabled so we mask the
 505                  * value to insure we only process bits we requested.
 506                  */
 507                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 508
 509                 status &= sc->imask;    /* discard unasked-for bits */
 510
 511                 /*
 512                  * If there are no status bits set, then this interrupt was not
 513                  * for me (should have been caught above).
 514                  */
 515                 if (!status)
 516                         return IRQ_NONE;
 517
 518                 sc->intrstatus = status;
 519                 ath9k_ps_wakeup(sc);
 520
 521                 if (status & ATH9K_INT_FATAL) {
 522                         /* need a chip reset */
 523                         sched = true;
 524                 } else if (status & ATH9K_INT_RXORN) {
 525                         /* need a chip reset */
 526                         sched = true;
 527                 } else {
 528                         if (status & ATH9K_INT_SWBA) {
 529                                 /* schedule a tasklet for beacon handling */
 530                                 tasklet_schedule(&sc->bcon_tasklet);
 531                         }
 532                         if (status & ATH9K_INT_RXEOL) {
 533                                 /*
 534                                  * NB: the hardware should re-read the link when
 535                                  *     RXE bit is written, but it doesn't work
 536                                  *     at least on older hardware revs.
 537                                  */
 538                                 sched = true;
 539                         }
 540
 541                         if (status & ATH9K_INT_TXURN)
 542                                 /* bump tx trigger level */
 543                                 ath9k_hw_updatetxtriglevel(ah, true);
 544                         /* XXX: optimize this */
 545                         if (status & ATH9K_INT_RX)
 546                                 sched = true;
 547                         if (status & ATH9K_INT_TX)
 548                                 sched = true;
 549                         if (status & ATH9K_INT_BMISS)
 550                                 sched = true;
 551                         /* carrier sense timeout */
 552                         if (status & ATH9K_INT_CST)
 553                                 sched = true;
 554                         if (status & ATH9K_INT_MIB) {
 555                                 /*
 556                                  * Disable interrupts until we service the MIB
 557                                  * interrupt; otherwise it will continue to
 558                                  * fire.
 559                                  */
 560                                 ath9k_hw_set_interrupts(ah, 0);
 561                                 /*
 562                                  * Let the hal handle the event. We assume
 563                                  * it will clear whatever condition caused
 564                                  * the interrupt.
 565                                  */
 566                                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 567                                 ath9k_hw_set_interrupts(ah, sc->imask);
 568                         }
 569                         if (status & ATH9K_INT_TIM_TIMER) {
 570                                 if (!(ah->caps.hw_caps &
 571                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 572                                         /* Clear RxAbort bit so that we can
 573                                          * receive frames */
 574                                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 575                                         ath9k_hw_setrxabort(ah, 0);
 576                                         sched = true;
 577                                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 578                                 }
 579                         }
 580                         if (status & ATH9K_INT_TSFOOR) {
 581                                 /* FIXME: Handle this interrupt for power save */
 582                                 sched = true;
 583                         }
 584                 }
 585                 ath9k_ps_restore(sc);
 586         } while (0);
 587
 588         ath_debug_stat_interrupt(sc, status);
 589
 590         if (sched) {
 591                 /* turn off every interrupt except SWBA */
 592                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 593                 tasklet_schedule(&sc->intr_tq);
 594         }
 595
 596         return IRQ_HANDLED;
 597 }
 598
 599 static u32 ath_get_extchanmode(struct ath_softc *sc,
 600                                struct ieee80211_channel *chan,
 601                                enum nl80211_channel_type channel_type)
 602 {
 603         u32 chanmode = 0;
 604
 605         switch (chan->band) {
 606         case IEEE80211_BAND_2GHZ:
 607                 switch(channel_type) {
 608                 case NL80211_CHAN_NO_HT:
 609                 case NL80211_CHAN_HT20:
 610                         chanmode = CHANNEL_G_HT20;
 611                         break;
 612                 case NL80211_CHAN_HT40PLUS:
 613                         chanmode = CHANNEL_G_HT40PLUS;
 614                         break;
 615                 case NL80211_CHAN_HT40MINUS:
 616                         chanmode = CHANNEL_G_HT40MINUS;
 617                         break;
 618                 }
 619                 break;
 620         case IEEE80211_BAND_5GHZ:
 621                 switch(channel_type) {
 622                 case NL80211_CHAN_NO_HT:
 623                 case NL80211_CHAN_HT20:
 624                         chanmode = CHANNEL_A_HT20;
 625                         break;
 626                 case NL80211_CHAN_HT40PLUS:
 627                         chanmode = CHANNEL_A_HT40PLUS;
 628                         break;
 629                 case NL80211_CHAN_HT40MINUS:
 630                         chanmode = CHANNEL_A_HT40MINUS;
 631                         break;
 632                 }
 633                 break;
 634         default:
 635                 break;
 636         }
 637
 638         return chanmode;
 639 }
 640
 641 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 642                            struct ath9k_keyval *hk, const u8 *addr,
 643                            bool authenticator)
 644 {
 645         const u8 *key_rxmic;
 646         const u8 *key_txmic;
 647
 648         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 649         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 650
 651         if (addr == NULL) {
 652                 /*
 653                  * Group key installation - only two key cache entries are used
 654                  * regardless of splitmic capability since group key is only
 655                  * used either for TX or RX.
 656                  */
 657                 if (authenticator) {
 658                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 659                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 660                 } else {
 661                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 662                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 663                 }
 664                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 665         }
 666         if (!sc->splitmic) {
 667                 /* TX and RX keys share the same key cache entry. */
 668                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 669                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 670                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 671         }
 672
 673         /* Separate key cache entries for TX and RX */
 674
 675         /* TX key goes at first index, RX key at +32. */
 676         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 677         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 678                 /* TX MIC entry failed. No need to proceed further */
 679                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 680                         "Setting TX MIC Key Failed\n");
 681                 return 0;
 682         }
 683
 684         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 685         /* XXX delete tx key on failure? */
 686         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 687 }
 688
 689 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 690 {
 691         int i;
 692
 693         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 694                 if (test_bit(i, sc->keymap) ||
 695                     test_bit(i + 64, sc->keymap))
 696                         continue; /* At least one part of TKIP key allocated */
 697                 if (sc->splitmic &&
 698                     (test_bit(i + 32, sc->keymap) ||
 699                      test_bit(i + 64 + 32, sc->keymap)))
 700                         continue; /* At least one part of TKIP key allocated */
 701
 702                 /* Found a free slot for a TKIP key */
 703                 return i;
 704         }
 705         return -1;
 706 }
 707
 708 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 709 {
 710         int i;
 711
 712         /* First, try to find slots that would not be available for TKIP. */
 713         if (sc->splitmic) {
 714                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 715                         if (!test_bit(i, sc->keymap) &&
 716                             (test_bit(i + 32, sc->keymap) ||
 717                              test_bit(i + 64, sc->keymap) ||
 718                              test_bit(i + 64 + 32, sc->keymap)))
 719                                 return i;
 720                         if (!test_bit(i + 32, sc->keymap) &&
 721                             (test_bit(i, sc->keymap) ||
 722                              test_bit(i + 64, sc->keymap) ||
 723                              test_bit(i + 64 + 32, sc->keymap)))
 724                                 return i + 32;
 725                         if (!test_bit(i + 64, sc->keymap) &&
 726                             (test_bit(i , sc->keymap) ||
 727                              test_bit(i + 32, sc->keymap) ||
 728                              test_bit(i + 64 + 32, sc->keymap)))
 729                                 return i + 64;
 730                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 731                             (test_bit(i, sc->keymap) ||
 732                              test_bit(i + 32, sc->keymap) ||
 733                              test_bit(i + 64, sc->keymap)))
 734                                 return i + 64 + 32;
 735                 }
 736         } else {
 737                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 738                         if (!test_bit(i, sc->keymap) &&
 739                             test_bit(i + 64, sc->keymap))
 740                                 return i;
 741                         if (test_bit(i, sc->keymap) &&
 742                             !test_bit(i + 64, sc->keymap))
 743                                 return i + 64;
 744                 }
 745         }
 746
 747         /* No partially used TKIP slots, pick any available slot */
 748         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 749                 /* Do not allow slots that could be needed for TKIP group keys
 750                  * to be used. This limitation could be removed if we know that
 751                  * TKIP will not be used. */
 752                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 753                         continue;
 754                 if (sc->splitmic) {
 755                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 756                                 continue;
 757                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 758                                 continue;
 759                 }
 760
 761                 if (!test_bit(i, sc->keymap))
 762                         return i; /* Found a free slot for a key */
 763         }
 764
 765         /* No free slot found */
 766         return -1;
 767 }
 768
 769 static int ath_key_config(struct ath_softc *sc,
 770                           struct ieee80211_vif *vif,
 771                           struct ieee80211_sta *sta,
 772                           struct ieee80211_key_conf *key)
 773 {
 774         struct ath9k_keyval hk;
 775         const u8 *mac = NULL;
 776         int ret = 0;
 777         int idx;
 778
 779         memset(&hk, 0, sizeof(hk));
 780
 781         switch (key->alg) {
 782         case ALG_WEP:
 783                 hk.kv_type = ATH9K_CIPHER_WEP;
 784                 break;
 785         case ALG_TKIP:
 786                 hk.kv_type = ATH9K_CIPHER_TKIP;
 787                 break;
 788         case ALG_CCMP:
 789                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 790                 break;
 791         default:
 792                 return -EOPNOTSUPP;
 793         }
 794
 795         hk.kv_len = key->keylen;
 796         memcpy(hk.kv_val, key->key, key->keylen);
 797
 798         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 799                 /* For now, use the default keys for broadcast keys. This may
 800                  * need to change with virtual interfaces. */
 801                 idx = key->keyidx;
 802         } else if (key->keyidx) {
 803                 if (WARN_ON(!sta))
 804                         return -EOPNOTSUPP;
 805                 mac = sta->addr;
 806
 807                 if (vif->type != NL80211_IFTYPE_AP) {
 808                         /* Only keyidx 0 should be used with unicast key, but
 809                          * allow this for client mode for now. */
 810                         idx = key->keyidx;
 811                 } else
 812                         return -EIO;
 813         } else {
 814                 if (WARN_ON(!sta))
 815                         return -EOPNOTSUPP;
 816                 mac = sta->addr;
 817
 818                 if (key->alg == ALG_TKIP)
 819                         idx = ath_reserve_key_cache_slot_tkip(sc);
 820                 else
 821                         idx = ath_reserve_key_cache_slot(sc);
 822                 if (idx < 0)
 823                         return -ENOSPC; /* no free key cache entries */
 824         }
 825
 826         if (key->alg == ALG_TKIP)
 827                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 828                                       vif->type == NL80211_IFTYPE_AP);
 829         else
 830                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 831
 832         if (!ret)
 833                 return -EIO;
 834
 835         set_bit(idx, sc->keymap);
 836         if (key->alg == ALG_TKIP) {
 837                 set_bit(idx + 64, sc->keymap);
 838                 if (sc->splitmic) {
 839                         set_bit(idx + 32, sc->keymap);
 840                         set_bit(idx + 64 + 32, sc->keymap);
 841                 }
 842         }
 843
 844         return idx;
 845 }
 846
 847 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 848 {
 849         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 850         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 851                 return;
 852
 853         clear_bit(key->hw_key_idx, sc->keymap);
 854         if (key->alg != ALG_TKIP)
 855                 return;
 856
 857         clear_bit(key->hw_key_idx + 64, sc->keymap);
 858         if (sc->splitmic) {
 859                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 860                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 861         }
 862 }
 863
 864 static void setup_ht_cap(struct ath_softc *sc,
 865                          struct ieee80211_sta_ht_cap *ht_info)
 866 {
 867 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 868 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 869
 870         ht_info->ht_supported = true;
 871         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 872                        IEEE80211_HT_CAP_SM_PS |
 873                        IEEE80211_HT_CAP_SGI_40 |
 874                        IEEE80211_HT_CAP_DSSSCCK40;
 875
 876         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 877         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 878
 879         /* set up supported mcs set */
 880         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 881
 882         switch(sc->rx_chainmask) {
 883         case 1:
 884                 ht_info->mcs.rx_mask[0] = 0xff;
 885                 break;
 886         case 3:
 887         case 5:
 888         case 7:
 889         default:
 890                 ht_info->mcs.rx_mask[0] = 0xff;
 891                 ht_info->mcs.rx_mask[1] = 0xff;
 892                 break;
 893         }
 894
 895         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 896 }
 897
 898 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 899                                  struct ieee80211_vif *vif,
 900                                  struct ieee80211_bss_conf *bss_conf)
 901 {
 902         struct ath_vif *avp = (void *)vif->drv_priv;
 903
 904         if (bss_conf->assoc) {
 905                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 906                         bss_conf->aid, sc->curbssid);
 907
 908                 /* New association, store aid */
 909                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 910                         sc->curaid = bss_conf->aid;
 911                         ath9k_hw_write_associd(sc);
 912                 }
 913
 914                 /* Configure the beacon */
 915                 ath_beacon_config(sc, vif);
 916
 917                 /* Reset rssi stats */
 918                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 919                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 920                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 921                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 922
 923                 /* Start ANI */
 924                 mod_timer(&sc->ani.timer,
 925                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 926         } else {
 927                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 928                 sc->curaid = 0;
 929         }
 930 }
 931
 932 /********************************/
 933 /*       LED functions          */
 934 /********************************/
 935
 936 static void ath_led_blink_work(struct work_struct *work)
 937 {
 938         struct ath_softc *sc = container_of(work, struct ath_softc,
 939                                             ath_led_blink_work.work);
 940
 941         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 942                 return;
 943
 944         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
 945             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
 946                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 947         else
 948                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 949                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 950
 951         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 952                            (sc->sc_flags & SC_OP_LED_ON) ?
 953                            msecs_to_jiffies(sc->led_off_duration) :
 954                            msecs_to_jiffies(sc->led_on_duration));
 955
 956         sc->led_on_duration = sc->led_on_cnt ?
 957                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
 958                         ATH_LED_ON_DURATION_IDLE;
 959         sc->led_off_duration = sc->led_off_cnt ?
 960                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
 961                         ATH_LED_OFF_DURATION_IDLE;
 962         sc->led_on_cnt = sc->led_off_cnt = 0;
 963         if (sc->sc_flags & SC_OP_LED_ON)
 964                 sc->sc_flags &= ~SC_OP_LED_ON;
 965         else
 966                 sc->sc_flags |= SC_OP_LED_ON;
 967 }
 968
 969 static void ath_led_brightness(struct led_classdev *led_cdev,
 970                                enum led_brightness brightness)
 971 {
 972         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 973         struct ath_softc *sc = led->sc;
 974
 975         switch (brightness) {
 976         case LED_OFF:
 977                 if (led->led_type == ATH_LED_ASSOC ||
 978                     led->led_type == ATH_LED_RADIO) {
 979                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 980                                 (led->led_type == ATH_LED_RADIO));
 981                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 982                         if (led->led_type == ATH_LED_RADIO)
 983                                 sc->sc_flags &= ~SC_OP_LED_ON;
 984                 } else {
 985                         sc->led_off_cnt++;
 986                 }
 987                 break;
 988         case LED_FULL:
 989                 if (led->led_type == ATH_LED_ASSOC) {
 990                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 991                         queue_delayed_work(sc->hw->workqueue,
 992                                            &sc->ath_led_blink_work, 0);
 993                 } else if (led->led_type == ATH_LED_RADIO) {
 994                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 995                         sc->sc_flags |= SC_OP_LED_ON;
 996                 } else {
 997                         sc->led_on_cnt++;
 998                 }
 999                 break;
1000         default:
1001                 break;
1002         }
1003 }
1004
1005 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1006                             char *trigger)
1007 {
1008         int ret;
1009
1010         led->sc = sc;
1011         led->led_cdev.name = led->name;
1012         led->led_cdev.default_trigger = trigger;
1013         led->led_cdev.brightness_set = ath_led_brightness;
1014
1015         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1016         if (ret)
1017                 DPRINTF(sc, ATH_DBG_FATAL,
1018                         "Failed to register led:%s", led->name);
1019         else
1020                 led->registered = 1;
1021         return ret;
1022 }
1023
1024 static void ath_unregister_led(struct ath_led *led)
1025 {
1026         if (led->registered) {
1027                 led_classdev_unregister(&led->led_cdev);
1028                 led->registered = 0;
1029         }
1030 }
1031
1032 static void ath_deinit_leds(struct ath_softc *sc)
1033 {
1034         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1035         ath_unregister_led(&sc->assoc_led);
1036         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1037         ath_unregister_led(&sc->tx_led);
1038         ath_unregister_led(&sc->rx_led);
1039         ath_unregister_led(&sc->radio_led);
1040         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1041 }
1042
1043 static void ath_init_leds(struct ath_softc *sc)
1044 {
1045         char *trigger;
1046         int ret;
1047
1048         /* Configure gpio 1 for output */
1049         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1050                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1051         /* LED off, active low */
1052         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1053
1054         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1055
1056         trigger = ieee80211_get_radio_led_name(sc->hw);
1057         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1058                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1059         ret = ath_register_led(sc, &sc->radio_led, trigger);
1060         sc->radio_led.led_type = ATH_LED_RADIO;
1061         if (ret)
1062                 goto fail;
1063
1064         trigger = ieee80211_get_assoc_led_name(sc->hw);
1065         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1066                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1067         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1068         sc->assoc_led.led_type = ATH_LED_ASSOC;
1069         if (ret)
1070                 goto fail;
1071
1072         trigger = ieee80211_get_tx_led_name(sc->hw);
1073         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1074                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1075         ret = ath_register_led(sc, &sc->tx_led, trigger);
1076         sc->tx_led.led_type = ATH_LED_TX;
1077         if (ret)
1078                 goto fail;
1079
1080         trigger = ieee80211_get_rx_led_name(sc->hw);
1081         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1082                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1083         ret = ath_register_led(sc, &sc->rx_led, trigger);
1084         sc->rx_led.led_type = ATH_LED_RX;
1085         if (ret)
1086                 goto fail;
1087
1088         return;
1089
1090 fail:
1091         ath_deinit_leds(sc);
1092 }
1093
1094 void ath_radio_enable(struct ath_softc *sc)
1095 {
1096         struct ath_hw *ah = sc->sc_ah;
1097         struct ieee80211_channel *channel = sc->hw->conf.channel;
1098         int r;
1099
1100         ath9k_ps_wakeup(sc);
1101         spin_lock_bh(&sc->sc_resetlock);
1102
1103         r = ath9k_hw_reset(ah, ah->curchan, false);
1104
1105         if (r) {
1106                 DPRINTF(sc, ATH_DBG_FATAL,
1107                         "Unable to reset channel %u (%uMhz) ",
1108                         "reset status %u\n",
1109                         channel->center_freq, r);
1110         }
1111         spin_unlock_bh(&sc->sc_resetlock);
1112
1113         ath_update_txpow(sc);
1114         if (ath_startrecv(sc) != 0) {
1115                 DPRINTF(sc, ATH_DBG_FATAL,
1116                         "Unable to restart recv logic\n");
1117                 return;
1118         }
1119
1120         if (sc->sc_flags & SC_OP_BEACONS)
1121                 ath_beacon_config(sc, NULL);    /* restart beacons */
1122
1123         /* Re-Enable  interrupts */
1124         ath9k_hw_set_interrupts(ah, sc->imask);
1125
1126         /* Enable LED */
1127         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1128                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1129         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1130
1131         ieee80211_wake_queues(sc->hw);
1132         ath9k_ps_restore(sc);
1133 }
1134
1135 void ath_radio_disable(struct ath_softc *sc)
1136 {
1137         struct ath_hw *ah = sc->sc_ah;
1138         struct ieee80211_channel *channel = sc->hw->conf.channel;
1139         int r;
1140
1141         ath9k_ps_wakeup(sc);
1142         ieee80211_stop_queues(sc->hw);
1143
1144         /* Disable LED */
1145         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1146         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1147
1148         /* Disable interrupts */
1149         ath9k_hw_set_interrupts(ah, 0);
1150
1151         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1152         ath_stoprecv(sc);               /* turn off frame recv */
1153         ath_flushrecv(sc);              /* flush recv queue */
1154
1155         spin_lock_bh(&sc->sc_resetlock);
1156         r = ath9k_hw_reset(ah, ah->curchan, false);
1157         if (r) {
1158                 DPRINTF(sc, ATH_DBG_FATAL,
1159                         "Unable to reset channel %u (%uMhz) "
1160                         "reset status %u\n",
1161                         channel->center_freq, r);
1162         }
1163         spin_unlock_bh(&sc->sc_resetlock);
1164
1165         ath9k_hw_phy_disable(ah);
1166         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1167         ath9k_ps_restore(sc);
1168 }
1169
1170 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1171
1172 /*******************/
1173 /*      Rfkill     */
1174 /*******************/
1175
1176 static bool ath_is_rfkill_set(struct ath_softc *sc)
1177 {
1178         struct ath_hw *ah = sc->sc_ah;
1179
1180         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1181                                   ah->rfkill_polarity;
1182 }
1183
1184 /* h/w rfkill poll function */
1185 static void ath_rfkill_poll(struct work_struct *work)
1186 {
1187         struct ath_softc *sc = container_of(work, struct ath_softc,
1188                                             rf_kill.rfkill_poll.work);
1189         bool radio_on;
1190
1191         if (sc->sc_flags & SC_OP_INVALID)
1192                 return;
1193
1194         radio_on = !ath_is_rfkill_set(sc);
1195
1196         /*
1197          * enable/disable radio only when there is a
1198          * state change in RF switch
1199          */
1200         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1201                 enum rfkill_state state;
1202
1203                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1204                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1205                                 : RFKILL_STATE_HARD_BLOCKED;
1206                 } else if (radio_on) {
1207                         ath_radio_enable(sc);
1208                         state = RFKILL_STATE_UNBLOCKED;
1209                 } else {
1210                         ath_radio_disable(sc);
1211                         state = RFKILL_STATE_HARD_BLOCKED;
1212                 }
1213
1214                 if (state == RFKILL_STATE_HARD_BLOCKED)
1215                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1216                 else
1217                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1218
1219                 rfkill_force_state(sc->rf_kill.rfkill, state);
1220         }
1221
1222         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1223                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1224 }
1225
1226 /* s/w rfkill handler */
1227 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1228 {
1229         struct ath_softc *sc = data;
1230
1231         switch (state) {
1232         case RFKILL_STATE_SOFT_BLOCKED:
1233                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1234                     SC_OP_RFKILL_SW_BLOCKED)))
1235                         ath_radio_disable(sc);
1236                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1237                 return 0;
1238         case RFKILL_STATE_UNBLOCKED:
1239                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1240                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1241                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1242                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1243                                         "radio as it is disabled by h/w\n");
1244                                 return -EPERM;
1245                         }
1246                         ath_radio_enable(sc);
1247                 }
1248                 return 0;
1249         default:
1250                 return -EINVAL;
1251         }
1252 }
1253
1254 /* Init s/w rfkill */
1255 static int ath_init_sw_rfkill(struct ath_softc *sc)
1256 {
1257         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1258                                              RFKILL_TYPE_WLAN);
1259         if (!sc->rf_kill.rfkill) {
1260                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1261                 return -ENOMEM;
1262         }
1263
1264         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1265                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1266         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1267         sc->rf_kill.rfkill->data = sc;
1268         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1269         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1270
1271         return 0;
1272 }
1273
1274 /* Deinitialize rfkill */
1275 static void ath_deinit_rfkill(struct ath_softc *sc)
1276 {
1277         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1278                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1279
1280         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1281                 rfkill_unregister(sc->rf_kill.rfkill);
1282                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1283                 sc->rf_kill.rfkill = NULL;
1284         }
1285 }
1286
1287 static int ath_start_rfkill_poll(struct ath_softc *sc)
1288 {
1289         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1290                 queue_delayed_work(sc->hw->workqueue,
1291                                    &sc->rf_kill.rfkill_poll, 0);
1292
1293         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1294                 if (rfkill_register(sc->rf_kill.rfkill)) {
1295                         DPRINTF(sc, ATH_DBG_FATAL,
1296                                 "Unable to register rfkill\n");
1297                         rfkill_free(sc->rf_kill.rfkill);
1298
1299                         /* Deinitialize the device */
1300                         ath_cleanup(sc);
1301                         return -EIO;
1302                 } else {
1303                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1304                 }
1305         }
1306
1307         return 0;
1308 }
1309 #endif /* CONFIG_RFKILL */
1310
1311 void ath_cleanup(struct ath_softc *sc)
1312 {
1313         ath_detach(sc);
1314         free_irq(sc->irq, sc);
1315         ath_bus_cleanup(sc);
1316         kfree(sc->sec_wiphy);
1317         ieee80211_free_hw(sc->hw);
1318 }
1319
1320 void ath_detach(struct ath_softc *sc)
1321 {
1322         struct ieee80211_hw *hw = sc->hw;
1323         int i = 0;
1324
1325         ath9k_ps_wakeup(sc);
1326
1327         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1328
1329 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1330         ath_deinit_rfkill(sc);
1331 #endif
1332         ath_deinit_leds(sc);
1333         cancel_work_sync(&sc->chan_work);
1334         cancel_delayed_work_sync(&sc->wiphy_work);
1335
1336         for (i = 0; i < sc->num_sec_wiphy; i++) {
1337                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1338                 if (aphy == NULL)
1339                         continue;
1340                 sc->sec_wiphy[i] = NULL;
1341                 ieee80211_unregister_hw(aphy->hw);
1342                 ieee80211_free_hw(aphy->hw);
1343         }
1344         ieee80211_unregister_hw(hw);
1345         ath_rx_cleanup(sc);
1346         ath_tx_cleanup(sc);
1347
1348         tasklet_kill(&sc->intr_tq);
1349         tasklet_kill(&sc->bcon_tasklet);
1350
1351         if (!(sc->sc_flags & SC_OP_INVALID))
1352                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1353
1354         /* cleanup tx queues */
1355         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1356                 if (ATH_TXQ_SETUP(sc, i))
1357                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1358
1359         ath9k_hw_detach(sc->sc_ah);
1360         ath9k_exit_debug(sc);
1361         ath9k_ps_restore(sc);
1362 }
1363
1364 static int ath_init(u16 devid, struct ath_softc *sc)
1365 {
1366         struct ath_hw *ah = NULL;
1367         int status;
1368         int error = 0, i;
1369         int csz = 0;
1370
1371         /* XXX: hardware will not be ready until ath_open() being called */
1372         sc->sc_flags |= SC_OP_INVALID;
1373
1374         if (ath9k_init_debug(sc) < 0)
1375                 printk(KERN_ERR "Unable to create debugfs files\n");
1376
1377         spin_lock_init(&sc->wiphy_lock);
1378         spin_lock_init(&sc->sc_resetlock);
1379         spin_lock_init(&sc->sc_serial_rw);
1380         mutex_init(&sc->mutex);
1381         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1382         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1383                      (unsigned long)sc);
1384
1385         /*
1386          * Cache line size is used to size and align various
1387          * structures used to communicate with the hardware.
1388          */
1389         ath_read_cachesize(sc, &csz);
1390         /* XXX assert csz is non-zero */
1391         sc->cachelsz = csz << 2;        /* convert to bytes */
1392
1393         ah = ath9k_hw_attach(devid, sc, &status);
1394         if (ah == NULL) {
1395                 DPRINTF(sc, ATH_DBG_FATAL,
1396                         "Unable to attach hardware; HAL status %d\n", status);
1397                 error = -ENXIO;
1398                 goto bad;
1399         }
1400         sc->sc_ah = ah;
1401
1402         /* Get the hardware key cache size. */
1403         sc->keymax = ah->caps.keycache_size;
1404         if (sc->keymax > ATH_KEYMAX) {
1405                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1406                         "Warning, using only %u entries in %u key cache\n",
1407                         ATH_KEYMAX, sc->keymax);
1408                 sc->keymax = ATH_KEYMAX;
1409         }
1410
1411         /*
1412          * Reset the key cache since some parts do not
1413          * reset the contents on initial power up.
1414          */
1415         for (i = 0; i < sc->keymax; i++)
1416                 ath9k_hw_keyreset(ah, (u16) i);
1417
1418         if (ath9k_regd_init(sc->sc_ah))
1419                 goto bad;
1420
1421         /* default to MONITOR mode */
1422         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1423
1424         /* Setup rate tables */
1425
1426         ath_rate_attach(sc);
1427         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1428         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1429
1430         /*
1431          * Allocate hardware transmit queues: one queue for
1432          * beacon frames and one data queue for each QoS
1433          * priority.  Note that the hal handles reseting
1434          * these queues at the needed time.
1435          */
1436         sc->beacon.beaconq = ath_beaconq_setup(ah);
1437         if (sc->beacon.beaconq == -1) {
1438                 DPRINTF(sc, ATH_DBG_FATAL,
1439                         "Unable to setup a beacon xmit queue\n");
1440                 error = -EIO;
1441                 goto bad2;
1442         }
1443         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1444         if (sc->beacon.cabq == NULL) {
1445                 DPRINTF(sc, ATH_DBG_FATAL,
1446                         "Unable to setup CAB xmit queue\n");
1447                 error = -EIO;
1448                 goto bad2;
1449         }
1450
1451         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1452         ath_cabq_update(sc);
1453
1454         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1455                 sc->tx.hwq_map[i] = -1;
1456
1457         /* Setup data queues */
1458         /* NB: ensure BK queue is the lowest priority h/w queue */
1459         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1460                 DPRINTF(sc, ATH_DBG_FATAL,
1461                         "Unable to setup xmit queue for BK traffic\n");
1462                 error = -EIO;
1463                 goto bad2;
1464         }
1465
1466         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1467                 DPRINTF(sc, ATH_DBG_FATAL,
1468                         "Unable to setup xmit queue for BE traffic\n");
1469                 error = -EIO;
1470                 goto bad2;
1471         }
1472         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1473                 DPRINTF(sc, ATH_DBG_FATAL,
1474                         "Unable to setup xmit queue for VI traffic\n");
1475                 error = -EIO;
1476                 goto bad2;
1477         }
1478         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1479                 DPRINTF(sc, ATH_DBG_FATAL,
1480                         "Unable to setup xmit queue for VO traffic\n");
1481                 error = -EIO;
1482                 goto bad2;
1483         }
1484
1485         /* Initializes the noise floor to a reasonable default value.
1486          * Later on this will be updated during ANI processing. */
1487
1488         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1489         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1490
1491         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1492                                    ATH9K_CIPHER_TKIP, NULL)) {
1493                 /*
1494                  * Whether we should enable h/w TKIP MIC.
1495                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1496                  * report WMM capable, so it's always safe to turn on
1497                  * TKIP MIC in this case.
1498                  */
1499                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1500                                        0, 1, NULL);
1501         }
1502
1503         /*
1504          * Check whether the separate key cache entries
1505          * are required to handle both tx+rx MIC keys.
1506          * With split mic keys the number of stations is limited
1507          * to 27 otherwise 59.
1508          */
1509         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1510                                    ATH9K_CIPHER_TKIP, NULL)
1511             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1512                                       ATH9K_CIPHER_MIC, NULL)
1513             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1514                                       0, NULL))
1515                 sc->splitmic = 1;
1516
1517         /* turn on mcast key search if possible */
1518         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1519                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1520                                              1, NULL);
1521
1522         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1523
1524         /* 11n Capabilities */
1525         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1526                 sc->sc_flags |= SC_OP_TXAGGR;
1527                 sc->sc_flags |= SC_OP_RXAGGR;
1528         }
1529
1530         sc->tx_chainmask = ah->caps.tx_chainmask;
1531         sc->rx_chainmask = ah->caps.rx_chainmask;
1532
1533         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1534         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1535
1536         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1537                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1538
1539         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1540
1541         /* initialize beacon slots */
1542         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1543                 sc->beacon.bslot[i] = NULL;
1544                 sc->beacon.bslot_aphy[i] = NULL;
1545         }
1546
1547         /* save MISC configurations */
1548         sc->config.swBeaconProcess = 1;
1549
1550         /* setup channels and rates */
1551
1552         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1553         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1554                 sc->rates[IEEE80211_BAND_2GHZ];
1555         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1556         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1557                 ARRAY_SIZE(ath9k_2ghz_chantable);
1558
1559         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1560                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1561                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1562                         sc->rates[IEEE80211_BAND_5GHZ];
1563                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1564                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1565                         ARRAY_SIZE(ath9k_5ghz_chantable);
1566         }
1567
1568         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1569                 ath9k_hw_btcoex_enable(sc->sc_ah);
1570
1571         return 0;
1572 bad2:
1573         /* cleanup tx queues */
1574         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1575                 if (ATH_TXQ_SETUP(sc, i))
1576                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1577 bad:
1578         if (ah)
1579                 ath9k_hw_detach(ah);
1580         ath9k_exit_debug(sc);
1581
1582         return error;
1583 }
1584
1585 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1586 {
1587         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1588                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1589                 IEEE80211_HW_SIGNAL_DBM |
1590                 IEEE80211_HW_AMPDU_AGGREGATION |
1591                 IEEE80211_HW_SUPPORTS_PS |
1592                 IEEE80211_HW_PS_NULLFUNC_STACK |
1593                 IEEE80211_HW_SPECTRUM_MGMT;
1594
1595         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1596                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1597
1598         hw->wiphy->interface_modes =
1599                 BIT(NL80211_IFTYPE_AP) |
1600                 BIT(NL80211_IFTYPE_STATION) |
1601                 BIT(NL80211_IFTYPE_ADHOC) |
1602                 BIT(NL80211_IFTYPE_MESH_POINT);
1603
1604         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1605         hw->wiphy->strict_regulatory = true;
1606
1607         hw->queues = 4;
1608         hw->max_rates = 4;
1609         hw->channel_change_time = 5000;
1610         hw->max_listen_interval = 10;
1611         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1612         hw->sta_data_size = sizeof(struct ath_node);
1613         hw->vif_data_size = sizeof(struct ath_vif);
1614
1615         hw->rate_control_algorithm = "ath9k_rate_control";
1616
1617         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1618                 &sc->sbands[IEEE80211_BAND_2GHZ];
1619         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1620                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1621                         &sc->sbands[IEEE80211_BAND_5GHZ];
1622 }
1623
1624 int ath_attach(u16 devid, struct ath_softc *sc)
1625 {
1626         struct ieee80211_hw *hw = sc->hw;
1627         const struct ieee80211_regdomain *regd;
1628         int error = 0, i;
1629
1630         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1631
1632         error = ath_init(devid, sc);
1633         if (error != 0)
1634                 return error;
1635
1636         /* get mac address from hardware and set in mac80211 */
1637
1638         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1639
1640         ath_set_hw_capab(sc, hw);
1641
1642         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1643                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1644                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1645                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1646         }
1647
1648         /* initialize tx/rx engine */
1649         error = ath_tx_init(sc, ATH_TXBUF);
1650         if (error != 0)
1651                 goto error_attach;
1652
1653         error = ath_rx_init(sc, ATH_RXBUF);
1654         if (error != 0)
1655                 goto error_attach;
1656
1657 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1658         /* Initialze h/w Rfkill */
1659         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1660                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1661
1662         /* Initialize s/w rfkill */
1663         error = ath_init_sw_rfkill(sc);
1664         if (error)
1665                 goto error_attach;
1666 #endif
1667
1668         if (ath9k_is_world_regd(sc->sc_ah)) {
1669                 /* Anything applied here (prior to wiphy registration) gets
1670                  * saved on the wiphy orig_* parameters */
1671                 regd = ath9k_world_regdomain(sc->sc_ah);
1672                 hw->wiphy->custom_regulatory = true;
1673                 hw->wiphy->strict_regulatory = false;
1674         } else {
1675                 /* This gets applied in the case of the absense of CRDA,
1676                  * it's our own custom world regulatory domain, similar to
1677                  * cfg80211's but we enable passive scanning */
1678                 regd = ath9k_default_world_regdomain();
1679         }
1680         wiphy_apply_custom_regulatory(hw->wiphy, regd);
1681         ath9k_reg_apply_radar_flags(hw->wiphy);
1682         ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
1683
1684         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1685         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1686         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1687
1688         error = ieee80211_register_hw(hw);
1689
1690         if (!ath9k_is_world_regd(sc->sc_ah)) {
1691                 error = regulatory_hint(hw->wiphy,
1692                         sc->sc_ah->regulatory.alpha2);
1693                 if (error)
1694                         goto error_attach;
1695         }
1696
1697         /* Initialize LED control */
1698         ath_init_leds(sc);
1699
1700
1701         return 0;
1702
1703 error_attach:
1704         /* cleanup tx queues */
1705         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1706                 if (ATH_TXQ_SETUP(sc, i))
1707                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1708
1709         ath9k_hw_detach(sc->sc_ah);
1710         ath9k_exit_debug(sc);
1711
1712         return error;
1713 }
1714
1715 int ath_reset(struct ath_softc *sc, bool retry_tx)
1716 {
1717         struct ath_hw *ah = sc->sc_ah;
1718         struct ieee80211_hw *hw = sc->hw;
1719         int r;
1720
1721         ath9k_hw_set_interrupts(ah, 0);
1722         ath_drain_all_txq(sc, retry_tx);
1723         ath_stoprecv(sc);
1724         ath_flushrecv(sc);
1725
1726         spin_lock_bh(&sc->sc_resetlock);
1727         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1728         if (r)
1729                 DPRINTF(sc, ATH_DBG_FATAL,
1730                         "Unable to reset hardware; reset status %u\n", r);
1731         spin_unlock_bh(&sc->sc_resetlock);
1732
1733         if (ath_startrecv(sc) != 0)
1734                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1735
1736         /*
1737          * We may be doing a reset in response to a request
1738          * that changes the channel so update any state that
1739          * might change as a result.
1740          */
1741         ath_cache_conf_rate(sc, &hw->conf);
1742
1743         ath_update_txpow(sc);
1744
1745         if (sc->sc_flags & SC_OP_BEACONS)
1746                 ath_beacon_config(sc, NULL);    /* restart beacons */
1747
1748         ath9k_hw_set_interrupts(ah, sc->imask);
1749
1750         if (retry_tx) {
1751                 int i;
1752                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1753                         if (ATH_TXQ_SETUP(sc, i)) {
1754                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1755                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1756                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1757                         }
1758                 }
1759         }
1760
1761         return r;
1762 }
1763
1764 /*
1765  *  This function will allocate both the DMA descriptor structure, and the
1766  *  buffers it contains.  These are used to contain the descriptors used
1767  *  by the system.
1768 */
1769 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1770                       struct list_head *head, const char *name,
1771                       int nbuf, int ndesc)
1772 {
1773 #define DS2PHYS(_dd, _ds)                                               \
1774         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1775 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1776 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1777
1778         struct ath_desc *ds;
1779         struct ath_buf *bf;
1780         int i, bsize, error;
1781
1782         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1783                 name, nbuf, ndesc);
1784
1785         INIT_LIST_HEAD(head);
1786         /* ath_desc must be a multiple of DWORDs */
1787         if ((sizeof(struct ath_desc) % 4) != 0) {
1788                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1789                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1790                 error = -ENOMEM;
1791                 goto fail;
1792         }
1793
1794         dd->dd_name = name;
1795         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1796
1797         /*
1798          * Need additional DMA memory because we can't use
1799          * descriptors that cross the 4K page boundary. Assume
1800          * one skipped descriptor per 4K page.
1801          */
1802         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1803                 u32 ndesc_skipped =
1804                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1805                 u32 dma_len;
1806
1807                 while (ndesc_skipped) {
1808                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1809                         dd->dd_desc_len += dma_len;
1810
1811                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1812                 };
1813         }
1814
1815         /* allocate descriptors */
1816         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1817                                          &dd->dd_desc_paddr, GFP_KERNEL);
1818         if (dd->dd_desc == NULL) {
1819                 error = -ENOMEM;
1820                 goto fail;
1821         }
1822         ds = dd->dd_desc;
1823         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1824                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1825                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1826
1827         /* allocate buffers */
1828         bsize = sizeof(struct ath_buf) * nbuf;
1829         bf = kzalloc(bsize, GFP_KERNEL);
1830         if (bf == NULL) {
1831                 error = -ENOMEM;
1832                 goto fail2;
1833         }
1834         dd->dd_bufptr = bf;
1835
1836         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1837                 bf->bf_desc = ds;
1838                 bf->bf_daddr = DS2PHYS(dd, ds);
1839
1840                 if (!(sc->sc_ah->caps.hw_caps &
1841                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1842                         /*
1843                          * Skip descriptor addresses which can cause 4KB
1844                          * boundary crossing (addr + length) with a 32 dword
1845                          * descriptor fetch.
1846                          */
1847                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1848                                 ASSERT((caddr_t) bf->bf_desc <
1849                                        ((caddr_t) dd->dd_desc +
1850                                         dd->dd_desc_len));
1851
1852                                 ds += ndesc;
1853                                 bf->bf_desc = ds;
1854                                 bf->bf_daddr = DS2PHYS(dd, ds);
1855                         }
1856                 }
1857                 list_add_tail(&bf->list, head);
1858         }
1859         return 0;
1860 fail2:
1861         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1862                           dd->dd_desc_paddr);
1863 fail:
1864         memset(dd, 0, sizeof(*dd));
1865         return error;
1866 #undef ATH_DESC_4KB_BOUND_CHECK
1867 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1868 #undef DS2PHYS
1869 }
1870
1871 void ath_descdma_cleanup(struct ath_softc *sc,
1872                          struct ath_descdma *dd,
1873                          struct list_head *head)
1874 {
1875         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1876                           dd->dd_desc_paddr);
1877
1878         INIT_LIST_HEAD(head);
1879         kfree(dd->dd_bufptr);
1880         memset(dd, 0, sizeof(*dd));
1881 }
1882
1883 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1884 {
1885         int qnum;
1886
1887         switch (queue) {
1888         case 0:
1889                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1890                 break;
1891         case 1:
1892                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1893                 break;
1894         case 2:
1895                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1896                 break;
1897         case 3:
1898                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1899                 break;
1900         default:
1901                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1902                 break;
1903         }
1904
1905         return qnum;
1906 }
1907
1908 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1909 {
1910         int qnum;
1911
1912         switch (queue) {
1913         case ATH9K_WME_AC_VO:
1914                 qnum = 0;
1915                 break;
1916         case ATH9K_WME_AC_VI:
1917                 qnum = 1;
1918                 break;
1919         case ATH9K_WME_AC_BE:
1920                 qnum = 2;
1921                 break;
1922         case ATH9K_WME_AC_BK:
1923                 qnum = 3;
1924                 break;
1925         default:
1926                 qnum = -1;
1927                 break;
1928         }
1929
1930         return qnum;
1931 }
1932
1933 /* XXX: Remove me once we don't depend on ath9k_channel for all
1934  * this redundant data */
1935 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1936                            struct ath9k_channel *ichan)
1937 {
1938         struct ieee80211_channel *chan = hw->conf.channel;
1939         struct ieee80211_conf *conf = &hw->conf;
1940
1941         ichan->channel = chan->center_freq;
1942         ichan->chan = chan;
1943
1944         if (chan->band == IEEE80211_BAND_2GHZ) {
1945                 ichan->chanmode = CHANNEL_G;
1946                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1947         } else {
1948                 ichan->chanmode = CHANNEL_A;
1949                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1950         }
1951
1952         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1953
1954         if (conf_is_ht(conf)) {
1955                 if (conf_is_ht40(conf))
1956                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1957
1958                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1959                                             conf->channel_type);
1960         }
1961 }
1962
1963 /**********************/
1964 /* mac80211 callbacks */
1965 /**********************/
1966
1967 static int ath9k_start(struct ieee80211_hw *hw)
1968 {
1969         struct ath_wiphy *aphy = hw->priv;
1970         struct ath_softc *sc = aphy->sc;
1971         struct ieee80211_channel *curchan = hw->conf.channel;
1972         struct ath9k_channel *init_channel;
1973         int r, pos;
1974
1975         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1976                 "initial channel: %d MHz\n", curchan->center_freq);
1977
1978         mutex_lock(&sc->mutex);
1979
1980         if (ath9k_wiphy_started(sc)) {
1981                 if (sc->chan_idx == curchan->hw_value) {
1982                         /*
1983                          * Already on the operational channel, the new wiphy
1984                          * can be marked active.
1985                          */
1986                         aphy->state = ATH_WIPHY_ACTIVE;
1987                         ieee80211_wake_queues(hw);
1988                 } else {
1989                         /*
1990                          * Another wiphy is on another channel, start the new
1991                          * wiphy in paused state.
1992                          */
1993                         aphy->state = ATH_WIPHY_PAUSED;
1994                         ieee80211_stop_queues(hw);
1995                 }
1996                 mutex_unlock(&sc->mutex);
1997                 return 0;
1998         }
1999         aphy->state = ATH_WIPHY_ACTIVE;
2000
2001         /* setup initial channel */
2002
2003         pos = curchan->hw_value;
2004
2005         sc->chan_idx = pos;
2006         init_channel = &sc->sc_ah->channels[pos];
2007         ath9k_update_ichannel(sc, hw, init_channel);
2008
2009         /* Reset SERDES registers */
2010         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2011
2012         /*
2013          * The basic interface to setting the hardware in a good
2014          * state is ``reset''.  On return the hardware is known to
2015          * be powered up and with interrupts disabled.  This must
2016          * be followed by initialization of the appropriate bits
2017          * and then setup of the interrupt mask.
2018          */
2019         spin_lock_bh(&sc->sc_resetlock);
2020         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2021         if (r) {
2022                 DPRINTF(sc, ATH_DBG_FATAL,
2023                         "Unable to reset hardware; reset status %u "
2024                         "(freq %u MHz)\n", r,
2025                         curchan->center_freq);
2026                 spin_unlock_bh(&sc->sc_resetlock);
2027                 goto mutex_unlock;
2028         }
2029         spin_unlock_bh(&sc->sc_resetlock);
2030
2031         /*
2032          * This is needed only to setup initial state
2033          * but it's best done after a reset.
2034          */
2035         ath_update_txpow(sc);
2036
2037         /*
2038          * Setup the hardware after reset:
2039          * The receive engine is set going.
2040          * Frame transmit is handled entirely
2041          * in the frame output path; there's nothing to do
2042          * here except setup the interrupt mask.
2043          */
2044         if (ath_startrecv(sc) != 0) {
2045                 DPRINTF(sc, ATH_DBG_FATAL,
2046                         "Unable to start recv logic\n");
2047                 r = -EIO;
2048                 goto mutex_unlock;
2049         }
2050
2051         /* Setup our intr mask. */
2052         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2053                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2054                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2055
2056         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2057                 sc->imask |= ATH9K_INT_GTT;
2058
2059         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2060                 sc->imask |= ATH9K_INT_CST;
2061
2062         ath_cache_conf_rate(sc, &hw->conf);
2063
2064         sc->sc_flags &= ~SC_OP_INVALID;
2065
2066         /* Disable BMISS interrupt when we're not associated */
2067         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2068         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2069
2070         ieee80211_wake_queues(hw);
2071
2072 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2073         r = ath_start_rfkill_poll(sc);
2074 #endif
2075
2076 mutex_unlock:
2077         mutex_unlock(&sc->mutex);
2078
2079         return r;
2080 }
2081
2082 static int ath9k_tx(struct ieee80211_hw *hw,
2083                     struct sk_buff *skb)
2084 {
2085         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2086         struct ath_wiphy *aphy = hw->priv;
2087         struct ath_softc *sc = aphy->sc;
2088         struct ath_tx_control txctl;
2089         int hdrlen, padsize;
2090
2091         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2092                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2093                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2094                 goto exit;
2095         }
2096
2097         memset(&txctl, 0, sizeof(struct ath_tx_control));
2098
2099         /*
2100          * As a temporary workaround, assign seq# here; this will likely need
2101          * to be cleaned up to work better with Beacon transmission and virtual
2102          * BSSes.
2103          */
2104         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2105                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2106                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2107                         sc->tx.seq_no += 0x10;
2108                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2109                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2110         }
2111
2112         /* Add the padding after the header if this is not already done */
2113         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2114         if (hdrlen & 3) {
2115                 padsize = hdrlen % 4;
2116                 if (skb_headroom(skb) < padsize)
2117                         return -1;
2118                 skb_push(skb, padsize);
2119                 memmove(skb->data, skb->data + padsize, hdrlen);
2120         }
2121
2122         /* Check if a tx queue is available */
2123
2124         txctl.txq = ath_test_get_txq(sc, skb);
2125         if (!txctl.txq)
2126                 goto exit;
2127
2128         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2129
2130         if (ath_tx_start(hw, skb, &txctl) != 0) {
2131                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2132                 goto exit;
2133         }
2134
2135         return 0;
2136 exit:
2137         dev_kfree_skb_any(skb);
2138         return 0;
2139 }
2140
2141 static void ath9k_stop(struct ieee80211_hw *hw)
2142 {
2143         struct ath_wiphy *aphy = hw->priv;
2144         struct ath_softc *sc = aphy->sc;
2145
2146         aphy->state = ATH_WIPHY_INACTIVE;
2147
2148         if (sc->sc_flags & SC_OP_INVALID) {
2149                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2150                 return;
2151         }
2152
2153         mutex_lock(&sc->mutex);
2154
2155         ieee80211_stop_queues(hw);
2156
2157         if (ath9k_wiphy_started(sc)) {
2158                 mutex_unlock(&sc->mutex);
2159                 return; /* another wiphy still in use */
2160         }
2161
2162         /* make sure h/w will not generate any interrupt
2163          * before setting the invalid flag. */
2164         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2165
2166         if (!(sc->sc_flags & SC_OP_INVALID)) {
2167                 ath_drain_all_txq(sc, false);
2168                 ath_stoprecv(sc);
2169                 ath9k_hw_phy_disable(sc->sc_ah);
2170         } else
2171                 sc->rx.rxlink = NULL;
2172
2173 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2174         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2175                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2176 #endif
2177         /* disable HAL and put h/w to sleep */
2178         ath9k_hw_disable(sc->sc_ah);
2179         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2180
2181         sc->sc_flags |= SC_OP_INVALID;
2182
2183         mutex_unlock(&sc->mutex);
2184
2185         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2186 }
2187
2188 static int ath9k_add_interface(struct ieee80211_hw *hw,
2189                                struct ieee80211_if_init_conf *conf)
2190 {
2191         struct ath_wiphy *aphy = hw->priv;
2192         struct ath_softc *sc = aphy->sc;
2193         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2194         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2195         int ret = 0;
2196
2197         mutex_lock(&sc->mutex);
2198
2199         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2200             sc->nvifs > 0) {
2201                 ret = -ENOBUFS;
2202                 goto out;
2203         }
2204
2205         switch (conf->type) {
2206         case NL80211_IFTYPE_STATION:
2207                 ic_opmode = NL80211_IFTYPE_STATION;
2208                 break;
2209         case NL80211_IFTYPE_ADHOC:
2210         case NL80211_IFTYPE_AP:
2211         case NL80211_IFTYPE_MESH_POINT:
2212                 if (sc->nbcnvifs >= ATH_BCBUF) {
2213                         ret = -ENOBUFS;
2214                         goto out;
2215                 }
2216                 ic_opmode = conf->type;
2217                 break;
2218         default:
2219                 DPRINTF(sc, ATH_DBG_FATAL,
2220                         "Interface type %d not yet supported\n", conf->type);
2221                 ret = -EOPNOTSUPP;
2222                 goto out;
2223         }
2224
2225         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2226
2227         /* Set the VIF opmode */
2228         avp->av_opmode = ic_opmode;
2229         avp->av_bslot = -1;
2230
2231         sc->nvifs++;
2232
2233         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2234                 ath9k_set_bssid_mask(hw);
2235
2236         if (sc->nvifs > 1)
2237                 goto out; /* skip global settings for secondary vif */
2238
2239         if (ic_opmode == NL80211_IFTYPE_AP) {
2240                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2241                 sc->sc_flags |= SC_OP_TSF_RESET;
2242         }
2243
2244         /* Set the device opmode */
2245         sc->sc_ah->opmode = ic_opmode;
2246
2247         /*
2248          * Enable MIB interrupts when there are hardware phy counters.
2249          * Note we only do this (at the moment) for station mode.
2250          */
2251         if ((conf->type == NL80211_IFTYPE_STATION) ||
2252             (conf->type == NL80211_IFTYPE_ADHOC) ||
2253             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2254                 if (ath9k_hw_phycounters(sc->sc_ah))
2255                         sc->imask |= ATH9K_INT_MIB;
2256                 sc->imask |= ATH9K_INT_TSFOOR;
2257         }
2258
2259         /*
2260          * Some hardware processes the TIM IE and fires an
2261          * interrupt when the TIM bit is set.  For hardware
2262          * that does, if not overridden by configuration,
2263          * enable the TIM interrupt when operating as station.
2264          */
2265         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2266             (conf->type == NL80211_IFTYPE_STATION) &&
2267             !sc->config.swBeaconProcess)
2268                 sc->imask |= ATH9K_INT_TIM;
2269
2270         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2271
2272         if (conf->type == NL80211_IFTYPE_AP) {
2273                 /* TODO: is this a suitable place to start ANI for AP mode? */
2274                 /* Start ANI */
2275                 mod_timer(&sc->ani.timer,
2276                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2277         }
2278
2279 out:
2280         mutex_unlock(&sc->mutex);
2281         return ret;
2282 }
2283
2284 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2285                                    struct ieee80211_if_init_conf *conf)
2286 {
2287         struct ath_wiphy *aphy = hw->priv;
2288         struct ath_softc *sc = aphy->sc;
2289         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2290         int i;
2291
2292         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2293
2294         mutex_lock(&sc->mutex);
2295
2296         /* Stop ANI */
2297         del_timer_sync(&sc->ani.timer);
2298
2299         /* Reclaim beacon resources */
2300         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2301             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2302             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2303                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2304                 ath_beacon_return(sc, avp);
2305         }
2306
2307         sc->sc_flags &= ~SC_OP_BEACONS;
2308
2309         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2310                 if (sc->beacon.bslot[i] == conf->vif) {
2311                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2312                                "slot\n", __func__);
2313                         sc->beacon.bslot[i] = NULL;
2314                         sc->beacon.bslot_aphy[i] = NULL;
2315                 }
2316         }
2317
2318         sc->nvifs--;
2319
2320         mutex_unlock(&sc->mutex);
2321 }
2322
2323 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2324 {
2325         struct ath_wiphy *aphy = hw->priv;
2326         struct ath_softc *sc = aphy->sc;
2327         struct ieee80211_conf *conf = &hw->conf;
2328         struct ath_hw *ah = sc->sc_ah;
2329
2330         mutex_lock(&sc->mutex);
2331
2332         if (changed & IEEE80211_CONF_CHANGE_PS) {
2333                 if (conf->flags & IEEE80211_CONF_PS) {
2334                         if (!(ah->caps.hw_caps &
2335                               ATH9K_HW_CAP_AUTOSLEEP)) {
2336                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2337                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2338                                         ath9k_hw_set_interrupts(sc->sc_ah,
2339                                                         sc->imask);
2340                                 }
2341                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2342                         }
2343                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2344                 } else {
2345                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2346                         if (!(ah->caps.hw_caps &
2347                               ATH9K_HW_CAP_AUTOSLEEP)) {
2348                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2349                                 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2350                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2351                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2352                                         ath9k_hw_set_interrupts(sc->sc_ah,
2353                                                         sc->imask);
2354                                 }
2355                         }
2356                 }
2357         }
2358
2359         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2360                 struct ieee80211_channel *curchan = hw->conf.channel;
2361                 int pos = curchan->hw_value;
2362
2363                 aphy->chan_idx = pos;
2364                 aphy->chan_is_ht = conf_is_ht(conf);
2365
2366                 if (aphy->state == ATH_WIPHY_SCAN ||
2367                     aphy->state == ATH_WIPHY_ACTIVE)
2368                         ath9k_wiphy_pause_all_forced(sc, aphy);
2369                 else {
2370                         /*
2371                          * Do not change operational channel based on a paused
2372                          * wiphy changes.
2373                          */
2374                         goto skip_chan_change;
2375                 }
2376
2377                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2378                         curchan->center_freq);
2379
2380                 /* XXX: remove me eventualy */
2381                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2382
2383                 ath_update_chainmask(sc, conf_is_ht(conf));
2384
2385                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2386                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2387                         mutex_unlock(&sc->mutex);
2388                         return -EINVAL;
2389                 }
2390         }
2391
2392 skip_chan_change:
2393         if (changed & IEEE80211_CONF_CHANGE_POWER)
2394                 sc->config.txpowlimit = 2 * conf->power_level;
2395
2396         /*
2397          * The HW TSF has to be reset when the beacon interval changes.
2398          * We set the flag here, and ath_beacon_config_ap() would take this
2399          * into account when it gets called through the subsequent
2400          * config_interface() call - with IFCC_BEACON in the changed field.
2401          */
2402
2403         if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2404                 sc->sc_flags |= SC_OP_TSF_RESET;
2405
2406         mutex_unlock(&sc->mutex);
2407
2408         return 0;
2409 }
2410
2411 static int ath9k_config_interface(struct ieee80211_hw *hw,
2412                                   struct ieee80211_vif *vif,
2413                                   struct ieee80211_if_conf *conf)
2414 {
2415         struct ath_wiphy *aphy = hw->priv;
2416         struct ath_softc *sc = aphy->sc;
2417         struct ath_hw *ah = sc->sc_ah;
2418         struct ath_vif *avp = (void *)vif->drv_priv;
2419         u32 rfilt = 0;
2420         int error, i;
2421
2422         mutex_lock(&sc->mutex);
2423
2424         /* TODO: Need to decide which hw opmode to use for multi-interface
2425          * cases */
2426         if (vif->type == NL80211_IFTYPE_AP &&
2427             ah->opmode != NL80211_IFTYPE_AP) {
2428                 ah->opmode = NL80211_IFTYPE_STATION;
2429                 ath9k_hw_setopmode(ah);
2430                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2431                 sc->curaid = 0;
2432                 ath9k_hw_write_associd(sc);
2433                 /* Request full reset to get hw opmode changed properly */
2434                 sc->sc_flags |= SC_OP_FULL_RESET;
2435         }
2436
2437         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2438             !is_zero_ether_addr(conf->bssid)) {
2439                 switch (vif->type) {
2440                 case NL80211_IFTYPE_STATION:
2441                 case NL80211_IFTYPE_ADHOC:
2442                 case NL80211_IFTYPE_MESH_POINT:
2443                         /* Set BSSID */
2444                         memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2445                         memcpy(avp->bssid, conf->bssid, ETH_ALEN);
2446                         sc->curaid = 0;
2447                         ath9k_hw_write_associd(sc);
2448
2449                         /* Set aggregation protection mode parameters */
2450                         sc->config.ath_aggr_prot = 0;
2451
2452                         DPRINTF(sc, ATH_DBG_CONFIG,
2453                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2454                                 rfilt, sc->curbssid, sc->curaid);
2455
2456                         /* need to reconfigure the beacon */
2457                         sc->sc_flags &= ~SC_OP_BEACONS ;
2458
2459                         break;
2460                 default:
2461                         break;
2462                 }
2463         }
2464
2465         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2466             (vif->type == NL80211_IFTYPE_AP) ||
2467             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2468                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2469                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2470                      conf->enable_beacon)) {
2471                         /*
2472                          * Allocate and setup the beacon frame.
2473                          *
2474                          * Stop any previous beacon DMA.  This may be
2475                          * necessary, for example, when an ibss merge
2476                          * causes reconfiguration; we may be called
2477                          * with beacon transmission active.
2478                          */
2479                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2480
2481                         error = ath_beacon_alloc(aphy, vif);
2482                         if (error != 0) {
2483                                 mutex_unlock(&sc->mutex);
2484                                 return error;
2485                         }
2486
2487                         ath_beacon_config(sc, vif);
2488                 }
2489         }
2490
2491         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2492         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2493                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2494                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2495                                 ath9k_hw_keysetmac(sc->sc_ah,
2496                                                    (u16)i,
2497                                                    sc->curbssid);
2498         }
2499
2500         /* Only legacy IBSS for now */
2501         if (vif->type == NL80211_IFTYPE_ADHOC)
2502                 ath_update_chainmask(sc, 0);
2503
2504         mutex_unlock(&sc->mutex);
2505
2506         return 0;
2507 }
2508
2509 #define SUPPORTED_FILTERS                       \
2510         (FIF_PROMISC_IN_BSS |                   \
2511         FIF_ALLMULTI |                          \
2512         FIF_CONTROL |                           \
2513         FIF_OTHER_BSS |                         \
2514         FIF_BCN_PRBRESP_PROMISC |               \
2515         FIF_FCSFAIL)
2516
2517 /* FIXME: sc->sc_full_reset ? */
2518 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2519                                    unsigned int changed_flags,
2520                                    unsigned int *total_flags,
2521                                    int mc_count,
2522                                    struct dev_mc_list *mclist)
2523 {
2524         struct ath_wiphy *aphy = hw->priv;
2525         struct ath_softc *sc = aphy->sc;
2526         u32 rfilt;
2527
2528         changed_flags &= SUPPORTED_FILTERS;
2529         *total_flags &= SUPPORTED_FILTERS;
2530
2531         sc->rx.rxfilter = *total_flags;
2532         rfilt = ath_calcrxfilter(sc);
2533         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2534
2535         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2536 }
2537
2538 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2539                              struct ieee80211_vif *vif,
2540                              enum sta_notify_cmd cmd,
2541                              struct ieee80211_sta *sta)
2542 {
2543         struct ath_wiphy *aphy = hw->priv;
2544         struct ath_softc *sc = aphy->sc;
2545
2546         switch (cmd) {
2547         case STA_NOTIFY_ADD:
2548                 ath_node_attach(sc, sta);
2549                 break;
2550         case STA_NOTIFY_REMOVE:
2551                 ath_node_detach(sc, sta);
2552                 break;
2553         default:
2554                 break;
2555         }
2556 }
2557
2558 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2559                          const struct ieee80211_tx_queue_params *params)
2560 {
2561         struct ath_wiphy *aphy = hw->priv;
2562         struct ath_softc *sc = aphy->sc;
2563         struct ath9k_tx_queue_info qi;
2564         int ret = 0, qnum;
2565
2566         if (queue >= WME_NUM_AC)
2567                 return 0;
2568
2569         mutex_lock(&sc->mutex);
2570
2571         qi.tqi_aifs = params->aifs;
2572         qi.tqi_cwmin = params->cw_min;
2573         qi.tqi_cwmax = params->cw_max;
2574         qi.tqi_burstTime = params->txop;
2575         qnum = ath_get_hal_qnum(queue, sc);
2576
2577         DPRINTF(sc, ATH_DBG_CONFIG,
2578                 "Configure tx [queue/halq] [%d/%d],  "
2579                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2580                 queue, qnum, params->aifs, params->cw_min,
2581                 params->cw_max, params->txop);
2582
2583         ret = ath_txq_update(sc, qnum, &qi);
2584         if (ret)
2585                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2586
2587         mutex_unlock(&sc->mutex);
2588
2589         return ret;
2590 }
2591
2592 static int ath9k_set_key(struct ieee80211_hw *hw,
2593                          enum set_key_cmd cmd,
2594                          struct ieee80211_vif *vif,
2595                          struct ieee80211_sta *sta,
2596                          struct ieee80211_key_conf *key)
2597 {
2598         struct ath_wiphy *aphy = hw->priv;
2599         struct ath_softc *sc = aphy->sc;
2600         int ret = 0;
2601
2602         if (modparam_nohwcrypt)
2603                 return -ENOSPC;
2604
2605         mutex_lock(&sc->mutex);
2606         ath9k_ps_wakeup(sc);
2607         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2608
2609         switch (cmd) {
2610         case SET_KEY:
2611                 ret = ath_key_config(sc, vif, sta, key);
2612                 if (ret >= 0) {
2613                         key->hw_key_idx = ret;
2614                         /* push IV and Michael MIC generation to stack */
2615                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2616                         if (key->alg == ALG_TKIP)
2617                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2618                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2619                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2620                         ret = 0;
2621                 }
2622                 break;
2623         case DISABLE_KEY:
2624                 ath_key_delete(sc, key);
2625                 break;
2626         default:
2627                 ret = -EINVAL;
2628         }
2629
2630         ath9k_ps_restore(sc);
2631         mutex_unlock(&sc->mutex);
2632
2633         return ret;
2634 }
2635
2636 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2637                                    struct ieee80211_vif *vif,
2638                                    struct ieee80211_bss_conf *bss_conf,
2639                                    u32 changed)
2640 {
2641         struct ath_wiphy *aphy = hw->priv;
2642         struct ath_softc *sc = aphy->sc;
2643
2644         mutex_lock(&sc->mutex);
2645
2646         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2647                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2648                         bss_conf->use_short_preamble);
2649                 if (bss_conf->use_short_preamble)
2650                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2651                 else
2652                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2653         }
2654
2655         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2656                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2657                         bss_conf->use_cts_prot);
2658                 if (bss_conf->use_cts_prot &&
2659                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2660                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2661                 else
2662                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2663         }
2664
2665         if (changed & BSS_CHANGED_ASSOC) {
2666                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2667                         bss_conf->assoc);
2668                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2669         }
2670
2671         mutex_unlock(&sc->mutex);
2672 }
2673
2674 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2675 {
2676         u64 tsf;
2677         struct ath_wiphy *aphy = hw->priv;
2678         struct ath_softc *sc = aphy->sc;
2679
2680         mutex_lock(&sc->mutex);
2681         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2682         mutex_unlock(&sc->mutex);
2683
2684         return tsf;
2685 }
2686
2687 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2688 {
2689         struct ath_wiphy *aphy = hw->priv;
2690         struct ath_softc *sc = aphy->sc;
2691
2692         mutex_lock(&sc->mutex);
2693         ath9k_hw_settsf64(sc->sc_ah, tsf);
2694         mutex_unlock(&sc->mutex);
2695 }
2696
2697 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2698 {
2699         struct ath_wiphy *aphy = hw->priv;
2700         struct ath_softc *sc = aphy->sc;
2701
2702         mutex_lock(&sc->mutex);
2703         ath9k_hw_reset_tsf(sc->sc_ah);
2704         mutex_unlock(&sc->mutex);
2705 }
2706
2707 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2708                               enum ieee80211_ampdu_mlme_action action,
2709                               struct ieee80211_sta *sta,
2710                               u16 tid, u16 *ssn)
2711 {
2712         struct ath_wiphy *aphy = hw->priv;
2713         struct ath_softc *sc = aphy->sc;
2714         int ret = 0;
2715
2716         switch (action) {
2717         case IEEE80211_AMPDU_RX_START:
2718                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2719                         ret = -ENOTSUPP;
2720                 break;
2721         case IEEE80211_AMPDU_RX_STOP:
2722                 break;
2723         case IEEE80211_AMPDU_TX_START:
2724                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2725                 if (ret < 0)
2726                         DPRINTF(sc, ATH_DBG_FATAL,
2727                                 "Unable to start TX aggregation\n");
2728                 else
2729                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2730                 break;
2731         case IEEE80211_AMPDU_TX_STOP:
2732                 ret = ath_tx_aggr_stop(sc, sta, tid);
2733                 if (ret < 0)
2734                         DPRINTF(sc, ATH_DBG_FATAL,
2735                                 "Unable to stop TX aggregation\n");
2736
2737                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2738                 break;
2739         case IEEE80211_AMPDU_TX_OPERATIONAL:
2740                 ath_tx_aggr_resume(sc, sta, tid);
2741                 break;
2742         default:
2743                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2744         }
2745
2746         return ret;
2747 }
2748
2749 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2750 {
2751         struct ath_wiphy *aphy = hw->priv;
2752         struct ath_softc *sc = aphy->sc;
2753
2754         if (ath9k_wiphy_scanning(sc)) {
2755                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2756                        "same time\n");
2757                 /*
2758                  * Do not allow the concurrent scanning state for now. This
2759                  * could be improved with scanning control moved into ath9k.
2760                  */
2761                 return;
2762         }
2763
2764         aphy->state = ATH_WIPHY_SCAN;
2765         ath9k_wiphy_pause_all_forced(sc, aphy);
2766
2767         mutex_lock(&sc->mutex);
2768         sc->sc_flags |= SC_OP_SCANNING;
2769         mutex_unlock(&sc->mutex);
2770 }
2771
2772 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2773 {
2774         struct ath_wiphy *aphy = hw->priv;
2775         struct ath_softc *sc = aphy->sc;
2776
2777         mutex_lock(&sc->mutex);
2778         aphy->state = ATH_WIPHY_ACTIVE;
2779         sc->sc_flags &= ~SC_OP_SCANNING;
2780         mutex_unlock(&sc->mutex);
2781 }
2782
2783 struct ieee80211_ops ath9k_ops = {
2784         .tx                 = ath9k_tx,
2785         .start              = ath9k_start,
2786         .stop               = ath9k_stop,
2787         .add_interface      = ath9k_add_interface,
2788         .remove_interface   = ath9k_remove_interface,
2789         .config             = ath9k_config,
2790         .config_interface   = ath9k_config_interface,
2791         .configure_filter   = ath9k_configure_filter,
2792         .sta_notify         = ath9k_sta_notify,
2793         .conf_tx            = ath9k_conf_tx,
2794         .bss_info_changed   = ath9k_bss_info_changed,
2795         .set_key            = ath9k_set_key,
2796         .get_tsf            = ath9k_get_tsf,
2797         .set_tsf            = ath9k_set_tsf,
2798         .reset_tsf          = ath9k_reset_tsf,
2799         .ampdu_action       = ath9k_ampdu_action,
2800         .sw_scan_start      = ath9k_sw_scan_start,
2801         .sw_scan_complete   = ath9k_sw_scan_complete,
2802 };
2803
2804 static struct {
2805         u32 version;
2806         const char * name;
2807 } ath_mac_bb_names[] = {
2808         { AR_SREV_VERSION_5416_PCI,     "5416" },
2809         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2810         { AR_SREV_VERSION_9100,         "9100" },
2811         { AR_SREV_VERSION_9160,         "9160" },
2812         { AR_SREV_VERSION_9280,         "9280" },
2813         { AR_SREV_VERSION_9285,         "9285" }
2814 };
2815
2816 static struct {
2817         u16 version;
2818         const char * name;
2819 } ath_rf_names[] = {
2820         { 0,                            "5133" },
2821         { AR_RAD5133_SREV_MAJOR,        "5133" },
2822         { AR_RAD5122_SREV_MAJOR,        "5122" },
2823         { AR_RAD2133_SREV_MAJOR,        "2133" },
2824         { AR_RAD2122_SREV_MAJOR,        "2122" }
2825 };
2826
2827 /*
2828  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2829  */
2830 const char *
2831 ath_mac_bb_name(u32 mac_bb_version)
2832 {
2833         int i;
2834
2835         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2836                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2837                         return ath_mac_bb_names[i].name;
2838                 }
2839         }
2840
2841         return "????";
2842 }
2843
2844 /*
2845  * Return the RF name. "????" is returned if the RF is unknown.
2846  */
2847 const char *
2848 ath_rf_name(u16 rf_version)
2849 {
2850         int i;
2851
2852         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2853                 if (ath_rf_names[i].version == rf_version) {
2854                         return ath_rf_names[i].name;
2855                 }
2856         }
2857
2858         return "????";
2859 }
2860
2861 static int __init ath9k_init(void)
2862 {
2863         int error;
2864
2865         /* Register rate control algorithm */
2866         error = ath_rate_control_register();
2867         if (error != 0) {
2868                 printk(KERN_ERR
2869                         "ath9k: Unable to register rate control "
2870                         "algorithm: %d\n",
2871                         error);
2872                 goto err_out;
2873         }
2874
2875         error = ath9k_debug_create_root();
2876         if (error) {
2877                 printk(KERN_ERR
2878                         "ath9k: Unable to create debugfs root: %d\n",
2879                         error);
2880                 goto err_rate_unregister;
2881         }
2882
2883         error = ath_pci_init();
2884         if (error < 0) {
2885                 printk(KERN_ERR
2886                         "ath9k: No PCI devices found, driver not installed.\n");
2887                 error = -ENODEV;
2888                 goto err_remove_root;
2889         }
2890
2891         error = ath_ahb_init();
2892         if (error < 0) {
2893                 error = -ENODEV;
2894                 goto err_pci_exit;
2895         }
2896
2897         return 0;
2898
2899  err_pci_exit:
2900         ath_pci_exit();
2901
2902  err_remove_root:
2903         ath9k_debug_remove_root();
2904  err_rate_unregister:
2905         ath_rate_control_unregister();
2906  err_out:
2907         return error;
2908 }
2909 module_init(ath9k_init);
2910
2911 static void __exit ath9k_exit(void)
2912 {
2913         ath_ahb_exit();
2914         ath_pci_exit();
2915         ath9k_debug_remove_root();
2916         ath_rate_control_unregister();
2917         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2918 }
2919 module_exit(ath9k_exit);