2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
26 #define ATH9K_CLOCK_RATE_CCK 22
27 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
28 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
31 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
32 enum ath9k_ht_macmode macmode);
33 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
34 struct ar5416_eeprom_def *pEepData,
36 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
37 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
39 /********************/
40 /* Helper Functions */
41 /********************/
43 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
45 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
46 if (!ah->ah_curchan) /* should really check for CCK instead */
47 return clks / ATH9K_CLOCK_RATE_CCK;
48 if (conf->channel->band == IEEE80211_BAND_2GHZ)
49 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
50 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
53 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
55 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
56 if (conf_is_ht40(conf))
57 return ath9k_hw_mac_usec(ah, clks) / 2;
59 return ath9k_hw_mac_usec(ah, clks);
62 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
64 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
65 if (!ah->ah_curchan) /* should really check for CCK instead */
66 return usecs *ATH9K_CLOCK_RATE_CCK;
67 if (conf->channel->band == IEEE80211_BAND_2GHZ)
68 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
69 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
72 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
74 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
75 if (conf_is_ht40(conf))
76 return ath9k_hw_mac_clks(ah, usecs) * 2;
78 return ath9k_hw_mac_clks(ah, usecs);
81 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
85 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
86 if ((REG_READ(ah, reg) & mask) == val)
89 udelay(AH_TIME_QUANTUM);
92 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
93 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
94 reg, REG_READ(ah, reg), mask, val);
99 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
104 for (i = 0, retval = 0; i < n; i++) {
105 retval = (retval << 1) | (val & 1);
111 bool ath9k_get_channel_edges(struct ath_hal *ah,
115 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
117 if (flags & CHANNEL_5GHZ) {
118 *low = pCap->low_5ghz_chan;
119 *high = pCap->high_5ghz_chan;
122 if ((flags & CHANNEL_2GHZ)) {
123 *low = pCap->low_2ghz_chan;
124 *high = pCap->high_2ghz_chan;
130 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
131 struct ath_rate_table *rates,
132 u32 frameLen, u16 rateix,
135 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
138 kbps = rates->info[rateix].ratekbps;
143 switch (rates->info[rateix].phy) {
144 case WLAN_RC_PHY_CCK:
145 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
146 if (shortPreamble && rates->info[rateix].short_preamble)
148 numBits = frameLen << 3;
149 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
151 case WLAN_RC_PHY_OFDM:
152 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
153 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
154 numBits = OFDM_PLCP_BITS + (frameLen << 3);
155 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
156 txTime = OFDM_SIFS_TIME_QUARTER
157 + OFDM_PREAMBLE_TIME_QUARTER
158 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
159 } else if (ah->ah_curchan &&
160 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
161 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
162 numBits = OFDM_PLCP_BITS + (frameLen << 3);
163 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
164 txTime = OFDM_SIFS_TIME_HALF +
165 OFDM_PREAMBLE_TIME_HALF
166 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
168 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
169 numBits = OFDM_PLCP_BITS + (frameLen << 3);
170 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
171 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
172 + (numSymbols * OFDM_SYMBOL_TIME);
176 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
177 "Unknown phy %u (rate ix %u)\n",
178 rates->info[rateix].phy, rateix);
186 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
188 if (flags & CHANNEL_2GHZ) {
192 return (freq - 2407) / 5;
194 return 15 + ((freq - 2512) / 20);
195 } else if (flags & CHANNEL_5GHZ) {
196 if (ath9k_regd_is_public_safety_sku(ah) &&
197 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
198 return ((freq * 10) +
199 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
200 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
201 return (freq - 4000) / 5;
203 return (freq - 5000) / 5;
209 return (freq - 2407) / 5;
211 if (ath9k_regd_is_public_safety_sku(ah)
212 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
213 return ((freq * 10) +
215 2) ? 5 : 0) - 49400) / 5;
216 } else if (freq > 4900) {
217 return (freq - 4000) / 5;
219 return 15 + ((freq - 2512) / 20);
222 return (freq - 5000) / 5;
226 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
231 struct ath_hal_5416 *ahp = AH5416(ah);
233 if (!IS_CHAN_HT40(chan)) {
234 centers->ctl_center = centers->ext_center =
235 centers->synth_center = chan->channel;
239 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
240 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
241 centers->synth_center =
242 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
245 centers->synth_center =
246 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
250 centers->ctl_center =
251 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
252 centers->ext_center =
253 centers->synth_center + (extoff *
254 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
255 HT40_CHANNEL_CENTER_SHIFT : 15));
263 static void ath9k_hw_read_revisions(struct ath_hal *ah)
267 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
270 val = REG_READ(ah, AR_SREV);
271 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
272 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
273 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
275 if (!AR_SREV_9100(ah))
276 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
278 ah->ah_macRev = val & AR_SREV_REVISION;
280 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
281 ah->ah_isPciExpress = true;
285 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
290 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
292 for (i = 0; i < 8; i++)
293 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
294 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
295 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
297 return ath9k_hw_reverse_bits(val, 8);
300 /************************************/
301 /* HW Attach, Detach, Init Routines */
302 /************************************/
304 static void ath9k_hw_disablepcie(struct ath_hal *ah)
306 if (!AR_SREV_9100(ah))
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
319 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
322 static bool ath9k_hw_chip_test(struct ath_hal *ah)
324 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
326 u32 patternData[4] = { 0x55555555,
332 for (i = 0; i < 2; i++) {
333 u32 addr = regAddr[i];
336 regHold[i] = REG_READ(ah, addr);
337 for (j = 0; j < 0x100; j++) {
338 wrData = (j << 16) | j;
339 REG_WRITE(ah, addr, wrData);
340 rdData = REG_READ(ah, addr);
341 if (rdData != wrData) {
342 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
343 "address test failed "
344 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
345 addr, wrData, rdData);
349 for (j = 0; j < 4; j++) {
350 wrData = patternData[j];
351 REG_WRITE(ah, addr, wrData);
352 rdData = REG_READ(ah, addr);
353 if (wrData != rdData) {
354 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
355 "address test failed "
356 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
357 addr, wrData, rdData);
361 REG_WRITE(ah, regAddr[i], regHold[i]);
367 static const char *ath9k_hw_devname(u16 devid)
370 case AR5416_DEVID_PCI:
371 return "Atheros 5416";
372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
376 case AR9280_DEVID_PCI:
377 case AR9280_DEVID_PCIE:
378 return "Atheros 9280";
379 case AR9285_DEVID_PCIE:
380 return "Atheros 9285";
386 static void ath9k_hw_set_defaults(struct ath_hal *ah)
390 ah->ah_config.dma_beacon_response_time = 2;
391 ah->ah_config.sw_beacon_response_time = 10;
392 ah->ah_config.additional_swba_backoff = 0;
393 ah->ah_config.ack_6mb = 0x0;
394 ah->ah_config.cwm_ignore_extcca = 0;
395 ah->ah_config.pcie_powersave_enable = 0;
396 ah->ah_config.pcie_l1skp_enable = 0;
397 ah->ah_config.pcie_clock_req = 0;
398 ah->ah_config.pcie_power_reset = 0x100;
399 ah->ah_config.pcie_restore = 0;
400 ah->ah_config.pcie_waen = 0;
401 ah->ah_config.analog_shiftreg = 1;
402 ah->ah_config.ht_enable = 1;
403 ah->ah_config.ofdm_trig_low = 200;
404 ah->ah_config.ofdm_trig_high = 500;
405 ah->ah_config.cck_trig_high = 200;
406 ah->ah_config.cck_trig_low = 100;
407 ah->ah_config.enable_ani = 1;
408 ah->ah_config.noise_immunity_level = 4;
409 ah->ah_config.ofdm_weaksignal_det = 1;
410 ah->ah_config.cck_weaksignal_thr = 0;
411 ah->ah_config.spur_immunity_level = 2;
412 ah->ah_config.firstep_level = 0;
413 ah->ah_config.rssi_thr_high = 40;
414 ah->ah_config.rssi_thr_low = 7;
415 ah->ah_config.diversity_control = 0;
416 ah->ah_config.antenna_switch_swap = 0;
418 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
419 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
420 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
423 ah->ah_config.intr_mitigation = 1;
426 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
427 struct ath_softc *sc,
431 static const u8 defbssidmask[ETH_ALEN] =
432 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
433 struct ath_hal_5416 *ahp;
436 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
438 DPRINTF(sc, ATH_DBG_FATAL,
439 "Cannot allocate memory for state block\n");
447 ah->ah_magic = AR5416_MAGIC;
448 ah->ah_countryCode = CTRY_DEFAULT;
449 ah->ah_devid = devid;
450 ah->ah_subvendorid = 0;
453 if ((devid == AR5416_AR9100_DEVID))
454 ah->ah_macVersion = AR_SREV_VERSION_9100;
455 if (!AR_SREV_9100(ah))
456 ah->ah_flags = AH_USE_EEPROM;
458 ah->ah_powerLimit = MAX_RATE_POWER;
459 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
460 ahp->ah_atimWindow = 0;
461 ahp->ah_diversityControl = ah->ah_config.diversity_control;
462 ahp->ah_antennaSwitchSwap =
463 ah->ah_config.antenna_switch_swap;
464 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
465 ahp->ah_beaconInterval = 100;
466 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
467 ahp->ah_slottime = (u32) -1;
468 ahp->ah_acktimeout = (u32) -1;
469 ahp->ah_ctstimeout = (u32) -1;
470 ahp->ah_globaltxtimeout = (u32) -1;
471 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
473 ahp->ah_gBeaconRate = 0;
478 static int ath9k_hw_rfattach(struct ath_hal *ah)
480 bool rfStatus = false;
483 rfStatus = ath9k_hw_init_rf(ah, &ecode);
485 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
486 "RF setup failed, status %u\n", ecode);
493 static int ath9k_hw_rf_claim(struct ath_hal *ah)
497 REG_WRITE(ah, AR_PHY(0), 0x00000007);
499 val = ath9k_hw_get_radiorev(ah);
500 switch (val & AR_RADIO_SREV_MAJOR) {
502 val = AR_RAD5133_SREV_MAJOR;
504 case AR_RAD5133_SREV_MAJOR:
505 case AR_RAD5122_SREV_MAJOR:
506 case AR_RAD2133_SREV_MAJOR:
507 case AR_RAD2122_SREV_MAJOR:
510 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
511 "5G Radio Chip Rev 0x%02X is not "
512 "supported by this driver\n",
513 ah->ah_analog5GhzRev);
517 ah->ah_analog5GhzRev = val;
522 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
527 struct ath_hal_5416 *ahp = AH5416(ah);
530 for (i = 0; i < 3; i++) {
531 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
533 ahp->ah_macaddr[2 * i] = eeval >> 8;
534 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
536 if (sum == 0 || sum == 0xffff * 3) {
537 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
538 "mac address read failed: %pM\n",
540 return -EADDRNOTAVAIL;
546 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
549 struct ath_hal_5416 *ahp = AH5416(ah);
551 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
552 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
554 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
555 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
556 ar9280Modes_backoff_13db_rxgain_9280_2,
557 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
558 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
559 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
560 ar9280Modes_backoff_23db_rxgain_9280_2,
561 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
563 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
564 ar9280Modes_original_rxgain_9280_2,
565 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
567 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
568 ar9280Modes_original_rxgain_9280_2,
569 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
572 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
575 struct ath_hal_5416 *ahp = AH5416(ah);
577 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
578 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
580 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
581 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
582 ar9280Modes_high_power_tx_gain_9280_2,
583 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
585 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
586 ar9280Modes_original_tx_gain_9280_2,
587 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
589 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
590 ar9280Modes_original_tx_gain_9280_2,
591 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
594 static int ath9k_hw_post_attach(struct ath_hal *ah)
598 if (!ath9k_hw_chip_test(ah)) {
599 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
600 "hardware self-test failed\n");
604 ecode = ath9k_hw_rf_claim(ah);
608 ecode = ath9k_hw_eeprom_attach(ah);
611 ecode = ath9k_hw_rfattach(ah);
615 if (!AR_SREV_9100(ah)) {
616 ath9k_hw_ani_setup(ah);
617 ath9k_hw_ani_attach(ah);
623 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
624 void __iomem *mem, int *status)
626 struct ath_hal_5416 *ahp;
631 ahp = ath9k_hw_newstate(devid, sc, mem, status);
637 ath9k_hw_set_defaults(ah);
639 if (ah->ah_config.intr_mitigation != 0)
640 ahp->ah_intrMitigation = true;
642 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
643 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
648 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
649 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
654 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
655 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
656 ah->ah_config.serialize_regmode =
659 ah->ah_config.serialize_regmode =
664 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
665 "serialize_regmode is %d\n",
666 ah->ah_config.serialize_regmode);
668 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
669 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
670 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
671 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
672 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
673 "Mac Chip Rev 0x%02x.%x is not supported by "
674 "this driver\n", ah->ah_macVersion, ah->ah_macRev);
679 if (AR_SREV_9100(ah)) {
680 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
681 ahp->ah_suppCals = IQ_MISMATCH_CAL;
682 ah->ah_isPciExpress = false;
684 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
686 if (AR_SREV_9160_10_OR_LATER(ah)) {
687 if (AR_SREV_9280_10_OR_LATER(ah)) {
688 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
689 ahp->ah_adcGainCalData.calData =
690 &adc_gain_cal_single_sample;
691 ahp->ah_adcDcCalData.calData =
692 &adc_dc_cal_single_sample;
693 ahp->ah_adcDcCalInitData.calData =
696 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
697 ahp->ah_adcGainCalData.calData =
698 &adc_gain_cal_multi_sample;
699 ahp->ah_adcDcCalData.calData =
700 &adc_dc_cal_multi_sample;
701 ahp->ah_adcDcCalInitData.calData =
704 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
707 if (AR_SREV_9160(ah)) {
708 ah->ah_config.enable_ani = 1;
709 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
710 ATH9K_ANI_FIRSTEP_LEVEL);
712 ahp->ah_ani_function = ATH9K_ANI_ALL;
713 if (AR_SREV_9280_10_OR_LATER(ah)) {
714 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
718 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
719 "This Mac Chip Rev 0x%02x.%x is \n",
720 ah->ah_macVersion, ah->ah_macRev);
722 if (AR_SREV_9285_12_OR_LATER(ah)) {
723 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
724 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
725 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
726 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
728 if (ah->ah_config.pcie_clock_req) {
729 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
730 ar9285PciePhy_clkreq_off_L1_9285_1_2,
731 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
733 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
734 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
735 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
738 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
739 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
740 ARRAY_SIZE(ar9285Modes_9285), 6);
741 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
742 ARRAY_SIZE(ar9285Common_9285), 2);
744 if (ah->ah_config.pcie_clock_req) {
745 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
746 ar9285PciePhy_clkreq_off_L1_9285,
747 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
749 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
750 ar9285PciePhy_clkreq_always_on_L1_9285,
751 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
753 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
754 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
755 ARRAY_SIZE(ar9280Modes_9280_2), 6);
756 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
757 ARRAY_SIZE(ar9280Common_9280_2), 2);
759 if (ah->ah_config.pcie_clock_req) {
760 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
761 ar9280PciePhy_clkreq_off_L1_9280,
762 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
764 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
765 ar9280PciePhy_clkreq_always_on_L1_9280,
766 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
768 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
769 ar9280Modes_fast_clock_9280_2,
770 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
771 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
772 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
773 ARRAY_SIZE(ar9280Modes_9280), 6);
774 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
775 ARRAY_SIZE(ar9280Common_9280), 2);
776 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
777 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
778 ARRAY_SIZE(ar5416Modes_9160), 6);
779 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
780 ARRAY_SIZE(ar5416Common_9160), 2);
781 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
782 ARRAY_SIZE(ar5416Bank0_9160), 2);
783 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
784 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
785 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
786 ARRAY_SIZE(ar5416Bank1_9160), 2);
787 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
788 ARRAY_SIZE(ar5416Bank2_9160), 2);
789 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
790 ARRAY_SIZE(ar5416Bank3_9160), 3);
791 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
792 ARRAY_SIZE(ar5416Bank6_9160), 3);
793 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
794 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
795 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
796 ARRAY_SIZE(ar5416Bank7_9160), 2);
797 if (AR_SREV_9160_11(ah)) {
798 INIT_INI_ARRAY(&ahp->ah_iniAddac,
800 ARRAY_SIZE(ar5416Addac_91601_1), 2);
802 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
803 ARRAY_SIZE(ar5416Addac_9160), 2);
805 } else if (AR_SREV_9100_OR_LATER(ah)) {
806 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
807 ARRAY_SIZE(ar5416Modes_9100), 6);
808 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
809 ARRAY_SIZE(ar5416Common_9100), 2);
810 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
811 ARRAY_SIZE(ar5416Bank0_9100), 2);
812 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
813 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
814 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
815 ARRAY_SIZE(ar5416Bank1_9100), 2);
816 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
817 ARRAY_SIZE(ar5416Bank2_9100), 2);
818 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
819 ARRAY_SIZE(ar5416Bank3_9100), 3);
820 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
821 ARRAY_SIZE(ar5416Bank6_9100), 3);
822 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
823 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
824 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
825 ARRAY_SIZE(ar5416Bank7_9100), 2);
826 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
827 ARRAY_SIZE(ar5416Addac_9100), 2);
829 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
830 ARRAY_SIZE(ar5416Modes), 6);
831 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
832 ARRAY_SIZE(ar5416Common), 2);
833 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
834 ARRAY_SIZE(ar5416Bank0), 2);
835 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
836 ARRAY_SIZE(ar5416BB_RfGain), 3);
837 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
838 ARRAY_SIZE(ar5416Bank1), 2);
839 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
840 ARRAY_SIZE(ar5416Bank2), 2);
841 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
842 ARRAY_SIZE(ar5416Bank3), 3);
843 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
844 ARRAY_SIZE(ar5416Bank6), 3);
845 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
846 ARRAY_SIZE(ar5416Bank6TPC), 3);
847 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
848 ARRAY_SIZE(ar5416Bank7), 2);
849 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
850 ARRAY_SIZE(ar5416Addac), 2);
853 if (ah->ah_isPciExpress)
854 ath9k_hw_configpcipowersave(ah, 0);
856 ath9k_hw_disablepcie(ah);
858 ecode = ath9k_hw_post_attach(ah);
863 if (AR_SREV_9280_20(ah))
864 ath9k_hw_init_rxgain_ini(ah);
867 if (AR_SREV_9280_20(ah))
868 ath9k_hw_init_txgain_ini(ah);
870 if (ah->ah_devid == AR9280_DEVID_PCI) {
871 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
872 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
874 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
875 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
877 INI_RA(&ahp->ah_iniModes, i, j) =
878 ath9k_hw_ini_fixup(ah,
885 if (!ath9k_hw_fill_cap_info(ah)) {
886 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
887 "failed ath9k_hw_fill_cap_info\n");
892 ecode = ath9k_hw_init_macaddr(ah);
894 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
895 "failed initializing mac address\n");
899 if (AR_SREV_9285(ah))
900 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
902 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
904 ath9k_init_nfcal_hist_buffer(ah);
909 ath9k_hw_detach((struct ath_hal *) ahp);
916 static void ath9k_hw_init_bb(struct ath_hal *ah,
917 struct ath9k_channel *chan)
921 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
923 synthDelay = (4 * synthDelay) / 22;
927 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
929 udelay(synthDelay + BASE_ACTIVATE_DELAY);
932 static void ath9k_hw_init_qos(struct ath_hal *ah)
934 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
935 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
937 REG_WRITE(ah, AR_QOS_NO_ACK,
938 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
939 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
940 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
942 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
943 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
944 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
945 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
946 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
949 static void ath9k_hw_init_pll(struct ath_hal *ah,
950 struct ath9k_channel *chan)
954 if (AR_SREV_9100(ah)) {
955 if (chan && IS_CHAN_5GHZ(chan))
960 if (AR_SREV_9280_10_OR_LATER(ah)) {
961 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
963 if (chan && IS_CHAN_HALF_RATE(chan))
964 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
965 else if (chan && IS_CHAN_QUARTER_RATE(chan))
966 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
968 if (chan && IS_CHAN_5GHZ(chan)) {
969 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
972 if (AR_SREV_9280_20(ah)) {
973 if (((chan->channel % 20) == 0)
974 || ((chan->channel % 10) == 0))
980 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
983 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
985 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
987 if (chan && IS_CHAN_HALF_RATE(chan))
988 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
989 else if (chan && IS_CHAN_QUARTER_RATE(chan))
990 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
992 if (chan && IS_CHAN_5GHZ(chan))
993 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
995 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
997 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
999 if (chan && IS_CHAN_HALF_RATE(chan))
1000 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1001 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1002 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1004 if (chan && IS_CHAN_5GHZ(chan))
1005 pll |= SM(0xa, AR_RTC_PLL_DIV);
1007 pll |= SM(0xb, AR_RTC_PLL_DIV);
1010 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1012 udelay(RTC_PLL_SETTLE_DELAY);
1014 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1017 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1019 struct ath_hal_5416 *ahp = AH5416(ah);
1020 int rx_chainmask, tx_chainmask;
1022 rx_chainmask = ahp->ah_rxchainmask;
1023 tx_chainmask = ahp->ah_txchainmask;
1025 switch (rx_chainmask) {
1027 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1028 AR_PHY_SWAP_ALT_CHAIN);
1030 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1031 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1032 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1038 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1039 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1045 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1046 if (tx_chainmask == 0x5) {
1047 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1048 AR_PHY_SWAP_ALT_CHAIN);
1050 if (AR_SREV_9100(ah))
1051 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1052 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1055 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1056 enum nl80211_iftype opmode)
1058 struct ath_hal_5416 *ahp = AH5416(ah);
1060 ahp->ah_maskReg = AR_IMR_TXERR |
1066 if (ahp->ah_intrMitigation)
1067 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1069 ahp->ah_maskReg |= AR_IMR_RXOK;
1071 ahp->ah_maskReg |= AR_IMR_TXOK;
1073 if (opmode == NL80211_IFTYPE_AP)
1074 ahp->ah_maskReg |= AR_IMR_MIB;
1076 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1077 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1079 if (!AR_SREV_9100(ah)) {
1080 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1081 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1082 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1086 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1088 struct ath_hal_5416 *ahp = AH5416(ah);
1090 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1091 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1092 ahp->ah_acktimeout = (u32) -1;
1095 REG_RMW_FIELD(ah, AR_TIME_OUT,
1096 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1097 ahp->ah_acktimeout = us;
1102 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1104 struct ath_hal_5416 *ahp = AH5416(ah);
1106 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1107 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1108 ahp->ah_ctstimeout = (u32) -1;
1111 REG_RMW_FIELD(ah, AR_TIME_OUT,
1112 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1113 ahp->ah_ctstimeout = us;
1118 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1120 struct ath_hal_5416 *ahp = AH5416(ah);
1123 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1124 "bad global tx timeout %u\n", tu);
1125 ahp->ah_globaltxtimeout = (u32) -1;
1128 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1129 ahp->ah_globaltxtimeout = tu;
1134 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1136 struct ath_hal_5416 *ahp = AH5416(ah);
1138 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1141 if (ahp->ah_miscMode != 0)
1142 REG_WRITE(ah, AR_PCU_MISC,
1143 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1144 if (ahp->ah_slottime != (u32) -1)
1145 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1146 if (ahp->ah_acktimeout != (u32) -1)
1147 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1148 if (ahp->ah_ctstimeout != (u32) -1)
1149 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1150 if (ahp->ah_globaltxtimeout != (u32) -1)
1151 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1154 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1156 return vendorid == ATHEROS_VENDOR_ID ?
1157 ath9k_hw_devname(devid) : NULL;
1160 void ath9k_hw_detach(struct ath_hal *ah)
1162 if (!AR_SREV_9100(ah))
1163 ath9k_hw_ani_detach(ah);
1165 ath9k_hw_rfdetach(ah);
1166 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1170 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1171 void __iomem *mem, int *error)
1173 struct ath_hal *ah = NULL;
1176 case AR5416_DEVID_PCI:
1177 case AR5416_DEVID_PCIE:
1178 case AR9160_DEVID_PCI:
1179 case AR9280_DEVID_PCI:
1180 case AR9280_DEVID_PCIE:
1181 case AR9285_DEVID_PCIE:
1182 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1196 static void ath9k_hw_override_ini(struct ath_hal *ah,
1197 struct ath9k_channel *chan)
1200 * Set the RX_ABORT and RX_DIS and clear if off only after
1201 * RXE is set for MAC. This prevents frames with corrupted
1202 * descriptor status.
1204 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1207 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1208 AR_SREV_9280_10_OR_LATER(ah))
1211 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1214 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1215 struct ar5416_eeprom_def *pEepData,
1218 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1220 switch (ah->ah_devid) {
1221 case AR9280_DEVID_PCI:
1222 if (reg == 0x7894) {
1223 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1224 "ini VAL: %x EEPROM: %x\n", value,
1225 (pBase->version & 0xff));
1227 if ((pBase->version & 0xff) > 0x0a) {
1228 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1231 value &= ~AR_AN_TOP2_PWDCLKIND;
1232 value |= AR_AN_TOP2_PWDCLKIND &
1233 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1235 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1236 "PWDCLKIND Earlier Rev\n");
1239 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1240 "final ini VAL: %x\n", value);
1248 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1249 struct ar5416_eeprom_def *pEepData,
1252 struct ath_hal_5416 *ahp = AH5416(ah);
1254 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1257 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1260 static int ath9k_hw_process_ini(struct ath_hal *ah,
1261 struct ath9k_channel *chan,
1262 enum ath9k_ht_macmode macmode)
1264 int i, regWrites = 0;
1265 struct ath_hal_5416 *ahp = AH5416(ah);
1266 u32 modesIndex, freqIndex;
1269 switch (chan->chanmode) {
1271 case CHANNEL_A_HT20:
1275 case CHANNEL_A_HT40PLUS:
1276 case CHANNEL_A_HT40MINUS:
1281 case CHANNEL_G_HT20:
1286 case CHANNEL_G_HT40PLUS:
1287 case CHANNEL_G_HT40MINUS:
1296 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1298 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1300 ath9k_hw_set_addac(ah, chan);
1302 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1303 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1305 struct ar5416IniArray temp;
1307 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1308 ahp->ah_iniAddac.ia_columns;
1310 memcpy(ahp->ah_addac5416_21,
1311 ahp->ah_iniAddac.ia_array, addacSize);
1313 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1315 temp.ia_array = ahp->ah_addac5416_21;
1316 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1317 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1318 REG_WRITE_ARRAY(&temp, 1, regWrites);
1321 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1323 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1324 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1325 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1327 REG_WRITE(ah, reg, val);
1329 if (reg >= 0x7800 && reg < 0x78a0
1330 && ah->ah_config.analog_shiftreg) {
1334 DO_DELAY(regWrites);
1337 if (AR_SREV_9280(ah))
1338 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1340 if (AR_SREV_9280(ah))
1341 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1343 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1344 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1345 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1347 REG_WRITE(ah, reg, val);
1349 if (reg >= 0x7800 && reg < 0x78a0
1350 && ah->ah_config.analog_shiftreg) {
1354 DO_DELAY(regWrites);
1357 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1359 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1360 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1364 ath9k_hw_override_ini(ah, chan);
1365 ath9k_hw_set_regs(ah, chan, macmode);
1366 ath9k_hw_init_chain_masks(ah);
1368 status = ath9k_hw_set_txpower(ah, chan,
1369 ath9k_regd_get_ctl(ah, chan),
1370 ath9k_regd_get_antenna_allowed(ah,
1372 chan->maxRegTxPower * 2,
1373 min((u32) MAX_RATE_POWER,
1374 (u32) ah->ah_powerLimit));
1376 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1377 "error init'ing transmit power\n");
1381 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1382 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1383 "ar5416SetRfRegs failed\n");
1390 /****************************************/
1391 /* Reset and Channel Switching Routines */
1392 /****************************************/
1394 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1401 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1402 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1404 if (!AR_SREV_9280_10_OR_LATER(ah))
1405 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1406 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1408 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1409 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1411 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1414 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1416 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1419 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1423 regval = REG_READ(ah, AR_AHB_MODE);
1424 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1426 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1427 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1429 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1431 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1432 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1434 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1436 if (AR_SREV_9285(ah)) {
1437 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1438 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1440 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1441 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1445 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1449 val = REG_READ(ah, AR_STA_ID1);
1450 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1452 case NL80211_IFTYPE_AP:
1453 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1454 | AR_STA_ID1_KSRCH_MODE);
1455 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1457 case NL80211_IFTYPE_ADHOC:
1458 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1459 | AR_STA_ID1_KSRCH_MODE);
1460 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1462 case NL80211_IFTYPE_STATION:
1463 case NL80211_IFTYPE_MONITOR:
1464 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1469 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1474 u32 coef_exp, coef_man;
1476 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1477 if ((coef_scaled >> coef_exp) & 0x1)
1480 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1482 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1484 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1485 *coef_exponent = coef_exp - 16;
1488 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1489 struct ath9k_channel *chan)
1491 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1492 u32 clockMhzScaled = 0x64000000;
1493 struct chan_centers centers;
1495 if (IS_CHAN_HALF_RATE(chan))
1496 clockMhzScaled = clockMhzScaled >> 1;
1497 else if (IS_CHAN_QUARTER_RATE(chan))
1498 clockMhzScaled = clockMhzScaled >> 2;
1500 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1501 coef_scaled = clockMhzScaled / centers.synth_center;
1503 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1506 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1507 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1508 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1509 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1511 coef_scaled = (9 * coef_scaled) / 10;
1513 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1516 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1517 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1518 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1519 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1522 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1527 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1528 AR_RTC_FORCE_WAKE_ON_INT);
1530 if (AR_SREV_9100(ah)) {
1531 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1532 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1534 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1536 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1537 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1538 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1539 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1541 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1544 rst_flags = AR_RTC_RC_MAC_WARM;
1545 if (type == ATH9K_RESET_COLD)
1546 rst_flags |= AR_RTC_RC_MAC_COLD;
1549 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1552 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1553 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1554 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1555 "RTC stuck in MAC reset\n");
1559 if (!AR_SREV_9100(ah))
1560 REG_WRITE(ah, AR_RC, 0);
1562 ath9k_hw_init_pll(ah, NULL);
1564 if (AR_SREV_9100(ah))
1570 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1572 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1573 AR_RTC_FORCE_WAKE_ON_INT);
1575 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1576 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1578 if (!ath9k_hw_wait(ah,
1581 AR_RTC_STATUS_ON)) {
1582 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1586 ath9k_hw_read_revisions(ah);
1588 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1591 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1593 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1594 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1597 case ATH9K_RESET_POWER_ON:
1598 return ath9k_hw_set_reset_power_on(ah);
1600 case ATH9K_RESET_WARM:
1601 case ATH9K_RESET_COLD:
1602 return ath9k_hw_set_reset(ah, type);
1609 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1610 enum ath9k_ht_macmode macmode)
1613 u32 enableDacFifo = 0;
1614 struct ath_hal_5416 *ahp = AH5416(ah);
1616 if (AR_SREV_9285_10_OR_LATER(ah))
1617 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1618 AR_PHY_FC_ENABLE_DAC_FIFO);
1620 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1621 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1623 if (IS_CHAN_HT40(chan)) {
1624 phymode |= AR_PHY_FC_DYN2040_EN;
1626 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1627 (chan->chanmode == CHANNEL_G_HT40PLUS))
1628 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1630 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1631 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1633 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1635 ath9k_hw_set11nmac2040(ah, macmode);
1637 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1638 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1641 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1642 struct ath9k_channel *chan)
1644 struct ath_hal_5416 *ahp = AH5416(ah);
1646 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1649 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1652 ahp->ah_chipFullSleep = false;
1654 ath9k_hw_init_pll(ah, chan);
1656 ath9k_hw_set_rfmode(ah, chan);
1661 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1662 struct ath9k_channel *chan,
1663 enum ath9k_ht_macmode macmode)
1665 u32 synthDelay, qnum;
1667 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1668 if (ath9k_hw_numtxpending(ah, qnum)) {
1669 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1670 "Transmit frames pending on queue %d\n", qnum);
1675 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1676 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1677 AR_PHY_RFBUS_GRANT_EN)) {
1678 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1679 "Could not kill baseband RX\n");
1683 ath9k_hw_set_regs(ah, chan, macmode);
1685 if (AR_SREV_9280_10_OR_LATER(ah)) {
1686 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1687 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1688 "failed to set channel\n");
1692 if (!(ath9k_hw_set_channel(ah, chan))) {
1693 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1694 "failed to set channel\n");
1699 if (ath9k_hw_set_txpower(ah, chan,
1700 ath9k_regd_get_ctl(ah, chan),
1701 ath9k_regd_get_antenna_allowed(ah, chan),
1702 chan->maxRegTxPower * 2,
1703 min((u32) MAX_RATE_POWER,
1704 (u32) ah->ah_powerLimit)) != 0) {
1705 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1706 "error init'ing transmit power\n");
1710 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1711 if (IS_CHAN_B(chan))
1712 synthDelay = (4 * synthDelay) / 22;
1716 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1718 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1720 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1721 ath9k_hw_set_delta_slope(ah, chan);
1723 if (AR_SREV_9280_10_OR_LATER(ah))
1724 ath9k_hw_9280_spur_mitigate(ah, chan);
1726 ath9k_hw_spur_mitigate(ah, chan);
1728 if (!chan->oneTimeCalsDone)
1729 chan->oneTimeCalsDone = true;
1734 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1736 int bb_spur = AR_NO_SPUR;
1739 int bb_spur_off, spur_subchannel_sd;
1741 int spur_delta_phase;
1743 int upper, lower, cur_vit_mask;
1746 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1747 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1749 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1750 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1752 int inc[4] = { 0, 100, 0, 0 };
1753 struct chan_centers centers;
1760 bool is2GHz = IS_CHAN_2GHZ(chan);
1762 memset(&mask_m, 0, sizeof(int8_t) * 123);
1763 memset(&mask_p, 0, sizeof(int8_t) * 123);
1765 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1766 freq = centers.synth_center;
1768 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1769 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1770 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1773 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1775 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1777 if (AR_NO_SPUR == cur_bb_spur)
1779 cur_bb_spur = cur_bb_spur - freq;
1781 if (IS_CHAN_HT40(chan)) {
1782 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1783 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1784 bb_spur = cur_bb_spur;
1787 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1788 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1789 bb_spur = cur_bb_spur;
1794 if (AR_NO_SPUR == bb_spur) {
1795 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1796 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1799 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1800 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1803 bin = bb_spur * 320;
1805 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1807 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1808 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1809 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1810 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1811 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1813 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1814 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1815 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1816 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1817 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1818 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1820 if (IS_CHAN_HT40(chan)) {
1822 spur_subchannel_sd = 1;
1823 bb_spur_off = bb_spur + 10;
1825 spur_subchannel_sd = 0;
1826 bb_spur_off = bb_spur - 10;
1829 spur_subchannel_sd = 0;
1830 bb_spur_off = bb_spur;
1833 if (IS_CHAN_HT40(chan))
1835 ((bb_spur * 262144) /
1836 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1839 ((bb_spur * 524288) /
1840 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1842 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1843 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1845 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1846 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1847 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1848 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1850 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1851 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1857 for (i = 0; i < 4; i++) {
1861 for (bp = 0; bp < 30; bp++) {
1862 if ((cur_bin > lower) && (cur_bin < upper)) {
1863 pilot_mask = pilot_mask | 0x1 << bp;
1864 chan_mask = chan_mask | 0x1 << bp;
1869 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1870 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1873 cur_vit_mask = 6100;
1877 for (i = 0; i < 123; i++) {
1878 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1880 /* workaround for gcc bug #37014 */
1881 volatile int tmp_v = abs(cur_vit_mask - bin);
1887 if (cur_vit_mask < 0)
1888 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1890 mask_p[cur_vit_mask / 100] = mask_amt;
1892 cur_vit_mask -= 100;
1895 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1896 | (mask_m[48] << 26) | (mask_m[49] << 24)
1897 | (mask_m[50] << 22) | (mask_m[51] << 20)
1898 | (mask_m[52] << 18) | (mask_m[53] << 16)
1899 | (mask_m[54] << 14) | (mask_m[55] << 12)
1900 | (mask_m[56] << 10) | (mask_m[57] << 8)
1901 | (mask_m[58] << 6) | (mask_m[59] << 4)
1902 | (mask_m[60] << 2) | (mask_m[61] << 0);
1903 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1904 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1906 tmp_mask = (mask_m[31] << 28)
1907 | (mask_m[32] << 26) | (mask_m[33] << 24)
1908 | (mask_m[34] << 22) | (mask_m[35] << 20)
1909 | (mask_m[36] << 18) | (mask_m[37] << 16)
1910 | (mask_m[48] << 14) | (mask_m[39] << 12)
1911 | (mask_m[40] << 10) | (mask_m[41] << 8)
1912 | (mask_m[42] << 6) | (mask_m[43] << 4)
1913 | (mask_m[44] << 2) | (mask_m[45] << 0);
1914 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1915 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1917 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1918 | (mask_m[18] << 26) | (mask_m[18] << 24)
1919 | (mask_m[20] << 22) | (mask_m[20] << 20)
1920 | (mask_m[22] << 18) | (mask_m[22] << 16)
1921 | (mask_m[24] << 14) | (mask_m[24] << 12)
1922 | (mask_m[25] << 10) | (mask_m[26] << 8)
1923 | (mask_m[27] << 6) | (mask_m[28] << 4)
1924 | (mask_m[29] << 2) | (mask_m[30] << 0);
1925 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1926 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1928 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1929 | (mask_m[2] << 26) | (mask_m[3] << 24)
1930 | (mask_m[4] << 22) | (mask_m[5] << 20)
1931 | (mask_m[6] << 18) | (mask_m[7] << 16)
1932 | (mask_m[8] << 14) | (mask_m[9] << 12)
1933 | (mask_m[10] << 10) | (mask_m[11] << 8)
1934 | (mask_m[12] << 6) | (mask_m[13] << 4)
1935 | (mask_m[14] << 2) | (mask_m[15] << 0);
1936 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1937 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1939 tmp_mask = (mask_p[15] << 28)
1940 | (mask_p[14] << 26) | (mask_p[13] << 24)
1941 | (mask_p[12] << 22) | (mask_p[11] << 20)
1942 | (mask_p[10] << 18) | (mask_p[9] << 16)
1943 | (mask_p[8] << 14) | (mask_p[7] << 12)
1944 | (mask_p[6] << 10) | (mask_p[5] << 8)
1945 | (mask_p[4] << 6) | (mask_p[3] << 4)
1946 | (mask_p[2] << 2) | (mask_p[1] << 0);
1947 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1948 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1950 tmp_mask = (mask_p[30] << 28)
1951 | (mask_p[29] << 26) | (mask_p[28] << 24)
1952 | (mask_p[27] << 22) | (mask_p[26] << 20)
1953 | (mask_p[25] << 18) | (mask_p[24] << 16)
1954 | (mask_p[23] << 14) | (mask_p[22] << 12)
1955 | (mask_p[21] << 10) | (mask_p[20] << 8)
1956 | (mask_p[19] << 6) | (mask_p[18] << 4)
1957 | (mask_p[17] << 2) | (mask_p[16] << 0);
1958 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1959 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1961 tmp_mask = (mask_p[45] << 28)
1962 | (mask_p[44] << 26) | (mask_p[43] << 24)
1963 | (mask_p[42] << 22) | (mask_p[41] << 20)
1964 | (mask_p[40] << 18) | (mask_p[39] << 16)
1965 | (mask_p[38] << 14) | (mask_p[37] << 12)
1966 | (mask_p[36] << 10) | (mask_p[35] << 8)
1967 | (mask_p[34] << 6) | (mask_p[33] << 4)
1968 | (mask_p[32] << 2) | (mask_p[31] << 0);
1969 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1970 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1972 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1973 | (mask_p[59] << 26) | (mask_p[58] << 24)
1974 | (mask_p[57] << 22) | (mask_p[56] << 20)
1975 | (mask_p[55] << 18) | (mask_p[54] << 16)
1976 | (mask_p[53] << 14) | (mask_p[52] << 12)
1977 | (mask_p[51] << 10) | (mask_p[50] << 8)
1978 | (mask_p[49] << 6) | (mask_p[48] << 4)
1979 | (mask_p[47] << 2) | (mask_p[46] << 0);
1980 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1981 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1984 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1986 int bb_spur = AR_NO_SPUR;
1989 int spur_delta_phase;
1991 int upper, lower, cur_vit_mask;
1994 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1995 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1997 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1998 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2000 int inc[4] = { 0, 100, 0, 0 };
2007 bool is2GHz = IS_CHAN_2GHZ(chan);
2009 memset(&mask_m, 0, sizeof(int8_t) * 123);
2010 memset(&mask_p, 0, sizeof(int8_t) * 123);
2012 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2013 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2014 if (AR_NO_SPUR == cur_bb_spur)
2016 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2017 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2018 bb_spur = cur_bb_spur;
2023 if (AR_NO_SPUR == bb_spur)
2028 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2029 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2030 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2031 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2032 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2034 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2036 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2037 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2038 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2039 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2040 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2041 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2043 spur_delta_phase = ((bb_spur * 524288) / 100) &
2044 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2046 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2047 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2049 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2050 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2051 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2052 REG_WRITE(ah, AR_PHY_TIMING11, new);
2058 for (i = 0; i < 4; i++) {
2062 for (bp = 0; bp < 30; bp++) {
2063 if ((cur_bin > lower) && (cur_bin < upper)) {
2064 pilot_mask = pilot_mask | 0x1 << bp;
2065 chan_mask = chan_mask | 0x1 << bp;
2070 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2071 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2074 cur_vit_mask = 6100;
2078 for (i = 0; i < 123; i++) {
2079 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2081 /* workaround for gcc bug #37014 */
2082 volatile int tmp_v = abs(cur_vit_mask - bin);
2088 if (cur_vit_mask < 0)
2089 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2091 mask_p[cur_vit_mask / 100] = mask_amt;
2093 cur_vit_mask -= 100;
2096 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2097 | (mask_m[48] << 26) | (mask_m[49] << 24)
2098 | (mask_m[50] << 22) | (mask_m[51] << 20)
2099 | (mask_m[52] << 18) | (mask_m[53] << 16)
2100 | (mask_m[54] << 14) | (mask_m[55] << 12)
2101 | (mask_m[56] << 10) | (mask_m[57] << 8)
2102 | (mask_m[58] << 6) | (mask_m[59] << 4)
2103 | (mask_m[60] << 2) | (mask_m[61] << 0);
2104 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2105 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2107 tmp_mask = (mask_m[31] << 28)
2108 | (mask_m[32] << 26) | (mask_m[33] << 24)
2109 | (mask_m[34] << 22) | (mask_m[35] << 20)
2110 | (mask_m[36] << 18) | (mask_m[37] << 16)
2111 | (mask_m[48] << 14) | (mask_m[39] << 12)
2112 | (mask_m[40] << 10) | (mask_m[41] << 8)
2113 | (mask_m[42] << 6) | (mask_m[43] << 4)
2114 | (mask_m[44] << 2) | (mask_m[45] << 0);
2115 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2116 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2118 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2119 | (mask_m[18] << 26) | (mask_m[18] << 24)
2120 | (mask_m[20] << 22) | (mask_m[20] << 20)
2121 | (mask_m[22] << 18) | (mask_m[22] << 16)
2122 | (mask_m[24] << 14) | (mask_m[24] << 12)
2123 | (mask_m[25] << 10) | (mask_m[26] << 8)
2124 | (mask_m[27] << 6) | (mask_m[28] << 4)
2125 | (mask_m[29] << 2) | (mask_m[30] << 0);
2126 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2127 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2129 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2130 | (mask_m[2] << 26) | (mask_m[3] << 24)
2131 | (mask_m[4] << 22) | (mask_m[5] << 20)
2132 | (mask_m[6] << 18) | (mask_m[7] << 16)
2133 | (mask_m[8] << 14) | (mask_m[9] << 12)
2134 | (mask_m[10] << 10) | (mask_m[11] << 8)
2135 | (mask_m[12] << 6) | (mask_m[13] << 4)
2136 | (mask_m[14] << 2) | (mask_m[15] << 0);
2137 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2138 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2140 tmp_mask = (mask_p[15] << 28)
2141 | (mask_p[14] << 26) | (mask_p[13] << 24)
2142 | (mask_p[12] << 22) | (mask_p[11] << 20)
2143 | (mask_p[10] << 18) | (mask_p[9] << 16)
2144 | (mask_p[8] << 14) | (mask_p[7] << 12)
2145 | (mask_p[6] << 10) | (mask_p[5] << 8)
2146 | (mask_p[4] << 6) | (mask_p[3] << 4)
2147 | (mask_p[2] << 2) | (mask_p[1] << 0);
2148 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2149 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2151 tmp_mask = (mask_p[30] << 28)
2152 | (mask_p[29] << 26) | (mask_p[28] << 24)
2153 | (mask_p[27] << 22) | (mask_p[26] << 20)
2154 | (mask_p[25] << 18) | (mask_p[24] << 16)
2155 | (mask_p[23] << 14) | (mask_p[22] << 12)
2156 | (mask_p[21] << 10) | (mask_p[20] << 8)
2157 | (mask_p[19] << 6) | (mask_p[18] << 4)
2158 | (mask_p[17] << 2) | (mask_p[16] << 0);
2159 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2160 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2162 tmp_mask = (mask_p[45] << 28)
2163 | (mask_p[44] << 26) | (mask_p[43] << 24)
2164 | (mask_p[42] << 22) | (mask_p[41] << 20)
2165 | (mask_p[40] << 18) | (mask_p[39] << 16)
2166 | (mask_p[38] << 14) | (mask_p[37] << 12)
2167 | (mask_p[36] << 10) | (mask_p[35] << 8)
2168 | (mask_p[34] << 6) | (mask_p[33] << 4)
2169 | (mask_p[32] << 2) | (mask_p[31] << 0);
2170 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2171 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2173 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2174 | (mask_p[59] << 26) | (mask_p[58] << 24)
2175 | (mask_p[57] << 22) | (mask_p[56] << 20)
2176 | (mask_p[55] << 18) | (mask_p[54] << 16)
2177 | (mask_p[53] << 14) | (mask_p[52] << 12)
2178 | (mask_p[51] << 10) | (mask_p[50] << 8)
2179 | (mask_p[49] << 6) | (mask_p[48] << 4)
2180 | (mask_p[47] << 2) | (mask_p[46] << 0);
2181 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2182 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2185 int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2186 bool bChannelChange)
2189 struct ath_softc *sc = ah->ah_sc;
2190 struct ath_hal_5416 *ahp = AH5416(ah);
2191 struct ath9k_channel *curchan = ah->ah_curchan;
2194 int i, rx_chainmask, r;
2196 ahp->ah_extprotspacing = sc->sc_ht_extprotspacing;
2197 ahp->ah_txchainmask = sc->sc_tx_chainmask;
2198 ahp->ah_rxchainmask = sc->sc_rx_chainmask;
2200 if (AR_SREV_9280(ah)) {
2201 ahp->ah_txchainmask &= 0x3;
2202 ahp->ah_rxchainmask &= 0x3;
2205 if (ath9k_regd_check_channel(ah, chan) == NULL) {
2206 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2207 "invalid channel %u/0x%x; no mapping\n",
2208 chan->channel, chan->channelFlags);
2212 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2216 ath9k_hw_getnf(ah, curchan);
2218 if (bChannelChange &&
2219 (ahp->ah_chipFullSleep != true) &&
2220 (ah->ah_curchan != NULL) &&
2221 (chan->channel != ah->ah_curchan->channel) &&
2222 ((chan->channelFlags & CHANNEL_ALL) ==
2223 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2224 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2225 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2227 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2228 ath9k_hw_loadnf(ah, ah->ah_curchan);
2229 ath9k_hw_start_nfcal(ah);
2234 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2235 if (saveDefAntenna == 0)
2238 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2240 saveLedState = REG_READ(ah, AR_CFG_LED) &
2241 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2242 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2244 ath9k_hw_mark_phy_inactive(ah);
2246 if (!ath9k_hw_chip_reset(ah, chan)) {
2247 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2251 if (AR_SREV_9280(ah)) {
2252 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2253 AR_GPIO_JTAG_DISABLE);
2255 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2256 if (IS_CHAN_5GHZ(chan))
2257 ath9k_hw_set_gpio(ah, 9, 0);
2259 ath9k_hw_set_gpio(ah, 9, 1);
2261 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2264 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2268 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2269 ath9k_hw_set_delta_slope(ah, chan);
2271 if (AR_SREV_9280_10_OR_LATER(ah))
2272 ath9k_hw_9280_spur_mitigate(ah, chan);
2274 ath9k_hw_spur_mitigate(ah, chan);
2276 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2277 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2278 "error setting board options\n");
2282 ath9k_hw_decrease_chain_power(ah, chan);
2284 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2285 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2287 | AR_STA_ID1_RTS_USE_DEF
2289 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2290 | ahp->ah_staId1Defaults);
2291 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2293 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2294 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2296 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2298 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2299 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2300 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2302 REG_WRITE(ah, AR_ISR, ~0);
2304 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2306 if (AR_SREV_9280_10_OR_LATER(ah)) {
2307 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2310 if (!(ath9k_hw_set_channel(ah, chan)))
2314 for (i = 0; i < AR_NUM_DCU; i++)
2315 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2317 ahp->ah_intrTxqs = 0;
2318 for (i = 0; i < ah->ah_caps.total_queues; i++)
2319 ath9k_hw_resettxqueue(ah, i);
2321 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2322 ath9k_hw_init_qos(ah);
2324 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2325 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2326 ath9k_enable_rfkill(ah);
2328 ath9k_hw_init_user_settings(ah);
2330 REG_WRITE(ah, AR_STA_ID1,
2331 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2333 ath9k_hw_set_dma(ah);
2335 REG_WRITE(ah, AR_OBS, 8);
2337 if (ahp->ah_intrMitigation) {
2339 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2340 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2343 ath9k_hw_init_bb(ah, chan);
2345 if (!ath9k_hw_init_cal(ah, chan))
2348 rx_chainmask = ahp->ah_rxchainmask;
2349 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2350 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2351 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2354 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2356 if (AR_SREV_9100(ah)) {
2358 mask = REG_READ(ah, AR_CFG);
2359 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2360 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2361 "CFG Byte Swap Set 0x%x\n", mask);
2364 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2365 REG_WRITE(ah, AR_CFG, mask);
2366 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2367 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2371 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2378 /************************/
2379 /* Key Cache Management */
2380 /************************/
2382 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2386 if (entry >= ah->ah_caps.keycache_size) {
2387 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2388 "entry %u out of range\n", entry);
2392 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2394 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2395 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2396 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2397 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2398 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2399 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2400 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2401 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2403 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2404 u16 micentry = entry + 64;
2406 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2407 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2408 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2409 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2413 if (ah->ah_curchan == NULL)
2419 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2423 if (entry >= ah->ah_caps.keycache_size) {
2424 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2425 "entry %u out of range\n", entry);
2430 macHi = (mac[5] << 8) | mac[4];
2431 macLo = (mac[3] << 24) |
2436 macLo |= (macHi & 1) << 31;
2441 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2442 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2447 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2448 const struct ath9k_keyval *k,
2449 const u8 *mac, int xorKey)
2451 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2452 u32 key0, key1, key2, key3, key4;
2454 u32 xorMask = xorKey ?
2455 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2456 | ATH9K_KEY_XOR) : 0;
2457 struct ath_hal_5416 *ahp = AH5416(ah);
2459 if (entry >= pCap->keycache_size) {
2460 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2461 "entry %u out of range\n", entry);
2465 switch (k->kv_type) {
2466 case ATH9K_CIPHER_AES_OCB:
2467 keyType = AR_KEYTABLE_TYPE_AES;
2469 case ATH9K_CIPHER_AES_CCM:
2470 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2471 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2472 "AES-CCM not supported by mac rev 0x%x\n",
2476 keyType = AR_KEYTABLE_TYPE_CCM;
2478 case ATH9K_CIPHER_TKIP:
2479 keyType = AR_KEYTABLE_TYPE_TKIP;
2480 if (ATH9K_IS_MIC_ENABLED(ah)
2481 && entry + 64 >= pCap->keycache_size) {
2482 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2483 "entry %u inappropriate for TKIP\n", entry);
2487 case ATH9K_CIPHER_WEP:
2488 if (k->kv_len < LEN_WEP40) {
2489 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2490 "WEP key length %u too small\n", k->kv_len);
2493 if (k->kv_len <= LEN_WEP40)
2494 keyType = AR_KEYTABLE_TYPE_40;
2495 else if (k->kv_len <= LEN_WEP104)
2496 keyType = AR_KEYTABLE_TYPE_104;
2498 keyType = AR_KEYTABLE_TYPE_128;
2500 case ATH9K_CIPHER_CLR:
2501 keyType = AR_KEYTABLE_TYPE_CLR;
2504 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2505 "cipher %u not supported\n", k->kv_type);
2509 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2510 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2511 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2512 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2513 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2514 if (k->kv_len <= LEN_WEP104)
2517 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2518 u16 micentry = entry + 64;
2520 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2521 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2522 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2523 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2524 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2525 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2526 (void) ath9k_hw_keysetmac(ah, entry, mac);
2528 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2529 u32 mic0, mic1, mic2, mic3, mic4;
2531 mic0 = get_unaligned_le32(k->kv_mic + 0);
2532 mic2 = get_unaligned_le32(k->kv_mic + 4);
2533 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2534 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2535 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2536 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2537 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2538 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2539 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2540 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2541 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2542 AR_KEYTABLE_TYPE_CLR);
2547 mic0 = get_unaligned_le32(k->kv_mic + 0);
2548 mic2 = get_unaligned_le32(k->kv_mic + 4);
2549 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2550 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2551 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2552 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2553 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2554 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2555 AR_KEYTABLE_TYPE_CLR);
2557 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2558 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2559 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2560 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2562 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2563 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2564 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2565 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2566 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2567 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2569 (void) ath9k_hw_keysetmac(ah, entry, mac);
2572 if (ah->ah_curchan == NULL)
2578 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2580 if (entry < ah->ah_caps.keycache_size) {
2581 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2582 if (val & AR_KEYTABLE_VALID)
2588 /******************************/
2589 /* Power Management (Chipset) */
2590 /******************************/
2592 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2594 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2596 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2597 AR_RTC_FORCE_WAKE_EN);
2598 if (!AR_SREV_9100(ah))
2599 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2601 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2606 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2608 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2610 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2612 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2613 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2614 AR_RTC_FORCE_WAKE_ON_INT);
2616 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2617 AR_RTC_FORCE_WAKE_EN);
2622 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2629 if ((REG_READ(ah, AR_RTC_STATUS) &
2630 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2631 if (ath9k_hw_set_reset_reg(ah,
2632 ATH9K_RESET_POWER_ON) != true) {
2636 if (AR_SREV_9100(ah))
2637 REG_SET_BIT(ah, AR_RTC_RESET,
2640 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2641 AR_RTC_FORCE_WAKE_EN);
2644 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2645 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2646 if (val == AR_RTC_STATUS_ON)
2649 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2650 AR_RTC_FORCE_WAKE_EN);
2653 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2654 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2659 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2664 bool ath9k_hw_setpower(struct ath_hal *ah,
2665 enum ath9k_power_mode mode)
2667 struct ath_hal_5416 *ahp = AH5416(ah);
2668 static const char *modes[] = {
2674 int status = true, setChip = true;
2676 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2677 modes[ahp->ah_powerMode], modes[mode],
2678 setChip ? "set chip " : "");
2681 case ATH9K_PM_AWAKE:
2682 status = ath9k_hw_set_power_awake(ah, setChip);
2684 case ATH9K_PM_FULL_SLEEP:
2685 ath9k_set_power_sleep(ah, setChip);
2686 ahp->ah_chipFullSleep = true;
2688 case ATH9K_PM_NETWORK_SLEEP:
2689 ath9k_set_power_network_sleep(ah, setChip);
2692 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2693 "Unknown power mode %u\n", mode);
2696 ahp->ah_powerMode = mode;
2701 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2703 struct ath_hal_5416 *ahp = AH5416(ah);
2706 if (ah->ah_isPciExpress != true)
2709 if (ah->ah_config.pcie_powersave_enable == 2)
2715 if (AR_SREV_9280_20_OR_LATER(ah)) {
2716 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2717 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2718 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2721 } else if (AR_SREV_9280(ah) &&
2722 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2723 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2724 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2726 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2727 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2728 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2730 if (ah->ah_config.pcie_clock_req)
2731 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2733 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2735 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2736 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2737 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2739 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2743 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2744 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2745 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2746 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2747 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2748 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2749 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2750 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2751 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2752 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2755 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2757 if (ah->ah_config.pcie_waen) {
2758 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2760 if (AR_SREV_9285(ah))
2761 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2762 else if (AR_SREV_9280(ah))
2763 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2765 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2770 /**********************/
2771 /* Interrupt Handling */
2772 /**********************/
2774 bool ath9k_hw_intrpend(struct ath_hal *ah)
2778 if (AR_SREV_9100(ah))
2781 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2782 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2785 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2786 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2787 && (host_isr != AR_INTR_SPURIOUS))
2793 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2797 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2799 bool fatal_int = false;
2800 struct ath_hal_5416 *ahp = AH5416(ah);
2802 if (!AR_SREV_9100(ah)) {
2803 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2804 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2805 == AR_RTC_STATUS_ON) {
2806 isr = REG_READ(ah, AR_ISR);
2810 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2811 AR_INTR_SYNC_DEFAULT;
2815 if (!isr && !sync_cause)
2819 isr = REG_READ(ah, AR_ISR);
2823 if (isr & AR_ISR_BCNMISC) {
2825 isr2 = REG_READ(ah, AR_ISR_S2);
2826 if (isr2 & AR_ISR_S2_TIM)
2827 mask2 |= ATH9K_INT_TIM;
2828 if (isr2 & AR_ISR_S2_DTIM)
2829 mask2 |= ATH9K_INT_DTIM;
2830 if (isr2 & AR_ISR_S2_DTIMSYNC)
2831 mask2 |= ATH9K_INT_DTIMSYNC;
2832 if (isr2 & (AR_ISR_S2_CABEND))
2833 mask2 |= ATH9K_INT_CABEND;
2834 if (isr2 & AR_ISR_S2_GTT)
2835 mask2 |= ATH9K_INT_GTT;
2836 if (isr2 & AR_ISR_S2_CST)
2837 mask2 |= ATH9K_INT_CST;
2840 isr = REG_READ(ah, AR_ISR_RAC);
2841 if (isr == 0xffffffff) {
2846 *masked = isr & ATH9K_INT_COMMON;
2848 if (ahp->ah_intrMitigation) {
2849 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2850 *masked |= ATH9K_INT_RX;
2853 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2854 *masked |= ATH9K_INT_RX;
2856 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2860 *masked |= ATH9K_INT_TX;
2862 s0_s = REG_READ(ah, AR_ISR_S0_S);
2863 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2864 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2866 s1_s = REG_READ(ah, AR_ISR_S1_S);
2867 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2868 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2871 if (isr & AR_ISR_RXORN) {
2872 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2873 "receive FIFO overrun interrupt\n");
2876 if (!AR_SREV_9100(ah)) {
2877 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2878 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2879 if (isr5 & AR_ISR_S5_TIM_TIMER)
2880 *masked |= ATH9K_INT_TIM_TIMER;
2887 if (AR_SREV_9100(ah))
2893 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2897 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2898 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2899 "received PCI FATAL interrupt\n");
2901 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2902 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2903 "received PCI PERR interrupt\n");
2906 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2907 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2908 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2909 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2910 REG_WRITE(ah, AR_RC, 0);
2911 *masked |= ATH9K_INT_FATAL;
2913 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2914 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2915 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2918 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2919 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2925 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2927 return AH5416(ah)->ah_maskReg;
2930 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2932 struct ath_hal_5416 *ahp = AH5416(ah);
2933 u32 omask = ahp->ah_maskReg;
2935 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2937 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2939 if (omask & ATH9K_INT_GLOBAL) {
2940 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2941 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2942 (void) REG_READ(ah, AR_IER);
2943 if (!AR_SREV_9100(ah)) {
2944 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2945 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2947 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2948 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2952 mask = ints & ATH9K_INT_COMMON;
2955 if (ints & ATH9K_INT_TX) {
2956 if (ahp->ah_txOkInterruptMask)
2957 mask |= AR_IMR_TXOK;
2958 if (ahp->ah_txDescInterruptMask)
2959 mask |= AR_IMR_TXDESC;
2960 if (ahp->ah_txErrInterruptMask)
2961 mask |= AR_IMR_TXERR;
2962 if (ahp->ah_txEolInterruptMask)
2963 mask |= AR_IMR_TXEOL;
2965 if (ints & ATH9K_INT_RX) {
2966 mask |= AR_IMR_RXERR;
2967 if (ahp->ah_intrMitigation)
2968 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2970 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2971 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2972 mask |= AR_IMR_GENTMR;
2975 if (ints & (ATH9K_INT_BMISC)) {
2976 mask |= AR_IMR_BCNMISC;
2977 if (ints & ATH9K_INT_TIM)
2978 mask2 |= AR_IMR_S2_TIM;
2979 if (ints & ATH9K_INT_DTIM)
2980 mask2 |= AR_IMR_S2_DTIM;
2981 if (ints & ATH9K_INT_DTIMSYNC)
2982 mask2 |= AR_IMR_S2_DTIMSYNC;
2983 if (ints & ATH9K_INT_CABEND)
2984 mask2 |= (AR_IMR_S2_CABEND);
2987 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2988 mask |= AR_IMR_BCNMISC;
2989 if (ints & ATH9K_INT_GTT)
2990 mask2 |= AR_IMR_S2_GTT;
2991 if (ints & ATH9K_INT_CST)
2992 mask2 |= AR_IMR_S2_CST;
2995 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2996 REG_WRITE(ah, AR_IMR, mask);
2997 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2999 AR_IMR_S2_DTIMSYNC |
3003 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3004 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3005 ahp->ah_maskReg = ints;
3007 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3008 if (ints & ATH9K_INT_TIM_TIMER)
3009 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3011 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3014 if (ints & ATH9K_INT_GLOBAL) {
3015 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3016 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3017 if (!AR_SREV_9100(ah)) {
3018 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3020 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3023 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3024 AR_INTR_SYNC_DEFAULT);
3025 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3026 AR_INTR_SYNC_DEFAULT);
3028 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3029 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3035 /*******************/
3036 /* Beacon Handling */
3037 /*******************/
3039 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3041 struct ath_hal_5416 *ahp = AH5416(ah);
3044 ahp->ah_beaconInterval = beacon_period;
3046 switch (ah->ah_opmode) {
3047 case NL80211_IFTYPE_STATION:
3048 case NL80211_IFTYPE_MONITOR:
3049 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3050 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3051 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3052 flags |= AR_TBTT_TIMER_EN;
3054 case NL80211_IFTYPE_ADHOC:
3055 REG_SET_BIT(ah, AR_TXCFG,
3056 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3057 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3058 TU_TO_USEC(next_beacon +
3059 (ahp->ah_atimWindow ? ahp->
3060 ah_atimWindow : 1)));
3061 flags |= AR_NDP_TIMER_EN;
3062 case NL80211_IFTYPE_AP:
3063 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3064 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3065 TU_TO_USEC(next_beacon -
3067 dma_beacon_response_time));
3068 REG_WRITE(ah, AR_NEXT_SWBA,
3069 TU_TO_USEC(next_beacon -
3071 sw_beacon_response_time));
3073 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3076 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3077 "%s: unsupported opmode: %d\n",
3078 __func__, ah->ah_opmode);
3083 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3084 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3085 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3086 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3088 beacon_period &= ~ATH9K_BEACON_ENA;
3089 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3090 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3091 ath9k_hw_reset_tsf(ah);
3094 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3097 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3098 const struct ath9k_beacon_state *bs)
3100 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3101 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3103 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3105 REG_WRITE(ah, AR_BEACON_PERIOD,
3106 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3107 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3108 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3110 REG_RMW_FIELD(ah, AR_RSSI_THR,
3111 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3113 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3115 if (bs->bs_sleepduration > beaconintval)
3116 beaconintval = bs->bs_sleepduration;
3118 dtimperiod = bs->bs_dtimperiod;
3119 if (bs->bs_sleepduration > dtimperiod)
3120 dtimperiod = bs->bs_sleepduration;
3122 if (beaconintval == dtimperiod)
3123 nextTbtt = bs->bs_nextdtim;
3125 nextTbtt = bs->bs_nexttbtt;
3127 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3128 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3129 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3130 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3132 REG_WRITE(ah, AR_NEXT_DTIM,
3133 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3134 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3136 REG_WRITE(ah, AR_SLEEP1,
3137 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3138 | AR_SLEEP1_ASSUME_DTIM);
3140 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3141 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3143 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3145 REG_WRITE(ah, AR_SLEEP2,
3146 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3148 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3149 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3151 REG_SET_BIT(ah, AR_TIMER_MODE,
3152 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3157 /*******************/
3158 /* HW Capabilities */
3159 /*******************/
3161 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3163 struct ath_hal_5416 *ahp = AH5416(ah);
3164 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3165 u16 capField = 0, eeval;
3167 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3169 ah->ah_currentRD = eeval;
3171 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3172 ah->ah_currentRDExt = eeval;
3174 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3176 if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3177 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3178 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3179 ah->ah_currentRD += 5;
3180 else if (ah->ah_currentRD == 0x41)
3181 ah->ah_currentRD = 0x43;
3182 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3183 "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3186 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3187 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3189 if (eeval & AR5416_OPFLAGS_11A) {
3190 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3191 if (ah->ah_config.ht_enable) {
3192 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3193 set_bit(ATH9K_MODE_11NA_HT20,
3194 pCap->wireless_modes);
3195 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3196 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3197 pCap->wireless_modes);
3198 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3199 pCap->wireless_modes);
3204 if (eeval & AR5416_OPFLAGS_11G) {
3205 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3206 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3207 if (ah->ah_config.ht_enable) {
3208 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3209 set_bit(ATH9K_MODE_11NG_HT20,
3210 pCap->wireless_modes);
3211 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3212 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3213 pCap->wireless_modes);
3214 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3215 pCap->wireless_modes);
3220 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3221 if ((ah->ah_isPciExpress)
3222 || (eeval & AR5416_OPFLAGS_11A)) {
3223 pCap->rx_chainmask =
3224 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3226 pCap->rx_chainmask =
3227 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3230 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3231 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3233 pCap->low_2ghz_chan = 2312;
3234 pCap->high_2ghz_chan = 2732;
3236 pCap->low_5ghz_chan = 4920;
3237 pCap->high_5ghz_chan = 6100;
3239 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3240 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3241 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3243 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3244 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3245 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3247 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3249 if (ah->ah_config.ht_enable)
3250 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3252 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3254 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3255 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3256 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3257 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3259 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3260 pCap->total_queues =
3261 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3263 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3265 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3266 pCap->keycache_size =
3267 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3269 pCap->keycache_size = AR_KEYTABLE_SIZE;
3271 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3272 pCap->num_mr_retries = 4;
3273 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3275 if (AR_SREV_9285_10_OR_LATER(ah))
3276 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3277 else if (AR_SREV_9280_10_OR_LATER(ah))
3278 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3280 pCap->num_gpio_pins = AR_NUM_GPIO;
3282 if (AR_SREV_9280_10_OR_LATER(ah)) {
3283 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3284 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3286 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3287 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3290 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3291 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3292 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3294 pCap->rts_aggr_limit = (8 * 1024);
3297 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3299 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3300 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3301 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3302 ah->ah_rfkill_gpio =
3303 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3304 ah->ah_rfkill_polarity =
3305 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3307 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3311 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3312 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3313 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3314 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3315 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3316 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3318 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3320 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3321 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3323 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3325 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3327 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3328 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3329 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3330 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3333 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3334 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3337 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3339 pCap->num_antcfg_5ghz =
3340 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3341 pCap->num_antcfg_2ghz =
3342 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3344 if (AR_SREV_9280_10_OR_LATER(ah)) {
3345 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3346 ah->ah_btactive_gpio = 6;
3347 ah->ah_wlanactive_gpio = 5;
3353 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3354 u32 capability, u32 *result)
3356 struct ath_hal_5416 *ahp = AH5416(ah);
3357 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3360 case ATH9K_CAP_CIPHER:
3361 switch (capability) {
3362 case ATH9K_CIPHER_AES_CCM:
3363 case ATH9K_CIPHER_AES_OCB:
3364 case ATH9K_CIPHER_TKIP:
3365 case ATH9K_CIPHER_WEP:
3366 case ATH9K_CIPHER_MIC:
3367 case ATH9K_CIPHER_CLR:
3372 case ATH9K_CAP_TKIP_MIC:
3373 switch (capability) {
3377 return (ahp->ah_staId1Defaults &
3378 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3381 case ATH9K_CAP_TKIP_SPLIT:
3382 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3384 case ATH9K_CAP_WME_TKIPMIC:
3386 case ATH9K_CAP_PHYCOUNTERS:
3387 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3388 case ATH9K_CAP_DIVERSITY:
3389 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3390 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3392 case ATH9K_CAP_PHYDIAG:
3394 case ATH9K_CAP_MCAST_KEYSRCH:
3395 switch (capability) {
3399 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3402 return (ahp->ah_staId1Defaults &
3403 AR_STA_ID1_MCAST_KSRCH) ? true :
3408 case ATH9K_CAP_TSF_ADJUST:
3409 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3411 case ATH9K_CAP_RFSILENT:
3412 if (capability == 3)
3414 case ATH9K_CAP_ANT_CFG_2GHZ:
3415 *result = pCap->num_antcfg_2ghz;
3417 case ATH9K_CAP_ANT_CFG_5GHZ:
3418 *result = pCap->num_antcfg_5ghz;
3420 case ATH9K_CAP_TXPOW:
3421 switch (capability) {
3425 *result = ah->ah_powerLimit;
3428 *result = ah->ah_maxPowerLevel;
3431 *result = ah->ah_tpScale;
3440 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3441 u32 capability, u32 setting, int *status)
3443 struct ath_hal_5416 *ahp = AH5416(ah);
3447 case ATH9K_CAP_TKIP_MIC:
3449 ahp->ah_staId1Defaults |=
3450 AR_STA_ID1_CRPT_MIC_ENABLE;
3452 ahp->ah_staId1Defaults &=
3453 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3455 case ATH9K_CAP_DIVERSITY:
3456 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3458 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3460 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3461 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3463 case ATH9K_CAP_MCAST_KEYSRCH:
3465 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3467 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3469 case ATH9K_CAP_TSF_ADJUST:
3471 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3473 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3480 /****************************/
3481 /* GPIO / RFKILL / Antennae */
3482 /****************************/
3484 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3488 u32 gpio_shift, tmp;
3491 addr = AR_GPIO_OUTPUT_MUX3;
3493 addr = AR_GPIO_OUTPUT_MUX2;
3495 addr = AR_GPIO_OUTPUT_MUX1;
3497 gpio_shift = (gpio % 6) * 5;
3499 if (AR_SREV_9280_20_OR_LATER(ah)
3500 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3501 REG_RMW(ah, addr, (type << gpio_shift),
3502 (0x1f << gpio_shift));
3504 tmp = REG_READ(ah, addr);
3505 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3506 tmp &= ~(0x1f << gpio_shift);
3507 tmp |= (type << gpio_shift);
3508 REG_WRITE(ah, addr, tmp);
3512 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3516 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3518 gpio_shift = gpio << 1;
3522 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3523 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3526 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3528 #define MS_REG_READ(x, y) \
3529 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3531 if (gpio >= ah->ah_caps.num_gpio_pins)
3534 if (AR_SREV_9285_10_OR_LATER(ah))
3535 return MS_REG_READ(AR9285, gpio) != 0;
3536 else if (AR_SREV_9280_10_OR_LATER(ah))
3537 return MS_REG_READ(AR928X, gpio) != 0;
3539 return MS_REG_READ(AR, gpio) != 0;
3542 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3547 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3549 gpio_shift = 2 * gpio;
3553 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3554 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3557 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3559 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3563 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3564 void ath9k_enable_rfkill(struct ath_hal *ah)
3566 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3567 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3569 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3570 AR_GPIO_INPUT_MUX2_RFSILENT);
3572 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3573 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3577 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3579 struct ath9k_channel *chan = ah->ah_curchan;
3580 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3582 u32 halNumAntConfig;
3584 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3585 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3587 if (cfg < halNumAntConfig) {
3588 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3589 cfg, &ant_config)) {
3590 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3598 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3600 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3603 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3605 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3608 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3609 enum ath9k_ant_setting settings,
3610 struct ath9k_channel *chan,
3615 struct ath_hal_5416 *ahp = AH5416(ah);
3616 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3618 if (AR_SREV_9280(ah)) {
3619 if (!tx_chainmask_cfg) {
3621 tx_chainmask_cfg = *tx_chainmask;
3622 rx_chainmask_cfg = *rx_chainmask;
3626 case ATH9K_ANT_FIXED_A:
3627 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3628 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3629 *antenna_cfgd = true;
3631 case ATH9K_ANT_FIXED_B:
3632 if (ah->ah_caps.tx_chainmask >
3633 ATH9K_ANTENNA1_CHAINMASK) {
3634 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3636 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3637 *antenna_cfgd = true;
3639 case ATH9K_ANT_VARIABLE:
3640 *tx_chainmask = tx_chainmask_cfg;
3641 *rx_chainmask = rx_chainmask_cfg;
3642 *antenna_cfgd = true;
3648 ahp->ah_diversityControl = settings;
3654 /*********************/
3655 /* General Operation */
3656 /*********************/
3658 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3660 u32 bits = REG_READ(ah, AR_RX_FILTER);
3661 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3663 if (phybits & AR_PHY_ERR_RADAR)
3664 bits |= ATH9K_RX_FILTER_PHYRADAR;
3665 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3666 bits |= ATH9K_RX_FILTER_PHYERR;
3671 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3675 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3677 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3678 phybits |= AR_PHY_ERR_RADAR;
3679 if (bits & ATH9K_RX_FILTER_PHYERR)
3680 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3681 REG_WRITE(ah, AR_PHY_ERR, phybits);
3684 REG_WRITE(ah, AR_RXCFG,
3685 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3687 REG_WRITE(ah, AR_RXCFG,
3688 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3691 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3693 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3696 bool ath9k_hw_disable(struct ath_hal *ah)
3698 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3701 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3704 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3706 struct ath9k_channel *chan = ah->ah_curchan;
3708 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3710 if (ath9k_hw_set_txpower(ah, chan,
3711 ath9k_regd_get_ctl(ah, chan),
3712 ath9k_regd_get_antenna_allowed(ah, chan),
3713 chan->maxRegTxPower * 2,
3714 min((u32) MAX_RATE_POWER,
3715 (u32) ah->ah_powerLimit)) != 0)
3721 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3723 struct ath_hal_5416 *ahp = AH5416(ah);
3725 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3728 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3730 struct ath_hal_5416 *ahp = AH5416(ah);
3732 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3737 void ath9k_hw_setopmode(struct ath_hal *ah)
3739 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3742 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3744 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3745 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3748 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3750 struct ath_hal_5416 *ahp = AH5416(ah);
3752 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3755 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3757 struct ath_hal_5416 *ahp = AH5416(ah);
3759 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3761 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3762 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3767 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3769 struct ath_hal_5416 *ahp = AH5416(ah);
3771 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3772 ahp->ah_assocId = assocId;
3774 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3775 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3776 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3779 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3783 tsf = REG_READ(ah, AR_TSF_U32);
3784 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3789 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3794 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3797 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3798 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3803 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3806 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3808 struct ath_hal_5416 *ahp = AH5416(ah);
3811 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3813 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3818 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3820 struct ath_hal_5416 *ahp = AH5416(ah);
3822 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3823 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3824 ahp->ah_slottime = (u32) -1;
3827 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3828 ahp->ah_slottime = us;
3833 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3837 if (mode == ATH9K_HT_MACMODE_2040 &&
3838 !ah->ah_config.cwm_ignore_extcca)
3839 macmode = AR_2040_JOINED_RX_CLEAR;
3843 REG_WRITE(ah, AR_2040_MODE, macmode);
3846 /***************************/
3847 /* Bluetooth Coexistence */
3848 /***************************/
3850 void ath9k_hw_btcoex_enable(struct ath_hal *ah)
3852 /* connect bt_active to baseband */
3853 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3854 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3855 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3857 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3858 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3860 /* Set input mux for bt_active to gpio pin */
3861 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3862 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3863 ah->ah_btactive_gpio);
3865 /* Configure the desired gpio port for input */
3866 ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio);
3868 /* Configure the desired GPIO port for TX_FRAME output */
3869 ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio,
3870 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);