2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/pci.h>
22 #include <net/mac80211.h>
23 #include <linux/leds.h>
24 #include <linux/rfkill.h>
31 /* Macro to expand scalars to 64-bit objects */
33 #define ito64(x) (sizeof(x) == 8) ? \
34 (((unsigned long long int)(x)) & (0xff)) : \
36 (((unsigned long long int)(x)) & 0xffff) : \
37 ((sizeof(x) == 32) ? \
38 (((unsigned long long int)(x)) & 0xffffffff) : \
39 (unsigned long long int)(x))
41 /* increment with wrap-around */
42 #define INCR(_l, _sz) do { \
44 (_l) &= ((_sz) - 1); \
47 /* decrement with wrap-around */
48 #define DECR(_l, _sz) do { \
50 (_l) &= ((_sz) - 1); \
53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
55 #define ASSERT(exp) do { \
56 if (unlikely(!(exp))) { \
61 #define TSF_TO_TU(_h,_l) \
62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
66 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
69 ATH_DBG_RESET = 0x00000001,
70 ATH_DBG_REG_IO = 0x00000002,
71 ATH_DBG_QUEUE = 0x00000004,
72 ATH_DBG_EEPROM = 0x00000008,
73 ATH_DBG_CALIBRATE = 0x00000010,
74 ATH_DBG_CHANNEL = 0x00000020,
75 ATH_DBG_INTERRUPT = 0x00000040,
76 ATH_DBG_REGULATORY = 0x00000080,
77 ATH_DBG_ANI = 0x00000100,
78 ATH_DBG_POWER_MGMT = 0x00000200,
79 ATH_DBG_XMIT = 0x00000400,
80 ATH_DBG_BEACON = 0x00001000,
81 ATH_DBG_CONFIG = 0x00002000,
82 ATH_DBG_KEYCACHE = 0x00004000,
83 ATH_DBG_FATAL = 0x00008000,
84 ATH_DBG_ANY = 0xffffffff
87 #define DBG_DEFAULT (ATH_DBG_FATAL)
89 #ifdef CONFIG_ATH9K_DEBUG
93 struct dentry *debugfs_root;
94 struct dentry *debugfs_phy;
97 void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
98 int ath9k_init_debug(struct ath_softc *sc);
99 void ath9k_exit_debug(struct ath_softc *sc);
103 static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
104 const char *fmt, ...)
108 static inline int ath9k_init_debug(struct ath_softc *sc)
113 static inline void ath9k_exit_debug(struct ath_softc *sc)
117 #endif /* CONFIG_ATH9K_DEBUG */
122 u16 txpowlimit_override;
127 /*************************/
128 /* Descriptor Management */
129 /*************************/
131 #define ATH_TXBUF_RESET(_bf) do { \
132 (_bf)->bf_status = 0; \
133 (_bf)->bf_lastbf = NULL; \
134 (_bf)->bf_lastfrm = NULL; \
135 (_bf)->bf_next = NULL; \
136 memset(&((_bf)->bf_state), 0, \
137 sizeof(struct ath_buf_state)); \
147 BUF_SHORT_PREAMBLE = BIT(6),
150 BUF_AGGR_BURST = BIT(9),
151 BUF_CALC_AIRTIME = BIT(10),
154 struct ath_buf_state {
155 int bfs_nframes; /* # frames in aggregate */
156 u16 bfs_al; /* length of aggregate */
157 u16 bfs_frmlen; /* length of frame */
158 int bfs_seqno; /* sequence number */
159 int bfs_tidno; /* tid of this frame */
160 int bfs_retries; /* current retries */
161 u32 bf_type; /* BUF_* (enum buffer_type) */
163 enum ath9k_key_type bfs_keytype;
166 #define bf_nframes bf_state.bfs_nframes
167 #define bf_al bf_state.bfs_al
168 #define bf_frmlen bf_state.bfs_frmlen
169 #define bf_retries bf_state.bfs_retries
170 #define bf_seqno bf_state.bfs_seqno
171 #define bf_tidno bf_state.bfs_tidno
172 #define bf_rcs bf_state.bfs_rcs
173 #define bf_keyix bf_state.bfs_keyix
174 #define bf_keytype bf_state.bfs_keytype
175 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
176 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
177 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
178 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
179 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
180 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
181 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
182 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
183 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
184 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
187 * Abstraction of a contiguous buffer to transmit/receive. There is only
188 * a single hw descriptor encapsulated here.
191 struct list_head list;
192 struct list_head *last;
193 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
195 struct ath_buf *bf_lastfrm; /* last buf of this frame */
196 struct ath_buf *bf_next; /* next subframe in the aggregate */
197 void *bf_mpdu; /* enclosing frame structure */
198 struct ath_desc *bf_desc; /* virtual addr of desc */
199 dma_addr_t bf_daddr; /* physical addr of desc */
200 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
202 u16 bf_flags; /* tx descriptor flags */
203 struct ath_buf_state bf_state; /* buffer state */
204 dma_addr_t bf_dmacontext;
207 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
209 /* hw processing complete, desc processed by hal */
210 #define ATH_BUFSTATUS_DONE 0x00000001
211 /* hw processing complete, desc hold for hw */
212 #define ATH_BUFSTATUS_STALE 0x00000002
213 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
214 #define ATH_BUFSTATUS_FREE 0x00000004
216 /* DMA state for tx/rx descriptors */
220 struct ath_desc *dd_desc; /* descriptors */
221 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
222 u32 dd_desc_len; /* size of dd_desc */
223 struct ath_buf *dd_bufptr; /* associated buffers */
224 dma_addr_t dd_dmacontext;
227 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
228 struct list_head *head, const char *name,
229 int nbuf, int ndesc);
230 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
231 struct list_head *head);
237 #define ATH_MAX_ANTENNA 3
238 #define ATH_RXBUF 512
239 #define WME_NUM_TID 16
241 int ath_startrecv(struct ath_softc *sc);
242 bool ath_stoprecv(struct ath_softc *sc);
243 void ath_flushrecv(struct ath_softc *sc);
244 u32 ath_calcrxfilter(struct ath_softc *sc);
245 int ath_rx_init(struct ath_softc *sc, int nbufs);
246 void ath_rx_cleanup(struct ath_softc *sc);
247 int ath_rx_tasklet(struct ath_softc *sc, int flush);
249 #define ATH_TXBUF 512
250 #define ATH_TXMAXTRY 13
251 #define ATH_11N_TXMAXTRY 10
252 #define ATH_MGT_TXMAXTRY 4
253 #define WME_BA_BMP_SIZE 64
254 #define WME_MAX_BA WME_BA_BMP_SIZE
255 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
256 #define TID_TO_WME_AC(_tid) \
257 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
258 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
259 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
270 u32 axq_qnum; /* hardware q number */
271 u32 *axq_link; /* link ptr in last TX desc */
272 struct list_head axq_q; /* transmit queue */
274 unsigned long axq_lockflags; /* intr state when must cli */
275 u32 axq_depth; /* queue depth */
276 u8 axq_aggr_depth; /* aggregates queued */
277 u32 axq_totalqueued; /* total ever queued */
279 bool stopped; /* Is mac80211 queue stopped ? */
280 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
282 /* first desc of the last descriptor that contains CTS */
283 struct ath_desc *axq_lastdsWithCTS;
285 /* final desc of the gating desc that determines whether
286 lastdsWithCTS has been DMA'ed or not */
287 struct ath_desc *axq_gatingds;
289 struct list_head axq_acq;
292 #define AGGR_CLEANUP BIT(1)
293 #define AGGR_ADDBA_COMPLETE BIT(2)
294 #define AGGR_ADDBA_PROGRESS BIT(3)
296 /* per TID aggregate tx state for a destination */
298 struct list_head list; /* round-robin tid entry */
299 struct list_head buf_q; /* pending buffers */
301 struct ath_atx_ac *ac;
302 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
307 int baw_head; /* first un-acked tx buffer */
308 int baw_tail; /* next unused tx buffer slot */
312 int addba_exchangeattempts;
315 /* per access-category aggregate tx state for a destination */
317 int sched; /* dest-ac is scheduled */
318 int qnum; /* H/W queue number associated
320 struct list_head list; /* round-robin txq entry */
321 struct list_head tid_q; /* queue of TIDs with buffers */
324 /* per dest tx state */
326 struct ath_atx_tid tid[WME_NUM_TID];
327 struct ath_atx_ac ac[WME_NUM_AC];
330 /* per-frame tx control block */
331 struct ath_tx_control {
336 /* per frame tx status block */
337 struct ath_xmit_status {
338 int retries; /* number of retries to successufully
339 transmit this frame */
340 int flags; /* status of transmit */
341 #define ATH_TX_ERROR 0x01
342 #define ATH_TX_XRETRY 0x02
343 #define ATH_TX_BAR 0x04
346 /* All RSSI values are noise floor adjusted */
349 int rssictl[ATH_MAX_ANTENNA];
350 int rssiextn[ATH_MAX_ANTENNA];
355 /* if any of ctl,extn chain rssis are valid */
356 #define ATH_TX_CHAIN_RSSI_VALID 0x01
357 /* if extn chain rssis are valid */
358 #define ATH_TX_RSSI_EXTN_VALID 0x02
359 u32 airtime; /* time on air per final tx rate */
362 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
363 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
364 int ath_tx_setup(struct ath_softc *sc, int haltype);
365 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
366 void ath_tx_draintxq(struct ath_softc *sc,
367 struct ath_txq *txq, bool retry_tx);
368 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
369 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
370 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
371 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
372 int ath_tx_init(struct ath_softc *sc, int nbufs);
373 int ath_tx_cleanup(struct ath_softc *sc);
374 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
375 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
376 int ath_txq_update(struct ath_softc *sc, int qnum,
377 struct ath9k_tx_queue_info *q);
378 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
379 struct ath_tx_control *txctl);
380 void ath_tx_tasklet(struct ath_softc *sc);
381 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
382 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
383 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
385 /**********************/
386 /* Node / Aggregation */
387 /**********************/
389 #define ADDBA_EXCHANGE_ATTEMPTS 10
390 #define ATH_AGGR_DELIM_SZ 4
391 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
392 /* number of delimiters for encryption padding */
393 #define ATH_AGGR_ENCRYPTDELIM 10
394 /* minimum h/w qdepth to be sustained to maximize aggregation */
395 #define ATH_AGGR_MIN_QDEPTH 2
396 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
397 #define IEEE80211_SEQ_SEQ_SHIFT 4
398 #define IEEE80211_SEQ_MAX 4096
399 #define IEEE80211_MIN_AMPDU_BUF 0x8
400 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
402 /* return whether a bit at index _n in bitmap _bm is set
403 * _sz is the size of the bitmap */
404 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
405 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
407 /* return block-ack bitmap index given sequence and starting sequence */
408 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
410 /* returns delimiter padding required given the packet length */
411 #define ATH_AGGR_GET_NDELIM(_len) \
412 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
413 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
415 #define BAW_WITHIN(_start, _bawsz, _seqno) \
416 ((((_seqno) - (_start)) & 4095) < (_bawsz))
418 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
419 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
420 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
421 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
423 enum ATH_AGGR_STATUS {
431 struct aggr_rifs_param {
432 int param_max_frames;
436 struct ath_rc_series *param_rcs;
439 /* Per-node aggregation state */
440 struct ath_node_aggr {
445 struct ath_softc *an_sc;
446 struct ath_node_aggr an_aggr;
451 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid);
452 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
453 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tidno);
454 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
456 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
457 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
464 * Define the scheme that we select MAC address for multiple
465 * BSS on the same radio. The very first VAP will just use the MAC
466 * address from the EEPROM. For the next 3 VAPs, we set the
467 * U/L bit (bit 1) in MAC address, and use the next two bits as the
471 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
472 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
476 enum ath9k_opmode av_opmode;
477 struct ath_buf *av_bcbuf;
478 struct ath_tx_control av_btxctl;
481 /*******************/
482 /* Beacon Handling */
483 /*******************/
486 * Regardless of the number of beacons we stagger, (i.e. regardless of the
487 * number of BSSIDs) if a given beacon does not go out even after waiting this
488 * number of beacon intervals, the game's up.
490 #define BSTUCK_THRESH (9 * ATH_BCBUF)
492 #define ATH_DEFAULT_BINTVAL 100 /* TU */
493 #define ATH_DEFAULT_BMISS_LIMIT 10
494 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
496 struct ath_beacon_config {
506 } u; /* last received beacon/probe response timestamp of this BSS. */
509 void ath9k_beacon_tasklet(unsigned long data);
510 void ath_beacon_config(struct ath_softc *sc, int if_id);
511 int ath_beaconq_setup(struct ath_hal *ah);
512 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
513 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
514 void ath_beacon_sync(struct ath_softc *sc, int if_id);
520 /* ANI values for STA only.
521 FIXME: Add appropriate values for AP later */
523 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
524 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
525 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
526 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
530 int16_t sc_noise_floor;
531 unsigned int sc_longcal_timer;
532 unsigned int sc_shortcal_timer;
533 unsigned int sc_resetcal_timer;
534 unsigned int sc_checkani_timer;
535 struct timer_list timer;
538 /********************/
540 /********************/
542 #define ATH_LED_PIN 1
552 struct ath_softc *sc;
553 struct led_classdev led_cdev;
554 enum ath_led_type led_type;
560 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
563 struct rfkill *rfkill;
564 struct delayed_work rfkill_poll;
565 char rfkill_name[32];
568 /********************/
569 /* Main driver core */
570 /********************/
573 * Default cache line size, in bytes.
574 * Used when PCI device not fully initialized by bootrom/BIOS
576 #define DEFAULT_CACHELINE 32
577 #define ATH_DEFAULT_NOISE_FLOOR -95
578 #define ATH_REGCLASSIDS_MAX 10
579 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
580 #define ATH_MAX_SW_RETRIES 10
581 #define ATH_CHAN_MAX 255
582 #define IEEE80211_WEP_NKID 4 /* number of key ids */
583 #define IEEE80211_RATE_VAL 0x7f
585 * The key cache is used for h/w cipher state and also for
586 * tracking station state such as the current tx antenna.
587 * We also setup a mapping table between key cache slot indices
588 * and station state to short-circuit node lookups on rx.
589 * Different parts have different size key caches. We handle
590 * up to ATH_KEYMAX entries (could dynamically allocate state).
592 #define ATH_KEYMAX 128 /* max key cache size we handle */
594 #define ATH_IF_ID_ANY 0xff
595 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
596 #define ATH_RSSI_DUMMY_MARKER 0x127
597 #define ATH_RATE_DUMMY_MARKER 0
605 #define SC_OP_INVALID BIT(0)
606 #define SC_OP_BEACONS BIT(1)
607 #define SC_OP_RXAGGR BIT(2)
608 #define SC_OP_TXAGGR BIT(3)
609 #define SC_OP_CHAINMASK_UPDATE BIT(4)
610 #define SC_OP_FULL_RESET BIT(5)
611 #define SC_OP_NO_RESET BIT(6)
612 #define SC_OP_PREAMBLE_SHORT BIT(7)
613 #define SC_OP_PROTECT_ENABLE BIT(8)
614 #define SC_OP_RXFLUSH BIT(9)
615 #define SC_OP_LED_ASSOCIATED BIT(10)
616 #define SC_OP_RFKILL_REGISTERED BIT(11)
617 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
618 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
621 struct ieee80211_hw *hw;
622 struct pci_dev *pdev;
623 struct tasklet_struct intr_tq;
624 struct tasklet_struct bcon_tasklet;
625 struct ath_config sc_config;
626 struct ath_hal *sc_ah;
629 u8 sc_curbssid[ETH_ALEN];
630 u8 sc_myaddr[ETH_ALEN];
631 u8 sc_bssidmask[ETH_ALEN];
633 #ifdef CONFIG_ATH9K_DEBUG
634 struct ath9k_debug sc_debug;
637 u32 sc_flags; /* SC_OP_* */
638 unsigned int rx_filter;
642 int sc_slotupdate; /* slot to next advance fsm */
644 int sc_bslot[ATH_BCBUF];
647 enum ath9k_int sc_imask;
648 enum wireless_mode sc_curmode;
649 enum PROT_MODE sc_protmode;
653 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
659 struct ath9k_node_stats sc_halstats;
660 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
661 enum ath9k_ht_macmode tx_chan_width;
663 #ifdef CONFIG_SLOW_ANT_DIV
664 struct ath_antdiv sc_antdiv;
667 OK, /* no change needed */
668 UPDATE, /* update pending */
669 COMMIT /* beacon sent, commit change */
670 } sc_updateslot; /* slot time update fsm */
674 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
675 u8 sc_splitmic; /* split TKIP MIC keys */
678 struct list_head sc_rxbuf;
679 struct ath_descdma sc_rxdma;
684 struct list_head sc_txbuf;
685 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
686 struct ath_descdma sc_txdma;
688 int sc_haltype2q[ATH9K_WME_AC_VO+1];
689 u16 seq_no; /* TX sequence number */
692 struct ath9k_tx_queue_info sc_beacon_qi;
693 struct ath_descdma sc_bdma;
694 struct ath_txq *sc_cabq;
695 struct list_head sc_bbuf;
702 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
703 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
707 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
708 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
711 spinlock_t sc_rxflushlock;
712 spinlock_t sc_rxbuflock;
713 spinlock_t sc_txbuflock;
714 spinlock_t sc_resetlock;
717 struct ath_led radio_led;
718 struct ath_led assoc_led;
719 struct ath_led tx_led;
720 struct ath_led rx_led;
723 struct ath_rfkill rf_kill;
726 struct ath_ani sc_ani;
729 int ath_reset(struct ath_softc *sc, bool retry_tx);
730 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
731 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
732 int ath_cabq_update(struct ath_softc *);