2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/pci.h>
22 #include <net/mac80211.h>
23 #include <linux/leds.h>
24 #include <linux/rfkill.h>
31 /* Macro to expand scalars to 64-bit objects */
33 #define ito64(x) (sizeof(x) == 8) ? \
34 (((unsigned long long int)(x)) & (0xff)) : \
36 (((unsigned long long int)(x)) & 0xffff) : \
37 ((sizeof(x) == 32) ? \
38 (((unsigned long long int)(x)) & 0xffffffff) : \
39 (unsigned long long int)(x))
41 /* increment with wrap-around */
42 #define INCR(_l, _sz) do { \
44 (_l) &= ((_sz) - 1); \
47 /* decrement with wrap-around */
48 #define DECR(_l, _sz) do { \
50 (_l) &= ((_sz) - 1); \
53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
55 #define ASSERT(exp) do { \
56 if (unlikely(!(exp))) { \
61 #define TSF_TO_TU(_h,_l) \
62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
66 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
69 ATH_DBG_RESET = 0x00000001,
70 ATH_DBG_REG_IO = 0x00000002,
71 ATH_DBG_QUEUE = 0x00000004,
72 ATH_DBG_EEPROM = 0x00000008,
73 ATH_DBG_CALIBRATE = 0x00000010,
74 ATH_DBG_CHANNEL = 0x00000020,
75 ATH_DBG_INTERRUPT = 0x00000040,
76 ATH_DBG_REGULATORY = 0x00000080,
77 ATH_DBG_ANI = 0x00000100,
78 ATH_DBG_POWER_MGMT = 0x00000200,
79 ATH_DBG_XMIT = 0x00000400,
80 ATH_DBG_BEACON = 0x00001000,
81 ATH_DBG_CONFIG = 0x00002000,
82 ATH_DBG_KEYCACHE = 0x00004000,
83 ATH_DBG_FATAL = 0x00008000,
84 ATH_DBG_ANY = 0xffffffff
87 #define DBG_DEFAULT (ATH_DBG_FATAL)
89 #ifdef CONFIG_ATH9K_DEBUG
92 * struct ath_interrupt_stats - Contains statistics about interrupts
93 * @total: Total no. of interrupts generated so far
94 * @rxok: RX with no errors
95 * @rxeol: RX with no more RXDESC available
96 * @rxorn: RX FIFO overrun
97 * @txok: TX completed at the requested rate
98 * @txurn: TX FIFO underrun
99 * @mib: MIB regs reaching its threshold
100 * @rxphyerr: RX with phy errors
101 * @rx_keycache_miss: RX with key cache misses
102 * @swba: Software Beacon Alert
103 * @bmiss: Beacon Miss
104 * @bnr: Beacon Not Ready
105 * @cst: Carrier Sense TImeout
106 * @gtt: Global TX Timeout
107 * @tim: RX beacon TIM occurrence
108 * @cabend: RX End of CAB traffic
109 * @dtimsync: DTIM sync lossage
110 * @dtim: RX Beacon with DTIM
112 struct ath_interrupt_stats {
122 u32 rx_keycache_miss;
135 struct ath_interrupt_stats istats;
140 struct dentry *debugfs_root;
141 struct dentry *debugfs_phy;
142 struct dentry *debugfs_dma;
143 struct dentry *debugfs_interrupt;
144 struct ath_stats stats;
147 void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
148 int ath9k_init_debug(struct ath_softc *sc);
149 void ath9k_exit_debug(struct ath_softc *sc);
150 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
154 static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
155 const char *fmt, ...)
159 static inline int ath9k_init_debug(struct ath_softc *sc)
164 static inline void ath9k_exit_debug(struct ath_softc *sc)
168 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
169 enum ath9k_int status)
173 #endif /* CONFIG_ATH9K_DEBUG */
178 u16 txpowlimit_override;
183 /*************************/
184 /* Descriptor Management */
185 /*************************/
187 #define ATH_TXBUF_RESET(_bf) do { \
188 (_bf)->bf_status = 0; \
189 (_bf)->bf_lastbf = NULL; \
190 (_bf)->bf_lastfrm = NULL; \
191 (_bf)->bf_next = NULL; \
192 memset(&((_bf)->bf_state), 0, \
193 sizeof(struct ath_buf_state)); \
203 BUF_SHORT_PREAMBLE = BIT(6),
206 BUF_AGGR_BURST = BIT(9),
207 BUF_CALC_AIRTIME = BIT(10),
210 struct ath_buf_state {
211 int bfs_nframes; /* # frames in aggregate */
212 u16 bfs_al; /* length of aggregate */
213 u16 bfs_frmlen; /* length of frame */
214 int bfs_seqno; /* sequence number */
215 int bfs_tidno; /* tid of this frame */
216 int bfs_retries; /* current retries */
217 u32 bf_type; /* BUF_* (enum buffer_type) */
219 enum ath9k_key_type bfs_keytype;
222 #define bf_nframes bf_state.bfs_nframes
223 #define bf_al bf_state.bfs_al
224 #define bf_frmlen bf_state.bfs_frmlen
225 #define bf_retries bf_state.bfs_retries
226 #define bf_seqno bf_state.bfs_seqno
227 #define bf_tidno bf_state.bfs_tidno
228 #define bf_rcs bf_state.bfs_rcs
229 #define bf_keyix bf_state.bfs_keyix
230 #define bf_keytype bf_state.bfs_keytype
231 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
232 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
233 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
234 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
235 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
236 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
237 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
238 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
239 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
240 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
243 * Abstraction of a contiguous buffer to transmit/receive. There is only
244 * a single hw descriptor encapsulated here.
247 struct list_head list;
248 struct list_head *last;
249 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
251 struct ath_buf *bf_lastfrm; /* last buf of this frame */
252 struct ath_buf *bf_next; /* next subframe in the aggregate */
253 void *bf_mpdu; /* enclosing frame structure */
254 struct ath_desc *bf_desc; /* virtual addr of desc */
255 dma_addr_t bf_daddr; /* physical addr of desc */
256 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
258 u16 bf_flags; /* tx descriptor flags */
259 struct ath_buf_state bf_state; /* buffer state */
260 dma_addr_t bf_dmacontext;
263 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
265 /* hw processing complete, desc processed by hal */
266 #define ATH_BUFSTATUS_DONE 0x00000001
267 /* hw processing complete, desc hold for hw */
268 #define ATH_BUFSTATUS_STALE 0x00000002
269 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
270 #define ATH_BUFSTATUS_FREE 0x00000004
272 /* DMA state for tx/rx descriptors */
276 struct ath_desc *dd_desc; /* descriptors */
277 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
278 u32 dd_desc_len; /* size of dd_desc */
279 struct ath_buf *dd_bufptr; /* associated buffers */
280 dma_addr_t dd_dmacontext;
283 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
284 struct list_head *head, const char *name,
285 int nbuf, int ndesc);
286 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
287 struct list_head *head);
293 #define ATH_MAX_ANTENNA 3
294 #define ATH_RXBUF 512
295 #define WME_NUM_TID 16
297 int ath_startrecv(struct ath_softc *sc);
298 bool ath_stoprecv(struct ath_softc *sc);
299 void ath_flushrecv(struct ath_softc *sc);
300 u32 ath_calcrxfilter(struct ath_softc *sc);
301 int ath_rx_init(struct ath_softc *sc, int nbufs);
302 void ath_rx_cleanup(struct ath_softc *sc);
303 int ath_rx_tasklet(struct ath_softc *sc, int flush);
305 #define ATH_TXBUF 512
306 #define ATH_TXMAXTRY 13
307 #define ATH_11N_TXMAXTRY 10
308 #define ATH_MGT_TXMAXTRY 4
309 #define WME_BA_BMP_SIZE 64
310 #define WME_MAX_BA WME_BA_BMP_SIZE
311 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
312 #define TID_TO_WME_AC(_tid) \
313 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
314 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
315 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
326 u32 axq_qnum; /* hardware q number */
327 u32 *axq_link; /* link ptr in last TX desc */
328 struct list_head axq_q; /* transmit queue */
330 unsigned long axq_lockflags; /* intr state when must cli */
331 u32 axq_depth; /* queue depth */
332 u8 axq_aggr_depth; /* aggregates queued */
333 u32 axq_totalqueued; /* total ever queued */
335 bool stopped; /* Is mac80211 queue stopped ? */
336 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
338 /* first desc of the last descriptor that contains CTS */
339 struct ath_desc *axq_lastdsWithCTS;
341 /* final desc of the gating desc that determines whether
342 lastdsWithCTS has been DMA'ed or not */
343 struct ath_desc *axq_gatingds;
345 struct list_head axq_acq;
348 #define AGGR_CLEANUP BIT(1)
349 #define AGGR_ADDBA_COMPLETE BIT(2)
350 #define AGGR_ADDBA_PROGRESS BIT(3)
352 /* per TID aggregate tx state for a destination */
354 struct list_head list; /* round-robin tid entry */
355 struct list_head buf_q; /* pending buffers */
357 struct ath_atx_ac *ac;
358 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
363 int baw_head; /* first un-acked tx buffer */
364 int baw_tail; /* next unused tx buffer slot */
368 int addba_exchangeattempts;
371 /* per access-category aggregate tx state for a destination */
373 int sched; /* dest-ac is scheduled */
374 int qnum; /* H/W queue number associated
376 struct list_head list; /* round-robin txq entry */
377 struct list_head tid_q; /* queue of TIDs with buffers */
380 /* per dest tx state */
382 struct ath_atx_tid tid[WME_NUM_TID];
383 struct ath_atx_ac ac[WME_NUM_AC];
386 /* per-frame tx control block */
387 struct ath_tx_control {
392 /* per frame tx status block */
393 struct ath_xmit_status {
394 int retries; /* number of retries to successufully
395 transmit this frame */
396 int flags; /* status of transmit */
397 #define ATH_TX_ERROR 0x01
398 #define ATH_TX_XRETRY 0x02
399 #define ATH_TX_BAR 0x04
402 /* All RSSI values are noise floor adjusted */
405 int rssictl[ATH_MAX_ANTENNA];
406 int rssiextn[ATH_MAX_ANTENNA];
411 /* if any of ctl,extn chain rssis are valid */
412 #define ATH_TX_CHAIN_RSSI_VALID 0x01
413 /* if extn chain rssis are valid */
414 #define ATH_TX_RSSI_EXTN_VALID 0x02
415 u32 airtime; /* time on air per final tx rate */
418 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
419 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
420 int ath_tx_setup(struct ath_softc *sc, int haltype);
421 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
422 void ath_tx_draintxq(struct ath_softc *sc,
423 struct ath_txq *txq, bool retry_tx);
424 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
425 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
426 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
427 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
428 int ath_tx_init(struct ath_softc *sc, int nbufs);
429 int ath_tx_cleanup(struct ath_softc *sc);
430 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
431 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
432 int ath_txq_update(struct ath_softc *sc, int qnum,
433 struct ath9k_tx_queue_info *q);
434 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
435 struct ath_tx_control *txctl);
436 void ath_tx_tasklet(struct ath_softc *sc);
437 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
438 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
439 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
441 /**********************/
442 /* Node / Aggregation */
443 /**********************/
445 #define ADDBA_EXCHANGE_ATTEMPTS 10
446 #define ATH_AGGR_DELIM_SZ 4
447 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
448 /* number of delimiters for encryption padding */
449 #define ATH_AGGR_ENCRYPTDELIM 10
450 /* minimum h/w qdepth to be sustained to maximize aggregation */
451 #define ATH_AGGR_MIN_QDEPTH 2
452 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
453 #define IEEE80211_SEQ_SEQ_SHIFT 4
454 #define IEEE80211_SEQ_MAX 4096
455 #define IEEE80211_MIN_AMPDU_BUF 0x8
456 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
458 /* return whether a bit at index _n in bitmap _bm is set
459 * _sz is the size of the bitmap */
460 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
461 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
463 /* return block-ack bitmap index given sequence and starting sequence */
464 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
466 /* returns delimiter padding required given the packet length */
467 #define ATH_AGGR_GET_NDELIM(_len) \
468 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
469 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
471 #define BAW_WITHIN(_start, _bawsz, _seqno) \
472 ((((_seqno) - (_start)) & 4095) < (_bawsz))
474 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
475 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
476 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
477 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
479 enum ATH_AGGR_STATUS {
487 struct aggr_rifs_param {
488 int param_max_frames;
492 struct ath_rc_series *param_rcs;
495 /* Per-node aggregation state */
496 struct ath_node_aggr {
501 struct ath_softc *an_sc;
502 struct ath_node_aggr an_aggr;
507 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid);
508 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
509 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tidno);
510 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
512 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
513 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
520 * Define the scheme that we select MAC address for multiple
521 * BSS on the same radio. The very first VAP will just use the MAC
522 * address from the EEPROM. For the next 3 VAPs, we set the
523 * U/L bit (bit 1) in MAC address, and use the next two bits as the
527 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
528 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
532 enum nl80211_iftype av_opmode;
533 struct ath_buf *av_bcbuf;
534 struct ath_tx_control av_btxctl;
537 /*******************/
538 /* Beacon Handling */
539 /*******************/
542 * Regardless of the number of beacons we stagger, (i.e. regardless of the
543 * number of BSSIDs) if a given beacon does not go out even after waiting this
544 * number of beacon intervals, the game's up.
546 #define BSTUCK_THRESH (9 * ATH_BCBUF)
548 #define ATH_DEFAULT_BINTVAL 100 /* TU */
549 #define ATH_DEFAULT_BMISS_LIMIT 10
550 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
552 struct ath_beacon_config {
562 } u; /* last received beacon/probe response timestamp of this BSS. */
565 void ath9k_beacon_tasklet(unsigned long data);
566 void ath_beacon_config(struct ath_softc *sc, int if_id);
567 int ath_beaconq_setup(struct ath_hal *ah);
568 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
569 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
570 void ath_beacon_sync(struct ath_softc *sc, int if_id);
576 /* ANI values for STA only.
577 FIXME: Add appropriate values for AP later */
579 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
580 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
581 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
582 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
586 int16_t sc_noise_floor;
587 unsigned int sc_longcal_timer;
588 unsigned int sc_shortcal_timer;
589 unsigned int sc_resetcal_timer;
590 unsigned int sc_checkani_timer;
591 struct timer_list timer;
594 /********************/
596 /********************/
598 #define ATH_LED_PIN 1
608 struct ath_softc *sc;
609 struct led_classdev led_cdev;
610 enum ath_led_type led_type;
616 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
619 struct rfkill *rfkill;
620 struct delayed_work rfkill_poll;
621 char rfkill_name[32];
624 /********************/
625 /* Main driver core */
626 /********************/
629 * Default cache line size, in bytes.
630 * Used when PCI device not fully initialized by bootrom/BIOS
632 #define DEFAULT_CACHELINE 32
633 #define ATH_DEFAULT_NOISE_FLOOR -95
634 #define ATH_REGCLASSIDS_MAX 10
635 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
636 #define ATH_MAX_SW_RETRIES 10
637 #define ATH_CHAN_MAX 255
638 #define IEEE80211_WEP_NKID 4 /* number of key ids */
639 #define IEEE80211_RATE_VAL 0x7f
641 * The key cache is used for h/w cipher state and also for
642 * tracking station state such as the current tx antenna.
643 * We also setup a mapping table between key cache slot indices
644 * and station state to short-circuit node lookups on rx.
645 * Different parts have different size key caches. We handle
646 * up to ATH_KEYMAX entries (could dynamically allocate state).
648 #define ATH_KEYMAX 128 /* max key cache size we handle */
650 #define ATH_IF_ID_ANY 0xff
651 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
652 #define ATH_RSSI_DUMMY_MARKER 0x127
653 #define ATH_RATE_DUMMY_MARKER 0
661 #define SC_OP_INVALID BIT(0)
662 #define SC_OP_BEACONS BIT(1)
663 #define SC_OP_RXAGGR BIT(2)
664 #define SC_OP_TXAGGR BIT(3)
665 #define SC_OP_CHAINMASK_UPDATE BIT(4)
666 #define SC_OP_FULL_RESET BIT(5)
667 #define SC_OP_NO_RESET BIT(6)
668 #define SC_OP_PREAMBLE_SHORT BIT(7)
669 #define SC_OP_PROTECT_ENABLE BIT(8)
670 #define SC_OP_RXFLUSH BIT(9)
671 #define SC_OP_LED_ASSOCIATED BIT(10)
672 #define SC_OP_RFKILL_REGISTERED BIT(11)
673 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
674 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
677 struct ieee80211_hw *hw;
678 struct pci_dev *pdev;
679 struct tasklet_struct intr_tq;
680 struct tasklet_struct bcon_tasklet;
681 struct ath_config sc_config;
682 struct ath_hal *sc_ah;
685 u8 sc_curbssid[ETH_ALEN];
686 u8 sc_myaddr[ETH_ALEN];
687 u8 sc_bssidmask[ETH_ALEN];
689 #ifdef CONFIG_ATH9K_DEBUG
690 struct ath9k_debug sc_debug;
693 u32 sc_flags; /* SC_OP_* */
694 unsigned int rx_filter;
698 int sc_slotupdate; /* slot to next advance fsm */
700 int sc_bslot[ATH_BCBUF];
703 enum ath9k_int sc_imask;
704 enum PROT_MODE sc_protmode;
708 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
714 struct ath9k_node_stats sc_halstats;
715 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
716 enum ath9k_ht_macmode tx_chan_width;
718 #ifdef CONFIG_SLOW_ANT_DIV
719 struct ath_antdiv sc_antdiv;
722 OK, /* no change needed */
723 UPDATE, /* update pending */
724 COMMIT /* beacon sent, commit change */
725 } sc_updateslot; /* slot time update fsm */
729 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
730 u8 sc_splitmic; /* split TKIP MIC keys */
733 struct list_head sc_rxbuf;
734 struct ath_descdma sc_rxdma;
739 struct list_head sc_txbuf;
740 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
741 struct ath_descdma sc_txdma;
743 int sc_haltype2q[ATH9K_WME_AC_VO+1];
744 u16 seq_no; /* TX sequence number */
747 struct ath9k_tx_queue_info sc_beacon_qi;
748 struct ath_descdma sc_bdma;
749 struct ath_txq *sc_cabq;
750 struct list_head sc_bbuf;
757 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
758 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
759 struct ath_rate_table *cur_rate_table;
763 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
764 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
767 spinlock_t sc_rxflushlock;
768 spinlock_t sc_rxbuflock;
769 spinlock_t sc_txbuflock;
770 spinlock_t sc_resetlock;
773 struct ath_led radio_led;
774 struct ath_led assoc_led;
775 struct ath_led tx_led;
776 struct ath_led rx_led;
779 struct ath_rfkill rf_kill;
782 struct ath_ani sc_ani;
785 int ath_reset(struct ath_softc *sc, bool retry_tx);
786 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
787 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
788 int ath_cabq_update(struct ath_softc *);