2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <net/mac80211.h>
23 #include <linux/leds.h>
24 #include <linux/rfkill.h>
31 /* Macro to expand scalars to 64-bit objects */
33 #define ito64(x) (sizeof(x) == 8) ? \
34 (((unsigned long long int)(x)) & (0xff)) : \
36 (((unsigned long long int)(x)) & 0xffff) : \
37 ((sizeof(x) == 32) ? \
38 (((unsigned long long int)(x)) & 0xffffffff) : \
39 (unsigned long long int)(x))
41 /* increment with wrap-around */
42 #define INCR(_l, _sz) do { \
44 (_l) &= ((_sz) - 1); \
47 /* decrement with wrap-around */
48 #define DECR(_l, _sz) do { \
50 (_l) &= ((_sz) - 1); \
53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
55 #define ASSERT(exp) do { \
56 if (unlikely(!(exp))) { \
61 #define TSF_TO_TU(_h,_l) \
62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
66 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
69 ATH_DBG_RESET = 0x00000001,
70 ATH_DBG_REG_IO = 0x00000002,
71 ATH_DBG_QUEUE = 0x00000004,
72 ATH_DBG_EEPROM = 0x00000008,
73 ATH_DBG_CALIBRATE = 0x00000010,
74 ATH_DBG_CHANNEL = 0x00000020,
75 ATH_DBG_INTERRUPT = 0x00000040,
76 ATH_DBG_REGULATORY = 0x00000080,
77 ATH_DBG_ANI = 0x00000100,
78 ATH_DBG_POWER_MGMT = 0x00000200,
79 ATH_DBG_XMIT = 0x00000400,
80 ATH_DBG_BEACON = 0x00001000,
81 ATH_DBG_CONFIG = 0x00002000,
82 ATH_DBG_KEYCACHE = 0x00004000,
83 ATH_DBG_FATAL = 0x00008000,
84 ATH_DBG_ANY = 0xffffffff
87 #define DBG_DEFAULT (ATH_DBG_FATAL)
89 #ifdef CONFIG_ATH9K_DEBUG
92 * struct ath_interrupt_stats - Contains statistics about interrupts
93 * @total: Total no. of interrupts generated so far
94 * @rxok: RX with no errors
95 * @rxeol: RX with no more RXDESC available
96 * @rxorn: RX FIFO overrun
97 * @txok: TX completed at the requested rate
98 * @txurn: TX FIFO underrun
99 * @mib: MIB regs reaching its threshold
100 * @rxphyerr: RX with phy errors
101 * @rx_keycache_miss: RX with key cache misses
102 * @swba: Software Beacon Alert
103 * @bmiss: Beacon Miss
104 * @bnr: Beacon Not Ready
105 * @cst: Carrier Sense TImeout
106 * @gtt: Global TX Timeout
107 * @tim: RX beacon TIM occurrence
108 * @cabend: RX End of CAB traffic
109 * @dtimsync: DTIM sync lossage
110 * @dtim: RX Beacon with DTIM
112 struct ath_interrupt_stats {
122 u32 rx_keycache_miss;
135 struct ath_interrupt_stats istats;
140 struct dentry *debugfs_root;
141 struct dentry *debugfs_phy;
142 struct dentry *debugfs_dma;
143 struct dentry *debugfs_interrupt;
144 struct ath_stats stats;
147 void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
148 int ath9k_init_debug(struct ath_softc *sc);
149 void ath9k_exit_debug(struct ath_softc *sc);
150 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
154 static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
155 const char *fmt, ...)
159 static inline int ath9k_init_debug(struct ath_softc *sc)
164 static inline void ath9k_exit_debug(struct ath_softc *sc)
168 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
169 enum ath9k_int status)
173 #endif /* CONFIG_ATH9K_DEBUG */
178 u16 txpowlimit_override;
183 /*************************/
184 /* Descriptor Management */
185 /*************************/
187 #define ATH_TXBUF_RESET(_bf) do { \
188 (_bf)->bf_status = 0; \
189 (_bf)->bf_lastbf = NULL; \
190 (_bf)->bf_next = NULL; \
191 memset(&((_bf)->bf_state), 0, \
192 sizeof(struct ath_buf_state)); \
202 BUF_SHORT_PREAMBLE = BIT(6),
205 BUF_AGGR_BURST = BIT(9),
206 BUF_CALC_AIRTIME = BIT(10),
209 struct ath_buf_state {
210 int bfs_nframes; /* # frames in aggregate */
211 u16 bfs_al; /* length of aggregate */
212 u16 bfs_frmlen; /* length of frame */
213 int bfs_seqno; /* sequence number */
214 int bfs_tidno; /* tid of this frame */
215 int bfs_retries; /* current retries */
216 u32 bf_type; /* BUF_* (enum buffer_type) */
218 enum ath9k_key_type bfs_keytype;
221 #define bf_nframes bf_state.bfs_nframes
222 #define bf_al bf_state.bfs_al
223 #define bf_frmlen bf_state.bfs_frmlen
224 #define bf_retries bf_state.bfs_retries
225 #define bf_seqno bf_state.bfs_seqno
226 #define bf_tidno bf_state.bfs_tidno
227 #define bf_rcs bf_state.bfs_rcs
228 #define bf_keyix bf_state.bfs_keyix
229 #define bf_keytype bf_state.bfs_keytype
230 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
231 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
232 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
233 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
234 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
235 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
236 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
237 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
238 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
241 * Abstraction of a contiguous buffer to transmit/receive. There is only
242 * a single hw descriptor encapsulated here.
245 struct list_head list;
246 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
248 struct ath_buf *bf_next; /* next subframe in the aggregate */
249 void *bf_mpdu; /* enclosing frame structure */
250 struct ath_desc *bf_desc; /* virtual addr of desc */
251 dma_addr_t bf_daddr; /* physical addr of desc */
252 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
254 u16 bf_flags; /* tx descriptor flags */
255 struct ath_buf_state bf_state; /* buffer state */
256 dma_addr_t bf_dmacontext;
259 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
260 #define ATH_BUFSTATUS_STALE 0x00000002
262 /* DMA state for tx/rx descriptors */
266 struct ath_desc *dd_desc; /* descriptors */
267 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
268 u32 dd_desc_len; /* size of dd_desc */
269 struct ath_buf *dd_bufptr; /* associated buffers */
270 dma_addr_t dd_dmacontext;
273 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
274 struct list_head *head, const char *name,
275 int nbuf, int ndesc);
276 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
277 struct list_head *head);
283 #define ATH_MAX_ANTENNA 3
284 #define ATH_RXBUF 512
285 #define WME_NUM_TID 16
286 #define ATH_TXBUF 512
287 #define ATH_TXMAXTRY 13
288 #define ATH_11N_TXMAXTRY 10
289 #define ATH_MGT_TXMAXTRY 4
290 #define WME_BA_BMP_SIZE 64
291 #define WME_MAX_BA WME_BA_BMP_SIZE
292 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
294 #define TID_TO_WME_AC(_tid) \
295 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
296 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
297 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
306 #define ADDBA_EXCHANGE_ATTEMPTS 10
307 #define ATH_AGGR_DELIM_SZ 4
308 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
309 /* number of delimiters for encryption padding */
310 #define ATH_AGGR_ENCRYPTDELIM 10
311 /* minimum h/w qdepth to be sustained to maximize aggregation */
312 #define ATH_AGGR_MIN_QDEPTH 2
313 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
314 #define IEEE80211_SEQ_SEQ_SHIFT 4
315 #define IEEE80211_SEQ_MAX 4096
316 #define IEEE80211_MIN_AMPDU_BUF 0x8
317 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
319 /* return whether a bit at index _n in bitmap _bm is set
320 * _sz is the size of the bitmap */
321 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
322 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
324 /* return block-ack bitmap index given sequence and starting sequence */
325 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
327 /* returns delimiter padding required given the packet length */
328 #define ATH_AGGR_GET_NDELIM(_len) \
329 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
330 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
332 #define BAW_WITHIN(_start, _bawsz, _seqno) \
333 ((((_seqno) - (_start)) & 4095) < (_bawsz))
335 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
336 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
337 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
338 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
340 enum ATH_AGGR_STATUS {
349 u32 axq_qnum; /* hardware q number */
350 u32 *axq_link; /* link ptr in last TX desc */
351 struct list_head axq_q; /* transmit queue */
353 u32 axq_depth; /* queue depth */
354 u8 axq_aggr_depth; /* aggregates queued */
355 u32 axq_totalqueued; /* total ever queued */
356 bool stopped; /* Is mac80211 queue stopped ? */
357 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
359 /* first desc of the last descriptor that contains CTS */
360 struct ath_desc *axq_lastdsWithCTS;
362 /* final desc of the gating desc that determines whether
363 lastdsWithCTS has been DMA'ed or not */
364 struct ath_desc *axq_gatingds;
366 struct list_head axq_acq;
369 #define AGGR_CLEANUP BIT(1)
370 #define AGGR_ADDBA_COMPLETE BIT(2)
371 #define AGGR_ADDBA_PROGRESS BIT(3)
373 /* per TID aggregate tx state for a destination */
375 struct list_head list; /* round-robin tid entry */
376 struct list_head buf_q; /* pending buffers */
378 struct ath_atx_ac *ac;
379 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
384 int baw_head; /* first un-acked tx buffer */
385 int baw_tail; /* next unused tx buffer slot */
389 int addba_exchangeattempts;
392 /* per access-category aggregate tx state for a destination */
394 int sched; /* dest-ac is scheduled */
395 int qnum; /* H/W queue number associated
397 struct list_head list; /* round-robin txq entry */
398 struct list_head tid_q; /* queue of TIDs with buffers */
401 /* per-frame tx control block */
402 struct ath_tx_control {
407 /* per frame tx status block */
408 struct ath_xmit_status {
409 int retries; /* number of retries to successufully
410 transmit this frame */
411 int flags; /* status of transmit */
412 #define ATH_TX_ERROR 0x01
413 #define ATH_TX_XRETRY 0x02
414 #define ATH_TX_BAR 0x04
417 /* All RSSI values are noise floor adjusted */
420 int rssictl[ATH_MAX_ANTENNA];
421 int rssiextn[ATH_MAX_ANTENNA];
426 u32 airtime; /* time on air per final tx rate */
429 struct aggr_rifs_param {
430 int param_max_frames;
434 struct ath_rc_series *param_rcs;
438 struct ath_softc *an_sc;
439 struct ath_atx_tid tid[WME_NUM_TID];
440 struct ath_atx_ac ac[WME_NUM_AC];
448 int hwq_map[ATH9K_WME_AC_VO+1];
449 spinlock_t txbuflock;
450 struct list_head txbuf;
451 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
452 struct ath_descdma txdma;
460 unsigned int rxfilter;
461 spinlock_t rxflushlock;
462 spinlock_t rxbuflock;
463 struct list_head rxbuf;
464 struct ath_descdma rxdma;
467 int ath_startrecv(struct ath_softc *sc);
468 bool ath_stoprecv(struct ath_softc *sc);
469 void ath_flushrecv(struct ath_softc *sc);
470 u32 ath_calcrxfilter(struct ath_softc *sc);
471 int ath_rx_init(struct ath_softc *sc, int nbufs);
472 void ath_rx_cleanup(struct ath_softc *sc);
473 int ath_rx_tasklet(struct ath_softc *sc, int flush);
474 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
475 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
476 int ath_tx_setup(struct ath_softc *sc, int haltype);
477 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
478 void ath_draintxq(struct ath_softc *sc,
479 struct ath_txq *txq, bool retry_tx);
480 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
481 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
482 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
483 int ath_tx_init(struct ath_softc *sc, int nbufs);
484 int ath_tx_cleanup(struct ath_softc *sc);
485 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
486 int ath_txq_update(struct ath_softc *sc, int qnum,
487 struct ath9k_tx_queue_info *q);
488 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
489 struct ath_tx_control *txctl);
490 void ath_tx_tasklet(struct ath_softc *sc);
491 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
492 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
493 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
495 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
496 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
503 * Define the scheme that we select MAC address for multiple
504 * BSS on the same radio. The very first VAP will just use the MAC
505 * address from the EEPROM. For the next 3 VAPs, we set the
506 * U/L bit (bit 1) in MAC address, and use the next two bits as the
510 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
511 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
515 enum nl80211_iftype av_opmode;
516 struct ath_buf *av_bcbuf;
517 struct ath_tx_control av_btxctl;
520 /*******************/
521 /* Beacon Handling */
522 /*******************/
525 * Regardless of the number of beacons we stagger, (i.e. regardless of the
526 * number of BSSIDs) if a given beacon does not go out even after waiting this
527 * number of beacon intervals, the game's up.
529 #define BSTUCK_THRESH (9 * ATH_BCBUF)
531 #define ATH_DEFAULT_BINTVAL 100 /* TU */
532 #define ATH_DEFAULT_BMISS_LIMIT 10
533 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
535 struct ath_beacon_config {
545 } u; /* last received beacon/probe response timestamp of this BSS. */
550 OK, /* no change needed */
551 UPDATE, /* update pending */
552 COMMIT /* beacon sent, commit change */
553 } updateslot; /* slot time update fsm */
559 int bslot[ATH_BCBUF];
562 struct ath9k_tx_queue_info beacon_qi;
563 struct ath_descdma bdma;
564 struct ath_txq *cabq;
565 struct list_head bbuf;
568 void ath9k_beacon_tasklet(unsigned long data);
569 void ath_beacon_config(struct ath_softc *sc, int if_id);
570 int ath_beaconq_setup(struct ath_hal *ah);
571 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
572 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
573 void ath_beacon_sync(struct ath_softc *sc, int if_id);
579 /* ANI values for STA only.
580 FIXME: Add appropriate values for AP later */
582 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
583 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
584 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
585 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
589 int16_t sc_noise_floor;
590 unsigned int sc_longcal_timer;
591 unsigned int sc_shortcal_timer;
592 unsigned int sc_resetcal_timer;
593 unsigned int sc_checkani_timer;
594 struct timer_list timer;
597 /********************/
599 /********************/
601 #define ATH_LED_PIN 1
602 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
603 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
613 struct ath_softc *sc;
614 struct led_classdev led_cdev;
615 enum ath_led_type led_type;
621 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
624 struct rfkill *rfkill;
625 struct delayed_work rfkill_poll;
626 char rfkill_name[32];
629 /********************/
630 /* Main driver core */
631 /********************/
634 * Default cache line size, in bytes.
635 * Used when PCI device not fully initialized by bootrom/BIOS
637 #define DEFAULT_CACHELINE 32
638 #define ATH_DEFAULT_NOISE_FLOOR -95
639 #define ATH_REGCLASSIDS_MAX 10
640 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
641 #define ATH_MAX_SW_RETRIES 10
642 #define ATH_CHAN_MAX 255
643 #define IEEE80211_WEP_NKID 4 /* number of key ids */
644 #define IEEE80211_RATE_VAL 0x7f
646 * The key cache is used for h/w cipher state and also for
647 * tracking station state such as the current tx antenna.
648 * We also setup a mapping table between key cache slot indices
649 * and station state to short-circuit node lookups on rx.
650 * Different parts have different size key caches. We handle
651 * up to ATH_KEYMAX entries (could dynamically allocate state).
653 #define ATH_KEYMAX 128 /* max key cache size we handle */
655 #define ATH_IF_ID_ANY 0xff
656 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
657 #define ATH_RSSI_DUMMY_MARKER 0x127
658 #define ATH_RATE_DUMMY_MARKER 0
660 #define SC_OP_INVALID BIT(0)
661 #define SC_OP_BEACONS BIT(1)
662 #define SC_OP_RXAGGR BIT(2)
663 #define SC_OP_TXAGGR BIT(3)
664 #define SC_OP_CHAINMASK_UPDATE BIT(4)
665 #define SC_OP_FULL_RESET BIT(5)
666 #define SC_OP_NO_RESET BIT(6)
667 #define SC_OP_PREAMBLE_SHORT BIT(7)
668 #define SC_OP_PROTECT_ENABLE BIT(8)
669 #define SC_OP_RXFLUSH BIT(9)
670 #define SC_OP_LED_ASSOCIATED BIT(10)
671 #define SC_OP_RFKILL_REGISTERED BIT(11)
672 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
673 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
674 #define SC_OP_WAIT_FOR_BEACON BIT(14)
675 #define SC_OP_LED_ON BIT(15)
678 void (*read_cachesize)(struct ath_softc *sc, int *csz);
679 void (*cleanup)(struct ath_softc *sc);
680 bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data);
684 struct ieee80211_hw *hw;
686 struct tasklet_struct intr_tq;
687 struct tasklet_struct bcon_tasklet;
688 struct ath_hal *sc_ah;
691 spinlock_t sc_resetlock;
694 u8 sc_curbssid[ETH_ALEN];
695 u8 sc_myaddr[ETH_ALEN];
696 u8 sc_bssidmask[ETH_ALEN];
698 u32 sc_flags; /* SC_OP_* */
707 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
709 atomic_t ps_usecount;
710 enum ath9k_int sc_imask;
711 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
712 enum ath9k_ht_macmode tx_chan_width;
714 struct ath_config sc_config;
717 struct ath_beacon beacon;
718 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
719 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
720 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
721 struct ath_rate_table *cur_rate_table;
722 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
724 struct ath_led radio_led;
725 struct ath_led assoc_led;
726 struct ath_led tx_led;
727 struct ath_led rx_led;
728 struct delayed_work ath_led_blink_work;
730 int led_off_duration;
734 struct ath_rfkill rf_kill;
735 struct ath_ani sc_ani;
736 struct ath9k_node_stats sc_halstats;
737 #ifdef CONFIG_ATH9K_DEBUG
738 struct ath9k_debug sc_debug;
740 struct ath_bus_ops *bus_ops;
743 int ath_reset(struct ath_softc *sc, bool retry_tx);
744 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
745 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
746 int ath_cabq_update(struct ath_softc *);
748 static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
750 sc->bus_ops->read_cachesize(sc, csz);
753 static inline void ath_bus_cleanup(struct ath_softc *sc)
755 sc->bus_ops->cleanup(sc);
758 extern struct ieee80211_ops ath9k_ops;
760 irqreturn_t ath_isr(int irq, void *dev);
761 void ath_cleanup(struct ath_softc *sc);
762 int ath_attach(u16 devid, struct ath_softc *sc);
763 void ath_detach(struct ath_softc *sc);
764 const char *ath_mac_bb_name(u32 mac_bb_version);
765 const char *ath_rf_name(u16 rf_version);
768 int ath_pci_init(void);
769 void ath_pci_exit(void);
771 static inline int ath_pci_init(void) { return 0; };
772 static inline void ath_pci_exit(void) {};
775 #ifdef CONFIG_ATHEROS_AR71XX
776 int ath_ahb_init(void);
777 void ath_ahb_exit(void);
779 static inline int ath_ahb_init(void) { return 0; };
780 static inline void ath_ahb_exit(void) {};
783 static inline void ath9k_ps_wakeup(struct ath_softc *sc)
785 if (atomic_inc_return(&sc->ps_usecount) == 1)
786 if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) {
787 sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode;
788 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
792 static inline void ath9k_ps_restore(struct ath_softc *sc)
794 if (atomic_dec_and_test(&sc->ps_usecount))
795 if (sc->hw->conf.flags & IEEE80211_CONF_PS)
796 ath9k_hw_setpower(sc->sc_ah,
797 sc->sc_ah->ah_restore_mode);