2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <net/mac80211.h>
23 #include <linux/leds.h>
24 #include <linux/rfkill.h>
31 /* Macro to expand scalars to 64-bit objects */
33 #define ito64(x) (sizeof(x) == 8) ? \
34 (((unsigned long long int)(x)) & (0xff)) : \
36 (((unsigned long long int)(x)) & 0xffff) : \
37 ((sizeof(x) == 32) ? \
38 (((unsigned long long int)(x)) & 0xffffffff) : \
39 (unsigned long long int)(x))
41 /* increment with wrap-around */
42 #define INCR(_l, _sz) do { \
44 (_l) &= ((_sz) - 1); \
47 /* decrement with wrap-around */
48 #define DECR(_l, _sz) do { \
50 (_l) &= ((_sz) - 1); \
53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
55 #define ASSERT(exp) do { \
56 if (unlikely(!(exp))) { \
61 #define TSF_TO_TU(_h,_l) \
62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
66 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
69 ATH_DBG_RESET = 0x00000001,
70 ATH_DBG_REG_IO = 0x00000002,
71 ATH_DBG_QUEUE = 0x00000004,
72 ATH_DBG_EEPROM = 0x00000008,
73 ATH_DBG_CALIBRATE = 0x00000010,
74 ATH_DBG_CHANNEL = 0x00000020,
75 ATH_DBG_INTERRUPT = 0x00000040,
76 ATH_DBG_REGULATORY = 0x00000080,
77 ATH_DBG_ANI = 0x00000100,
78 ATH_DBG_POWER_MGMT = 0x00000200,
79 ATH_DBG_XMIT = 0x00000400,
80 ATH_DBG_BEACON = 0x00001000,
81 ATH_DBG_CONFIG = 0x00002000,
82 ATH_DBG_KEYCACHE = 0x00004000,
83 ATH_DBG_FATAL = 0x00008000,
84 ATH_DBG_ANY = 0xffffffff
87 #define DBG_DEFAULT (ATH_DBG_FATAL)
89 #ifdef CONFIG_ATH9K_DEBUG
92 * struct ath_interrupt_stats - Contains statistics about interrupts
93 * @total: Total no. of interrupts generated so far
94 * @rxok: RX with no errors
95 * @rxeol: RX with no more RXDESC available
96 * @rxorn: RX FIFO overrun
97 * @txok: TX completed at the requested rate
98 * @txurn: TX FIFO underrun
99 * @mib: MIB regs reaching its threshold
100 * @rxphyerr: RX with phy errors
101 * @rx_keycache_miss: RX with key cache misses
102 * @swba: Software Beacon Alert
103 * @bmiss: Beacon Miss
104 * @bnr: Beacon Not Ready
105 * @cst: Carrier Sense TImeout
106 * @gtt: Global TX Timeout
107 * @tim: RX beacon TIM occurrence
108 * @cabend: RX End of CAB traffic
109 * @dtimsync: DTIM sync lossage
110 * @dtim: RX Beacon with DTIM
112 struct ath_interrupt_stats {
122 u32 rx_keycache_miss;
135 struct ath_interrupt_stats istats;
140 struct dentry *debugfs_root;
141 struct dentry *debugfs_phy;
142 struct dentry *debugfs_dma;
143 struct dentry *debugfs_interrupt;
144 struct ath_stats stats;
147 void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
148 int ath9k_init_debug(struct ath_softc *sc);
149 void ath9k_exit_debug(struct ath_softc *sc);
150 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
154 static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
155 const char *fmt, ...)
159 static inline int ath9k_init_debug(struct ath_softc *sc)
164 static inline void ath9k_exit_debug(struct ath_softc *sc)
168 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
169 enum ath9k_int status)
173 #endif /* CONFIG_ATH9K_DEBUG */
178 u16 txpowlimit_override;
183 /*************************/
184 /* Descriptor Management */
185 /*************************/
187 #define ATH_TXBUF_RESET(_bf) do { \
188 (_bf)->bf_status = 0; \
189 (_bf)->bf_lastbf = NULL; \
190 (_bf)->bf_next = NULL; \
191 memset(&((_bf)->bf_state), 0, \
192 sizeof(struct ath_buf_state)); \
202 BUF_SHORT_PREAMBLE = BIT(6),
205 BUF_AGGR_BURST = BIT(9),
206 BUF_CALC_AIRTIME = BIT(10),
209 struct ath_buf_state {
210 int bfs_nframes; /* # frames in aggregate */
211 u16 bfs_al; /* length of aggregate */
212 u16 bfs_frmlen; /* length of frame */
213 int bfs_seqno; /* sequence number */
214 int bfs_tidno; /* tid of this frame */
215 int bfs_retries; /* current retries */
216 u32 bf_type; /* BUF_* (enum buffer_type) */
218 enum ath9k_key_type bfs_keytype;
221 #define bf_nframes bf_state.bfs_nframes
222 #define bf_al bf_state.bfs_al
223 #define bf_frmlen bf_state.bfs_frmlen
224 #define bf_retries bf_state.bfs_retries
225 #define bf_seqno bf_state.bfs_seqno
226 #define bf_tidno bf_state.bfs_tidno
227 #define bf_rcs bf_state.bfs_rcs
228 #define bf_keyix bf_state.bfs_keyix
229 #define bf_keytype bf_state.bfs_keytype
230 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
231 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
232 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
233 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
234 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
235 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
236 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
237 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
238 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
239 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
242 * Abstraction of a contiguous buffer to transmit/receive. There is only
243 * a single hw descriptor encapsulated here.
246 struct list_head list;
247 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
249 struct ath_buf *bf_next; /* next subframe in the aggregate */
250 void *bf_mpdu; /* enclosing frame structure */
251 struct ath_desc *bf_desc; /* virtual addr of desc */
252 dma_addr_t bf_daddr; /* physical addr of desc */
253 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
255 u16 bf_flags; /* tx descriptor flags */
256 struct ath_buf_state bf_state; /* buffer state */
257 dma_addr_t bf_dmacontext;
260 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
261 #define ATH_BUFSTATUS_STALE 0x00000002
263 /* DMA state for tx/rx descriptors */
267 struct ath_desc *dd_desc; /* descriptors */
268 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
269 u32 dd_desc_len; /* size of dd_desc */
270 struct ath_buf *dd_bufptr; /* associated buffers */
271 dma_addr_t dd_dmacontext;
274 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
275 struct list_head *head, const char *name,
276 int nbuf, int ndesc);
277 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
278 struct list_head *head);
284 #define ATH_MAX_ANTENNA 3
285 #define ATH_RXBUF 512
286 #define WME_NUM_TID 16
287 #define ATH_TXBUF 512
288 #define ATH_TXMAXTRY 13
289 #define ATH_11N_TXMAXTRY 10
290 #define ATH_MGT_TXMAXTRY 4
291 #define WME_BA_BMP_SIZE 64
292 #define WME_MAX_BA WME_BA_BMP_SIZE
293 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
295 #define TID_TO_WME_AC(_tid) \
296 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
297 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
298 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
307 #define ADDBA_EXCHANGE_ATTEMPTS 10
308 #define ATH_AGGR_DELIM_SZ 4
309 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
310 /* number of delimiters for encryption padding */
311 #define ATH_AGGR_ENCRYPTDELIM 10
312 /* minimum h/w qdepth to be sustained to maximize aggregation */
313 #define ATH_AGGR_MIN_QDEPTH 2
314 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
315 #define IEEE80211_SEQ_SEQ_SHIFT 4
316 #define IEEE80211_SEQ_MAX 4096
317 #define IEEE80211_MIN_AMPDU_BUF 0x8
318 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
320 /* return whether a bit at index _n in bitmap _bm is set
321 * _sz is the size of the bitmap */
322 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
323 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
325 /* return block-ack bitmap index given sequence and starting sequence */
326 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
328 /* returns delimiter padding required given the packet length */
329 #define ATH_AGGR_GET_NDELIM(_len) \
330 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
331 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
333 #define BAW_WITHIN(_start, _bawsz, _seqno) \
334 ((((_seqno) - (_start)) & 4095) < (_bawsz))
336 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
337 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
338 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
339 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
341 enum ATH_AGGR_STATUS {
350 u32 axq_qnum; /* hardware q number */
351 u32 *axq_link; /* link ptr in last TX desc */
352 struct list_head axq_q; /* transmit queue */
354 u32 axq_depth; /* queue depth */
355 u8 axq_aggr_depth; /* aggregates queued */
356 u32 axq_totalqueued; /* total ever queued */
357 bool stopped; /* Is mac80211 queue stopped ? */
358 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
360 /* first desc of the last descriptor that contains CTS */
361 struct ath_desc *axq_lastdsWithCTS;
363 /* final desc of the gating desc that determines whether
364 lastdsWithCTS has been DMA'ed or not */
365 struct ath_desc *axq_gatingds;
367 struct list_head axq_acq;
370 #define AGGR_CLEANUP BIT(1)
371 #define AGGR_ADDBA_COMPLETE BIT(2)
372 #define AGGR_ADDBA_PROGRESS BIT(3)
374 /* per TID aggregate tx state for a destination */
376 struct list_head list; /* round-robin tid entry */
377 struct list_head buf_q; /* pending buffers */
379 struct ath_atx_ac *ac;
380 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
385 int baw_head; /* first un-acked tx buffer */
386 int baw_tail; /* next unused tx buffer slot */
390 int addba_exchangeattempts;
393 /* per access-category aggregate tx state for a destination */
395 int sched; /* dest-ac is scheduled */
396 int qnum; /* H/W queue number associated
398 struct list_head list; /* round-robin txq entry */
399 struct list_head tid_q; /* queue of TIDs with buffers */
402 /* per-frame tx control block */
403 struct ath_tx_control {
408 /* per frame tx status block */
409 struct ath_xmit_status {
410 int retries; /* number of retries to successufully
411 transmit this frame */
412 int flags; /* status of transmit */
413 #define ATH_TX_ERROR 0x01
414 #define ATH_TX_XRETRY 0x02
415 #define ATH_TX_BAR 0x04
418 /* All RSSI values are noise floor adjusted */
421 int rssictl[ATH_MAX_ANTENNA];
422 int rssiextn[ATH_MAX_ANTENNA];
427 u32 airtime; /* time on air per final tx rate */
430 struct aggr_rifs_param {
431 int param_max_frames;
435 struct ath_rc_series *param_rcs;
439 struct ath_softc *an_sc;
440 struct ath_atx_tid tid[WME_NUM_TID];
441 struct ath_atx_ac ac[WME_NUM_AC];
449 int hwq_map[ATH9K_WME_AC_VO+1];
450 spinlock_t txbuflock;
451 struct list_head txbuf;
452 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
453 struct ath_descdma txdma;
461 unsigned int rxfilter;
462 spinlock_t rxflushlock;
463 spinlock_t rxbuflock;
464 struct list_head rxbuf;
465 struct ath_descdma rxdma;
468 int ath_startrecv(struct ath_softc *sc);
469 bool ath_stoprecv(struct ath_softc *sc);
470 void ath_flushrecv(struct ath_softc *sc);
471 u32 ath_calcrxfilter(struct ath_softc *sc);
472 int ath_rx_init(struct ath_softc *sc, int nbufs);
473 void ath_rx_cleanup(struct ath_softc *sc);
474 int ath_rx_tasklet(struct ath_softc *sc, int flush);
475 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
476 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
477 int ath_tx_setup(struct ath_softc *sc, int haltype);
478 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
479 void ath_draintxq(struct ath_softc *sc,
480 struct ath_txq *txq, bool retry_tx);
481 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
482 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
483 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
484 int ath_tx_init(struct ath_softc *sc, int nbufs);
485 int ath_tx_cleanup(struct ath_softc *sc);
486 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
487 int ath_txq_update(struct ath_softc *sc, int qnum,
488 struct ath9k_tx_queue_info *q);
489 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
490 struct ath_tx_control *txctl);
491 void ath_tx_tasklet(struct ath_softc *sc);
492 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
493 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
494 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
496 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
497 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
504 * Define the scheme that we select MAC address for multiple
505 * BSS on the same radio. The very first VAP will just use the MAC
506 * address from the EEPROM. For the next 3 VAPs, we set the
507 * U/L bit (bit 1) in MAC address, and use the next two bits as the
511 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
512 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
516 enum nl80211_iftype av_opmode;
517 struct ath_buf *av_bcbuf;
518 struct ath_tx_control av_btxctl;
521 /*******************/
522 /* Beacon Handling */
523 /*******************/
526 * Regardless of the number of beacons we stagger, (i.e. regardless of the
527 * number of BSSIDs) if a given beacon does not go out even after waiting this
528 * number of beacon intervals, the game's up.
530 #define BSTUCK_THRESH (9 * ATH_BCBUF)
532 #define ATH_DEFAULT_BINTVAL 100 /* TU */
533 #define ATH_DEFAULT_BMISS_LIMIT 10
534 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
536 struct ath_beacon_config {
546 } u; /* last received beacon/probe response timestamp of this BSS. */
551 OK, /* no change needed */
552 UPDATE, /* update pending */
553 COMMIT /* beacon sent, commit change */
554 } updateslot; /* slot time update fsm */
560 int bslot[ATH_BCBUF];
563 struct ath9k_tx_queue_info beacon_qi;
564 struct ath_descdma bdma;
565 struct ath_txq *cabq;
566 struct list_head bbuf;
569 void ath9k_beacon_tasklet(unsigned long data);
570 void ath_beacon_config(struct ath_softc *sc, int if_id);
571 int ath_beaconq_setup(struct ath_hal *ah);
572 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
573 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
574 void ath_beacon_sync(struct ath_softc *sc, int if_id);
580 /* ANI values for STA only.
581 FIXME: Add appropriate values for AP later */
583 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
584 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
585 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
586 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
590 int16_t sc_noise_floor;
591 unsigned int sc_longcal_timer;
592 unsigned int sc_shortcal_timer;
593 unsigned int sc_resetcal_timer;
594 unsigned int sc_checkani_timer;
595 struct timer_list timer;
598 /********************/
600 /********************/
602 #define ATH_LED_PIN 1
612 struct ath_softc *sc;
613 struct led_classdev led_cdev;
614 enum ath_led_type led_type;
620 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
623 struct rfkill *rfkill;
624 struct delayed_work rfkill_poll;
625 char rfkill_name[32];
628 /********************/
629 /* Main driver core */
630 /********************/
633 * Default cache line size, in bytes.
634 * Used when PCI device not fully initialized by bootrom/BIOS
636 #define DEFAULT_CACHELINE 32
637 #define ATH_DEFAULT_NOISE_FLOOR -95
638 #define ATH_REGCLASSIDS_MAX 10
639 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
640 #define ATH_MAX_SW_RETRIES 10
641 #define ATH_CHAN_MAX 255
642 #define IEEE80211_WEP_NKID 4 /* number of key ids */
643 #define IEEE80211_RATE_VAL 0x7f
645 * The key cache is used for h/w cipher state and also for
646 * tracking station state such as the current tx antenna.
647 * We also setup a mapping table between key cache slot indices
648 * and station state to short-circuit node lookups on rx.
649 * Different parts have different size key caches. We handle
650 * up to ATH_KEYMAX entries (could dynamically allocate state).
652 #define ATH_KEYMAX 128 /* max key cache size we handle */
654 #define ATH_IF_ID_ANY 0xff
655 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
656 #define ATH_RSSI_DUMMY_MARKER 0x127
657 #define ATH_RATE_DUMMY_MARKER 0
665 #define SC_OP_INVALID BIT(0)
666 #define SC_OP_BEACONS BIT(1)
667 #define SC_OP_RXAGGR BIT(2)
668 #define SC_OP_TXAGGR BIT(3)
669 #define SC_OP_CHAINMASK_UPDATE BIT(4)
670 #define SC_OP_FULL_RESET BIT(5)
671 #define SC_OP_NO_RESET BIT(6)
672 #define SC_OP_PREAMBLE_SHORT BIT(7)
673 #define SC_OP_PROTECT_ENABLE BIT(8)
674 #define SC_OP_RXFLUSH BIT(9)
675 #define SC_OP_LED_ASSOCIATED BIT(10)
676 #define SC_OP_RFKILL_REGISTERED BIT(11)
677 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
678 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
679 #define SC_OP_WAIT_FOR_BEACON BIT(14)
682 void (*read_cachesize)(struct ath_softc *sc, int *csz);
683 void (*cleanup)(struct ath_softc *sc);
684 bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data);
688 struct ieee80211_hw *hw;
690 struct tasklet_struct intr_tq;
691 struct tasklet_struct bcon_tasklet;
692 struct ath_hal *sc_ah;
695 spinlock_t sc_resetlock;
698 u8 sc_curbssid[ETH_ALEN];
699 u8 sc_myaddr[ETH_ALEN];
700 u8 sc_bssidmask[ETH_ALEN];
702 u32 sc_flags; /* SC_OP_* */
711 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
713 atomic_t ps_usecount;
714 enum ath9k_int sc_imask;
715 enum PROT_MODE sc_protmode;
716 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
717 enum ath9k_ht_macmode tx_chan_width;
719 struct ath_config sc_config;
722 struct ath_beacon beacon;
723 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
724 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
725 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
726 struct ath_rate_table *cur_rate_table;
727 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
728 struct ath_led radio_led;
729 struct ath_led assoc_led;
730 struct ath_led tx_led;
731 struct ath_led rx_led;
732 struct ath_rfkill rf_kill;
733 struct ath_ani sc_ani;
734 struct ath9k_node_stats sc_halstats;
735 #ifdef CONFIG_ATH9K_DEBUG
736 struct ath9k_debug sc_debug;
738 struct ath_bus_ops *bus_ops;
741 int ath_reset(struct ath_softc *sc, bool retry_tx);
742 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
743 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
744 int ath_cabq_update(struct ath_softc *);
746 static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
748 sc->bus_ops->read_cachesize(sc, csz);
751 static inline void ath_bus_cleanup(struct ath_softc *sc)
753 sc->bus_ops->cleanup(sc);
756 extern struct ieee80211_ops ath9k_ops;
758 irqreturn_t ath_isr(int irq, void *dev);
759 void ath_cleanup(struct ath_softc *sc);
760 int ath_attach(u16 devid, struct ath_softc *sc);
761 void ath_detach(struct ath_softc *sc);
762 const char *ath_mac_bb_name(u32 mac_bb_version);
763 const char *ath_rf_name(u16 rf_version);
766 int ath_pci_init(void);
767 void ath_pci_exit(void);
769 static inline int ath_pci_init(void) { return 0; };
770 static inline void ath_pci_exit(void) {};
773 #ifdef CONFIG_ATHEROS_AR71XX
774 int ath_ahb_init(void);
775 void ath_ahb_exit(void);
777 static inline int ath_ahb_init(void) { return 0; };
778 static inline void ath_ahb_exit(void) {};
781 static inline void ath9k_ps_wakeup(struct ath_softc *sc)
783 if (atomic_inc_return(&sc->ps_usecount) == 1)
784 if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) {
785 sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode;
786 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
790 static inline void ath9k_ps_restore(struct ath_softc *sc)
792 if (atomic_dec_and_test(&sc->ps_usecount))
793 if (sc->hw->conf.flags & IEEE80211_CONF_PS)
794 ath9k_hw_setpower(sc->sc_ah,
795 sc->sc_ah->ah_restore_mode);