2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #define ATHEROS_VENDOR_ID 0x168c
24 #define AR5416_DEVID_PCI 0x0023
25 #define AR5416_DEVID_PCIE 0x0024
26 #define AR9160_DEVID_PCI 0x0027
27 #define AR9280_DEVID_PCI 0x0029
28 #define AR9280_DEVID_PCIE 0x002a
29 #define AR9285_DEVID_PCIE 0x002b
31 #define AR5416_AR9100_DEVID 0x000b
33 #define AR_SUBVENDOR_ID_NOG 0x0e11
34 #define AR_SUBVENDOR_ID_NEW_A 0x7065
36 #define ATH9K_TXERR_XRETRY 0x01
37 #define ATH9K_TXERR_FILT 0x02
38 #define ATH9K_TXERR_FIFO 0x04
39 #define ATH9K_TXERR_XTXOP 0x08
40 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
42 #define ATH9K_TX_BA 0x01
43 #define ATH9K_TX_PWRMGMT 0x02
44 #define ATH9K_TX_DESC_CFG_ERR 0x04
45 #define ATH9K_TX_DATA_UNDERRUN 0x08
46 #define ATH9K_TX_DELIM_UNDERRUN 0x10
47 #define ATH9K_TX_SW_ABORTED 0x40
48 #define ATH9K_TX_SW_FILTERED 0x80
52 struct ath_tx_status {
78 struct ath_rx_status {
103 #define ATH9K_RXERR_CRC 0x01
104 #define ATH9K_RXERR_PHY 0x02
105 #define ATH9K_RXERR_FIFO 0x04
106 #define ATH9K_RXERR_DECRYPT 0x08
107 #define ATH9K_RXERR_MIC 0x10
109 #define ATH9K_RX_MORE 0x01
110 #define ATH9K_RX_MORE_AGGR 0x02
111 #define ATH9K_RX_GI 0x04
112 #define ATH9K_RX_2040 0x08
113 #define ATH9K_RX_DELIM_CRC_PRE 0x10
114 #define ATH9K_RX_DELIM_CRC_POST 0x20
115 #define ATH9K_RX_DECRYPT_BUSY 0x40
117 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
118 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
127 struct ath_tx_status tx;
128 struct ath_rx_status rx;
134 #define ds_txstat ds_us.tx
135 #define ds_rxstat ds_us.rx
136 #define ds_stat ds_us.stats
138 #define ATH9K_TXDESC_CLRDMASK 0x0001
139 #define ATH9K_TXDESC_NOACK 0x0002
140 #define ATH9K_TXDESC_RTSENA 0x0004
141 #define ATH9K_TXDESC_CTSENA 0x0008
142 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
143 * the descriptor its marked on. We take a tx interrupt to reap
144 * descriptors when the h/w hits an EOL condition or
145 * when the descriptor is specifically marked to generate
146 * an interrupt with this flag. Descriptors should be
147 * marked periodically to insure timely replenishing of the
148 * supply needed for sending frames. Defering interrupts
149 * reduces system load and potentially allows more concurrent
150 * work to be done but if done to aggressively can cause
151 * senders to backup. When the hardware queue is left too
152 * large rate control information may also be too out of
153 * date. An Alternative for this is TX interrupt mitigation
154 * but this needs more testing. */
155 #define ATH9K_TXDESC_INTREQ 0x0010
156 #define ATH9K_TXDESC_VEOL 0x0020
157 #define ATH9K_TXDESC_EXT_ONLY 0x0040
158 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
159 #define ATH9K_TXDESC_VMF 0x0100
160 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
161 #define ATH9K_TXDESC_CAB 0x0400
163 #define ATH9K_RXDESC_INTREQ 0x0020
169 ATH9K_MODE_11NA_HT20 = 6,
170 ATH9K_MODE_11NG_HT20 = 7,
171 ATH9K_MODE_11NA_HT40PLUS = 8,
172 ATH9K_MODE_11NA_HT40MINUS = 9,
173 ATH9K_MODE_11NG_HT40PLUS = 10,
174 ATH9K_MODE_11NG_HT40MINUS = 11,
179 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
180 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
181 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
182 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
183 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
184 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
185 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
186 ATH9K_HW_CAP_VEOL = BIT(7),
187 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
188 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
189 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
190 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
191 ATH9K_HW_CAP_HT = BIT(12),
192 ATH9K_HW_CAP_GTT = BIT(13),
193 ATH9K_HW_CAP_FASTCC = BIT(14),
194 ATH9K_HW_CAP_RFSILENT = BIT(15),
195 ATH9K_HW_CAP_WOW = BIT(16),
196 ATH9K_HW_CAP_CST = BIT(17),
197 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
198 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
199 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
200 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
201 ATH9K_HW_CAP_BT_COEX = BIT(22)
204 enum ath9k_capability_type {
205 ATH9K_CAP_CIPHER = 0,
207 ATH9K_CAP_TKIP_SPLIT,
208 ATH9K_CAP_PHYCOUNTERS,
212 ATH9K_CAP_MCAST_KEYSRCH,
213 ATH9K_CAP_TSF_ADJUST,
214 ATH9K_CAP_WME_TKIPMIC,
216 ATH9K_CAP_ANT_CFG_2GHZ,
217 ATH9K_CAP_ANT_CFG_5GHZ
220 struct ath9k_hw_capabilities {
221 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
222 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
225 u16 low_5ghz_chan, high_5ghz_chan;
226 u16 low_2ghz_chan, high_2ghz_chan;
231 u16 tx_triglevel_max;
238 struct ath9k_ops_config {
239 int dma_beacon_response_time;
240 int sw_beacon_response_time;
241 int additional_swba_backoff;
243 int cwm_ignore_extcca;
244 u8 pcie_powersave_enable;
245 u8 pcie_l1skp_enable;
248 int pcie_power_reset;
257 u8 noise_immunity_level;
258 u32 ofdm_weaksignal_det;
259 u32 cck_weaksignal_thr;
260 u8 spur_immunity_level;
262 int8_t rssi_thr_high;
264 u16 diversity_control;
265 u16 antenna_switch_swap;
266 int serialize_regmode;
268 #define SPUR_DISABLE 0
269 #define SPUR_ENABLE_IOCTL 1
270 #define SPUR_ENABLE_EEPROM 2
271 #define AR_EEPROM_MODAL_SPURS 5
272 #define AR_SPUR_5413_1 1640
273 #define AR_SPUR_5413_2 1200
274 #define AR_NO_SPUR 0x8000
275 #define AR_BASE_FREQ_2GHZ 2300
276 #define AR_BASE_FREQ_5GHZ 4900
277 #define AR_SPUR_FEEQ_BOUND_HT40 19
278 #define AR_SPUR_FEEQ_BOUND_HT20 10
280 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
283 enum ath9k_tx_queue {
284 ATH9K_TX_QUEUE_INACTIVE = 0,
286 ATH9K_TX_QUEUE_BEACON,
288 ATH9K_TX_QUEUE_UAPSD,
289 ATH9K_TX_QUEUE_PSPOLL
292 #define ATH9K_NUM_TX_QUEUES 10
294 enum ath9k_tx_queue_subtype {
302 enum ath9k_tx_queue_flags {
303 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
304 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
305 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
306 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
307 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
308 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
309 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
310 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
311 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
314 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
316 #define ATH9K_DECOMP_MASK_SIZE 128
317 #define ATH9K_READY_TIME_LO_BOUND 50
318 #define ATH9K_READY_TIME_HI_BOUND 96
320 enum ath9k_pkt_type {
321 ATH9K_PKT_TYPE_NORMAL = 0,
323 ATH9K_PKT_TYPE_PSPOLL,
324 ATH9K_PKT_TYPE_BEACON,
325 ATH9K_PKT_TYPE_PROBE_RESP,
326 ATH9K_PKT_TYPE_CHIRP,
327 ATH9K_PKT_TYPE_GRP_POLL,
330 struct ath9k_tx_queue_info {
332 enum ath9k_tx_queue tqi_type;
333 enum ath9k_tx_queue_subtype tqi_subtype;
334 enum ath9k_tx_queue_flags tqi_qflags;
342 u32 tqi_cbrOverflowLimit;
349 enum ath9k_rx_filter {
350 ATH9K_RX_FILTER_UCAST = 0x00000001,
351 ATH9K_RX_FILTER_MCAST = 0x00000002,
352 ATH9K_RX_FILTER_BCAST = 0x00000004,
353 ATH9K_RX_FILTER_CONTROL = 0x00000008,
354 ATH9K_RX_FILTER_BEACON = 0x00000010,
355 ATH9K_RX_FILTER_PROM = 0x00000020,
356 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
357 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
358 ATH9K_RX_FILTER_PHYERR = 0x00000100,
359 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
363 ATH9K_INT_RX = 0x00000001,
364 ATH9K_INT_RXDESC = 0x00000002,
365 ATH9K_INT_RXNOFRM = 0x00000008,
366 ATH9K_INT_RXEOL = 0x00000010,
367 ATH9K_INT_RXORN = 0x00000020,
368 ATH9K_INT_TX = 0x00000040,
369 ATH9K_INT_TXDESC = 0x00000080,
370 ATH9K_INT_TIM_TIMER = 0x00000100,
371 ATH9K_INT_TXURN = 0x00000800,
372 ATH9K_INT_MIB = 0x00001000,
373 ATH9K_INT_RXPHY = 0x00004000,
374 ATH9K_INT_RXKCM = 0x00008000,
375 ATH9K_INT_SWBA = 0x00010000,
376 ATH9K_INT_BMISS = 0x00040000,
377 ATH9K_INT_BNR = 0x00100000,
378 ATH9K_INT_TIM = 0x00200000,
379 ATH9K_INT_DTIM = 0x00400000,
380 ATH9K_INT_DTIMSYNC = 0x00800000,
381 ATH9K_INT_GPIO = 0x01000000,
382 ATH9K_INT_CABEND = 0x02000000,
383 ATH9K_INT_CST = 0x10000000,
384 ATH9K_INT_GTT = 0x20000000,
385 ATH9K_INT_FATAL = 0x40000000,
386 ATH9K_INT_GLOBAL = 0x80000000,
387 ATH9K_INT_BMISC = ATH9K_INT_TIM |
391 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
403 ATH9K_INT_NOCARD = 0xffffffff
406 #define ATH9K_RATESERIES_RTS_CTS 0x0001
407 #define ATH9K_RATESERIES_2040 0x0002
408 #define ATH9K_RATESERIES_HALFGI 0x0004
410 struct ath9k_11n_rate_series {
418 #define CHANNEL_CW_INT 0x00002
419 #define CHANNEL_CCK 0x00020
420 #define CHANNEL_OFDM 0x00040
421 #define CHANNEL_2GHZ 0x00080
422 #define CHANNEL_5GHZ 0x00100
423 #define CHANNEL_PASSIVE 0x00200
424 #define CHANNEL_DYN 0x00400
425 #define CHANNEL_HALF 0x04000
426 #define CHANNEL_QUARTER 0x08000
427 #define CHANNEL_HT20 0x10000
428 #define CHANNEL_HT40PLUS 0x20000
429 #define CHANNEL_HT40MINUS 0x40000
431 #define CHANNEL_INTERFERENCE 0x01
432 #define CHANNEL_DFS 0x02
433 #define CHANNEL_4MS_LIMIT 0x04
434 #define CHANNEL_DFS_CLEAR 0x08
435 #define CHANNEL_DISALLOW_ADHOC 0x10
436 #define CHANNEL_PER_11D_ADHOC 0x20
438 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
439 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
440 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
441 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
442 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
443 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
444 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
445 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
446 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
447 #define CHANNEL_ALL \
456 struct ath9k_channel {
457 struct ieee80211_channel *chan;
462 bool oneTimeCalsDone;
465 int16_t rawNoiseFloor;
468 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
469 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
470 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
471 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
472 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
473 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
474 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
475 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
476 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
477 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
478 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
479 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
480 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
481 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
483 /* These macros check chanmode and not channelFlags */
484 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
485 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
486 ((_c)->chanmode == CHANNEL_G_HT20))
487 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
488 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
489 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
490 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
491 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
493 #define IS_CHAN_A_5MHZ_SPACED(_c) \
494 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
495 (((_c)->channel % 20) != 0) && \
496 (((_c)->channel % 10) != 0))
498 struct ath9k_keyval {
507 enum ath9k_key_type {
508 ATH9K_KEY_TYPE_CLEAR,
515 ATH9K_CIPHER_WEP = 0,
516 ATH9K_CIPHER_AES_OCB = 1,
517 ATH9K_CIPHER_AES_CCM = 2,
518 ATH9K_CIPHER_CKIP = 3,
519 ATH9K_CIPHER_TKIP = 4,
520 ATH9K_CIPHER_CLR = 5,
521 ATH9K_CIPHER_MIC = 127
524 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
525 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
526 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
527 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
528 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
529 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
530 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
531 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
532 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
534 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
535 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
536 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
537 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
538 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
539 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
541 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
542 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
544 #define SD_NO_CTL 0xE0
555 #define AR_EEPROM_MAC(i) (0x1d+(i))
557 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
558 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
559 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
560 #define AR_EEPROM_RFSILENT_POLARITY_S 1
562 #define CTRY_DEBUG 0x1ff
563 #define CTRY_DEFAULT 0
565 enum reg_ext_bitmap {
566 REG_EXT_JAPAN_MIDBAND = 1,
567 REG_EXT_FCC_DFS_HT40 = 2,
568 REG_EXT_JAPAN_NONDFS_HT40 = 3,
569 REG_EXT_JAPAN_DFS_HT40 = 4
572 struct ath9k_country_entry {
581 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
582 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
584 #define SM(_v, _f) (((_v) << _f##_S) & _f)
585 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
586 #define REG_RMW(_a, _r, _set, _clr) \
587 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
588 #define REG_RMW_FIELD(_a, _r, _f, _v) \
590 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
591 #define REG_SET_BIT(_a, _r, _f) \
592 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
593 #define REG_CLR_BIT(_a, _r, _f) \
594 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
596 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
599 #define INIT_CWMIN 15
600 #define INIT_CWMIN_11B 31
601 #define INIT_CWMAX 1023
602 #define INIT_SH_RETRY 10
603 #define INIT_LG_RETRY 10
604 #define INIT_SSH_RETRY 32
605 #define INIT_SLG_RETRY 32
607 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
609 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
610 #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
612 #define IEEE80211_WEP_IVLEN 3
613 #define IEEE80211_WEP_KIDLEN 1
614 #define IEEE80211_WEP_CRCLEN 4
615 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
616 (IEEE80211_WEP_IVLEN + \
617 IEEE80211_WEP_KIDLEN + \
618 IEEE80211_WEP_CRCLEN))
619 #define MAX_RATE_POWER 63
621 enum ath9k_power_mode {
624 ATH9K_PM_NETWORK_SLEEP,
628 struct ath9k_mib_stats {
636 enum ath9k_ant_setting {
637 ATH9K_ANT_VARIABLE = 0,
642 #define ATH9K_SLOT_TIME_6 6
643 #define ATH9K_SLOT_TIME_9 9
644 #define ATH9K_SLOT_TIME_20 20
646 enum ath9k_ht_macmode {
647 ATH9K_HT_MACMODE_20 = 0,
648 ATH9K_HT_MACMODE_2040 = 1,
651 enum ath9k_ht_extprotspacing {
652 ATH9K_HT_EXTPROTSPACING_20 = 0,
653 ATH9K_HT_EXTPROTSPACING_25 = 1,
656 struct ath9k_ht_cwm {
657 enum ath9k_ht_macmode ht_macmode;
658 enum ath9k_ht_extprotspacing ht_extprotspacing;
662 ATH9K_ANI_PRESENT = 0x1,
663 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
664 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
665 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
666 ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
667 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
668 ATH9K_ANI_MODE = 0x40,
669 ATH9K_ANI_PHYERR_RESET = 0x80,
676 WLAN_RC_PHY_HT_20_SS,
677 WLAN_RC_PHY_HT_20_DS,
678 WLAN_RC_PHY_HT_40_SS,
679 WLAN_RC_PHY_HT_40_DS,
680 WLAN_RC_PHY_HT_20_SS_HGI,
681 WLAN_RC_PHY_HT_20_DS_HGI,
682 WLAN_RC_PHY_HT_40_SS_HGI,
683 WLAN_RC_PHY_HT_40_DS_HGI,
687 enum ath9k_tp_scale {
688 ATH9K_TP_SCALE_MAX = 0,
696 SER_REG_MODE_OFF = 0,
698 SER_REG_MODE_AUTO = 2,
701 #define AR_PHY_CCA_MAX_GOOD_VALUE -85
702 #define AR_PHY_CCA_MAX_HIGH_VALUE -62
703 #define AR_PHY_CCA_MIN_BAD_VALUE -121
704 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
705 #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
707 #define ATH9K_NF_CAL_HIST_MAX 5
708 #define NUM_NF_READINGS 6
710 struct ath9k_nfcal_hist {
711 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
717 struct ath9k_beacon_state {
721 #define ATH9K_BEACON_PERIOD 0x0000ffff
722 #define ATH9K_BEACON_ENA 0x00800000
723 #define ATH9K_BEACON_RESET_TSF 0x01000000
726 u16 bs_cfpmaxduration;
729 u16 bs_bmissthreshold;
730 u32 bs_sleepduration;
733 struct ath9k_node_stats {
740 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
742 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
743 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
744 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
745 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
746 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
747 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
750 ATH9K_RESET_POWER_ON,
755 #define AH_USE_EEPROM 0x1
764 u16 ah_analog5GhzRev;
765 u16 ah_analog2GhzRev;
768 struct ath_softc *ah_sc;
770 enum nl80211_iftype ah_opmode;
771 struct ath9k_ops_config ah_config;
772 struct ath9k_hw_capabilities ah_caps;
776 int16_t ah_powerLimit;
777 u16 ah_maxPowerLevel;
781 u16 ah_currentRDInUse;
783 struct reg_dmn_pair_mapping *regpair;
784 enum ath9k_power_mode ah_power_mode;
785 enum ath9k_power_mode ah_restore_mode;
787 struct ath9k_channel ah_channels[38];
788 struct ath9k_channel *ah_curchan;
790 bool ah_isPciExpress;
794 u32 ah_rfkill_polarity;
795 u32 ah_btactive_gpio;
796 u32 ah_wlanactive_gpio;
797 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
802 struct chan_centers {
808 struct ath_rate_table;
812 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val);
813 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
814 bool ath9k_get_channel_edges(struct ath_hal *ah,
817 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
818 struct ath_rate_table *rates,
819 u32 frameLen, u16 rateix,
821 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
822 struct ath9k_channel *chan,
823 struct chan_centers *centers);
827 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
828 void ath9k_hw_detach(struct ath_hal *ah);
829 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
830 void __iomem *mem, int *error);
831 void ath9k_hw_rfdetach(struct ath_hal *ah);
836 int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
837 bool bChannelChange);
839 /* Key Cache Management */
841 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
842 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac);
843 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
844 const struct ath9k_keyval *k,
845 const u8 *mac, int xorKey);
846 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
848 /* Power Management */
850 bool ath9k_hw_setpower(struct ath_hal *ah,
851 enum ath9k_power_mode mode);
852 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
856 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period);
857 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
858 const struct ath9k_beacon_state *bs);
859 /* HW Capabilities */
861 bool ath9k_hw_fill_cap_info(struct ath_hal *ah);
862 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
863 u32 capability, u32 *result);
864 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
865 u32 capability, u32 setting, int *status);
867 /* GPIO / RFKILL / Antennae */
869 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio);
870 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
871 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
873 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val);
874 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
875 void ath9k_enable_rfkill(struct ath_hal *ah);
877 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
878 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
879 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
880 enum ath9k_ant_setting settings,
881 struct ath9k_channel *chan,
886 /* General Operation */
888 u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
889 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
890 bool ath9k_hw_phy_disable(struct ath_hal *ah);
891 bool ath9k_hw_disable(struct ath_hal *ah);
892 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
893 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
894 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
895 void ath9k_hw_setopmode(struct ath_hal *ah);
896 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1);
897 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
898 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask);
899 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId);
900 u64 ath9k_hw_gettsf64(struct ath_hal *ah);
901 void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64);
902 void ath9k_hw_reset_tsf(struct ath_hal *ah);
903 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting);
904 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
905 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
908 u16 ath9k_regd_get_rd(struct ath_hal *ah);
909 bool ath9k_is_world_regd(struct ath_hal *ah);
910 const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah);
911 const struct ieee80211_regdomain *ath9k_default_world_regdomain(void);
913 void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby);
914 void ath9k_reg_apply_radar_flags(struct wiphy *wiphy);
916 int ath9k_regd_init(struct ath_hal *ah);
917 bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah);
918 u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
919 int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
923 void ath9k_ani_reset(struct ath_hal *ah);
924 void ath9k_hw_ani_monitor(struct ath_hal *ah,
925 const struct ath9k_node_stats *stats,
926 struct ath9k_channel *chan);
927 bool ath9k_hw_phycounters(struct ath_hal *ah);
928 void ath9k_enable_mib_counters(struct ath_hal *ah);
929 void ath9k_hw_disable_mib_counters(struct ath_hal *ah);
930 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
934 void ath9k_hw_procmibevent(struct ath_hal *ah,
935 const struct ath9k_node_stats *stats);
936 void ath9k_hw_ani_setup(struct ath_hal *ah);
937 void ath9k_hw_ani_attach(struct ath_hal *ah);
938 void ath9k_hw_ani_detach(struct ath_hal *ah);
942 bool ath9k_hw_reset_calvalid(struct ath_hal *ah);
943 void ath9k_hw_start_nfcal(struct ath_hal *ah);
944 void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
945 int16_t ath9k_hw_getnf(struct ath_hal *ah,
946 struct ath9k_channel *chan);
947 void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah);
948 s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan);
949 bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
950 u8 rxchainmask, bool longcal,
952 bool ath9k_hw_init_cal(struct ath_hal *ah,
953 struct ath9k_channel *chan);
958 int ath9k_hw_set_txpower(struct ath_hal *ah,
959 struct ath9k_channel *chan,
961 u8 twiceAntennaReduction,
962 u8 twiceMaxRegulatoryPower,
964 void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan);
965 bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
966 struct ath9k_channel *chan,
970 u8 twiceMaxRegulatoryPower,
972 bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
973 struct ath9k_channel *chan,
974 int16_t *pTxPowerIndexOffset);
975 bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
976 struct ath9k_channel *chan);
977 int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
978 struct ath9k_channel *chan,
979 u8 index, u16 *config);
980 u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
981 enum ieee80211_band freq_band);
982 u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz);
983 int ath9k_hw_eeprom_attach(struct ath_hal *ah);
985 /* Interrupt Handling */
987 bool ath9k_hw_intrpend(struct ath_hal *ah);
988 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
989 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
990 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints);
994 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
995 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp);
996 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
997 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
998 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel);
999 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
1000 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1001 u32 segLen, bool firstSeg,
1002 bool lastSeg, const struct ath_desc *ds0);
1003 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1004 int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds);
1005 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1006 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
1007 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
1008 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
1009 struct ath_desc *lastds,
1010 u32 durUpdateEn, u32 rtsctsRate,
1012 struct ath9k_11n_rate_series series[],
1013 u32 nseries, u32 flags);
1014 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1016 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1018 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1019 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1020 void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
1022 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
1024 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1025 bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
1026 const struct ath9k_tx_queue_info *qinfo);
1027 bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
1028 struct ath9k_tx_queue_info *qinfo);
1029 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1030 const struct ath9k_tx_queue_info *qinfo);
1031 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
1032 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
1033 int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
1034 u32 pa, struct ath_desc *nds, u64 tsf);
1035 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1036 u32 size, u32 flags);
1037 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
1038 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
1039 void ath9k_hw_rxena(struct ath_hal *ah);
1040 void ath9k_hw_startpcureceive(struct ath_hal *ah);
1041 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1042 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
1043 void ath9k_hw_btcoex_enable(struct ath_hal *ah);