2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #define ATHEROS_VENDOR_ID 0x168c
24 #define AR5416_DEVID_PCI 0x0023
25 #define AR5416_DEVID_PCIE 0x0024
26 #define AR9160_DEVID_PCI 0x0027
27 #define AR9280_DEVID_PCI 0x0029
28 #define AR9280_DEVID_PCIE 0x002a
30 #define AR5416_AR9100_DEVID 0x000b
32 #define AR_SUBVENDOR_ID_NOG 0x0e11
33 #define AR_SUBVENDOR_ID_NEW_A 0x7065
35 #define ATH9K_TXERR_XRETRY 0x01
36 #define ATH9K_TXERR_FILT 0x02
37 #define ATH9K_TXERR_FIFO 0x04
38 #define ATH9K_TXERR_XTXOP 0x08
39 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
41 #define ATH9K_TX_BA 0x01
42 #define ATH9K_TX_PWRMGMT 0x02
43 #define ATH9K_TX_DESC_CFG_ERR 0x04
44 #define ATH9K_TX_DATA_UNDERRUN 0x08
45 #define ATH9K_TX_DELIM_UNDERRUN 0x10
46 #define ATH9K_TX_SW_ABORTED 0x40
47 #define ATH9K_TX_SW_FILTERED 0x80
51 struct ath_tx_status {
77 struct ath_rx_status {
102 #define ATH9K_RXERR_CRC 0x01
103 #define ATH9K_RXERR_PHY 0x02
104 #define ATH9K_RXERR_FIFO 0x04
105 #define ATH9K_RXERR_DECRYPT 0x08
106 #define ATH9K_RXERR_MIC 0x10
108 #define ATH9K_RX_MORE 0x01
109 #define ATH9K_RX_MORE_AGGR 0x02
110 #define ATH9K_RX_GI 0x04
111 #define ATH9K_RX_2040 0x08
112 #define ATH9K_RX_DELIM_CRC_PRE 0x10
113 #define ATH9K_RX_DELIM_CRC_POST 0x20
114 #define ATH9K_RX_DECRYPT_BUSY 0x40
116 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
117 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
126 struct ath_tx_status tx;
127 struct ath_rx_status rx;
133 #define ds_txstat ds_us.tx
134 #define ds_rxstat ds_us.rx
135 #define ds_stat ds_us.stats
137 #define ATH9K_TXDESC_CLRDMASK 0x0001
138 #define ATH9K_TXDESC_NOACK 0x0002
139 #define ATH9K_TXDESC_RTSENA 0x0004
140 #define ATH9K_TXDESC_CTSENA 0x0008
141 #define ATH9K_TXDESC_INTREQ 0x0010
142 #define ATH9K_TXDESC_VEOL 0x0020
143 #define ATH9K_TXDESC_EXT_ONLY 0x0040
144 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
145 #define ATH9K_TXDESC_VMF 0x0100
146 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
148 #define ATH9K_RXDESC_INTREQ 0x0020
150 enum hal_capability_type {
159 HAL_CAP_MCAST_KEYSRCH,
163 HAL_CAP_ANT_CFG_2GHZ,
167 struct hal_capabilities {
168 u32 halChanSpreadSupport:1,
169 halChapTuningSupport:1,
170 halMicAesCcmSupport:1,
173 halCipherAesCcmSupport:1,
174 halCipherCkipSupport:1,
175 halCipherTkipSupport:1,
177 halBssIdMaskSupport:1,
178 halMcastKeySrchSupport:1,
181 halChanQuarterRate:1,
185 halRfSilentSupport:1,
188 halEnhancedPmSupport:1,
189 halAutoSleepSupport:1,
190 hal4kbSplitTransSupport:1,
191 halWowMatchPatternExact:1;
192 u32 halWirelessModes;
195 u16 halLow5GhzChan, halHigh5GhzChan;
196 u16 halLow2GhzChan, halHigh2GhzChan;
201 u16 halTxTrigLevelMax;
208 struct hal_ops_config {
209 int ath_hal_dma_beacon_response_time;
210 int ath_hal_sw_beacon_response_time;
211 int ath_hal_additional_swba_backoff;
213 int ath_hal_cwmIgnoreExtCCA;
214 u8 ath_hal_pciePowerSaveEnable;
215 u8 ath_hal_pcieL1SKPEnable;
216 u8 ath_hal_pcieClockReq;
217 u32 ath_hal_pcieWaen;
218 int ath_hal_pciePowerReset;
219 u8 ath_hal_pcieRestore;
220 u8 ath_hal_analogShiftReg;
222 u32 ath_hal_ofdmTrigLow;
223 u32 ath_hal_ofdmTrigHigh;
224 u32 ath_hal_cckTrigHigh;
225 u32 ath_hal_cckTrigLow;
226 u32 ath_hal_enableANI;
227 u8 ath_hal_noiseImmunityLvl;
228 u32 ath_hal_ofdmWeakSigDet;
229 u32 ath_hal_cckWeakSigThr;
230 u8 ath_hal_spurImmunityLvl;
231 u8 ath_hal_firStepLvl;
232 int8_t ath_hal_rssiThrHigh;
233 int8_t ath_hal_rssiThrLow;
234 u16 ath_hal_diversityControl;
235 u16 ath_hal_antennaSwitchSwap;
236 int ath_hal_serializeRegMode;
237 int ath_hal_intrMitigation;
238 #define SPUR_DISABLE 0
239 #define SPUR_ENABLE_IOCTL 1
240 #define SPUR_ENABLE_EEPROM 2
241 #define AR_EEPROM_MODAL_SPURS 5
242 #define AR_SPUR_5413_1 1640
243 #define AR_SPUR_5413_2 1200
244 #define AR_NO_SPUR 0x8000
245 #define AR_BASE_FREQ_2GHZ 2300
246 #define AR_BASE_FREQ_5GHZ 4900
247 #define AR_SPUR_FEEQ_BOUND_HT40 19
248 #define AR_SPUR_FEEQ_BOUND_HT20 10
249 int ath_hal_spurMode;
250 u16 ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
253 enum ath9k_tx_queue {
254 ATH9K_TX_QUEUE_INACTIVE = 0,
256 ATH9K_TX_QUEUE_BEACON,
258 ATH9K_TX_QUEUE_UAPSD,
259 ATH9K_TX_QUEUE_PSPOLL
262 #define ATH9K_NUM_TX_QUEUES 10
264 enum ath9k_tx_queue_subtype {
272 enum ath9k_tx_queue_flags {
273 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
274 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
275 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
276 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
277 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
278 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
279 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
280 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
281 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
284 struct ath9k_txq_info {
286 enum ath9k_tx_queue_subtype tqi_subtype;
287 enum ath9k_tx_queue_flags tqi_qflags;
295 u32 tqi_cbrOverflowLimit;
301 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
303 #define ATH9K_DECOMP_MASK_SIZE 128
304 #define ATH9K_READY_TIME_LO_BOUND 50
305 #define ATH9K_READY_TIME_HI_BOUND 96
307 enum ath9k_pkt_type {
308 ATH9K_PKT_TYPE_NORMAL = 0,
310 ATH9K_PKT_TYPE_PSPOLL,
311 ATH9K_PKT_TYPE_BEACON,
312 ATH9K_PKT_TYPE_PROBE_RESP,
313 ATH9K_PKT_TYPE_CHIRP,
314 ATH9K_PKT_TYPE_GRP_POLL,
317 struct ath9k_tx_queue_info {
319 enum ath9k_tx_queue tqi_type;
320 enum ath9k_tx_queue_subtype tqi_subtype;
321 enum ath9k_tx_queue_flags tqi_qflags;
329 u32 tqi_cbrOverflowLimit;
336 enum ath9k_rx_filter {
337 ATH9K_RX_FILTER_UCAST = 0x00000001,
338 ATH9K_RX_FILTER_MCAST = 0x00000002,
339 ATH9K_RX_FILTER_BCAST = 0x00000004,
340 ATH9K_RX_FILTER_CONTROL = 0x00000008,
341 ATH9K_RX_FILTER_BEACON = 0x00000010,
342 ATH9K_RX_FILTER_PROM = 0x00000020,
343 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
344 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
345 ATH9K_RX_FILTER_PHYERR = 0x00000100,
346 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
350 ATH9K_INT_RX = 0x00000001,
351 ATH9K_INT_RXDESC = 0x00000002,
352 ATH9K_INT_RXNOFRM = 0x00000008,
353 ATH9K_INT_RXEOL = 0x00000010,
354 ATH9K_INT_RXORN = 0x00000020,
355 ATH9K_INT_TX = 0x00000040,
356 ATH9K_INT_TXDESC = 0x00000080,
357 ATH9K_INT_TIM_TIMER = 0x00000100,
358 ATH9K_INT_TXURN = 0x00000800,
359 ATH9K_INT_MIB = 0x00001000,
360 ATH9K_INT_RXPHY = 0x00004000,
361 ATH9K_INT_RXKCM = 0x00008000,
362 ATH9K_INT_SWBA = 0x00010000,
363 ATH9K_INT_BMISS = 0x00040000,
364 ATH9K_INT_BNR = 0x00100000,
365 ATH9K_INT_TIM = 0x00200000,
366 ATH9K_INT_DTIM = 0x00400000,
367 ATH9K_INT_DTIMSYNC = 0x00800000,
368 ATH9K_INT_GPIO = 0x01000000,
369 ATH9K_INT_CABEND = 0x02000000,
370 ATH9K_INT_CST = 0x10000000,
371 ATH9K_INT_GTT = 0x20000000,
372 ATH9K_INT_FATAL = 0x40000000,
373 ATH9K_INT_GLOBAL = 0x80000000,
374 ATH9K_INT_BMISC = ATH9K_INT_TIM |
378 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
390 ATH9K_INT_NOCARD = 0xffffffff
393 struct ath9k_rate_table {
395 u8 rateCodeToIndex[256];
409 #define ATH9K_RATESERIES_RTS_CTS 0x0001
410 #define ATH9K_RATESERIES_2040 0x0002
411 #define ATH9K_RATESERIES_HALFGI 0x0004
413 struct ath9k_11n_rate_series {
421 #define CHANNEL_CW_INT 0x00002
422 #define CHANNEL_CCK 0x00020
423 #define CHANNEL_OFDM 0x00040
424 #define CHANNEL_2GHZ 0x00080
425 #define CHANNEL_5GHZ 0x00100
426 #define CHANNEL_PASSIVE 0x00200
427 #define CHANNEL_DYN 0x00400
428 #define CHANNEL_HALF 0x04000
429 #define CHANNEL_QUARTER 0x08000
430 #define CHANNEL_HT20 0x10000
431 #define CHANNEL_HT40PLUS 0x20000
432 #define CHANNEL_HT40MINUS 0x40000
434 #define CHANNEL_INTERFERENCE 0x01
435 #define CHANNEL_DFS 0x02
436 #define CHANNEL_4MS_LIMIT 0x04
437 #define CHANNEL_DFS_CLEAR 0x08
438 #define CHANNEL_DISALLOW_ADHOC 0x10
439 #define CHANNEL_PER_11D_ADHOC 0x20
441 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
442 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
443 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
444 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
445 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
446 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
447 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
448 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
449 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
450 #define CHANNEL_ALL \
459 struct ath9k_channel {
463 int8_t maxRegTxPower;
468 bool oneTimeCalsDone;
471 int16_t rawNoiseFloor;
474 u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
475 #ifdef ATH_NF_PER_CHAN
476 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
480 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
481 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
482 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
483 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
484 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
485 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
486 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
487 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
488 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
489 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
490 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
491 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
492 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
493 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
494 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
495 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
497 /* These macros check chanmode and not channelFlags */
498 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
499 ((_c)->chanmode == CHANNEL_G_HT20))
500 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
501 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
502 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
503 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
504 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
506 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
507 #define IS_CHAN_A_5MHZ_SPACED(_c) \
508 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
509 (((_c)->channel % 20) != 0) && \
510 (((_c)->channel % 10) != 0))
512 struct ath9k_keyval {
521 enum ath9k_key_type {
522 ATH9K_KEY_TYPE_CLEAR,
529 ATH9K_CIPHER_WEP = 0,
530 ATH9K_CIPHER_AES_OCB = 1,
531 ATH9K_CIPHER_AES_CCM = 2,
532 ATH9K_CIPHER_CKIP = 3,
533 ATH9K_CIPHER_TKIP = 4,
534 ATH9K_CIPHER_CLR = 5,
535 ATH9K_CIPHER_MIC = 127
538 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
539 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
540 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
541 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
542 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
543 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
544 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
545 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
546 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
548 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
549 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
550 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
551 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
552 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
553 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
555 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
556 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
558 #define SD_NO_CTL 0xE0
569 #define AR_EEPROM_MAC(i) (0x1d+(i))
570 #define EEP_SCALE 100
573 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
574 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
575 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
576 #define AR_EEPROM_RFSILENT_POLARITY_S 1
578 #define CTRY_DEBUG 0x1ff
579 #define CTRY_DEFAULT 0
581 enum reg_ext_bitmap {
582 REG_EXT_JAPAN_MIDBAND = 1,
583 REG_EXT_FCC_DFS_HT40 = 2,
584 REG_EXT_JAPAN_NONDFS_HT40 = 3,
585 REG_EXT_JAPAN_DFS_HT40 = 4
588 struct ath9k_country_entry {
597 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
598 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
600 #define SM(_v, _f) (((_v) << _f##_S) & _f)
601 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
602 #define REG_RMW(_a, _r, _set, _clr) \
603 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
604 #define REG_RMW_FIELD(_a, _r, _f, _v) \
606 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
607 #define REG_SET_BIT(_a, _r, _f) \
608 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
609 #define REG_CLR_BIT(_a, _r, _f) \
610 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
612 #define ATH9K_COMP_BUF_MAX_SIZE 9216
613 #define ATH9K_COMP_BUF_ALIGN_SIZE 512
615 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
618 #define INIT_CWMIN 15
619 #define INIT_CWMIN_11B 31
620 #define INIT_CWMAX 1023
621 #define INIT_SH_RETRY 10
622 #define INIT_LG_RETRY 10
623 #define INIT_SSH_RETRY 32
624 #define INIT_SLG_RETRY 32
626 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
628 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
629 #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
631 #define IEEE80211_WEP_IVLEN 3
632 #define IEEE80211_WEP_KIDLEN 1
633 #define IEEE80211_WEP_CRCLEN 4
634 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
635 (IEEE80211_WEP_IVLEN + \
636 IEEE80211_WEP_KIDLEN + \
637 IEEE80211_WEP_CRCLEN))
638 #define IEEE80211_MAX_LEN (2300 + FCS_LEN + \
639 (IEEE80211_WEP_IVLEN + \
640 IEEE80211_WEP_KIDLEN + \
641 IEEE80211_WEP_CRCLEN))
643 #define MAX_REG_ADD_COUNT 129
644 #define MAX_RATE_POWER 63
646 enum ath9k_power_mode {
649 ATH9K_PM_NETWORK_SLEEP,
653 #define HAL_ANTENNA_MIN_MODE 0
654 #define HAL_ANTENNA_FIXED_A 1
655 #define HAL_ANTENNA_FIXED_B 2
656 #define HAL_ANTENNA_MAX_MODE 3
658 struct ath9k_mib_stats {
666 enum ath9k_ant_setting {
667 ATH9K_ANT_VARIABLE = 0,
679 #define ATH9K_SLOT_TIME_6 6
680 #define ATH9K_SLOT_TIME_9 9
681 #define ATH9K_SLOT_TIME_20 20
683 enum ath9k_ht_macmode {
684 ATH9K_HT_MACMODE_20 = 0,
685 ATH9K_HT_MACMODE_2040 = 1,
688 enum ath9k_ht_extprotspacing {
689 ATH9K_HT_EXTPROTSPACING_20 = 0,
690 ATH9K_HT_EXTPROTSPACING_25 = 1,
693 struct ath9k_ht_cwm {
694 enum ath9k_ht_macmode ht_macmode;
695 enum ath9k_ht_extprotspacing ht_extprotspacing;
699 HAL_FREQ_BAND_5GHZ = 0,
700 HAL_FREQ_BAND_2GHZ = 1,
704 ATH9K_ANI_PRESENT = 0x1,
705 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
706 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
707 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
708 ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
709 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
710 ATH9K_ANI_MODE = 0x40,
711 ATH9K_ANI_PHYERR_RESET = 0x80,
722 #define PHY_CCK PHY_DS
724 enum start_adhoc_option {
731 enum ath9k_tp_scale {
732 ATH9K_TP_SCALE_MAX = 0,
740 SER_REG_MODE_OFF = 0,
742 SER_REG_MODE_AUTO = 2,
745 #define AR_PHY_CCA_MAX_GOOD_VALUE -85
746 #define AR_PHY_CCA_MAX_HIGH_VALUE -62
747 #define AR_PHY_CCA_MIN_BAD_VALUE -121
748 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
749 #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
751 #define ATH9K_NF_CAL_HIST_MAX 5
752 #define NUM_NF_READINGS 6
754 struct ath9k_nfcal_hist {
755 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
761 struct ath9k_beacon_state {
765 #define ATH9K_BEACON_PERIOD 0x0000ffff
766 #define ATH9K_BEACON_ENA 0x00800000
767 #define ATH9K_BEACON_RESET_TSF 0x01000000
770 u16 bs_cfpmaxduration;
773 u16 bs_bmissthreshold;
774 u32 bs_sleepduration;
777 struct ath9k_node_stats {
784 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
786 enum ath9k_gpio_output_mux_type {
787 ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT,
788 ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
789 ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
790 ATH9K_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
791 ATH9K_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
792 ATH9K_GPIO_OUTPUT_MUX_NUM_ENTRIES
796 ATH9K_RESET_POWER_ON,
801 #define AH_USE_EEPROM 0x1
807 struct ath_softc *ah_sc;
813 u16 ah_analog5GhzRev;
814 u16 ah_analog2GhzRev;
815 u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
817 enum ath9k_opmode ah_opmode;
818 struct hal_ops_config ah_config;
819 struct hal_capabilities ah_caps;
820 int16_t ah_powerLimit;
821 u16 ah_maxPowerLevel;
825 u16 ah_currentRDInUse;
829 enum start_adhoc_option ah_adHocMode;
831 struct ath9k_channel ah_channels[150];
833 struct ath9k_channel *ah_curchan;
835 bool ah_rfkillEnabled;
836 bool ah_isPciExpress;
838 #ifndef ATH_NF_PER_CHAN
839 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
844 WIRELESS_MODE_11a = 0,
845 WIRELESS_MODE_11b = 2,
846 WIRELESS_MODE_11g = 3,
847 WIRELESS_MODE_11NA_HT20 = 6,
848 WIRELESS_MODE_11NG_HT20 = 7,
849 WIRELESS_MODE_11NA_HT40PLUS = 8,
850 WIRELESS_MODE_11NA_HT40MINUS = 9,
851 WIRELESS_MODE_11NG_HT40PLUS = 10,
852 WIRELESS_MODE_11NG_HT40MINUS = 11,
857 ATH9K_MODE_SEL_11A = 0x00001,
858 ATH9K_MODE_SEL_11B = 0x00002,
859 ATH9K_MODE_SEL_11G = 0x00004,
860 ATH9K_MODE_SEL_11NG_HT20 = 0x00008,
861 ATH9K_MODE_SEL_11NA_HT20 = 0x00010,
862 ATH9K_MODE_SEL_11NG_HT40PLUS = 0x00020,
863 ATH9K_MODE_SEL_11NG_HT40MINUS = 0x00040,
864 ATH9K_MODE_SEL_11NA_HT40PLUS = 0x00080,
865 ATH9K_MODE_SEL_11NA_HT40MINUS = 0x00100,
866 ATH9K_MODE_SEL_2GHZ = (ATH9K_MODE_SEL_11B |
868 ATH9K_MODE_SEL_11NG_HT20),
869 ATH9K_MODE_SEL_5GHZ = (ATH9K_MODE_SEL_11A |
870 ATH9K_MODE_SEL_11NA_HT20),
871 ATH9K_MODE_SEL_ALL = 0xffffffff
874 struct chan_centers {
880 int ath_hal_getcapability(struct ath_hal *ah,
881 enum hal_capability_type type,
884 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
886 void ath9k_hw_detach(struct ath_hal *ah);
887 struct ath_hal *ath9k_hw_attach(u16 devid,
888 struct ath_softc *sc,
891 bool ath9k_regd_init_channels(struct ath_hal *ah,
892 u32 maxchans, u32 *nchans,
894 u32 maxregids, u32 *nregids,
895 u16 cc, u32 modeSelect,
897 bool enableExtendedChannels);
898 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
899 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,
900 enum ath9k_int ints);
901 bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
902 struct ath9k_channel *chan,
903 enum ath9k_ht_macmode macmode,
904 u8 txchainmask, u8 rxchainmask,
905 enum ath9k_ht_extprotspacing extprotspacing,
908 bool ath9k_hw_phy_disable(struct ath_hal *ah);
909 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
911 void ath9k_hw_ani_monitor(struct ath_hal *ah,
912 const struct ath9k_node_stats *stats,
913 struct ath9k_channel *chan);
914 bool ath9k_hw_calibrate(struct ath_hal *ah,
915 struct ath9k_channel *chan,
919 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
920 struct ath9k_channel *chan);
921 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
923 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
924 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
926 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
927 void ath9k_hw_reset_tsf(struct ath_hal *ah);
928 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
929 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
931 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
933 const struct ath9k_keyval *k,
936 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
938 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
939 bool ath9k_hw_intrpend(struct ath_hal *ah);
940 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
941 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
943 void ath9k_hw_procmibevent(struct ath_hal *ah,
944 const struct ath9k_node_stats *stats);
945 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
946 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
947 bool ath9k_hw_phycounters(struct ath_hal *ah);
948 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
949 bool ath9k_hw_getcapability(struct ath_hal *ah,
950 enum hal_capability_type type,
953 bool ath9k_hw_setcapability(struct ath_hal *ah,
954 enum hal_capability_type type,
958 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
959 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
960 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
961 bool ath9k_hw_setbssidmask(struct ath_hal *ah,
963 bool ath9k_hw_setpower(struct ath_hal *ah,
964 enum ath9k_power_mode mode);
965 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
966 u64 ath9k_hw_gettsf64(struct ath_hal *ah);
967 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
968 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
969 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
970 enum ath9k_ant_setting settings,
971 struct ath9k_channel *chan,
975 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
976 int ath9k_hw_select_antconfig(struct ath_hal *ah,
978 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
980 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
981 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
982 const struct ath9k_rate_table *rates,
983 u32 frameLen, u16 rateix,
985 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
986 struct ath_desc *lastds,
987 u32 durUpdateEn, u32 rtsctsRate,
989 struct ath9k_11n_rate_series series[],
990 u32 nseries, u32 flags);
991 void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
994 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
995 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
996 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
997 u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
998 u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
999 struct ath9k_channel *chan);
1000 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
1001 bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
1002 struct ath9k_txq_info *qInfo);
1003 bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
1004 const struct ath9k_txq_info *qInfo);
1005 struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
1006 const struct ath9k_channel *c);
1007 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1008 u32 pktLen, enum ath9k_pkt_type type,
1009 u32 txPower, u32 keyIx,
1010 enum ath9k_key_type keyType, u32 flags);
1011 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1012 u32 segLen, bool firstSeg,
1014 const struct ath_desc *ds0);
1015 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1019 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
1020 void ath9k_hw_beaconinit(struct ath_hal *ah,
1021 u32 next_beacon, u32 beacon_period);
1022 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
1023 const struct ath9k_beacon_state *bs);
1024 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1025 u32 size, u32 flags);
1026 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
1027 void ath9k_hw_rxena(struct ath_hal *ah);
1028 void ath9k_hw_setopmode(struct ath_hal *ah);
1029 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
1030 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
1032 u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
1033 void ath9k_hw_startpcureceive(struct ath_hal *ah);
1034 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1035 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
1036 int ath9k_hw_rxprocdesc(struct ath_hal *ah,
1037 struct ath_desc *ds, u32 pa,
1038 struct ath_desc *nds, u64 tsf);
1039 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
1040 int ath9k_hw_txprocdesc(struct ath_hal *ah,
1041 struct ath_desc *ds);
1042 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1044 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1046 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1047 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
1048 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1049 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1050 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
1051 struct ath_desc *ds, u32 vmf);
1052 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
1053 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
1054 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1055 const struct ath9k_txq_info *qInfo);
1056 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
1057 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
1058 bool ath9k_hw_disable(struct ath_hal *ah);
1059 void ath9k_hw_rfdetach(struct ath_hal *ah);
1060 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1061 struct ath9k_channel *chan,
1062 struct chan_centers *centers);
1063 bool ath9k_get_channel_edges(struct ath_hal *ah,
1064 u16 flags, u16 *low,