2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
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39 * Defintions for the Atheros Wireless LAN controller driver.
41 #ifndef _DEV_ATH_ATHVAR_H
42 #define _DEV_ATH_ATHVAR_H
44 #include <linux/interrupt.h>
45 #include <linux/list.h>
46 #include <linux/wireless.h>
47 #include <linux/if_ether.h>
48 #include <linux/leds.h>
53 #define ATH_RXBUF 40 /* number of RX buffers */
54 #define ATH_TXBUF 200 /* number of TX buffers */
55 #define ATH_BCBUF 1 /* number of beacon buffers */
58 struct list_head list;
59 unsigned int flags; /* rx descriptor flags */
60 struct ath5k_desc *desc; /* virtual addr of desc */
61 dma_addr_t daddr; /* physical addr of desc */
62 struct sk_buff *skb; /* skbuff for buf */
63 dma_addr_t skbaddr;/* physical addr of skb data */
67 * Data transmit queue state. One of these exists for each
68 * hardware transmit queue. Packets sent to us from above
69 * are assigned to queues based on their priority. Not all
70 * devices support a complete set of hardware transmit queues.
71 * For those devices the array sc_ac2q will map multiple
72 * priorities to fewer hardware queues (typically all to one
76 unsigned int qnum; /* hardware q number */
77 u32 *link; /* link ptr in last TX desc */
78 struct list_head q; /* transmit queue */
79 spinlock_t lock; /* lock on q and link */
83 #define ATH5K_LED_MAX_NAME_LEN 31
86 * State for LED triggers
90 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
91 struct ath5k_softc *sc; /* driver state */
92 struct led_classdev led_dev; /* led classdev */
97 #define ATH_CHAN_MAX (26+26+26+200+200)
99 #define ATH_CHAN_MAX (14+14+14+252+20)
102 /* Software Carrier, keeps track of the driver state
103 * associated with an instance of a device */
105 struct pci_dev *pdev; /* for dma mapping */
106 void __iomem *iobase; /* address of the device */
107 struct mutex lock; /* dev-level lock */
108 /* FIXME: how many does it really need? */
109 struct ieee80211_tx_queue_stats tx_stats[16];
110 struct ieee80211_low_level_stats ll_stats;
111 struct ieee80211_hw *hw; /* IEEE 802.11 common */
112 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
113 struct ieee80211_channel channels[ATH_CHAN_MAX];
114 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
115 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
116 enum nl80211_iftype opmode;
117 struct ath5k_hw *ah; /* Atheros HW */
119 struct ieee80211_supported_band *curband;
121 #ifdef CONFIG_ATH5K_DEBUG
122 struct ath5k_dbg_info debug; /* debug info */
123 #endif /* CONFIG_ATH5K_DEBUG */
125 struct ath5k_buf *bufptr; /* allocated buffer ptr */
126 struct ath5k_desc *desc; /* TX/RX descriptors */
127 dma_addr_t desc_daddr; /* DMA (physical) address */
128 size_t desc_len; /* size of TX/RX descriptors */
129 u16 cachelsz; /* cache line size */
131 DECLARE_BITMAP(status, 5);
132 #define ATH_STAT_INVALID 0 /* disable hardware accesses */
133 #define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
134 #define ATH_STAT_PROMISC 2
135 #define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
136 #define ATH_STAT_STARTED 4 /* opened & irqs enabled */
138 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
139 unsigned int curmode; /* current phy mode */
140 struct ieee80211_channel *curchan; /* current h/w channel */
142 struct ieee80211_vif *vif;
144 enum ath5k_int imask; /* interrupt mask copy */
146 DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */
148 u8 bssidmask[ETH_ALEN];
150 unsigned int led_pin, /* GPIO pin for driving LED */
151 led_on; /* pin setting for LED on */
153 struct tasklet_struct restq; /* reset tasklet */
155 unsigned int rxbufsize; /* rx size based on mtu */
156 struct list_head rxbuf; /* receive buffer */
157 spinlock_t rxbuflock;
158 u32 *rxlink; /* link ptr in last RX desc */
159 struct tasklet_struct rxtq; /* rx intr tasklet */
160 struct ath5k_led rx_led; /* rx led */
162 struct list_head txbuf; /* transmit buffer */
163 spinlock_t txbuflock;
164 unsigned int txbuf_len; /* buf count in txbuf list */
165 struct ath5k_txq txqs[2]; /* beacon and tx */
167 struct ath5k_txq *txq; /* beacon and tx*/
168 struct tasklet_struct txtq; /* tx intr tasklet */
169 struct ath5k_led tx_led; /* tx led */
171 spinlock_t block; /* protects beacon */
172 struct tasklet_struct beacontq; /* beacon intr tasklet */
173 struct ath5k_buf *bbuf; /* beacon buffer */
174 unsigned int bhalq, /* SW q for outgoing beacons */
175 bmisscount, /* missed beacon transmits */
176 bintval, /* beacon interval in TU */
178 unsigned int nexttbtt; /* next beacon time in TU */
180 struct timer_list calib_tim; /* calibration timer */
181 int power_level; /* Requested tx power in dbm */
182 bool assoc; /* assocate state */
185 #define ath5k_hw_hasbssidmask(_ah) \
186 (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
187 #define ath5k_hw_hasveol(_ah) \
188 (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)