2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
53 #include <net/ieee80211_radiotap.h>
55 #include <asm/unaligned.h>
61 /* unaligned little endian access */
62 #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63 #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
70 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
87 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
109 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
112 static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
121 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
122 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
123 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
124 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
125 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
126 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
127 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
128 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
129 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
130 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
131 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
132 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
136 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
142 * Prototypes - PCI stack related functions
144 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
145 const struct pci_device_id *id);
146 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
148 static int ath5k_pci_suspend(struct pci_dev *pdev,
150 static int ath5k_pci_resume(struct pci_dev *pdev);
152 #define ath5k_pci_suspend NULL
153 #define ath5k_pci_resume NULL
154 #endif /* CONFIG_PM */
156 static struct pci_driver ath5k_pci_driver = {
158 .id_table = ath5k_pci_id_table,
159 .probe = ath5k_pci_probe,
160 .remove = __devexit_p(ath5k_pci_remove),
161 .suspend = ath5k_pci_suspend,
162 .resume = ath5k_pci_resume,
168 * Prototypes - MAC 802.11 stack related functions
170 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
171 struct ieee80211_tx_control *ctl);
172 static int ath5k_reset(struct ieee80211_hw *hw);
173 static int ath5k_start(struct ieee80211_hw *hw);
174 static void ath5k_stop(struct ieee80211_hw *hw);
175 static int ath5k_add_interface(struct ieee80211_hw *hw,
176 struct ieee80211_if_init_conf *conf);
177 static void ath5k_remove_interface(struct ieee80211_hw *hw,
178 struct ieee80211_if_init_conf *conf);
179 static int ath5k_config(struct ieee80211_hw *hw,
180 struct ieee80211_conf *conf);
181 static int ath5k_config_interface(struct ieee80211_hw *hw,
182 struct ieee80211_vif *vif,
183 struct ieee80211_if_conf *conf);
184 static void ath5k_configure_filter(struct ieee80211_hw *hw,
185 unsigned int changed_flags,
186 unsigned int *new_flags,
187 int mc_count, struct dev_mc_list *mclist);
188 static int ath5k_set_key(struct ieee80211_hw *hw,
189 enum set_key_cmd cmd,
190 const u8 *local_addr, const u8 *addr,
191 struct ieee80211_key_conf *key);
192 static int ath5k_get_stats(struct ieee80211_hw *hw,
193 struct ieee80211_low_level_stats *stats);
194 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
195 struct ieee80211_tx_queue_stats *stats);
196 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198 static int ath5k_beacon_update(struct ieee80211_hw *hw,
200 struct ieee80211_tx_control *ctl);
202 static struct ieee80211_ops ath5k_hw_ops = {
204 .start = ath5k_start,
206 .add_interface = ath5k_add_interface,
207 .remove_interface = ath5k_remove_interface,
208 .config = ath5k_config,
209 .config_interface = ath5k_config_interface,
210 .configure_filter = ath5k_configure_filter,
211 .set_key = ath5k_set_key,
212 .get_stats = ath5k_get_stats,
214 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
221 * Prototypes - Internal functions
224 static int ath5k_attach(struct pci_dev *pdev,
225 struct ieee80211_hw *hw);
226 static void ath5k_detach(struct pci_dev *pdev,
227 struct ieee80211_hw *hw);
228 /* Channel/mode setup */
229 static inline short ath5k_ieee2mhz(short chan);
230 static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
231 const struct ath5k_rate_table *rt,
233 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
234 struct ieee80211_channel *channels,
237 static int ath5k_getchannels(struct ieee80211_hw *hw);
238 static int ath5k_chan_set(struct ath5k_softc *sc,
239 struct ieee80211_channel *chan);
240 static void ath5k_setcurmode(struct ath5k_softc *sc,
242 static void ath5k_mode_setup(struct ath5k_softc *sc);
243 static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
245 /* Descriptor setup */
246 static int ath5k_desc_alloc(struct ath5k_softc *sc,
247 struct pci_dev *pdev);
248 static void ath5k_desc_free(struct ath5k_softc *sc,
249 struct pci_dev *pdev);
251 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf);
253 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
254 struct ath5k_buf *bf,
255 struct ieee80211_tx_control *ctl);
257 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
258 struct ath5k_buf *bf)
263 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
265 dev_kfree_skb(bf->skb);
270 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
271 int qtype, int subtype);
272 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
273 static int ath5k_beaconq_config(struct ath5k_softc *sc);
274 static void ath5k_txq_drainq(struct ath5k_softc *sc,
275 struct ath5k_txq *txq);
276 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
277 static void ath5k_txq_release(struct ath5k_softc *sc);
279 static int ath5k_rx_start(struct ath5k_softc *sc);
280 static void ath5k_rx_stop(struct ath5k_softc *sc);
281 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
282 struct ath5k_desc *ds,
283 struct sk_buff *skb);
284 static void ath5k_tasklet_rx(unsigned long data);
286 static void ath5k_tx_processq(struct ath5k_softc *sc,
287 struct ath5k_txq *txq);
288 static void ath5k_tasklet_tx(unsigned long data);
289 /* Beacon handling */
290 static int ath5k_beacon_setup(struct ath5k_softc *sc,
291 struct ath5k_buf *bf,
292 struct ieee80211_tx_control *ctl);
293 static void ath5k_beacon_send(struct ath5k_softc *sc);
294 static void ath5k_beacon_config(struct ath5k_softc *sc);
295 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
297 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
299 u64 tsf = ath5k_hw_get_tsf64(ah);
301 if ((tsf & 0x7fff) < rstamp)
304 return (tsf & ~0x7fff) | rstamp;
307 /* Interrupt handling */
308 static int ath5k_init(struct ath5k_softc *sc);
309 static int ath5k_stop_locked(struct ath5k_softc *sc);
310 static int ath5k_stop_hw(struct ath5k_softc *sc);
311 static irqreturn_t ath5k_intr(int irq, void *dev_id);
312 static void ath5k_tasklet_reset(unsigned long data);
314 static void ath5k_calibrate(unsigned long data);
316 static void ath5k_led_off(unsigned long data);
317 static void ath5k_led_blink(struct ath5k_softc *sc,
320 static void ath5k_led_event(struct ath5k_softc *sc,
325 * Module init/exit functions
334 ret = pci_register_driver(&ath5k_pci_driver);
336 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
346 pci_unregister_driver(&ath5k_pci_driver);
348 ath5k_debug_finish();
351 module_init(init_ath5k_pci);
352 module_exit(exit_ath5k_pci);
355 /********************\
356 * PCI Initialization *
357 \********************/
360 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
362 const char *name = "xxxxx";
365 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
366 if (srev_names[i].sr_type != type)
368 if ((val & 0xff) < srev_names[i + 1].sr_val) {
369 name = srev_names[i].sr_name;
378 ath5k_pci_probe(struct pci_dev *pdev,
379 const struct pci_device_id *id)
382 struct ath5k_softc *sc;
383 struct ieee80211_hw *hw;
387 ret = pci_enable_device(pdev);
389 dev_err(&pdev->dev, "can't enable device\n");
393 /* XXX 32-bit addressing only */
394 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
396 dev_err(&pdev->dev, "32-bit DMA not available\n");
401 * Cache line size is used to size and align various
402 * structures used to communicate with the hardware.
404 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
407 * Linux 2.4.18 (at least) writes the cache line size
408 * register as a 16-bit wide register which is wrong.
409 * We must have this setup properly for rx buffer
410 * DMA to work so force a reasonable value here if it
413 csz = L1_CACHE_BYTES / sizeof(u32);
414 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
417 * The default setting of latency timer yields poor results,
418 * set it to the value used by other systems. It may be worth
419 * tweaking this setting more.
421 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
423 /* Enable bus mastering */
424 pci_set_master(pdev);
427 * Disable the RETRY_TIMEOUT register (0x41) to keep
428 * PCI Tx retries from interfering with C3 CPU state.
430 pci_write_config_byte(pdev, 0x41, 0);
432 ret = pci_request_region(pdev, 0, "ath5k");
434 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
438 mem = pci_iomap(pdev, 0, 0);
440 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
446 * Allocate hw (mac80211 main struct)
447 * and hw->priv (driver private data)
449 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
451 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
456 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
458 /* Initialize driver private data */
459 SET_IEEE80211_DEV(hw, &pdev->dev);
460 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
461 hw->extra_tx_headroom = 2;
462 hw->channel_change_time = 5000;
463 /* these names are misleading */
464 hw->max_rssi = -110; /* signal in dBm */
465 hw->max_noise = -110; /* noise in dBm */
466 hw->max_signal = 100; /* we will provide a percentage based on rssi */
471 ath5k_debug_init_device(sc);
474 * Mark the device as detached to avoid processing
475 * interrupts until setup is complete.
477 __set_bit(ATH_STAT_INVALID, sc->status);
479 sc->iobase = mem; /* So we can unmap it on detach */
480 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
481 sc->opmode = IEEE80211_IF_TYPE_STA;
482 mutex_init(&sc->lock);
483 spin_lock_init(&sc->rxbuflock);
484 spin_lock_init(&sc->txbuflock);
486 /* Set private data */
487 pci_set_drvdata(pdev, hw);
489 /* Enable msi for devices that support it */
490 pci_enable_msi(pdev);
492 /* Setup interrupt handler */
493 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
495 ATH5K_ERR(sc, "request_irq failed\n");
499 /* Initialize device */
500 sc->ah = ath5k_hw_attach(sc, id->driver_data);
501 if (IS_ERR(sc->ah)) {
502 ret = PTR_ERR(sc->ah);
506 /* Finish private driver data initialization */
507 ret = ath5k_attach(pdev, hw);
511 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
512 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
514 sc->ah->ah_phy_revision);
516 if (!sc->ah->ah_single_chip) {
517 /* Single chip radio (!RF5111) */
518 if (sc->ah->ah_radio_5ghz_revision &&
519 !sc->ah->ah_radio_2ghz_revision) {
520 /* No 5GHz support -> report 2GHz radio */
521 if (!test_bit(AR5K_MODE_11A,
522 sc->ah->ah_capabilities.cap_mode)) {
523 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
524 ath5k_chip_name(AR5K_VERSION_RAD,
525 sc->ah->ah_radio_5ghz_revision),
526 sc->ah->ah_radio_5ghz_revision);
527 /* No 2GHz support (5110 and some
528 * 5Ghz only cards) -> report 5Ghz radio */
529 } else if (!test_bit(AR5K_MODE_11B,
530 sc->ah->ah_capabilities.cap_mode)) {
531 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
532 ath5k_chip_name(AR5K_VERSION_RAD,
533 sc->ah->ah_radio_5ghz_revision),
534 sc->ah->ah_radio_5ghz_revision);
535 /* Multiband radio */
537 ATH5K_INFO(sc, "RF%s multiband radio found"
539 ath5k_chip_name(AR5K_VERSION_RAD,
540 sc->ah->ah_radio_5ghz_revision),
541 sc->ah->ah_radio_5ghz_revision);
544 /* Multi chip radio (RF5111 - RF2111) ->
545 * report both 2GHz/5GHz radios */
546 else if (sc->ah->ah_radio_5ghz_revision &&
547 sc->ah->ah_radio_2ghz_revision){
548 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
549 ath5k_chip_name(AR5K_VERSION_RAD,
550 sc->ah->ah_radio_5ghz_revision),
551 sc->ah->ah_radio_5ghz_revision);
552 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
553 ath5k_chip_name(AR5K_VERSION_RAD,
554 sc->ah->ah_radio_2ghz_revision),
555 sc->ah->ah_radio_2ghz_revision);
560 /* ready to process interrupts */
561 __clear_bit(ATH_STAT_INVALID, sc->status);
565 ath5k_hw_detach(sc->ah);
567 free_irq(pdev->irq, sc);
569 pci_disable_msi(pdev);
570 ieee80211_free_hw(hw);
572 pci_iounmap(pdev, mem);
574 pci_release_region(pdev, 0);
576 pci_disable_device(pdev);
581 static void __devexit
582 ath5k_pci_remove(struct pci_dev *pdev)
584 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
585 struct ath5k_softc *sc = hw->priv;
587 ath5k_debug_finish_device(sc);
588 ath5k_detach(pdev, hw);
589 ath5k_hw_detach(sc->ah);
590 free_irq(pdev->irq, sc);
591 pci_disable_msi(pdev);
592 pci_iounmap(pdev, sc->iobase);
593 pci_release_region(pdev, 0);
594 pci_disable_device(pdev);
595 ieee80211_free_hw(hw);
600 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
602 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
603 struct ath5k_softc *sc = hw->priv;
605 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
606 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
609 pci_save_state(pdev);
610 pci_disable_device(pdev);
611 pci_set_power_state(pdev, PCI_D3hot);
617 ath5k_pci_resume(struct pci_dev *pdev)
619 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
620 struct ath5k_softc *sc = hw->priv;
621 struct ath5k_hw *ah = sc->ah;
624 err = pci_set_power_state(pdev, PCI_D0);
628 err = pci_enable_device(pdev);
632 pci_restore_state(pdev);
634 * Suspend/Resume resets the PCI configuration space, so we have to
635 * re-disable the RETRY_TIMEOUT register (0x41) to keep
636 * PCI Tx retries from interfering with C3 CPU state
638 pci_write_config_byte(pdev, 0x41, 0);
641 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
642 ath5k_hw_set_gpio_output(ah, sc->led_pin);
643 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
647 * Reset the key cache since some parts do not
648 * reset the contents on initial power up or resume.
650 * FIXME: This may need to be revisited when mac80211 becomes
651 * aware of suspend/resume.
653 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
654 ath5k_hw_reset_key(ah, i);
658 #endif /* CONFIG_PM */
662 /***********************\
663 * Driver Initialization *
664 \***********************/
667 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
669 struct ath5k_softc *sc = hw->priv;
670 struct ath5k_hw *ah = sc->ah;
675 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
678 * Check if the MAC has multi-rate retry support.
679 * We do this by trying to setup a fake extended
680 * descriptor. MAC's that don't have support will
681 * return false w/o doing anything. MAC's that do
682 * support it will return true w/o doing anything.
684 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
688 __set_bit(ATH_STAT_MRRETRY, sc->status);
691 * Reset the key cache since some parts do not
692 * reset the contents on initial power up.
694 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
695 ath5k_hw_reset_key(ah, i);
698 * Collect the channel list. The 802.11 layer
699 * is resposible for filtering this list based
700 * on settings like the phy mode and regulatory
701 * domain restrictions.
703 ret = ath5k_getchannels(hw);
705 ATH5K_ERR(sc, "can't get channels\n");
709 /* Set *_rates so we can map hw rate index */
710 ath5k_set_total_hw_rates(sc);
712 /* NB: setup here so ath5k_rate_update is happy */
713 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
714 ath5k_setcurmode(sc, AR5K_MODE_11A);
716 ath5k_setcurmode(sc, AR5K_MODE_11B);
719 * Allocate tx+rx descriptors and populate the lists.
721 ret = ath5k_desc_alloc(sc, pdev);
723 ATH5K_ERR(sc, "can't allocate descriptors\n");
728 * Allocate hardware transmit queues: one queue for
729 * beacon frames and one data queue for each QoS
730 * priority. Note that hw functions handle reseting
731 * these queues at the needed time.
733 ret = ath5k_beaconq_setup(ah);
735 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
740 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
741 if (IS_ERR(sc->txq)) {
742 ATH5K_ERR(sc, "can't setup xmit queue\n");
743 ret = PTR_ERR(sc->txq);
747 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
748 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
749 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
750 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
751 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
753 sc->led_on = 0; /* low true */
755 * Auto-enable soft led processing for IBM cards and for
756 * 5211 minipci cards.
758 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
759 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
760 __set_bit(ATH_STAT_LEDSOFT, sc->status);
763 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
764 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
765 __set_bit(ATH_STAT_LEDSOFT, sc->status);
768 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
769 ath5k_hw_set_gpio_output(ah, sc->led_pin);
770 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
773 ath5k_hw_get_lladdr(ah, mac);
774 SET_IEEE80211_PERM_ADDR(hw, mac);
775 /* All MAC address bits matter for ACKs */
776 memset(sc->bssidmask, 0xff, ETH_ALEN);
777 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
779 ret = ieee80211_register_hw(hw);
781 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
787 ath5k_txq_release(sc);
789 ath5k_hw_release_tx_queue(ah, sc->bhalq);
791 ath5k_desc_free(sc, pdev);
797 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
799 struct ath5k_softc *sc = hw->priv;
802 * NB: the order of these is important:
803 * o call the 802.11 layer before detaching ath5k_hw to
804 * insure callbacks into the driver to delete global
805 * key cache entries can be handled
806 * o reclaim the tx queue data structures after calling
807 * the 802.11 layer as we'll get called back to reclaim
808 * node state and potentially want to use them
809 * o to cleanup the tx queues the hal is called, so detach
811 * XXX: ??? detach ath5k_hw ???
812 * Other than that, it's straightforward...
814 ieee80211_unregister_hw(hw);
815 ath5k_desc_free(sc, pdev);
816 ath5k_txq_release(sc);
817 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
820 * NB: can't reclaim these until after ieee80211_ifdetach
821 * returns because we'll get called back to reclaim node
822 * state and potentially want to use them.
829 /********************\
830 * Channel/mode setup *
831 \********************/
834 * Convert IEEE channel number to MHz frequency.
837 ath5k_ieee2mhz(short chan)
839 if (chan <= 14 || chan >= 27)
840 return ieee80211chan2mhz(chan);
842 return 2212 + chan * 20;
846 ath5k_copy_rates(struct ieee80211_rate *rates,
847 const struct ath5k_rate_table *rt,
850 unsigned int i, count;
855 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
856 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
857 rates[count].hw_value = rt->rates[i].rate_code;
858 rates[count].flags = rt->rates[i].modulation;
867 ath5k_copy_channels(struct ath5k_hw *ah,
868 struct ieee80211_channel *channels,
872 unsigned int i, count, size, chfreq, freq, ch;
874 if (!test_bit(mode, ah->ah_modes))
879 case AR5K_MODE_11A_TURBO:
880 /* 1..220, but 2GHz frequencies are filtered by check_channel */
882 chfreq = CHANNEL_5GHZ;
886 case AR5K_MODE_11G_TURBO:
888 chfreq = CHANNEL_2GHZ;
891 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
895 for (i = 0, count = 0; i < size && max > 0; i++) {
897 freq = ath5k_ieee2mhz(ch);
899 /* Check if channel is supported by the chipset */
900 if (!ath5k_channel_ok(ah, freq, chfreq))
903 /* Write channel info and increment counter */
904 channels[count].center_freq = freq;
908 channels[count].hw_value = chfreq | CHANNEL_OFDM;
910 case AR5K_MODE_11A_TURBO:
911 case AR5K_MODE_11G_TURBO:
912 channels[count].hw_value = chfreq |
913 CHANNEL_OFDM | CHANNEL_TURBO;
916 channels[count].hw_value = CHANNEL_B;
927 ath5k_getchannels(struct ieee80211_hw *hw)
929 struct ath5k_softc *sc = hw->priv;
930 struct ath5k_hw *ah = sc->ah;
931 struct ieee80211_supported_band *sbands = sc->sbands;
932 const struct ath5k_rate_table *hw_rates;
933 unsigned int max_r, max_c, count_r, count_c;
934 int mode2g = AR5K_MODE_11G;
936 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
938 max_r = ARRAY_SIZE(sc->rates);
939 max_c = ARRAY_SIZE(sc->channels);
940 count_r = count_c = 0;
943 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
944 mode2g = AR5K_MODE_11B;
945 if (!test_bit(AR5K_MODE_11B,
946 sc->ah->ah_capabilities.cap_mode))
951 struct ieee80211_supported_band *sband =
952 &sbands[IEEE80211_BAND_2GHZ];
954 sband->bitrates = sc->rates;
955 sband->channels = sc->channels;
957 sband->band = IEEE80211_BAND_2GHZ;
958 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
961 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
962 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
965 count_c = sband->n_channels;
966 count_r = sband->n_bitrates;
968 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
977 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
978 struct ieee80211_supported_band *sband =
979 &sbands[IEEE80211_BAND_5GHZ];
981 sband->bitrates = &sc->rates[count_r];
982 sband->channels = &sc->channels[count_c];
984 sband->band = IEEE80211_BAND_5GHZ;
985 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
986 AR5K_MODE_11A, max_c);
988 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
989 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
992 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
995 /* FIXME: ath5k_debug_dump_modes(sc, modes); */
1001 * Set/change channels. If the channel is really being changed,
1002 * it's done by reseting the chip. To accomplish this we must
1003 * first cleanup any pending DMA, then restart stuff after a la
1007 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1009 struct ath5k_hw *ah = sc->ah;
1012 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1013 sc->curchan->center_freq, chan->center_freq);
1015 if (chan->center_freq != sc->curchan->center_freq ||
1016 chan->hw_value != sc->curchan->hw_value) {
1019 sc->curband = &sc->sbands[chan->band];
1022 * To switch channels clear any pending DMA operations;
1023 * wait long enough for the RX fifo to drain, reset the
1024 * hardware at the new frequency, and then re-enable
1025 * the relevant bits of the h/w.
1027 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1028 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1029 ath5k_rx_stop(sc); /* turn off frame recv */
1030 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
1032 ATH5K_ERR(sc, "%s: unable to reset channel "
1033 "(%u Mhz)\n", __func__, chan->center_freq);
1037 ath5k_hw_set_txpower_limit(sc->ah, 0);
1040 * Re-enable rx framework.
1042 ret = ath5k_rx_start(sc);
1044 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1050 * Change channels and update the h/w rate map
1051 * if we're switching; e.g. 11a to 11b/g.
1055 /* ath5k_chan_change(sc, chan); */
1057 ath5k_beacon_config(sc);
1059 * Re-enable interrupts.
1061 ath5k_hw_set_intr(ah, sc->imask);
1068 * TODO: CLEAN THIS !!!
1071 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1073 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1074 /* from Atheros NDIS driver, w/ permission */
1075 static const struct {
1076 u16 rate; /* tx/rx 802.11 rate */
1077 u16 timeOn; /* LED on time (ms) */
1078 u16 timeOff; /* LED off time (ms) */
1095 const struct ath5k_rate_table *rt =
1096 ath5k_hw_get_rate_table(sc->ah, mode);
1101 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1102 for (i = 0; i < 32; i++) {
1103 u8 ix = rt->rate_code_to_index[i];
1105 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1106 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1109 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1110 /* receive frames include FCS */
1111 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1112 IEEE80211_RADIOTAP_F_FCS;
1113 /* setup blink rate table to avoid per-packet lookup */
1114 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1115 if (blinkrates[j].rate == /* XXX why 7f? */
1116 (rt->rates[ix].dot11_rate&0x7f))
1119 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1121 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1128 if (mode == AR5K_MODE_11A) {
1129 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1131 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1136 ath5k_mode_setup(struct ath5k_softc *sc)
1138 struct ath5k_hw *ah = sc->ah;
1141 /* configure rx filter */
1142 rfilt = sc->filter_flags;
1143 ath5k_hw_set_rx_filter(ah, rfilt);
1145 if (ath5k_hw_hasbssidmask(ah))
1146 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1148 /* configure operational mode */
1149 ath5k_hw_set_opmode(ah);
1151 ath5k_hw_set_mcast_filter(ah, 0, 0);
1152 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1156 * Match the hw provided rate index (through descriptors)
1157 * to an index for sc->curband->bitrates, so it can be used
1160 * This one is a little bit tricky but i think i'm right
1163 * We have 4 rate tables in the following order:
1167 * 802.11g (12 rates)
1168 * that make the hw rate table.
1170 * Lets take a 5211 for example that supports a and b modes only.
1171 * First comes the 802.11a table and then 802.11b (total 12 rates).
1172 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1173 * if it returns 2 it points to the second 802.11a rate etc.
1175 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1176 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1177 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1180 ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
1182 struct ath5k_hw *ah = sc->ah;
1184 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
1187 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
1190 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
1193 /* XXX: Need to see what what happens when
1194 xr disable bits in eeprom are set */
1195 if (ah->ah_version >= AR5K_AR5212)
1201 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
1205 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
1206 /* We setup a g ratetable for both b/g modes */
1208 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
1210 mac80211_rix = hw_rix - sc->xr_rates;
1213 /* Something went wrong, fallback to basic rate for this band */
1214 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1215 (mac80211_rix <= 0 ))
1218 return mac80211_rix;
1229 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1231 struct ath5k_hw *ah = sc->ah;
1232 struct sk_buff *skb = bf->skb;
1233 struct ath5k_desc *ds;
1235 if (likely(skb == NULL)) {
1239 * Allocate buffer with headroom_needed space for the
1240 * fake physical layer header at the start.
1242 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1243 if (unlikely(skb == NULL)) {
1244 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1245 sc->rxbufsize + sc->cachelsz - 1);
1249 * Cache-line-align. This is important (for the
1250 * 5210 at least) as not doing so causes bogus data
1253 off = ((unsigned long)skb->data) % sc->cachelsz;
1255 skb_reserve(skb, sc->cachelsz - off);
1258 bf->skbaddr = pci_map_single(sc->pdev,
1259 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1260 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1261 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1269 * Setup descriptors. For receive we always terminate
1270 * the descriptor list with a self-linked entry so we'll
1271 * not get overrun under high load (as can happen with a
1272 * 5212 when ANI processing enables PHY error frames).
1274 * To insure the last descriptor is self-linked we create
1275 * each descriptor as self-linked and add it to the end. As
1276 * each additional descriptor is added the previous self-linked
1277 * entry is ``fixed'' naturally. This should be safe even
1278 * if DMA is happening. When processing RX interrupts we
1279 * never remove/process the last, self-linked, entry on the
1280 * descriptor list. This insures the hardware always has
1281 * someplace to write a new frame.
1284 ds->ds_link = bf->daddr; /* link to self */
1285 ds->ds_data = bf->skbaddr;
1286 ath5k_hw_setup_rx_desc(ah, ds,
1287 skb_tailroom(skb), /* buffer size */
1290 if (sc->rxlink != NULL)
1291 *sc->rxlink = bf->daddr;
1292 sc->rxlink = &ds->ds_link;
1297 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1298 struct ieee80211_tx_control *ctl)
1300 struct ath5k_hw *ah = sc->ah;
1301 struct ath5k_txq *txq = sc->txq;
1302 struct ath5k_desc *ds = bf->desc;
1303 struct sk_buff *skb = bf->skb;
1304 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1307 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1309 /* XXX endianness */
1310 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1313 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1314 flags |= AR5K_TXDESC_NOACK;
1318 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1319 keyidx = ctl->key_idx;
1320 pktlen += ctl->icv_len;
1323 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1324 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1325 (sc->power_level * 2), ctl->tx_rate->hw_value,
1326 ctl->retry_limit, keyidx, 0, flags, 0, 0);
1331 ds->ds_data = bf->skbaddr;
1333 spin_lock_bh(&txq->lock);
1334 list_add_tail(&bf->list, &txq->q);
1335 sc->tx_stats.data[txq->qnum].len++;
1336 if (txq->link == NULL) /* is this first packet? */
1337 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1338 else /* no, so only link it */
1339 *txq->link = bf->daddr;
1341 txq->link = &ds->ds_link;
1342 ath5k_hw_tx_start(ah, txq->qnum);
1343 spin_unlock_bh(&txq->lock);
1347 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1351 /*******************\
1352 * Descriptors setup *
1353 \*******************/
1356 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1358 struct ath5k_desc *ds;
1359 struct ath5k_buf *bf;
1364 /* allocate descriptors */
1365 sc->desc_len = sizeof(struct ath5k_desc) *
1366 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1367 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1368 if (sc->desc == NULL) {
1369 ATH5K_ERR(sc, "can't allocate descriptors\n");
1374 da = sc->desc_daddr;
1375 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1376 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1378 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1379 sizeof(struct ath5k_buf), GFP_KERNEL);
1381 ATH5K_ERR(sc, "can't allocate bufptr\n");
1387 INIT_LIST_HEAD(&sc->rxbuf);
1388 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1391 list_add_tail(&bf->list, &sc->rxbuf);
1394 INIT_LIST_HEAD(&sc->txbuf);
1395 sc->txbuf_len = ATH_TXBUF;
1396 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1397 da += sizeof(*ds)) {
1400 list_add_tail(&bf->list, &sc->txbuf);
1410 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1417 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1419 struct ath5k_buf *bf;
1421 ath5k_txbuf_free(sc, sc->bbuf);
1422 list_for_each_entry(bf, &sc->txbuf, list)
1423 ath5k_txbuf_free(sc, bf);
1424 list_for_each_entry(bf, &sc->rxbuf, list)
1425 ath5k_txbuf_free(sc, bf);
1427 /* Free memory associated with all descriptors */
1428 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1442 static struct ath5k_txq *
1443 ath5k_txq_setup(struct ath5k_softc *sc,
1444 int qtype, int subtype)
1446 struct ath5k_hw *ah = sc->ah;
1447 struct ath5k_txq *txq;
1448 struct ath5k_txq_info qi = {
1449 .tqi_subtype = subtype,
1450 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1451 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1452 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1457 * Enable interrupts only for EOL and DESC conditions.
1458 * We mark tx descriptors to receive a DESC interrupt
1459 * when a tx queue gets deep; otherwise waiting for the
1460 * EOL to reap descriptors. Note that this is done to
1461 * reduce interrupt load and this only defers reaping
1462 * descriptors, never transmitting frames. Aside from
1463 * reducing interrupts this also permits more concurrency.
1464 * The only potential downside is if the tx queue backs
1465 * up in which case the top half of the kernel may backup
1466 * due to a lack of tx descriptors.
1468 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1469 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1470 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1473 * NB: don't print a message, this happens
1474 * normally on parts with too few tx queues
1476 return ERR_PTR(qnum);
1478 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1479 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1480 qnum, ARRAY_SIZE(sc->txqs));
1481 ath5k_hw_release_tx_queue(ah, qnum);
1482 return ERR_PTR(-EINVAL);
1484 txq = &sc->txqs[qnum];
1488 INIT_LIST_HEAD(&txq->q);
1489 spin_lock_init(&txq->lock);
1492 return &sc->txqs[qnum];
1496 ath5k_beaconq_setup(struct ath5k_hw *ah)
1498 struct ath5k_txq_info qi = {
1499 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1500 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1501 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1502 /* NB: for dynamic turbo, don't enable any other interrupts */
1503 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1506 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1510 ath5k_beaconq_config(struct ath5k_softc *sc)
1512 struct ath5k_hw *ah = sc->ah;
1513 struct ath5k_txq_info qi;
1516 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1519 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
1521 * Always burst out beacon and CAB traffic
1522 * (aifs = cwmin = cwmax = 0)
1527 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1529 * Adhoc mode; backoff between 0 and (2 * cw_min).
1533 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1536 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1537 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1538 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1540 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1542 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1543 "hardware queue!\n", __func__);
1547 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1551 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1553 struct ath5k_buf *bf, *bf0;
1556 * NB: this assumes output has been stopped and
1557 * we do not need to block ath5k_tx_tasklet
1559 spin_lock_bh(&txq->lock);
1560 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1561 ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah,
1564 ath5k_txbuf_free(sc, bf);
1566 spin_lock_bh(&sc->txbuflock);
1567 sc->tx_stats.data[txq->qnum].len--;
1568 list_move_tail(&bf->list, &sc->txbuf);
1570 spin_unlock_bh(&sc->txbuflock);
1573 spin_unlock_bh(&txq->lock);
1577 * Drain the transmit queues and reclaim resources.
1580 ath5k_txq_cleanup(struct ath5k_softc *sc)
1582 struct ath5k_hw *ah = sc->ah;
1585 /* XXX return value */
1586 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1587 /* don't touch the hardware if marked invalid */
1588 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1589 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1590 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1591 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1592 if (sc->txqs[i].setup) {
1593 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1594 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1597 ath5k_hw_get_tx_buf(ah,
1602 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1604 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1605 if (sc->txqs[i].setup)
1606 ath5k_txq_drainq(sc, &sc->txqs[i]);
1610 ath5k_txq_release(struct ath5k_softc *sc)
1612 struct ath5k_txq *txq = sc->txqs;
1615 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1617 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1630 * Enable the receive h/w following a reset.
1633 ath5k_rx_start(struct ath5k_softc *sc)
1635 struct ath5k_hw *ah = sc->ah;
1636 struct ath5k_buf *bf;
1639 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1641 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1642 sc->cachelsz, sc->rxbufsize);
1646 spin_lock_bh(&sc->rxbuflock);
1647 list_for_each_entry(bf, &sc->rxbuf, list) {
1648 ret = ath5k_rxbuf_setup(sc, bf);
1650 spin_unlock_bh(&sc->rxbuflock);
1654 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1655 spin_unlock_bh(&sc->rxbuflock);
1657 ath5k_hw_put_rx_buf(ah, bf->daddr);
1658 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1659 ath5k_mode_setup(sc); /* set filters, etc. */
1660 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1668 * Disable the receive h/w in preparation for a reset.
1671 ath5k_rx_stop(struct ath5k_softc *sc)
1673 struct ath5k_hw *ah = sc->ah;
1675 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1676 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1677 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1678 mdelay(3); /* 3ms is long enough for 1 frame */
1680 ath5k_debug_printrxbuffs(sc, ah);
1682 sc->rxlink = NULL; /* just in case */
1686 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1687 struct sk_buff *skb)
1689 struct ieee80211_hdr *hdr = (void *)skb->data;
1690 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1692 if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1693 ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID)
1694 return RX_FLAG_DECRYPTED;
1696 /* Apparently when a default key is used to decrypt the packet
1697 the hw does not set the index used to decrypt. In such cases
1698 get the index from the packet. */
1699 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1700 !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1701 skb->len >= hlen + 4) {
1702 keyix = skb->data[hlen + 3] >> 6;
1704 if (test_bit(keyix, sc->keymap))
1705 return RX_FLAG_DECRYPTED;
1713 ath5k_check_ibss_hw_merge(struct ath5k_softc *sc, struct sk_buff *skb)
1716 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1718 if ((mgmt->frame_control & IEEE80211_FCTL_FTYPE) ==
1719 IEEE80211_FTYPE_MGMT &&
1720 (mgmt->frame_control & IEEE80211_FCTL_STYPE) ==
1721 IEEE80211_STYPE_BEACON &&
1722 mgmt->u.beacon.capab_info & WLAN_CAPABILITY_IBSS &&
1723 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1725 * Received an IBSS beacon with the same BSSID. Hardware might
1726 * have updated the TSF, check if we need to update timers.
1728 hw_tu = TSF_TO_TU(ath5k_hw_get_tsf64(sc->ah));
1729 if (hw_tu >= sc->nexttbtt) {
1730 ath5k_beacon_update_timers(sc,
1731 mgmt->u.beacon.timestamp);
1732 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1733 "detected HW merge from received beacon\n");
1740 ath5k_tasklet_rx(unsigned long data)
1742 struct ieee80211_rx_status rxs = {};
1743 struct sk_buff *skb;
1744 struct ath5k_softc *sc = (void *)data;
1745 struct ath5k_buf *bf;
1746 struct ath5k_desc *ds;
1753 spin_lock(&sc->rxbuflock);
1755 if (unlikely(list_empty(&sc->rxbuf))) {
1756 ATH5K_WARN(sc, "empty rx buf pool\n");
1759 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1760 BUG_ON(bf->skb == NULL);
1764 /* TODO only one segment */
1765 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1766 sc->desc_len, PCI_DMA_FROMDEVICE);
1768 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1771 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds);
1772 if (unlikely(ret == -EINPROGRESS))
1774 else if (unlikely(ret)) {
1775 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1776 spin_unlock(&sc->rxbuflock);
1780 if (unlikely(ds->ds_rxstat.rs_more)) {
1781 ATH5K_WARN(sc, "unsupported jumbo\n");
1785 stat = ds->ds_rxstat.rs_status;
1786 if (unlikely(stat)) {
1787 if (stat & AR5K_RXERR_PHY)
1789 if (stat & AR5K_RXERR_DECRYPT) {
1791 * Decrypt error. If the error occurred
1792 * because there was no hardware key, then
1793 * let the frame through so the upper layers
1794 * can process it. This is necessary for 5210
1795 * parts which have no way to setup a ``clear''
1798 * XXX do key cache faulting
1800 if (ds->ds_rxstat.rs_keyix ==
1801 AR5K_RXKEYIX_INVALID &&
1802 !(stat & AR5K_RXERR_CRC))
1805 if (stat & AR5K_RXERR_MIC) {
1806 rxs.flag |= RX_FLAG_MMIC_ERROR;
1810 /* let crypto-error packets fall through in MNTR */
1811 if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1812 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1816 len = ds->ds_rxstat.rs_datalen;
1817 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len,
1818 PCI_DMA_FROMDEVICE);
1819 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1820 PCI_DMA_FROMDEVICE);
1826 * the hardware adds a padding to 4 byte boundaries between
1827 * the header and the payload data if the header length is
1828 * not multiples of 4 - remove it
1830 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1833 memmove(skb->data + pad, skb->data, hdrlen);
1838 * always extend the mac timestamp, since this information is
1839 * also needed for proper IBSS merging.
1841 * XXX: it might be too late to do it here, since rs_tstamp is
1842 * 15bit only. that means TSF extension has to be done within
1843 * 32768usec (about 32ms). it might be necessary to move this to
1844 * the interrupt handler, like it is done in madwifi.
1846 rxs.mactime = ath5k_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp);
1847 rxs.flag |= RX_FLAG_TSFT;
1849 rxs.freq = sc->curchan->center_freq;
1850 rxs.band = sc->curband->band;
1854 * the names here are misleading and the usage of these
1855 * values by iwconfig makes it even worse
1857 /* noise floor in dBm, from the last noise calibration */
1858 rxs.noise = sc->ah->ah_noise_floor;
1859 /* signal level in dBm */
1860 rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi;
1862 * "signal" is actually displayed as Link Quality by iwconfig
1863 * we provide a percentage based on rssi (assuming max rssi 64)
1865 rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64;
1867 rxs.antenna = ds->ds_rxstat.rs_antenna;
1868 rxs.rate_idx = ath5k_hw_to_driver_rix(sc,
1869 ds->ds_rxstat.rs_rate);
1870 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb);
1872 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1874 /* check beacons in IBSS mode */
1875 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1876 ath5k_check_ibss_hw_merge(sc, skb);
1878 __ieee80211_rx(sc->hw, skb, &rxs);
1879 sc->led_rxrate = ds->ds_rxstat.rs_rate;
1880 ath5k_led_event(sc, ATH_LED_RX);
1882 list_move_tail(&bf->list, &sc->rxbuf);
1883 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1884 spin_unlock(&sc->rxbuflock);
1895 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1897 struct ieee80211_tx_status txs = {};
1898 struct ath5k_buf *bf, *bf0;
1899 struct ath5k_desc *ds;
1900 struct sk_buff *skb;
1903 spin_lock(&txq->lock);
1904 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1907 /* TODO only one segment */
1908 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1909 sc->desc_len, PCI_DMA_FROMDEVICE);
1910 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds);
1911 if (unlikely(ret == -EINPROGRESS))
1913 else if (unlikely(ret)) {
1914 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1921 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1924 txs.control = bf->ctl;
1925 txs.retry_count = ds->ds_txstat.ts_shortretry +
1926 ds->ds_txstat.ts_longretry / 6;
1927 if (unlikely(ds->ds_txstat.ts_status)) {
1928 sc->ll_stats.dot11ACKFailureCount++;
1929 if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY)
1930 txs.excessive_retries = 1;
1931 else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT)
1932 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1934 txs.flags |= IEEE80211_TX_STATUS_ACK;
1935 txs.ack_signal = ds->ds_txstat.ts_rssi;
1938 ieee80211_tx_status(sc->hw, skb, &txs);
1939 sc->tx_stats.data[txq->qnum].count++;
1941 spin_lock(&sc->txbuflock);
1942 sc->tx_stats.data[txq->qnum].len--;
1943 list_move_tail(&bf->list, &sc->txbuf);
1945 spin_unlock(&sc->txbuflock);
1947 if (likely(list_empty(&txq->q)))
1949 spin_unlock(&txq->lock);
1950 if (sc->txbuf_len > ATH_TXBUF / 5)
1951 ieee80211_wake_queues(sc->hw);
1955 ath5k_tasklet_tx(unsigned long data)
1957 struct ath5k_softc *sc = (void *)data;
1959 ath5k_tx_processq(sc, sc->txq);
1961 ath5k_led_event(sc, ATH_LED_TX);
1972 * Setup the beacon frame for transmit.
1975 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1976 struct ieee80211_tx_control *ctl)
1978 struct sk_buff *skb = bf->skb;
1979 struct ath5k_hw *ah = sc->ah;
1980 struct ath5k_desc *ds;
1981 int ret, antenna = 0;
1984 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1986 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1987 "skbaddr %llx\n", skb, skb->data, skb->len,
1988 (unsigned long long)bf->skbaddr);
1989 if (pci_dma_mapping_error(bf->skbaddr)) {
1990 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1996 flags = AR5K_TXDESC_NOACK;
1997 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1998 ds->ds_link = bf->daddr; /* self-linked */
1999 flags |= AR5K_TXDESC_VEOL;
2001 * Let hardware handle antenna switching if txantenna is not set
2006 * Switch antenna every 4 beacons if txantenna is not set
2007 * XXX assumes two antennas
2010 antenna = sc->bsent & 4 ? 2 : 1;
2013 ds->ds_data = bf->skbaddr;
2014 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2015 ieee80211_get_hdrlen_from_skb(skb),
2016 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2017 ctl->tx_rate->hw_value, 1, AR5K_TXKEYIX_INVALID,
2018 antenna, flags, 0, 0);
2024 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2029 * Transmit a beacon frame at SWBA. Dynamic updates to the
2030 * frame contents are done as needed and the slot time is
2031 * also adjusted based on current state.
2033 * this is usually called from interrupt context (ath5k_intr())
2034 * but also from ath5k_beacon_config() in IBSS mode which in turn
2035 * can be called from a tasklet and user context
2038 ath5k_beacon_send(struct ath5k_softc *sc)
2040 struct ath5k_buf *bf = sc->bbuf;
2041 struct ath5k_hw *ah = sc->ah;
2043 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2045 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
2046 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
2047 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2051 * Check if the previous beacon has gone out. If
2052 * not don't don't try to post another, skip this
2053 * period and wait for the next. Missed beacons
2054 * indicate a problem and should not occur. If we
2055 * miss too many consecutive beacons reset the device.
2057 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2059 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2060 "missed %u consecutive beacons\n", sc->bmisscount);
2061 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2062 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2063 "stuck beacon time (%u missed)\n",
2065 tasklet_schedule(&sc->restq);
2069 if (unlikely(sc->bmisscount != 0)) {
2070 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2071 "resume beacon xmit after %u misses\n",
2077 * Stop any current dma and put the new frame on the queue.
2078 * This should never fail since we check above that no frames
2079 * are still pending on the queue.
2081 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2082 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2083 /* NB: hw still stops DMA, so proceed */
2085 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2088 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2089 ath5k_hw_tx_start(ah, sc->bhalq);
2090 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2091 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2098 * ath5k_beacon_update_timers - update beacon timers
2100 * @sc: struct ath5k_softc pointer we are operating on
2101 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2102 * beacon timer update based on the current HW TSF.
2104 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2105 * of a received beacon or the current local hardware TSF and write it to the
2106 * beacon timer registers.
2108 * This is called in a variety of situations, e.g. when a beacon is received,
2109 * when a HW merge has been detected, but also when an new IBSS is created or
2110 * when we otherwise know we have to update the timers, but we keep it in this
2111 * function to have it all together in one place.
2114 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2116 struct ath5k_hw *ah = sc->ah;
2117 u32 nexttbtt, intval, hw_tu, bc_tu;
2120 intval = sc->bintval & AR5K_BEACON_PERIOD;
2121 if (WARN_ON(!intval))
2124 /* beacon TSF converted to TU */
2125 bc_tu = TSF_TO_TU(bc_tsf);
2127 /* current TSF converted to TU */
2128 hw_tsf = ath5k_hw_get_tsf64(ah);
2129 hw_tu = TSF_TO_TU(hw_tsf);
2132 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2135 * no beacons received, called internally.
2136 * just need to refresh timers based on HW TSF.
2138 nexttbtt = roundup(hw_tu + FUDGE, intval);
2139 } else if (bc_tsf == 0) {
2141 * no beacon received, probably called by ath5k_reset_tsf().
2142 * reset TSF to start with 0.
2145 intval |= AR5K_BEACON_RESET_TSF;
2146 } else if (bc_tsf > hw_tsf) {
2148 * beacon received, SW merge happend but HW TSF not yet updated.
2149 * not possible to reconfigure timers yet, but next time we
2150 * receive a beacon with the same BSSID, the hardware will
2151 * automatically update the TSF and then we need to reconfigure
2154 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2155 "need to wait for HW TSF sync\n");
2159 * most important case for beacon synchronization between STA.
2161 * beacon received and HW TSF has been already updated by HW.
2162 * update next TBTT based on the TSF of the beacon, but make
2163 * sure it is ahead of our local TSF timer.
2165 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2169 sc->nexttbtt = nexttbtt;
2171 intval |= AR5K_BEACON_ENA;
2172 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2175 * debugging output last in order to preserve the time critical aspect
2179 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2180 "reconfigured timers based on HW TSF\n");
2181 else if (bc_tsf == 0)
2182 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2183 "reset HW TSF and timers\n");
2185 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2186 "updated timers based on beacon TSF\n");
2188 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2189 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2190 (unsigned long long) bc_tsf,
2191 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2192 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2193 intval & AR5K_BEACON_PERIOD,
2194 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2195 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2200 * ath5k_beacon_config - Configure the beacon queues and interrupts
2202 * @sc: struct ath5k_softc pointer we are operating on
2204 * When operating in station mode we want to receive a BMISS interrupt when we
2205 * stop seeing beacons from the AP we've associated with so we can look for
2206 * another AP to associate with.
2208 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2209 * interrupts to detect HW merges only.
2211 * AP mode is missing.
2214 ath5k_beacon_config(struct ath5k_softc *sc)
2216 struct ath5k_hw *ah = sc->ah;
2218 ath5k_hw_set_intr(ah, 0);
2221 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2222 sc->imask |= AR5K_INT_BMISS;
2223 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2225 * In IBSS mode we use a self-linked tx descriptor and let the
2226 * hardware send the beacons automatically. We have to load it
2228 * We use the SWBA interrupt only to keep track of the beacon
2229 * timers in order to detect HW merges (automatic TSF updates).
2231 ath5k_beaconq_config(sc);
2233 sc->imask |= AR5K_INT_SWBA;
2235 if (ath5k_hw_hasveol(ah))
2236 ath5k_beacon_send(sc);
2240 ath5k_hw_set_intr(ah, sc->imask);
2244 /********************\
2245 * Interrupt handling *
2246 \********************/
2249 ath5k_init(struct ath5k_softc *sc)
2253 mutex_lock(&sc->lock);
2255 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2258 * Stop anything previously setup. This is safe
2259 * no matter this is the first time through or not.
2261 ath5k_stop_locked(sc);
2264 * The basic interface to setting the hardware in a good
2265 * state is ``reset''. On return the hardware is known to
2266 * be powered up and with interrupts disabled. This must
2267 * be followed by initialization of the appropriate bits
2268 * and then setup of the interrupt mask.
2270 sc->curchan = sc->hw->conf.channel;
2271 sc->curband = &sc->sbands[sc->curchan->band];
2272 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2274 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2278 * This is needed only to setup initial state
2279 * but it's best done after a reset.
2281 ath5k_hw_set_txpower_limit(sc->ah, 0);
2284 * Setup the hardware after reset: the key cache
2285 * is filled as needed and the receive engine is
2286 * set going. Frame transmit is handled entirely
2287 * in the frame output path; there's nothing to do
2288 * here except setup the interrupt mask.
2290 ret = ath5k_rx_start(sc);
2295 * Enable interrupts.
2297 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2298 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2300 ath5k_hw_set_intr(sc->ah, sc->imask);
2301 /* Set ack to be sent at low bit-rates */
2302 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2304 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2305 msecs_to_jiffies(ath5k_calinterval * 1000)));
2309 mutex_unlock(&sc->lock);
2314 ath5k_stop_locked(struct ath5k_softc *sc)
2316 struct ath5k_hw *ah = sc->ah;
2318 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2319 test_bit(ATH_STAT_INVALID, sc->status));
2322 * Shutdown the hardware and driver:
2323 * stop output from above
2324 * disable interrupts
2326 * turn off the radio
2327 * clear transmit machinery
2328 * clear receive machinery
2329 * drain and release tx queues
2330 * reclaim beacon resources
2331 * power down hardware
2333 * Note that some of this work is not possible if the
2334 * hardware is gone (invalid).
2336 ieee80211_stop_queues(sc->hw);
2338 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2339 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2340 del_timer_sync(&sc->led_tim);
2341 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2342 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2344 ath5k_hw_set_intr(ah, 0);
2346 ath5k_txq_cleanup(sc);
2347 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2349 ath5k_hw_phy_disable(ah);
2357 * Stop the device, grabbing the top-level lock to protect
2358 * against concurrent entry through ath5k_init (which can happen
2359 * if another thread does a system call and the thread doing the
2360 * stop is preempted).
2363 ath5k_stop_hw(struct ath5k_softc *sc)
2367 mutex_lock(&sc->lock);
2368 ret = ath5k_stop_locked(sc);
2369 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2371 * Set the chip in full sleep mode. Note that we are
2372 * careful to do this only when bringing the interface
2373 * completely to a stop. When the chip is in this state
2374 * it must be carefully woken up or references to
2375 * registers in the PCI clock domain may freeze the bus
2376 * (and system). This varies by chip and is mostly an
2377 * issue with newer parts that go to sleep more quickly.
2379 if (sc->ah->ah_mac_srev >= 0x78) {
2382 * don't put newer MAC revisions > 7.8 to sleep because
2383 * of the above mentioned problems
2385 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2386 "not putting device to sleep\n");
2388 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2389 "putting device to full sleep\n");
2390 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2393 ath5k_txbuf_free(sc, sc->bbuf);
2394 mutex_unlock(&sc->lock);
2396 del_timer_sync(&sc->calib_tim);
2402 ath5k_intr(int irq, void *dev_id)
2404 struct ath5k_softc *sc = dev_id;
2405 struct ath5k_hw *ah = sc->ah;
2406 enum ath5k_int status;
2407 unsigned int counter = 1000;
2409 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2410 !ath5k_hw_is_intr_pending(ah)))
2415 * Figure out the reason(s) for the interrupt. Note
2416 * that get_isr returns a pseudo-ISR that may include
2417 * bits we haven't explicitly enabled so we mask the
2418 * value to insure we only process bits we requested.
2420 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2421 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2423 status &= sc->imask; /* discard unasked for bits */
2424 if (unlikely(status & AR5K_INT_FATAL)) {
2426 * Fatal errors are unrecoverable.
2427 * Typically these are caused by DMA errors.
2429 tasklet_schedule(&sc->restq);
2430 } else if (unlikely(status & AR5K_INT_RXORN)) {
2431 tasklet_schedule(&sc->restq);
2433 if (status & AR5K_INT_SWBA) {
2435 * Software beacon alert--time to send a beacon.
2436 * Handle beacon transmission directly; deferring
2437 * this is too slow to meet timing constraints
2440 * In IBSS mode we use this interrupt just to
2441 * keep track of the next TBTT (target beacon
2442 * transmission time) in order to detect hardware
2443 * merges (TSF updates).
2445 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2446 /* XXX: only if VEOL suppported */
2447 u64 tsf = ath5k_hw_get_tsf64(ah);
2448 sc->nexttbtt += sc->bintval;
2449 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2450 "SWBA nexttbtt: %x hw_tu: %x "
2454 (unsigned long long) tsf);
2456 ath5k_beacon_send(sc);
2459 if (status & AR5K_INT_RXEOL) {
2461 * NB: the hardware should re-read the link when
2462 * RXE bit is written, but it doesn't work at
2463 * least on older hardware revs.
2467 if (status & AR5K_INT_TXURN) {
2468 /* bump tx trigger level */
2469 ath5k_hw_update_tx_triglevel(ah, true);
2471 if (status & AR5K_INT_RX)
2472 tasklet_schedule(&sc->rxtq);
2473 if (status & AR5K_INT_TX)
2474 tasklet_schedule(&sc->txtq);
2475 if (status & AR5K_INT_BMISS) {
2477 if (status & AR5K_INT_MIB) {
2481 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2483 if (unlikely(!counter))
2484 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2490 ath5k_tasklet_reset(unsigned long data)
2492 struct ath5k_softc *sc = (void *)data;
2494 ath5k_reset(sc->hw);
2498 * Periodically recalibrate the PHY to account
2499 * for temperature/environment changes.
2502 ath5k_calibrate(unsigned long data)
2504 struct ath5k_softc *sc = (void *)data;
2505 struct ath5k_hw *ah = sc->ah;
2507 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2508 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2509 sc->curchan->hw_value);
2511 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2513 * Rfgain is out of bounds, reset the chip
2514 * to load new gain values.
2516 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2517 ath5k_reset(sc->hw);
2519 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2520 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2521 ieee80211_frequency_to_channel(
2522 sc->curchan->center_freq));
2524 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2525 msecs_to_jiffies(ath5k_calinterval * 1000)));
2535 ath5k_led_off(unsigned long data)
2537 struct ath5k_softc *sc = (void *)data;
2539 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2540 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2542 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2543 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2544 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2549 * Blink the LED according to the specified on/off times.
2552 ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2555 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2556 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2557 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2558 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2560 mod_timer(&sc->led_tim, jiffies + on);
2564 ath5k_led_event(struct ath5k_softc *sc, int event)
2566 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2568 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2569 return; /* don't interrupt active blink */
2572 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2573 sc->hwmap[sc->led_txrate].ledoff);
2576 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2577 sc->hwmap[sc->led_rxrate].ledoff);
2585 /********************\
2586 * Mac80211 functions *
2587 \********************/
2590 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2591 struct ieee80211_tx_control *ctl)
2593 struct ath5k_softc *sc = hw->priv;
2594 struct ath5k_buf *bf;
2595 unsigned long flags;
2599 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2601 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2602 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2605 * the hardware expects the header padded to 4 byte boundaries
2606 * if this is not the case we add the padding after the header
2608 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2611 if (skb_headroom(skb) < pad) {
2612 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2613 " headroom to pad %d\n", hdrlen, pad);
2617 memmove(skb->data, skb->data+pad, hdrlen);
2620 sc->led_txrate = ctl->tx_rate->hw_value;
2622 spin_lock_irqsave(&sc->txbuflock, flags);
2623 if (list_empty(&sc->txbuf)) {
2624 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2625 spin_unlock_irqrestore(&sc->txbuflock, flags);
2626 ieee80211_stop_queue(hw, ctl->queue);
2629 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2630 list_del(&bf->list);
2632 if (list_empty(&sc->txbuf))
2633 ieee80211_stop_queues(hw);
2634 spin_unlock_irqrestore(&sc->txbuflock, flags);
2638 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2640 spin_lock_irqsave(&sc->txbuflock, flags);
2641 list_add_tail(&bf->list, &sc->txbuf);
2643 spin_unlock_irqrestore(&sc->txbuflock, flags);
2644 dev_kfree_skb_any(skb);
2652 ath5k_reset(struct ieee80211_hw *hw)
2654 struct ath5k_softc *sc = hw->priv;
2655 struct ath5k_hw *ah = sc->ah;
2658 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2660 ath5k_hw_set_intr(ah, 0);
2661 ath5k_txq_cleanup(sc);
2664 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2665 if (unlikely(ret)) {
2666 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2669 ath5k_hw_set_txpower_limit(sc->ah, 0);
2671 ret = ath5k_rx_start(sc);
2672 if (unlikely(ret)) {
2673 ATH5K_ERR(sc, "can't start recv logic\n");
2677 * We may be doing a reset in response to an ioctl
2678 * that changes the channel so update any state that
2679 * might change as a result.
2683 /* ath5k_chan_change(sc, c); */
2684 ath5k_beacon_config(sc);
2685 /* intrs are started by ath5k_beacon_config */
2687 ieee80211_wake_queues(hw);
2694 static int ath5k_start(struct ieee80211_hw *hw)
2696 return ath5k_init(hw->priv);
2699 static void ath5k_stop(struct ieee80211_hw *hw)
2701 ath5k_stop_hw(hw->priv);
2704 static int ath5k_add_interface(struct ieee80211_hw *hw,
2705 struct ieee80211_if_init_conf *conf)
2707 struct ath5k_softc *sc = hw->priv;
2710 mutex_lock(&sc->lock);
2716 sc->vif = conf->vif;
2718 switch (conf->type) {
2719 case IEEE80211_IF_TYPE_STA:
2720 case IEEE80211_IF_TYPE_IBSS:
2721 case IEEE80211_IF_TYPE_MNTR:
2722 sc->opmode = conf->type;
2730 mutex_unlock(&sc->lock);
2735 ath5k_remove_interface(struct ieee80211_hw *hw,
2736 struct ieee80211_if_init_conf *conf)
2738 struct ath5k_softc *sc = hw->priv;
2740 mutex_lock(&sc->lock);
2741 if (sc->vif != conf->vif)
2746 mutex_unlock(&sc->lock);
2750 * TODO: Phy disable/diversity etc
2753 ath5k_config(struct ieee80211_hw *hw,
2754 struct ieee80211_conf *conf)
2756 struct ath5k_softc *sc = hw->priv;
2758 sc->bintval = conf->beacon_int;
2759 sc->power_level = conf->power_level;
2761 return ath5k_chan_set(sc, conf->channel);
2765 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2766 struct ieee80211_if_conf *conf)
2768 struct ath5k_softc *sc = hw->priv;
2769 struct ath5k_hw *ah = sc->ah;
2772 /* Set to a reasonable value. Note that this will
2773 * be set to mac80211's value at ath5k_config(). */
2775 mutex_lock(&sc->lock);
2776 if (sc->vif != vif) {
2781 /* Cache for later use during resets */
2782 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2783 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2784 * a clean way of letting us retrieve this yet. */
2785 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2787 mutex_unlock(&sc->lock);
2789 return ath5k_reset(hw);
2791 mutex_unlock(&sc->lock);
2795 #define SUPPORTED_FIF_FLAGS \
2796 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2797 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2798 FIF_BCN_PRBRESP_PROMISC
2800 * o always accept unicast, broadcast, and multicast traffic
2801 * o multicast traffic for all BSSIDs will be enabled if mac80211
2803 * o maintain current state of phy ofdm or phy cck error reception.
2804 * If the hardware detects any of these type of errors then
2805 * ath5k_hw_get_rx_filter() will pass to us the respective
2806 * hardware filters to be able to receive these type of frames.
2807 * o probe request frames are accepted only when operating in
2808 * hostap, adhoc, or monitor modes
2809 * o enable promiscuous mode according to the interface state
2811 * - when operating in adhoc mode so the 802.11 layer creates
2812 * node table entries for peers,
2813 * - when operating in station mode for collecting rssi data when
2814 * the station is otherwise quiet, or
2817 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2818 unsigned int changed_flags,
2819 unsigned int *new_flags,
2820 int mc_count, struct dev_mc_list *mclist)
2822 struct ath5k_softc *sc = hw->priv;
2823 struct ath5k_hw *ah = sc->ah;
2824 u32 mfilt[2], val, rfilt;
2831 /* Only deal with supported flags */
2832 changed_flags &= SUPPORTED_FIF_FLAGS;
2833 *new_flags &= SUPPORTED_FIF_FLAGS;
2835 /* If HW detects any phy or radar errors, leave those filters on.
2836 * Also, always enable Unicast, Broadcasts and Multicast
2837 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2838 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2839 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2840 AR5K_RX_FILTER_MCAST);
2842 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2843 if (*new_flags & FIF_PROMISC_IN_BSS) {
2844 rfilt |= AR5K_RX_FILTER_PROM;
2845 __set_bit(ATH_STAT_PROMISC, sc->status);
2848 __clear_bit(ATH_STAT_PROMISC, sc->status);
2851 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2852 if (*new_flags & FIF_ALLMULTI) {
2856 for (i = 0; i < mc_count; i++) {
2859 /* calculate XOR of eight 6-bit values */
2860 val = LE_READ_4(mclist->dmi_addr + 0);
2861 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2862 val = LE_READ_4(mclist->dmi_addr + 3);
2863 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2865 mfilt[pos / 32] |= (1 << (pos % 32));
2866 /* XXX: we might be able to just do this instead,
2867 * but not sure, needs testing, if we do use this we'd
2868 * neet to inform below to not reset the mcast */
2869 /* ath5k_hw_set_mcast_filterindex(ah,
2870 * mclist->dmi_addr[5]); */
2871 mclist = mclist->next;
2875 /* This is the best we can do */
2876 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2877 rfilt |= AR5K_RX_FILTER_PHYERR;
2879 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2880 * and probes for any BSSID, this needs testing */
2881 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2882 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2884 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2885 * set we should only pass on control frames for this
2886 * station. This needs testing. I believe right now this
2887 * enables *all* control frames, which is OK.. but
2888 * but we should see if we can improve on granularity */
2889 if (*new_flags & FIF_CONTROL)
2890 rfilt |= AR5K_RX_FILTER_CONTROL;
2892 /* Additional settings per mode -- this is per ath5k */
2894 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2896 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2897 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2898 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2899 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2900 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2901 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2902 test_bit(ATH_STAT_PROMISC, sc->status))
2903 rfilt |= AR5K_RX_FILTER_PROM;
2904 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2905 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2906 rfilt |= AR5K_RX_FILTER_BEACON;
2910 ath5k_hw_set_rx_filter(ah,rfilt);
2912 /* Set multicast bits */
2913 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2914 /* Set the cached hw filter flags, this will alter actually
2916 sc->filter_flags = rfilt;
2920 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2921 const u8 *local_addr, const u8 *addr,
2922 struct ieee80211_key_conf *key)
2924 struct ath5k_softc *sc = hw->priv;
2938 mutex_lock(&sc->lock);
2942 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2944 ATH5K_ERR(sc, "can't set the key\n");
2947 __set_bit(key->keyidx, sc->keymap);
2948 key->hw_key_idx = key->keyidx;
2951 ath5k_hw_reset_key(sc->ah, key->keyidx);
2952 __clear_bit(key->keyidx, sc->keymap);
2960 mutex_unlock(&sc->lock);
2965 ath5k_get_stats(struct ieee80211_hw *hw,
2966 struct ieee80211_low_level_stats *stats)
2968 struct ath5k_softc *sc = hw->priv;
2970 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2976 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2977 struct ieee80211_tx_queue_stats *stats)
2979 struct ath5k_softc *sc = hw->priv;
2981 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2987 ath5k_get_tsf(struct ieee80211_hw *hw)
2989 struct ath5k_softc *sc = hw->priv;
2991 return ath5k_hw_get_tsf64(sc->ah);
2995 ath5k_reset_tsf(struct ieee80211_hw *hw)
2997 struct ath5k_softc *sc = hw->priv;
3000 * in IBSS mode we need to update the beacon timers too.
3001 * this will also reset the TSF if we call it with 0
3003 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3004 ath5k_beacon_update_timers(sc, 0);
3006 ath5k_hw_reset_tsf(sc->ah);
3010 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
3011 struct ieee80211_tx_control *ctl)
3013 struct ath5k_softc *sc = hw->priv;
3016 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3018 mutex_lock(&sc->lock);
3020 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3025 ath5k_txbuf_free(sc, sc->bbuf);
3026 sc->bbuf->skb = skb;
3027 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
3029 sc->bbuf->skb = NULL;
3031 ath5k_beacon_config(sc);
3034 mutex_unlock(&sc->lock);