drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19 #include "btcoex.h"
  20
  21 static char *dev_info = "ath9k";
  22
  23 MODULE_AUTHOR("Atheros Communications");
  24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  26 MODULE_LICENSE("Dual BSD/GPL");
  27
  28 static int modparam_nohwcrypt;
  29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  31
  32 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  33 module_param_named(debug, ath9k_debug, uint, 0);
  34 MODULE_PARM_DESC(debug, "Debugging mask");
  35
  36 /* We use the hw_value as an index into our private channel structure */
  37
  38 #define CHAN2G(_freq, _idx)  { \
  39         .center_freq = (_freq), \
  40         .hw_value = (_idx), \
  41         .max_power = 20, \
  42 }
  43
  44 #define CHAN5G(_freq, _idx) { \
  45         .band = IEEE80211_BAND_5GHZ, \
  46         .center_freq = (_freq), \
  47         .hw_value = (_idx), \
  48         .max_power = 20, \
  49 }
  50
  51 /* Some 2 GHz radios are actually tunable on 2312-2732
  52  * on 5 MHz steps, we support the channels which we know
  53  * we have calibration data for all cards though to make
  54  * this static */
  55 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  56         CHAN2G(2412, 0), /* Channel 1 */
  57         CHAN2G(2417, 1), /* Channel 2 */
  58         CHAN2G(2422, 2), /* Channel 3 */
  59         CHAN2G(2427, 3), /* Channel 4 */
  60         CHAN2G(2432, 4), /* Channel 5 */
  61         CHAN2G(2437, 5), /* Channel 6 */
  62         CHAN2G(2442, 6), /* Channel 7 */
  63         CHAN2G(2447, 7), /* Channel 8 */
  64         CHAN2G(2452, 8), /* Channel 9 */
  65         CHAN2G(2457, 9), /* Channel 10 */
  66         CHAN2G(2462, 10), /* Channel 11 */
  67         CHAN2G(2467, 11), /* Channel 12 */
  68         CHAN2G(2472, 12), /* Channel 13 */
  69         CHAN2G(2484, 13), /* Channel 14 */
  70 };
  71
  72 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  73  * on 5 MHz steps, we support the channels which we know
  74  * we have calibration data for all cards though to make
  75  * this static */
  76 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  77         /* _We_ call this UNII 1 */
  78         CHAN5G(5180, 14), /* Channel 36 */
  79         CHAN5G(5200, 15), /* Channel 40 */
  80         CHAN5G(5220, 16), /* Channel 44 */
  81         CHAN5G(5240, 17), /* Channel 48 */
  82         /* _We_ call this UNII 2 */
  83         CHAN5G(5260, 18), /* Channel 52 */
  84         CHAN5G(5280, 19), /* Channel 56 */
  85         CHAN5G(5300, 20), /* Channel 60 */
  86         CHAN5G(5320, 21), /* Channel 64 */
  87         /* _We_ call this "Middle band" */
  88         CHAN5G(5500, 22), /* Channel 100 */
  89         CHAN5G(5520, 23), /* Channel 104 */
  90         CHAN5G(5540, 24), /* Channel 108 */
  91         CHAN5G(5560, 25), /* Channel 112 */
  92         CHAN5G(5580, 26), /* Channel 116 */
  93         CHAN5G(5600, 27), /* Channel 120 */
  94         CHAN5G(5620, 28), /* Channel 124 */
  95         CHAN5G(5640, 29), /* Channel 128 */
  96         CHAN5G(5660, 30), /* Channel 132 */
  97         CHAN5G(5680, 31), /* Channel 136 */
  98         CHAN5G(5700, 32), /* Channel 140 */
  99         /* _We_ call this UNII 3 */
 100         CHAN5G(5745, 33), /* Channel 149 */
 101         CHAN5G(5765, 34), /* Channel 153 */
 102         CHAN5G(5785, 35), /* Channel 157 */
 103         CHAN5G(5805, 36), /* Channel 161 */
 104         CHAN5G(5825, 37), /* Channel 165 */
 105 };
 106
 107 /* Atheros hardware rate code addition for short premble */
 108 #define SHPCHECK(__hw_rate, __flags) \
 109         ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
 110
 111 #define RATE(_bitrate, _hw_rate, _flags) {              \
 112         .bitrate        = (_bitrate),                   \
 113         .flags          = (_flags),                     \
 114         .hw_value       = (_hw_rate),                   \
 115         .hw_value_short = (SHPCHECK(_hw_rate, _flags))  \
 116 }
 117
 118 static struct ieee80211_rate ath9k_legacy_rates[] = {
 119         RATE(10, 0x1b, 0),
 120         RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
 121         RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
 122         RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
 123         RATE(60, 0x0b, 0),
 124         RATE(90, 0x0f, 0),
 125         RATE(120, 0x0a, 0),
 126         RATE(180, 0x0e, 0),
 127         RATE(240, 0x09, 0),
 128         RATE(360, 0x0d, 0),
 129         RATE(480, 0x08, 0),
 130         RATE(540, 0x0c, 0),
 131 };
 132
 133 static void ath_cache_conf_rate(struct ath_softc *sc,
 134                                 struct ieee80211_conf *conf)
 135 {
 136         switch (conf->channel->band) {
 137         case IEEE80211_BAND_2GHZ:
 138                 if (conf_is_ht20(conf))
 139                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
 140                 else if (conf_is_ht40_minus(conf))
 141                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
 142                 else if (conf_is_ht40_plus(conf))
 143                         sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
 144                 else
 145                         sc->cur_rate_mode = ATH9K_MODE_11G;
 146                 break;
 147         case IEEE80211_BAND_5GHZ:
 148                 if (conf_is_ht20(conf))
 149                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
 150                 else if (conf_is_ht40_minus(conf))
 151                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
 152                 else if (conf_is_ht40_plus(conf))
 153                         sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
 154                 else
 155                         sc->cur_rate_mode = ATH9K_MODE_11A;
 156                 break;
 157         default:
 158                 BUG_ON(1);
 159                 break;
 160         }
 161 }
 162
 163 static void ath_update_txpow(struct ath_softc *sc)
 164 {
 165         struct ath_hw *ah = sc->sc_ah;
 166         u32 txpow;
 167
 168         if (sc->curtxpow != sc->config.txpowlimit) {
 169                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 170                 /* read back in case value is clamped */
 171                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 172                 sc->curtxpow = txpow;
 173         }
 174 }
 175
 176 static u8 parse_mpdudensity(u8 mpdudensity)
 177 {
 178         /*
 179          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 180          *   0 for no restriction
 181          *   1 for 1/4 us
 182          *   2 for 1/2 us
 183          *   3 for 1 us
 184          *   4 for 2 us
 185          *   5 for 4 us
 186          *   6 for 8 us
 187          *   7 for 16 us
 188          */
 189         switch (mpdudensity) {
 190         case 0:
 191                 return 0;
 192         case 1:
 193         case 2:
 194         case 3:
 195                 /* Our lower layer calculations limit our precision to
 196                    1 microsecond */
 197                 return 1;
 198         case 4:
 199                 return 2;
 200         case 5:
 201                 return 4;
 202         case 6:
 203                 return 8;
 204         case 7:
 205                 return 16;
 206         default:
 207                 return 0;
 208         }
 209 }
 210
 211 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
 212                                                 struct ieee80211_hw *hw)
 213 {
 214         struct ieee80211_channel *curchan = hw->conf.channel;
 215         struct ath9k_channel *channel;
 216         u8 chan_idx;
 217
 218         chan_idx = curchan->hw_value;
 219         channel = &sc->sc_ah->channels[chan_idx];
 220         ath9k_update_ichannel(sc, hw, channel);
 221         return channel;
 222 }
 223
 224 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
 225 {
 226         unsigned long flags;
 227         bool ret;
 228
 229         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 230         ret = ath9k_hw_setpower(sc->sc_ah, mode);
 231         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 232
 233         return ret;
 234 }
 235
 236 void ath9k_ps_wakeup(struct ath_softc *sc)
 237 {
 238         unsigned long flags;
 239
 240         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 241         if (++sc->ps_usecount != 1)
 242                 goto unlock;
 243
 244         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 245
 246  unlock:
 247         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 248 }
 249
 250 void ath9k_ps_restore(struct ath_softc *sc)
 251 {
 252         unsigned long flags;
 253
 254         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 255         if (--sc->ps_usecount != 0)
 256                 goto unlock;
 257
 258         if (sc->ps_enabled &&
 259             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
 260                               SC_OP_WAIT_FOR_CAB |
 261                               SC_OP_WAIT_FOR_PSPOLL_DATA |
 262                               SC_OP_WAIT_FOR_TX_ACK)))
 263                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
 264
 265  unlock:
 266         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 267 }
 268
 269 /*
 270  * Set/change channels.  If the channel is really being changed, it's done
 271  * by reseting the chip.  To accomplish this we must first cleanup any pending
 272  * DMA, then restart stuff.
 273 */
 274 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 275                     struct ath9k_channel *hchan)
 276 {
 277         struct ath_hw *ah = sc->sc_ah;
 278         struct ath_common *common = ath9k_hw_common(ah);
 279         struct ieee80211_conf *conf = &common->hw->conf;
 280         bool fastcc = true, stopped;
 281         struct ieee80211_channel *channel = hw->conf.channel;
 282         int r;
 283
 284         if (sc->sc_flags & SC_OP_INVALID)
 285                 return -EIO;
 286
 287         ath9k_ps_wakeup(sc);
 288
 289         /*
 290          * This is only performed if the channel settings have
 291          * actually changed.
 292          *
 293          * To switch channels clear any pending DMA operations;
 294          * wait long enough for the RX fifo to drain, reset the
 295          * hardware at the new frequency, and then re-enable
 296          * the relevant bits of the h/w.
 297          */
 298         ath9k_hw_set_interrupts(ah, 0);
 299         ath_drain_all_txq(sc, false);
 300         stopped = ath_stoprecv(sc);
 301
 302         /* XXX: do not flush receive queue here. We don't want
 303          * to flush data frames already in queue because of
 304          * changing channel. */
 305
 306         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 307                 fastcc = false;
 308
 309         ath_print(common, ATH_DBG_CONFIG,
 310                   "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
 311                   sc->sc_ah->curchan->channel,
 312                   channel->center_freq, conf_is_ht40(conf));
 313
 314         spin_lock_bh(&sc->sc_resetlock);
 315
 316         r = ath9k_hw_reset(ah, hchan, fastcc);
 317         if (r) {
 318                 ath_print(common, ATH_DBG_FATAL,
 319                           "Unable to reset channel (%u Mhz) "
 320                           "reset status %d\n",
 321                           channel->center_freq, r);
 322                 spin_unlock_bh(&sc->sc_resetlock);
 323                 goto ps_restore;
 324         }
 325         spin_unlock_bh(&sc->sc_resetlock);
 326
 327         sc->sc_flags &= ~SC_OP_FULL_RESET;
 328
 329         if (ath_startrecv(sc) != 0) {
 330                 ath_print(common, ATH_DBG_FATAL,
 331                           "Unable to restart recv logic\n");
 332                 r = -EIO;
 333                 goto ps_restore;
 334         }
 335
 336         ath_cache_conf_rate(sc, &hw->conf);
 337         ath_update_txpow(sc);
 338         ath9k_hw_set_interrupts(ah, sc->imask);
 339
 340  ps_restore:
 341         ath9k_ps_restore(sc);
 342         return r;
 343 }
 344
 345 /*
 346  *  This routine performs the periodic noise floor calibration function
 347  *  that is used to adjust and optimize the chip performance.  This
 348  *  takes environmental changes (location, temperature) into account.
 349  *  When the task is complete, it reschedules itself depending on the
 350  *  appropriate interval that was calculated.
 351  */
 352 static void ath_ani_calibrate(unsigned long data)
 353 {
 354         struct ath_softc *sc = (struct ath_softc *)data;
 355         struct ath_hw *ah = sc->sc_ah;
 356         struct ath_common *common = ath9k_hw_common(ah);
 357         bool longcal = false;
 358         bool shortcal = false;
 359         bool aniflag = false;
 360         unsigned int timestamp = jiffies_to_msecs(jiffies);
 361         u32 cal_interval, short_cal_interval;
 362
 363         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 364                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 365
 366         /*
 367         * don't calibrate when we're scanning.
 368         * we are most likely not on our home channel.
 369         */
 370         spin_lock(&sc->ani_lock);
 371         if (sc->sc_flags & SC_OP_SCANNING)
 372                 goto set_timer;
 373
 374         /* Only calibrate if awake */
 375         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 376                 goto set_timer;
 377
 378         ath9k_ps_wakeup(sc);
 379
 380         /* Long calibration runs independently of short calibration. */
 381         if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 382                 longcal = true;
 383                 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 384                 common->ani.longcal_timer = timestamp;
 385         }
 386
 387         /* Short calibration applies only while caldone is false */
 388         if (!common->ani.caldone) {
 389                 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
 390                         shortcal = true;
 391                         ath_print(common, ATH_DBG_ANI,
 392                                   "shortcal @%lu\n", jiffies);
 393                         common->ani.shortcal_timer = timestamp;
 394                         common->ani.resetcal_timer = timestamp;
 395                 }
 396         } else {
 397                 if ((timestamp - common->ani.resetcal_timer) >=
 398                     ATH_RESTART_CALINTERVAL) {
 399                         common->ani.caldone = ath9k_hw_reset_calvalid(ah);
 400                         if (common->ani.caldone)
 401                                 common->ani.resetcal_timer = timestamp;
 402                 }
 403         }
 404
 405         /* Verify whether we must check ANI */
 406         if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 407                 aniflag = true;
 408                 common->ani.checkani_timer = timestamp;
 409         }
 410
 411         /* Skip all processing if there's nothing to do. */
 412         if (longcal || shortcal || aniflag) {
 413                 /* Call ANI routine if necessary */
 414                 if (aniflag)
 415                         ath9k_hw_ani_monitor(ah, ah->curchan);
 416
 417                 /* Perform calibration if necessary */
 418                 if (longcal || shortcal) {
 419                         common->ani.caldone =
 420                                 ath9k_hw_calibrate(ah,
 421                                                    ah->curchan,
 422                                                    common->rx_chainmask,
 423                                                    longcal);
 424
 425                         if (longcal)
 426                                 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 427                                                                      ah->curchan);
 428
 429                         ath_print(common, ATH_DBG_ANI,
 430                                   " calibrate chan %u/%x nf: %d\n",
 431                                   ah->curchan->channel,
 432                                   ah->curchan->channelFlags,
 433                                   common->ani.noise_floor);
 434                 }
 435         }
 436
 437         ath9k_ps_restore(sc);
 438
 439 set_timer:
 440         spin_unlock(&sc->ani_lock);
 441         /*
 442         * Set timer interval based on previous results.
 443         * The interval must be the shortest necessary to satisfy ANI,
 444         * short calibration and long calibration.
 445         */
 446         cal_interval = ATH_LONG_CALINTERVAL;
 447         if (sc->sc_ah->config.enable_ani)
 448                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 449         if (!common->ani.caldone)
 450                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 451
 452         mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 453 }
 454
 455 static void ath_start_ani(struct ath_common *common)
 456 {
 457         unsigned long timestamp = jiffies_to_msecs(jiffies);
 458
 459         common->ani.longcal_timer = timestamp;
 460         common->ani.shortcal_timer = timestamp;
 461         common->ani.checkani_timer = timestamp;
 462
 463         mod_timer(&common->ani.timer,
 464                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 465 }
 466
 467 /*
 468  * Update tx/rx chainmask. For legacy association,
 469  * hard code chainmask to 1x1, for 11n association, use
 470  * the chainmask configuration, for bt coexistence, use
 471  * the chainmask configuration even in legacy mode.
 472  */
 473 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 474 {
 475         struct ath_hw *ah = sc->sc_ah;
 476         struct ath_common *common = ath9k_hw_common(ah);
 477
 478         if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
 479             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
 480                 common->tx_chainmask = ah->caps.tx_chainmask;
 481                 common->rx_chainmask = ah->caps.rx_chainmask;
 482         } else {
 483                 common->tx_chainmask = 1;
 484                 common->rx_chainmask = 1;
 485         }
 486
 487         ath_print(common, ATH_DBG_CONFIG,
 488                   "tx chmask: %d, rx chmask: %d\n",
 489                   common->tx_chainmask,
 490                   common->rx_chainmask);
 491 }
 492
 493 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 494 {
 495         struct ath_node *an;
 496
 497         an = (struct ath_node *)sta->drv_priv;
 498
 499         if (sc->sc_flags & SC_OP_TXAGGR) {
 500                 ath_tx_node_init(sc, an);
 501                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
 502                                      sta->ht_cap.ampdu_factor);
 503                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 504                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
 505         }
 506 }
 507
 508 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 509 {
 510         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 511
 512         if (sc->sc_flags & SC_OP_TXAGGR)
 513                 ath_tx_node_cleanup(sc, an);
 514 }
 515
 516 static void ath9k_tasklet(unsigned long data)
 517 {
 518         struct ath_softc *sc = (struct ath_softc *)data;
 519         struct ath_hw *ah = sc->sc_ah;
 520         struct ath_common *common = ath9k_hw_common(ah);
 521
 522         u32 status = sc->intrstatus;
 523
 524         ath9k_ps_wakeup(sc);
 525
 526         if (status & ATH9K_INT_FATAL) {
 527                 ath_reset(sc, false);
 528                 ath9k_ps_restore(sc);
 529                 return;
 530         }
 531
 532         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 533                 spin_lock_bh(&sc->rx.rxflushlock);
 534                 ath_rx_tasklet(sc, 0);
 535                 spin_unlock_bh(&sc->rx.rxflushlock);
 536         }
 537
 538         if (status & ATH9K_INT_TX)
 539                 ath_tx_tasklet(sc);
 540
 541         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 542                 /*
 543                  * TSF sync does not look correct; remain awake to sync with
 544                  * the next Beacon.
 545                  */
 546                 ath_print(common, ATH_DBG_PS,
 547                           "TSFOOR - Sync with next Beacon\n");
 548                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
 549         }
 550
 551         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
 552                 if (status & ATH9K_INT_GENTIMER)
 553                         ath_gen_timer_isr(sc->sc_ah);
 554
 555         /* re-enable hardware interrupt */
 556         ath9k_hw_set_interrupts(ah, sc->imask);
 557         ath9k_ps_restore(sc);
 558 }
 559
 560 irqreturn_t ath_isr(int irq, void *dev)
 561 {
 562 #define SCHED_INTR (                            \
 563                 ATH9K_INT_FATAL |               \
 564                 ATH9K_INT_RXORN |               \
 565                 ATH9K_INT_RXEOL |               \
 566                 ATH9K_INT_RX |                  \
 567                 ATH9K_INT_TX |                  \
 568                 ATH9K_INT_BMISS |               \
 569                 ATH9K_INT_CST |                 \
 570                 ATH9K_INT_TSFOOR |              \
 571                 ATH9K_INT_GENTIMER)
 572
 573         struct ath_softc *sc = dev;
 574         struct ath_hw *ah = sc->sc_ah;
 575         enum ath9k_int status;
 576         bool sched = false;
 577
 578         /*
 579          * The hardware is not ready/present, don't
 580          * touch anything. Note this can happen early
 581          * on if the IRQ is shared.
 582          */
 583         if (sc->sc_flags & SC_OP_INVALID)
 584                 return IRQ_NONE;
 585
 586
 587         /* shared irq, not for us */
 588
 589         if (!ath9k_hw_intrpend(ah))
 590                 return IRQ_NONE;
 591
 592         /*
 593          * Figure out the reason(s) for the interrupt.  Note
 594          * that the hal returns a pseudo-ISR that may include
 595          * bits we haven't explicitly enabled so we mask the
 596          * value to insure we only process bits we requested.
 597          */
 598         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 599         status &= sc->imask;    /* discard unasked-for bits */
 600
 601         /*
 602          * If there are no status bits set, then this interrupt was not
 603          * for me (should have been caught above).
 604          */
 605         if (!status)
 606                 return IRQ_NONE;
 607
 608         /* Cache the status */
 609         sc->intrstatus = status;
 610
 611         if (status & SCHED_INTR)
 612                 sched = true;
 613
 614         /*
 615          * If a FATAL or RXORN interrupt is received, we have to reset the
 616          * chip immediately.
 617          */
 618         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 619                 goto chip_reset;
 620
 621         if (status & ATH9K_INT_SWBA)
 622                 tasklet_schedule(&sc->bcon_tasklet);
 623
 624         if (status & ATH9K_INT_TXURN)
 625                 ath9k_hw_updatetxtriglevel(ah, true);
 626
 627         if (status & ATH9K_INT_MIB) {
 628                 /*
 629                  * Disable interrupts until we service the MIB
 630                  * interrupt; otherwise it will continue to
 631                  * fire.
 632                  */
 633                 ath9k_hw_set_interrupts(ah, 0);
 634                 /*
 635                  * Let the hal handle the event. We assume
 636                  * it will clear whatever condition caused
 637                  * the interrupt.
 638                  */
 639                 ath9k_hw_procmibevent(ah);
 640                 ath9k_hw_set_interrupts(ah, sc->imask);
 641         }
 642
 643         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 644                 if (status & ATH9K_INT_TIM_TIMER) {
 645                         /* Clear RxAbort bit so that we can
 646                          * receive frames */
 647                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 648                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 649                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 650                 }
 651
 652 chip_reset:
 653
 654         ath_debug_stat_interrupt(sc, status);
 655
 656         if (sched) {
 657                 /* turn off every interrupt except SWBA */
 658                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 659                 tasklet_schedule(&sc->intr_tq);
 660         }
 661
 662         return IRQ_HANDLED;
 663
 664 #undef SCHED_INTR
 665 }
 666
 667 static u32 ath_get_extchanmode(struct ath_softc *sc,
 668                                struct ieee80211_channel *chan,
 669                                enum nl80211_channel_type channel_type)
 670 {
 671         u32 chanmode = 0;
 672
 673         switch (chan->band) {
 674         case IEEE80211_BAND_2GHZ:
 675                 switch(channel_type) {
 676                 case NL80211_CHAN_NO_HT:
 677                 case NL80211_CHAN_HT20:
 678                         chanmode = CHANNEL_G_HT20;
 679                         break;
 680                 case NL80211_CHAN_HT40PLUS:
 681                         chanmode = CHANNEL_G_HT40PLUS;
 682                         break;
 683                 case NL80211_CHAN_HT40MINUS:
 684                         chanmode = CHANNEL_G_HT40MINUS;
 685                         break;
 686                 }
 687                 break;
 688         case IEEE80211_BAND_5GHZ:
 689                 switch(channel_type) {
 690                 case NL80211_CHAN_NO_HT:
 691                 case NL80211_CHAN_HT20:
 692                         chanmode = CHANNEL_A_HT20;
 693                         break;
 694                 case NL80211_CHAN_HT40PLUS:
 695                         chanmode = CHANNEL_A_HT40PLUS;
 696                         break;
 697                 case NL80211_CHAN_HT40MINUS:
 698                         chanmode = CHANNEL_A_HT40MINUS;
 699                         break;
 700                 }
 701                 break;
 702         default:
 703                 break;
 704         }
 705
 706         return chanmode;
 707 }
 708
 709 static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
 710                            struct ath9k_keyval *hk, const u8 *addr,
 711                            bool authenticator)
 712 {
 713         struct ath_hw *ah = common->ah;
 714         const u8 *key_rxmic;
 715         const u8 *key_txmic;
 716
 717         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 718         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 719
 720         if (addr == NULL) {
 721                 /*
 722                  * Group key installation - only two key cache entries are used
 723                  * regardless of splitmic capability since group key is only
 724                  * used either for TX or RX.
 725                  */
 726                 if (authenticator) {
 727                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 728                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 729                 } else {
 730                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 731                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 732                 }
 733                 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
 734         }
 735         if (!common->splitmic) {
 736                 /* TX and RX keys share the same key cache entry. */
 737                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 738                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 739                 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
 740         }
 741
 742         /* Separate key cache entries for TX and RX */
 743
 744         /* TX key goes at first index, RX key at +32. */
 745         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 746         if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
 747                 /* TX MIC entry failed. No need to proceed further */
 748                 ath_print(common, ATH_DBG_FATAL,
 749                           "Setting TX MIC Key Failed\n");
 750                 return 0;
 751         }
 752
 753         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 754         /* XXX delete tx key on failure? */
 755         return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
 756 }
 757
 758 static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
 759 {
 760         int i;
 761
 762         for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
 763                 if (test_bit(i, common->keymap) ||
 764                     test_bit(i + 64, common->keymap))
 765                         continue; /* At least one part of TKIP key allocated */
 766                 if (common->splitmic &&
 767                     (test_bit(i + 32, common->keymap) ||
 768                      test_bit(i + 64 + 32, common->keymap)))
 769                         continue; /* At least one part of TKIP key allocated */
 770
 771                 /* Found a free slot for a TKIP key */
 772                 return i;
 773         }
 774         return -1;
 775 }
 776
 777 static int ath_reserve_key_cache_slot(struct ath_common *common)
 778 {
 779         int i;
 780
 781         /* First, try to find slots that would not be available for TKIP. */
 782         if (common->splitmic) {
 783                 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
 784                         if (!test_bit(i, common->keymap) &&
 785                             (test_bit(i + 32, common->keymap) ||
 786                              test_bit(i + 64, common->keymap) ||
 787                              test_bit(i + 64 + 32, common->keymap)))
 788                                 return i;
 789                         if (!test_bit(i + 32, common->keymap) &&
 790                             (test_bit(i, common->keymap) ||
 791                              test_bit(i + 64, common->keymap) ||
 792                              test_bit(i + 64 + 32, common->keymap)))
 793                                 return i + 32;
 794                         if (!test_bit(i + 64, common->keymap) &&
 795                             (test_bit(i , common->keymap) ||
 796                              test_bit(i + 32, common->keymap) ||
 797                              test_bit(i + 64 + 32, common->keymap)))
 798                                 return i + 64;
 799                         if (!test_bit(i + 64 + 32, common->keymap) &&
 800                             (test_bit(i, common->keymap) ||
 801                              test_bit(i + 32, common->keymap) ||
 802                              test_bit(i + 64, common->keymap)))
 803                                 return i + 64 + 32;
 804                 }
 805         } else {
 806                 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
 807                         if (!test_bit(i, common->keymap) &&
 808                             test_bit(i + 64, common->keymap))
 809                                 return i;
 810                         if (test_bit(i, common->keymap) &&
 811                             !test_bit(i + 64, common->keymap))
 812                                 return i + 64;
 813                 }
 814         }
 815
 816         /* No partially used TKIP slots, pick any available slot */
 817         for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
 818                 /* Do not allow slots that could be needed for TKIP group keys
 819                  * to be used. This limitation could be removed if we know that
 820                  * TKIP will not be used. */
 821                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 822                         continue;
 823                 if (common->splitmic) {
 824                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 825                                 continue;
 826                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 827                                 continue;
 828                 }
 829
 830                 if (!test_bit(i, common->keymap))
 831                         return i; /* Found a free slot for a key */
 832         }
 833
 834         /* No free slot found */
 835         return -1;
 836 }
 837
 838 static int ath_key_config(struct ath_common *common,
 839                           struct ieee80211_vif *vif,
 840                           struct ieee80211_sta *sta,
 841                           struct ieee80211_key_conf *key)
 842 {
 843         struct ath_hw *ah = common->ah;
 844         struct ath9k_keyval hk;
 845         const u8 *mac = NULL;
 846         int ret = 0;
 847         int idx;
 848
 849         memset(&hk, 0, sizeof(hk));
 850
 851         switch (key->alg) {
 852         case ALG_WEP:
 853                 hk.kv_type = ATH9K_CIPHER_WEP;
 854                 break;
 855         case ALG_TKIP:
 856                 hk.kv_type = ATH9K_CIPHER_TKIP;
 857                 break;
 858         case ALG_CCMP:
 859                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 860                 break;
 861         default:
 862                 return -EOPNOTSUPP;
 863         }
 864
 865         hk.kv_len = key->keylen;
 866         memcpy(hk.kv_val, key->key, key->keylen);
 867
 868         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 869                 /* For now, use the default keys for broadcast keys. This may
 870                  * need to change with virtual interfaces. */
 871                 idx = key->keyidx;
 872         } else if (key->keyidx) {
 873                 if (WARN_ON(!sta))
 874                         return -EOPNOTSUPP;
 875                 mac = sta->addr;
 876
 877                 if (vif->type != NL80211_IFTYPE_AP) {
 878                         /* Only keyidx 0 should be used with unicast key, but
 879                          * allow this for client mode for now. */
 880                         idx = key->keyidx;
 881                 } else
 882                         return -EIO;
 883         } else {
 884                 if (WARN_ON(!sta))
 885                         return -EOPNOTSUPP;
 886                 mac = sta->addr;
 887
 888                 if (key->alg == ALG_TKIP)
 889                         idx = ath_reserve_key_cache_slot_tkip(common);
 890                 else
 891                         idx = ath_reserve_key_cache_slot(common);
 892                 if (idx < 0)
 893                         return -ENOSPC; /* no free key cache entries */
 894         }
 895
 896         if (key->alg == ALG_TKIP)
 897                 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
 898                                       vif->type == NL80211_IFTYPE_AP);
 899         else
 900                 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
 901
 902         if (!ret)
 903                 return -EIO;
 904
 905         set_bit(idx, common->keymap);
 906         if (key->alg == ALG_TKIP) {
 907                 set_bit(idx + 64, common->keymap);
 908                 if (common->splitmic) {
 909                         set_bit(idx + 32, common->keymap);
 910                         set_bit(idx + 64 + 32, common->keymap);
 911                 }
 912         }
 913
 914         return idx;
 915 }
 916
 917 static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
 918 {
 919         struct ath_hw *ah = common->ah;
 920
 921         ath9k_hw_keyreset(ah, key->hw_key_idx);
 922         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 923                 return;
 924
 925         clear_bit(key->hw_key_idx, common->keymap);
 926         if (key->alg != ALG_TKIP)
 927                 return;
 928
 929         clear_bit(key->hw_key_idx + 64, common->keymap);
 930         if (common->splitmic) {
 931                 clear_bit(key->hw_key_idx + 32, common->keymap);
 932                 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
 933         }
 934 }
 935
 936 static void setup_ht_cap(struct ath_softc *sc,
 937                          struct ieee80211_sta_ht_cap *ht_info)
 938 {
 939         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 940         u8 tx_streams, rx_streams;
 941
 942         ht_info->ht_supported = true;
 943         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 944                        IEEE80211_HT_CAP_SM_PS |
 945                        IEEE80211_HT_CAP_SGI_40 |
 946                        IEEE80211_HT_CAP_DSSSCCK40;
 947
 948         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
 949         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 950
 951         /* set up supported mcs set */
 952         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 953         tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
 954                      1 : 2;
 955         rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
 956                      1 : 2;
 957
 958         if (tx_streams != rx_streams) {
 959                 ath_print(common, ATH_DBG_CONFIG,
 960                           "TX streams %d, RX streams: %d\n",
 961                           tx_streams, rx_streams);
 962                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 963                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
 964                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 965         }
 966
 967         ht_info->mcs.rx_mask[0] = 0xff;
 968         if (rx_streams >= 2)
 969                 ht_info->mcs.rx_mask[1] = 0xff;
 970
 971         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
 972 }
 973
 974 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 975                                  struct ieee80211_vif *vif,
 976                                  struct ieee80211_bss_conf *bss_conf)
 977 {
 978         struct ath_hw *ah = sc->sc_ah;
 979         struct ath_common *common = ath9k_hw_common(ah);
 980
 981         if (bss_conf->assoc) {
 982                 ath_print(common, ATH_DBG_CONFIG,
 983                           "Bss Info ASSOC %d, bssid: %pM\n",
 984                            bss_conf->aid, common->curbssid);
 985
 986                 /* New association, store aid */
 987                 common->curaid = bss_conf->aid;
 988                 ath9k_hw_write_associd(ah);
 989
 990                 /*
 991                  * Request a re-configuration of Beacon related timers
 992                  * on the receipt of the first Beacon frame (i.e.,
 993                  * after time sync with the AP).
 994                  */
 995                 sc->sc_flags |= SC_OP_BEACON_SYNC;
 996
 997                 /* Configure the beacon */
 998                 ath_beacon_config(sc, vif);
 999
1000                 /* Reset rssi stats */
1001                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1002
1003                 ath_start_ani(common);
1004         } else {
1005                 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1006                 common->curaid = 0;
1007                 /* Stop ANI */
1008                 del_timer_sync(&common->ani.timer);
1009         }
1010 }
1011
1012 /********************************/
1013 /*       LED functions          */
1014 /********************************/
1015
1016 static void ath_led_blink_work(struct work_struct *work)
1017 {
1018         struct ath_softc *sc = container_of(work, struct ath_softc,
1019                                             ath_led_blink_work.work);
1020
1021         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1022                 return;
1023
1024         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1025             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1026                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1027         else
1028                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1029                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1030
1031         ieee80211_queue_delayed_work(sc->hw,
1032                                      &sc->ath_led_blink_work,
1033                                      (sc->sc_flags & SC_OP_LED_ON) ?
1034                                         msecs_to_jiffies(sc->led_off_duration) :
1035                                         msecs_to_jiffies(sc->led_on_duration));
1036
1037         sc->led_on_duration = sc->led_on_cnt ?
1038                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1039                         ATH_LED_ON_DURATION_IDLE;
1040         sc->led_off_duration = sc->led_off_cnt ?
1041                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1042                         ATH_LED_OFF_DURATION_IDLE;
1043         sc->led_on_cnt = sc->led_off_cnt = 0;
1044         if (sc->sc_flags & SC_OP_LED_ON)
1045                 sc->sc_flags &= ~SC_OP_LED_ON;
1046         else
1047                 sc->sc_flags |= SC_OP_LED_ON;
1048 }
1049
1050 static void ath_led_brightness(struct led_classdev *led_cdev,
1051                                enum led_brightness brightness)
1052 {
1053         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1054         struct ath_softc *sc = led->sc;
1055
1056         switch (brightness) {
1057         case LED_OFF:
1058                 if (led->led_type == ATH_LED_ASSOC ||
1059                     led->led_type == ATH_LED_RADIO) {
1060                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1061                                 (led->led_type == ATH_LED_RADIO));
1062                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1063                         if (led->led_type == ATH_LED_RADIO)
1064                                 sc->sc_flags &= ~SC_OP_LED_ON;
1065                 } else {
1066                         sc->led_off_cnt++;
1067                 }
1068                 break;
1069         case LED_FULL:
1070                 if (led->led_type == ATH_LED_ASSOC) {
1071                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1072                         ieee80211_queue_delayed_work(sc->hw,
1073                                                      &sc->ath_led_blink_work, 0);
1074                 } else if (led->led_type == ATH_LED_RADIO) {
1075                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1076                         sc->sc_flags |= SC_OP_LED_ON;
1077                 } else {
1078                         sc->led_on_cnt++;
1079                 }
1080                 break;
1081         default:
1082                 break;
1083         }
1084 }
1085
1086 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1087                             char *trigger)
1088 {
1089         int ret;
1090
1091         led->sc = sc;
1092         led->led_cdev.name = led->name;
1093         led->led_cdev.default_trigger = trigger;
1094         led->led_cdev.brightness_set = ath_led_brightness;
1095
1096         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1097         if (ret)
1098                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1099                           "Failed to register led:%s", led->name);
1100         else
1101                 led->registered = 1;
1102         return ret;
1103 }
1104
1105 static void ath_unregister_led(struct ath_led *led)
1106 {
1107         if (led->registered) {
1108                 led_classdev_unregister(&led->led_cdev);
1109                 led->registered = 0;
1110         }
1111 }
1112
1113 static void ath_deinit_leds(struct ath_softc *sc)
1114 {
1115         ath_unregister_led(&sc->assoc_led);
1116         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1117         ath_unregister_led(&sc->tx_led);
1118         ath_unregister_led(&sc->rx_led);
1119         ath_unregister_led(&sc->radio_led);
1120         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1121 }
1122
1123 static void ath_init_leds(struct ath_softc *sc)
1124 {
1125         char *trigger;
1126         int ret;
1127
1128         if (AR_SREV_9287(sc->sc_ah))
1129                 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1130         else
1131                 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1132
1133         /* Configure gpio 1 for output */
1134         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1135                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1136         /* LED off, active low */
1137         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1138
1139         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1140
1141         trigger = ieee80211_get_radio_led_name(sc->hw);
1142         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1143                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1144         ret = ath_register_led(sc, &sc->radio_led, trigger);
1145         sc->radio_led.led_type = ATH_LED_RADIO;
1146         if (ret)
1147                 goto fail;
1148
1149         trigger = ieee80211_get_assoc_led_name(sc->hw);
1150         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1151                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1152         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1153         sc->assoc_led.led_type = ATH_LED_ASSOC;
1154         if (ret)
1155                 goto fail;
1156
1157         trigger = ieee80211_get_tx_led_name(sc->hw);
1158         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1159                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1160         ret = ath_register_led(sc, &sc->tx_led, trigger);
1161         sc->tx_led.led_type = ATH_LED_TX;
1162         if (ret)
1163                 goto fail;
1164
1165         trigger = ieee80211_get_rx_led_name(sc->hw);
1166         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1167                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1168         ret = ath_register_led(sc, &sc->rx_led, trigger);
1169         sc->rx_led.led_type = ATH_LED_RX;
1170         if (ret)
1171                 goto fail;
1172
1173         return;
1174
1175 fail:
1176         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1177         ath_deinit_leds(sc);
1178 }
1179
1180 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
1181 {
1182         struct ath_hw *ah = sc->sc_ah;
1183         struct ath_common *common = ath9k_hw_common(ah);
1184         struct ieee80211_channel *channel = hw->conf.channel;
1185         int r;
1186
1187         ath9k_ps_wakeup(sc);
1188         ath9k_hw_configpcipowersave(ah, 0, 0);
1189
1190         if (!ah->curchan)
1191                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1192
1193         spin_lock_bh(&sc->sc_resetlock);
1194         r = ath9k_hw_reset(ah, ah->curchan, false);
1195         if (r) {
1196                 ath_print(common, ATH_DBG_FATAL,
1197                           "Unable to reset channel %u (%uMhz) ",
1198                           "reset status %d\n",
1199                           channel->center_freq, r);
1200         }
1201         spin_unlock_bh(&sc->sc_resetlock);
1202
1203         ath_update_txpow(sc);
1204         if (ath_startrecv(sc) != 0) {
1205                 ath_print(common, ATH_DBG_FATAL,
1206                           "Unable to restart recv logic\n");
1207                 return;
1208         }
1209
1210         if (sc->sc_flags & SC_OP_BEACONS)
1211                 ath_beacon_config(sc, NULL);    /* restart beacons */
1212
1213         /* Re-Enable  interrupts */
1214         ath9k_hw_set_interrupts(ah, sc->imask);
1215
1216         /* Enable LED */
1217         ath9k_hw_cfg_output(ah, ah->led_pin,
1218                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1219         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1220
1221         ieee80211_wake_queues(hw);
1222         ath9k_ps_restore(sc);
1223 }
1224
1225 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
1226 {
1227         struct ath_hw *ah = sc->sc_ah;
1228         struct ieee80211_channel *channel = hw->conf.channel;
1229         int r;
1230
1231         ath9k_ps_wakeup(sc);
1232         ieee80211_stop_queues(hw);
1233
1234         /* Disable LED */
1235         ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1236         ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1237
1238         /* Disable interrupts */
1239         ath9k_hw_set_interrupts(ah, 0);
1240
1241         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1242         ath_stoprecv(sc);               /* turn off frame recv */
1243         ath_flushrecv(sc);              /* flush recv queue */
1244
1245         if (!ah->curchan)
1246                 ah->curchan = ath_get_curchannel(sc, hw);
1247
1248         spin_lock_bh(&sc->sc_resetlock);
1249         r = ath9k_hw_reset(ah, ah->curchan, false);
1250         if (r) {
1251                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1252                           "Unable to reset channel %u (%uMhz) "
1253                           "reset status %d\n",
1254                           channel->center_freq, r);
1255         }
1256         spin_unlock_bh(&sc->sc_resetlock);
1257
1258         ath9k_hw_phy_disable(ah);
1259         ath9k_hw_configpcipowersave(ah, 1, 1);
1260         ath9k_ps_restore(sc);
1261         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1262 }
1263
1264 /*******************/
1265 /*      Rfkill     */
1266 /*******************/
1267
1268 static bool ath_is_rfkill_set(struct ath_softc *sc)
1269 {
1270         struct ath_hw *ah = sc->sc_ah;
1271
1272         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1273                                   ah->rfkill_polarity;
1274 }
1275
1276 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1277 {
1278         struct ath_wiphy *aphy = hw->priv;
1279         struct ath_softc *sc = aphy->sc;
1280         bool blocked = !!ath_is_rfkill_set(sc);
1281
1282         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1283 }
1284
1285 static void ath_start_rfkill_poll(struct ath_softc *sc)
1286 {
1287         struct ath_hw *ah = sc->sc_ah;
1288
1289         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1290                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1291 }
1292
1293 static void ath9k_uninit_hw(struct ath_softc *sc)
1294 {
1295         struct ath_hw *ah = sc->sc_ah;
1296
1297         BUG_ON(!ah);
1298
1299         ath9k_exit_debug(ah);
1300         ath9k_hw_detach(ah);
1301         sc->sc_ah = NULL;
1302 }
1303
1304 static void ath_clean_core(struct ath_softc *sc)
1305 {
1306         struct ieee80211_hw *hw = sc->hw;
1307         struct ath_hw *ah = sc->sc_ah;
1308         int i = 0;
1309
1310         ath9k_ps_wakeup(sc);
1311
1312         dev_dbg(sc->dev, "Detach ATH hw\n");
1313
1314         ath_deinit_leds(sc);
1315         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1316
1317         for (i = 0; i < sc->num_sec_wiphy; i++) {
1318                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1319                 if (aphy == NULL)
1320                         continue;
1321                 sc->sec_wiphy[i] = NULL;
1322                 ieee80211_unregister_hw(aphy->hw);
1323                 ieee80211_free_hw(aphy->hw);
1324         }
1325         ieee80211_unregister_hw(hw);
1326         ath_rx_cleanup(sc);
1327         ath_tx_cleanup(sc);
1328
1329         tasklet_kill(&sc->intr_tq);
1330         tasklet_kill(&sc->bcon_tasklet);
1331
1332         if (!(sc->sc_flags & SC_OP_INVALID))
1333                 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1334
1335         /* cleanup tx queues */
1336         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1337                 if (ATH_TXQ_SETUP(sc, i))
1338                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1339
1340         if ((sc->btcoex.no_stomp_timer) &&
1341             ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1342                 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1343 }
1344
1345 void ath_detach(struct ath_softc *sc)
1346 {
1347         ath_clean_core(sc);
1348         ath9k_uninit_hw(sc);
1349 }
1350
1351 void ath_cleanup(struct ath_softc *sc)
1352 {
1353         struct ath_hw *ah = sc->sc_ah;
1354         struct ath_common *common = ath9k_hw_common(ah);
1355
1356         ath_clean_core(sc);
1357         free_irq(sc->irq, sc);
1358         ath_bus_cleanup(common);
1359         kfree(sc->sec_wiphy);
1360         ieee80211_free_hw(sc->hw);
1361
1362         ath9k_uninit_hw(sc);
1363 }
1364
1365 static int ath9k_reg_notifier(struct wiphy *wiphy,
1366                               struct regulatory_request *request)
1367 {
1368         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1369         struct ath_wiphy *aphy = hw->priv;
1370         struct ath_softc *sc = aphy->sc;
1371         struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1372
1373         return ath_reg_notifier_apply(wiphy, request, reg);
1374 }
1375
1376 /*
1377  * Detects if there is any priority bt traffic
1378  */
1379 static void ath_detect_bt_priority(struct ath_softc *sc)
1380 {
1381         struct ath_btcoex *btcoex = &sc->btcoex;
1382         struct ath_hw *ah = sc->sc_ah;
1383
1384         if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1385                 btcoex->bt_priority_cnt++;
1386
1387         if (time_after(jiffies, btcoex->bt_priority_time +
1388                         msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1389                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1390                         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1391                                   "BT priority traffic detected");
1392                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1393                 } else {
1394                         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1395                 }
1396
1397                 btcoex->bt_priority_cnt = 0;
1398                 btcoex->bt_priority_time = jiffies;
1399         }
1400 }
1401
1402 /*
1403  * Configures appropriate weight based on stomp type.
1404  */
1405 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1406                                   enum ath_stomp_type stomp_type)
1407 {
1408         struct ath_hw *ah = sc->sc_ah;
1409
1410         switch (stomp_type) {
1411         case ATH_BTCOEX_STOMP_ALL:
1412                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1413                                            AR_STOMP_ALL_WLAN_WGHT);
1414                 break;
1415         case ATH_BTCOEX_STOMP_LOW:
1416                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1417                                            AR_STOMP_LOW_WLAN_WGHT);
1418                 break;
1419         case ATH_BTCOEX_STOMP_NONE:
1420                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1421                                            AR_STOMP_NONE_WLAN_WGHT);
1422                 break;
1423         default:
1424                 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1425                           "Invalid Stomptype\n");
1426                 break;
1427         }
1428
1429         ath9k_hw_btcoex_enable(ah);
1430 }
1431
1432 static void ath9k_gen_timer_start(struct ath_hw *ah,
1433                                   struct ath_gen_timer *timer,
1434                                   u32 timer_next,
1435                                   u32 timer_period)
1436 {
1437         struct ath_common *common = ath9k_hw_common(ah);
1438         struct ath_softc *sc = (struct ath_softc *) common->priv;
1439
1440         ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1441
1442         if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
1443                 ath9k_hw_set_interrupts(ah, 0);
1444                 sc->imask |= ATH9K_INT_GENTIMER;
1445                 ath9k_hw_set_interrupts(ah, sc->imask);
1446         }
1447 }
1448
1449 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1450 {
1451         struct ath_common *common = ath9k_hw_common(ah);
1452         struct ath_softc *sc = (struct ath_softc *) common->priv;
1453         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1454
1455         ath9k_hw_gen_timer_stop(ah, timer);
1456
1457         /* if no timer is enabled, turn off interrupt mask */
1458         if (timer_table->timer_mask.val == 0) {
1459                 ath9k_hw_set_interrupts(ah, 0);
1460                 sc->imask &= ~ATH9K_INT_GENTIMER;
1461                 ath9k_hw_set_interrupts(ah, sc->imask);
1462         }
1463 }
1464
1465 /*
1466  * This is the master bt coex timer which runs for every
1467  * 45ms, bt traffic will be given priority during 55% of this
1468  * period while wlan gets remaining 45%
1469  */
1470 static void ath_btcoex_period_timer(unsigned long data)
1471 {
1472         struct ath_softc *sc = (struct ath_softc *) data;
1473         struct ath_hw *ah = sc->sc_ah;
1474         struct ath_btcoex *btcoex = &sc->btcoex;
1475
1476         ath_detect_bt_priority(sc);
1477
1478         spin_lock_bh(&btcoex->btcoex_lock);
1479
1480         ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1481
1482         spin_unlock_bh(&btcoex->btcoex_lock);
1483
1484         if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1485                 if (btcoex->hw_timer_enabled)
1486                         ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1487
1488                 ath9k_gen_timer_start(ah,
1489                                       btcoex->no_stomp_timer,
1490                                       (ath9k_hw_gettsf32(ah) +
1491                                        btcoex->btcoex_no_stomp),
1492                                        btcoex->btcoex_no_stomp * 10);
1493                 btcoex->hw_timer_enabled = true;
1494         }
1495
1496         mod_timer(&btcoex->period_timer, jiffies +
1497                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1498 }
1499
1500 /*
1501  * Generic tsf based hw timer which configures weight
1502  * registers to time slice between wlan and bt traffic
1503  */
1504 static void ath_btcoex_no_stomp_timer(void *arg)
1505 {
1506         struct ath_softc *sc = (struct ath_softc *)arg;
1507         struct ath_hw *ah = sc->sc_ah;
1508         struct ath_btcoex *btcoex = &sc->btcoex;
1509
1510         ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1511                   "no stomp timer running \n");
1512
1513         spin_lock_bh(&btcoex->btcoex_lock);
1514
1515         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1516                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1517          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1518                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1519
1520         spin_unlock_bh(&btcoex->btcoex_lock);
1521 }
1522
1523 static int ath_init_btcoex_timer(struct ath_softc *sc)
1524 {
1525         struct ath_btcoex *btcoex = &sc->btcoex;
1526
1527         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1528         btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1529                 btcoex->btcoex_period / 100;
1530
1531         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1532                         (unsigned long) sc);
1533
1534         spin_lock_init(&btcoex->btcoex_lock);
1535
1536         btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1537                         ath_btcoex_no_stomp_timer,
1538                         ath_btcoex_no_stomp_timer,
1539                         (void *) sc, AR_FIRST_NDP_TIMER);
1540
1541         if (!btcoex->no_stomp_timer)
1542                 return -ENOMEM;
1543
1544         return 0;
1545 }
1546
1547 /*
1548  * Read and write, they both share the same lock. We do this to serialize
1549  * reads and writes on Atheros 802.11n PCI devices only. This is required
1550  * as the FIFO on these devices can only accept sanely 2 requests. After
1551  * that the device goes bananas. Serializing the reads/writes prevents this
1552  * from happening.
1553  */
1554
1555 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1556 {
1557         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1558         struct ath_common *common = ath9k_hw_common(ah);
1559         struct ath_softc *sc = (struct ath_softc *) common->priv;
1560
1561         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1562                 unsigned long flags;
1563                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1564                 iowrite32(val, sc->mem + reg_offset);
1565                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1566         } else
1567                 iowrite32(val, sc->mem + reg_offset);
1568 }
1569
1570 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1571 {
1572         struct ath_hw *ah = (struct ath_hw *) hw_priv;
1573         struct ath_common *common = ath9k_hw_common(ah);
1574         struct ath_softc *sc = (struct ath_softc *) common->priv;
1575         u32 val;
1576
1577         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1578                 unsigned long flags;
1579                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1580                 val = ioread32(sc->mem + reg_offset);
1581                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1582         } else
1583                 val = ioread32(sc->mem + reg_offset);
1584         return val;
1585 }
1586
1587 static const struct ath_ops ath9k_common_ops = {
1588         .read = ath9k_ioread32,
1589         .write = ath9k_iowrite32,
1590 };
1591
1592 /*
1593  * Initialize and fill ath_softc, ath_sofct is the
1594  * "Software Carrier" struct. Historically it has existed
1595  * to allow the separation between hardware specific
1596  * variables (now in ath_hw) and driver specific variables.
1597  */
1598 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1599                           const struct ath_bus_ops *bus_ops)
1600 {
1601         struct ath_hw *ah = NULL;
1602         struct ath_common *common;
1603         int r = 0, i;
1604         int csz = 0;
1605         int qnum;
1606
1607         /* XXX: hardware will not be ready until ath_open() being called */
1608         sc->sc_flags |= SC_OP_INVALID;
1609
1610         spin_lock_init(&sc->wiphy_lock);
1611         spin_lock_init(&sc->sc_resetlock);
1612         spin_lock_init(&sc->sc_serial_rw);
1613         spin_lock_init(&sc->ani_lock);
1614         spin_lock_init(&sc->sc_pm_lock);
1615         mutex_init(&sc->mutex);
1616         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1617         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1618                      (unsigned long)sc);
1619
1620         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1621         if (!ah)
1622                 return -ENOMEM;
1623
1624         ah->hw_version.devid = devid;
1625         ah->hw_version.subsysid = subsysid;
1626         sc->sc_ah = ah;
1627
1628         common = ath9k_hw_common(ah);
1629         common->ops = &ath9k_common_ops;
1630         common->bus_ops = bus_ops;
1631         common->ah = ah;
1632         common->hw = sc->hw;
1633         common->priv = sc;
1634         common->debug_mask = ath9k_debug;
1635
1636         /*
1637          * Cache line size is used to size and align various
1638          * structures used to communicate with the hardware.
1639          */
1640         ath_read_cachesize(common, &csz);
1641         /* XXX assert csz is non-zero */
1642         common->cachelsz = csz << 2;    /* convert to bytes */
1643
1644         r = ath9k_hw_init(ah);
1645         if (r) {
1646                 ath_print(common, ATH_DBG_FATAL,
1647                           "Unable to initialize hardware; "
1648                           "initialization status: %d\n", r);
1649                 goto bad_free_hw;
1650         }
1651
1652         if (ath9k_init_debug(ah) < 0) {
1653                 ath_print(common, ATH_DBG_FATAL,
1654                           "Unable to create debugfs files\n");
1655                 goto bad_free_hw;
1656         }
1657
1658         /* Get the hardware key cache size. */
1659         common->keymax = ah->caps.keycache_size;
1660         if (common->keymax > ATH_KEYMAX) {
1661                 ath_print(common, ATH_DBG_ANY,
1662                           "Warning, using only %u entries in %u key cache\n",
1663                           ATH_KEYMAX, common->keymax);
1664                 common->keymax = ATH_KEYMAX;
1665         }
1666
1667         /*
1668          * Reset the key cache since some parts do not
1669          * reset the contents on initial power up.
1670          */
1671         for (i = 0; i < common->keymax; i++)
1672                 ath9k_hw_keyreset(ah, (u16) i);
1673
1674         /* default to MONITOR mode */
1675         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1676
1677         /*
1678          * Allocate hardware transmit queues: one queue for
1679          * beacon frames and one data queue for each QoS
1680          * priority.  Note that the hal handles reseting
1681          * these queues at the needed time.
1682          */
1683         sc->beacon.beaconq = ath9k_hw_beaconq_setup(ah);
1684         if (sc->beacon.beaconq == -1) {
1685                 ath_print(common, ATH_DBG_FATAL,
1686                           "Unable to setup a beacon xmit queue\n");
1687                 r = -EIO;
1688                 goto bad2;
1689         }
1690         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1691         if (sc->beacon.cabq == NULL) {
1692                 ath_print(common, ATH_DBG_FATAL,
1693                           "Unable to setup CAB xmit queue\n");
1694                 r = -EIO;
1695                 goto bad2;
1696         }
1697
1698         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1699         ath_cabq_update(sc);
1700
1701         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1702                 sc->tx.hwq_map[i] = -1;
1703
1704         /* Setup data queues */
1705         /* NB: ensure BK queue is the lowest priority h/w queue */
1706         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1707                 ath_print(common, ATH_DBG_FATAL,
1708                           "Unable to setup xmit queue for BK traffic\n");
1709                 r = -EIO;
1710                 goto bad2;
1711         }
1712
1713         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1714                 ath_print(common, ATH_DBG_FATAL,
1715                           "Unable to setup xmit queue for BE traffic\n");
1716                 r = -EIO;
1717                 goto bad2;
1718         }
1719         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1720                 ath_print(common, ATH_DBG_FATAL,
1721                           "Unable to setup xmit queue for VI traffic\n");
1722                 r = -EIO;
1723                 goto bad2;
1724         }
1725         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1726                 ath_print(common, ATH_DBG_FATAL,
1727                           "Unable to setup xmit queue for VO traffic\n");
1728                 r = -EIO;
1729                 goto bad2;
1730         }
1731
1732         /* Initializes the noise floor to a reasonable default value.
1733          * Later on this will be updated during ANI processing. */
1734
1735         common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1736         setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1737
1738         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1739                                    ATH9K_CIPHER_TKIP, NULL)) {
1740                 /*
1741                  * Whether we should enable h/w TKIP MIC.
1742                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1743                  * report WMM capable, so it's always safe to turn on
1744                  * TKIP MIC in this case.
1745                  */
1746                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1747                                        0, 1, NULL);
1748         }
1749
1750         /*
1751          * Check whether the separate key cache entries
1752          * are required to handle both tx+rx MIC keys.
1753          * With split mic keys the number of stations is limited
1754          * to 27 otherwise 59.
1755          */
1756         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1757                                    ATH9K_CIPHER_TKIP, NULL)
1758             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1759                                       ATH9K_CIPHER_MIC, NULL)
1760             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1761                                       0, NULL))
1762                 common->splitmic = 1;
1763
1764         /* turn on mcast key search if possible */
1765         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1766                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1767                                              1, NULL);
1768
1769         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1770
1771         /* 11n Capabilities */
1772         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1773                 sc->sc_flags |= SC_OP_TXAGGR;
1774                 sc->sc_flags |= SC_OP_RXAGGR;
1775         }
1776
1777         common->tx_chainmask = ah->caps.tx_chainmask;
1778         common->rx_chainmask = ah->caps.rx_chainmask;
1779
1780         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1781         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1782
1783         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1784                 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1785
1786         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1787
1788         /* initialize beacon slots */
1789         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1790                 sc->beacon.bslot[i] = NULL;
1791                 sc->beacon.bslot_aphy[i] = NULL;
1792         }
1793
1794         /* setup channels and rates */
1795
1796         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1797         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1798         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1799                 ARRAY_SIZE(ath9k_2ghz_chantable);
1800         sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
1801         sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
1802                 ARRAY_SIZE(ath9k_legacy_rates);
1803
1804         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1805                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1806                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1807                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1808                         ARRAY_SIZE(ath9k_5ghz_chantable);
1809                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1810                         ath9k_legacy_rates + 4;
1811                 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
1812                         ARRAY_SIZE(ath9k_legacy_rates) - 4;
1813         }
1814
1815         switch (ah->btcoex_hw.scheme) {
1816         case ATH_BTCOEX_CFG_NONE:
1817                 break;
1818         case ATH_BTCOEX_CFG_2WIRE:
1819                 ath9k_hw_btcoex_init_2wire(ah);
1820                 break;
1821         case ATH_BTCOEX_CFG_3WIRE:
1822                 ath9k_hw_btcoex_init_3wire(ah);
1823                 r = ath_init_btcoex_timer(sc);
1824                 if (r)
1825                         goto bad2;
1826                 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1827                 ath9k_hw_init_btcoex_hw(ah, qnum);
1828                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1829                 break;
1830         default:
1831                 WARN_ON(1);
1832                 break;
1833         }
1834
1835         return 0;
1836 bad2:
1837         /* cleanup tx queues */
1838         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1839                 if (ATH_TXQ_SETUP(sc, i))
1840                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1841
1842 bad_free_hw:
1843         ath9k_uninit_hw(sc);
1844         return r;
1845 }
1846
1847 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1848 {
1849         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1850                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1851                 IEEE80211_HW_SIGNAL_DBM |
1852                 IEEE80211_HW_AMPDU_AGGREGATION |
1853                 IEEE80211_HW_SUPPORTS_PS |
1854                 IEEE80211_HW_PS_NULLFUNC_STACK |
1855                 IEEE80211_HW_SPECTRUM_MGMT;
1856
1857         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1858                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1859
1860         hw->wiphy->interface_modes =
1861                 BIT(NL80211_IFTYPE_AP) |
1862                 BIT(NL80211_IFTYPE_STATION) |
1863                 BIT(NL80211_IFTYPE_ADHOC) |
1864                 BIT(NL80211_IFTYPE_MESH_POINT);
1865
1866         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1867
1868         hw->queues = 4;
1869         hw->max_rates = 4;
1870         hw->channel_change_time = 5000;
1871         hw->max_listen_interval = 10;
1872         /* Hardware supports 10 but we use 4 */
1873         hw->max_rate_tries = 4;
1874         hw->sta_data_size = sizeof(struct ath_node);
1875         hw->vif_data_size = sizeof(struct ath_vif);
1876
1877         hw->rate_control_algorithm = "ath9k_rate_control";
1878
1879         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1880                 &sc->sbands[IEEE80211_BAND_2GHZ];
1881         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1882                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1883                         &sc->sbands[IEEE80211_BAND_5GHZ];
1884 }
1885
1886 /* Device driver core initialization */
1887 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1888                     const struct ath_bus_ops *bus_ops)
1889 {
1890         struct ieee80211_hw *hw = sc->hw;
1891         struct ath_common *common;
1892         struct ath_hw *ah;
1893         int error = 0, i;
1894         struct ath_regulatory *reg;
1895
1896         dev_dbg(sc->dev, "Attach ATH hw\n");
1897
1898         error = ath_init_softc(devid, sc, subsysid, bus_ops);
1899         if (error != 0)
1900                 return error;
1901
1902         ah = sc->sc_ah;
1903         common = ath9k_hw_common(ah);
1904
1905         /* get mac address from hardware and set in mac80211 */
1906
1907         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1908
1909         ath_set_hw_capab(sc, hw);
1910
1911         error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1912                               ath9k_reg_notifier);
1913         if (error)
1914                 return error;
1915
1916         reg = &common->regulatory;
1917
1918         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1919                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1920                 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1921                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1922         }
1923
1924         /* initialize tx/rx engine */
1925         error = ath_tx_init(sc, ATH_TXBUF);
1926         if (error != 0)
1927                 goto error_attach;
1928
1929         error = ath_rx_init(sc, ATH_RXBUF);
1930         if (error != 0)
1931                 goto error_attach;
1932
1933         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1934         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1935         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1936
1937         error = ieee80211_register_hw(hw);
1938
1939         if (!ath_is_world_regd(reg)) {
1940                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1941                 if (error)
1942                         goto error_attach;
1943         }
1944
1945         /* Initialize LED control */
1946         ath_init_leds(sc);
1947
1948         ath_start_rfkill_poll(sc);
1949
1950         return 0;
1951
1952 error_attach:
1953         /* cleanup tx queues */
1954         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1955                 if (ATH_TXQ_SETUP(sc, i))
1956                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1957
1958         ath9k_uninit_hw(sc);
1959
1960         return error;
1961 }
1962
1963 int ath_reset(struct ath_softc *sc, bool retry_tx)
1964 {
1965         struct ath_hw *ah = sc->sc_ah;
1966         struct ath_common *common = ath9k_hw_common(ah);
1967         struct ieee80211_hw *hw = sc->hw;
1968         int r;
1969
1970         ath9k_hw_set_interrupts(ah, 0);
1971         ath_drain_all_txq(sc, retry_tx);
1972         ath_stoprecv(sc);
1973         ath_flushrecv(sc);
1974
1975         spin_lock_bh(&sc->sc_resetlock);
1976         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1977         if (r)
1978                 ath_print(common, ATH_DBG_FATAL,
1979                           "Unable to reset hardware; reset status %d\n", r);
1980         spin_unlock_bh(&sc->sc_resetlock);
1981
1982         if (ath_startrecv(sc) != 0)
1983                 ath_print(common, ATH_DBG_FATAL,
1984                           "Unable to start recv logic\n");
1985
1986         /*
1987          * We may be doing a reset in response to a request
1988          * that changes the channel so update any state that
1989          * might change as a result.
1990          */
1991         ath_cache_conf_rate(sc, &hw->conf);
1992
1993         ath_update_txpow(sc);
1994
1995         if (sc->sc_flags & SC_OP_BEACONS)
1996                 ath_beacon_config(sc, NULL);    /* restart beacons */
1997
1998         ath9k_hw_set_interrupts(ah, sc->imask);
1999
2000         if (retry_tx) {
2001                 int i;
2002                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2003                         if (ATH_TXQ_SETUP(sc, i)) {
2004                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2005                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
2006                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
2007                         }
2008                 }
2009         }
2010
2011         return r;
2012 }
2013
2014 /*
2015  *  This function will allocate both the DMA descriptor structure, and the
2016  *  buffers it contains.  These are used to contain the descriptors used
2017  *  by the system.
2018 */
2019 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2020                       struct list_head *head, const char *name,
2021                       int nbuf, int ndesc)
2022 {
2023 #define DS2PHYS(_dd, _ds)                                               \
2024         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2025 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2026 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2027         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2028         struct ath_desc *ds;
2029         struct ath_buf *bf;
2030         int i, bsize, error;
2031
2032         ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2033                   name, nbuf, ndesc);
2034
2035         INIT_LIST_HEAD(head);
2036         /* ath_desc must be a multiple of DWORDs */
2037         if ((sizeof(struct ath_desc) % 4) != 0) {
2038                 ath_print(common, ATH_DBG_FATAL,
2039                           "ath_desc not DWORD aligned\n");
2040                 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
2041                 error = -ENOMEM;
2042                 goto fail;
2043         }
2044
2045         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2046
2047         /*
2048          * Need additional DMA memory because we can't use
2049          * descriptors that cross the 4K page boundary. Assume
2050          * one skipped descriptor per 4K page.
2051          */
2052         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2053                 u32 ndesc_skipped =
2054                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2055                 u32 dma_len;
2056
2057                 while (ndesc_skipped) {
2058                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
2059                         dd->dd_desc_len += dma_len;
2060
2061                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2062                 };
2063         }
2064
2065         /* allocate descriptors */
2066         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2067                                          &dd->dd_desc_paddr, GFP_KERNEL);
2068         if (dd->dd_desc == NULL) {
2069                 error = -ENOMEM;
2070                 goto fail;
2071         }
2072         ds = dd->dd_desc;
2073         ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2074                   name, ds, (u32) dd->dd_desc_len,
2075                   ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2076
2077         /* allocate buffers */
2078         bsize = sizeof(struct ath_buf) * nbuf;
2079         bf = kzalloc(bsize, GFP_KERNEL);
2080         if (bf == NULL) {
2081                 error = -ENOMEM;
2082                 goto fail2;
2083         }
2084         dd->dd_bufptr = bf;
2085
2086         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2087                 bf->bf_desc = ds;
2088                 bf->bf_daddr = DS2PHYS(dd, ds);
2089
2090                 if (!(sc->sc_ah->caps.hw_caps &
2091                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2092                         /*
2093                          * Skip descriptor addresses which can cause 4KB
2094                          * boundary crossing (addr + length) with a 32 dword
2095                          * descriptor fetch.
2096                          */
2097                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2098                                 BUG_ON((caddr_t) bf->bf_desc >=
2099                                        ((caddr_t) dd->dd_desc +
2100                                         dd->dd_desc_len));
2101
2102                                 ds += ndesc;
2103                                 bf->bf_desc = ds;
2104                                 bf->bf_daddr = DS2PHYS(dd, ds);
2105                         }
2106                 }
2107                 list_add_tail(&bf->list, head);
2108         }
2109         return 0;
2110 fail2:
2111         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2112                           dd->dd_desc_paddr);
2113 fail:
2114         memset(dd, 0, sizeof(*dd));
2115         return error;
2116 #undef ATH_DESC_4KB_BOUND_CHECK
2117 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2118 #undef DS2PHYS
2119 }
2120
2121 void ath_descdma_cleanup(struct ath_softc *sc,
2122                          struct ath_descdma *dd,
2123                          struct list_head *head)
2124 {
2125         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2126                           dd->dd_desc_paddr);
2127
2128         INIT_LIST_HEAD(head);
2129         kfree(dd->dd_bufptr);
2130         memset(dd, 0, sizeof(*dd));
2131 }
2132
2133 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2134 {
2135         int qnum;
2136
2137         switch (queue) {
2138         case 0:
2139                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2140                 break;
2141         case 1:
2142                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2143                 break;
2144         case 2:
2145                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2146                 break;
2147         case 3:
2148                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2149                 break;
2150         default:
2151                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2152                 break;
2153         }
2154
2155         return qnum;
2156 }
2157
2158 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2159 {
2160         int qnum;
2161
2162         switch (queue) {
2163         case ATH9K_WME_AC_VO:
2164                 qnum = 0;
2165                 break;
2166         case ATH9K_WME_AC_VI:
2167                 qnum = 1;
2168                 break;
2169         case ATH9K_WME_AC_BE:
2170                 qnum = 2;
2171                 break;
2172         case ATH9K_WME_AC_BK:
2173                 qnum = 3;
2174                 break;
2175         default:
2176                 qnum = -1;
2177                 break;
2178         }
2179
2180         return qnum;
2181 }
2182
2183 /* XXX: Remove me once we don't depend on ath9k_channel for all
2184  * this redundant data */
2185 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2186                            struct ath9k_channel *ichan)
2187 {
2188         struct ieee80211_channel *chan = hw->conf.channel;
2189         struct ieee80211_conf *conf = &hw->conf;
2190
2191         ichan->channel = chan->center_freq;
2192         ichan->chan = chan;
2193
2194         if (chan->band == IEEE80211_BAND_2GHZ) {
2195                 ichan->chanmode = CHANNEL_G;
2196                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2197         } else {
2198                 ichan->chanmode = CHANNEL_A;
2199                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2200         }
2201
2202         if (conf_is_ht(conf))
2203                 ichan->chanmode = ath_get_extchanmode(sc, chan,
2204                                             conf->channel_type);
2205 }
2206
2207 /**********************/
2208 /* mac80211 callbacks */
2209 /**********************/
2210
2211 /*
2212  * (Re)start btcoex timers
2213  */
2214 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2215 {
2216         struct ath_btcoex *btcoex = &sc->btcoex;
2217         struct ath_hw *ah = sc->sc_ah;
2218
2219         ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2220                   "Starting btcoex timers");
2221
2222         /* make sure duty cycle timer is also stopped when resuming */
2223         if (btcoex->hw_timer_enabled)
2224                 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2225
2226         btcoex->bt_priority_cnt = 0;
2227         btcoex->bt_priority_time = jiffies;
2228         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2229
2230         mod_timer(&btcoex->period_timer, jiffies);
2231 }
2232
2233 static int ath9k_start(struct ieee80211_hw *hw)
2234 {
2235         struct ath_wiphy *aphy = hw->priv;
2236         struct ath_softc *sc = aphy->sc;
2237         struct ath_hw *ah = sc->sc_ah;
2238         struct ath_common *common = ath9k_hw_common(ah);
2239         struct ieee80211_channel *curchan = hw->conf.channel;
2240         struct ath9k_channel *init_channel;
2241         int r;
2242
2243         ath_print(common, ATH_DBG_CONFIG,
2244                   "Starting driver with initial channel: %d MHz\n",
2245                   curchan->center_freq);
2246
2247         mutex_lock(&sc->mutex);
2248
2249         if (ath9k_wiphy_started(sc)) {
2250                 if (sc->chan_idx == curchan->hw_value) {
2251                         /*
2252                          * Already on the operational channel, the new wiphy
2253                          * can be marked active.
2254                          */
2255                         aphy->state = ATH_WIPHY_ACTIVE;
2256                         ieee80211_wake_queues(hw);
2257                 } else {
2258                         /*
2259                          * Another wiphy is on another channel, start the new
2260                          * wiphy in paused state.
2261                          */
2262                         aphy->state = ATH_WIPHY_PAUSED;
2263                         ieee80211_stop_queues(hw);
2264                 }
2265                 mutex_unlock(&sc->mutex);
2266                 return 0;
2267         }
2268         aphy->state = ATH_WIPHY_ACTIVE;
2269
2270         /* setup initial channel */
2271
2272         sc->chan_idx = curchan->hw_value;
2273
2274         init_channel = ath_get_curchannel(sc, hw);
2275
2276         /* Reset SERDES registers */
2277         ath9k_hw_configpcipowersave(ah, 0, 0);
2278
2279         /*
2280          * The basic interface to setting the hardware in a good
2281          * state is ``reset''.  On return the hardware is known to
2282          * be powered up and with interrupts disabled.  This must
2283          * be followed by initialization of the appropriate bits
2284          * and then setup of the interrupt mask.
2285          */
2286         spin_lock_bh(&sc->sc_resetlock);
2287         r = ath9k_hw_reset(ah, init_channel, false);
2288         if (r) {
2289                 ath_print(common, ATH_DBG_FATAL,
2290                           "Unable to reset hardware; reset status %d "
2291                           "(freq %u MHz)\n", r,
2292                           curchan->center_freq);
2293                 spin_unlock_bh(&sc->sc_resetlock);
2294                 goto mutex_unlock;
2295         }
2296         spin_unlock_bh(&sc->sc_resetlock);
2297
2298         /*
2299          * This is needed only to setup initial state
2300          * but it's best done after a reset.
2301          */
2302         ath_update_txpow(sc);
2303
2304         /*
2305          * Setup the hardware after reset:
2306          * The receive engine is set going.
2307          * Frame transmit is handled entirely
2308          * in the frame output path; there's nothing to do
2309          * here except setup the interrupt mask.
2310          */
2311         if (ath_startrecv(sc) != 0) {
2312                 ath_print(common, ATH_DBG_FATAL,
2313                           "Unable to start recv logic\n");
2314                 r = -EIO;
2315                 goto mutex_unlock;
2316         }
2317
2318         /* Setup our intr mask. */
2319         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2320                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2321                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2322
2323         if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2324                 sc->imask |= ATH9K_INT_GTT;
2325
2326         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2327                 sc->imask |= ATH9K_INT_CST;
2328
2329         ath_cache_conf_rate(sc, &hw->conf);
2330
2331         sc->sc_flags &= ~SC_OP_INVALID;
2332
2333         /* Disable BMISS interrupt when we're not associated */
2334         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2335         ath9k_hw_set_interrupts(ah, sc->imask);
2336
2337         ieee80211_wake_queues(hw);
2338
2339         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2340
2341         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2342             !ah->btcoex_hw.enabled) {
2343                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2344                                            AR_STOMP_LOW_WLAN_WGHT);
2345                 ath9k_hw_btcoex_enable(ah);
2346
2347                 if (common->bus_ops->bt_coex_prep)
2348                         common->bus_ops->bt_coex_prep(common);
2349                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2350                         ath9k_btcoex_timer_resume(sc);
2351         }
2352
2353 mutex_unlock:
2354         mutex_unlock(&sc->mutex);
2355
2356         return r;
2357 }
2358
2359 static int ath9k_tx(struct ieee80211_hw *hw,
2360                     struct sk_buff *skb)
2361 {
2362         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2363         struct ath_wiphy *aphy = hw->priv;
2364         struct ath_softc *sc = aphy->sc;
2365         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2366         struct ath_tx_control txctl;
2367         int hdrlen, padsize;
2368
2369         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2370                 ath_print(common, ATH_DBG_XMIT,
2371                           "ath9k: %s: TX in unexpected wiphy state "
2372                           "%d\n", wiphy_name(hw->wiphy), aphy->state);
2373                 goto exit;
2374         }
2375
2376         if (sc->ps_enabled) {
2377                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2378                 /*
2379                  * mac80211 does not set PM field for normal data frames, so we
2380                  * need to update that based on the current PS mode.
2381                  */
2382                 if (ieee80211_is_data(hdr->frame_control) &&
2383                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2384                     !ieee80211_has_pm(hdr->frame_control)) {
2385                         ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2386                                   "while in PS mode\n");
2387                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2388                 }
2389         }
2390
2391         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2392                 /*
2393                  * We are using PS-Poll and mac80211 can request TX while in
2394                  * power save mode. Need to wake up hardware for the TX to be
2395                  * completed and if needed, also for RX of buffered frames.
2396                  */
2397                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2398                 ath9k_ps_wakeup(sc);
2399                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2400                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2401                         ath_print(common, ATH_DBG_PS,
2402                                   "Sending PS-Poll to pick a buffered frame\n");
2403                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2404                 } else {
2405                         ath_print(common, ATH_DBG_PS,
2406                                   "Wake up to complete TX\n");
2407                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2408                 }
2409                 /*
2410                  * The actual restore operation will happen only after
2411                  * the sc_flags bit is cleared. We are just dropping
2412                  * the ps_usecount here.
2413                  */
2414                 ath9k_ps_restore(sc);
2415         }
2416
2417         memset(&txctl, 0, sizeof(struct ath_tx_control));
2418
2419         /*
2420          * As a temporary workaround, assign seq# here; this will likely need
2421          * to be cleaned up to work better with Beacon transmission and virtual
2422          * BSSes.
2423          */
2424         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2425                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2426                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2427                         sc->tx.seq_no += 0x10;
2428                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2429                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2430         }
2431
2432         /* Add the padding after the header if this is not already done */
2433         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2434         if (hdrlen & 3) {
2435                 padsize = hdrlen % 4;
2436                 if (skb_headroom(skb) < padsize)
2437                         return -1;
2438                 skb_push(skb, padsize);
2439                 memmove(skb->data, skb->data + padsize, hdrlen);
2440         }
2441
2442         /* Check if a tx queue is available */
2443
2444         txctl.txq = ath_test_get_txq(sc, skb);
2445         if (!txctl.txq)
2446                 goto exit;
2447
2448         ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2449
2450         if (ath_tx_start(hw, skb, &txctl) != 0) {
2451                 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2452                 goto exit;
2453         }
2454
2455         return 0;
2456 exit:
2457         dev_kfree_skb_any(skb);
2458         return 0;
2459 }
2460
2461 /*
2462  * Pause btcoex timer and bt duty cycle timer
2463  */
2464 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2465 {
2466         struct ath_btcoex *btcoex = &sc->btcoex;
2467         struct ath_hw *ah = sc->sc_ah;
2468
2469         del_timer_sync(&btcoex->period_timer);
2470
2471         if (btcoex->hw_timer_enabled)
2472                 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2473
2474         btcoex->hw_timer_enabled = false;
2475 }
2476
2477 static void ath9k_stop(struct ieee80211_hw *hw)
2478 {
2479         struct ath_wiphy *aphy = hw->priv;
2480         struct ath_softc *sc = aphy->sc;
2481         struct ath_hw *ah = sc->sc_ah;
2482         struct ath_common *common = ath9k_hw_common(ah);
2483
2484         mutex_lock(&sc->mutex);
2485
2486         aphy->state = ATH_WIPHY_INACTIVE;
2487
2488         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2489         cancel_delayed_work_sync(&sc->tx_complete_work);
2490
2491         if (!sc->num_sec_wiphy) {
2492                 cancel_delayed_work_sync(&sc->wiphy_work);
2493                 cancel_work_sync(&sc->chan_work);
2494         }
2495
2496         if (sc->sc_flags & SC_OP_INVALID) {
2497                 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2498                 mutex_unlock(&sc->mutex);
2499                 return;
2500         }
2501
2502         if (ath9k_wiphy_started(sc)) {
2503                 mutex_unlock(&sc->mutex);
2504                 return; /* another wiphy still in use */
2505         }
2506
2507         if (ah->btcoex_hw.enabled) {
2508                 ath9k_hw_btcoex_disable(ah);
2509                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2510                         ath9k_btcoex_timer_pause(sc);
2511         }
2512
2513         /* make sure h/w will not generate any interrupt
2514          * before setting the invalid flag. */
2515         ath9k_hw_set_interrupts(ah, 0);
2516
2517         if (!(sc->sc_flags & SC_OP_INVALID)) {
2518                 ath_drain_all_txq(sc, false);
2519                 ath_stoprecv(sc);
2520                 ath9k_hw_phy_disable(ah);
2521         } else
2522                 sc->rx.rxlink = NULL;
2523
2524         /* disable HAL and put h/w to sleep */
2525         ath9k_hw_disable(ah);
2526         ath9k_hw_configpcipowersave(ah, 1, 1);
2527         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2528
2529         sc->sc_flags |= SC_OP_INVALID;
2530
2531         mutex_unlock(&sc->mutex);
2532
2533         ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2534 }
2535
2536 static int ath9k_add_interface(struct ieee80211_hw *hw,
2537                                struct ieee80211_if_init_conf *conf)
2538 {
2539         struct ath_wiphy *aphy = hw->priv;
2540         struct ath_softc *sc = aphy->sc;
2541         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2542         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2543         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2544         int ret = 0;
2545
2546         mutex_lock(&sc->mutex);
2547
2548         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2549             sc->nvifs > 0) {
2550                 ret = -ENOBUFS;
2551                 goto out;
2552         }
2553
2554         switch (conf->type) {
2555         case NL80211_IFTYPE_STATION:
2556                 ic_opmode = NL80211_IFTYPE_STATION;
2557                 break;
2558         case NL80211_IFTYPE_ADHOC:
2559         case NL80211_IFTYPE_AP:
2560         case NL80211_IFTYPE_MESH_POINT:
2561                 if (sc->nbcnvifs >= ATH_BCBUF) {
2562                         ret = -ENOBUFS;
2563                         goto out;
2564                 }
2565                 ic_opmode = conf->type;
2566                 break;
2567         default:
2568                 ath_print(common, ATH_DBG_FATAL,
2569                         "Interface type %d not yet supported\n", conf->type);
2570                 ret = -EOPNOTSUPP;
2571                 goto out;
2572         }
2573
2574         ath_print(common, ATH_DBG_CONFIG,
2575                   "Attach a VIF of type: %d\n", ic_opmode);
2576
2577         /* Set the VIF opmode */
2578         avp->av_opmode = ic_opmode;
2579         avp->av_bslot = -1;
2580
2581         sc->nvifs++;
2582
2583         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2584                 ath9k_set_bssid_mask(hw);
2585
2586         if (sc->nvifs > 1)
2587                 goto out; /* skip global settings for secondary vif */
2588
2589         if (ic_opmode == NL80211_IFTYPE_AP) {
2590                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2591                 sc->sc_flags |= SC_OP_TSF_RESET;
2592         }
2593
2594         /* Set the device opmode */
2595         sc->sc_ah->opmode = ic_opmode;
2596
2597         /*
2598          * Enable MIB interrupts when there are hardware phy counters.
2599          * Note we only do this (at the moment) for station mode.
2600          */
2601         if ((conf->type == NL80211_IFTYPE_STATION) ||
2602             (conf->type == NL80211_IFTYPE_ADHOC) ||
2603             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2604                 sc->imask |= ATH9K_INT_MIB;
2605                 sc->imask |= ATH9K_INT_TSFOOR;
2606         }
2607
2608         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2609
2610         if (conf->type == NL80211_IFTYPE_AP    ||
2611             conf->type == NL80211_IFTYPE_ADHOC ||
2612             conf->type == NL80211_IFTYPE_MONITOR)
2613                 ath_start_ani(common);
2614
2615 out:
2616         mutex_unlock(&sc->mutex);
2617         return ret;
2618 }
2619
2620 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2621                                    struct ieee80211_if_init_conf *conf)
2622 {
2623         struct ath_wiphy *aphy = hw->priv;
2624         struct ath_softc *sc = aphy->sc;
2625         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2626         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2627         int i;
2628
2629         ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2630
2631         mutex_lock(&sc->mutex);
2632
2633         /* Stop ANI */
2634         del_timer_sync(&common->ani.timer);
2635
2636         /* Reclaim beacon resources */
2637         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2638             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2639             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2640                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2641                 ath_beacon_return(sc, avp);
2642         }
2643
2644         sc->sc_flags &= ~SC_OP_BEACONS;
2645
2646         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2647                 if (sc->beacon.bslot[i] == conf->vif) {
2648                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2649                                "slot\n", __func__);
2650                         sc->beacon.bslot[i] = NULL;
2651                         sc->beacon.bslot_aphy[i] = NULL;
2652                 }
2653         }
2654
2655         sc->nvifs--;
2656
2657         mutex_unlock(&sc->mutex);
2658 }
2659
2660 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2661 {
2662         struct ath_wiphy *aphy = hw->priv;
2663         struct ath_softc *sc = aphy->sc;
2664         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2665         struct ieee80211_conf *conf = &hw->conf;
2666         struct ath_hw *ah = sc->sc_ah;
2667         bool disable_radio;
2668
2669         mutex_lock(&sc->mutex);
2670
2671         /*
2672          * Leave this as the first check because we need to turn on the
2673          * radio if it was disabled before prior to processing the rest
2674          * of the changes. Likewise we must only disable the radio towards
2675          * the end.
2676          */
2677         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2678                 bool enable_radio;
2679                 bool all_wiphys_idle;
2680                 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
2681
2682                 spin_lock_bh(&sc->wiphy_lock);
2683                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2684                 ath9k_set_wiphy_idle(aphy, idle);
2685
2686                 if (!idle && all_wiphys_idle)
2687                         enable_radio = true;
2688
2689                 /*
2690                  * After we unlock here its possible another wiphy
2691                  * can be re-renabled so to account for that we will
2692                  * only disable the radio toward the end of this routine
2693                  * if by then all wiphys are still idle.
2694                  */
2695                 spin_unlock_bh(&sc->wiphy_lock);
2696
2697                 if (enable_radio) {
2698                         ath_radio_enable(sc, hw);
2699                         ath_print(common, ATH_DBG_CONFIG,
2700                                   "not-idle: enabling radio\n");
2701                 }
2702         }
2703
2704         /*
2705          * We just prepare to enable PS. We have to wait until our AP has
2706          * ACK'd our null data frame to disable RX otherwise we'll ignore
2707          * those ACKs and end up retransmitting the same null data frames.
2708          * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
2709          */
2710         if (changed & IEEE80211_CONF_CHANGE_PS) {
2711                 if (conf->flags & IEEE80211_CONF_PS) {
2712                         sc->sc_flags |= SC_OP_PS_ENABLED;
2713                         if (!(ah->caps.hw_caps &
2714                               ATH9K_HW_CAP_AUTOSLEEP)) {
2715                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2716                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2717                                         ath9k_hw_set_interrupts(sc->sc_ah,
2718                                                         sc->imask);
2719                                 }
2720                         }
2721                         /*
2722                          * At this point we know hardware has received an ACK
2723                          * of a previously sent null data frame.
2724                          */
2725                         if ((sc->sc_flags & SC_OP_NULLFUNC_COMPLETED)) {
2726                                 sc->sc_flags &= ~SC_OP_NULLFUNC_COMPLETED;
2727                                 sc->ps_enabled = true;
2728                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2729                         }
2730                 } else {
2731                         sc->ps_enabled = false;
2732                         sc->sc_flags &= ~(SC_OP_PS_ENABLED |
2733                                           SC_OP_NULLFUNC_COMPLETED);
2734                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
2735                         if (!(ah->caps.hw_caps &
2736                               ATH9K_HW_CAP_AUTOSLEEP)) {
2737                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2738                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2739                                                   SC_OP_WAIT_FOR_CAB |
2740                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2741                                                   SC_OP_WAIT_FOR_TX_ACK);
2742                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2743                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2744                                         ath9k_hw_set_interrupts(sc->sc_ah,
2745                                                         sc->imask);
2746                                 }
2747                         }
2748                 }
2749         }
2750
2751         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2752                 struct ieee80211_channel *curchan = hw->conf.channel;
2753                 int pos = curchan->hw_value;
2754
2755                 aphy->chan_idx = pos;
2756                 aphy->chan_is_ht = conf_is_ht(conf);
2757
2758                 if (aphy->state == ATH_WIPHY_SCAN ||
2759                     aphy->state == ATH_WIPHY_ACTIVE)
2760                         ath9k_wiphy_pause_all_forced(sc, aphy);
2761                 else {
2762                         /*
2763                          * Do not change operational channel based on a paused
2764                          * wiphy changes.
2765                          */
2766                         goto skip_chan_change;
2767                 }
2768
2769                 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2770                           curchan->center_freq);
2771
2772                 /* XXX: remove me eventualy */
2773                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2774
2775                 ath_update_chainmask(sc, conf_is_ht(conf));
2776
2777                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2778                         ath_print(common, ATH_DBG_FATAL,
2779                                   "Unable to set channel\n");
2780                         mutex_unlock(&sc->mutex);
2781                         return -EINVAL;
2782                 }
2783         }
2784
2785 skip_chan_change:
2786         if (changed & IEEE80211_CONF_CHANGE_POWER)
2787                 sc->config.txpowlimit = 2 * conf->power_level;
2788
2789         spin_lock_bh(&sc->wiphy_lock);
2790         disable_radio = ath9k_all_wiphys_idle(sc);
2791         spin_unlock_bh(&sc->wiphy_lock);
2792
2793         if (disable_radio) {
2794                 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2795                 ath_radio_disable(sc, hw);
2796         }
2797
2798         mutex_unlock(&sc->mutex);
2799
2800         return 0;
2801 }
2802
2803 #define SUPPORTED_FILTERS                       \
2804         (FIF_PROMISC_IN_BSS |                   \
2805         FIF_ALLMULTI |                          \
2806         FIF_CONTROL |                           \
2807         FIF_PSPOLL |                            \
2808         FIF_OTHER_BSS |                         \
2809         FIF_BCN_PRBRESP_PROMISC |               \
2810         FIF_FCSFAIL)
2811
2812 /* FIXME: sc->sc_full_reset ? */
2813 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2814                                    unsigned int changed_flags,
2815                                    unsigned int *total_flags,
2816                                    u64 multicast)
2817 {
2818         struct ath_wiphy *aphy = hw->priv;
2819         struct ath_softc *sc = aphy->sc;
2820         u32 rfilt;
2821
2822         changed_flags &= SUPPORTED_FILTERS;
2823         *total_flags &= SUPPORTED_FILTERS;
2824
2825         sc->rx.rxfilter = *total_flags;
2826         ath9k_ps_wakeup(sc);
2827         rfilt = ath_calcrxfilter(sc);
2828         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2829         ath9k_ps_restore(sc);
2830
2831         ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2832                   "Set HW RX filter: 0x%x\n", rfilt);
2833 }
2834
2835 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2836                              struct ieee80211_vif *vif,
2837                              enum sta_notify_cmd cmd,
2838                              struct ieee80211_sta *sta)
2839 {
2840         struct ath_wiphy *aphy = hw->priv;
2841         struct ath_softc *sc = aphy->sc;
2842
2843         switch (cmd) {
2844         case STA_NOTIFY_ADD:
2845                 ath_node_attach(sc, sta);
2846                 break;
2847         case STA_NOTIFY_REMOVE:
2848                 ath_node_detach(sc, sta);
2849                 break;
2850         default:
2851                 break;
2852         }
2853 }
2854
2855 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2856                          const struct ieee80211_tx_queue_params *params)
2857 {
2858         struct ath_wiphy *aphy = hw->priv;
2859         struct ath_softc *sc = aphy->sc;
2860         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2861         struct ath9k_tx_queue_info qi;
2862         int ret = 0, qnum;
2863
2864         if (queue >= WME_NUM_AC)
2865                 return 0;
2866
2867         mutex_lock(&sc->mutex);
2868
2869         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2870
2871         qi.tqi_aifs = params->aifs;
2872         qi.tqi_cwmin = params->cw_min;
2873         qi.tqi_cwmax = params->cw_max;
2874         qi.tqi_burstTime = params->txop;
2875         qnum = ath_get_hal_qnum(queue, sc);
2876
2877         ath_print(common, ATH_DBG_CONFIG,
2878                   "Configure tx [queue/halq] [%d/%d],  "
2879                   "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2880                   queue, qnum, params->aifs, params->cw_min,
2881                   params->cw_max, params->txop);
2882
2883         ret = ath_txq_update(sc, qnum, &qi);
2884         if (ret)
2885                 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2886
2887         mutex_unlock(&sc->mutex);
2888
2889         return ret;
2890 }
2891
2892 static int ath9k_set_key(struct ieee80211_hw *hw,
2893                          enum set_key_cmd cmd,
2894                          struct ieee80211_vif *vif,
2895                          struct ieee80211_sta *sta,
2896                          struct ieee80211_key_conf *key)
2897 {
2898         struct ath_wiphy *aphy = hw->priv;
2899         struct ath_softc *sc = aphy->sc;
2900         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2901         int ret = 0;
2902
2903         if (modparam_nohwcrypt)
2904                 return -ENOSPC;
2905
2906         mutex_lock(&sc->mutex);
2907         ath9k_ps_wakeup(sc);
2908         ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2909
2910         switch (cmd) {
2911         case SET_KEY:
2912                 ret = ath_key_config(common, vif, sta, key);
2913                 if (ret >= 0) {
2914                         key->hw_key_idx = ret;
2915                         /* push IV and Michael MIC generation to stack */
2916                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2917                         if (key->alg == ALG_TKIP)
2918                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2919                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2920                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2921                         ret = 0;
2922                 }
2923                 break;
2924         case DISABLE_KEY:
2925                 ath_key_delete(common, key);
2926                 break;
2927         default:
2928                 ret = -EINVAL;
2929         }
2930
2931         ath9k_ps_restore(sc);
2932         mutex_unlock(&sc->mutex);
2933
2934         return ret;
2935 }
2936
2937 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2938                                    struct ieee80211_vif *vif,
2939                                    struct ieee80211_bss_conf *bss_conf,
2940                                    u32 changed)
2941 {
2942         struct ath_wiphy *aphy = hw->priv;
2943         struct ath_softc *sc = aphy->sc;
2944         struct ath_hw *ah = sc->sc_ah;
2945         struct ath_common *common = ath9k_hw_common(ah);
2946         struct ath_vif *avp = (void *)vif->drv_priv;
2947         int error;
2948
2949         mutex_lock(&sc->mutex);
2950
2951         if (changed & BSS_CHANGED_BSSID) {
2952                 /* Set BSSID */
2953                 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2954                 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2955                 common->curaid = 0;
2956                 ath9k_hw_write_associd(ah);
2957
2958                 /* Set aggregation protection mode parameters */
2959                 sc->config.ath_aggr_prot = 0;
2960
2961                 /* Only legacy IBSS for now */
2962                 if (vif->type == NL80211_IFTYPE_ADHOC)
2963                         ath_update_chainmask(sc, 0);
2964
2965                 ath_print(common, ATH_DBG_CONFIG,
2966                           "BSSID: %pM aid: 0x%x\n",
2967                           common->curbssid, common->curaid);
2968
2969                 /* need to reconfigure the beacon */
2970                 sc->sc_flags &= ~SC_OP_BEACONS ;
2971         }
2972
2973         /* Enable transmission of beacons (AP, IBSS, MESH) */
2974         if ((changed & BSS_CHANGED_BEACON) ||
2975             ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2976                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2977                 error = ath_beacon_alloc(aphy, vif);
2978                 if (!error)
2979                         ath_beacon_config(sc, vif);
2980         }
2981
2982         /* Disable transmission of beacons */
2983         if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
2984                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2985
2986         if (changed & BSS_CHANGED_BEACON_INT) {
2987                 sc->beacon_interval = bss_conf->beacon_int;
2988                 /*
2989                  * In case of AP mode, the HW TSF has to be reset
2990                  * when the beacon interval changes.
2991                  */
2992                 if (vif->type == NL80211_IFTYPE_AP) {
2993                         sc->sc_flags |= SC_OP_TSF_RESET;
2994                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2995                         error = ath_beacon_alloc(aphy, vif);
2996                         if (!error)
2997                                 ath_beacon_config(sc, vif);
2998                 } else {
2999                         ath_beacon_config(sc, vif);
3000                 }
3001         }
3002
3003         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3004                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3005                           bss_conf->use_short_preamble);
3006                 if (bss_conf->use_short_preamble)
3007                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3008                 else
3009                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3010         }
3011
3012         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
3013                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3014                           bss_conf->use_cts_prot);
3015                 if (bss_conf->use_cts_prot &&
3016                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3017                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3018                 else
3019                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3020         }
3021
3022         if (changed & BSS_CHANGED_ASSOC) {
3023                 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
3024                         bss_conf->assoc);
3025                 ath9k_bss_assoc_info(sc, vif, bss_conf);
3026         }
3027
3028         mutex_unlock(&sc->mutex);
3029 }
3030
3031 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3032 {
3033         u64 tsf;
3034         struct ath_wiphy *aphy = hw->priv;
3035         struct ath_softc *sc = aphy->sc;
3036
3037         mutex_lock(&sc->mutex);
3038         tsf = ath9k_hw_gettsf64(sc->sc_ah);
3039         mutex_unlock(&sc->mutex);
3040
3041         return tsf;
3042 }
3043
3044 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3045 {
3046         struct ath_wiphy *aphy = hw->priv;
3047         struct ath_softc *sc = aphy->sc;
3048
3049         mutex_lock(&sc->mutex);
3050         ath9k_hw_settsf64(sc->sc_ah, tsf);
3051         mutex_unlock(&sc->mutex);
3052 }
3053
3054 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3055 {
3056         struct ath_wiphy *aphy = hw->priv;
3057         struct ath_softc *sc = aphy->sc;
3058
3059         mutex_lock(&sc->mutex);
3060
3061         ath9k_ps_wakeup(sc);
3062         ath9k_hw_reset_tsf(sc->sc_ah);
3063         ath9k_ps_restore(sc);
3064
3065         mutex_unlock(&sc->mutex);
3066 }
3067
3068 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3069                               struct ieee80211_vif *vif,
3070                               enum ieee80211_ampdu_mlme_action action,
3071                               struct ieee80211_sta *sta,
3072                               u16 tid, u16 *ssn)
3073 {
3074         struct ath_wiphy *aphy = hw->priv;
3075         struct ath_softc *sc = aphy->sc;
3076         int ret = 0;
3077
3078         switch (action) {
3079         case IEEE80211_AMPDU_RX_START:
3080                 if (!(sc->sc_flags & SC_OP_RXAGGR))
3081                         ret = -ENOTSUPP;
3082                 break;
3083         case IEEE80211_AMPDU_RX_STOP:
3084                 break;
3085         case IEEE80211_AMPDU_TX_START:
3086                 ath_tx_aggr_start(sc, sta, tid, ssn);
3087                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3088                 break;
3089         case IEEE80211_AMPDU_TX_STOP:
3090                 ath_tx_aggr_stop(sc, sta, tid);
3091                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3092                 break;
3093         case IEEE80211_AMPDU_TX_OPERATIONAL:
3094                 ath_tx_aggr_resume(sc, sta, tid);
3095                 break;
3096         default:
3097                 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3098                           "Unknown AMPDU action\n");
3099         }
3100
3101         return ret;
3102 }
3103
3104 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3105 {
3106         struct ath_wiphy *aphy = hw->priv;
3107         struct ath_softc *sc = aphy->sc;
3108
3109         mutex_lock(&sc->mutex);
3110         if (ath9k_wiphy_scanning(sc)) {
3111                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3112                        "same time\n");
3113                 /*
3114                  * Do not allow the concurrent scanning state for now. This
3115                  * could be improved with scanning control moved into ath9k.
3116                  */
3117                 mutex_unlock(&sc->mutex);
3118                 return;
3119         }
3120
3121         aphy->state = ATH_WIPHY_SCAN;
3122         ath9k_wiphy_pause_all_forced(sc, aphy);
3123
3124         spin_lock_bh(&sc->ani_lock);
3125         sc->sc_flags |= SC_OP_SCANNING;
3126         spin_unlock_bh(&sc->ani_lock);
3127         mutex_unlock(&sc->mutex);
3128 }
3129
3130 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3131 {
3132         struct ath_wiphy *aphy = hw->priv;
3133         struct ath_softc *sc = aphy->sc;
3134
3135         mutex_lock(&sc->mutex);
3136         spin_lock_bh(&sc->ani_lock);
3137         aphy->state = ATH_WIPHY_ACTIVE;
3138         sc->sc_flags &= ~SC_OP_SCANNING;
3139         sc->sc_flags |= SC_OP_FULL_RESET;
3140         spin_unlock_bh(&sc->ani_lock);
3141         ath_beacon_config(sc, NULL);
3142         mutex_unlock(&sc->mutex);
3143 }
3144
3145 struct ieee80211_ops ath9k_ops = {
3146         .tx                 = ath9k_tx,
3147         .start              = ath9k_start,
3148         .stop               = ath9k_stop,
3149         .add_interface      = ath9k_add_interface,
3150         .remove_interface   = ath9k_remove_interface,
3151         .config             = ath9k_config,
3152         .configure_filter   = ath9k_configure_filter,
3153         .sta_notify         = ath9k_sta_notify,
3154         .conf_tx            = ath9k_conf_tx,
3155         .bss_info_changed   = ath9k_bss_info_changed,
3156         .set_key            = ath9k_set_key,
3157         .get_tsf            = ath9k_get_tsf,
3158         .set_tsf            = ath9k_set_tsf,
3159         .reset_tsf          = ath9k_reset_tsf,
3160         .ampdu_action       = ath9k_ampdu_action,
3161         .sw_scan_start      = ath9k_sw_scan_start,
3162         .sw_scan_complete   = ath9k_sw_scan_complete,
3163         .rfkill_poll        = ath9k_rfkill_poll_state,
3164 };
3165
3166 static int __init ath9k_init(void)
3167 {
3168         int error;
3169
3170         /* Register rate control algorithm */
3171         error = ath_rate_control_register();
3172         if (error != 0) {
3173                 printk(KERN_ERR
3174                         "ath9k: Unable to register rate control "
3175                         "algorithm: %d\n",
3176                         error);
3177                 goto err_out;
3178         }
3179
3180         error = ath9k_debug_create_root();
3181         if (error) {
3182                 printk(KERN_ERR
3183                         "ath9k: Unable to create debugfs root: %d\n",
3184                         error);
3185                 goto err_rate_unregister;
3186         }
3187
3188         error = ath_pci_init();
3189         if (error < 0) {
3190                 printk(KERN_ERR
3191                         "ath9k: No PCI devices found, driver not installed.\n");
3192                 error = -ENODEV;
3193                 goto err_remove_root;
3194         }
3195
3196         error = ath_ahb_init();
3197         if (error < 0) {
3198                 error = -ENODEV;
3199                 goto err_pci_exit;
3200         }
3201
3202         return 0;
3203
3204  err_pci_exit:
3205         ath_pci_exit();
3206
3207  err_remove_root:
3208         ath9k_debug_remove_root();
3209  err_rate_unregister:
3210         ath_rate_control_unregister();
3211  err_out:
3212         return error;
3213 }
3214 module_init(ath9k_init);
3215
3216 static void __exit ath9k_exit(void)
3217 {
3218         ath_ahb_exit();
3219         ath_pci_exit();
3220         ath9k_debug_remove_root();
3221         ath_rate_control_unregister();
3222         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3223 }
3224 module_exit(ath9k_exit);