drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 static int modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  32
  33 /* We use the hw_value as an index into our private channel structure */
  34
  35 #define CHAN2G(_freq, _idx)  { \
  36         .center_freq = (_freq), \
  37         .hw_value = (_idx), \
  38         .max_power = 20, \
  39 }
  40
  41 #define CHAN5G(_freq, _idx) { \
  42         .band = IEEE80211_BAND_5GHZ, \
  43         .center_freq = (_freq), \
  44         .hw_value = (_idx), \
  45         .max_power = 20, \
  46 }
  47
  48 /* Some 2 GHz radios are actually tunable on 2312-2732
  49  * on 5 MHz steps, we support the channels which we know
  50  * we have calibration data for all cards though to make
  51  * this static */
  52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  53         CHAN2G(2412, 0), /* Channel 1 */
  54         CHAN2G(2417, 1), /* Channel 2 */
  55         CHAN2G(2422, 2), /* Channel 3 */
  56         CHAN2G(2427, 3), /* Channel 4 */
  57         CHAN2G(2432, 4), /* Channel 5 */
  58         CHAN2G(2437, 5), /* Channel 6 */
  59         CHAN2G(2442, 6), /* Channel 7 */
  60         CHAN2G(2447, 7), /* Channel 8 */
  61         CHAN2G(2452, 8), /* Channel 9 */
  62         CHAN2G(2457, 9), /* Channel 10 */
  63         CHAN2G(2462, 10), /* Channel 11 */
  64         CHAN2G(2467, 11), /* Channel 12 */
  65         CHAN2G(2472, 12), /* Channel 13 */
  66         CHAN2G(2484, 13), /* Channel 14 */
  67 };
  68
  69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  70  * on 5 MHz steps, we support the channels which we know
  71  * we have calibration data for all cards though to make
  72  * this static */
  73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  74         /* _We_ call this UNII 1 */
  75         CHAN5G(5180, 14), /* Channel 36 */
  76         CHAN5G(5200, 15), /* Channel 40 */
  77         CHAN5G(5220, 16), /* Channel 44 */
  78         CHAN5G(5240, 17), /* Channel 48 */
  79         /* _We_ call this UNII 2 */
  80         CHAN5G(5260, 18), /* Channel 52 */
  81         CHAN5G(5280, 19), /* Channel 56 */
  82         CHAN5G(5300, 20), /* Channel 60 */
  83         CHAN5G(5320, 21), /* Channel 64 */
  84         /* _We_ call this "Middle band" */
  85         CHAN5G(5500, 22), /* Channel 100 */
  86         CHAN5G(5520, 23), /* Channel 104 */
  87         CHAN5G(5540, 24), /* Channel 108 */
  88         CHAN5G(5560, 25), /* Channel 112 */
  89         CHAN5G(5580, 26), /* Channel 116 */
  90         CHAN5G(5600, 27), /* Channel 120 */
  91         CHAN5G(5620, 28), /* Channel 124 */
  92         CHAN5G(5640, 29), /* Channel 128 */
  93         CHAN5G(5660, 30), /* Channel 132 */
  94         CHAN5G(5680, 31), /* Channel 136 */
  95         CHAN5G(5700, 32), /* Channel 140 */
  96         /* _We_ call this UNII 3 */
  97         CHAN5G(5745, 33), /* Channel 149 */
  98         CHAN5G(5765, 34), /* Channel 153 */
  99         CHAN5G(5785, 35), /* Channel 157 */
 100         CHAN5G(5805, 36), /* Channel 161 */
 101         CHAN5G(5825, 37), /* Channel 165 */
 102 };
 103
 104 static void ath_cache_conf_rate(struct ath_softc *sc,
 105                                 struct ieee80211_conf *conf)
 106 {
 107         switch (conf->channel->band) {
 108         case IEEE80211_BAND_2GHZ:
 109                 if (conf_is_ht20(conf))
 110                         sc->cur_rate_table =
 111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 112                 else if (conf_is_ht40_minus(conf))
 113                         sc->cur_rate_table =
 114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 115                 else if (conf_is_ht40_plus(conf))
 116                         sc->cur_rate_table =
 117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 118                 else
 119                         sc->cur_rate_table =
 120                           sc->hw_rate_table[ATH9K_MODE_11G];
 121                 break;
 122         case IEEE80211_BAND_5GHZ:
 123                 if (conf_is_ht20(conf))
 124                         sc->cur_rate_table =
 125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 126                 else if (conf_is_ht40_minus(conf))
 127                         sc->cur_rate_table =
 128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 129                 else if (conf_is_ht40_plus(conf))
 130                         sc->cur_rate_table =
 131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 132                 else
 133                         sc->cur_rate_table =
 134                           sc->hw_rate_table[ATH9K_MODE_11A];
 135                 break;
 136         default:
 137                 BUG_ON(1);
 138                 break;
 139         }
 140 }
 141
 142 static void ath_update_txpow(struct ath_softc *sc)
 143 {
 144         struct ath_hw *ah = sc->sc_ah;
 145         u32 txpow;
 146
 147         if (sc->curtxpow != sc->config.txpowlimit) {
 148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 149                 /* read back in case value is clamped */
 150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 151                 sc->curtxpow = txpow;
 152         }
 153 }
 154
 155 static u8 parse_mpdudensity(u8 mpdudensity)
 156 {
 157         /*
 158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 159          *   0 for no restriction
 160          *   1 for 1/4 us
 161          *   2 for 1/2 us
 162          *   3 for 1 us
 163          *   4 for 2 us
 164          *   5 for 4 us
 165          *   6 for 8 us
 166          *   7 for 16 us
 167          */
 168         switch (mpdudensity) {
 169         case 0:
 170                 return 0;
 171         case 1:
 172         case 2:
 173         case 3:
 174                 /* Our lower layer calculations limit our precision to
 175                    1 microsecond */
 176                 return 1;
 177         case 4:
 178                 return 2;
 179         case 5:
 180                 return 4;
 181         case 6:
 182                 return 8;
 183         case 7:
 184                 return 16;
 185         default:
 186                 return 0;
 187         }
 188 }
 189
 190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 191 {
 192         const struct ath_rate_table *rate_table = NULL;
 193         struct ieee80211_supported_band *sband;
 194         struct ieee80211_rate *rate;
 195         int i, maxrates;
 196
 197         switch (band) {
 198         case IEEE80211_BAND_2GHZ:
 199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 200                 break;
 201         case IEEE80211_BAND_5GHZ:
 202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 203                 break;
 204         default:
 205                 break;
 206         }
 207
 208         if (rate_table == NULL)
 209                 return;
 210
 211         sband = &sc->sbands[band];
 212         rate = sc->rates[band];
 213
 214         if (rate_table->rate_cnt > ATH_RATE_MAX)
 215                 maxrates = ATH_RATE_MAX;
 216         else
 217                 maxrates = rate_table->rate_cnt;
 218
 219         for (i = 0; i < maxrates; i++) {
 220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 221                 rate[i].hw_value = rate_table->info[i].ratecode;
 222                 if (rate_table->info[i].short_preamble) {
 223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 224                                 rate_table->info[i].short_preamble;
 225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 226                 }
 227                 sband->n_bitrates++;
 228
 229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 230                         rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 /*
 235  * Set/change channels.  If the channel is really being changed, it's done
 236  * by reseting the chip.  To accomplish this we must first cleanup any pending
 237  * DMA, then restart stuff.
 238 */
 239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 240                     struct ath9k_channel *hchan)
 241 {
 242         struct ath_hw *ah = sc->sc_ah;
 243         bool fastcc = true, stopped;
 244         struct ieee80211_channel *channel = hw->conf.channel;
 245         int r;
 246
 247         if (sc->sc_flags & SC_OP_INVALID)
 248                 return -EIO;
 249
 250         ath9k_ps_wakeup(sc);
 251
 252         /*
 253          * This is only performed if the channel settings have
 254          * actually changed.
 255          *
 256          * To switch channels clear any pending DMA operations;
 257          * wait long enough for the RX fifo to drain, reset the
 258          * hardware at the new frequency, and then re-enable
 259          * the relevant bits of the h/w.
 260          */
 261         ath9k_hw_set_interrupts(ah, 0);
 262         ath_drain_all_txq(sc, false);
 263         stopped = ath_stoprecv(sc);
 264
 265         /* XXX: do not flush receive queue here. We don't want
 266          * to flush data frames already in queue because of
 267          * changing channel. */
 268
 269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 270                 fastcc = false;
 271
 272         DPRINTF(sc, ATH_DBG_CONFIG,
 273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 274                 sc->sc_ah->curchan->channel,
 275                 channel->center_freq, sc->tx_chan_width);
 276
 277         spin_lock_bh(&sc->sc_resetlock);
 278
 279         r = ath9k_hw_reset(ah, hchan, fastcc);
 280         if (r) {
 281                 DPRINTF(sc, ATH_DBG_FATAL,
 282                         "Unable to reset channel (%u Mhz) "
 283                         "reset status %d\n",
 284                         channel->center_freq, r);
 285                 spin_unlock_bh(&sc->sc_resetlock);
 286                 return r;
 287         }
 288         spin_unlock_bh(&sc->sc_resetlock);
 289
 290         sc->sc_flags &= ~SC_OP_FULL_RESET;
 291
 292         if (ath_startrecv(sc) != 0) {
 293                 DPRINTF(sc, ATH_DBG_FATAL,
 294                         "Unable to restart recv logic\n");
 295                 return -EIO;
 296         }
 297
 298         ath_cache_conf_rate(sc, &hw->conf);
 299         ath_update_txpow(sc);
 300         ath9k_hw_set_interrupts(ah, sc->imask);
 301         ath9k_ps_restore(sc);
 302         return 0;
 303 }
 304
 305 /*
 306  *  This routine performs the periodic noise floor calibration function
 307  *  that is used to adjust and optimize the chip performance.  This
 308  *  takes environmental changes (location, temperature) into account.
 309  *  When the task is complete, it reschedules itself depending on the
 310  *  appropriate interval that was calculated.
 311  */
 312 static void ath_ani_calibrate(unsigned long data)
 313 {
 314         struct ath_softc *sc = (struct ath_softc *)data;
 315         struct ath_hw *ah = sc->sc_ah;
 316         bool longcal = false;
 317         bool shortcal = false;
 318         bool aniflag = false;
 319         unsigned int timestamp = jiffies_to_msecs(jiffies);
 320         u32 cal_interval, short_cal_interval;
 321
 322         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 323                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 324
 325         /*
 326         * don't calibrate when we're scanning.
 327         * we are most likely not on our home channel.
 328         */
 329         if (sc->sc_flags & SC_OP_SCANNING)
 330                 goto set_timer;
 331
 332         /* Only calibrate if awake */
 333         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 334                 goto set_timer;
 335
 336         ath9k_ps_wakeup(sc);
 337
 338         /* Long calibration runs independently of short calibration. */
 339         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 340                 longcal = true;
 341                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 342                 sc->ani.longcal_timer = timestamp;
 343         }
 344
 345         /* Short calibration applies only while caldone is false */
 346         if (!sc->ani.caldone) {
 347                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 348                         shortcal = true;
 349                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 350                         sc->ani.shortcal_timer = timestamp;
 351                         sc->ani.resetcal_timer = timestamp;
 352                 }
 353         } else {
 354                 if ((timestamp - sc->ani.resetcal_timer) >=
 355                     ATH_RESTART_CALINTERVAL) {
 356                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 357                         if (sc->ani.caldone)
 358                                 sc->ani.resetcal_timer = timestamp;
 359                 }
 360         }
 361
 362         /* Verify whether we must check ANI */
 363         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 364                 aniflag = true;
 365                 sc->ani.checkani_timer = timestamp;
 366         }
 367
 368         /* Skip all processing if there's nothing to do. */
 369         if (longcal || shortcal || aniflag) {
 370                 /* Call ANI routine if necessary */
 371                 if (aniflag)
 372                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 373
 374                 /* Perform calibration if necessary */
 375                 if (longcal || shortcal) {
 376                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
 377                                                      sc->rx_chainmask, longcal);
 378
 379                         if (longcal)
 380                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 381                                                                      ah->curchan);
 382
 383                         DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
 384                                 ah->curchan->channel, ah->curchan->channelFlags,
 385                                 sc->ani.noise_floor);
 386                 }
 387         }
 388
 389         ath9k_ps_restore(sc);
 390
 391 set_timer:
 392         /*
 393         * Set timer interval based on previous results.
 394         * The interval must be the shortest necessary to satisfy ANI,
 395         * short calibration and long calibration.
 396         */
 397         cal_interval = ATH_LONG_CALINTERVAL;
 398         if (sc->sc_ah->config.enable_ani)
 399                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 400         if (!sc->ani.caldone)
 401                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 402
 403         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 404 }
 405
 406 static void ath_start_ani(struct ath_softc *sc)
 407 {
 408         unsigned long timestamp = jiffies_to_msecs(jiffies);
 409
 410         sc->ani.longcal_timer = timestamp;
 411         sc->ani.shortcal_timer = timestamp;
 412         sc->ani.checkani_timer = timestamp;
 413
 414         mod_timer(&sc->ani.timer,
 415                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 416 }
 417
 418 /*
 419  * Update tx/rx chainmask. For legacy association,
 420  * hard code chainmask to 1x1, for 11n association, use
 421  * the chainmask configuration, for bt coexistence, use
 422  * the chainmask configuration even in legacy mode.
 423  */
 424 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 425 {
 426         if (is_ht ||
 427             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 428                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 429                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 430         } else {
 431                 sc->tx_chainmask = 1;
 432                 sc->rx_chainmask = 1;
 433         }
 434
 435         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 436                 sc->tx_chainmask, sc->rx_chainmask);
 437 }
 438
 439 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 440 {
 441         struct ath_node *an;
 442
 443         an = (struct ath_node *)sta->drv_priv;
 444
 445         if (sc->sc_flags & SC_OP_TXAGGR) {
 446                 ath_tx_node_init(sc, an);
 447                 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 448                                      sta->ht_cap.ampdu_factor);
 449                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 450         }
 451 }
 452
 453 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 454 {
 455         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 456
 457         if (sc->sc_flags & SC_OP_TXAGGR)
 458                 ath_tx_node_cleanup(sc, an);
 459 }
 460
 461 static void ath9k_tasklet(unsigned long data)
 462 {
 463         struct ath_softc *sc = (struct ath_softc *)data;
 464         u32 status = sc->intrstatus;
 465
 466         ath9k_ps_wakeup(sc);
 467
 468         if (status & ATH9K_INT_FATAL) {
 469                 ath_reset(sc, false);
 470                 ath9k_ps_restore(sc);
 471                 return;
 472         }
 473
 474         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 475                 spin_lock_bh(&sc->rx.rxflushlock);
 476                 ath_rx_tasklet(sc, 0);
 477                 spin_unlock_bh(&sc->rx.rxflushlock);
 478         }
 479
 480         if (status & ATH9K_INT_TX)
 481                 ath_tx_tasklet(sc);
 482
 483         if ((status & ATH9K_INT_TSFOOR) &&
 484             (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
 485                 /*
 486                  * TSF sync does not look correct; remain awake to sync with
 487                  * the next Beacon.
 488                  */
 489                 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
 490                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
 491         }
 492
 493         /* re-enable hardware interrupt */
 494         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 495         ath9k_ps_restore(sc);
 496 }
 497
 498 irqreturn_t ath_isr(int irq, void *dev)
 499 {
 500 #define SCHED_INTR (                            \
 501                 ATH9K_INT_FATAL |               \
 502                 ATH9K_INT_RXORN |               \
 503                 ATH9K_INT_RXEOL |               \
 504                 ATH9K_INT_RX |                  \
 505                 ATH9K_INT_TX |                  \
 506                 ATH9K_INT_BMISS |               \
 507                 ATH9K_INT_CST |                 \
 508                 ATH9K_INT_TSFOOR)
 509
 510         struct ath_softc *sc = dev;
 511         struct ath_hw *ah = sc->sc_ah;
 512         enum ath9k_int status;
 513         bool sched = false;
 514
 515         /*
 516          * The hardware is not ready/present, don't
 517          * touch anything. Note this can happen early
 518          * on if the IRQ is shared.
 519          */
 520         if (sc->sc_flags & SC_OP_INVALID)
 521                 return IRQ_NONE;
 522
 523
 524         /* shared irq, not for us */
 525
 526         if (!ath9k_hw_intrpend(ah))
 527                 return IRQ_NONE;
 528
 529         /*
 530          * Figure out the reason(s) for the interrupt.  Note
 531          * that the hal returns a pseudo-ISR that may include
 532          * bits we haven't explicitly enabled so we mask the
 533          * value to insure we only process bits we requested.
 534          */
 535         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 536         status &= sc->imask;    /* discard unasked-for bits */
 537
 538         /*
 539          * If there are no status bits set, then this interrupt was not
 540          * for me (should have been caught above).
 541          */
 542         if (!status)
 543                 return IRQ_NONE;
 544
 545         /* Cache the status */
 546         sc->intrstatus = status;
 547
 548         if (status & SCHED_INTR)
 549                 sched = true;
 550
 551         /*
 552          * If a FATAL or RXORN interrupt is received, we have to reset the
 553          * chip immediately.
 554          */
 555         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 556                 goto chip_reset;
 557
 558         if (status & ATH9K_INT_SWBA)
 559                 tasklet_schedule(&sc->bcon_tasklet);
 560
 561         if (status & ATH9K_INT_TXURN)
 562                 ath9k_hw_updatetxtriglevel(ah, true);
 563
 564         if (status & ATH9K_INT_MIB) {
 565                 /*
 566                  * Disable interrupts until we service the MIB
 567                  * interrupt; otherwise it will continue to
 568                  * fire.
 569                  */
 570                 ath9k_hw_set_interrupts(ah, 0);
 571                 /*
 572                  * Let the hal handle the event. We assume
 573                  * it will clear whatever condition caused
 574                  * the interrupt.
 575                  */
 576                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 577                 ath9k_hw_set_interrupts(ah, sc->imask);
 578         }
 579
 580         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 581                 if (status & ATH9K_INT_TIM_TIMER) {
 582                         /* Clear RxAbort bit so that we can
 583                          * receive frames */
 584                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 585                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 586                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 587                 }
 588
 589 chip_reset:
 590
 591         ath_debug_stat_interrupt(sc, status);
 592
 593         if (sched) {
 594                 /* turn off every interrupt except SWBA */
 595                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 596                 tasklet_schedule(&sc->intr_tq);
 597         }
 598
 599         return IRQ_HANDLED;
 600
 601 #undef SCHED_INTR
 602 }
 603
 604 static u32 ath_get_extchanmode(struct ath_softc *sc,
 605                                struct ieee80211_channel *chan,
 606                                enum nl80211_channel_type channel_type)
 607 {
 608         u32 chanmode = 0;
 609
 610         switch (chan->band) {
 611         case IEEE80211_BAND_2GHZ:
 612                 switch(channel_type) {
 613                 case NL80211_CHAN_NO_HT:
 614                 case NL80211_CHAN_HT20:
 615                         chanmode = CHANNEL_G_HT20;
 616                         break;
 617                 case NL80211_CHAN_HT40PLUS:
 618                         chanmode = CHANNEL_G_HT40PLUS;
 619                         break;
 620                 case NL80211_CHAN_HT40MINUS:
 621                         chanmode = CHANNEL_G_HT40MINUS;
 622                         break;
 623                 }
 624                 break;
 625         case IEEE80211_BAND_5GHZ:
 626                 switch(channel_type) {
 627                 case NL80211_CHAN_NO_HT:
 628                 case NL80211_CHAN_HT20:
 629                         chanmode = CHANNEL_A_HT20;
 630                         break;
 631                 case NL80211_CHAN_HT40PLUS:
 632                         chanmode = CHANNEL_A_HT40PLUS;
 633                         break;
 634                 case NL80211_CHAN_HT40MINUS:
 635                         chanmode = CHANNEL_A_HT40MINUS;
 636                         break;
 637                 }
 638                 break;
 639         default:
 640                 break;
 641         }
 642
 643         return chanmode;
 644 }
 645
 646 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 647                            struct ath9k_keyval *hk, const u8 *addr,
 648                            bool authenticator)
 649 {
 650         const u8 *key_rxmic;
 651         const u8 *key_txmic;
 652
 653         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 654         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 655
 656         if (addr == NULL) {
 657                 /*
 658                  * Group key installation - only two key cache entries are used
 659                  * regardless of splitmic capability since group key is only
 660                  * used either for TX or RX.
 661                  */
 662                 if (authenticator) {
 663                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 664                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 665                 } else {
 666                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 667                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 668                 }
 669                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 670         }
 671         if (!sc->splitmic) {
 672                 /* TX and RX keys share the same key cache entry. */
 673                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 674                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 675                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 676         }
 677
 678         /* Separate key cache entries for TX and RX */
 679
 680         /* TX key goes at first index, RX key at +32. */
 681         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 682         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 683                 /* TX MIC entry failed. No need to proceed further */
 684                 DPRINTF(sc, ATH_DBG_FATAL,
 685                         "Setting TX MIC Key Failed\n");
 686                 return 0;
 687         }
 688
 689         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 690         /* XXX delete tx key on failure? */
 691         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 692 }
 693
 694 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 695 {
 696         int i;
 697
 698         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 699                 if (test_bit(i, sc->keymap) ||
 700                     test_bit(i + 64, sc->keymap))
 701                         continue; /* At least one part of TKIP key allocated */
 702                 if (sc->splitmic &&
 703                     (test_bit(i + 32, sc->keymap) ||
 704                      test_bit(i + 64 + 32, sc->keymap)))
 705                         continue; /* At least one part of TKIP key allocated */
 706
 707                 /* Found a free slot for a TKIP key */
 708                 return i;
 709         }
 710         return -1;
 711 }
 712
 713 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 714 {
 715         int i;
 716
 717         /* First, try to find slots that would not be available for TKIP. */
 718         if (sc->splitmic) {
 719                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 720                         if (!test_bit(i, sc->keymap) &&
 721                             (test_bit(i + 32, sc->keymap) ||
 722                              test_bit(i + 64, sc->keymap) ||
 723                              test_bit(i + 64 + 32, sc->keymap)))
 724                                 return i;
 725                         if (!test_bit(i + 32, sc->keymap) &&
 726                             (test_bit(i, sc->keymap) ||
 727                              test_bit(i + 64, sc->keymap) ||
 728                              test_bit(i + 64 + 32, sc->keymap)))
 729                                 return i + 32;
 730                         if (!test_bit(i + 64, sc->keymap) &&
 731                             (test_bit(i , sc->keymap) ||
 732                              test_bit(i + 32, sc->keymap) ||
 733                              test_bit(i + 64 + 32, sc->keymap)))
 734                                 return i + 64;
 735                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 736                             (test_bit(i, sc->keymap) ||
 737                              test_bit(i + 32, sc->keymap) ||
 738                              test_bit(i + 64, sc->keymap)))
 739                                 return i + 64 + 32;
 740                 }
 741         } else {
 742                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 743                         if (!test_bit(i, sc->keymap) &&
 744                             test_bit(i + 64, sc->keymap))
 745                                 return i;
 746                         if (test_bit(i, sc->keymap) &&
 747                             !test_bit(i + 64, sc->keymap))
 748                                 return i + 64;
 749                 }
 750         }
 751
 752         /* No partially used TKIP slots, pick any available slot */
 753         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 754                 /* Do not allow slots that could be needed for TKIP group keys
 755                  * to be used. This limitation could be removed if we know that
 756                  * TKIP will not be used. */
 757                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 758                         continue;
 759                 if (sc->splitmic) {
 760                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 761                                 continue;
 762                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 763                                 continue;
 764                 }
 765
 766                 if (!test_bit(i, sc->keymap))
 767                         return i; /* Found a free slot for a key */
 768         }
 769
 770         /* No free slot found */
 771         return -1;
 772 }
 773
 774 static int ath_key_config(struct ath_softc *sc,
 775                           struct ieee80211_vif *vif,
 776                           struct ieee80211_sta *sta,
 777                           struct ieee80211_key_conf *key)
 778 {
 779         struct ath9k_keyval hk;
 780         const u8 *mac = NULL;
 781         int ret = 0;
 782         int idx;
 783
 784         memset(&hk, 0, sizeof(hk));
 785
 786         switch (key->alg) {
 787         case ALG_WEP:
 788                 hk.kv_type = ATH9K_CIPHER_WEP;
 789                 break;
 790         case ALG_TKIP:
 791                 hk.kv_type = ATH9K_CIPHER_TKIP;
 792                 break;
 793         case ALG_CCMP:
 794                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 795                 break;
 796         default:
 797                 return -EOPNOTSUPP;
 798         }
 799
 800         hk.kv_len = key->keylen;
 801         memcpy(hk.kv_val, key->key, key->keylen);
 802
 803         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 804                 /* For now, use the default keys for broadcast keys. This may
 805                  * need to change with virtual interfaces. */
 806                 idx = key->keyidx;
 807         } else if (key->keyidx) {
 808                 if (WARN_ON(!sta))
 809                         return -EOPNOTSUPP;
 810                 mac = sta->addr;
 811
 812                 if (vif->type != NL80211_IFTYPE_AP) {
 813                         /* Only keyidx 0 should be used with unicast key, but
 814                          * allow this for client mode for now. */
 815                         idx = key->keyidx;
 816                 } else
 817                         return -EIO;
 818         } else {
 819                 if (WARN_ON(!sta))
 820                         return -EOPNOTSUPP;
 821                 mac = sta->addr;
 822
 823                 if (key->alg == ALG_TKIP)
 824                         idx = ath_reserve_key_cache_slot_tkip(sc);
 825                 else
 826                         idx = ath_reserve_key_cache_slot(sc);
 827                 if (idx < 0)
 828                         return -ENOSPC; /* no free key cache entries */
 829         }
 830
 831         if (key->alg == ALG_TKIP)
 832                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 833                                       vif->type == NL80211_IFTYPE_AP);
 834         else
 835                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 836
 837         if (!ret)
 838                 return -EIO;
 839
 840         set_bit(idx, sc->keymap);
 841         if (key->alg == ALG_TKIP) {
 842                 set_bit(idx + 64, sc->keymap);
 843                 if (sc->splitmic) {
 844                         set_bit(idx + 32, sc->keymap);
 845                         set_bit(idx + 64 + 32, sc->keymap);
 846                 }
 847         }
 848
 849         return idx;
 850 }
 851
 852 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 853 {
 854         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 855         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 856                 return;
 857
 858         clear_bit(key->hw_key_idx, sc->keymap);
 859         if (key->alg != ALG_TKIP)
 860                 return;
 861
 862         clear_bit(key->hw_key_idx + 64, sc->keymap);
 863         if (sc->splitmic) {
 864                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 865                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 866         }
 867 }
 868
 869 static void setup_ht_cap(struct ath_softc *sc,
 870                          struct ieee80211_sta_ht_cap *ht_info)
 871 {
 872 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 873 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 874
 875         ht_info->ht_supported = true;
 876         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 877                        IEEE80211_HT_CAP_SM_PS |
 878                        IEEE80211_HT_CAP_SGI_40 |
 879                        IEEE80211_HT_CAP_DSSSCCK40;
 880
 881         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 882         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 883
 884         /* set up supported mcs set */
 885         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 886
 887         switch(sc->rx_chainmask) {
 888         case 1:
 889                 ht_info->mcs.rx_mask[0] = 0xff;
 890                 break;
 891         case 3:
 892         case 5:
 893         case 7:
 894         default:
 895                 ht_info->mcs.rx_mask[0] = 0xff;
 896                 ht_info->mcs.rx_mask[1] = 0xff;
 897                 break;
 898         }
 899
 900         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 901 }
 902
 903 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 904                                  struct ieee80211_vif *vif,
 905                                  struct ieee80211_bss_conf *bss_conf)
 906 {
 907         struct ath_vif *avp = (void *)vif->drv_priv;
 908
 909         if (bss_conf->assoc) {
 910                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 911                         bss_conf->aid, sc->curbssid);
 912
 913                 /* New association, store aid */
 914                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 915                         sc->curaid = bss_conf->aid;
 916                         ath9k_hw_write_associd(sc);
 917
 918                         /*
 919                          * Request a re-configuration of Beacon related timers
 920                          * on the receipt of the first Beacon frame (i.e.,
 921                          * after time sync with the AP).
 922                          */
 923                         sc->sc_flags |= SC_OP_BEACON_SYNC;
 924                 }
 925
 926                 /* Configure the beacon */
 927                 ath_beacon_config(sc, vif);
 928
 929                 /* Reset rssi stats */
 930                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 931                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 932                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 933                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 934
 935                 ath_start_ani(sc);
 936         } else {
 937                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
 938                 sc->curaid = 0;
 939         }
 940 }
 941
 942 /********************************/
 943 /*       LED functions          */
 944 /********************************/
 945
 946 static void ath_led_blink_work(struct work_struct *work)
 947 {
 948         struct ath_softc *sc = container_of(work, struct ath_softc,
 949                                             ath_led_blink_work.work);
 950
 951         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 952                 return;
 953
 954         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
 955             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
 956                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 957         else
 958                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 959                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 960
 961         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 962                            (sc->sc_flags & SC_OP_LED_ON) ?
 963                            msecs_to_jiffies(sc->led_off_duration) :
 964                            msecs_to_jiffies(sc->led_on_duration));
 965
 966         sc->led_on_duration = sc->led_on_cnt ?
 967                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
 968                         ATH_LED_ON_DURATION_IDLE;
 969         sc->led_off_duration = sc->led_off_cnt ?
 970                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
 971                         ATH_LED_OFF_DURATION_IDLE;
 972         sc->led_on_cnt = sc->led_off_cnt = 0;
 973         if (sc->sc_flags & SC_OP_LED_ON)
 974                 sc->sc_flags &= ~SC_OP_LED_ON;
 975         else
 976                 sc->sc_flags |= SC_OP_LED_ON;
 977 }
 978
 979 static void ath_led_brightness(struct led_classdev *led_cdev,
 980                                enum led_brightness brightness)
 981 {
 982         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 983         struct ath_softc *sc = led->sc;
 984
 985         switch (brightness) {
 986         case LED_OFF:
 987                 if (led->led_type == ATH_LED_ASSOC ||
 988                     led->led_type == ATH_LED_RADIO) {
 989                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 990                                 (led->led_type == ATH_LED_RADIO));
 991                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 992                         if (led->led_type == ATH_LED_RADIO)
 993                                 sc->sc_flags &= ~SC_OP_LED_ON;
 994                 } else {
 995                         sc->led_off_cnt++;
 996                 }
 997                 break;
 998         case LED_FULL:
 999                 if (led->led_type == ATH_LED_ASSOC) {
1000                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1001                         queue_delayed_work(sc->hw->workqueue,
1002                                            &sc->ath_led_blink_work, 0);
1003                 } else if (led->led_type == ATH_LED_RADIO) {
1004                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1005                         sc->sc_flags |= SC_OP_LED_ON;
1006                 } else {
1007                         sc->led_on_cnt++;
1008                 }
1009                 break;
1010         default:
1011                 break;
1012         }
1013 }
1014
1015 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1016                             char *trigger)
1017 {
1018         int ret;
1019
1020         led->sc = sc;
1021         led->led_cdev.name = led->name;
1022         led->led_cdev.default_trigger = trigger;
1023         led->led_cdev.brightness_set = ath_led_brightness;
1024
1025         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1026         if (ret)
1027                 DPRINTF(sc, ATH_DBG_FATAL,
1028                         "Failed to register led:%s", led->name);
1029         else
1030                 led->registered = 1;
1031         return ret;
1032 }
1033
1034 static void ath_unregister_led(struct ath_led *led)
1035 {
1036         if (led->registered) {
1037                 led_classdev_unregister(&led->led_cdev);
1038                 led->registered = 0;
1039         }
1040 }
1041
1042 static void ath_deinit_leds(struct ath_softc *sc)
1043 {
1044         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1045         ath_unregister_led(&sc->assoc_led);
1046         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1047         ath_unregister_led(&sc->tx_led);
1048         ath_unregister_led(&sc->rx_led);
1049         ath_unregister_led(&sc->radio_led);
1050         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1051 }
1052
1053 static void ath_init_leds(struct ath_softc *sc)
1054 {
1055         char *trigger;
1056         int ret;
1057
1058         /* Configure gpio 1 for output */
1059         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1060                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1061         /* LED off, active low */
1062         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1063
1064         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1065
1066         trigger = ieee80211_get_radio_led_name(sc->hw);
1067         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1068                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1069         ret = ath_register_led(sc, &sc->radio_led, trigger);
1070         sc->radio_led.led_type = ATH_LED_RADIO;
1071         if (ret)
1072                 goto fail;
1073
1074         trigger = ieee80211_get_assoc_led_name(sc->hw);
1075         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1076                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1077         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1078         sc->assoc_led.led_type = ATH_LED_ASSOC;
1079         if (ret)
1080                 goto fail;
1081
1082         trigger = ieee80211_get_tx_led_name(sc->hw);
1083         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1084                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1085         ret = ath_register_led(sc, &sc->tx_led, trigger);
1086         sc->tx_led.led_type = ATH_LED_TX;
1087         if (ret)
1088                 goto fail;
1089
1090         trigger = ieee80211_get_rx_led_name(sc->hw);
1091         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1092                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1093         ret = ath_register_led(sc, &sc->rx_led, trigger);
1094         sc->rx_led.led_type = ATH_LED_RX;
1095         if (ret)
1096                 goto fail;
1097
1098         return;
1099
1100 fail:
1101         ath_deinit_leds(sc);
1102 }
1103
1104 void ath_radio_enable(struct ath_softc *sc)
1105 {
1106         struct ath_hw *ah = sc->sc_ah;
1107         struct ieee80211_channel *channel = sc->hw->conf.channel;
1108         int r;
1109
1110         ath9k_ps_wakeup(sc);
1111         ath9k_hw_configpcipowersave(ah, 0);
1112
1113         spin_lock_bh(&sc->sc_resetlock);
1114         r = ath9k_hw_reset(ah, ah->curchan, false);
1115         if (r) {
1116                 DPRINTF(sc, ATH_DBG_FATAL,
1117                         "Unable to reset channel %u (%uMhz) ",
1118                         "reset status %d\n",
1119                         channel->center_freq, r);
1120         }
1121         spin_unlock_bh(&sc->sc_resetlock);
1122
1123         ath_update_txpow(sc);
1124         if (ath_startrecv(sc) != 0) {
1125                 DPRINTF(sc, ATH_DBG_FATAL,
1126                         "Unable to restart recv logic\n");
1127                 return;
1128         }
1129
1130         if (sc->sc_flags & SC_OP_BEACONS)
1131                 ath_beacon_config(sc, NULL);    /* restart beacons */
1132
1133         /* Re-Enable  interrupts */
1134         ath9k_hw_set_interrupts(ah, sc->imask);
1135
1136         /* Enable LED */
1137         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1138                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1139         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1140
1141         ieee80211_wake_queues(sc->hw);
1142         ath9k_ps_restore(sc);
1143 }
1144
1145 void ath_radio_disable(struct ath_softc *sc)
1146 {
1147         struct ath_hw *ah = sc->sc_ah;
1148         struct ieee80211_channel *channel = sc->hw->conf.channel;
1149         int r;
1150
1151         ath9k_ps_wakeup(sc);
1152         ieee80211_stop_queues(sc->hw);
1153
1154         /* Disable LED */
1155         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1156         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1157
1158         /* Disable interrupts */
1159         ath9k_hw_set_interrupts(ah, 0);
1160
1161         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1162         ath_stoprecv(sc);               /* turn off frame recv */
1163         ath_flushrecv(sc);              /* flush recv queue */
1164
1165         spin_lock_bh(&sc->sc_resetlock);
1166         r = ath9k_hw_reset(ah, ah->curchan, false);
1167         if (r) {
1168                 DPRINTF(sc, ATH_DBG_FATAL,
1169                         "Unable to reset channel %u (%uMhz) "
1170                         "reset status %d\n",
1171                         channel->center_freq, r);
1172         }
1173         spin_unlock_bh(&sc->sc_resetlock);
1174
1175         ath9k_hw_phy_disable(ah);
1176         ath9k_hw_configpcipowersave(ah, 1);
1177         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1178         ath9k_ps_restore(sc);
1179 }
1180
1181 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1182
1183 /*******************/
1184 /*      Rfkill     */
1185 /*******************/
1186
1187 static bool ath_is_rfkill_set(struct ath_softc *sc)
1188 {
1189         struct ath_hw *ah = sc->sc_ah;
1190
1191         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1192                                   ah->rfkill_polarity;
1193 }
1194
1195 /* h/w rfkill poll function */
1196 static void ath_rfkill_poll(struct work_struct *work)
1197 {
1198         struct ath_softc *sc = container_of(work, struct ath_softc,
1199                                             rf_kill.rfkill_poll.work);
1200         bool radio_on;
1201
1202         if (sc->sc_flags & SC_OP_INVALID)
1203                 return;
1204
1205         radio_on = !ath_is_rfkill_set(sc);
1206
1207         /*
1208          * enable/disable radio only when there is a
1209          * state change in RF switch
1210          */
1211         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1212                 enum rfkill_state state;
1213
1214                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1215                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1216                                 : RFKILL_STATE_HARD_BLOCKED;
1217                 } else if (radio_on) {
1218                         ath_radio_enable(sc);
1219                         state = RFKILL_STATE_UNBLOCKED;
1220                 } else {
1221                         ath_radio_disable(sc);
1222                         state = RFKILL_STATE_HARD_BLOCKED;
1223                 }
1224
1225                 if (state == RFKILL_STATE_HARD_BLOCKED)
1226                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1227                 else
1228                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1229
1230                 rfkill_force_state(sc->rf_kill.rfkill, state);
1231         }
1232
1233         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1234                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1235 }
1236
1237 /* s/w rfkill handler */
1238 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1239 {
1240         struct ath_softc *sc = data;
1241
1242         switch (state) {
1243         case RFKILL_STATE_SOFT_BLOCKED:
1244                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1245                     SC_OP_RFKILL_SW_BLOCKED)))
1246                         ath_radio_disable(sc);
1247                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1248                 return 0;
1249         case RFKILL_STATE_UNBLOCKED:
1250                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1251                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1252                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1253                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1254                                         "radio as it is disabled by h/w\n");
1255                                 return -EPERM;
1256                         }
1257                         ath_radio_enable(sc);
1258                 }
1259                 return 0;
1260         default:
1261                 return -EINVAL;
1262         }
1263 }
1264
1265 /* Init s/w rfkill */
1266 static int ath_init_sw_rfkill(struct ath_softc *sc)
1267 {
1268         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1269                                              RFKILL_TYPE_WLAN);
1270         if (!sc->rf_kill.rfkill) {
1271                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1272                 return -ENOMEM;
1273         }
1274
1275         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1276                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1277         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1278         sc->rf_kill.rfkill->data = sc;
1279         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1280         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1281
1282         return 0;
1283 }
1284
1285 /* Deinitialize rfkill */
1286 static void ath_deinit_rfkill(struct ath_softc *sc)
1287 {
1288         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1289                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1290
1291         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1292                 rfkill_unregister(sc->rf_kill.rfkill);
1293                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1294                 sc->rf_kill.rfkill = NULL;
1295         }
1296 }
1297
1298 static int ath_start_rfkill_poll(struct ath_softc *sc)
1299 {
1300         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1301                 queue_delayed_work(sc->hw->workqueue,
1302                                    &sc->rf_kill.rfkill_poll, 0);
1303
1304         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1305                 if (rfkill_register(sc->rf_kill.rfkill)) {
1306                         DPRINTF(sc, ATH_DBG_FATAL,
1307                                 "Unable to register rfkill\n");
1308                         rfkill_free(sc->rf_kill.rfkill);
1309
1310                         /* Deinitialize the device */
1311                         ath_cleanup(sc);
1312                         return -EIO;
1313                 } else {
1314                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1315                 }
1316         }
1317
1318         return 0;
1319 }
1320 #endif /* CONFIG_RFKILL */
1321
1322 void ath_cleanup(struct ath_softc *sc)
1323 {
1324         ath_detach(sc);
1325         free_irq(sc->irq, sc);
1326         ath_bus_cleanup(sc);
1327         kfree(sc->sec_wiphy);
1328         ieee80211_free_hw(sc->hw);
1329 }
1330
1331 void ath_detach(struct ath_softc *sc)
1332 {
1333         struct ieee80211_hw *hw = sc->hw;
1334         int i = 0;
1335
1336         ath9k_ps_wakeup(sc);
1337
1338         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1339
1340 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1341         ath_deinit_rfkill(sc);
1342 #endif
1343         ath_deinit_leds(sc);
1344         cancel_work_sync(&sc->chan_work);
1345         cancel_delayed_work_sync(&sc->wiphy_work);
1346
1347         for (i = 0; i < sc->num_sec_wiphy; i++) {
1348                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1349                 if (aphy == NULL)
1350                         continue;
1351                 sc->sec_wiphy[i] = NULL;
1352                 ieee80211_unregister_hw(aphy->hw);
1353                 ieee80211_free_hw(aphy->hw);
1354         }
1355         ieee80211_unregister_hw(hw);
1356         ath_rx_cleanup(sc);
1357         ath_tx_cleanup(sc);
1358
1359         tasklet_kill(&sc->intr_tq);
1360         tasklet_kill(&sc->bcon_tasklet);
1361
1362         if (!(sc->sc_flags & SC_OP_INVALID))
1363                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1364
1365         /* cleanup tx queues */
1366         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1367                 if (ATH_TXQ_SETUP(sc, i))
1368                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1369
1370         ath9k_hw_detach(sc->sc_ah);
1371         ath9k_exit_debug(sc);
1372         ath9k_ps_restore(sc);
1373 }
1374
1375 static int ath9k_reg_notifier(struct wiphy *wiphy,
1376                               struct regulatory_request *request)
1377 {
1378         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1379         struct ath_wiphy *aphy = hw->priv;
1380         struct ath_softc *sc = aphy->sc;
1381         struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1382
1383         return ath_reg_notifier_apply(wiphy, request, reg);
1384 }
1385
1386 static int ath_init(u16 devid, struct ath_softc *sc)
1387 {
1388         struct ath_hw *ah = NULL;
1389         int status;
1390         int error = 0, i;
1391         int csz = 0;
1392
1393         /* XXX: hardware will not be ready until ath_open() being called */
1394         sc->sc_flags |= SC_OP_INVALID;
1395
1396         if (ath9k_init_debug(sc) < 0)
1397                 printk(KERN_ERR "Unable to create debugfs files\n");
1398
1399         spin_lock_init(&sc->wiphy_lock);
1400         spin_lock_init(&sc->sc_resetlock);
1401         spin_lock_init(&sc->sc_serial_rw);
1402         mutex_init(&sc->mutex);
1403         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1404         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1405                      (unsigned long)sc);
1406
1407         /*
1408          * Cache line size is used to size and align various
1409          * structures used to communicate with the hardware.
1410          */
1411         ath_read_cachesize(sc, &csz);
1412         /* XXX assert csz is non-zero */
1413         sc->cachelsz = csz << 2;        /* convert to bytes */
1414
1415         ah = ath9k_hw_attach(devid, sc, &status);
1416         if (ah == NULL) {
1417                 DPRINTF(sc, ATH_DBG_FATAL,
1418                         "Unable to attach hardware; HAL status %d\n", status);
1419                 error = -ENXIO;
1420                 goto bad;
1421         }
1422         sc->sc_ah = ah;
1423
1424         /* Get the hardware key cache size. */
1425         sc->keymax = ah->caps.keycache_size;
1426         if (sc->keymax > ATH_KEYMAX) {
1427                 DPRINTF(sc, ATH_DBG_ANY,
1428                         "Warning, using only %u entries in %u key cache\n",
1429                         ATH_KEYMAX, sc->keymax);
1430                 sc->keymax = ATH_KEYMAX;
1431         }
1432
1433         /*
1434          * Reset the key cache since some parts do not
1435          * reset the contents on initial power up.
1436          */
1437         for (i = 0; i < sc->keymax; i++)
1438                 ath9k_hw_keyreset(ah, (u16) i);
1439
1440         if (error)
1441                 goto bad;
1442
1443         /* default to MONITOR mode */
1444         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1445
1446         /* Setup rate tables */
1447
1448         ath_rate_attach(sc);
1449         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1450         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1451
1452         /*
1453          * Allocate hardware transmit queues: one queue for
1454          * beacon frames and one data queue for each QoS
1455          * priority.  Note that the hal handles reseting
1456          * these queues at the needed time.
1457          */
1458         sc->beacon.beaconq = ath_beaconq_setup(ah);
1459         if (sc->beacon.beaconq == -1) {
1460                 DPRINTF(sc, ATH_DBG_FATAL,
1461                         "Unable to setup a beacon xmit queue\n");
1462                 error = -EIO;
1463                 goto bad2;
1464         }
1465         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1466         if (sc->beacon.cabq == NULL) {
1467                 DPRINTF(sc, ATH_DBG_FATAL,
1468                         "Unable to setup CAB xmit queue\n");
1469                 error = -EIO;
1470                 goto bad2;
1471         }
1472
1473         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1474         ath_cabq_update(sc);
1475
1476         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1477                 sc->tx.hwq_map[i] = -1;
1478
1479         /* Setup data queues */
1480         /* NB: ensure BK queue is the lowest priority h/w queue */
1481         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1482                 DPRINTF(sc, ATH_DBG_FATAL,
1483                         "Unable to setup xmit queue for BK traffic\n");
1484                 error = -EIO;
1485                 goto bad2;
1486         }
1487
1488         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1489                 DPRINTF(sc, ATH_DBG_FATAL,
1490                         "Unable to setup xmit queue for BE traffic\n");
1491                 error = -EIO;
1492                 goto bad2;
1493         }
1494         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1495                 DPRINTF(sc, ATH_DBG_FATAL,
1496                         "Unable to setup xmit queue for VI traffic\n");
1497                 error = -EIO;
1498                 goto bad2;
1499         }
1500         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1501                 DPRINTF(sc, ATH_DBG_FATAL,
1502                         "Unable to setup xmit queue for VO traffic\n");
1503                 error = -EIO;
1504                 goto bad2;
1505         }
1506
1507         /* Initializes the noise floor to a reasonable default value.
1508          * Later on this will be updated during ANI processing. */
1509
1510         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1511         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1512
1513         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1514                                    ATH9K_CIPHER_TKIP, NULL)) {
1515                 /*
1516                  * Whether we should enable h/w TKIP MIC.
1517                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1518                  * report WMM capable, so it's always safe to turn on
1519                  * TKIP MIC in this case.
1520                  */
1521                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1522                                        0, 1, NULL);
1523         }
1524
1525         /*
1526          * Check whether the separate key cache entries
1527          * are required to handle both tx+rx MIC keys.
1528          * With split mic keys the number of stations is limited
1529          * to 27 otherwise 59.
1530          */
1531         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1532                                    ATH9K_CIPHER_TKIP, NULL)
1533             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1534                                       ATH9K_CIPHER_MIC, NULL)
1535             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1536                                       0, NULL))
1537                 sc->splitmic = 1;
1538
1539         /* turn on mcast key search if possible */
1540         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1541                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1542                                              1, NULL);
1543
1544         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1545
1546         /* 11n Capabilities */
1547         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1548                 sc->sc_flags |= SC_OP_TXAGGR;
1549                 sc->sc_flags |= SC_OP_RXAGGR;
1550         }
1551
1552         sc->tx_chainmask = ah->caps.tx_chainmask;
1553         sc->rx_chainmask = ah->caps.rx_chainmask;
1554
1555         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1556         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1557
1558         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1559                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1560
1561         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1562
1563         /* initialize beacon slots */
1564         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1565                 sc->beacon.bslot[i] = NULL;
1566                 sc->beacon.bslot_aphy[i] = NULL;
1567         }
1568
1569         /* setup channels and rates */
1570
1571         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1572         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1573                 sc->rates[IEEE80211_BAND_2GHZ];
1574         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1575         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1576                 ARRAY_SIZE(ath9k_2ghz_chantable);
1577
1578         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1579                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1580                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1581                         sc->rates[IEEE80211_BAND_5GHZ];
1582                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1583                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1584                         ARRAY_SIZE(ath9k_5ghz_chantable);
1585         }
1586
1587         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1588                 ath9k_hw_btcoex_enable(sc->sc_ah);
1589
1590         return 0;
1591 bad2:
1592         /* cleanup tx queues */
1593         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1594                 if (ATH_TXQ_SETUP(sc, i))
1595                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1596 bad:
1597         if (ah)
1598                 ath9k_hw_detach(ah);
1599         ath9k_exit_debug(sc);
1600
1601         return error;
1602 }
1603
1604 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1605 {
1606         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1607                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1608                 IEEE80211_HW_SIGNAL_DBM |
1609                 IEEE80211_HW_AMPDU_AGGREGATION |
1610                 IEEE80211_HW_SUPPORTS_PS |
1611                 IEEE80211_HW_PS_NULLFUNC_STACK |
1612                 IEEE80211_HW_SPECTRUM_MGMT;
1613
1614         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1615                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1616
1617         hw->wiphy->interface_modes =
1618                 BIT(NL80211_IFTYPE_AP) |
1619                 BIT(NL80211_IFTYPE_STATION) |
1620                 BIT(NL80211_IFTYPE_ADHOC) |
1621                 BIT(NL80211_IFTYPE_MESH_POINT);
1622
1623         hw->queues = 4;
1624         hw->max_rates = 4;
1625         hw->channel_change_time = 5000;
1626         hw->max_listen_interval = 10;
1627         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1628         hw->sta_data_size = sizeof(struct ath_node);
1629         hw->vif_data_size = sizeof(struct ath_vif);
1630
1631         hw->rate_control_algorithm = "ath9k_rate_control";
1632
1633         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1634                 &sc->sbands[IEEE80211_BAND_2GHZ];
1635         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1636                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1637                         &sc->sbands[IEEE80211_BAND_5GHZ];
1638 }
1639
1640 int ath_attach(u16 devid, struct ath_softc *sc)
1641 {
1642         struct ieee80211_hw *hw = sc->hw;
1643         int error = 0, i;
1644         struct ath_regulatory *reg;
1645
1646         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1647
1648         error = ath_init(devid, sc);
1649         if (error != 0)
1650                 return error;
1651
1652         /* get mac address from hardware and set in mac80211 */
1653
1654         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1655
1656         ath_set_hw_capab(sc, hw);
1657
1658         error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1659                               ath9k_reg_notifier);
1660         if (error)
1661                 return error;
1662
1663         reg = &sc->sc_ah->regulatory;
1664
1665         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1666                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1667                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1668                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1669         }
1670
1671         /* initialize tx/rx engine */
1672         error = ath_tx_init(sc, ATH_TXBUF);
1673         if (error != 0)
1674                 goto error_attach;
1675
1676         error = ath_rx_init(sc, ATH_RXBUF);
1677         if (error != 0)
1678                 goto error_attach;
1679
1680 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1681         /* Initialze h/w Rfkill */
1682         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1683                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1684
1685         /* Initialize s/w rfkill */
1686         error = ath_init_sw_rfkill(sc);
1687         if (error)
1688                 goto error_attach;
1689 #endif
1690
1691         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1692         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1693         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1694
1695         error = ieee80211_register_hw(hw);
1696
1697         if (!ath_is_world_regd(reg)) {
1698                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1699                 if (error)
1700                         goto error_attach;
1701         }
1702
1703         /* Initialize LED control */
1704         ath_init_leds(sc);
1705
1706
1707         return 0;
1708
1709 error_attach:
1710         /* cleanup tx queues */
1711         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1712                 if (ATH_TXQ_SETUP(sc, i))
1713                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1714
1715         ath9k_hw_detach(sc->sc_ah);
1716         ath9k_exit_debug(sc);
1717
1718         return error;
1719 }
1720
1721 int ath_reset(struct ath_softc *sc, bool retry_tx)
1722 {
1723         struct ath_hw *ah = sc->sc_ah;
1724         struct ieee80211_hw *hw = sc->hw;
1725         int r;
1726
1727         ath9k_hw_set_interrupts(ah, 0);
1728         ath_drain_all_txq(sc, retry_tx);
1729         ath_stoprecv(sc);
1730         ath_flushrecv(sc);
1731
1732         spin_lock_bh(&sc->sc_resetlock);
1733         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1734         if (r)
1735                 DPRINTF(sc, ATH_DBG_FATAL,
1736                         "Unable to reset hardware; reset status %d\n", r);
1737         spin_unlock_bh(&sc->sc_resetlock);
1738
1739         if (ath_startrecv(sc) != 0)
1740                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1741
1742         /*
1743          * We may be doing a reset in response to a request
1744          * that changes the channel so update any state that
1745          * might change as a result.
1746          */
1747         ath_cache_conf_rate(sc, &hw->conf);
1748
1749         ath_update_txpow(sc);
1750
1751         if (sc->sc_flags & SC_OP_BEACONS)
1752                 ath_beacon_config(sc, NULL);    /* restart beacons */
1753
1754         ath9k_hw_set_interrupts(ah, sc->imask);
1755
1756         if (retry_tx) {
1757                 int i;
1758                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1759                         if (ATH_TXQ_SETUP(sc, i)) {
1760                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1761                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1762                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1763                         }
1764                 }
1765         }
1766
1767         return r;
1768 }
1769
1770 /*
1771  *  This function will allocate both the DMA descriptor structure, and the
1772  *  buffers it contains.  These are used to contain the descriptors used
1773  *  by the system.
1774 */
1775 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1776                       struct list_head *head, const char *name,
1777                       int nbuf, int ndesc)
1778 {
1779 #define DS2PHYS(_dd, _ds)                                               \
1780         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1781 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1782 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1783
1784         struct ath_desc *ds;
1785         struct ath_buf *bf;
1786         int i, bsize, error;
1787
1788         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1789                 name, nbuf, ndesc);
1790
1791         INIT_LIST_HEAD(head);
1792         /* ath_desc must be a multiple of DWORDs */
1793         if ((sizeof(struct ath_desc) % 4) != 0) {
1794                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1795                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1796                 error = -ENOMEM;
1797                 goto fail;
1798         }
1799
1800         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1801
1802         /*
1803          * Need additional DMA memory because we can't use
1804          * descriptors that cross the 4K page boundary. Assume
1805          * one skipped descriptor per 4K page.
1806          */
1807         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1808                 u32 ndesc_skipped =
1809                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1810                 u32 dma_len;
1811
1812                 while (ndesc_skipped) {
1813                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1814                         dd->dd_desc_len += dma_len;
1815
1816                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1817                 };
1818         }
1819
1820         /* allocate descriptors */
1821         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1822                                          &dd->dd_desc_paddr, GFP_KERNEL);
1823         if (dd->dd_desc == NULL) {
1824                 error = -ENOMEM;
1825                 goto fail;
1826         }
1827         ds = dd->dd_desc;
1828         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1829                 name, ds, (u32) dd->dd_desc_len,
1830                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1831
1832         /* allocate buffers */
1833         bsize = sizeof(struct ath_buf) * nbuf;
1834         bf = kzalloc(bsize, GFP_KERNEL);
1835         if (bf == NULL) {
1836                 error = -ENOMEM;
1837                 goto fail2;
1838         }
1839         dd->dd_bufptr = bf;
1840
1841         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1842                 bf->bf_desc = ds;
1843                 bf->bf_daddr = DS2PHYS(dd, ds);
1844
1845                 if (!(sc->sc_ah->caps.hw_caps &
1846                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1847                         /*
1848                          * Skip descriptor addresses which can cause 4KB
1849                          * boundary crossing (addr + length) with a 32 dword
1850                          * descriptor fetch.
1851                          */
1852                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1853                                 ASSERT((caddr_t) bf->bf_desc <
1854                                        ((caddr_t) dd->dd_desc +
1855                                         dd->dd_desc_len));
1856
1857                                 ds += ndesc;
1858                                 bf->bf_desc = ds;
1859                                 bf->bf_daddr = DS2PHYS(dd, ds);
1860                         }
1861                 }
1862                 list_add_tail(&bf->list, head);
1863         }
1864         return 0;
1865 fail2:
1866         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1867                           dd->dd_desc_paddr);
1868 fail:
1869         memset(dd, 0, sizeof(*dd));
1870         return error;
1871 #undef ATH_DESC_4KB_BOUND_CHECK
1872 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1873 #undef DS2PHYS
1874 }
1875
1876 void ath_descdma_cleanup(struct ath_softc *sc,
1877                          struct ath_descdma *dd,
1878                          struct list_head *head)
1879 {
1880         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1881                           dd->dd_desc_paddr);
1882
1883         INIT_LIST_HEAD(head);
1884         kfree(dd->dd_bufptr);
1885         memset(dd, 0, sizeof(*dd));
1886 }
1887
1888 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1889 {
1890         int qnum;
1891
1892         switch (queue) {
1893         case 0:
1894                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1895                 break;
1896         case 1:
1897                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1898                 break;
1899         case 2:
1900                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1901                 break;
1902         case 3:
1903                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1904                 break;
1905         default:
1906                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1907                 break;
1908         }
1909
1910         return qnum;
1911 }
1912
1913 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1914 {
1915         int qnum;
1916
1917         switch (queue) {
1918         case ATH9K_WME_AC_VO:
1919                 qnum = 0;
1920                 break;
1921         case ATH9K_WME_AC_VI:
1922                 qnum = 1;
1923                 break;
1924         case ATH9K_WME_AC_BE:
1925                 qnum = 2;
1926                 break;
1927         case ATH9K_WME_AC_BK:
1928                 qnum = 3;
1929                 break;
1930         default:
1931                 qnum = -1;
1932                 break;
1933         }
1934
1935         return qnum;
1936 }
1937
1938 /* XXX: Remove me once we don't depend on ath9k_channel for all
1939  * this redundant data */
1940 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1941                            struct ath9k_channel *ichan)
1942 {
1943         struct ieee80211_channel *chan = hw->conf.channel;
1944         struct ieee80211_conf *conf = &hw->conf;
1945
1946         ichan->channel = chan->center_freq;
1947         ichan->chan = chan;
1948
1949         if (chan->band == IEEE80211_BAND_2GHZ) {
1950                 ichan->chanmode = CHANNEL_G;
1951                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1952         } else {
1953                 ichan->chanmode = CHANNEL_A;
1954                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1955         }
1956
1957         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1958
1959         if (conf_is_ht(conf)) {
1960                 if (conf_is_ht40(conf))
1961                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1962
1963                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1964                                             conf->channel_type);
1965         }
1966 }
1967
1968 /**********************/
1969 /* mac80211 callbacks */
1970 /**********************/
1971
1972 static int ath9k_start(struct ieee80211_hw *hw)
1973 {
1974         struct ath_wiphy *aphy = hw->priv;
1975         struct ath_softc *sc = aphy->sc;
1976         struct ieee80211_channel *curchan = hw->conf.channel;
1977         struct ath9k_channel *init_channel;
1978         int r, pos;
1979
1980         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1981                 "initial channel: %d MHz\n", curchan->center_freq);
1982
1983         mutex_lock(&sc->mutex);
1984
1985         if (ath9k_wiphy_started(sc)) {
1986                 if (sc->chan_idx == curchan->hw_value) {
1987                         /*
1988                          * Already on the operational channel, the new wiphy
1989                          * can be marked active.
1990                          */
1991                         aphy->state = ATH_WIPHY_ACTIVE;
1992                         ieee80211_wake_queues(hw);
1993                 } else {
1994                         /*
1995                          * Another wiphy is on another channel, start the new
1996                          * wiphy in paused state.
1997                          */
1998                         aphy->state = ATH_WIPHY_PAUSED;
1999                         ieee80211_stop_queues(hw);
2000                 }
2001                 mutex_unlock(&sc->mutex);
2002                 return 0;
2003         }
2004         aphy->state = ATH_WIPHY_ACTIVE;
2005
2006         /* setup initial channel */
2007
2008         pos = curchan->hw_value;
2009
2010         sc->chan_idx = pos;
2011         init_channel = &sc->sc_ah->channels[pos];
2012         ath9k_update_ichannel(sc, hw, init_channel);
2013
2014         /* Reset SERDES registers */
2015         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2016
2017         /*
2018          * The basic interface to setting the hardware in a good
2019          * state is ``reset''.  On return the hardware is known to
2020          * be powered up and with interrupts disabled.  This must
2021          * be followed by initialization of the appropriate bits
2022          * and then setup of the interrupt mask.
2023          */
2024         spin_lock_bh(&sc->sc_resetlock);
2025         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2026         if (r) {
2027                 DPRINTF(sc, ATH_DBG_FATAL,
2028                         "Unable to reset hardware; reset status %d "
2029                         "(freq %u MHz)\n", r,
2030                         curchan->center_freq);
2031                 spin_unlock_bh(&sc->sc_resetlock);
2032                 goto mutex_unlock;
2033         }
2034         spin_unlock_bh(&sc->sc_resetlock);
2035
2036         /*
2037          * This is needed only to setup initial state
2038          * but it's best done after a reset.
2039          */
2040         ath_update_txpow(sc);
2041
2042         /*
2043          * Setup the hardware after reset:
2044          * The receive engine is set going.
2045          * Frame transmit is handled entirely
2046          * in the frame output path; there's nothing to do
2047          * here except setup the interrupt mask.
2048          */
2049         if (ath_startrecv(sc) != 0) {
2050                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
2051                 r = -EIO;
2052                 goto mutex_unlock;
2053         }
2054
2055         /* Setup our intr mask. */
2056         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2057                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2058                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2059
2060         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2061                 sc->imask |= ATH9K_INT_GTT;
2062
2063         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2064                 sc->imask |= ATH9K_INT_CST;
2065
2066         ath_cache_conf_rate(sc, &hw->conf);
2067
2068         sc->sc_flags &= ~SC_OP_INVALID;
2069
2070         /* Disable BMISS interrupt when we're not associated */
2071         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2072         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2073
2074         ieee80211_wake_queues(hw);
2075
2076 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2077         r = ath_start_rfkill_poll(sc);
2078 #endif
2079
2080 mutex_unlock:
2081         mutex_unlock(&sc->mutex);
2082
2083         return r;
2084 }
2085
2086 static int ath9k_tx(struct ieee80211_hw *hw,
2087                     struct sk_buff *skb)
2088 {
2089         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2090         struct ath_wiphy *aphy = hw->priv;
2091         struct ath_softc *sc = aphy->sc;
2092         struct ath_tx_control txctl;
2093         int hdrlen, padsize;
2094
2095         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2096                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2097                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2098                 goto exit;
2099         }
2100
2101         if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2102                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2103                 /*
2104                  * mac80211 does not set PM field for normal data frames, so we
2105                  * need to update that based on the current PS mode.
2106                  */
2107                 if (ieee80211_is_data(hdr->frame_control) &&
2108                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2109                     !ieee80211_has_pm(hdr->frame_control)) {
2110                         DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2111                                 "while in PS mode\n");
2112                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2113                 }
2114         }
2115
2116         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2117                 /*
2118                  * We are using PS-Poll and mac80211 can request TX while in
2119                  * power save mode. Need to wake up hardware for the TX to be
2120                  * completed and if needed, also for RX of buffered frames.
2121                  */
2122                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2123                 ath9k_ps_wakeup(sc);
2124                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2125                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2126                         DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2127                                 "buffered frame\n");
2128                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2129                 } else {
2130                         DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2131                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2132                 }
2133                 /*
2134                  * The actual restore operation will happen only after
2135                  * the sc_flags bit is cleared. We are just dropping
2136                  * the ps_usecount here.
2137                  */
2138                 ath9k_ps_restore(sc);
2139         }
2140
2141         memset(&txctl, 0, sizeof(struct ath_tx_control));
2142
2143         /*
2144          * As a temporary workaround, assign seq# here; this will likely need
2145          * to be cleaned up to work better with Beacon transmission and virtual
2146          * BSSes.
2147          */
2148         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2149                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2150                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2151                         sc->tx.seq_no += 0x10;
2152                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2153                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2154         }
2155
2156         /* Add the padding after the header if this is not already done */
2157         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2158         if (hdrlen & 3) {
2159                 padsize = hdrlen % 4;
2160                 if (skb_headroom(skb) < padsize)
2161                         return -1;
2162                 skb_push(skb, padsize);
2163                 memmove(skb->data, skb->data + padsize, hdrlen);
2164         }
2165
2166         /* Check if a tx queue is available */
2167
2168         txctl.txq = ath_test_get_txq(sc, skb);
2169         if (!txctl.txq)
2170                 goto exit;
2171
2172         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2173
2174         if (ath_tx_start(hw, skb, &txctl) != 0) {
2175                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2176                 goto exit;
2177         }
2178
2179         return 0;
2180 exit:
2181         dev_kfree_skb_any(skb);
2182         return 0;
2183 }
2184
2185 static void ath9k_stop(struct ieee80211_hw *hw)
2186 {
2187         struct ath_wiphy *aphy = hw->priv;
2188         struct ath_softc *sc = aphy->sc;
2189
2190         aphy->state = ATH_WIPHY_INACTIVE;
2191
2192         if (sc->sc_flags & SC_OP_INVALID) {
2193                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2194                 return;
2195         }
2196
2197         mutex_lock(&sc->mutex);
2198
2199         ieee80211_stop_queues(hw);
2200
2201         if (ath9k_wiphy_started(sc)) {
2202                 mutex_unlock(&sc->mutex);
2203                 return; /* another wiphy still in use */
2204         }
2205
2206         /* make sure h/w will not generate any interrupt
2207          * before setting the invalid flag. */
2208         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2209
2210         if (!(sc->sc_flags & SC_OP_INVALID)) {
2211                 ath_drain_all_txq(sc, false);
2212                 ath_stoprecv(sc);
2213                 ath9k_hw_phy_disable(sc->sc_ah);
2214         } else
2215                 sc->rx.rxlink = NULL;
2216
2217 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2218         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2219                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2220 #endif
2221         /* disable HAL and put h/w to sleep */
2222         ath9k_hw_disable(sc->sc_ah);
2223         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2224
2225         sc->sc_flags |= SC_OP_INVALID;
2226
2227         mutex_unlock(&sc->mutex);
2228
2229         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2230 }
2231
2232 static int ath9k_add_interface(struct ieee80211_hw *hw,
2233                                struct ieee80211_if_init_conf *conf)
2234 {
2235         struct ath_wiphy *aphy = hw->priv;
2236         struct ath_softc *sc = aphy->sc;
2237         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2238         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2239         int ret = 0;
2240
2241         mutex_lock(&sc->mutex);
2242
2243         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2244             sc->nvifs > 0) {
2245                 ret = -ENOBUFS;
2246                 goto out;
2247         }
2248
2249         switch (conf->type) {
2250         case NL80211_IFTYPE_STATION:
2251                 ic_opmode = NL80211_IFTYPE_STATION;
2252                 break;
2253         case NL80211_IFTYPE_ADHOC:
2254         case NL80211_IFTYPE_AP:
2255         case NL80211_IFTYPE_MESH_POINT:
2256                 if (sc->nbcnvifs >= ATH_BCBUF) {
2257                         ret = -ENOBUFS;
2258                         goto out;
2259                 }
2260                 ic_opmode = conf->type;
2261                 break;
2262         default:
2263                 DPRINTF(sc, ATH_DBG_FATAL,
2264                         "Interface type %d not yet supported\n", conf->type);
2265                 ret = -EOPNOTSUPP;
2266                 goto out;
2267         }
2268
2269         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2270
2271         /* Set the VIF opmode */
2272         avp->av_opmode = ic_opmode;
2273         avp->av_bslot = -1;
2274
2275         sc->nvifs++;
2276
2277         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2278                 ath9k_set_bssid_mask(hw);
2279
2280         if (sc->nvifs > 1)
2281                 goto out; /* skip global settings for secondary vif */
2282
2283         if (ic_opmode == NL80211_IFTYPE_AP) {
2284                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2285                 sc->sc_flags |= SC_OP_TSF_RESET;
2286         }
2287
2288         /* Set the device opmode */
2289         sc->sc_ah->opmode = ic_opmode;
2290
2291         /*
2292          * Enable MIB interrupts when there are hardware phy counters.
2293          * Note we only do this (at the moment) for station mode.
2294          */
2295         if ((conf->type == NL80211_IFTYPE_STATION) ||
2296             (conf->type == NL80211_IFTYPE_ADHOC) ||
2297             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2298                 if (ath9k_hw_phycounters(sc->sc_ah))
2299                         sc->imask |= ATH9K_INT_MIB;
2300                 sc->imask |= ATH9K_INT_TSFOOR;
2301         }
2302
2303         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2304
2305         if (conf->type == NL80211_IFTYPE_AP)
2306                 ath_start_ani(sc);
2307
2308 out:
2309         mutex_unlock(&sc->mutex);
2310         return ret;
2311 }
2312
2313 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2314                                    struct ieee80211_if_init_conf *conf)
2315 {
2316         struct ath_wiphy *aphy = hw->priv;
2317         struct ath_softc *sc = aphy->sc;
2318         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2319         int i;
2320
2321         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2322
2323         mutex_lock(&sc->mutex);
2324
2325         /* Stop ANI */
2326         del_timer_sync(&sc->ani.timer);
2327
2328         /* Reclaim beacon resources */
2329         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2330             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2331             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2332                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2333                 ath_beacon_return(sc, avp);
2334         }
2335
2336         sc->sc_flags &= ~SC_OP_BEACONS;
2337
2338         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2339                 if (sc->beacon.bslot[i] == conf->vif) {
2340                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2341                                "slot\n", __func__);
2342                         sc->beacon.bslot[i] = NULL;
2343                         sc->beacon.bslot_aphy[i] = NULL;
2344                 }
2345         }
2346
2347         sc->nvifs--;
2348
2349         mutex_unlock(&sc->mutex);
2350 }
2351
2352 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2353 {
2354         struct ath_wiphy *aphy = hw->priv;
2355         struct ath_softc *sc = aphy->sc;
2356         struct ieee80211_conf *conf = &hw->conf;
2357         struct ath_hw *ah = sc->sc_ah;
2358
2359         mutex_lock(&sc->mutex);
2360
2361         if (changed & IEEE80211_CONF_CHANGE_PS) {
2362                 if (conf->flags & IEEE80211_CONF_PS) {
2363                         if (!(ah->caps.hw_caps &
2364                               ATH9K_HW_CAP_AUTOSLEEP)) {
2365                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2366                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2367                                         ath9k_hw_set_interrupts(sc->sc_ah,
2368                                                         sc->imask);
2369                                 }
2370                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2371                         }
2372                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2373                 } else {
2374                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2375                         if (!(ah->caps.hw_caps &
2376                               ATH9K_HW_CAP_AUTOSLEEP)) {
2377                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2378                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2379                                                   SC_OP_WAIT_FOR_CAB |
2380                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2381                                                   SC_OP_WAIT_FOR_TX_ACK);
2382                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2383                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2384                                         ath9k_hw_set_interrupts(sc->sc_ah,
2385                                                         sc->imask);
2386                                 }
2387                         }
2388                 }
2389         }
2390
2391         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2392                 struct ieee80211_channel *curchan = hw->conf.channel;
2393                 int pos = curchan->hw_value;
2394
2395                 aphy->chan_idx = pos;
2396                 aphy->chan_is_ht = conf_is_ht(conf);
2397
2398                 if (aphy->state == ATH_WIPHY_SCAN ||
2399                     aphy->state == ATH_WIPHY_ACTIVE)
2400                         ath9k_wiphy_pause_all_forced(sc, aphy);
2401                 else {
2402                         /*
2403                          * Do not change operational channel based on a paused
2404                          * wiphy changes.
2405                          */
2406                         goto skip_chan_change;
2407                 }
2408
2409                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2410                         curchan->center_freq);
2411
2412                 /* XXX: remove me eventualy */
2413                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2414
2415                 ath_update_chainmask(sc, conf_is_ht(conf));
2416
2417                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2418                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2419                         mutex_unlock(&sc->mutex);
2420                         return -EINVAL;
2421                 }
2422         }
2423
2424 skip_chan_change:
2425         if (changed & IEEE80211_CONF_CHANGE_POWER)
2426                 sc->config.txpowlimit = 2 * conf->power_level;
2427
2428         mutex_unlock(&sc->mutex);
2429
2430         return 0;
2431 }
2432
2433 #define SUPPORTED_FILTERS                       \
2434         (FIF_PROMISC_IN_BSS |                   \
2435         FIF_ALLMULTI |                          \
2436         FIF_CONTROL |                           \
2437         FIF_OTHER_BSS |                         \
2438         FIF_BCN_PRBRESP_PROMISC |               \
2439         FIF_FCSFAIL)
2440
2441 /* FIXME: sc->sc_full_reset ? */
2442 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2443                                    unsigned int changed_flags,
2444                                    unsigned int *total_flags,
2445                                    int mc_count,
2446                                    struct dev_mc_list *mclist)
2447 {
2448         struct ath_wiphy *aphy = hw->priv;
2449         struct ath_softc *sc = aphy->sc;
2450         u32 rfilt;
2451
2452         changed_flags &= SUPPORTED_FILTERS;
2453         *total_flags &= SUPPORTED_FILTERS;
2454
2455         sc->rx.rxfilter = *total_flags;
2456         ath9k_ps_wakeup(sc);
2457         rfilt = ath_calcrxfilter(sc);
2458         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2459         ath9k_ps_restore(sc);
2460
2461         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2462 }
2463
2464 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2465                              struct ieee80211_vif *vif,
2466                              enum sta_notify_cmd cmd,
2467                              struct ieee80211_sta *sta)
2468 {
2469         struct ath_wiphy *aphy = hw->priv;
2470         struct ath_softc *sc = aphy->sc;
2471
2472         switch (cmd) {
2473         case STA_NOTIFY_ADD:
2474                 ath_node_attach(sc, sta);
2475                 break;
2476         case STA_NOTIFY_REMOVE:
2477                 ath_node_detach(sc, sta);
2478                 break;
2479         default:
2480                 break;
2481         }
2482 }
2483
2484 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2485                          const struct ieee80211_tx_queue_params *params)
2486 {
2487         struct ath_wiphy *aphy = hw->priv;
2488         struct ath_softc *sc = aphy->sc;
2489         struct ath9k_tx_queue_info qi;
2490         int ret = 0, qnum;
2491
2492         if (queue >= WME_NUM_AC)
2493                 return 0;
2494
2495         mutex_lock(&sc->mutex);
2496
2497         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2498
2499         qi.tqi_aifs = params->aifs;
2500         qi.tqi_cwmin = params->cw_min;
2501         qi.tqi_cwmax = params->cw_max;
2502         qi.tqi_burstTime = params->txop;
2503         qnum = ath_get_hal_qnum(queue, sc);
2504
2505         DPRINTF(sc, ATH_DBG_CONFIG,
2506                 "Configure tx [queue/halq] [%d/%d],  "
2507                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2508                 queue, qnum, params->aifs, params->cw_min,
2509                 params->cw_max, params->txop);
2510
2511         ret = ath_txq_update(sc, qnum, &qi);
2512         if (ret)
2513                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2514
2515         mutex_unlock(&sc->mutex);
2516
2517         return ret;
2518 }
2519
2520 static int ath9k_set_key(struct ieee80211_hw *hw,
2521                          enum set_key_cmd cmd,
2522                          struct ieee80211_vif *vif,
2523                          struct ieee80211_sta *sta,
2524                          struct ieee80211_key_conf *key)
2525 {
2526         struct ath_wiphy *aphy = hw->priv;
2527         struct ath_softc *sc = aphy->sc;
2528         int ret = 0;
2529
2530         if (modparam_nohwcrypt)
2531                 return -ENOSPC;
2532
2533         mutex_lock(&sc->mutex);
2534         ath9k_ps_wakeup(sc);
2535         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2536
2537         switch (cmd) {
2538         case SET_KEY:
2539                 ret = ath_key_config(sc, vif, sta, key);
2540                 if (ret >= 0) {
2541                         key->hw_key_idx = ret;
2542                         /* push IV and Michael MIC generation to stack */
2543                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2544                         if (key->alg == ALG_TKIP)
2545                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2546                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2547                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2548                         ret = 0;
2549                 }
2550                 break;
2551         case DISABLE_KEY:
2552                 ath_key_delete(sc, key);
2553                 break;
2554         default:
2555                 ret = -EINVAL;
2556         }
2557
2558         ath9k_ps_restore(sc);
2559         mutex_unlock(&sc->mutex);
2560
2561         return ret;
2562 }
2563
2564 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2565                                    struct ieee80211_vif *vif,
2566                                    struct ieee80211_bss_conf *bss_conf,
2567                                    u32 changed)
2568 {
2569         struct ath_wiphy *aphy = hw->priv;
2570         struct ath_softc *sc = aphy->sc;
2571         struct ath_hw *ah = sc->sc_ah;
2572         struct ath_vif *avp = (void *)vif->drv_priv;
2573         u32 rfilt = 0;
2574         int error, i;
2575
2576         mutex_lock(&sc->mutex);
2577
2578         /*
2579          * TODO: Need to decide which hw opmode to use for
2580          *       multi-interface cases
2581          * XXX: This belongs into add_interface!
2582          */
2583         if (vif->type == NL80211_IFTYPE_AP &&
2584             ah->opmode != NL80211_IFTYPE_AP) {
2585                 ah->opmode = NL80211_IFTYPE_STATION;
2586                 ath9k_hw_setopmode(ah);
2587                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2588                 sc->curaid = 0;
2589                 ath9k_hw_write_associd(sc);
2590                 /* Request full reset to get hw opmode changed properly */
2591                 sc->sc_flags |= SC_OP_FULL_RESET;
2592         }
2593
2594         if ((changed & BSS_CHANGED_BSSID) &&
2595             !is_zero_ether_addr(bss_conf->bssid)) {
2596                 switch (vif->type) {
2597                 case NL80211_IFTYPE_STATION:
2598                 case NL80211_IFTYPE_ADHOC:
2599                 case NL80211_IFTYPE_MESH_POINT:
2600                         /* Set BSSID */
2601                         memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2602                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2603                         sc->curaid = 0;
2604                         ath9k_hw_write_associd(sc);
2605
2606                         /* Set aggregation protection mode parameters */
2607                         sc->config.ath_aggr_prot = 0;
2608
2609                         DPRINTF(sc, ATH_DBG_CONFIG,
2610                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2611                                 rfilt, sc->curbssid, sc->curaid);
2612
2613                         /* need to reconfigure the beacon */
2614                         sc->sc_flags &= ~SC_OP_BEACONS ;
2615
2616                         break;
2617                 default:
2618                         break;
2619                 }
2620         }
2621
2622         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2623             (vif->type == NL80211_IFTYPE_AP) ||
2624             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2625                 if ((changed & BSS_CHANGED_BEACON) ||
2626                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2627                      bss_conf->enable_beacon)) {
2628                         /*
2629                          * Allocate and setup the beacon frame.
2630                          *
2631                          * Stop any previous beacon DMA.  This may be
2632                          * necessary, for example, when an ibss merge
2633                          * causes reconfiguration; we may be called
2634                          * with beacon transmission active.
2635                          */
2636                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2637
2638                         error = ath_beacon_alloc(aphy, vif);
2639                         if (!error)
2640                                 ath_beacon_config(sc, vif);
2641                 }
2642         }
2643
2644         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2645         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2646                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2647                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2648                                 ath9k_hw_keysetmac(sc->sc_ah,
2649                                                    (u16)i,
2650                                                    sc->curbssid);
2651         }
2652
2653         /* Only legacy IBSS for now */
2654         if (vif->type == NL80211_IFTYPE_ADHOC)
2655                 ath_update_chainmask(sc, 0);
2656
2657         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2658                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2659                         bss_conf->use_short_preamble);
2660                 if (bss_conf->use_short_preamble)
2661                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2662                 else
2663                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2664         }
2665
2666         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2667                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2668                         bss_conf->use_cts_prot);
2669                 if (bss_conf->use_cts_prot &&
2670                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2671                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2672                 else
2673                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2674         }
2675
2676         if (changed & BSS_CHANGED_ASSOC) {
2677                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2678                         bss_conf->assoc);
2679                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2680         }
2681
2682         /*
2683          * The HW TSF has to be reset when the beacon interval changes.
2684          * We set the flag here, and ath_beacon_config_ap() would take this
2685          * into account when it gets called through the subsequent
2686          * config_interface() call - with IFCC_BEACON in the changed field.
2687          */
2688
2689         if (changed & BSS_CHANGED_BEACON_INT) {
2690                 sc->sc_flags |= SC_OP_TSF_RESET;
2691                 sc->beacon_interval = bss_conf->beacon_int;
2692         }
2693
2694         mutex_unlock(&sc->mutex);
2695 }
2696
2697 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2698 {
2699         u64 tsf;
2700         struct ath_wiphy *aphy = hw->priv;
2701         struct ath_softc *sc = aphy->sc;
2702
2703         mutex_lock(&sc->mutex);
2704         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2705         mutex_unlock(&sc->mutex);
2706
2707         return tsf;
2708 }
2709
2710 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2711 {
2712         struct ath_wiphy *aphy = hw->priv;
2713         struct ath_softc *sc = aphy->sc;
2714
2715         mutex_lock(&sc->mutex);
2716         ath9k_hw_settsf64(sc->sc_ah, tsf);
2717         mutex_unlock(&sc->mutex);
2718 }
2719
2720 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2721 {
2722         struct ath_wiphy *aphy = hw->priv;
2723         struct ath_softc *sc = aphy->sc;
2724
2725         mutex_lock(&sc->mutex);
2726         ath9k_hw_reset_tsf(sc->sc_ah);
2727         mutex_unlock(&sc->mutex);
2728 }
2729
2730 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2731                               enum ieee80211_ampdu_mlme_action action,
2732                               struct ieee80211_sta *sta,
2733                               u16 tid, u16 *ssn)
2734 {
2735         struct ath_wiphy *aphy = hw->priv;
2736         struct ath_softc *sc = aphy->sc;
2737         int ret = 0;
2738
2739         switch (action) {
2740         case IEEE80211_AMPDU_RX_START:
2741                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2742                         ret = -ENOTSUPP;
2743                 break;
2744         case IEEE80211_AMPDU_RX_STOP:
2745                 break;
2746         case IEEE80211_AMPDU_TX_START:
2747                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2748                 if (ret < 0)
2749                         DPRINTF(sc, ATH_DBG_FATAL,
2750                                 "Unable to start TX aggregation\n");
2751                 else
2752                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2753                 break;
2754         case IEEE80211_AMPDU_TX_STOP:
2755                 ret = ath_tx_aggr_stop(sc, sta, tid);
2756                 if (ret < 0)
2757                         DPRINTF(sc, ATH_DBG_FATAL,
2758                                 "Unable to stop TX aggregation\n");
2759
2760                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2761                 break;
2762         case IEEE80211_AMPDU_TX_OPERATIONAL:
2763                 ath_tx_aggr_resume(sc, sta, tid);
2764                 break;
2765         default:
2766                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2767         }
2768
2769         return ret;
2770 }
2771
2772 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2773 {
2774         struct ath_wiphy *aphy = hw->priv;
2775         struct ath_softc *sc = aphy->sc;
2776
2777         if (ath9k_wiphy_scanning(sc)) {
2778                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2779                        "same time\n");
2780                 /*
2781                  * Do not allow the concurrent scanning state for now. This
2782                  * could be improved with scanning control moved into ath9k.
2783                  */
2784                 return;
2785         }
2786
2787         aphy->state = ATH_WIPHY_SCAN;
2788         ath9k_wiphy_pause_all_forced(sc, aphy);
2789
2790         mutex_lock(&sc->mutex);
2791         sc->sc_flags |= SC_OP_SCANNING;
2792         mutex_unlock(&sc->mutex);
2793 }
2794
2795 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2796 {
2797         struct ath_wiphy *aphy = hw->priv;
2798         struct ath_softc *sc = aphy->sc;
2799
2800         mutex_lock(&sc->mutex);
2801         aphy->state = ATH_WIPHY_ACTIVE;
2802         sc->sc_flags &= ~SC_OP_SCANNING;
2803         sc->sc_flags |= SC_OP_FULL_RESET;
2804         mutex_unlock(&sc->mutex);
2805 }
2806
2807 struct ieee80211_ops ath9k_ops = {
2808         .tx                 = ath9k_tx,
2809         .start              = ath9k_start,
2810         .stop               = ath9k_stop,
2811         .add_interface      = ath9k_add_interface,
2812         .remove_interface   = ath9k_remove_interface,
2813         .config             = ath9k_config,
2814         .configure_filter   = ath9k_configure_filter,
2815         .sta_notify         = ath9k_sta_notify,
2816         .conf_tx            = ath9k_conf_tx,
2817         .bss_info_changed   = ath9k_bss_info_changed,
2818         .set_key            = ath9k_set_key,
2819         .get_tsf            = ath9k_get_tsf,
2820         .set_tsf            = ath9k_set_tsf,
2821         .reset_tsf          = ath9k_reset_tsf,
2822         .ampdu_action       = ath9k_ampdu_action,
2823         .sw_scan_start      = ath9k_sw_scan_start,
2824         .sw_scan_complete   = ath9k_sw_scan_complete,
2825 };
2826
2827 static struct {
2828         u32 version;
2829         const char * name;
2830 } ath_mac_bb_names[] = {
2831         { AR_SREV_VERSION_5416_PCI,     "5416" },
2832         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2833         { AR_SREV_VERSION_9100,         "9100" },
2834         { AR_SREV_VERSION_9160,         "9160" },
2835         { AR_SREV_VERSION_9280,         "9280" },
2836         { AR_SREV_VERSION_9285,         "9285" }
2837 };
2838
2839 static struct {
2840         u16 version;
2841         const char * name;
2842 } ath_rf_names[] = {
2843         { 0,                            "5133" },
2844         { AR_RAD5133_SREV_MAJOR,        "5133" },
2845         { AR_RAD5122_SREV_MAJOR,        "5122" },
2846         { AR_RAD2133_SREV_MAJOR,        "2133" },
2847         { AR_RAD2122_SREV_MAJOR,        "2122" }
2848 };
2849
2850 /*
2851  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2852  */
2853 const char *
2854 ath_mac_bb_name(u32 mac_bb_version)
2855 {
2856         int i;
2857
2858         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2859                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2860                         return ath_mac_bb_names[i].name;
2861                 }
2862         }
2863
2864         return "????";
2865 }
2866
2867 /*
2868  * Return the RF name. "????" is returned if the RF is unknown.
2869  */
2870 const char *
2871 ath_rf_name(u16 rf_version)
2872 {
2873         int i;
2874
2875         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2876                 if (ath_rf_names[i].version == rf_version) {
2877                         return ath_rf_names[i].name;
2878                 }
2879         }
2880
2881         return "????";
2882 }
2883
2884 static int __init ath9k_init(void)
2885 {
2886         int error;
2887
2888         /* Register rate control algorithm */
2889         error = ath_rate_control_register();
2890         if (error != 0) {
2891                 printk(KERN_ERR
2892                         "ath9k: Unable to register rate control "
2893                         "algorithm: %d\n",
2894                         error);
2895                 goto err_out;
2896         }
2897
2898         error = ath9k_debug_create_root();
2899         if (error) {
2900                 printk(KERN_ERR
2901                         "ath9k: Unable to create debugfs root: %d\n",
2902                         error);
2903                 goto err_rate_unregister;
2904         }
2905
2906         error = ath_pci_init();
2907         if (error < 0) {
2908                 printk(KERN_ERR
2909                         "ath9k: No PCI devices found, driver not installed.\n");
2910                 error = -ENODEV;
2911                 goto err_remove_root;
2912         }
2913
2914         error = ath_ahb_init();
2915         if (error < 0) {
2916                 error = -ENODEV;
2917                 goto err_pci_exit;
2918         }
2919
2920         return 0;
2921
2922  err_pci_exit:
2923         ath_pci_exit();
2924
2925  err_remove_root:
2926         ath9k_debug_remove_root();
2927  err_rate_unregister:
2928         ath_rate_control_unregister();
2929  err_out:
2930         return error;
2931 }
2932 module_init(ath9k_init);
2933
2934 static void __exit ath9k_exit(void)
2935 {
2936         ath_ahb_exit();
2937         ath_pci_exit();
2938         ath9k_debug_remove_root();
2939         ath_rate_control_unregister();
2940         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2941 }
2942 module_exit(ath9k_exit);