2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
20 #define ATH_PCI_VERSION "0.1"
22 static char *dev_info = "ath9k";
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
33 /* We use the hw_value as an index into our private channel structure */
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
120 sc->hw_rate_table[ATH9K_MODE_11G];
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
134 sc->hw_rate_table[ATH9K_MODE_11A];
142 static void ath_update_txpow(struct ath_softc *sc)
144 struct ath_hw *ah = sc->sc_ah;
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
155 static u8 parse_mpdudensity(u8 mpdudensity)
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
168 switch (mpdudensity) {
174 /* Our lower layer calculations limit our precision to
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
192 const struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
208 if (rate_table == NULL)
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
217 maxrates = rate_table->rate_cnt;
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
234 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
252 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
255 struct ath_hw *ah = sc->sc_ah;
256 bool fastcc = true, stopped;
257 struct ieee80211_channel *channel = hw->conf.channel;
260 if (sc->sc_flags & SC_OP_INVALID)
266 * This is only performed if the channel settings have
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
274 ath9k_hw_set_interrupts(ah, 0);
275 ath_drain_all_txq(sc, false);
276 stopped = ath_stoprecv(sc);
278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
287 sc->sc_ah->curchan->channel,
288 channel->center_freq, sc->tx_chan_width);
290 spin_lock_bh(&sc->sc_resetlock);
292 r = ath9k_hw_reset(ah, hchan, fastcc);
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
301 spin_unlock_bh(&sc->sc_resetlock);
303 sc->sc_flags &= ~SC_OP_FULL_RESET;
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
312 ath_cache_conf_rate(sc, &hw->conf);
313 ath_update_txpow(sc);
314 ath9k_hw_set_interrupts(ah, sc->imask);
317 ath9k_ps_restore(sc);
322 * This routine performs the periodic noise floor calibration function
323 * that is used to adjust and optimize the chip performance. This
324 * takes environmental changes (location, temperature) into account.
325 * When the task is complete, it reschedules itself depending on the
326 * appropriate interval that was calculated.
328 static void ath_ani_calibrate(unsigned long data)
330 struct ath_softc *sc = (struct ath_softc *)data;
331 struct ath_hw *ah = sc->sc_ah;
332 bool longcal = false;
333 bool shortcal = false;
334 bool aniflag = false;
335 unsigned int timestamp = jiffies_to_msecs(jiffies);
336 u32 cal_interval, short_cal_interval;
338 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
339 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
342 * don't calibrate when we're scanning.
343 * we are most likely not on our home channel.
345 if (sc->sc_flags & SC_OP_SCANNING)
348 /* Only calibrate if awake */
349 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
354 /* Long calibration runs independently of short calibration. */
355 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
357 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
358 sc->ani.longcal_timer = timestamp;
361 /* Short calibration applies only while caldone is false */
362 if (!sc->ani.caldone) {
363 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
365 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
366 sc->ani.shortcal_timer = timestamp;
367 sc->ani.resetcal_timer = timestamp;
370 if ((timestamp - sc->ani.resetcal_timer) >=
371 ATH_RESTART_CALINTERVAL) {
372 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
374 sc->ani.resetcal_timer = timestamp;
378 /* Verify whether we must check ANI */
379 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
381 sc->ani.checkani_timer = timestamp;
384 /* Skip all processing if there's nothing to do. */
385 if (longcal || shortcal || aniflag) {
386 /* Call ANI routine if necessary */
388 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
390 /* Perform calibration if necessary */
391 if (longcal || shortcal) {
392 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
393 sc->rx_chainmask, longcal);
396 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
399 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
400 ah->curchan->channel, ah->curchan->channelFlags,
401 sc->ani.noise_floor);
405 ath9k_ps_restore(sc);
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
413 cal_interval = ATH_LONG_CALINTERVAL;
414 if (sc->sc_ah->config.enable_ani)
415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
416 if (!sc->ani.caldone)
417 cal_interval = min(cal_interval, (u32)short_cal_interval);
419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
422 static void ath_start_ani(struct ath_softc *sc)
424 unsigned long timestamp = jiffies_to_msecs(jiffies);
426 sc->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp;
430 mod_timer(&sc->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
440 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
443 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
447 sc->tx_chainmask = 1;
448 sc->rx_chainmask = 1;
451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
452 sc->tx_chainmask, sc->rx_chainmask);
455 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
459 an = (struct ath_node *)sta->drv_priv;
461 if (sc->sc_flags & SC_OP_TXAGGR) {
462 ath_tx_node_init(sc, an);
463 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
469 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471 struct ath_node *an = (struct ath_node *)sta->drv_priv;
473 if (sc->sc_flags & SC_OP_TXAGGR)
474 ath_tx_node_cleanup(sc, an);
477 static void ath9k_tasklet(unsigned long data)
479 struct ath_softc *sc = (struct ath_softc *)data;
480 u32 status = sc->intrstatus;
484 if (status & ATH9K_INT_FATAL) {
485 ath_reset(sc, false);
486 ath9k_ps_restore(sc);
490 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
491 spin_lock_bh(&sc->rx.rxflushlock);
492 ath_rx_tasklet(sc, 0);
493 spin_unlock_bh(&sc->rx.rxflushlock);
496 if (status & ATH9K_INT_TX)
499 if ((status & ATH9K_INT_TSFOOR) &&
500 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
502 * TSF sync does not look correct; remain awake to sync with
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
509 /* re-enable hardware interrupt */
510 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
511 ath9k_ps_restore(sc);
514 irqreturn_t ath_isr(int irq, void *dev)
516 #define SCHED_INTR ( \
526 struct ath_softc *sc = dev;
527 struct ath_hw *ah = sc->sc_ah;
528 enum ath9k_int status;
532 * The hardware is not ready/present, don't
533 * touch anything. Note this can happen early
534 * on if the IRQ is shared.
536 if (sc->sc_flags & SC_OP_INVALID)
540 /* shared irq, not for us */
542 if (!ath9k_hw_intrpend(ah))
546 * Figure out the reason(s) for the interrupt. Note
547 * that the hal returns a pseudo-ISR that may include
548 * bits we haven't explicitly enabled so we mask the
549 * value to insure we only process bits we requested.
551 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
552 status &= sc->imask; /* discard unasked-for bits */
555 * If there are no status bits set, then this interrupt was not
556 * for me (should have been caught above).
561 /* Cache the status */
562 sc->intrstatus = status;
564 if (status & SCHED_INTR)
568 * If a FATAL or RXORN interrupt is received, we have to reset the
571 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
574 if (status & ATH9K_INT_SWBA)
575 tasklet_schedule(&sc->bcon_tasklet);
577 if (status & ATH9K_INT_TXURN)
578 ath9k_hw_updatetxtriglevel(ah, true);
580 if (status & ATH9K_INT_MIB) {
582 * Disable interrupts until we service the MIB
583 * interrupt; otherwise it will continue to
586 ath9k_hw_set_interrupts(ah, 0);
588 * Let the hal handle the event. We assume
589 * it will clear whatever condition caused
592 ath9k_hw_procmibevent(ah, &sc->nodestats);
593 ath9k_hw_set_interrupts(ah, sc->imask);
596 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
597 if (status & ATH9K_INT_TIM_TIMER) {
598 /* Clear RxAbort bit so that we can
600 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
601 ath9k_hw_setrxabort(sc->sc_ah, 0);
602 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
607 ath_debug_stat_interrupt(sc, status);
610 /* turn off every interrupt except SWBA */
611 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
612 tasklet_schedule(&sc->intr_tq);
620 static u32 ath_get_extchanmode(struct ath_softc *sc,
621 struct ieee80211_channel *chan,
622 enum nl80211_channel_type channel_type)
626 switch (chan->band) {
627 case IEEE80211_BAND_2GHZ:
628 switch(channel_type) {
629 case NL80211_CHAN_NO_HT:
630 case NL80211_CHAN_HT20:
631 chanmode = CHANNEL_G_HT20;
633 case NL80211_CHAN_HT40PLUS:
634 chanmode = CHANNEL_G_HT40PLUS;
636 case NL80211_CHAN_HT40MINUS:
637 chanmode = CHANNEL_G_HT40MINUS;
641 case IEEE80211_BAND_5GHZ:
642 switch(channel_type) {
643 case NL80211_CHAN_NO_HT:
644 case NL80211_CHAN_HT20:
645 chanmode = CHANNEL_A_HT20;
647 case NL80211_CHAN_HT40PLUS:
648 chanmode = CHANNEL_A_HT40PLUS;
650 case NL80211_CHAN_HT40MINUS:
651 chanmode = CHANNEL_A_HT40MINUS;
662 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
663 struct ath9k_keyval *hk, const u8 *addr,
669 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
670 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
674 * Group key installation - only two key cache entries are used
675 * regardless of splitmic capability since group key is only
676 * used either for TX or RX.
679 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
680 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
685 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
688 /* TX and RX keys share the same key cache entry. */
689 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
690 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
691 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
694 /* Separate key cache entries for TX and RX */
696 /* TX key goes at first index, RX key at +32. */
697 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
698 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
699 /* TX MIC entry failed. No need to proceed further */
700 DPRINTF(sc, ATH_DBG_FATAL,
701 "Setting TX MIC Key Failed\n");
705 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
706 /* XXX delete tx key on failure? */
707 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
710 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
715 if (test_bit(i, sc->keymap) ||
716 test_bit(i + 64, sc->keymap))
717 continue; /* At least one part of TKIP key allocated */
719 (test_bit(i + 32, sc->keymap) ||
720 test_bit(i + 64 + 32, sc->keymap)))
721 continue; /* At least one part of TKIP key allocated */
723 /* Found a free slot for a TKIP key */
729 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
733 /* First, try to find slots that would not be available for TKIP. */
735 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
736 if (!test_bit(i, sc->keymap) &&
737 (test_bit(i + 32, sc->keymap) ||
738 test_bit(i + 64, sc->keymap) ||
739 test_bit(i + 64 + 32, sc->keymap)))
741 if (!test_bit(i + 32, sc->keymap) &&
742 (test_bit(i, sc->keymap) ||
743 test_bit(i + 64, sc->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap)))
746 if (!test_bit(i + 64, sc->keymap) &&
747 (test_bit(i , sc->keymap) ||
748 test_bit(i + 32, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
751 if (!test_bit(i + 64 + 32, sc->keymap) &&
752 (test_bit(i, sc->keymap) ||
753 test_bit(i + 32, sc->keymap) ||
754 test_bit(i + 64, sc->keymap)))
758 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
759 if (!test_bit(i, sc->keymap) &&
760 test_bit(i + 64, sc->keymap))
762 if (test_bit(i, sc->keymap) &&
763 !test_bit(i + 64, sc->keymap))
768 /* No partially used TKIP slots, pick any available slot */
769 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
770 /* Do not allow slots that could be needed for TKIP group keys
771 * to be used. This limitation could be removed if we know that
772 * TKIP will not be used. */
773 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
776 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
778 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
782 if (!test_bit(i, sc->keymap))
783 return i; /* Found a free slot for a key */
786 /* No free slot found */
790 static int ath_key_config(struct ath_softc *sc,
791 struct ieee80211_vif *vif,
792 struct ieee80211_sta *sta,
793 struct ieee80211_key_conf *key)
795 struct ath9k_keyval hk;
796 const u8 *mac = NULL;
800 memset(&hk, 0, sizeof(hk));
804 hk.kv_type = ATH9K_CIPHER_WEP;
807 hk.kv_type = ATH9K_CIPHER_TKIP;
810 hk.kv_type = ATH9K_CIPHER_AES_CCM;
816 hk.kv_len = key->keylen;
817 memcpy(hk.kv_val, key->key, key->keylen);
819 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
820 /* For now, use the default keys for broadcast keys. This may
821 * need to change with virtual interfaces. */
823 } else if (key->keyidx) {
828 if (vif->type != NL80211_IFTYPE_AP) {
829 /* Only keyidx 0 should be used with unicast key, but
830 * allow this for client mode for now. */
839 if (key->alg == ALG_TKIP)
840 idx = ath_reserve_key_cache_slot_tkip(sc);
842 idx = ath_reserve_key_cache_slot(sc);
844 return -ENOSPC; /* no free key cache entries */
847 if (key->alg == ALG_TKIP)
848 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
849 vif->type == NL80211_IFTYPE_AP);
851 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
856 set_bit(idx, sc->keymap);
857 if (key->alg == ALG_TKIP) {
858 set_bit(idx + 64, sc->keymap);
860 set_bit(idx + 32, sc->keymap);
861 set_bit(idx + 64 + 32, sc->keymap);
868 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
870 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
871 if (key->hw_key_idx < IEEE80211_WEP_NKID)
874 clear_bit(key->hw_key_idx, sc->keymap);
875 if (key->alg != ALG_TKIP)
878 clear_bit(key->hw_key_idx + 64, sc->keymap);
880 clear_bit(key->hw_key_idx + 32, sc->keymap);
881 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
885 static void setup_ht_cap(struct ath_softc *sc,
886 struct ieee80211_sta_ht_cap *ht_info)
888 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
889 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
891 ht_info->ht_supported = true;
892 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
893 IEEE80211_HT_CAP_SM_PS |
894 IEEE80211_HT_CAP_SGI_40 |
895 IEEE80211_HT_CAP_DSSSCCK40;
897 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
898 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
900 /* set up supported mcs set */
901 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
903 switch(sc->rx_chainmask) {
905 ht_info->mcs.rx_mask[0] = 0xff;
911 ht_info->mcs.rx_mask[0] = 0xff;
912 ht_info->mcs.rx_mask[1] = 0xff;
916 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
919 static void ath9k_bss_assoc_info(struct ath_softc *sc,
920 struct ieee80211_vif *vif,
921 struct ieee80211_bss_conf *bss_conf)
924 if (bss_conf->assoc) {
925 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
926 bss_conf->aid, sc->curbssid);
928 /* New association, store aid */
929 sc->curaid = bss_conf->aid;
930 ath9k_hw_write_associd(sc);
933 * Request a re-configuration of Beacon related timers
934 * on the receipt of the first Beacon frame (i.e.,
935 * after time sync with the AP).
937 sc->sc_flags |= SC_OP_BEACON_SYNC;
939 /* Configure the beacon */
940 ath_beacon_config(sc, vif);
942 /* Reset rssi stats */
943 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
944 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
945 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
946 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
950 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
955 /********************************/
957 /********************************/
959 static void ath_led_blink_work(struct work_struct *work)
961 struct ath_softc *sc = container_of(work, struct ath_softc,
962 ath_led_blink_work.work);
964 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
967 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
968 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
969 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
971 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
972 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
974 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
975 (sc->sc_flags & SC_OP_LED_ON) ?
976 msecs_to_jiffies(sc->led_off_duration) :
977 msecs_to_jiffies(sc->led_on_duration));
979 sc->led_on_duration = sc->led_on_cnt ?
980 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
981 ATH_LED_ON_DURATION_IDLE;
982 sc->led_off_duration = sc->led_off_cnt ?
983 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
984 ATH_LED_OFF_DURATION_IDLE;
985 sc->led_on_cnt = sc->led_off_cnt = 0;
986 if (sc->sc_flags & SC_OP_LED_ON)
987 sc->sc_flags &= ~SC_OP_LED_ON;
989 sc->sc_flags |= SC_OP_LED_ON;
992 static void ath_led_brightness(struct led_classdev *led_cdev,
993 enum led_brightness brightness)
995 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
996 struct ath_softc *sc = led->sc;
998 switch (brightness) {
1000 if (led->led_type == ATH_LED_ASSOC ||
1001 led->led_type == ATH_LED_RADIO) {
1002 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1003 (led->led_type == ATH_LED_RADIO));
1004 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1005 if (led->led_type == ATH_LED_RADIO)
1006 sc->sc_flags &= ~SC_OP_LED_ON;
1012 if (led->led_type == ATH_LED_ASSOC) {
1013 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1014 queue_delayed_work(sc->hw->workqueue,
1015 &sc->ath_led_blink_work, 0);
1016 } else if (led->led_type == ATH_LED_RADIO) {
1017 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1018 sc->sc_flags |= SC_OP_LED_ON;
1028 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1034 led->led_cdev.name = led->name;
1035 led->led_cdev.default_trigger = trigger;
1036 led->led_cdev.brightness_set = ath_led_brightness;
1038 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1040 DPRINTF(sc, ATH_DBG_FATAL,
1041 "Failed to register led:%s", led->name);
1043 led->registered = 1;
1047 static void ath_unregister_led(struct ath_led *led)
1049 if (led->registered) {
1050 led_classdev_unregister(&led->led_cdev);
1051 led->registered = 0;
1055 static void ath_deinit_leds(struct ath_softc *sc)
1057 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1058 ath_unregister_led(&sc->assoc_led);
1059 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1060 ath_unregister_led(&sc->tx_led);
1061 ath_unregister_led(&sc->rx_led);
1062 ath_unregister_led(&sc->radio_led);
1063 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1066 static void ath_init_leds(struct ath_softc *sc)
1071 /* Configure gpio 1 for output */
1072 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1073 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1074 /* LED off, active low */
1075 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1077 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1079 trigger = ieee80211_get_radio_led_name(sc->hw);
1080 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1081 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1082 ret = ath_register_led(sc, &sc->radio_led, trigger);
1083 sc->radio_led.led_type = ATH_LED_RADIO;
1087 trigger = ieee80211_get_assoc_led_name(sc->hw);
1088 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1089 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1090 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1091 sc->assoc_led.led_type = ATH_LED_ASSOC;
1095 trigger = ieee80211_get_tx_led_name(sc->hw);
1096 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1097 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1098 ret = ath_register_led(sc, &sc->tx_led, trigger);
1099 sc->tx_led.led_type = ATH_LED_TX;
1103 trigger = ieee80211_get_rx_led_name(sc->hw);
1104 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1105 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1106 ret = ath_register_led(sc, &sc->rx_led, trigger);
1107 sc->rx_led.led_type = ATH_LED_RX;
1114 ath_deinit_leds(sc);
1117 void ath_radio_enable(struct ath_softc *sc)
1119 struct ath_hw *ah = sc->sc_ah;
1120 struct ieee80211_channel *channel = sc->hw->conf.channel;
1123 ath9k_ps_wakeup(sc);
1124 ath9k_hw_configpcipowersave(ah, 0);
1127 ah->curchan = ath_get_curchannel(sc, sc->hw);
1129 spin_lock_bh(&sc->sc_resetlock);
1130 r = ath9k_hw_reset(ah, ah->curchan, false);
1132 DPRINTF(sc, ATH_DBG_FATAL,
1133 "Unable to reset channel %u (%uMhz) ",
1134 "reset status %d\n",
1135 channel->center_freq, r);
1137 spin_unlock_bh(&sc->sc_resetlock);
1139 ath_update_txpow(sc);
1140 if (ath_startrecv(sc) != 0) {
1141 DPRINTF(sc, ATH_DBG_FATAL,
1142 "Unable to restart recv logic\n");
1146 if (sc->sc_flags & SC_OP_BEACONS)
1147 ath_beacon_config(sc, NULL); /* restart beacons */
1149 /* Re-Enable interrupts */
1150 ath9k_hw_set_interrupts(ah, sc->imask);
1153 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1154 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1155 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1157 ieee80211_wake_queues(sc->hw);
1158 ath9k_ps_restore(sc);
1161 void ath_radio_disable(struct ath_softc *sc)
1163 struct ath_hw *ah = sc->sc_ah;
1164 struct ieee80211_channel *channel = sc->hw->conf.channel;
1167 ath9k_ps_wakeup(sc);
1168 ieee80211_stop_queues(sc->hw);
1171 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1172 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1174 /* Disable interrupts */
1175 ath9k_hw_set_interrupts(ah, 0);
1177 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1178 ath_stoprecv(sc); /* turn off frame recv */
1179 ath_flushrecv(sc); /* flush recv queue */
1182 ah->curchan = ath_get_curchannel(sc, sc->hw);
1184 spin_lock_bh(&sc->sc_resetlock);
1185 r = ath9k_hw_reset(ah, ah->curchan, false);
1187 DPRINTF(sc, ATH_DBG_FATAL,
1188 "Unable to reset channel %u (%uMhz) "
1189 "reset status %d\n",
1190 channel->center_freq, r);
1192 spin_unlock_bh(&sc->sc_resetlock);
1194 ath9k_hw_phy_disable(ah);
1195 ath9k_hw_configpcipowersave(ah, 1);
1196 ath9k_ps_restore(sc);
1197 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1200 /*******************/
1202 /*******************/
1204 static bool ath_is_rfkill_set(struct ath_softc *sc)
1206 struct ath_hw *ah = sc->sc_ah;
1208 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1209 ah->rfkill_polarity;
1212 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1214 struct ath_wiphy *aphy = hw->priv;
1215 struct ath_softc *sc = aphy->sc;
1216 bool blocked = !!ath_is_rfkill_set(sc);
1218 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1221 ath_radio_disable(sc);
1223 ath_radio_enable(sc);
1226 static void ath_start_rfkill_poll(struct ath_softc *sc)
1228 struct ath_hw *ah = sc->sc_ah;
1230 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1231 wiphy_rfkill_start_polling(sc->hw->wiphy);
1234 void ath_cleanup(struct ath_softc *sc)
1237 free_irq(sc->irq, sc);
1238 ath_bus_cleanup(sc);
1239 kfree(sc->sec_wiphy);
1240 ieee80211_free_hw(sc->hw);
1243 void ath_detach(struct ath_softc *sc)
1245 struct ieee80211_hw *hw = sc->hw;
1248 ath9k_ps_wakeup(sc);
1250 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1252 ath_deinit_leds(sc);
1253 cancel_work_sync(&sc->chan_work);
1254 cancel_delayed_work_sync(&sc->wiphy_work);
1256 for (i = 0; i < sc->num_sec_wiphy; i++) {
1257 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1260 sc->sec_wiphy[i] = NULL;
1261 ieee80211_unregister_hw(aphy->hw);
1262 ieee80211_free_hw(aphy->hw);
1264 ieee80211_unregister_hw(hw);
1268 tasklet_kill(&sc->intr_tq);
1269 tasklet_kill(&sc->bcon_tasklet);
1271 if (!(sc->sc_flags & SC_OP_INVALID))
1272 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1274 /* cleanup tx queues */
1275 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1276 if (ATH_TXQ_SETUP(sc, i))
1277 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1279 ath9k_hw_detach(sc->sc_ah);
1280 ath9k_exit_debug(sc);
1281 ath9k_ps_restore(sc);
1284 static int ath9k_reg_notifier(struct wiphy *wiphy,
1285 struct regulatory_request *request)
1287 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1288 struct ath_wiphy *aphy = hw->priv;
1289 struct ath_softc *sc = aphy->sc;
1290 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1292 return ath_reg_notifier_apply(wiphy, request, reg);
1295 static int ath_init(u16 devid, struct ath_softc *sc)
1297 struct ath_hw *ah = NULL;
1302 /* XXX: hardware will not be ready until ath_open() being called */
1303 sc->sc_flags |= SC_OP_INVALID;
1305 if (ath9k_init_debug(sc) < 0)
1306 printk(KERN_ERR "Unable to create debugfs files\n");
1308 spin_lock_init(&sc->wiphy_lock);
1309 spin_lock_init(&sc->sc_resetlock);
1310 spin_lock_init(&sc->sc_serial_rw);
1311 mutex_init(&sc->mutex);
1312 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1313 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1317 * Cache line size is used to size and align various
1318 * structures used to communicate with the hardware.
1320 ath_read_cachesize(sc, &csz);
1321 /* XXX assert csz is non-zero */
1322 sc->cachelsz = csz << 2; /* convert to bytes */
1324 ah = ath9k_hw_attach(devid, sc, &status);
1326 DPRINTF(sc, ATH_DBG_FATAL,
1327 "Unable to attach hardware; HAL status %d\n", status);
1333 /* Get the hardware key cache size. */
1334 sc->keymax = ah->caps.keycache_size;
1335 if (sc->keymax > ATH_KEYMAX) {
1336 DPRINTF(sc, ATH_DBG_ANY,
1337 "Warning, using only %u entries in %u key cache\n",
1338 ATH_KEYMAX, sc->keymax);
1339 sc->keymax = ATH_KEYMAX;
1343 * Reset the key cache since some parts do not
1344 * reset the contents on initial power up.
1346 for (i = 0; i < sc->keymax; i++)
1347 ath9k_hw_keyreset(ah, (u16) i);
1352 /* default to MONITOR mode */
1353 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1355 /* Setup rate tables */
1357 ath_rate_attach(sc);
1358 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1359 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1362 * Allocate hardware transmit queues: one queue for
1363 * beacon frames and one data queue for each QoS
1364 * priority. Note that the hal handles reseting
1365 * these queues at the needed time.
1367 sc->beacon.beaconq = ath_beaconq_setup(ah);
1368 if (sc->beacon.beaconq == -1) {
1369 DPRINTF(sc, ATH_DBG_FATAL,
1370 "Unable to setup a beacon xmit queue\n");
1374 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1375 if (sc->beacon.cabq == NULL) {
1376 DPRINTF(sc, ATH_DBG_FATAL,
1377 "Unable to setup CAB xmit queue\n");
1382 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1383 ath_cabq_update(sc);
1385 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1386 sc->tx.hwq_map[i] = -1;
1388 /* Setup data queues */
1389 /* NB: ensure BK queue is the lowest priority h/w queue */
1390 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1391 DPRINTF(sc, ATH_DBG_FATAL,
1392 "Unable to setup xmit queue for BK traffic\n");
1397 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
1399 "Unable to setup xmit queue for BE traffic\n");
1403 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1404 DPRINTF(sc, ATH_DBG_FATAL,
1405 "Unable to setup xmit queue for VI traffic\n");
1409 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1410 DPRINTF(sc, ATH_DBG_FATAL,
1411 "Unable to setup xmit queue for VO traffic\n");
1416 /* Initializes the noise floor to a reasonable default value.
1417 * Later on this will be updated during ANI processing. */
1419 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1420 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1422 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1423 ATH9K_CIPHER_TKIP, NULL)) {
1425 * Whether we should enable h/w TKIP MIC.
1426 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1427 * report WMM capable, so it's always safe to turn on
1428 * TKIP MIC in this case.
1430 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1435 * Check whether the separate key cache entries
1436 * are required to handle both tx+rx MIC keys.
1437 * With split mic keys the number of stations is limited
1438 * to 27 otherwise 59.
1440 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1441 ATH9K_CIPHER_TKIP, NULL)
1442 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1443 ATH9K_CIPHER_MIC, NULL)
1444 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1448 /* turn on mcast key search if possible */
1449 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1450 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1453 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1455 /* 11n Capabilities */
1456 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1457 sc->sc_flags |= SC_OP_TXAGGR;
1458 sc->sc_flags |= SC_OP_RXAGGR;
1461 sc->tx_chainmask = ah->caps.tx_chainmask;
1462 sc->rx_chainmask = ah->caps.rx_chainmask;
1464 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1465 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1467 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1468 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1470 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1472 /* initialize beacon slots */
1473 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1474 sc->beacon.bslot[i] = NULL;
1475 sc->beacon.bslot_aphy[i] = NULL;
1478 /* setup channels and rates */
1480 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1481 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1482 sc->rates[IEEE80211_BAND_2GHZ];
1483 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1484 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1485 ARRAY_SIZE(ath9k_2ghz_chantable);
1487 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1488 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1489 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1490 sc->rates[IEEE80211_BAND_5GHZ];
1491 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1492 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1493 ARRAY_SIZE(ath9k_5ghz_chantable);
1496 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1497 ath9k_hw_btcoex_enable(sc->sc_ah);
1501 /* cleanup tx queues */
1502 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1503 if (ATH_TXQ_SETUP(sc, i))
1504 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1507 ath9k_hw_detach(ah);
1508 ath9k_exit_debug(sc);
1513 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1515 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1516 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1517 IEEE80211_HW_SIGNAL_DBM |
1518 IEEE80211_HW_AMPDU_AGGREGATION |
1519 IEEE80211_HW_SUPPORTS_PS |
1520 IEEE80211_HW_PS_NULLFUNC_STACK |
1521 IEEE80211_HW_SPECTRUM_MGMT;
1523 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1524 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1526 hw->wiphy->interface_modes =
1527 BIT(NL80211_IFTYPE_AP) |
1528 BIT(NL80211_IFTYPE_STATION) |
1529 BIT(NL80211_IFTYPE_ADHOC) |
1530 BIT(NL80211_IFTYPE_MESH_POINT);
1534 hw->channel_change_time = 5000;
1535 hw->max_listen_interval = 10;
1536 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1537 hw->sta_data_size = sizeof(struct ath_node);
1538 hw->vif_data_size = sizeof(struct ath_vif);
1540 hw->rate_control_algorithm = "ath9k_rate_control";
1542 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1543 &sc->sbands[IEEE80211_BAND_2GHZ];
1544 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1545 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1546 &sc->sbands[IEEE80211_BAND_5GHZ];
1549 int ath_attach(u16 devid, struct ath_softc *sc)
1551 struct ieee80211_hw *hw = sc->hw;
1553 struct ath_regulatory *reg;
1555 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1557 error = ath_init(devid, sc);
1561 /* get mac address from hardware and set in mac80211 */
1563 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1565 ath_set_hw_capab(sc, hw);
1567 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1568 ath9k_reg_notifier);
1572 reg = &sc->sc_ah->regulatory;
1574 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1575 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1576 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1577 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1580 /* initialize tx/rx engine */
1581 error = ath_tx_init(sc, ATH_TXBUF);
1585 error = ath_rx_init(sc, ATH_RXBUF);
1589 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1590 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1591 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1593 error = ieee80211_register_hw(hw);
1595 if (!ath_is_world_regd(reg)) {
1596 error = regulatory_hint(hw->wiphy, reg->alpha2);
1601 /* Initialize LED control */
1604 ath_start_rfkill_poll(sc);
1609 /* cleanup tx queues */
1610 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1611 if (ATH_TXQ_SETUP(sc, i))
1612 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1614 ath9k_hw_detach(sc->sc_ah);
1615 ath9k_exit_debug(sc);
1620 int ath_reset(struct ath_softc *sc, bool retry_tx)
1622 struct ath_hw *ah = sc->sc_ah;
1623 struct ieee80211_hw *hw = sc->hw;
1626 ath9k_hw_set_interrupts(ah, 0);
1627 ath_drain_all_txq(sc, retry_tx);
1631 spin_lock_bh(&sc->sc_resetlock);
1632 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1634 DPRINTF(sc, ATH_DBG_FATAL,
1635 "Unable to reset hardware; reset status %d\n", r);
1636 spin_unlock_bh(&sc->sc_resetlock);
1638 if (ath_startrecv(sc) != 0)
1639 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1642 * We may be doing a reset in response to a request
1643 * that changes the channel so update any state that
1644 * might change as a result.
1646 ath_cache_conf_rate(sc, &hw->conf);
1648 ath_update_txpow(sc);
1650 if (sc->sc_flags & SC_OP_BEACONS)
1651 ath_beacon_config(sc, NULL); /* restart beacons */
1653 ath9k_hw_set_interrupts(ah, sc->imask);
1657 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1658 if (ATH_TXQ_SETUP(sc, i)) {
1659 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1660 ath_txq_schedule(sc, &sc->tx.txq[i]);
1661 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1670 * This function will allocate both the DMA descriptor structure, and the
1671 * buffers it contains. These are used to contain the descriptors used
1674 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1675 struct list_head *head, const char *name,
1676 int nbuf, int ndesc)
1678 #define DS2PHYS(_dd, _ds) \
1679 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1680 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1681 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1683 struct ath_desc *ds;
1685 int i, bsize, error;
1687 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1690 INIT_LIST_HEAD(head);
1691 /* ath_desc must be a multiple of DWORDs */
1692 if ((sizeof(struct ath_desc) % 4) != 0) {
1693 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1694 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1699 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1702 * Need additional DMA memory because we can't use
1703 * descriptors that cross the 4K page boundary. Assume
1704 * one skipped descriptor per 4K page.
1706 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1708 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1711 while (ndesc_skipped) {
1712 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1713 dd->dd_desc_len += dma_len;
1715 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1719 /* allocate descriptors */
1720 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1721 &dd->dd_desc_paddr, GFP_KERNEL);
1722 if (dd->dd_desc == NULL) {
1727 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1728 name, ds, (u32) dd->dd_desc_len,
1729 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1731 /* allocate buffers */
1732 bsize = sizeof(struct ath_buf) * nbuf;
1733 bf = kzalloc(bsize, GFP_KERNEL);
1740 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1742 bf->bf_daddr = DS2PHYS(dd, ds);
1744 if (!(sc->sc_ah->caps.hw_caps &
1745 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1747 * Skip descriptor addresses which can cause 4KB
1748 * boundary crossing (addr + length) with a 32 dword
1751 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1752 ASSERT((caddr_t) bf->bf_desc <
1753 ((caddr_t) dd->dd_desc +
1758 bf->bf_daddr = DS2PHYS(dd, ds);
1761 list_add_tail(&bf->list, head);
1765 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1768 memset(dd, 0, sizeof(*dd));
1770 #undef ATH_DESC_4KB_BOUND_CHECK
1771 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1775 void ath_descdma_cleanup(struct ath_softc *sc,
1776 struct ath_descdma *dd,
1777 struct list_head *head)
1779 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1782 INIT_LIST_HEAD(head);
1783 kfree(dd->dd_bufptr);
1784 memset(dd, 0, sizeof(*dd));
1787 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1793 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1796 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1799 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1802 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1805 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1812 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1817 case ATH9K_WME_AC_VO:
1820 case ATH9K_WME_AC_VI:
1823 case ATH9K_WME_AC_BE:
1826 case ATH9K_WME_AC_BK:
1837 /* XXX: Remove me once we don't depend on ath9k_channel for all
1838 * this redundant data */
1839 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1840 struct ath9k_channel *ichan)
1842 struct ieee80211_channel *chan = hw->conf.channel;
1843 struct ieee80211_conf *conf = &hw->conf;
1845 ichan->channel = chan->center_freq;
1848 if (chan->band == IEEE80211_BAND_2GHZ) {
1849 ichan->chanmode = CHANNEL_G;
1850 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1852 ichan->chanmode = CHANNEL_A;
1853 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1856 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1858 if (conf_is_ht(conf)) {
1859 if (conf_is_ht40(conf))
1860 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1862 ichan->chanmode = ath_get_extchanmode(sc, chan,
1863 conf->channel_type);
1867 /**********************/
1868 /* mac80211 callbacks */
1869 /**********************/
1871 static int ath9k_start(struct ieee80211_hw *hw)
1873 struct ath_wiphy *aphy = hw->priv;
1874 struct ath_softc *sc = aphy->sc;
1875 struct ieee80211_channel *curchan = hw->conf.channel;
1876 struct ath9k_channel *init_channel;
1879 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1880 "initial channel: %d MHz\n", curchan->center_freq);
1882 mutex_lock(&sc->mutex);
1884 if (ath9k_wiphy_started(sc)) {
1885 if (sc->chan_idx == curchan->hw_value) {
1887 * Already on the operational channel, the new wiphy
1888 * can be marked active.
1890 aphy->state = ATH_WIPHY_ACTIVE;
1891 ieee80211_wake_queues(hw);
1894 * Another wiphy is on another channel, start the new
1895 * wiphy in paused state.
1897 aphy->state = ATH_WIPHY_PAUSED;
1898 ieee80211_stop_queues(hw);
1900 mutex_unlock(&sc->mutex);
1903 aphy->state = ATH_WIPHY_ACTIVE;
1905 /* setup initial channel */
1907 sc->chan_idx = curchan->hw_value;
1909 init_channel = ath_get_curchannel(sc, hw);
1911 /* Reset SERDES registers */
1912 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1915 * The basic interface to setting the hardware in a good
1916 * state is ``reset''. On return the hardware is known to
1917 * be powered up and with interrupts disabled. This must
1918 * be followed by initialization of the appropriate bits
1919 * and then setup of the interrupt mask.
1921 spin_lock_bh(&sc->sc_resetlock);
1922 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1924 DPRINTF(sc, ATH_DBG_FATAL,
1925 "Unable to reset hardware; reset status %d "
1926 "(freq %u MHz)\n", r,
1927 curchan->center_freq);
1928 spin_unlock_bh(&sc->sc_resetlock);
1931 spin_unlock_bh(&sc->sc_resetlock);
1934 * This is needed only to setup initial state
1935 * but it's best done after a reset.
1937 ath_update_txpow(sc);
1940 * Setup the hardware after reset:
1941 * The receive engine is set going.
1942 * Frame transmit is handled entirely
1943 * in the frame output path; there's nothing to do
1944 * here except setup the interrupt mask.
1946 if (ath_startrecv(sc) != 0) {
1947 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1952 /* Setup our intr mask. */
1953 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1954 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1955 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1957 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1958 sc->imask |= ATH9K_INT_GTT;
1960 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1961 sc->imask |= ATH9K_INT_CST;
1963 ath_cache_conf_rate(sc, &hw->conf);
1965 sc->sc_flags &= ~SC_OP_INVALID;
1967 /* Disable BMISS interrupt when we're not associated */
1968 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1969 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
1971 ieee80211_wake_queues(hw);
1974 mutex_unlock(&sc->mutex);
1979 static int ath9k_tx(struct ieee80211_hw *hw,
1980 struct sk_buff *skb)
1982 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1983 struct ath_wiphy *aphy = hw->priv;
1984 struct ath_softc *sc = aphy->sc;
1985 struct ath_tx_control txctl;
1986 int hdrlen, padsize;
1988 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
1989 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
1990 "%d\n", wiphy_name(hw->wiphy), aphy->state);
1994 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
1995 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1997 * mac80211 does not set PM field for normal data frames, so we
1998 * need to update that based on the current PS mode.
2000 if (ieee80211_is_data(hdr->frame_control) &&
2001 !ieee80211_is_nullfunc(hdr->frame_control) &&
2002 !ieee80211_has_pm(hdr->frame_control)) {
2003 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2004 "while in PS mode\n");
2005 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2009 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2011 * We are using PS-Poll and mac80211 can request TX while in
2012 * power save mode. Need to wake up hardware for the TX to be
2013 * completed and if needed, also for RX of buffered frames.
2015 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2016 ath9k_ps_wakeup(sc);
2017 ath9k_hw_setrxabort(sc->sc_ah, 0);
2018 if (ieee80211_is_pspoll(hdr->frame_control)) {
2019 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2020 "buffered frame\n");
2021 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2023 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2024 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2027 * The actual restore operation will happen only after
2028 * the sc_flags bit is cleared. We are just dropping
2029 * the ps_usecount here.
2031 ath9k_ps_restore(sc);
2034 memset(&txctl, 0, sizeof(struct ath_tx_control));
2037 * As a temporary workaround, assign seq# here; this will likely need
2038 * to be cleaned up to work better with Beacon transmission and virtual
2041 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2042 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2043 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2044 sc->tx.seq_no += 0x10;
2045 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2046 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2049 /* Add the padding after the header if this is not already done */
2050 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2052 padsize = hdrlen % 4;
2053 if (skb_headroom(skb) < padsize)
2055 skb_push(skb, padsize);
2056 memmove(skb->data, skb->data + padsize, hdrlen);
2059 /* Check if a tx queue is available */
2061 txctl.txq = ath_test_get_txq(sc, skb);
2065 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2067 if (ath_tx_start(hw, skb, &txctl) != 0) {
2068 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2074 dev_kfree_skb_any(skb);
2078 static void ath9k_stop(struct ieee80211_hw *hw)
2080 struct ath_wiphy *aphy = hw->priv;
2081 struct ath_softc *sc = aphy->sc;
2083 aphy->state = ATH_WIPHY_INACTIVE;
2085 if (sc->sc_flags & SC_OP_INVALID) {
2086 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2090 mutex_lock(&sc->mutex);
2092 ieee80211_stop_queues(hw);
2094 if (ath9k_wiphy_started(sc)) {
2095 mutex_unlock(&sc->mutex);
2096 return; /* another wiphy still in use */
2099 /* make sure h/w will not generate any interrupt
2100 * before setting the invalid flag. */
2101 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2103 if (!(sc->sc_flags & SC_OP_INVALID)) {
2104 ath_drain_all_txq(sc, false);
2106 ath9k_hw_phy_disable(sc->sc_ah);
2108 sc->rx.rxlink = NULL;
2110 wiphy_rfkill_stop_polling(sc->hw->wiphy);
2112 /* disable HAL and put h/w to sleep */
2113 ath9k_hw_disable(sc->sc_ah);
2114 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2116 sc->sc_flags |= SC_OP_INVALID;
2118 mutex_unlock(&sc->mutex);
2120 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2123 static int ath9k_add_interface(struct ieee80211_hw *hw,
2124 struct ieee80211_if_init_conf *conf)
2126 struct ath_wiphy *aphy = hw->priv;
2127 struct ath_softc *sc = aphy->sc;
2128 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2129 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2132 mutex_lock(&sc->mutex);
2134 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2140 switch (conf->type) {
2141 case NL80211_IFTYPE_STATION:
2142 ic_opmode = NL80211_IFTYPE_STATION;
2144 case NL80211_IFTYPE_ADHOC:
2145 case NL80211_IFTYPE_AP:
2146 case NL80211_IFTYPE_MESH_POINT:
2147 if (sc->nbcnvifs >= ATH_BCBUF) {
2151 ic_opmode = conf->type;
2154 DPRINTF(sc, ATH_DBG_FATAL,
2155 "Interface type %d not yet supported\n", conf->type);
2160 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2162 /* Set the VIF opmode */
2163 avp->av_opmode = ic_opmode;
2168 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2169 ath9k_set_bssid_mask(hw);
2172 goto out; /* skip global settings for secondary vif */
2174 if (ic_opmode == NL80211_IFTYPE_AP) {
2175 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2176 sc->sc_flags |= SC_OP_TSF_RESET;
2179 /* Set the device opmode */
2180 sc->sc_ah->opmode = ic_opmode;
2183 * Enable MIB interrupts when there are hardware phy counters.
2184 * Note we only do this (at the moment) for station mode.
2186 if ((conf->type == NL80211_IFTYPE_STATION) ||
2187 (conf->type == NL80211_IFTYPE_ADHOC) ||
2188 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2189 if (ath9k_hw_phycounters(sc->sc_ah))
2190 sc->imask |= ATH9K_INT_MIB;
2191 sc->imask |= ATH9K_INT_TSFOOR;
2194 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2196 if (conf->type == NL80211_IFTYPE_AP)
2200 mutex_unlock(&sc->mutex);
2204 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2205 struct ieee80211_if_init_conf *conf)
2207 struct ath_wiphy *aphy = hw->priv;
2208 struct ath_softc *sc = aphy->sc;
2209 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2212 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2214 mutex_lock(&sc->mutex);
2217 del_timer_sync(&sc->ani.timer);
2219 /* Reclaim beacon resources */
2220 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2221 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2222 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2223 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2224 ath_beacon_return(sc, avp);
2227 sc->sc_flags &= ~SC_OP_BEACONS;
2229 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2230 if (sc->beacon.bslot[i] == conf->vif) {
2231 printk(KERN_DEBUG "%s: vif had allocated beacon "
2232 "slot\n", __func__);
2233 sc->beacon.bslot[i] = NULL;
2234 sc->beacon.bslot_aphy[i] = NULL;
2240 mutex_unlock(&sc->mutex);
2243 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2245 struct ath_wiphy *aphy = hw->priv;
2246 struct ath_softc *sc = aphy->sc;
2247 struct ieee80211_conf *conf = &hw->conf;
2248 struct ath_hw *ah = sc->sc_ah;
2250 mutex_lock(&sc->mutex);
2252 if (changed & IEEE80211_CONF_CHANGE_PS) {
2253 if (conf->flags & IEEE80211_CONF_PS) {
2254 if (!(ah->caps.hw_caps &
2255 ATH9K_HW_CAP_AUTOSLEEP)) {
2256 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2257 sc->imask |= ATH9K_INT_TIM_TIMER;
2258 ath9k_hw_set_interrupts(sc->sc_ah,
2261 ath9k_hw_setrxabort(sc->sc_ah, 1);
2263 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2265 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2266 if (!(ah->caps.hw_caps &
2267 ATH9K_HW_CAP_AUTOSLEEP)) {
2268 ath9k_hw_setrxabort(sc->sc_ah, 0);
2269 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2270 SC_OP_WAIT_FOR_CAB |
2271 SC_OP_WAIT_FOR_PSPOLL_DATA |
2272 SC_OP_WAIT_FOR_TX_ACK);
2273 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2274 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2275 ath9k_hw_set_interrupts(sc->sc_ah,
2282 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2283 struct ieee80211_channel *curchan = hw->conf.channel;
2284 int pos = curchan->hw_value;
2286 aphy->chan_idx = pos;
2287 aphy->chan_is_ht = conf_is_ht(conf);
2289 if (aphy->state == ATH_WIPHY_SCAN ||
2290 aphy->state == ATH_WIPHY_ACTIVE)
2291 ath9k_wiphy_pause_all_forced(sc, aphy);
2294 * Do not change operational channel based on a paused
2297 goto skip_chan_change;
2300 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2301 curchan->center_freq);
2303 /* XXX: remove me eventualy */
2304 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2306 ath_update_chainmask(sc, conf_is_ht(conf));
2308 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2309 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2310 mutex_unlock(&sc->mutex);
2316 if (changed & IEEE80211_CONF_CHANGE_POWER)
2317 sc->config.txpowlimit = 2 * conf->power_level;
2319 mutex_unlock(&sc->mutex);
2324 #define SUPPORTED_FILTERS \
2325 (FIF_PROMISC_IN_BSS | \
2329 FIF_BCN_PRBRESP_PROMISC | \
2332 /* FIXME: sc->sc_full_reset ? */
2333 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2334 unsigned int changed_flags,
2335 unsigned int *total_flags,
2337 struct dev_mc_list *mclist)
2339 struct ath_wiphy *aphy = hw->priv;
2340 struct ath_softc *sc = aphy->sc;
2343 changed_flags &= SUPPORTED_FILTERS;
2344 *total_flags &= SUPPORTED_FILTERS;
2346 sc->rx.rxfilter = *total_flags;
2347 ath9k_ps_wakeup(sc);
2348 rfilt = ath_calcrxfilter(sc);
2349 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2350 ath9k_ps_restore(sc);
2352 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2355 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2356 struct ieee80211_vif *vif,
2357 enum sta_notify_cmd cmd,
2358 struct ieee80211_sta *sta)
2360 struct ath_wiphy *aphy = hw->priv;
2361 struct ath_softc *sc = aphy->sc;
2364 case STA_NOTIFY_ADD:
2365 ath_node_attach(sc, sta);
2367 case STA_NOTIFY_REMOVE:
2368 ath_node_detach(sc, sta);
2375 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2376 const struct ieee80211_tx_queue_params *params)
2378 struct ath_wiphy *aphy = hw->priv;
2379 struct ath_softc *sc = aphy->sc;
2380 struct ath9k_tx_queue_info qi;
2383 if (queue >= WME_NUM_AC)
2386 mutex_lock(&sc->mutex);
2388 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2390 qi.tqi_aifs = params->aifs;
2391 qi.tqi_cwmin = params->cw_min;
2392 qi.tqi_cwmax = params->cw_max;
2393 qi.tqi_burstTime = params->txop;
2394 qnum = ath_get_hal_qnum(queue, sc);
2396 DPRINTF(sc, ATH_DBG_CONFIG,
2397 "Configure tx [queue/halq] [%d/%d], "
2398 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2399 queue, qnum, params->aifs, params->cw_min,
2400 params->cw_max, params->txop);
2402 ret = ath_txq_update(sc, qnum, &qi);
2404 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2406 mutex_unlock(&sc->mutex);
2411 static int ath9k_set_key(struct ieee80211_hw *hw,
2412 enum set_key_cmd cmd,
2413 struct ieee80211_vif *vif,
2414 struct ieee80211_sta *sta,
2415 struct ieee80211_key_conf *key)
2417 struct ath_wiphy *aphy = hw->priv;
2418 struct ath_softc *sc = aphy->sc;
2421 if (modparam_nohwcrypt)
2424 mutex_lock(&sc->mutex);
2425 ath9k_ps_wakeup(sc);
2426 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2430 ret = ath_key_config(sc, vif, sta, key);
2432 key->hw_key_idx = ret;
2433 /* push IV and Michael MIC generation to stack */
2434 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2435 if (key->alg == ALG_TKIP)
2436 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2437 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2438 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2443 ath_key_delete(sc, key);
2449 ath9k_ps_restore(sc);
2450 mutex_unlock(&sc->mutex);
2455 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2456 struct ieee80211_vif *vif,
2457 struct ieee80211_bss_conf *bss_conf,
2460 struct ath_wiphy *aphy = hw->priv;
2461 struct ath_softc *sc = aphy->sc;
2462 struct ath_hw *ah = sc->sc_ah;
2463 struct ath_vif *avp = (void *)vif->drv_priv;
2467 mutex_lock(&sc->mutex);
2470 * TODO: Need to decide which hw opmode to use for
2471 * multi-interface cases
2472 * XXX: This belongs into add_interface!
2474 if (vif->type == NL80211_IFTYPE_AP &&
2475 ah->opmode != NL80211_IFTYPE_AP) {
2476 ah->opmode = NL80211_IFTYPE_STATION;
2477 ath9k_hw_setopmode(ah);
2478 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2480 ath9k_hw_write_associd(sc);
2481 /* Request full reset to get hw opmode changed properly */
2482 sc->sc_flags |= SC_OP_FULL_RESET;
2485 if ((changed & BSS_CHANGED_BSSID) &&
2486 !is_zero_ether_addr(bss_conf->bssid)) {
2487 switch (vif->type) {
2488 case NL80211_IFTYPE_STATION:
2489 case NL80211_IFTYPE_ADHOC:
2490 case NL80211_IFTYPE_MESH_POINT:
2492 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2493 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2495 ath9k_hw_write_associd(sc);
2497 /* Set aggregation protection mode parameters */
2498 sc->config.ath_aggr_prot = 0;
2500 DPRINTF(sc, ATH_DBG_CONFIG,
2501 "RX filter 0x%x bssid %pM aid 0x%x\n",
2502 rfilt, sc->curbssid, sc->curaid);
2504 /* need to reconfigure the beacon */
2505 sc->sc_flags &= ~SC_OP_BEACONS ;
2513 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2514 (vif->type == NL80211_IFTYPE_AP) ||
2515 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2516 if ((changed & BSS_CHANGED_BEACON) ||
2517 (changed & BSS_CHANGED_BEACON_ENABLED &&
2518 bss_conf->enable_beacon)) {
2520 * Allocate and setup the beacon frame.
2522 * Stop any previous beacon DMA. This may be
2523 * necessary, for example, when an ibss merge
2524 * causes reconfiguration; we may be called
2525 * with beacon transmission active.
2527 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2529 error = ath_beacon_alloc(aphy, vif);
2531 ath_beacon_config(sc, vif);
2535 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2536 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2537 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2538 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2539 ath9k_hw_keysetmac(sc->sc_ah,
2544 /* Only legacy IBSS for now */
2545 if (vif->type == NL80211_IFTYPE_ADHOC)
2546 ath_update_chainmask(sc, 0);
2548 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2549 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2550 bss_conf->use_short_preamble);
2551 if (bss_conf->use_short_preamble)
2552 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2554 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2557 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2558 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2559 bss_conf->use_cts_prot);
2560 if (bss_conf->use_cts_prot &&
2561 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2562 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2564 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2567 if (changed & BSS_CHANGED_ASSOC) {
2568 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2570 ath9k_bss_assoc_info(sc, vif, bss_conf);
2574 * The HW TSF has to be reset when the beacon interval changes.
2575 * We set the flag here, and ath_beacon_config_ap() would take this
2576 * into account when it gets called through the subsequent
2577 * config_interface() call - with IFCC_BEACON in the changed field.
2580 if (changed & BSS_CHANGED_BEACON_INT) {
2581 sc->sc_flags |= SC_OP_TSF_RESET;
2582 sc->beacon_interval = bss_conf->beacon_int;
2585 mutex_unlock(&sc->mutex);
2588 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2591 struct ath_wiphy *aphy = hw->priv;
2592 struct ath_softc *sc = aphy->sc;
2594 mutex_lock(&sc->mutex);
2595 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2596 mutex_unlock(&sc->mutex);
2601 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2603 struct ath_wiphy *aphy = hw->priv;
2604 struct ath_softc *sc = aphy->sc;
2606 mutex_lock(&sc->mutex);
2607 ath9k_hw_settsf64(sc->sc_ah, tsf);
2608 mutex_unlock(&sc->mutex);
2611 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2613 struct ath_wiphy *aphy = hw->priv;
2614 struct ath_softc *sc = aphy->sc;
2616 mutex_lock(&sc->mutex);
2617 ath9k_hw_reset_tsf(sc->sc_ah);
2618 mutex_unlock(&sc->mutex);
2621 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2622 enum ieee80211_ampdu_mlme_action action,
2623 struct ieee80211_sta *sta,
2626 struct ath_wiphy *aphy = hw->priv;
2627 struct ath_softc *sc = aphy->sc;
2631 case IEEE80211_AMPDU_RX_START:
2632 if (!(sc->sc_flags & SC_OP_RXAGGR))
2635 case IEEE80211_AMPDU_RX_STOP:
2637 case IEEE80211_AMPDU_TX_START:
2638 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2640 DPRINTF(sc, ATH_DBG_FATAL,
2641 "Unable to start TX aggregation\n");
2643 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2645 case IEEE80211_AMPDU_TX_STOP:
2646 ret = ath_tx_aggr_stop(sc, sta, tid);
2648 DPRINTF(sc, ATH_DBG_FATAL,
2649 "Unable to stop TX aggregation\n");
2651 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2653 case IEEE80211_AMPDU_TX_OPERATIONAL:
2654 ath_tx_aggr_resume(sc, sta, tid);
2657 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2663 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2665 struct ath_wiphy *aphy = hw->priv;
2666 struct ath_softc *sc = aphy->sc;
2668 if (ath9k_wiphy_scanning(sc)) {
2669 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2672 * Do not allow the concurrent scanning state for now. This
2673 * could be improved with scanning control moved into ath9k.
2678 aphy->state = ATH_WIPHY_SCAN;
2679 ath9k_wiphy_pause_all_forced(sc, aphy);
2681 mutex_lock(&sc->mutex);
2682 sc->sc_flags |= SC_OP_SCANNING;
2683 mutex_unlock(&sc->mutex);
2686 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2688 struct ath_wiphy *aphy = hw->priv;
2689 struct ath_softc *sc = aphy->sc;
2691 mutex_lock(&sc->mutex);
2692 aphy->state = ATH_WIPHY_ACTIVE;
2693 sc->sc_flags &= ~SC_OP_SCANNING;
2694 sc->sc_flags |= SC_OP_FULL_RESET;
2695 mutex_unlock(&sc->mutex);
2698 struct ieee80211_ops ath9k_ops = {
2700 .start = ath9k_start,
2702 .add_interface = ath9k_add_interface,
2703 .remove_interface = ath9k_remove_interface,
2704 .config = ath9k_config,
2705 .configure_filter = ath9k_configure_filter,
2706 .sta_notify = ath9k_sta_notify,
2707 .conf_tx = ath9k_conf_tx,
2708 .bss_info_changed = ath9k_bss_info_changed,
2709 .set_key = ath9k_set_key,
2710 .get_tsf = ath9k_get_tsf,
2711 .set_tsf = ath9k_set_tsf,
2712 .reset_tsf = ath9k_reset_tsf,
2713 .ampdu_action = ath9k_ampdu_action,
2714 .sw_scan_start = ath9k_sw_scan_start,
2715 .sw_scan_complete = ath9k_sw_scan_complete,
2716 .rfkill_poll = ath9k_rfkill_poll_state,
2722 } ath_mac_bb_names[] = {
2723 { AR_SREV_VERSION_5416_PCI, "5416" },
2724 { AR_SREV_VERSION_5416_PCIE, "5418" },
2725 { AR_SREV_VERSION_9100, "9100" },
2726 { AR_SREV_VERSION_9160, "9160" },
2727 { AR_SREV_VERSION_9280, "9280" },
2728 { AR_SREV_VERSION_9285, "9285" }
2734 } ath_rf_names[] = {
2736 { AR_RAD5133_SREV_MAJOR, "5133" },
2737 { AR_RAD5122_SREV_MAJOR, "5122" },
2738 { AR_RAD2133_SREV_MAJOR, "2133" },
2739 { AR_RAD2122_SREV_MAJOR, "2122" }
2743 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2746 ath_mac_bb_name(u32 mac_bb_version)
2750 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2751 if (ath_mac_bb_names[i].version == mac_bb_version) {
2752 return ath_mac_bb_names[i].name;
2760 * Return the RF name. "????" is returned if the RF is unknown.
2763 ath_rf_name(u16 rf_version)
2767 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2768 if (ath_rf_names[i].version == rf_version) {
2769 return ath_rf_names[i].name;
2776 static int __init ath9k_init(void)
2780 /* Register rate control algorithm */
2781 error = ath_rate_control_register();
2784 "ath9k: Unable to register rate control "
2790 error = ath9k_debug_create_root();
2793 "ath9k: Unable to create debugfs root: %d\n",
2795 goto err_rate_unregister;
2798 error = ath_pci_init();
2801 "ath9k: No PCI devices found, driver not installed.\n");
2803 goto err_remove_root;
2806 error = ath_ahb_init();
2818 ath9k_debug_remove_root();
2819 err_rate_unregister:
2820 ath_rate_control_unregister();
2824 module_init(ath9k_init);
2826 static void __exit ath9k_exit(void)
2830 ath9k_debug_remove_root();
2831 ath_rate_control_unregister();
2832 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2834 module_exit(ath9k_exit);