drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 static int modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  32
  33 /* We use the hw_value as an index into our private channel structure */
  34
  35 #define CHAN2G(_freq, _idx)  { \
  36         .center_freq = (_freq), \
  37         .hw_value = (_idx), \
  38         .max_power = 30, \
  39 }
  40
  41 #define CHAN5G(_freq, _idx) { \
  42         .band = IEEE80211_BAND_5GHZ, \
  43         .center_freq = (_freq), \
  44         .hw_value = (_idx), \
  45         .max_power = 30, \
  46 }
  47
  48 /* Some 2 GHz radios are actually tunable on 2312-2732
  49  * on 5 MHz steps, we support the channels which we know
  50  * we have calibration data for all cards though to make
  51  * this static */
  52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  53         CHAN2G(2412, 0), /* Channel 1 */
  54         CHAN2G(2417, 1), /* Channel 2 */
  55         CHAN2G(2422, 2), /* Channel 3 */
  56         CHAN2G(2427, 3), /* Channel 4 */
  57         CHAN2G(2432, 4), /* Channel 5 */
  58         CHAN2G(2437, 5), /* Channel 6 */
  59         CHAN2G(2442, 6), /* Channel 7 */
  60         CHAN2G(2447, 7), /* Channel 8 */
  61         CHAN2G(2452, 8), /* Channel 9 */
  62         CHAN2G(2457, 9), /* Channel 10 */
  63         CHAN2G(2462, 10), /* Channel 11 */
  64         CHAN2G(2467, 11), /* Channel 12 */
  65         CHAN2G(2472, 12), /* Channel 13 */
  66         CHAN2G(2484, 13), /* Channel 14 */
  67 };
  68
  69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  70  * on 5 MHz steps, we support the channels which we know
  71  * we have calibration data for all cards though to make
  72  * this static */
  73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  74         /* _We_ call this UNII 1 */
  75         CHAN5G(5180, 14), /* Channel 36 */
  76         CHAN5G(5200, 15), /* Channel 40 */
  77         CHAN5G(5220, 16), /* Channel 44 */
  78         CHAN5G(5240, 17), /* Channel 48 */
  79         /* _We_ call this UNII 2 */
  80         CHAN5G(5260, 18), /* Channel 52 */
  81         CHAN5G(5280, 19), /* Channel 56 */
  82         CHAN5G(5300, 20), /* Channel 60 */
  83         CHAN5G(5320, 21), /* Channel 64 */
  84         /* _We_ call this "Middle band" */
  85         CHAN5G(5500, 22), /* Channel 100 */
  86         CHAN5G(5520, 23), /* Channel 104 */
  87         CHAN5G(5540, 24), /* Channel 108 */
  88         CHAN5G(5560, 25), /* Channel 112 */
  89         CHAN5G(5580, 26), /* Channel 116 */
  90         CHAN5G(5600, 27), /* Channel 120 */
  91         CHAN5G(5620, 28), /* Channel 124 */
  92         CHAN5G(5640, 29), /* Channel 128 */
  93         CHAN5G(5660, 30), /* Channel 132 */
  94         CHAN5G(5680, 31), /* Channel 136 */
  95         CHAN5G(5700, 32), /* Channel 140 */
  96         /* _We_ call this UNII 3 */
  97         CHAN5G(5745, 33), /* Channel 149 */
  98         CHAN5G(5765, 34), /* Channel 153 */
  99         CHAN5G(5785, 35), /* Channel 157 */
 100         CHAN5G(5805, 36), /* Channel 161 */
 101         CHAN5G(5825, 37), /* Channel 165 */
 102 };
 103
 104 static void ath_cache_conf_rate(struct ath_softc *sc,
 105                                 struct ieee80211_conf *conf)
 106 {
 107         switch (conf->channel->band) {
 108         case IEEE80211_BAND_2GHZ:
 109                 if (conf_is_ht20(conf))
 110                         sc->cur_rate_table =
 111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 112                 else if (conf_is_ht40_minus(conf))
 113                         sc->cur_rate_table =
 114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 115                 else if (conf_is_ht40_plus(conf))
 116                         sc->cur_rate_table =
 117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 118                 else
 119                         sc->cur_rate_table =
 120                           sc->hw_rate_table[ATH9K_MODE_11G];
 121                 break;
 122         case IEEE80211_BAND_5GHZ:
 123                 if (conf_is_ht20(conf))
 124                         sc->cur_rate_table =
 125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 126                 else if (conf_is_ht40_minus(conf))
 127                         sc->cur_rate_table =
 128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 129                 else if (conf_is_ht40_plus(conf))
 130                         sc->cur_rate_table =
 131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 132                 else
 133                         sc->cur_rate_table =
 134                           sc->hw_rate_table[ATH9K_MODE_11A];
 135                 break;
 136         default:
 137                 BUG_ON(1);
 138                 break;
 139         }
 140 }
 141
 142 static void ath_update_txpow(struct ath_softc *sc)
 143 {
 144         struct ath_hw *ah = sc->sc_ah;
 145         u32 txpow;
 146
 147         if (sc->curtxpow != sc->config.txpowlimit) {
 148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 149                 /* read back in case value is clamped */
 150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 151                 sc->curtxpow = txpow;
 152         }
 153 }
 154
 155 static u8 parse_mpdudensity(u8 mpdudensity)
 156 {
 157         /*
 158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 159          *   0 for no restriction
 160          *   1 for 1/4 us
 161          *   2 for 1/2 us
 162          *   3 for 1 us
 163          *   4 for 2 us
 164          *   5 for 4 us
 165          *   6 for 8 us
 166          *   7 for 16 us
 167          */
 168         switch (mpdudensity) {
 169         case 0:
 170                 return 0;
 171         case 1:
 172         case 2:
 173         case 3:
 174                 /* Our lower layer calculations limit our precision to
 175                    1 microsecond */
 176                 return 1;
 177         case 4:
 178                 return 2;
 179         case 5:
 180                 return 4;
 181         case 6:
 182                 return 8;
 183         case 7:
 184                 return 16;
 185         default:
 186                 return 0;
 187         }
 188 }
 189
 190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 191 {
 192         const struct ath_rate_table *rate_table = NULL;
 193         struct ieee80211_supported_band *sband;
 194         struct ieee80211_rate *rate;
 195         int i, maxrates;
 196
 197         switch (band) {
 198         case IEEE80211_BAND_2GHZ:
 199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 200                 break;
 201         case IEEE80211_BAND_5GHZ:
 202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 203                 break;
 204         default:
 205                 break;
 206         }
 207
 208         if (rate_table == NULL)
 209                 return;
 210
 211         sband = &sc->sbands[band];
 212         rate = sc->rates[band];
 213
 214         if (rate_table->rate_cnt > ATH_RATE_MAX)
 215                 maxrates = ATH_RATE_MAX;
 216         else
 217                 maxrates = rate_table->rate_cnt;
 218
 219         for (i = 0; i < maxrates; i++) {
 220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 221                 rate[i].hw_value = rate_table->info[i].ratecode;
 222                 if (rate_table->info[i].short_preamble) {
 223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 224                                 rate_table->info[i].short_preamble;
 225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 226                 }
 227                 sband->n_bitrates++;
 228
 229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 230                         rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 /*
 235  * Set/change channels.  If the channel is really being changed, it's done
 236  * by reseting the chip.  To accomplish this we must first cleanup any pending
 237  * DMA, then restart stuff.
 238 */
 239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 240                     struct ath9k_channel *hchan)
 241 {
 242         struct ath_hw *ah = sc->sc_ah;
 243         bool fastcc = true, stopped;
 244         struct ieee80211_channel *channel = hw->conf.channel;
 245         int r;
 246
 247         if (sc->sc_flags & SC_OP_INVALID)
 248                 return -EIO;
 249
 250         ath9k_ps_wakeup(sc);
 251
 252         /*
 253          * This is only performed if the channel settings have
 254          * actually changed.
 255          *
 256          * To switch channels clear any pending DMA operations;
 257          * wait long enough for the RX fifo to drain, reset the
 258          * hardware at the new frequency, and then re-enable
 259          * the relevant bits of the h/w.
 260          */
 261         ath9k_hw_set_interrupts(ah, 0);
 262         ath_drain_all_txq(sc, false);
 263         stopped = ath_stoprecv(sc);
 264
 265         /* XXX: do not flush receive queue here. We don't want
 266          * to flush data frames already in queue because of
 267          * changing channel. */
 268
 269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 270                 fastcc = false;
 271
 272         DPRINTF(sc, ATH_DBG_CONFIG,
 273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 274                 sc->sc_ah->curchan->channel,
 275                 channel->center_freq, sc->tx_chan_width);
 276
 277         spin_lock_bh(&sc->sc_resetlock);
 278
 279         r = ath9k_hw_reset(ah, hchan, fastcc);
 280         if (r) {
 281                 DPRINTF(sc, ATH_DBG_FATAL,
 282                         "Unable to reset channel (%u Mhz) "
 283                         "reset status %d\n",
 284                         channel->center_freq, r);
 285                 spin_unlock_bh(&sc->sc_resetlock);
 286                 return r;
 287         }
 288         spin_unlock_bh(&sc->sc_resetlock);
 289
 290         sc->sc_flags &= ~SC_OP_FULL_RESET;
 291
 292         if (ath_startrecv(sc) != 0) {
 293                 DPRINTF(sc, ATH_DBG_FATAL,
 294                         "Unable to restart recv logic\n");
 295                 return -EIO;
 296         }
 297
 298         ath_cache_conf_rate(sc, &hw->conf);
 299         ath_update_txpow(sc);
 300         ath9k_hw_set_interrupts(ah, sc->imask);
 301         ath9k_ps_restore(sc);
 302         return 0;
 303 }
 304
 305 /*
 306  *  This routine performs the periodic noise floor calibration function
 307  *  that is used to adjust and optimize the chip performance.  This
 308  *  takes environmental changes (location, temperature) into account.
 309  *  When the task is complete, it reschedules itself depending on the
 310  *  appropriate interval that was calculated.
 311  */
 312 static void ath_ani_calibrate(unsigned long data)
 313 {
 314         struct ath_softc *sc = (struct ath_softc *)data;
 315         struct ath_hw *ah = sc->sc_ah;
 316         bool longcal = false;
 317         bool shortcal = false;
 318         bool aniflag = false;
 319         unsigned int timestamp = jiffies_to_msecs(jiffies);
 320         u32 cal_interval, short_cal_interval;
 321
 322         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 323                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 324
 325         /*
 326         * don't calibrate when we're scanning.
 327         * we are most likely not on our home channel.
 328         */
 329         if (sc->sc_flags & SC_OP_SCANNING)
 330                 goto set_timer;
 331
 332         /* Long calibration runs independently of short calibration. */
 333         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 334                 longcal = true;
 335                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 336                 sc->ani.longcal_timer = timestamp;
 337         }
 338
 339         /* Short calibration applies only while caldone is false */
 340         if (!sc->ani.caldone) {
 341                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 342                         shortcal = true;
 343                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 344                         sc->ani.shortcal_timer = timestamp;
 345                         sc->ani.resetcal_timer = timestamp;
 346                 }
 347         } else {
 348                 if ((timestamp - sc->ani.resetcal_timer) >=
 349                     ATH_RESTART_CALINTERVAL) {
 350                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 351                         if (sc->ani.caldone)
 352                                 sc->ani.resetcal_timer = timestamp;
 353                 }
 354         }
 355
 356         /* Verify whether we must check ANI */
 357         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 358                 aniflag = true;
 359                 sc->ani.checkani_timer = timestamp;
 360         }
 361
 362         /* Skip all processing if there's nothing to do. */
 363         if (longcal || shortcal || aniflag) {
 364                 /* Call ANI routine if necessary */
 365                 if (aniflag)
 366                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 367
 368                 /* Perform calibration if necessary */
 369                 if (longcal || shortcal) {
 370                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
 371                                                      sc->rx_chainmask, longcal);
 372
 373                         if (longcal)
 374                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 375                                                                      ah->curchan);
 376
 377                         DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
 378                                 ah->curchan->channel, ah->curchan->channelFlags,
 379                                 sc->ani.noise_floor);
 380                 }
 381         }
 382
 383 set_timer:
 384         /*
 385         * Set timer interval based on previous results.
 386         * The interval must be the shortest necessary to satisfy ANI,
 387         * short calibration and long calibration.
 388         */
 389         cal_interval = ATH_LONG_CALINTERVAL;
 390         if (sc->sc_ah->config.enable_ani)
 391                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 392         if (!sc->ani.caldone)
 393                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 394
 395         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 396 }
 397
 398 static void ath_start_ani(struct ath_softc *sc)
 399 {
 400         unsigned long timestamp = jiffies_to_msecs(jiffies);
 401
 402         sc->ani.longcal_timer = timestamp;
 403         sc->ani.shortcal_timer = timestamp;
 404         sc->ani.checkani_timer = timestamp;
 405
 406         mod_timer(&sc->ani.timer,
 407                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 408 }
 409
 410 /*
 411  * Update tx/rx chainmask. For legacy association,
 412  * hard code chainmask to 1x1, for 11n association, use
 413  * the chainmask configuration, for bt coexistence, use
 414  * the chainmask configuration even in legacy mode.
 415  */
 416 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 417 {
 418         if (is_ht ||
 419             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 420                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 421                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 422         } else {
 423                 sc->tx_chainmask = 1;
 424                 sc->rx_chainmask = 1;
 425         }
 426
 427         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 428                 sc->tx_chainmask, sc->rx_chainmask);
 429 }
 430
 431 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 432 {
 433         struct ath_node *an;
 434
 435         an = (struct ath_node *)sta->drv_priv;
 436
 437         if (sc->sc_flags & SC_OP_TXAGGR) {
 438                 ath_tx_node_init(sc, an);
 439                 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 440                                      sta->ht_cap.ampdu_factor);
 441                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 442         }
 443 }
 444
 445 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 446 {
 447         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 448
 449         if (sc->sc_flags & SC_OP_TXAGGR)
 450                 ath_tx_node_cleanup(sc, an);
 451 }
 452
 453 static void ath9k_tasklet(unsigned long data)
 454 {
 455         struct ath_softc *sc = (struct ath_softc *)data;
 456         u32 status = sc->intrstatus;
 457
 458         ath9k_ps_wakeup(sc);
 459
 460         if (status & ATH9K_INT_FATAL) {
 461                 ath_reset(sc, false);
 462                 ath9k_ps_restore(sc);
 463                 return;
 464         }
 465
 466         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 467                 spin_lock_bh(&sc->rx.rxflushlock);
 468                 ath_rx_tasklet(sc, 0);
 469                 spin_unlock_bh(&sc->rx.rxflushlock);
 470         }
 471
 472         if (status & ATH9K_INT_TX)
 473                 ath_tx_tasklet(sc);
 474
 475         /* re-enable hardware interrupt */
 476         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 477         ath9k_ps_restore(sc);
 478 }
 479
 480 irqreturn_t ath_isr(int irq, void *dev)
 481 {
 482 #define SCHED_INTR (                            \
 483                 ATH9K_INT_FATAL |               \
 484                 ATH9K_INT_RXORN |               \
 485                 ATH9K_INT_RXEOL |               \
 486                 ATH9K_INT_RX |                  \
 487                 ATH9K_INT_TX |                  \
 488                 ATH9K_INT_BMISS |               \
 489                 ATH9K_INT_CST |                 \
 490                 ATH9K_INT_TSFOOR)
 491
 492         struct ath_softc *sc = dev;
 493         struct ath_hw *ah = sc->sc_ah;
 494         enum ath9k_int status;
 495         bool sched = false;
 496
 497         /*
 498          * The hardware is not ready/present, don't
 499          * touch anything. Note this can happen early
 500          * on if the IRQ is shared.
 501          */
 502         if (sc->sc_flags & SC_OP_INVALID)
 503                 return IRQ_NONE;
 504
 505
 506         /* shared irq, not for us */
 507
 508         if (!ath9k_hw_intrpend(ah))
 509                 return IRQ_NONE;
 510
 511         /*
 512          * Figure out the reason(s) for the interrupt.  Note
 513          * that the hal returns a pseudo-ISR that may include
 514          * bits we haven't explicitly enabled so we mask the
 515          * value to insure we only process bits we requested.
 516          */
 517         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 518         status &= sc->imask;    /* discard unasked-for bits */
 519
 520         /*
 521          * If there are no status bits set, then this interrupt was not
 522          * for me (should have been caught above).
 523          */
 524         if (!status)
 525                 return IRQ_NONE;
 526
 527         /* Cache the status */
 528         sc->intrstatus = status;
 529
 530         if (status & SCHED_INTR)
 531                 sched = true;
 532
 533         /*
 534          * If a FATAL or RXORN interrupt is received, we have to reset the
 535          * chip immediately.
 536          */
 537         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 538                 goto chip_reset;
 539
 540         if (status & ATH9K_INT_SWBA)
 541                 tasklet_schedule(&sc->bcon_tasklet);
 542
 543         if (status & ATH9K_INT_TXURN)
 544                 ath9k_hw_updatetxtriglevel(ah, true);
 545
 546         if (status & ATH9K_INT_MIB) {
 547                 /*
 548                  * Disable interrupts until we service the MIB
 549                  * interrupt; otherwise it will continue to
 550                  * fire.
 551                  */
 552                 ath9k_hw_set_interrupts(ah, 0);
 553                 /*
 554                  * Let the hal handle the event. We assume
 555                  * it will clear whatever condition caused
 556                  * the interrupt.
 557                  */
 558                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 559                 ath9k_hw_set_interrupts(ah, sc->imask);
 560         }
 561
 562         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 563                 if (status & ATH9K_INT_TIM_TIMER) {
 564                         /* Clear RxAbort bit so that we can
 565                          * receive frames */
 566                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 567                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 568                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 569                 }
 570
 571 chip_reset:
 572
 573         ath_debug_stat_interrupt(sc, status);
 574
 575         if (sched) {
 576                 /* turn off every interrupt except SWBA */
 577                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 578                 tasklet_schedule(&sc->intr_tq);
 579         }
 580
 581         return IRQ_HANDLED;
 582
 583 #undef SCHED_INTR
 584 }
 585
 586 static u32 ath_get_extchanmode(struct ath_softc *sc,
 587                                struct ieee80211_channel *chan,
 588                                enum nl80211_channel_type channel_type)
 589 {
 590         u32 chanmode = 0;
 591
 592         switch (chan->band) {
 593         case IEEE80211_BAND_2GHZ:
 594                 switch(channel_type) {
 595                 case NL80211_CHAN_NO_HT:
 596                 case NL80211_CHAN_HT20:
 597                         chanmode = CHANNEL_G_HT20;
 598                         break;
 599                 case NL80211_CHAN_HT40PLUS:
 600                         chanmode = CHANNEL_G_HT40PLUS;
 601                         break;
 602                 case NL80211_CHAN_HT40MINUS:
 603                         chanmode = CHANNEL_G_HT40MINUS;
 604                         break;
 605                 }
 606                 break;
 607         case IEEE80211_BAND_5GHZ:
 608                 switch(channel_type) {
 609                 case NL80211_CHAN_NO_HT:
 610                 case NL80211_CHAN_HT20:
 611                         chanmode = CHANNEL_A_HT20;
 612                         break;
 613                 case NL80211_CHAN_HT40PLUS:
 614                         chanmode = CHANNEL_A_HT40PLUS;
 615                         break;
 616                 case NL80211_CHAN_HT40MINUS:
 617                         chanmode = CHANNEL_A_HT40MINUS;
 618                         break;
 619                 }
 620                 break;
 621         default:
 622                 break;
 623         }
 624
 625         return chanmode;
 626 }
 627
 628 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 629                            struct ath9k_keyval *hk, const u8 *addr,
 630                            bool authenticator)
 631 {
 632         const u8 *key_rxmic;
 633         const u8 *key_txmic;
 634
 635         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 636         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 637
 638         if (addr == NULL) {
 639                 /*
 640                  * Group key installation - only two key cache entries are used
 641                  * regardless of splitmic capability since group key is only
 642                  * used either for TX or RX.
 643                  */
 644                 if (authenticator) {
 645                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 646                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 647                 } else {
 648                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 649                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 650                 }
 651                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 652         }
 653         if (!sc->splitmic) {
 654                 /* TX and RX keys share the same key cache entry. */
 655                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 656                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 657                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 658         }
 659
 660         /* Separate key cache entries for TX and RX */
 661
 662         /* TX key goes at first index, RX key at +32. */
 663         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 664         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 665                 /* TX MIC entry failed. No need to proceed further */
 666                 DPRINTF(sc, ATH_DBG_FATAL,
 667                         "Setting TX MIC Key Failed\n");
 668                 return 0;
 669         }
 670
 671         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 672         /* XXX delete tx key on failure? */
 673         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 674 }
 675
 676 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 677 {
 678         int i;
 679
 680         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 681                 if (test_bit(i, sc->keymap) ||
 682                     test_bit(i + 64, sc->keymap))
 683                         continue; /* At least one part of TKIP key allocated */
 684                 if (sc->splitmic &&
 685                     (test_bit(i + 32, sc->keymap) ||
 686                      test_bit(i + 64 + 32, sc->keymap)))
 687                         continue; /* At least one part of TKIP key allocated */
 688
 689                 /* Found a free slot for a TKIP key */
 690                 return i;
 691         }
 692         return -1;
 693 }
 694
 695 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 696 {
 697         int i;
 698
 699         /* First, try to find slots that would not be available for TKIP. */
 700         if (sc->splitmic) {
 701                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 702                         if (!test_bit(i, sc->keymap) &&
 703                             (test_bit(i + 32, sc->keymap) ||
 704                              test_bit(i + 64, sc->keymap) ||
 705                              test_bit(i + 64 + 32, sc->keymap)))
 706                                 return i;
 707                         if (!test_bit(i + 32, sc->keymap) &&
 708                             (test_bit(i, sc->keymap) ||
 709                              test_bit(i + 64, sc->keymap) ||
 710                              test_bit(i + 64 + 32, sc->keymap)))
 711                                 return i + 32;
 712                         if (!test_bit(i + 64, sc->keymap) &&
 713                             (test_bit(i , sc->keymap) ||
 714                              test_bit(i + 32, sc->keymap) ||
 715                              test_bit(i + 64 + 32, sc->keymap)))
 716                                 return i + 64;
 717                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 718                             (test_bit(i, sc->keymap) ||
 719                              test_bit(i + 32, sc->keymap) ||
 720                              test_bit(i + 64, sc->keymap)))
 721                                 return i + 64 + 32;
 722                 }
 723         } else {
 724                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 725                         if (!test_bit(i, sc->keymap) &&
 726                             test_bit(i + 64, sc->keymap))
 727                                 return i;
 728                         if (test_bit(i, sc->keymap) &&
 729                             !test_bit(i + 64, sc->keymap))
 730                                 return i + 64;
 731                 }
 732         }
 733
 734         /* No partially used TKIP slots, pick any available slot */
 735         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 736                 /* Do not allow slots that could be needed for TKIP group keys
 737                  * to be used. This limitation could be removed if we know that
 738                  * TKIP will not be used. */
 739                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 740                         continue;
 741                 if (sc->splitmic) {
 742                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 743                                 continue;
 744                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 745                                 continue;
 746                 }
 747
 748                 if (!test_bit(i, sc->keymap))
 749                         return i; /* Found a free slot for a key */
 750         }
 751
 752         /* No free slot found */
 753         return -1;
 754 }
 755
 756 static int ath_key_config(struct ath_softc *sc,
 757                           struct ieee80211_vif *vif,
 758                           struct ieee80211_sta *sta,
 759                           struct ieee80211_key_conf *key)
 760 {
 761         struct ath9k_keyval hk;
 762         const u8 *mac = NULL;
 763         int ret = 0;
 764         int idx;
 765
 766         memset(&hk, 0, sizeof(hk));
 767
 768         switch (key->alg) {
 769         case ALG_WEP:
 770                 hk.kv_type = ATH9K_CIPHER_WEP;
 771                 break;
 772         case ALG_TKIP:
 773                 hk.kv_type = ATH9K_CIPHER_TKIP;
 774                 break;
 775         case ALG_CCMP:
 776                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 777                 break;
 778         default:
 779                 return -EOPNOTSUPP;
 780         }
 781
 782         hk.kv_len = key->keylen;
 783         memcpy(hk.kv_val, key->key, key->keylen);
 784
 785         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 786                 /* For now, use the default keys for broadcast keys. This may
 787                  * need to change with virtual interfaces. */
 788                 idx = key->keyidx;
 789         } else if (key->keyidx) {
 790                 if (WARN_ON(!sta))
 791                         return -EOPNOTSUPP;
 792                 mac = sta->addr;
 793
 794                 if (vif->type != NL80211_IFTYPE_AP) {
 795                         /* Only keyidx 0 should be used with unicast key, but
 796                          * allow this for client mode for now. */
 797                         idx = key->keyidx;
 798                 } else
 799                         return -EIO;
 800         } else {
 801                 if (WARN_ON(!sta))
 802                         return -EOPNOTSUPP;
 803                 mac = sta->addr;
 804
 805                 if (key->alg == ALG_TKIP)
 806                         idx = ath_reserve_key_cache_slot_tkip(sc);
 807                 else
 808                         idx = ath_reserve_key_cache_slot(sc);
 809                 if (idx < 0)
 810                         return -ENOSPC; /* no free key cache entries */
 811         }
 812
 813         if (key->alg == ALG_TKIP)
 814                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 815                                       vif->type == NL80211_IFTYPE_AP);
 816         else
 817                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 818
 819         if (!ret)
 820                 return -EIO;
 821
 822         set_bit(idx, sc->keymap);
 823         if (key->alg == ALG_TKIP) {
 824                 set_bit(idx + 64, sc->keymap);
 825                 if (sc->splitmic) {
 826                         set_bit(idx + 32, sc->keymap);
 827                         set_bit(idx + 64 + 32, sc->keymap);
 828                 }
 829         }
 830
 831         return idx;
 832 }
 833
 834 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 835 {
 836         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 837         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 838                 return;
 839
 840         clear_bit(key->hw_key_idx, sc->keymap);
 841         if (key->alg != ALG_TKIP)
 842                 return;
 843
 844         clear_bit(key->hw_key_idx + 64, sc->keymap);
 845         if (sc->splitmic) {
 846                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 847                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 848         }
 849 }
 850
 851 static void setup_ht_cap(struct ath_softc *sc,
 852                          struct ieee80211_sta_ht_cap *ht_info)
 853 {
 854 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 855 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 856
 857         ht_info->ht_supported = true;
 858         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 859                        IEEE80211_HT_CAP_SM_PS |
 860                        IEEE80211_HT_CAP_SGI_40 |
 861                        IEEE80211_HT_CAP_DSSSCCK40;
 862
 863         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 864         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 865
 866         /* set up supported mcs set */
 867         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 868
 869         switch(sc->rx_chainmask) {
 870         case 1:
 871                 ht_info->mcs.rx_mask[0] = 0xff;
 872                 break;
 873         case 3:
 874         case 5:
 875         case 7:
 876         default:
 877                 ht_info->mcs.rx_mask[0] = 0xff;
 878                 ht_info->mcs.rx_mask[1] = 0xff;
 879                 break;
 880         }
 881
 882         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 883 }
 884
 885 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 886                                  struct ieee80211_vif *vif,
 887                                  struct ieee80211_bss_conf *bss_conf)
 888 {
 889         struct ath_vif *avp = (void *)vif->drv_priv;
 890
 891         if (bss_conf->assoc) {
 892                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 893                         bss_conf->aid, sc->curbssid);
 894
 895                 /* New association, store aid */
 896                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 897                         sc->curaid = bss_conf->aid;
 898                         ath9k_hw_write_associd(sc);
 899                 }
 900
 901                 /* Configure the beacon */
 902                 ath_beacon_config(sc, vif);
 903
 904                 /* Reset rssi stats */
 905                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 906                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 907                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 908                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 909
 910                 ath_start_ani(sc);
 911         } else {
 912                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
 913                 sc->curaid = 0;
 914         }
 915 }
 916
 917 /********************************/
 918 /*       LED functions          */
 919 /********************************/
 920
 921 static void ath_led_blink_work(struct work_struct *work)
 922 {
 923         struct ath_softc *sc = container_of(work, struct ath_softc,
 924                                             ath_led_blink_work.work);
 925
 926         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 927                 return;
 928
 929         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
 930             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
 931                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 932         else
 933                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 934                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 935
 936         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 937                            (sc->sc_flags & SC_OP_LED_ON) ?
 938                            msecs_to_jiffies(sc->led_off_duration) :
 939                            msecs_to_jiffies(sc->led_on_duration));
 940
 941         sc->led_on_duration = sc->led_on_cnt ?
 942                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
 943                         ATH_LED_ON_DURATION_IDLE;
 944         sc->led_off_duration = sc->led_off_cnt ?
 945                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
 946                         ATH_LED_OFF_DURATION_IDLE;
 947         sc->led_on_cnt = sc->led_off_cnt = 0;
 948         if (sc->sc_flags & SC_OP_LED_ON)
 949                 sc->sc_flags &= ~SC_OP_LED_ON;
 950         else
 951                 sc->sc_flags |= SC_OP_LED_ON;
 952 }
 953
 954 static void ath_led_brightness(struct led_classdev *led_cdev,
 955                                enum led_brightness brightness)
 956 {
 957         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 958         struct ath_softc *sc = led->sc;
 959
 960         switch (brightness) {
 961         case LED_OFF:
 962                 if (led->led_type == ATH_LED_ASSOC ||
 963                     led->led_type == ATH_LED_RADIO) {
 964                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 965                                 (led->led_type == ATH_LED_RADIO));
 966                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 967                         if (led->led_type == ATH_LED_RADIO)
 968                                 sc->sc_flags &= ~SC_OP_LED_ON;
 969                 } else {
 970                         sc->led_off_cnt++;
 971                 }
 972                 break;
 973         case LED_FULL:
 974                 if (led->led_type == ATH_LED_ASSOC) {
 975                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 976                         queue_delayed_work(sc->hw->workqueue,
 977                                            &sc->ath_led_blink_work, 0);
 978                 } else if (led->led_type == ATH_LED_RADIO) {
 979                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 980                         sc->sc_flags |= SC_OP_LED_ON;
 981                 } else {
 982                         sc->led_on_cnt++;
 983                 }
 984                 break;
 985         default:
 986                 break;
 987         }
 988 }
 989
 990 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 991                             char *trigger)
 992 {
 993         int ret;
 994
 995         led->sc = sc;
 996         led->led_cdev.name = led->name;
 997         led->led_cdev.default_trigger = trigger;
 998         led->led_cdev.brightness_set = ath_led_brightness;
 999
1000         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1001         if (ret)
1002                 DPRINTF(sc, ATH_DBG_FATAL,
1003                         "Failed to register led:%s", led->name);
1004         else
1005                 led->registered = 1;
1006         return ret;
1007 }
1008
1009 static void ath_unregister_led(struct ath_led *led)
1010 {
1011         if (led->registered) {
1012                 led_classdev_unregister(&led->led_cdev);
1013                 led->registered = 0;
1014         }
1015 }
1016
1017 static void ath_deinit_leds(struct ath_softc *sc)
1018 {
1019         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1020         ath_unregister_led(&sc->assoc_led);
1021         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1022         ath_unregister_led(&sc->tx_led);
1023         ath_unregister_led(&sc->rx_led);
1024         ath_unregister_led(&sc->radio_led);
1025         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1026 }
1027
1028 static void ath_init_leds(struct ath_softc *sc)
1029 {
1030         char *trigger;
1031         int ret;
1032
1033         /* Configure gpio 1 for output */
1034         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1035                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1036         /* LED off, active low */
1037         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1038
1039         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1040
1041         trigger = ieee80211_get_radio_led_name(sc->hw);
1042         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1043                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1044         ret = ath_register_led(sc, &sc->radio_led, trigger);
1045         sc->radio_led.led_type = ATH_LED_RADIO;
1046         if (ret)
1047                 goto fail;
1048
1049         trigger = ieee80211_get_assoc_led_name(sc->hw);
1050         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1051                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1052         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1053         sc->assoc_led.led_type = ATH_LED_ASSOC;
1054         if (ret)
1055                 goto fail;
1056
1057         trigger = ieee80211_get_tx_led_name(sc->hw);
1058         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1059                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1060         ret = ath_register_led(sc, &sc->tx_led, trigger);
1061         sc->tx_led.led_type = ATH_LED_TX;
1062         if (ret)
1063                 goto fail;
1064
1065         trigger = ieee80211_get_rx_led_name(sc->hw);
1066         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1067                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1068         ret = ath_register_led(sc, &sc->rx_led, trigger);
1069         sc->rx_led.led_type = ATH_LED_RX;
1070         if (ret)
1071                 goto fail;
1072
1073         return;
1074
1075 fail:
1076         ath_deinit_leds(sc);
1077 }
1078
1079 void ath_radio_enable(struct ath_softc *sc)
1080 {
1081         struct ath_hw *ah = sc->sc_ah;
1082         struct ieee80211_channel *channel = sc->hw->conf.channel;
1083         int r;
1084
1085         ath9k_ps_wakeup(sc);
1086         ath9k_hw_configpcipowersave(ah, 0);
1087
1088         spin_lock_bh(&sc->sc_resetlock);
1089         r = ath9k_hw_reset(ah, ah->curchan, false);
1090         if (r) {
1091                 DPRINTF(sc, ATH_DBG_FATAL,
1092                         "Unable to reset channel %u (%uMhz) ",
1093                         "reset status %d\n",
1094                         channel->center_freq, r);
1095         }
1096         spin_unlock_bh(&sc->sc_resetlock);
1097
1098         ath_update_txpow(sc);
1099         if (ath_startrecv(sc) != 0) {
1100                 DPRINTF(sc, ATH_DBG_FATAL,
1101                         "Unable to restart recv logic\n");
1102                 return;
1103         }
1104
1105         if (sc->sc_flags & SC_OP_BEACONS)
1106                 ath_beacon_config(sc, NULL);    /* restart beacons */
1107
1108         /* Re-Enable  interrupts */
1109         ath9k_hw_set_interrupts(ah, sc->imask);
1110
1111         /* Enable LED */
1112         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1113                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1114         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1115
1116         ieee80211_wake_queues(sc->hw);
1117         ath9k_ps_restore(sc);
1118 }
1119
1120 void ath_radio_disable(struct ath_softc *sc)
1121 {
1122         struct ath_hw *ah = sc->sc_ah;
1123         struct ieee80211_channel *channel = sc->hw->conf.channel;
1124         int r;
1125
1126         ath9k_ps_wakeup(sc);
1127         ieee80211_stop_queues(sc->hw);
1128
1129         /* Disable LED */
1130         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1131         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1132
1133         /* Disable interrupts */
1134         ath9k_hw_set_interrupts(ah, 0);
1135
1136         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1137         ath_stoprecv(sc);               /* turn off frame recv */
1138         ath_flushrecv(sc);              /* flush recv queue */
1139
1140         spin_lock_bh(&sc->sc_resetlock);
1141         r = ath9k_hw_reset(ah, ah->curchan, false);
1142         if (r) {
1143                 DPRINTF(sc, ATH_DBG_FATAL,
1144                         "Unable to reset channel %u (%uMhz) "
1145                         "reset status %d\n",
1146                         channel->center_freq, r);
1147         }
1148         spin_unlock_bh(&sc->sc_resetlock);
1149
1150         ath9k_hw_phy_disable(ah);
1151         ath9k_hw_configpcipowersave(ah, 1);
1152         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1153         ath9k_ps_restore(sc);
1154 }
1155
1156 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1157
1158 /*******************/
1159 /*      Rfkill     */
1160 /*******************/
1161
1162 static bool ath_is_rfkill_set(struct ath_softc *sc)
1163 {
1164         struct ath_hw *ah = sc->sc_ah;
1165
1166         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1167                                   ah->rfkill_polarity;
1168 }
1169
1170 /* h/w rfkill poll function */
1171 static void ath_rfkill_poll(struct work_struct *work)
1172 {
1173         struct ath_softc *sc = container_of(work, struct ath_softc,
1174                                             rf_kill.rfkill_poll.work);
1175         bool radio_on;
1176
1177         if (sc->sc_flags & SC_OP_INVALID)
1178                 return;
1179
1180         radio_on = !ath_is_rfkill_set(sc);
1181
1182         /*
1183          * enable/disable radio only when there is a
1184          * state change in RF switch
1185          */
1186         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1187                 enum rfkill_state state;
1188
1189                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1190                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1191                                 : RFKILL_STATE_HARD_BLOCKED;
1192                 } else if (radio_on) {
1193                         ath_radio_enable(sc);
1194                         state = RFKILL_STATE_UNBLOCKED;
1195                 } else {
1196                         ath_radio_disable(sc);
1197                         state = RFKILL_STATE_HARD_BLOCKED;
1198                 }
1199
1200                 if (state == RFKILL_STATE_HARD_BLOCKED)
1201                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1202                 else
1203                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1204
1205                 rfkill_force_state(sc->rf_kill.rfkill, state);
1206         }
1207
1208         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1209                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1210 }
1211
1212 /* s/w rfkill handler */
1213 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1214 {
1215         struct ath_softc *sc = data;
1216
1217         switch (state) {
1218         case RFKILL_STATE_SOFT_BLOCKED:
1219                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1220                     SC_OP_RFKILL_SW_BLOCKED)))
1221                         ath_radio_disable(sc);
1222                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1223                 return 0;
1224         case RFKILL_STATE_UNBLOCKED:
1225                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1226                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1227                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1228                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1229                                         "radio as it is disabled by h/w\n");
1230                                 return -EPERM;
1231                         }
1232                         ath_radio_enable(sc);
1233                 }
1234                 return 0;
1235         default:
1236                 return -EINVAL;
1237         }
1238 }
1239
1240 /* Init s/w rfkill */
1241 static int ath_init_sw_rfkill(struct ath_softc *sc)
1242 {
1243         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1244                                              RFKILL_TYPE_WLAN);
1245         if (!sc->rf_kill.rfkill) {
1246                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1247                 return -ENOMEM;
1248         }
1249
1250         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1251                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1252         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1253         sc->rf_kill.rfkill->data = sc;
1254         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1255         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1256
1257         return 0;
1258 }
1259
1260 /* Deinitialize rfkill */
1261 static void ath_deinit_rfkill(struct ath_softc *sc)
1262 {
1263         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1264                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1265
1266         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1267                 rfkill_unregister(sc->rf_kill.rfkill);
1268                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1269                 sc->rf_kill.rfkill = NULL;
1270         }
1271 }
1272
1273 static int ath_start_rfkill_poll(struct ath_softc *sc)
1274 {
1275         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1276                 queue_delayed_work(sc->hw->workqueue,
1277                                    &sc->rf_kill.rfkill_poll, 0);
1278
1279         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1280                 if (rfkill_register(sc->rf_kill.rfkill)) {
1281                         DPRINTF(sc, ATH_DBG_FATAL,
1282                                 "Unable to register rfkill\n");
1283                         rfkill_free(sc->rf_kill.rfkill);
1284
1285                         /* Deinitialize the device */
1286                         ath_cleanup(sc);
1287                         return -EIO;
1288                 } else {
1289                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1290                 }
1291         }
1292
1293         return 0;
1294 }
1295 #endif /* CONFIG_RFKILL */
1296
1297 void ath_cleanup(struct ath_softc *sc)
1298 {
1299         ath_detach(sc);
1300         free_irq(sc->irq, sc);
1301         ath_bus_cleanup(sc);
1302         kfree(sc->sec_wiphy);
1303         ieee80211_free_hw(sc->hw);
1304 }
1305
1306 void ath_detach(struct ath_softc *sc)
1307 {
1308         struct ieee80211_hw *hw = sc->hw;
1309         int i = 0;
1310
1311         ath9k_ps_wakeup(sc);
1312
1313         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1314
1315 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1316         ath_deinit_rfkill(sc);
1317 #endif
1318         ath_deinit_leds(sc);
1319         cancel_work_sync(&sc->chan_work);
1320         cancel_delayed_work_sync(&sc->wiphy_work);
1321
1322         for (i = 0; i < sc->num_sec_wiphy; i++) {
1323                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1324                 if (aphy == NULL)
1325                         continue;
1326                 sc->sec_wiphy[i] = NULL;
1327                 ieee80211_unregister_hw(aphy->hw);
1328                 ieee80211_free_hw(aphy->hw);
1329         }
1330         ieee80211_unregister_hw(hw);
1331         ath_rx_cleanup(sc);
1332         ath_tx_cleanup(sc);
1333
1334         tasklet_kill(&sc->intr_tq);
1335         tasklet_kill(&sc->bcon_tasklet);
1336
1337         if (!(sc->sc_flags & SC_OP_INVALID))
1338                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1339
1340         /* cleanup tx queues */
1341         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1342                 if (ATH_TXQ_SETUP(sc, i))
1343                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1344
1345         ath9k_hw_detach(sc->sc_ah);
1346         ath9k_exit_debug(sc);
1347         ath9k_ps_restore(sc);
1348 }
1349
1350 static int ath9k_reg_notifier(struct wiphy *wiphy,
1351                               struct regulatory_request *request)
1352 {
1353         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1354         struct ath_wiphy *aphy = hw->priv;
1355         struct ath_softc *sc = aphy->sc;
1356         struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1357
1358         return ath_reg_notifier_apply(wiphy, request, reg);
1359 }
1360
1361 static int ath_init(u16 devid, struct ath_softc *sc)
1362 {
1363         struct ath_hw *ah = NULL;
1364         int status;
1365         int error = 0, i;
1366         int csz = 0;
1367
1368         /* XXX: hardware will not be ready until ath_open() being called */
1369         sc->sc_flags |= SC_OP_INVALID;
1370
1371         if (ath9k_init_debug(sc) < 0)
1372                 printk(KERN_ERR "Unable to create debugfs files\n");
1373
1374         spin_lock_init(&sc->wiphy_lock);
1375         spin_lock_init(&sc->sc_resetlock);
1376         spin_lock_init(&sc->sc_serial_rw);
1377         mutex_init(&sc->mutex);
1378         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1379         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1380                      (unsigned long)sc);
1381
1382         /*
1383          * Cache line size is used to size and align various
1384          * structures used to communicate with the hardware.
1385          */
1386         ath_read_cachesize(sc, &csz);
1387         /* XXX assert csz is non-zero */
1388         sc->cachelsz = csz << 2;        /* convert to bytes */
1389
1390         ah = ath9k_hw_attach(devid, sc, &status);
1391         if (ah == NULL) {
1392                 DPRINTF(sc, ATH_DBG_FATAL,
1393                         "Unable to attach hardware; HAL status %d\n", status);
1394                 error = -ENXIO;
1395                 goto bad;
1396         }
1397         sc->sc_ah = ah;
1398
1399         /* Get the hardware key cache size. */
1400         sc->keymax = ah->caps.keycache_size;
1401         if (sc->keymax > ATH_KEYMAX) {
1402                 DPRINTF(sc, ATH_DBG_ANY,
1403                         "Warning, using only %u entries in %u key cache\n",
1404                         ATH_KEYMAX, sc->keymax);
1405                 sc->keymax = ATH_KEYMAX;
1406         }
1407
1408         /*
1409          * Reset the key cache since some parts do not
1410          * reset the contents on initial power up.
1411          */
1412         for (i = 0; i < sc->keymax; i++)
1413                 ath9k_hw_keyreset(ah, (u16) i);
1414
1415         error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1416                               ath9k_reg_notifier);
1417         if (error)
1418                 goto bad;
1419
1420         /* default to MONITOR mode */
1421         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1422
1423         /* Setup rate tables */
1424
1425         ath_rate_attach(sc);
1426         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1427         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1428
1429         /*
1430          * Allocate hardware transmit queues: one queue for
1431          * beacon frames and one data queue for each QoS
1432          * priority.  Note that the hal handles reseting
1433          * these queues at the needed time.
1434          */
1435         sc->beacon.beaconq = ath_beaconq_setup(ah);
1436         if (sc->beacon.beaconq == -1) {
1437                 DPRINTF(sc, ATH_DBG_FATAL,
1438                         "Unable to setup a beacon xmit queue\n");
1439                 error = -EIO;
1440                 goto bad2;
1441         }
1442         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1443         if (sc->beacon.cabq == NULL) {
1444                 DPRINTF(sc, ATH_DBG_FATAL,
1445                         "Unable to setup CAB xmit queue\n");
1446                 error = -EIO;
1447                 goto bad2;
1448         }
1449
1450         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1451         ath_cabq_update(sc);
1452
1453         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1454                 sc->tx.hwq_map[i] = -1;
1455
1456         /* Setup data queues */
1457         /* NB: ensure BK queue is the lowest priority h/w queue */
1458         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1459                 DPRINTF(sc, ATH_DBG_FATAL,
1460                         "Unable to setup xmit queue for BK traffic\n");
1461                 error = -EIO;
1462                 goto bad2;
1463         }
1464
1465         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1466                 DPRINTF(sc, ATH_DBG_FATAL,
1467                         "Unable to setup xmit queue for BE traffic\n");
1468                 error = -EIO;
1469                 goto bad2;
1470         }
1471         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1472                 DPRINTF(sc, ATH_DBG_FATAL,
1473                         "Unable to setup xmit queue for VI traffic\n");
1474                 error = -EIO;
1475                 goto bad2;
1476         }
1477         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1478                 DPRINTF(sc, ATH_DBG_FATAL,
1479                         "Unable to setup xmit queue for VO traffic\n");
1480                 error = -EIO;
1481                 goto bad2;
1482         }
1483
1484         /* Initializes the noise floor to a reasonable default value.
1485          * Later on this will be updated during ANI processing. */
1486
1487         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1488         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1489
1490         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1491                                    ATH9K_CIPHER_TKIP, NULL)) {
1492                 /*
1493                  * Whether we should enable h/w TKIP MIC.
1494                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1495                  * report WMM capable, so it's always safe to turn on
1496                  * TKIP MIC in this case.
1497                  */
1498                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1499                                        0, 1, NULL);
1500         }
1501
1502         /*
1503          * Check whether the separate key cache entries
1504          * are required to handle both tx+rx MIC keys.
1505          * With split mic keys the number of stations is limited
1506          * to 27 otherwise 59.
1507          */
1508         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1509                                    ATH9K_CIPHER_TKIP, NULL)
1510             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1511                                       ATH9K_CIPHER_MIC, NULL)
1512             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1513                                       0, NULL))
1514                 sc->splitmic = 1;
1515
1516         /* turn on mcast key search if possible */
1517         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1518                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1519                                              1, NULL);
1520
1521         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1522
1523         /* 11n Capabilities */
1524         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1525                 sc->sc_flags |= SC_OP_TXAGGR;
1526                 sc->sc_flags |= SC_OP_RXAGGR;
1527         }
1528
1529         sc->tx_chainmask = ah->caps.tx_chainmask;
1530         sc->rx_chainmask = ah->caps.rx_chainmask;
1531
1532         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1533         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1534
1535         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1536                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1537
1538         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1539
1540         /* initialize beacon slots */
1541         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1542                 sc->beacon.bslot[i] = NULL;
1543                 sc->beacon.bslot_aphy[i] = NULL;
1544         }
1545
1546         /* setup channels and rates */
1547
1548         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1549         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1550                 sc->rates[IEEE80211_BAND_2GHZ];
1551         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1552         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1553                 ARRAY_SIZE(ath9k_2ghz_chantable);
1554
1555         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1556                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1557                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1558                         sc->rates[IEEE80211_BAND_5GHZ];
1559                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1560                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1561                         ARRAY_SIZE(ath9k_5ghz_chantable);
1562         }
1563
1564         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1565                 ath9k_hw_btcoex_enable(sc->sc_ah);
1566
1567         return 0;
1568 bad2:
1569         /* cleanup tx queues */
1570         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1571                 if (ATH_TXQ_SETUP(sc, i))
1572                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1573 bad:
1574         if (ah)
1575                 ath9k_hw_detach(ah);
1576         ath9k_exit_debug(sc);
1577
1578         return error;
1579 }
1580
1581 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1582 {
1583         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1584                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1585                 IEEE80211_HW_SIGNAL_DBM |
1586                 IEEE80211_HW_AMPDU_AGGREGATION |
1587                 IEEE80211_HW_SUPPORTS_PS |
1588                 IEEE80211_HW_PS_NULLFUNC_STACK |
1589                 IEEE80211_HW_SPECTRUM_MGMT;
1590
1591         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1592                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1593
1594         hw->wiphy->interface_modes =
1595                 BIT(NL80211_IFTYPE_AP) |
1596                 BIT(NL80211_IFTYPE_STATION) |
1597                 BIT(NL80211_IFTYPE_ADHOC) |
1598                 BIT(NL80211_IFTYPE_MESH_POINT);
1599
1600         hw->queues = 4;
1601         hw->max_rates = 4;
1602         hw->channel_change_time = 5000;
1603         hw->max_listen_interval = 10;
1604         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1605         hw->sta_data_size = sizeof(struct ath_node);
1606         hw->vif_data_size = sizeof(struct ath_vif);
1607
1608         hw->rate_control_algorithm = "ath9k_rate_control";
1609
1610         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1611                 &sc->sbands[IEEE80211_BAND_2GHZ];
1612         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1613                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1614                         &sc->sbands[IEEE80211_BAND_5GHZ];
1615 }
1616
1617 int ath_attach(u16 devid, struct ath_softc *sc)
1618 {
1619         struct ieee80211_hw *hw = sc->hw;
1620         int error = 0, i;
1621         struct ath_regulatory *reg;
1622
1623         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1624
1625         error = ath_init(devid, sc);
1626         if (error != 0)
1627                 return error;
1628
1629         reg = &sc->sc_ah->regulatory;
1630
1631         /* get mac address from hardware and set in mac80211 */
1632
1633         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1634
1635         ath_set_hw_capab(sc, hw);
1636
1637         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1638                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1639                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1640                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1641         }
1642
1643         /* initialize tx/rx engine */
1644         error = ath_tx_init(sc, ATH_TXBUF);
1645         if (error != 0)
1646                 goto error_attach;
1647
1648         error = ath_rx_init(sc, ATH_RXBUF);
1649         if (error != 0)
1650                 goto error_attach;
1651
1652 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1653         /* Initialze h/w Rfkill */
1654         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1655                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1656
1657         /* Initialize s/w rfkill */
1658         error = ath_init_sw_rfkill(sc);
1659         if (error)
1660                 goto error_attach;
1661 #endif
1662
1663         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1664         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1665         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1666
1667         error = ieee80211_register_hw(hw);
1668
1669         if (!ath_is_world_regd(reg)) {
1670                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1671                 if (error)
1672                         goto error_attach;
1673         }
1674
1675         /* Initialize LED control */
1676         ath_init_leds(sc);
1677
1678
1679         return 0;
1680
1681 error_attach:
1682         /* cleanup tx queues */
1683         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1684                 if (ATH_TXQ_SETUP(sc, i))
1685                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1686
1687         ath9k_hw_detach(sc->sc_ah);
1688         ath9k_exit_debug(sc);
1689
1690         return error;
1691 }
1692
1693 int ath_reset(struct ath_softc *sc, bool retry_tx)
1694 {
1695         struct ath_hw *ah = sc->sc_ah;
1696         struct ieee80211_hw *hw = sc->hw;
1697         int r;
1698
1699         ath9k_hw_set_interrupts(ah, 0);
1700         ath_drain_all_txq(sc, retry_tx);
1701         ath_stoprecv(sc);
1702         ath_flushrecv(sc);
1703
1704         spin_lock_bh(&sc->sc_resetlock);
1705         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1706         if (r)
1707                 DPRINTF(sc, ATH_DBG_FATAL,
1708                         "Unable to reset hardware; reset status %d\n", r);
1709         spin_unlock_bh(&sc->sc_resetlock);
1710
1711         if (ath_startrecv(sc) != 0)
1712                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1713
1714         /*
1715          * We may be doing a reset in response to a request
1716          * that changes the channel so update any state that
1717          * might change as a result.
1718          */
1719         ath_cache_conf_rate(sc, &hw->conf);
1720
1721         ath_update_txpow(sc);
1722
1723         if (sc->sc_flags & SC_OP_BEACONS)
1724                 ath_beacon_config(sc, NULL);    /* restart beacons */
1725
1726         ath9k_hw_set_interrupts(ah, sc->imask);
1727
1728         if (retry_tx) {
1729                 int i;
1730                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1731                         if (ATH_TXQ_SETUP(sc, i)) {
1732                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1733                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1734                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1735                         }
1736                 }
1737         }
1738
1739         return r;
1740 }
1741
1742 /*
1743  *  This function will allocate both the DMA descriptor structure, and the
1744  *  buffers it contains.  These are used to contain the descriptors used
1745  *  by the system.
1746 */
1747 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1748                       struct list_head *head, const char *name,
1749                       int nbuf, int ndesc)
1750 {
1751 #define DS2PHYS(_dd, _ds)                                               \
1752         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1753 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1754 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1755
1756         struct ath_desc *ds;
1757         struct ath_buf *bf;
1758         int i, bsize, error;
1759
1760         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1761                 name, nbuf, ndesc);
1762
1763         INIT_LIST_HEAD(head);
1764         /* ath_desc must be a multiple of DWORDs */
1765         if ((sizeof(struct ath_desc) % 4) != 0) {
1766                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1767                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1768                 error = -ENOMEM;
1769                 goto fail;
1770         }
1771
1772         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1773
1774         /*
1775          * Need additional DMA memory because we can't use
1776          * descriptors that cross the 4K page boundary. Assume
1777          * one skipped descriptor per 4K page.
1778          */
1779         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1780                 u32 ndesc_skipped =
1781                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1782                 u32 dma_len;
1783
1784                 while (ndesc_skipped) {
1785                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1786                         dd->dd_desc_len += dma_len;
1787
1788                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1789                 };
1790         }
1791
1792         /* allocate descriptors */
1793         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1794                                          &dd->dd_desc_paddr, GFP_KERNEL);
1795         if (dd->dd_desc == NULL) {
1796                 error = -ENOMEM;
1797                 goto fail;
1798         }
1799         ds = dd->dd_desc;
1800         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1801                 name, ds, (u32) dd->dd_desc_len,
1802                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1803
1804         /* allocate buffers */
1805         bsize = sizeof(struct ath_buf) * nbuf;
1806         bf = kzalloc(bsize, GFP_KERNEL);
1807         if (bf == NULL) {
1808                 error = -ENOMEM;
1809                 goto fail2;
1810         }
1811         dd->dd_bufptr = bf;
1812
1813         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1814                 bf->bf_desc = ds;
1815                 bf->bf_daddr = DS2PHYS(dd, ds);
1816
1817                 if (!(sc->sc_ah->caps.hw_caps &
1818                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1819                         /*
1820                          * Skip descriptor addresses which can cause 4KB
1821                          * boundary crossing (addr + length) with a 32 dword
1822                          * descriptor fetch.
1823                          */
1824                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1825                                 ASSERT((caddr_t) bf->bf_desc <
1826                                        ((caddr_t) dd->dd_desc +
1827                                         dd->dd_desc_len));
1828
1829                                 ds += ndesc;
1830                                 bf->bf_desc = ds;
1831                                 bf->bf_daddr = DS2PHYS(dd, ds);
1832                         }
1833                 }
1834                 list_add_tail(&bf->list, head);
1835         }
1836         return 0;
1837 fail2:
1838         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1839                           dd->dd_desc_paddr);
1840 fail:
1841         memset(dd, 0, sizeof(*dd));
1842         return error;
1843 #undef ATH_DESC_4KB_BOUND_CHECK
1844 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1845 #undef DS2PHYS
1846 }
1847
1848 void ath_descdma_cleanup(struct ath_softc *sc,
1849                          struct ath_descdma *dd,
1850                          struct list_head *head)
1851 {
1852         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1853                           dd->dd_desc_paddr);
1854
1855         INIT_LIST_HEAD(head);
1856         kfree(dd->dd_bufptr);
1857         memset(dd, 0, sizeof(*dd));
1858 }
1859
1860 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1861 {
1862         int qnum;
1863
1864         switch (queue) {
1865         case 0:
1866                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1867                 break;
1868         case 1:
1869                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1870                 break;
1871         case 2:
1872                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1873                 break;
1874         case 3:
1875                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1876                 break;
1877         default:
1878                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1879                 break;
1880         }
1881
1882         return qnum;
1883 }
1884
1885 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1886 {
1887         int qnum;
1888
1889         switch (queue) {
1890         case ATH9K_WME_AC_VO:
1891                 qnum = 0;
1892                 break;
1893         case ATH9K_WME_AC_VI:
1894                 qnum = 1;
1895                 break;
1896         case ATH9K_WME_AC_BE:
1897                 qnum = 2;
1898                 break;
1899         case ATH9K_WME_AC_BK:
1900                 qnum = 3;
1901                 break;
1902         default:
1903                 qnum = -1;
1904                 break;
1905         }
1906
1907         return qnum;
1908 }
1909
1910 /* XXX: Remove me once we don't depend on ath9k_channel for all
1911  * this redundant data */
1912 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1913                            struct ath9k_channel *ichan)
1914 {
1915         struct ieee80211_channel *chan = hw->conf.channel;
1916         struct ieee80211_conf *conf = &hw->conf;
1917
1918         ichan->channel = chan->center_freq;
1919         ichan->chan = chan;
1920
1921         if (chan->band == IEEE80211_BAND_2GHZ) {
1922                 ichan->chanmode = CHANNEL_G;
1923                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1924         } else {
1925                 ichan->chanmode = CHANNEL_A;
1926                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1927         }
1928
1929         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1930
1931         if (conf_is_ht(conf)) {
1932                 if (conf_is_ht40(conf))
1933                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1934
1935                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1936                                             conf->channel_type);
1937         }
1938 }
1939
1940 /**********************/
1941 /* mac80211 callbacks */
1942 /**********************/
1943
1944 static int ath9k_start(struct ieee80211_hw *hw)
1945 {
1946         struct ath_wiphy *aphy = hw->priv;
1947         struct ath_softc *sc = aphy->sc;
1948         struct ieee80211_channel *curchan = hw->conf.channel;
1949         struct ath9k_channel *init_channel;
1950         int r, pos;
1951
1952         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1953                 "initial channel: %d MHz\n", curchan->center_freq);
1954
1955         mutex_lock(&sc->mutex);
1956
1957         if (ath9k_wiphy_started(sc)) {
1958                 if (sc->chan_idx == curchan->hw_value) {
1959                         /*
1960                          * Already on the operational channel, the new wiphy
1961                          * can be marked active.
1962                          */
1963                         aphy->state = ATH_WIPHY_ACTIVE;
1964                         ieee80211_wake_queues(hw);
1965                 } else {
1966                         /*
1967                          * Another wiphy is on another channel, start the new
1968                          * wiphy in paused state.
1969                          */
1970                         aphy->state = ATH_WIPHY_PAUSED;
1971                         ieee80211_stop_queues(hw);
1972                 }
1973                 mutex_unlock(&sc->mutex);
1974                 return 0;
1975         }
1976         aphy->state = ATH_WIPHY_ACTIVE;
1977
1978         /* setup initial channel */
1979
1980         pos = curchan->hw_value;
1981
1982         sc->chan_idx = pos;
1983         init_channel = &sc->sc_ah->channels[pos];
1984         ath9k_update_ichannel(sc, hw, init_channel);
1985
1986         /* Reset SERDES registers */
1987         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1988
1989         /*
1990          * The basic interface to setting the hardware in a good
1991          * state is ``reset''.  On return the hardware is known to
1992          * be powered up and with interrupts disabled.  This must
1993          * be followed by initialization of the appropriate bits
1994          * and then setup of the interrupt mask.
1995          */
1996         spin_lock_bh(&sc->sc_resetlock);
1997         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1998         if (r) {
1999                 DPRINTF(sc, ATH_DBG_FATAL,
2000                         "Unable to reset hardware; reset status %d "
2001                         "(freq %u MHz)\n", r,
2002                         curchan->center_freq);
2003                 spin_unlock_bh(&sc->sc_resetlock);
2004                 goto mutex_unlock;
2005         }
2006         spin_unlock_bh(&sc->sc_resetlock);
2007
2008         /*
2009          * This is needed only to setup initial state
2010          * but it's best done after a reset.
2011          */
2012         ath_update_txpow(sc);
2013
2014         /*
2015          * Setup the hardware after reset:
2016          * The receive engine is set going.
2017          * Frame transmit is handled entirely
2018          * in the frame output path; there's nothing to do
2019          * here except setup the interrupt mask.
2020          */
2021         if (ath_startrecv(sc) != 0) {
2022                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
2023                 r = -EIO;
2024                 goto mutex_unlock;
2025         }
2026
2027         /* Setup our intr mask. */
2028         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2029                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2030                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2031
2032         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2033                 sc->imask |= ATH9K_INT_GTT;
2034
2035         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2036                 sc->imask |= ATH9K_INT_CST;
2037
2038         ath_cache_conf_rate(sc, &hw->conf);
2039
2040         sc->sc_flags &= ~SC_OP_INVALID;
2041
2042         /* Disable BMISS interrupt when we're not associated */
2043         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2044         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2045
2046         ieee80211_wake_queues(hw);
2047
2048 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2049         r = ath_start_rfkill_poll(sc);
2050 #endif
2051
2052 mutex_unlock:
2053         mutex_unlock(&sc->mutex);
2054
2055         return r;
2056 }
2057
2058 static int ath9k_tx(struct ieee80211_hw *hw,
2059                     struct sk_buff *skb)
2060 {
2061         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2062         struct ath_wiphy *aphy = hw->priv;
2063         struct ath_softc *sc = aphy->sc;
2064         struct ath_tx_control txctl;
2065         int hdrlen, padsize;
2066
2067         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2068                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2069                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2070                 goto exit;
2071         }
2072
2073         memset(&txctl, 0, sizeof(struct ath_tx_control));
2074
2075         /*
2076          * As a temporary workaround, assign seq# here; this will likely need
2077          * to be cleaned up to work better with Beacon transmission and virtual
2078          * BSSes.
2079          */
2080         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2081                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2082                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2083                         sc->tx.seq_no += 0x10;
2084                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2085                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2086         }
2087
2088         /* Add the padding after the header if this is not already done */
2089         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2090         if (hdrlen & 3) {
2091                 padsize = hdrlen % 4;
2092                 if (skb_headroom(skb) < padsize)
2093                         return -1;
2094                 skb_push(skb, padsize);
2095                 memmove(skb->data, skb->data + padsize, hdrlen);
2096         }
2097
2098         /* Check if a tx queue is available */
2099
2100         txctl.txq = ath_test_get_txq(sc, skb);
2101         if (!txctl.txq)
2102                 goto exit;
2103
2104         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2105
2106         if (ath_tx_start(hw, skb, &txctl) != 0) {
2107                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2108                 goto exit;
2109         }
2110
2111         return 0;
2112 exit:
2113         dev_kfree_skb_any(skb);
2114         return 0;
2115 }
2116
2117 static void ath9k_stop(struct ieee80211_hw *hw)
2118 {
2119         struct ath_wiphy *aphy = hw->priv;
2120         struct ath_softc *sc = aphy->sc;
2121
2122         aphy->state = ATH_WIPHY_INACTIVE;
2123
2124         if (sc->sc_flags & SC_OP_INVALID) {
2125                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2126                 return;
2127         }
2128
2129         mutex_lock(&sc->mutex);
2130
2131         ieee80211_stop_queues(hw);
2132
2133         if (ath9k_wiphy_started(sc)) {
2134                 mutex_unlock(&sc->mutex);
2135                 return; /* another wiphy still in use */
2136         }
2137
2138         /* make sure h/w will not generate any interrupt
2139          * before setting the invalid flag. */
2140         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2141
2142         if (!(sc->sc_flags & SC_OP_INVALID)) {
2143                 ath_drain_all_txq(sc, false);
2144                 ath_stoprecv(sc);
2145                 ath9k_hw_phy_disable(sc->sc_ah);
2146         } else
2147                 sc->rx.rxlink = NULL;
2148
2149 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2150         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2151                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2152 #endif
2153         /* disable HAL and put h/w to sleep */
2154         ath9k_hw_disable(sc->sc_ah);
2155         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2156
2157         sc->sc_flags |= SC_OP_INVALID;
2158
2159         mutex_unlock(&sc->mutex);
2160
2161         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2162 }
2163
2164 static int ath9k_add_interface(struct ieee80211_hw *hw,
2165                                struct ieee80211_if_init_conf *conf)
2166 {
2167         struct ath_wiphy *aphy = hw->priv;
2168         struct ath_softc *sc = aphy->sc;
2169         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2170         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2171         int ret = 0;
2172
2173         mutex_lock(&sc->mutex);
2174
2175         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2176             sc->nvifs > 0) {
2177                 ret = -ENOBUFS;
2178                 goto out;
2179         }
2180
2181         switch (conf->type) {
2182         case NL80211_IFTYPE_STATION:
2183                 ic_opmode = NL80211_IFTYPE_STATION;
2184                 break;
2185         case NL80211_IFTYPE_ADHOC:
2186         case NL80211_IFTYPE_AP:
2187         case NL80211_IFTYPE_MESH_POINT:
2188                 if (sc->nbcnvifs >= ATH_BCBUF) {
2189                         ret = -ENOBUFS;
2190                         goto out;
2191                 }
2192                 ic_opmode = conf->type;
2193                 break;
2194         default:
2195                 DPRINTF(sc, ATH_DBG_FATAL,
2196                         "Interface type %d not yet supported\n", conf->type);
2197                 ret = -EOPNOTSUPP;
2198                 goto out;
2199         }
2200
2201         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2202
2203         /* Set the VIF opmode */
2204         avp->av_opmode = ic_opmode;
2205         avp->av_bslot = -1;
2206
2207         sc->nvifs++;
2208
2209         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2210                 ath9k_set_bssid_mask(hw);
2211
2212         if (sc->nvifs > 1)
2213                 goto out; /* skip global settings for secondary vif */
2214
2215         if (ic_opmode == NL80211_IFTYPE_AP) {
2216                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2217                 sc->sc_flags |= SC_OP_TSF_RESET;
2218         }
2219
2220         /* Set the device opmode */
2221         sc->sc_ah->opmode = ic_opmode;
2222
2223         /*
2224          * Enable MIB interrupts when there are hardware phy counters.
2225          * Note we only do this (at the moment) for station mode.
2226          */
2227         if ((conf->type == NL80211_IFTYPE_STATION) ||
2228             (conf->type == NL80211_IFTYPE_ADHOC) ||
2229             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2230                 if (ath9k_hw_phycounters(sc->sc_ah))
2231                         sc->imask |= ATH9K_INT_MIB;
2232                 sc->imask |= ATH9K_INT_TSFOOR;
2233         }
2234
2235         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2236
2237         if (conf->type == NL80211_IFTYPE_AP)
2238                 ath_start_ani(sc);
2239
2240 out:
2241         mutex_unlock(&sc->mutex);
2242         return ret;
2243 }
2244
2245 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2246                                    struct ieee80211_if_init_conf *conf)
2247 {
2248         struct ath_wiphy *aphy = hw->priv;
2249         struct ath_softc *sc = aphy->sc;
2250         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2251         int i;
2252
2253         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2254
2255         mutex_lock(&sc->mutex);
2256
2257         /* Stop ANI */
2258         del_timer_sync(&sc->ani.timer);
2259
2260         /* Reclaim beacon resources */
2261         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2262             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2263             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2264                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2265                 ath_beacon_return(sc, avp);
2266         }
2267
2268         sc->sc_flags &= ~SC_OP_BEACONS;
2269
2270         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2271                 if (sc->beacon.bslot[i] == conf->vif) {
2272                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2273                                "slot\n", __func__);
2274                         sc->beacon.bslot[i] = NULL;
2275                         sc->beacon.bslot_aphy[i] = NULL;
2276                 }
2277         }
2278
2279         sc->nvifs--;
2280
2281         mutex_unlock(&sc->mutex);
2282 }
2283
2284 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2285 {
2286         struct ath_wiphy *aphy = hw->priv;
2287         struct ath_softc *sc = aphy->sc;
2288         struct ieee80211_conf *conf = &hw->conf;
2289         struct ath_hw *ah = sc->sc_ah;
2290
2291         mutex_lock(&sc->mutex);
2292
2293         if (changed & IEEE80211_CONF_CHANGE_PS) {
2294                 if (conf->flags & IEEE80211_CONF_PS) {
2295                         if (!(ah->caps.hw_caps &
2296                               ATH9K_HW_CAP_AUTOSLEEP)) {
2297                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2298                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2299                                         ath9k_hw_set_interrupts(sc->sc_ah,
2300                                                         sc->imask);
2301                                 }
2302                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2303                         }
2304                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2305                 } else {
2306                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2307                         if (!(ah->caps.hw_caps &
2308                               ATH9K_HW_CAP_AUTOSLEEP)) {
2309                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2310                                 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2311                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2312                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2313                                         ath9k_hw_set_interrupts(sc->sc_ah,
2314                                                         sc->imask);
2315                                 }
2316                         }
2317                 }
2318         }
2319
2320         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2321                 struct ieee80211_channel *curchan = hw->conf.channel;
2322                 int pos = curchan->hw_value;
2323
2324                 aphy->chan_idx = pos;
2325                 aphy->chan_is_ht = conf_is_ht(conf);
2326
2327                 if (aphy->state == ATH_WIPHY_SCAN ||
2328                     aphy->state == ATH_WIPHY_ACTIVE)
2329                         ath9k_wiphy_pause_all_forced(sc, aphy);
2330                 else {
2331                         /*
2332                          * Do not change operational channel based on a paused
2333                          * wiphy changes.
2334                          */
2335                         goto skip_chan_change;
2336                 }
2337
2338                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2339                         curchan->center_freq);
2340
2341                 /* XXX: remove me eventualy */
2342                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2343
2344                 ath_update_chainmask(sc, conf_is_ht(conf));
2345
2346                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2347                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2348                         mutex_unlock(&sc->mutex);
2349                         return -EINVAL;
2350                 }
2351         }
2352
2353 skip_chan_change:
2354         if (changed & IEEE80211_CONF_CHANGE_POWER)
2355                 sc->config.txpowlimit = 2 * conf->power_level;
2356
2357         mutex_unlock(&sc->mutex);
2358
2359         return 0;
2360 }
2361
2362 #define SUPPORTED_FILTERS                       \
2363         (FIF_PROMISC_IN_BSS |                   \
2364         FIF_ALLMULTI |                          \
2365         FIF_CONTROL |                           \
2366         FIF_OTHER_BSS |                         \
2367         FIF_BCN_PRBRESP_PROMISC |               \
2368         FIF_FCSFAIL)
2369
2370 /* FIXME: sc->sc_full_reset ? */
2371 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2372                                    unsigned int changed_flags,
2373                                    unsigned int *total_flags,
2374                                    int mc_count,
2375                                    struct dev_mc_list *mclist)
2376 {
2377         struct ath_wiphy *aphy = hw->priv;
2378         struct ath_softc *sc = aphy->sc;
2379         u32 rfilt;
2380
2381         changed_flags &= SUPPORTED_FILTERS;
2382         *total_flags &= SUPPORTED_FILTERS;
2383
2384         sc->rx.rxfilter = *total_flags;
2385         rfilt = ath_calcrxfilter(sc);
2386         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2387
2388         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2389 }
2390
2391 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2392                              struct ieee80211_vif *vif,
2393                              enum sta_notify_cmd cmd,
2394                              struct ieee80211_sta *sta)
2395 {
2396         struct ath_wiphy *aphy = hw->priv;
2397         struct ath_softc *sc = aphy->sc;
2398
2399         switch (cmd) {
2400         case STA_NOTIFY_ADD:
2401                 ath_node_attach(sc, sta);
2402                 break;
2403         case STA_NOTIFY_REMOVE:
2404                 ath_node_detach(sc, sta);
2405                 break;
2406         default:
2407                 break;
2408         }
2409 }
2410
2411 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2412                          const struct ieee80211_tx_queue_params *params)
2413 {
2414         struct ath_wiphy *aphy = hw->priv;
2415         struct ath_softc *sc = aphy->sc;
2416         struct ath9k_tx_queue_info qi;
2417         int ret = 0, qnum;
2418
2419         if (queue >= WME_NUM_AC)
2420                 return 0;
2421
2422         mutex_lock(&sc->mutex);
2423
2424         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2425
2426         qi.tqi_aifs = params->aifs;
2427         qi.tqi_cwmin = params->cw_min;
2428         qi.tqi_cwmax = params->cw_max;
2429         qi.tqi_burstTime = params->txop;
2430         qnum = ath_get_hal_qnum(queue, sc);
2431
2432         DPRINTF(sc, ATH_DBG_CONFIG,
2433                 "Configure tx [queue/halq] [%d/%d],  "
2434                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2435                 queue, qnum, params->aifs, params->cw_min,
2436                 params->cw_max, params->txop);
2437
2438         ret = ath_txq_update(sc, qnum, &qi);
2439         if (ret)
2440                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2441
2442         mutex_unlock(&sc->mutex);
2443
2444         return ret;
2445 }
2446
2447 static int ath9k_set_key(struct ieee80211_hw *hw,
2448                          enum set_key_cmd cmd,
2449                          struct ieee80211_vif *vif,
2450                          struct ieee80211_sta *sta,
2451                          struct ieee80211_key_conf *key)
2452 {
2453         struct ath_wiphy *aphy = hw->priv;
2454         struct ath_softc *sc = aphy->sc;
2455         int ret = 0;
2456
2457         if (modparam_nohwcrypt)
2458                 return -ENOSPC;
2459
2460         mutex_lock(&sc->mutex);
2461         ath9k_ps_wakeup(sc);
2462         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2463
2464         switch (cmd) {
2465         case SET_KEY:
2466                 ret = ath_key_config(sc, vif, sta, key);
2467                 if (ret >= 0) {
2468                         key->hw_key_idx = ret;
2469                         /* push IV and Michael MIC generation to stack */
2470                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2471                         if (key->alg == ALG_TKIP)
2472                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2473                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2474                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2475                         ret = 0;
2476                 }
2477                 break;
2478         case DISABLE_KEY:
2479                 ath_key_delete(sc, key);
2480                 break;
2481         default:
2482                 ret = -EINVAL;
2483         }
2484
2485         ath9k_ps_restore(sc);
2486         mutex_unlock(&sc->mutex);
2487
2488         return ret;
2489 }
2490
2491 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2492                                    struct ieee80211_vif *vif,
2493                                    struct ieee80211_bss_conf *bss_conf,
2494                                    u32 changed)
2495 {
2496         struct ath_wiphy *aphy = hw->priv;
2497         struct ath_softc *sc = aphy->sc;
2498         struct ath_hw *ah = sc->sc_ah;
2499         struct ath_vif *avp = (void *)vif->drv_priv;
2500         u32 rfilt = 0;
2501         int error, i;
2502
2503         mutex_lock(&sc->mutex);
2504
2505         /*
2506          * TODO: Need to decide which hw opmode to use for
2507          *       multi-interface cases
2508          * XXX: This belongs into add_interface!
2509          */
2510         if (vif->type == NL80211_IFTYPE_AP &&
2511             ah->opmode != NL80211_IFTYPE_AP) {
2512                 ah->opmode = NL80211_IFTYPE_STATION;
2513                 ath9k_hw_setopmode(ah);
2514                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2515                 sc->curaid = 0;
2516                 ath9k_hw_write_associd(sc);
2517                 /* Request full reset to get hw opmode changed properly */
2518                 sc->sc_flags |= SC_OP_FULL_RESET;
2519         }
2520
2521         if ((changed & BSS_CHANGED_BSSID) &&
2522             !is_zero_ether_addr(bss_conf->bssid)) {
2523                 switch (vif->type) {
2524                 case NL80211_IFTYPE_STATION:
2525                 case NL80211_IFTYPE_ADHOC:
2526                 case NL80211_IFTYPE_MESH_POINT:
2527                         /* Set BSSID */
2528                         memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2529                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2530                         sc->curaid = 0;
2531                         ath9k_hw_write_associd(sc);
2532
2533                         /* Set aggregation protection mode parameters */
2534                         sc->config.ath_aggr_prot = 0;
2535
2536                         DPRINTF(sc, ATH_DBG_CONFIG,
2537                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2538                                 rfilt, sc->curbssid, sc->curaid);
2539
2540                         /* need to reconfigure the beacon */
2541                         sc->sc_flags &= ~SC_OP_BEACONS ;
2542
2543                         break;
2544                 default:
2545                         break;
2546                 }
2547         }
2548
2549         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2550             (vif->type == NL80211_IFTYPE_AP) ||
2551             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2552                 if ((changed & BSS_CHANGED_BEACON) ||
2553                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2554                      bss_conf->enable_beacon)) {
2555                         /*
2556                          * Allocate and setup the beacon frame.
2557                          *
2558                          * Stop any previous beacon DMA.  This may be
2559                          * necessary, for example, when an ibss merge
2560                          * causes reconfiguration; we may be called
2561                          * with beacon transmission active.
2562                          */
2563                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2564
2565                         error = ath_beacon_alloc(aphy, vif);
2566                         if (!error)
2567                                 ath_beacon_config(sc, vif);
2568                 }
2569         }
2570
2571         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2572         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2573                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2574                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2575                                 ath9k_hw_keysetmac(sc->sc_ah,
2576                                                    (u16)i,
2577                                                    sc->curbssid);
2578         }
2579
2580         /* Only legacy IBSS for now */
2581         if (vif->type == NL80211_IFTYPE_ADHOC)
2582                 ath_update_chainmask(sc, 0);
2583
2584         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2585                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2586                         bss_conf->use_short_preamble);
2587                 if (bss_conf->use_short_preamble)
2588                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2589                 else
2590                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2591         }
2592
2593         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2594                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2595                         bss_conf->use_cts_prot);
2596                 if (bss_conf->use_cts_prot &&
2597                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2598                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2599                 else
2600                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2601         }
2602
2603         if (changed & BSS_CHANGED_ASSOC) {
2604                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2605                         bss_conf->assoc);
2606                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2607         }
2608
2609         /*
2610          * The HW TSF has to be reset when the beacon interval changes.
2611          * We set the flag here, and ath_beacon_config_ap() would take this
2612          * into account when it gets called through the subsequent
2613          * config_interface() call - with IFCC_BEACON in the changed field.
2614          */
2615
2616         if (changed & BSS_CHANGED_BEACON_INT) {
2617                 sc->sc_flags |= SC_OP_TSF_RESET;
2618                 sc->beacon_interval = bss_conf->beacon_int;
2619         }
2620
2621         mutex_unlock(&sc->mutex);
2622 }
2623
2624 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2625 {
2626         u64 tsf;
2627         struct ath_wiphy *aphy = hw->priv;
2628         struct ath_softc *sc = aphy->sc;
2629
2630         mutex_lock(&sc->mutex);
2631         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2632         mutex_unlock(&sc->mutex);
2633
2634         return tsf;
2635 }
2636
2637 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2638 {
2639         struct ath_wiphy *aphy = hw->priv;
2640         struct ath_softc *sc = aphy->sc;
2641
2642         mutex_lock(&sc->mutex);
2643         ath9k_hw_settsf64(sc->sc_ah, tsf);
2644         mutex_unlock(&sc->mutex);
2645 }
2646
2647 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2648 {
2649         struct ath_wiphy *aphy = hw->priv;
2650         struct ath_softc *sc = aphy->sc;
2651
2652         mutex_lock(&sc->mutex);
2653         ath9k_hw_reset_tsf(sc->sc_ah);
2654         mutex_unlock(&sc->mutex);
2655 }
2656
2657 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2658                               enum ieee80211_ampdu_mlme_action action,
2659                               struct ieee80211_sta *sta,
2660                               u16 tid, u16 *ssn)
2661 {
2662         struct ath_wiphy *aphy = hw->priv;
2663         struct ath_softc *sc = aphy->sc;
2664         int ret = 0;
2665
2666         switch (action) {
2667         case IEEE80211_AMPDU_RX_START:
2668                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2669                         ret = -ENOTSUPP;
2670                 break;
2671         case IEEE80211_AMPDU_RX_STOP:
2672                 break;
2673         case IEEE80211_AMPDU_TX_START:
2674                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2675                 if (ret < 0)
2676                         DPRINTF(sc, ATH_DBG_FATAL,
2677                                 "Unable to start TX aggregation\n");
2678                 else
2679                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2680                 break;
2681         case IEEE80211_AMPDU_TX_STOP:
2682                 ret = ath_tx_aggr_stop(sc, sta, tid);
2683                 if (ret < 0)
2684                         DPRINTF(sc, ATH_DBG_FATAL,
2685                                 "Unable to stop TX aggregation\n");
2686
2687                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2688                 break;
2689         case IEEE80211_AMPDU_TX_OPERATIONAL:
2690                 ath_tx_aggr_resume(sc, sta, tid);
2691                 break;
2692         default:
2693                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2694         }
2695
2696         return ret;
2697 }
2698
2699 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2700 {
2701         struct ath_wiphy *aphy = hw->priv;
2702         struct ath_softc *sc = aphy->sc;
2703
2704         if (ath9k_wiphy_scanning(sc)) {
2705                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2706                        "same time\n");
2707                 /*
2708                  * Do not allow the concurrent scanning state for now. This
2709                  * could be improved with scanning control moved into ath9k.
2710                  */
2711                 return;
2712         }
2713
2714         aphy->state = ATH_WIPHY_SCAN;
2715         ath9k_wiphy_pause_all_forced(sc, aphy);
2716
2717         mutex_lock(&sc->mutex);
2718         sc->sc_flags |= SC_OP_SCANNING;
2719         mutex_unlock(&sc->mutex);
2720 }
2721
2722 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2723 {
2724         struct ath_wiphy *aphy = hw->priv;
2725         struct ath_softc *sc = aphy->sc;
2726
2727         mutex_lock(&sc->mutex);
2728         aphy->state = ATH_WIPHY_ACTIVE;
2729         sc->sc_flags &= ~SC_OP_SCANNING;
2730         sc->sc_flags |= SC_OP_FULL_RESET;
2731         mutex_unlock(&sc->mutex);
2732 }
2733
2734 struct ieee80211_ops ath9k_ops = {
2735         .tx                 = ath9k_tx,
2736         .start              = ath9k_start,
2737         .stop               = ath9k_stop,
2738         .add_interface      = ath9k_add_interface,
2739         .remove_interface   = ath9k_remove_interface,
2740         .config             = ath9k_config,
2741         .configure_filter   = ath9k_configure_filter,
2742         .sta_notify         = ath9k_sta_notify,
2743         .conf_tx            = ath9k_conf_tx,
2744         .bss_info_changed   = ath9k_bss_info_changed,
2745         .set_key            = ath9k_set_key,
2746         .get_tsf            = ath9k_get_tsf,
2747         .set_tsf            = ath9k_set_tsf,
2748         .reset_tsf          = ath9k_reset_tsf,
2749         .ampdu_action       = ath9k_ampdu_action,
2750         .sw_scan_start      = ath9k_sw_scan_start,
2751         .sw_scan_complete   = ath9k_sw_scan_complete,
2752 };
2753
2754 static struct {
2755         u32 version;
2756         const char * name;
2757 } ath_mac_bb_names[] = {
2758         { AR_SREV_VERSION_5416_PCI,     "5416" },
2759         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2760         { AR_SREV_VERSION_9100,         "9100" },
2761         { AR_SREV_VERSION_9160,         "9160" },
2762         { AR_SREV_VERSION_9280,         "9280" },
2763         { AR_SREV_VERSION_9285,         "9285" }
2764 };
2765
2766 static struct {
2767         u16 version;
2768         const char * name;
2769 } ath_rf_names[] = {
2770         { 0,                            "5133" },
2771         { AR_RAD5133_SREV_MAJOR,        "5133" },
2772         { AR_RAD5122_SREV_MAJOR,        "5122" },
2773         { AR_RAD2133_SREV_MAJOR,        "2133" },
2774         { AR_RAD2122_SREV_MAJOR,        "2122" }
2775 };
2776
2777 /*
2778  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2779  */
2780 const char *
2781 ath_mac_bb_name(u32 mac_bb_version)
2782 {
2783         int i;
2784
2785         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2786                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2787                         return ath_mac_bb_names[i].name;
2788                 }
2789         }
2790
2791         return "????";
2792 }
2793
2794 /*
2795  * Return the RF name. "????" is returned if the RF is unknown.
2796  */
2797 const char *
2798 ath_rf_name(u16 rf_version)
2799 {
2800         int i;
2801
2802         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2803                 if (ath_rf_names[i].version == rf_version) {
2804                         return ath_rf_names[i].name;
2805                 }
2806         }
2807
2808         return "????";
2809 }
2810
2811 static int __init ath9k_init(void)
2812 {
2813         int error;
2814
2815         /* Register rate control algorithm */
2816         error = ath_rate_control_register();
2817         if (error != 0) {
2818                 printk(KERN_ERR
2819                         "ath9k: Unable to register rate control "
2820                         "algorithm: %d\n",
2821                         error);
2822                 goto err_out;
2823         }
2824
2825         error = ath9k_debug_create_root();
2826         if (error) {
2827                 printk(KERN_ERR
2828                         "ath9k: Unable to create debugfs root: %d\n",
2829                         error);
2830                 goto err_rate_unregister;
2831         }
2832
2833         error = ath_pci_init();
2834         if (error < 0) {
2835                 printk(KERN_ERR
2836                         "ath9k: No PCI devices found, driver not installed.\n");
2837                 error = -ENODEV;
2838                 goto err_remove_root;
2839         }
2840
2841         error = ath_ahb_init();
2842         if (error < 0) {
2843                 error = -ENODEV;
2844                 goto err_pci_exit;
2845         }
2846
2847         return 0;
2848
2849  err_pci_exit:
2850         ath_pci_exit();
2851
2852  err_remove_root:
2853         ath9k_debug_remove_root();
2854  err_rate_unregister:
2855         ath_rate_control_unregister();
2856  err_out:
2857         return error;
2858 }
2859 module_init(ath9k_init);
2860
2861 static void __exit ath9k_exit(void)
2862 {
2863         ath_ahb_exit();
2864         ath_pci_exit();
2865         ath9k_debug_remove_root();
2866         ath_rate_control_unregister();
2867         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2868 }
2869 module_exit(ath9k_exit);