2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
20 #define ATH_PCI_VERSION "0.1"
22 static char *dev_info = "ath9k";
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
33 /* We use the hw_value as an index into our private channel structure */
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
120 sc->hw_rate_table[ATH9K_MODE_11G];
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
134 sc->hw_rate_table[ATH9K_MODE_11A];
142 static void ath_update_txpow(struct ath_softc *sc)
144 struct ath_hw *ah = sc->sc_ah;
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
155 static u8 parse_mpdudensity(u8 mpdudensity)
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
168 switch (mpdudensity) {
174 /* Our lower layer calculations limit our precision to
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
192 const struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
208 if (rate_table == NULL)
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
217 maxrates = rate_table->rate_cnt;
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
234 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
252 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
255 struct ath_hw *ah = sc->sc_ah;
256 bool fastcc = true, stopped;
257 struct ieee80211_channel *channel = hw->conf.channel;
260 if (sc->sc_flags & SC_OP_INVALID)
266 * This is only performed if the channel settings have
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
274 ath9k_hw_set_interrupts(ah, 0);
275 ath_drain_all_txq(sc, false);
276 stopped = ath_stoprecv(sc);
278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
287 sc->sc_ah->curchan->channel,
288 channel->center_freq, sc->tx_chan_width);
290 spin_lock_bh(&sc->sc_resetlock);
292 r = ath9k_hw_reset(ah, hchan, fastcc);
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
301 spin_unlock_bh(&sc->sc_resetlock);
303 sc->sc_flags &= ~SC_OP_FULL_RESET;
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
311 ath_cache_conf_rate(sc, &hw->conf);
312 ath_update_txpow(sc);
313 ath9k_hw_set_interrupts(ah, sc->imask);
314 ath9k_ps_restore(sc);
319 * This routine performs the periodic noise floor calibration function
320 * that is used to adjust and optimize the chip performance. This
321 * takes environmental changes (location, temperature) into account.
322 * When the task is complete, it reschedules itself depending on the
323 * appropriate interval that was calculated.
325 static void ath_ani_calibrate(unsigned long data)
327 struct ath_softc *sc = (struct ath_softc *)data;
328 struct ath_hw *ah = sc->sc_ah;
329 bool longcal = false;
330 bool shortcal = false;
331 bool aniflag = false;
332 unsigned int timestamp = jiffies_to_msecs(jiffies);
333 u32 cal_interval, short_cal_interval;
335 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
336 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
339 * don't calibrate when we're scanning.
340 * we are most likely not on our home channel.
342 if (sc->sc_flags & SC_OP_SCANNING)
345 /* Only calibrate if awake */
346 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
351 /* Long calibration runs independently of short calibration. */
352 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
354 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
355 sc->ani.longcal_timer = timestamp;
358 /* Short calibration applies only while caldone is false */
359 if (!sc->ani.caldone) {
360 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
362 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
363 sc->ani.shortcal_timer = timestamp;
364 sc->ani.resetcal_timer = timestamp;
367 if ((timestamp - sc->ani.resetcal_timer) >=
368 ATH_RESTART_CALINTERVAL) {
369 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
371 sc->ani.resetcal_timer = timestamp;
375 /* Verify whether we must check ANI */
376 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
378 sc->ani.checkani_timer = timestamp;
381 /* Skip all processing if there's nothing to do. */
382 if (longcal || shortcal || aniflag) {
383 /* Call ANI routine if necessary */
385 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
387 /* Perform calibration if necessary */
388 if (longcal || shortcal) {
389 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
390 sc->rx_chainmask, longcal);
393 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
397 ah->curchan->channel, ah->curchan->channelFlags,
398 sc->ani.noise_floor);
402 ath9k_ps_restore(sc);
406 * Set timer interval based on previous results.
407 * The interval must be the shortest necessary to satisfy ANI,
408 * short calibration and long calibration.
410 cal_interval = ATH_LONG_CALINTERVAL;
411 if (sc->sc_ah->config.enable_ani)
412 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
413 if (!sc->ani.caldone)
414 cal_interval = min(cal_interval, (u32)short_cal_interval);
416 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
419 static void ath_start_ani(struct ath_softc *sc)
421 unsigned long timestamp = jiffies_to_msecs(jiffies);
423 sc->ani.longcal_timer = timestamp;
424 sc->ani.shortcal_timer = timestamp;
425 sc->ani.checkani_timer = timestamp;
427 mod_timer(&sc->ani.timer,
428 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432 * Update tx/rx chainmask. For legacy association,
433 * hard code chainmask to 1x1, for 11n association, use
434 * the chainmask configuration, for bt coexistence, use
435 * the chainmask configuration even in legacy mode.
437 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
440 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
441 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
442 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
444 sc->tx_chainmask = 1;
445 sc->rx_chainmask = 1;
448 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
449 sc->tx_chainmask, sc->rx_chainmask);
452 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456 an = (struct ath_node *)sta->drv_priv;
458 if (sc->sc_flags & SC_OP_TXAGGR) {
459 ath_tx_node_init(sc, an);
460 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
461 sta->ht_cap.ampdu_factor);
462 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
466 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
468 struct ath_node *an = (struct ath_node *)sta->drv_priv;
470 if (sc->sc_flags & SC_OP_TXAGGR)
471 ath_tx_node_cleanup(sc, an);
474 static void ath9k_tasklet(unsigned long data)
476 struct ath_softc *sc = (struct ath_softc *)data;
477 u32 status = sc->intrstatus;
481 if (status & ATH9K_INT_FATAL) {
482 ath_reset(sc, false);
483 ath9k_ps_restore(sc);
487 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
488 spin_lock_bh(&sc->rx.rxflushlock);
489 ath_rx_tasklet(sc, 0);
490 spin_unlock_bh(&sc->rx.rxflushlock);
493 if (status & ATH9K_INT_TX)
496 if ((status & ATH9K_INT_TSFOOR) &&
497 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
499 * TSF sync does not look correct; remain awake to sync with
502 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
503 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
506 /* re-enable hardware interrupt */
507 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
508 ath9k_ps_restore(sc);
511 irqreturn_t ath_isr(int irq, void *dev)
513 #define SCHED_INTR ( \
523 struct ath_softc *sc = dev;
524 struct ath_hw *ah = sc->sc_ah;
525 enum ath9k_int status;
529 * The hardware is not ready/present, don't
530 * touch anything. Note this can happen early
531 * on if the IRQ is shared.
533 if (sc->sc_flags & SC_OP_INVALID)
537 /* shared irq, not for us */
539 if (!ath9k_hw_intrpend(ah))
543 * Figure out the reason(s) for the interrupt. Note
544 * that the hal returns a pseudo-ISR that may include
545 * bits we haven't explicitly enabled so we mask the
546 * value to insure we only process bits we requested.
548 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
549 status &= sc->imask; /* discard unasked-for bits */
552 * If there are no status bits set, then this interrupt was not
553 * for me (should have been caught above).
558 /* Cache the status */
559 sc->intrstatus = status;
561 if (status & SCHED_INTR)
565 * If a FATAL or RXORN interrupt is received, we have to reset the
568 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
571 if (status & ATH9K_INT_SWBA)
572 tasklet_schedule(&sc->bcon_tasklet);
574 if (status & ATH9K_INT_TXURN)
575 ath9k_hw_updatetxtriglevel(ah, true);
577 if (status & ATH9K_INT_MIB) {
579 * Disable interrupts until we service the MIB
580 * interrupt; otherwise it will continue to
583 ath9k_hw_set_interrupts(ah, 0);
585 * Let the hal handle the event. We assume
586 * it will clear whatever condition caused
589 ath9k_hw_procmibevent(ah, &sc->nodestats);
590 ath9k_hw_set_interrupts(ah, sc->imask);
593 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
594 if (status & ATH9K_INT_TIM_TIMER) {
595 /* Clear RxAbort bit so that we can
597 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
598 ath9k_hw_setrxabort(sc->sc_ah, 0);
599 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
604 ath_debug_stat_interrupt(sc, status);
607 /* turn off every interrupt except SWBA */
608 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
609 tasklet_schedule(&sc->intr_tq);
617 static u32 ath_get_extchanmode(struct ath_softc *sc,
618 struct ieee80211_channel *chan,
619 enum nl80211_channel_type channel_type)
623 switch (chan->band) {
624 case IEEE80211_BAND_2GHZ:
625 switch(channel_type) {
626 case NL80211_CHAN_NO_HT:
627 case NL80211_CHAN_HT20:
628 chanmode = CHANNEL_G_HT20;
630 case NL80211_CHAN_HT40PLUS:
631 chanmode = CHANNEL_G_HT40PLUS;
633 case NL80211_CHAN_HT40MINUS:
634 chanmode = CHANNEL_G_HT40MINUS;
638 case IEEE80211_BAND_5GHZ:
639 switch(channel_type) {
640 case NL80211_CHAN_NO_HT:
641 case NL80211_CHAN_HT20:
642 chanmode = CHANNEL_A_HT20;
644 case NL80211_CHAN_HT40PLUS:
645 chanmode = CHANNEL_A_HT40PLUS;
647 case NL80211_CHAN_HT40MINUS:
648 chanmode = CHANNEL_A_HT40MINUS;
659 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
660 struct ath9k_keyval *hk, const u8 *addr,
666 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
667 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
671 * Group key installation - only two key cache entries are used
672 * regardless of splitmic capability since group key is only
673 * used either for TX or RX.
676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
677 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
679 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
680 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
682 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
685 /* TX and RX keys share the same key cache entry. */
686 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
687 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
688 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
691 /* Separate key cache entries for TX and RX */
693 /* TX key goes at first index, RX key at +32. */
694 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
695 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
696 /* TX MIC entry failed. No need to proceed further */
697 DPRINTF(sc, ATH_DBG_FATAL,
698 "Setting TX MIC Key Failed\n");
702 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
703 /* XXX delete tx key on failure? */
704 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
707 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
711 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
712 if (test_bit(i, sc->keymap) ||
713 test_bit(i + 64, sc->keymap))
714 continue; /* At least one part of TKIP key allocated */
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64 + 32, sc->keymap)))
718 continue; /* At least one part of TKIP key allocated */
720 /* Found a free slot for a TKIP key */
726 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
730 /* First, try to find slots that would not be available for TKIP. */
732 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
733 if (!test_bit(i, sc->keymap) &&
734 (test_bit(i + 32, sc->keymap) ||
735 test_bit(i + 64, sc->keymap) ||
736 test_bit(i + 64 + 32, sc->keymap)))
738 if (!test_bit(i + 32, sc->keymap) &&
739 (test_bit(i, sc->keymap) ||
740 test_bit(i + 64, sc->keymap) ||
741 test_bit(i + 64 + 32, sc->keymap)))
743 if (!test_bit(i + 64, sc->keymap) &&
744 (test_bit(i , sc->keymap) ||
745 test_bit(i + 32, sc->keymap) ||
746 test_bit(i + 64 + 32, sc->keymap)))
748 if (!test_bit(i + 64 + 32, sc->keymap) &&
749 (test_bit(i, sc->keymap) ||
750 test_bit(i + 32, sc->keymap) ||
751 test_bit(i + 64, sc->keymap)))
755 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
756 if (!test_bit(i, sc->keymap) &&
757 test_bit(i + 64, sc->keymap))
759 if (test_bit(i, sc->keymap) &&
760 !test_bit(i + 64, sc->keymap))
765 /* No partially used TKIP slots, pick any available slot */
766 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
767 /* Do not allow slots that could be needed for TKIP group keys
768 * to be used. This limitation could be removed if we know that
769 * TKIP will not be used. */
770 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
773 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
775 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
779 if (!test_bit(i, sc->keymap))
780 return i; /* Found a free slot for a key */
783 /* No free slot found */
787 static int ath_key_config(struct ath_softc *sc,
788 struct ieee80211_vif *vif,
789 struct ieee80211_sta *sta,
790 struct ieee80211_key_conf *key)
792 struct ath9k_keyval hk;
793 const u8 *mac = NULL;
797 memset(&hk, 0, sizeof(hk));
801 hk.kv_type = ATH9K_CIPHER_WEP;
804 hk.kv_type = ATH9K_CIPHER_TKIP;
807 hk.kv_type = ATH9K_CIPHER_AES_CCM;
813 hk.kv_len = key->keylen;
814 memcpy(hk.kv_val, key->key, key->keylen);
816 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
817 /* For now, use the default keys for broadcast keys. This may
818 * need to change with virtual interfaces. */
820 } else if (key->keyidx) {
825 if (vif->type != NL80211_IFTYPE_AP) {
826 /* Only keyidx 0 should be used with unicast key, but
827 * allow this for client mode for now. */
836 if (key->alg == ALG_TKIP)
837 idx = ath_reserve_key_cache_slot_tkip(sc);
839 idx = ath_reserve_key_cache_slot(sc);
841 return -ENOSPC; /* no free key cache entries */
844 if (key->alg == ALG_TKIP)
845 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
846 vif->type == NL80211_IFTYPE_AP);
848 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
853 set_bit(idx, sc->keymap);
854 if (key->alg == ALG_TKIP) {
855 set_bit(idx + 64, sc->keymap);
857 set_bit(idx + 32, sc->keymap);
858 set_bit(idx + 64 + 32, sc->keymap);
865 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
867 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
868 if (key->hw_key_idx < IEEE80211_WEP_NKID)
871 clear_bit(key->hw_key_idx, sc->keymap);
872 if (key->alg != ALG_TKIP)
875 clear_bit(key->hw_key_idx + 64, sc->keymap);
877 clear_bit(key->hw_key_idx + 32, sc->keymap);
878 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
882 static void setup_ht_cap(struct ath_softc *sc,
883 struct ieee80211_sta_ht_cap *ht_info)
885 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
886 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
888 ht_info->ht_supported = true;
889 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
890 IEEE80211_HT_CAP_SM_PS |
891 IEEE80211_HT_CAP_SGI_40 |
892 IEEE80211_HT_CAP_DSSSCCK40;
894 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
895 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
897 /* set up supported mcs set */
898 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
900 switch(sc->rx_chainmask) {
902 ht_info->mcs.rx_mask[0] = 0xff;
908 ht_info->mcs.rx_mask[0] = 0xff;
909 ht_info->mcs.rx_mask[1] = 0xff;
913 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
916 static void ath9k_bss_assoc_info(struct ath_softc *sc,
917 struct ieee80211_vif *vif,
918 struct ieee80211_bss_conf *bss_conf)
920 struct ath_vif *avp = (void *)vif->drv_priv;
922 if (bss_conf->assoc) {
923 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
924 bss_conf->aid, sc->curbssid);
926 /* New association, store aid */
927 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
928 sc->curaid = bss_conf->aid;
929 ath9k_hw_write_associd(sc);
932 * Request a re-configuration of Beacon related timers
933 * on the receipt of the first Beacon frame (i.e.,
934 * after time sync with the AP).
936 sc->sc_flags |= SC_OP_BEACON_SYNC;
939 /* Configure the beacon */
940 ath_beacon_config(sc, vif);
942 /* Reset rssi stats */
943 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
944 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
945 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
946 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
950 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
955 /********************************/
957 /********************************/
959 static void ath_led_blink_work(struct work_struct *work)
961 struct ath_softc *sc = container_of(work, struct ath_softc,
962 ath_led_blink_work.work);
964 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
967 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
968 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
969 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
971 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
972 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
974 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
975 (sc->sc_flags & SC_OP_LED_ON) ?
976 msecs_to_jiffies(sc->led_off_duration) :
977 msecs_to_jiffies(sc->led_on_duration));
979 sc->led_on_duration = sc->led_on_cnt ?
980 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
981 ATH_LED_ON_DURATION_IDLE;
982 sc->led_off_duration = sc->led_off_cnt ?
983 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
984 ATH_LED_OFF_DURATION_IDLE;
985 sc->led_on_cnt = sc->led_off_cnt = 0;
986 if (sc->sc_flags & SC_OP_LED_ON)
987 sc->sc_flags &= ~SC_OP_LED_ON;
989 sc->sc_flags |= SC_OP_LED_ON;
992 static void ath_led_brightness(struct led_classdev *led_cdev,
993 enum led_brightness brightness)
995 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
996 struct ath_softc *sc = led->sc;
998 switch (brightness) {
1000 if (led->led_type == ATH_LED_ASSOC ||
1001 led->led_type == ATH_LED_RADIO) {
1002 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1003 (led->led_type == ATH_LED_RADIO));
1004 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1005 if (led->led_type == ATH_LED_RADIO)
1006 sc->sc_flags &= ~SC_OP_LED_ON;
1012 if (led->led_type == ATH_LED_ASSOC) {
1013 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1014 queue_delayed_work(sc->hw->workqueue,
1015 &sc->ath_led_blink_work, 0);
1016 } else if (led->led_type == ATH_LED_RADIO) {
1017 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1018 sc->sc_flags |= SC_OP_LED_ON;
1028 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1034 led->led_cdev.name = led->name;
1035 led->led_cdev.default_trigger = trigger;
1036 led->led_cdev.brightness_set = ath_led_brightness;
1038 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1040 DPRINTF(sc, ATH_DBG_FATAL,
1041 "Failed to register led:%s", led->name);
1043 led->registered = 1;
1047 static void ath_unregister_led(struct ath_led *led)
1049 if (led->registered) {
1050 led_classdev_unregister(&led->led_cdev);
1051 led->registered = 0;
1055 static void ath_deinit_leds(struct ath_softc *sc)
1057 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1058 ath_unregister_led(&sc->assoc_led);
1059 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1060 ath_unregister_led(&sc->tx_led);
1061 ath_unregister_led(&sc->rx_led);
1062 ath_unregister_led(&sc->radio_led);
1063 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1066 static void ath_init_leds(struct ath_softc *sc)
1071 /* Configure gpio 1 for output */
1072 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1073 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1074 /* LED off, active low */
1075 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1077 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1079 trigger = ieee80211_get_radio_led_name(sc->hw);
1080 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1081 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1082 ret = ath_register_led(sc, &sc->radio_led, trigger);
1083 sc->radio_led.led_type = ATH_LED_RADIO;
1087 trigger = ieee80211_get_assoc_led_name(sc->hw);
1088 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1089 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1090 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1091 sc->assoc_led.led_type = ATH_LED_ASSOC;
1095 trigger = ieee80211_get_tx_led_name(sc->hw);
1096 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1097 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1098 ret = ath_register_led(sc, &sc->tx_led, trigger);
1099 sc->tx_led.led_type = ATH_LED_TX;
1103 trigger = ieee80211_get_rx_led_name(sc->hw);
1104 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1105 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1106 ret = ath_register_led(sc, &sc->rx_led, trigger);
1107 sc->rx_led.led_type = ATH_LED_RX;
1114 ath_deinit_leds(sc);
1117 void ath_radio_enable(struct ath_softc *sc)
1119 struct ath_hw *ah = sc->sc_ah;
1120 struct ieee80211_channel *channel = sc->hw->conf.channel;
1123 ath9k_ps_wakeup(sc);
1124 ath9k_hw_configpcipowersave(ah, 0);
1127 ah->curchan = ath_get_curchannel(sc, sc->hw);
1129 spin_lock_bh(&sc->sc_resetlock);
1130 r = ath9k_hw_reset(ah, ah->curchan, false);
1132 DPRINTF(sc, ATH_DBG_FATAL,
1133 "Unable to reset channel %u (%uMhz) ",
1134 "reset status %d\n",
1135 channel->center_freq, r);
1137 spin_unlock_bh(&sc->sc_resetlock);
1139 ath_update_txpow(sc);
1140 if (ath_startrecv(sc) != 0) {
1141 DPRINTF(sc, ATH_DBG_FATAL,
1142 "Unable to restart recv logic\n");
1146 if (sc->sc_flags & SC_OP_BEACONS)
1147 ath_beacon_config(sc, NULL); /* restart beacons */
1149 /* Re-Enable interrupts */
1150 ath9k_hw_set_interrupts(ah, sc->imask);
1153 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1154 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1155 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1157 ieee80211_wake_queues(sc->hw);
1158 ath9k_ps_restore(sc);
1161 void ath_radio_disable(struct ath_softc *sc)
1163 struct ath_hw *ah = sc->sc_ah;
1164 struct ieee80211_channel *channel = sc->hw->conf.channel;
1167 ath9k_ps_wakeup(sc);
1168 ieee80211_stop_queues(sc->hw);
1171 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1172 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1174 /* Disable interrupts */
1175 ath9k_hw_set_interrupts(ah, 0);
1177 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1178 ath_stoprecv(sc); /* turn off frame recv */
1179 ath_flushrecv(sc); /* flush recv queue */
1182 ah->curchan = ath_get_curchannel(sc, sc->hw);
1184 spin_lock_bh(&sc->sc_resetlock);
1185 r = ath9k_hw_reset(ah, ah->curchan, false);
1187 DPRINTF(sc, ATH_DBG_FATAL,
1188 "Unable to reset channel %u (%uMhz) "
1189 "reset status %d\n",
1190 channel->center_freq, r);
1192 spin_unlock_bh(&sc->sc_resetlock);
1194 ath9k_hw_phy_disable(ah);
1195 ath9k_hw_configpcipowersave(ah, 1);
1196 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1197 ath9k_ps_restore(sc);
1200 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1202 /*******************/
1204 /*******************/
1206 static bool ath_is_rfkill_set(struct ath_softc *sc)
1208 struct ath_hw *ah = sc->sc_ah;
1210 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1211 ah->rfkill_polarity;
1214 /* s/w rfkill handlers */
1215 static int ath_rfkill_set_block(void *data, bool blocked)
1217 struct ath_softc *sc = data;
1220 ath_radio_disable(sc);
1222 ath_radio_enable(sc);
1227 static void ath_rfkill_poll_state(struct rfkill *rfkill, void *data)
1229 struct ath_softc *sc = data;
1230 bool blocked = !!ath_is_rfkill_set(sc);
1232 if (rfkill_set_hw_state(rfkill, blocked))
1233 ath_radio_disable(sc);
1235 ath_radio_enable(sc);
1238 /* Init s/w rfkill */
1239 static int ath_init_sw_rfkill(struct ath_softc *sc)
1241 sc->rf_kill.ops.set_block = ath_rfkill_set_block;
1242 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1243 sc->rf_kill.ops.poll = ath_rfkill_poll_state;
1245 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1246 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1248 sc->rf_kill.rfkill = rfkill_alloc(sc->rf_kill.rfkill_name,
1249 wiphy_dev(sc->hw->wiphy),
1251 &sc->rf_kill.ops, sc);
1252 if (!sc->rf_kill.rfkill) {
1253 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1260 /* Deinitialize rfkill */
1261 static void ath_deinit_rfkill(struct ath_softc *sc)
1263 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1264 rfkill_unregister(sc->rf_kill.rfkill);
1265 rfkill_destroy(sc->rf_kill.rfkill);
1266 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1270 static int ath_start_rfkill_poll(struct ath_softc *sc)
1272 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1273 if (rfkill_register(sc->rf_kill.rfkill)) {
1274 DPRINTF(sc, ATH_DBG_FATAL,
1275 "Unable to register rfkill\n");
1276 rfkill_destroy(sc->rf_kill.rfkill);
1278 /* Deinitialize the device */
1282 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1288 #endif /* CONFIG_RFKILL */
1290 void ath_cleanup(struct ath_softc *sc)
1293 free_irq(sc->irq, sc);
1294 ath_bus_cleanup(sc);
1295 kfree(sc->sec_wiphy);
1296 ieee80211_free_hw(sc->hw);
1299 void ath_detach(struct ath_softc *sc)
1301 struct ieee80211_hw *hw = sc->hw;
1304 ath9k_ps_wakeup(sc);
1306 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1308 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1309 ath_deinit_rfkill(sc);
1311 ath_deinit_leds(sc);
1312 cancel_work_sync(&sc->chan_work);
1313 cancel_delayed_work_sync(&sc->wiphy_work);
1315 for (i = 0; i < sc->num_sec_wiphy; i++) {
1316 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1319 sc->sec_wiphy[i] = NULL;
1320 ieee80211_unregister_hw(aphy->hw);
1321 ieee80211_free_hw(aphy->hw);
1323 ieee80211_unregister_hw(hw);
1327 tasklet_kill(&sc->intr_tq);
1328 tasklet_kill(&sc->bcon_tasklet);
1330 if (!(sc->sc_flags & SC_OP_INVALID))
1331 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1333 /* cleanup tx queues */
1334 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1335 if (ATH_TXQ_SETUP(sc, i))
1336 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1338 ath9k_hw_detach(sc->sc_ah);
1339 ath9k_exit_debug(sc);
1340 ath9k_ps_restore(sc);
1343 static int ath9k_reg_notifier(struct wiphy *wiphy,
1344 struct regulatory_request *request)
1346 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1347 struct ath_wiphy *aphy = hw->priv;
1348 struct ath_softc *sc = aphy->sc;
1349 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1351 return ath_reg_notifier_apply(wiphy, request, reg);
1354 static int ath_init(u16 devid, struct ath_softc *sc)
1356 struct ath_hw *ah = NULL;
1361 /* XXX: hardware will not be ready until ath_open() being called */
1362 sc->sc_flags |= SC_OP_INVALID;
1364 if (ath9k_init_debug(sc) < 0)
1365 printk(KERN_ERR "Unable to create debugfs files\n");
1367 spin_lock_init(&sc->wiphy_lock);
1368 spin_lock_init(&sc->sc_resetlock);
1369 spin_lock_init(&sc->sc_serial_rw);
1370 mutex_init(&sc->mutex);
1371 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1372 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1376 * Cache line size is used to size and align various
1377 * structures used to communicate with the hardware.
1379 ath_read_cachesize(sc, &csz);
1380 /* XXX assert csz is non-zero */
1381 sc->cachelsz = csz << 2; /* convert to bytes */
1383 ah = ath9k_hw_attach(devid, sc, &status);
1385 DPRINTF(sc, ATH_DBG_FATAL,
1386 "Unable to attach hardware; HAL status %d\n", status);
1392 /* Get the hardware key cache size. */
1393 sc->keymax = ah->caps.keycache_size;
1394 if (sc->keymax > ATH_KEYMAX) {
1395 DPRINTF(sc, ATH_DBG_ANY,
1396 "Warning, using only %u entries in %u key cache\n",
1397 ATH_KEYMAX, sc->keymax);
1398 sc->keymax = ATH_KEYMAX;
1402 * Reset the key cache since some parts do not
1403 * reset the contents on initial power up.
1405 for (i = 0; i < sc->keymax; i++)
1406 ath9k_hw_keyreset(ah, (u16) i);
1411 /* default to MONITOR mode */
1412 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1414 /* Setup rate tables */
1416 ath_rate_attach(sc);
1417 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1418 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1421 * Allocate hardware transmit queues: one queue for
1422 * beacon frames and one data queue for each QoS
1423 * priority. Note that the hal handles reseting
1424 * these queues at the needed time.
1426 sc->beacon.beaconq = ath_beaconq_setup(ah);
1427 if (sc->beacon.beaconq == -1) {
1428 DPRINTF(sc, ATH_DBG_FATAL,
1429 "Unable to setup a beacon xmit queue\n");
1433 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1434 if (sc->beacon.cabq == NULL) {
1435 DPRINTF(sc, ATH_DBG_FATAL,
1436 "Unable to setup CAB xmit queue\n");
1441 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1442 ath_cabq_update(sc);
1444 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1445 sc->tx.hwq_map[i] = -1;
1447 /* Setup data queues */
1448 /* NB: ensure BK queue is the lowest priority h/w queue */
1449 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1450 DPRINTF(sc, ATH_DBG_FATAL,
1451 "Unable to setup xmit queue for BK traffic\n");
1456 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1457 DPRINTF(sc, ATH_DBG_FATAL,
1458 "Unable to setup xmit queue for BE traffic\n");
1462 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1463 DPRINTF(sc, ATH_DBG_FATAL,
1464 "Unable to setup xmit queue for VI traffic\n");
1468 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1469 DPRINTF(sc, ATH_DBG_FATAL,
1470 "Unable to setup xmit queue for VO traffic\n");
1475 /* Initializes the noise floor to a reasonable default value.
1476 * Later on this will be updated during ANI processing. */
1478 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1479 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1481 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1482 ATH9K_CIPHER_TKIP, NULL)) {
1484 * Whether we should enable h/w TKIP MIC.
1485 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1486 * report WMM capable, so it's always safe to turn on
1487 * TKIP MIC in this case.
1489 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1494 * Check whether the separate key cache entries
1495 * are required to handle both tx+rx MIC keys.
1496 * With split mic keys the number of stations is limited
1497 * to 27 otherwise 59.
1499 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1500 ATH9K_CIPHER_TKIP, NULL)
1501 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1502 ATH9K_CIPHER_MIC, NULL)
1503 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1507 /* turn on mcast key search if possible */
1508 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1509 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1512 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1514 /* 11n Capabilities */
1515 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1516 sc->sc_flags |= SC_OP_TXAGGR;
1517 sc->sc_flags |= SC_OP_RXAGGR;
1520 sc->tx_chainmask = ah->caps.tx_chainmask;
1521 sc->rx_chainmask = ah->caps.rx_chainmask;
1523 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1524 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1526 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1527 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1529 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1531 /* initialize beacon slots */
1532 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1533 sc->beacon.bslot[i] = NULL;
1534 sc->beacon.bslot_aphy[i] = NULL;
1537 /* setup channels and rates */
1539 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1540 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1541 sc->rates[IEEE80211_BAND_2GHZ];
1542 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1543 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1544 ARRAY_SIZE(ath9k_2ghz_chantable);
1546 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1547 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1548 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1549 sc->rates[IEEE80211_BAND_5GHZ];
1550 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1551 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1552 ARRAY_SIZE(ath9k_5ghz_chantable);
1555 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1556 ath9k_hw_btcoex_enable(sc->sc_ah);
1560 /* cleanup tx queues */
1561 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1562 if (ATH_TXQ_SETUP(sc, i))
1563 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1566 ath9k_hw_detach(ah);
1567 ath9k_exit_debug(sc);
1572 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1574 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1575 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1576 IEEE80211_HW_SIGNAL_DBM |
1577 IEEE80211_HW_AMPDU_AGGREGATION |
1578 IEEE80211_HW_SUPPORTS_PS |
1579 IEEE80211_HW_PS_NULLFUNC_STACK |
1580 IEEE80211_HW_SPECTRUM_MGMT;
1582 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1583 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1585 hw->wiphy->interface_modes =
1586 BIT(NL80211_IFTYPE_AP) |
1587 BIT(NL80211_IFTYPE_STATION) |
1588 BIT(NL80211_IFTYPE_ADHOC) |
1589 BIT(NL80211_IFTYPE_MESH_POINT);
1593 hw->channel_change_time = 5000;
1594 hw->max_listen_interval = 10;
1595 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1596 hw->sta_data_size = sizeof(struct ath_node);
1597 hw->vif_data_size = sizeof(struct ath_vif);
1599 hw->rate_control_algorithm = "ath9k_rate_control";
1601 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1602 &sc->sbands[IEEE80211_BAND_2GHZ];
1603 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1604 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1605 &sc->sbands[IEEE80211_BAND_5GHZ];
1608 int ath_attach(u16 devid, struct ath_softc *sc)
1610 struct ieee80211_hw *hw = sc->hw;
1612 struct ath_regulatory *reg;
1614 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1616 error = ath_init(devid, sc);
1620 /* get mac address from hardware and set in mac80211 */
1622 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1624 ath_set_hw_capab(sc, hw);
1626 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1627 ath9k_reg_notifier);
1631 reg = &sc->sc_ah->regulatory;
1633 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1634 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1635 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1636 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1639 /* initialize tx/rx engine */
1640 error = ath_tx_init(sc, ATH_TXBUF);
1644 error = ath_rx_init(sc, ATH_RXBUF);
1648 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1649 /* Initialize s/w rfkill */
1650 error = ath_init_sw_rfkill(sc);
1655 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1656 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1657 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1659 error = ieee80211_register_hw(hw);
1661 if (!ath_is_world_regd(reg)) {
1662 error = regulatory_hint(hw->wiphy, reg->alpha2);
1667 /* Initialize LED control */
1674 /* cleanup tx queues */
1675 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1676 if (ATH_TXQ_SETUP(sc, i))
1677 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1679 ath9k_hw_detach(sc->sc_ah);
1680 ath9k_exit_debug(sc);
1685 int ath_reset(struct ath_softc *sc, bool retry_tx)
1687 struct ath_hw *ah = sc->sc_ah;
1688 struct ieee80211_hw *hw = sc->hw;
1691 ath9k_hw_set_interrupts(ah, 0);
1692 ath_drain_all_txq(sc, retry_tx);
1696 spin_lock_bh(&sc->sc_resetlock);
1697 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1699 DPRINTF(sc, ATH_DBG_FATAL,
1700 "Unable to reset hardware; reset status %d\n", r);
1701 spin_unlock_bh(&sc->sc_resetlock);
1703 if (ath_startrecv(sc) != 0)
1704 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1707 * We may be doing a reset in response to a request
1708 * that changes the channel so update any state that
1709 * might change as a result.
1711 ath_cache_conf_rate(sc, &hw->conf);
1713 ath_update_txpow(sc);
1715 if (sc->sc_flags & SC_OP_BEACONS)
1716 ath_beacon_config(sc, NULL); /* restart beacons */
1718 ath9k_hw_set_interrupts(ah, sc->imask);
1722 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1723 if (ATH_TXQ_SETUP(sc, i)) {
1724 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1725 ath_txq_schedule(sc, &sc->tx.txq[i]);
1726 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1735 * This function will allocate both the DMA descriptor structure, and the
1736 * buffers it contains. These are used to contain the descriptors used
1739 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1740 struct list_head *head, const char *name,
1741 int nbuf, int ndesc)
1743 #define DS2PHYS(_dd, _ds) \
1744 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1745 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1746 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1748 struct ath_desc *ds;
1750 int i, bsize, error;
1752 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1755 INIT_LIST_HEAD(head);
1756 /* ath_desc must be a multiple of DWORDs */
1757 if ((sizeof(struct ath_desc) % 4) != 0) {
1758 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1759 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1764 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1767 * Need additional DMA memory because we can't use
1768 * descriptors that cross the 4K page boundary. Assume
1769 * one skipped descriptor per 4K page.
1771 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1773 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1776 while (ndesc_skipped) {
1777 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1778 dd->dd_desc_len += dma_len;
1780 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1784 /* allocate descriptors */
1785 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1786 &dd->dd_desc_paddr, GFP_KERNEL);
1787 if (dd->dd_desc == NULL) {
1792 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1793 name, ds, (u32) dd->dd_desc_len,
1794 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1796 /* allocate buffers */
1797 bsize = sizeof(struct ath_buf) * nbuf;
1798 bf = kzalloc(bsize, GFP_KERNEL);
1805 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1807 bf->bf_daddr = DS2PHYS(dd, ds);
1809 if (!(sc->sc_ah->caps.hw_caps &
1810 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1812 * Skip descriptor addresses which can cause 4KB
1813 * boundary crossing (addr + length) with a 32 dword
1816 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1817 ASSERT((caddr_t) bf->bf_desc <
1818 ((caddr_t) dd->dd_desc +
1823 bf->bf_daddr = DS2PHYS(dd, ds);
1826 list_add_tail(&bf->list, head);
1830 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1833 memset(dd, 0, sizeof(*dd));
1835 #undef ATH_DESC_4KB_BOUND_CHECK
1836 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1840 void ath_descdma_cleanup(struct ath_softc *sc,
1841 struct ath_descdma *dd,
1842 struct list_head *head)
1844 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1847 INIT_LIST_HEAD(head);
1848 kfree(dd->dd_bufptr);
1849 memset(dd, 0, sizeof(*dd));
1852 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1858 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1861 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1864 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1867 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1870 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1877 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1882 case ATH9K_WME_AC_VO:
1885 case ATH9K_WME_AC_VI:
1888 case ATH9K_WME_AC_BE:
1891 case ATH9K_WME_AC_BK:
1902 /* XXX: Remove me once we don't depend on ath9k_channel for all
1903 * this redundant data */
1904 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1905 struct ath9k_channel *ichan)
1907 struct ieee80211_channel *chan = hw->conf.channel;
1908 struct ieee80211_conf *conf = &hw->conf;
1910 ichan->channel = chan->center_freq;
1913 if (chan->band == IEEE80211_BAND_2GHZ) {
1914 ichan->chanmode = CHANNEL_G;
1915 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1917 ichan->chanmode = CHANNEL_A;
1918 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1921 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1923 if (conf_is_ht(conf)) {
1924 if (conf_is_ht40(conf))
1925 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1927 ichan->chanmode = ath_get_extchanmode(sc, chan,
1928 conf->channel_type);
1932 /**********************/
1933 /* mac80211 callbacks */
1934 /**********************/
1936 static int ath9k_start(struct ieee80211_hw *hw)
1938 struct ath_wiphy *aphy = hw->priv;
1939 struct ath_softc *sc = aphy->sc;
1940 struct ieee80211_channel *curchan = hw->conf.channel;
1941 struct ath9k_channel *init_channel;
1944 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1945 "initial channel: %d MHz\n", curchan->center_freq);
1947 mutex_lock(&sc->mutex);
1949 if (ath9k_wiphy_started(sc)) {
1950 if (sc->chan_idx == curchan->hw_value) {
1952 * Already on the operational channel, the new wiphy
1953 * can be marked active.
1955 aphy->state = ATH_WIPHY_ACTIVE;
1956 ieee80211_wake_queues(hw);
1959 * Another wiphy is on another channel, start the new
1960 * wiphy in paused state.
1962 aphy->state = ATH_WIPHY_PAUSED;
1963 ieee80211_stop_queues(hw);
1965 mutex_unlock(&sc->mutex);
1968 aphy->state = ATH_WIPHY_ACTIVE;
1970 /* setup initial channel */
1972 sc->chan_idx = curchan->hw_value;
1974 init_channel = ath_get_curchannel(sc, hw);
1976 /* Reset SERDES registers */
1977 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1980 * The basic interface to setting the hardware in a good
1981 * state is ``reset''. On return the hardware is known to
1982 * be powered up and with interrupts disabled. This must
1983 * be followed by initialization of the appropriate bits
1984 * and then setup of the interrupt mask.
1986 spin_lock_bh(&sc->sc_resetlock);
1987 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1989 DPRINTF(sc, ATH_DBG_FATAL,
1990 "Unable to reset hardware; reset status %d "
1991 "(freq %u MHz)\n", r,
1992 curchan->center_freq);
1993 spin_unlock_bh(&sc->sc_resetlock);
1996 spin_unlock_bh(&sc->sc_resetlock);
1999 * This is needed only to setup initial state
2000 * but it's best done after a reset.
2002 ath_update_txpow(sc);
2005 * Setup the hardware after reset:
2006 * The receive engine is set going.
2007 * Frame transmit is handled entirely
2008 * in the frame output path; there's nothing to do
2009 * here except setup the interrupt mask.
2011 if (ath_startrecv(sc) != 0) {
2012 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
2017 /* Setup our intr mask. */
2018 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2019 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2020 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2022 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2023 sc->imask |= ATH9K_INT_GTT;
2025 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2026 sc->imask |= ATH9K_INT_CST;
2028 ath_cache_conf_rate(sc, &hw->conf);
2030 sc->sc_flags &= ~SC_OP_INVALID;
2032 /* Disable BMISS interrupt when we're not associated */
2033 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2034 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2036 ieee80211_wake_queues(hw);
2038 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2039 r = ath_start_rfkill_poll(sc);
2043 mutex_unlock(&sc->mutex);
2048 static int ath9k_tx(struct ieee80211_hw *hw,
2049 struct sk_buff *skb)
2051 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2052 struct ath_wiphy *aphy = hw->priv;
2053 struct ath_softc *sc = aphy->sc;
2054 struct ath_tx_control txctl;
2055 int hdrlen, padsize;
2057 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2058 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2059 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2063 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2064 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2066 * mac80211 does not set PM field for normal data frames, so we
2067 * need to update that based on the current PS mode.
2069 if (ieee80211_is_data(hdr->frame_control) &&
2070 !ieee80211_is_nullfunc(hdr->frame_control) &&
2071 !ieee80211_has_pm(hdr->frame_control)) {
2072 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2073 "while in PS mode\n");
2074 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2078 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2080 * We are using PS-Poll and mac80211 can request TX while in
2081 * power save mode. Need to wake up hardware for the TX to be
2082 * completed and if needed, also for RX of buffered frames.
2084 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2085 ath9k_ps_wakeup(sc);
2086 ath9k_hw_setrxabort(sc->sc_ah, 0);
2087 if (ieee80211_is_pspoll(hdr->frame_control)) {
2088 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2089 "buffered frame\n");
2090 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2092 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2093 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2096 * The actual restore operation will happen only after
2097 * the sc_flags bit is cleared. We are just dropping
2098 * the ps_usecount here.
2100 ath9k_ps_restore(sc);
2103 memset(&txctl, 0, sizeof(struct ath_tx_control));
2106 * As a temporary workaround, assign seq# here; this will likely need
2107 * to be cleaned up to work better with Beacon transmission and virtual
2110 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2111 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2112 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2113 sc->tx.seq_no += 0x10;
2114 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2115 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2118 /* Add the padding after the header if this is not already done */
2119 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2121 padsize = hdrlen % 4;
2122 if (skb_headroom(skb) < padsize)
2124 skb_push(skb, padsize);
2125 memmove(skb->data, skb->data + padsize, hdrlen);
2128 /* Check if a tx queue is available */
2130 txctl.txq = ath_test_get_txq(sc, skb);
2134 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2136 if (ath_tx_start(hw, skb, &txctl) != 0) {
2137 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2143 dev_kfree_skb_any(skb);
2147 static void ath9k_stop(struct ieee80211_hw *hw)
2149 struct ath_wiphy *aphy = hw->priv;
2150 struct ath_softc *sc = aphy->sc;
2152 aphy->state = ATH_WIPHY_INACTIVE;
2154 if (sc->sc_flags & SC_OP_INVALID) {
2155 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2159 mutex_lock(&sc->mutex);
2161 ieee80211_stop_queues(hw);
2163 if (ath9k_wiphy_started(sc)) {
2164 mutex_unlock(&sc->mutex);
2165 return; /* another wiphy still in use */
2168 /* make sure h/w will not generate any interrupt
2169 * before setting the invalid flag. */
2170 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2172 if (!(sc->sc_flags & SC_OP_INVALID)) {
2173 ath_drain_all_txq(sc, false);
2175 ath9k_hw_phy_disable(sc->sc_ah);
2177 sc->rx.rxlink = NULL;
2179 rfkill_pause_polling(sc->rf_kill.rfkill);
2181 /* disable HAL and put h/w to sleep */
2182 ath9k_hw_disable(sc->sc_ah);
2183 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2185 sc->sc_flags |= SC_OP_INVALID;
2187 mutex_unlock(&sc->mutex);
2189 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2192 static int ath9k_add_interface(struct ieee80211_hw *hw,
2193 struct ieee80211_if_init_conf *conf)
2195 struct ath_wiphy *aphy = hw->priv;
2196 struct ath_softc *sc = aphy->sc;
2197 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2198 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2201 mutex_lock(&sc->mutex);
2203 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2209 switch (conf->type) {
2210 case NL80211_IFTYPE_STATION:
2211 ic_opmode = NL80211_IFTYPE_STATION;
2213 case NL80211_IFTYPE_ADHOC:
2214 case NL80211_IFTYPE_AP:
2215 case NL80211_IFTYPE_MESH_POINT:
2216 if (sc->nbcnvifs >= ATH_BCBUF) {
2220 ic_opmode = conf->type;
2223 DPRINTF(sc, ATH_DBG_FATAL,
2224 "Interface type %d not yet supported\n", conf->type);
2229 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2231 /* Set the VIF opmode */
2232 avp->av_opmode = ic_opmode;
2237 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2238 ath9k_set_bssid_mask(hw);
2241 goto out; /* skip global settings for secondary vif */
2243 if (ic_opmode == NL80211_IFTYPE_AP) {
2244 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2245 sc->sc_flags |= SC_OP_TSF_RESET;
2248 /* Set the device opmode */
2249 sc->sc_ah->opmode = ic_opmode;
2252 * Enable MIB interrupts when there are hardware phy counters.
2253 * Note we only do this (at the moment) for station mode.
2255 if ((conf->type == NL80211_IFTYPE_STATION) ||
2256 (conf->type == NL80211_IFTYPE_ADHOC) ||
2257 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2258 if (ath9k_hw_phycounters(sc->sc_ah))
2259 sc->imask |= ATH9K_INT_MIB;
2260 sc->imask |= ATH9K_INT_TSFOOR;
2263 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2265 if (conf->type == NL80211_IFTYPE_AP)
2269 mutex_unlock(&sc->mutex);
2273 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2274 struct ieee80211_if_init_conf *conf)
2276 struct ath_wiphy *aphy = hw->priv;
2277 struct ath_softc *sc = aphy->sc;
2278 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2281 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2283 mutex_lock(&sc->mutex);
2286 del_timer_sync(&sc->ani.timer);
2288 /* Reclaim beacon resources */
2289 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2290 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2291 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2292 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2293 ath_beacon_return(sc, avp);
2296 sc->sc_flags &= ~SC_OP_BEACONS;
2298 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2299 if (sc->beacon.bslot[i] == conf->vif) {
2300 printk(KERN_DEBUG "%s: vif had allocated beacon "
2301 "slot\n", __func__);
2302 sc->beacon.bslot[i] = NULL;
2303 sc->beacon.bslot_aphy[i] = NULL;
2309 mutex_unlock(&sc->mutex);
2312 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2314 struct ath_wiphy *aphy = hw->priv;
2315 struct ath_softc *sc = aphy->sc;
2316 struct ieee80211_conf *conf = &hw->conf;
2317 struct ath_hw *ah = sc->sc_ah;
2319 mutex_lock(&sc->mutex);
2321 if (changed & IEEE80211_CONF_CHANGE_PS) {
2322 if (conf->flags & IEEE80211_CONF_PS) {
2323 if (!(ah->caps.hw_caps &
2324 ATH9K_HW_CAP_AUTOSLEEP)) {
2325 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2326 sc->imask |= ATH9K_INT_TIM_TIMER;
2327 ath9k_hw_set_interrupts(sc->sc_ah,
2330 ath9k_hw_setrxabort(sc->sc_ah, 1);
2332 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2334 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2335 if (!(ah->caps.hw_caps &
2336 ATH9K_HW_CAP_AUTOSLEEP)) {
2337 ath9k_hw_setrxabort(sc->sc_ah, 0);
2338 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2339 SC_OP_WAIT_FOR_CAB |
2340 SC_OP_WAIT_FOR_PSPOLL_DATA |
2341 SC_OP_WAIT_FOR_TX_ACK);
2342 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2343 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2344 ath9k_hw_set_interrupts(sc->sc_ah,
2351 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2352 struct ieee80211_channel *curchan = hw->conf.channel;
2353 int pos = curchan->hw_value;
2355 aphy->chan_idx = pos;
2356 aphy->chan_is_ht = conf_is_ht(conf);
2358 if (aphy->state == ATH_WIPHY_SCAN ||
2359 aphy->state == ATH_WIPHY_ACTIVE)
2360 ath9k_wiphy_pause_all_forced(sc, aphy);
2363 * Do not change operational channel based on a paused
2366 goto skip_chan_change;
2369 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2370 curchan->center_freq);
2372 /* XXX: remove me eventualy */
2373 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2375 ath_update_chainmask(sc, conf_is_ht(conf));
2377 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2378 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2379 mutex_unlock(&sc->mutex);
2385 if (changed & IEEE80211_CONF_CHANGE_POWER)
2386 sc->config.txpowlimit = 2 * conf->power_level;
2388 mutex_unlock(&sc->mutex);
2393 #define SUPPORTED_FILTERS \
2394 (FIF_PROMISC_IN_BSS | \
2398 FIF_BCN_PRBRESP_PROMISC | \
2401 /* FIXME: sc->sc_full_reset ? */
2402 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2403 unsigned int changed_flags,
2404 unsigned int *total_flags,
2406 struct dev_mc_list *mclist)
2408 struct ath_wiphy *aphy = hw->priv;
2409 struct ath_softc *sc = aphy->sc;
2412 changed_flags &= SUPPORTED_FILTERS;
2413 *total_flags &= SUPPORTED_FILTERS;
2415 sc->rx.rxfilter = *total_flags;
2416 ath9k_ps_wakeup(sc);
2417 rfilt = ath_calcrxfilter(sc);
2418 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2419 ath9k_ps_restore(sc);
2421 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2424 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2425 struct ieee80211_vif *vif,
2426 enum sta_notify_cmd cmd,
2427 struct ieee80211_sta *sta)
2429 struct ath_wiphy *aphy = hw->priv;
2430 struct ath_softc *sc = aphy->sc;
2433 case STA_NOTIFY_ADD:
2434 ath_node_attach(sc, sta);
2436 case STA_NOTIFY_REMOVE:
2437 ath_node_detach(sc, sta);
2444 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2445 const struct ieee80211_tx_queue_params *params)
2447 struct ath_wiphy *aphy = hw->priv;
2448 struct ath_softc *sc = aphy->sc;
2449 struct ath9k_tx_queue_info qi;
2452 if (queue >= WME_NUM_AC)
2455 mutex_lock(&sc->mutex);
2457 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2459 qi.tqi_aifs = params->aifs;
2460 qi.tqi_cwmin = params->cw_min;
2461 qi.tqi_cwmax = params->cw_max;
2462 qi.tqi_burstTime = params->txop;
2463 qnum = ath_get_hal_qnum(queue, sc);
2465 DPRINTF(sc, ATH_DBG_CONFIG,
2466 "Configure tx [queue/halq] [%d/%d], "
2467 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2468 queue, qnum, params->aifs, params->cw_min,
2469 params->cw_max, params->txop);
2471 ret = ath_txq_update(sc, qnum, &qi);
2473 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2475 mutex_unlock(&sc->mutex);
2480 static int ath9k_set_key(struct ieee80211_hw *hw,
2481 enum set_key_cmd cmd,
2482 struct ieee80211_vif *vif,
2483 struct ieee80211_sta *sta,
2484 struct ieee80211_key_conf *key)
2486 struct ath_wiphy *aphy = hw->priv;
2487 struct ath_softc *sc = aphy->sc;
2490 if (modparam_nohwcrypt)
2493 mutex_lock(&sc->mutex);
2494 ath9k_ps_wakeup(sc);
2495 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2499 ret = ath_key_config(sc, vif, sta, key);
2501 key->hw_key_idx = ret;
2502 /* push IV and Michael MIC generation to stack */
2503 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2504 if (key->alg == ALG_TKIP)
2505 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2506 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2507 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2512 ath_key_delete(sc, key);
2518 ath9k_ps_restore(sc);
2519 mutex_unlock(&sc->mutex);
2524 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2525 struct ieee80211_vif *vif,
2526 struct ieee80211_bss_conf *bss_conf,
2529 struct ath_wiphy *aphy = hw->priv;
2530 struct ath_softc *sc = aphy->sc;
2531 struct ath_hw *ah = sc->sc_ah;
2532 struct ath_vif *avp = (void *)vif->drv_priv;
2536 mutex_lock(&sc->mutex);
2539 * TODO: Need to decide which hw opmode to use for
2540 * multi-interface cases
2541 * XXX: This belongs into add_interface!
2543 if (vif->type == NL80211_IFTYPE_AP &&
2544 ah->opmode != NL80211_IFTYPE_AP) {
2545 ah->opmode = NL80211_IFTYPE_STATION;
2546 ath9k_hw_setopmode(ah);
2547 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2549 ath9k_hw_write_associd(sc);
2550 /* Request full reset to get hw opmode changed properly */
2551 sc->sc_flags |= SC_OP_FULL_RESET;
2554 if ((changed & BSS_CHANGED_BSSID) &&
2555 !is_zero_ether_addr(bss_conf->bssid)) {
2556 switch (vif->type) {
2557 case NL80211_IFTYPE_STATION:
2558 case NL80211_IFTYPE_ADHOC:
2559 case NL80211_IFTYPE_MESH_POINT:
2561 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2562 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2564 ath9k_hw_write_associd(sc);
2566 /* Set aggregation protection mode parameters */
2567 sc->config.ath_aggr_prot = 0;
2569 DPRINTF(sc, ATH_DBG_CONFIG,
2570 "RX filter 0x%x bssid %pM aid 0x%x\n",
2571 rfilt, sc->curbssid, sc->curaid);
2573 /* need to reconfigure the beacon */
2574 sc->sc_flags &= ~SC_OP_BEACONS ;
2582 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2583 (vif->type == NL80211_IFTYPE_AP) ||
2584 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2585 if ((changed & BSS_CHANGED_BEACON) ||
2586 (changed & BSS_CHANGED_BEACON_ENABLED &&
2587 bss_conf->enable_beacon)) {
2589 * Allocate and setup the beacon frame.
2591 * Stop any previous beacon DMA. This may be
2592 * necessary, for example, when an ibss merge
2593 * causes reconfiguration; we may be called
2594 * with beacon transmission active.
2596 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2598 error = ath_beacon_alloc(aphy, vif);
2600 ath_beacon_config(sc, vif);
2604 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2605 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2606 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2607 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2608 ath9k_hw_keysetmac(sc->sc_ah,
2613 /* Only legacy IBSS for now */
2614 if (vif->type == NL80211_IFTYPE_ADHOC)
2615 ath_update_chainmask(sc, 0);
2617 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2618 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2619 bss_conf->use_short_preamble);
2620 if (bss_conf->use_short_preamble)
2621 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2623 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2626 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2627 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2628 bss_conf->use_cts_prot);
2629 if (bss_conf->use_cts_prot &&
2630 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2631 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2633 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2636 if (changed & BSS_CHANGED_ASSOC) {
2637 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2639 ath9k_bss_assoc_info(sc, vif, bss_conf);
2643 * The HW TSF has to be reset when the beacon interval changes.
2644 * We set the flag here, and ath_beacon_config_ap() would take this
2645 * into account when it gets called through the subsequent
2646 * config_interface() call - with IFCC_BEACON in the changed field.
2649 if (changed & BSS_CHANGED_BEACON_INT) {
2650 sc->sc_flags |= SC_OP_TSF_RESET;
2651 sc->beacon_interval = bss_conf->beacon_int;
2654 mutex_unlock(&sc->mutex);
2657 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2660 struct ath_wiphy *aphy = hw->priv;
2661 struct ath_softc *sc = aphy->sc;
2663 mutex_lock(&sc->mutex);
2664 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2665 mutex_unlock(&sc->mutex);
2670 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2672 struct ath_wiphy *aphy = hw->priv;
2673 struct ath_softc *sc = aphy->sc;
2675 mutex_lock(&sc->mutex);
2676 ath9k_hw_settsf64(sc->sc_ah, tsf);
2677 mutex_unlock(&sc->mutex);
2680 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2682 struct ath_wiphy *aphy = hw->priv;
2683 struct ath_softc *sc = aphy->sc;
2685 mutex_lock(&sc->mutex);
2686 ath9k_hw_reset_tsf(sc->sc_ah);
2687 mutex_unlock(&sc->mutex);
2690 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2691 enum ieee80211_ampdu_mlme_action action,
2692 struct ieee80211_sta *sta,
2695 struct ath_wiphy *aphy = hw->priv;
2696 struct ath_softc *sc = aphy->sc;
2700 case IEEE80211_AMPDU_RX_START:
2701 if (!(sc->sc_flags & SC_OP_RXAGGR))
2704 case IEEE80211_AMPDU_RX_STOP:
2706 case IEEE80211_AMPDU_TX_START:
2707 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2709 DPRINTF(sc, ATH_DBG_FATAL,
2710 "Unable to start TX aggregation\n");
2712 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2714 case IEEE80211_AMPDU_TX_STOP:
2715 ret = ath_tx_aggr_stop(sc, sta, tid);
2717 DPRINTF(sc, ATH_DBG_FATAL,
2718 "Unable to stop TX aggregation\n");
2720 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2722 case IEEE80211_AMPDU_TX_OPERATIONAL:
2723 ath_tx_aggr_resume(sc, sta, tid);
2726 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2732 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2734 struct ath_wiphy *aphy = hw->priv;
2735 struct ath_softc *sc = aphy->sc;
2737 if (ath9k_wiphy_scanning(sc)) {
2738 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2741 * Do not allow the concurrent scanning state for now. This
2742 * could be improved with scanning control moved into ath9k.
2747 aphy->state = ATH_WIPHY_SCAN;
2748 ath9k_wiphy_pause_all_forced(sc, aphy);
2750 mutex_lock(&sc->mutex);
2751 sc->sc_flags |= SC_OP_SCANNING;
2752 mutex_unlock(&sc->mutex);
2755 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2757 struct ath_wiphy *aphy = hw->priv;
2758 struct ath_softc *sc = aphy->sc;
2760 mutex_lock(&sc->mutex);
2761 aphy->state = ATH_WIPHY_ACTIVE;
2762 sc->sc_flags &= ~SC_OP_SCANNING;
2763 sc->sc_flags |= SC_OP_FULL_RESET;
2764 mutex_unlock(&sc->mutex);
2767 struct ieee80211_ops ath9k_ops = {
2769 .start = ath9k_start,
2771 .add_interface = ath9k_add_interface,
2772 .remove_interface = ath9k_remove_interface,
2773 .config = ath9k_config,
2774 .configure_filter = ath9k_configure_filter,
2775 .sta_notify = ath9k_sta_notify,
2776 .conf_tx = ath9k_conf_tx,
2777 .bss_info_changed = ath9k_bss_info_changed,
2778 .set_key = ath9k_set_key,
2779 .get_tsf = ath9k_get_tsf,
2780 .set_tsf = ath9k_set_tsf,
2781 .reset_tsf = ath9k_reset_tsf,
2782 .ampdu_action = ath9k_ampdu_action,
2783 .sw_scan_start = ath9k_sw_scan_start,
2784 .sw_scan_complete = ath9k_sw_scan_complete,
2790 } ath_mac_bb_names[] = {
2791 { AR_SREV_VERSION_5416_PCI, "5416" },
2792 { AR_SREV_VERSION_5416_PCIE, "5418" },
2793 { AR_SREV_VERSION_9100, "9100" },
2794 { AR_SREV_VERSION_9160, "9160" },
2795 { AR_SREV_VERSION_9280, "9280" },
2796 { AR_SREV_VERSION_9285, "9285" }
2802 } ath_rf_names[] = {
2804 { AR_RAD5133_SREV_MAJOR, "5133" },
2805 { AR_RAD5122_SREV_MAJOR, "5122" },
2806 { AR_RAD2133_SREV_MAJOR, "2133" },
2807 { AR_RAD2122_SREV_MAJOR, "2122" }
2811 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2814 ath_mac_bb_name(u32 mac_bb_version)
2818 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2819 if (ath_mac_bb_names[i].version == mac_bb_version) {
2820 return ath_mac_bb_names[i].name;
2828 * Return the RF name. "????" is returned if the RF is unknown.
2831 ath_rf_name(u16 rf_version)
2835 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2836 if (ath_rf_names[i].version == rf_version) {
2837 return ath_rf_names[i].name;
2844 static int __init ath9k_init(void)
2848 /* Register rate control algorithm */
2849 error = ath_rate_control_register();
2852 "ath9k: Unable to register rate control "
2858 error = ath9k_debug_create_root();
2861 "ath9k: Unable to create debugfs root: %d\n",
2863 goto err_rate_unregister;
2866 error = ath_pci_init();
2869 "ath9k: No PCI devices found, driver not installed.\n");
2871 goto err_remove_root;
2874 error = ath_ahb_init();
2886 ath9k_debug_remove_root();
2887 err_rate_unregister:
2888 ath_rate_control_unregister();
2892 module_init(ath9k_init);
2894 static void __exit ath9k_exit(void)
2898 ath9k_debug_remove_root();
2899 ath_rate_control_unregister();
2900 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2902 module_exit(ath9k_exit);