2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
21 static char *dev_info = "ath9k";
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
28 static int modparam_nohwcrypt;
29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33 module_param_named(debug, ath9k_debug, uint, 0);
34 MODULE_PARM_DESC(ath9k_debug, "Debugging mask");
36 /* We use the hw_value as an index into our private channel structure */
38 #define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
44 #define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
51 /* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
55 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
72 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
76 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
107 static void ath_cache_conf_rate(struct ath_softc *sc,
108 struct ieee80211_conf *conf)
110 switch (conf->channel->band) {
111 case IEEE80211_BAND_2GHZ:
112 if (conf_is_ht20(conf))
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
115 else if (conf_is_ht40_minus(conf))
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
118 else if (conf_is_ht40_plus(conf))
120 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
123 sc->hw_rate_table[ATH9K_MODE_11G];
125 case IEEE80211_BAND_5GHZ:
126 if (conf_is_ht20(conf))
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
129 else if (conf_is_ht40_minus(conf))
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
132 else if (conf_is_ht40_plus(conf))
134 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
137 sc->hw_rate_table[ATH9K_MODE_11A];
145 static void ath_update_txpow(struct ath_softc *sc)
147 struct ath_hw *ah = sc->sc_ah;
150 if (sc->curtxpow != sc->config.txpowlimit) {
151 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
152 /* read back in case value is clamped */
153 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
154 sc->curtxpow = txpow;
158 static u8 parse_mpdudensity(u8 mpdudensity)
161 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
162 * 0 for no restriction
171 switch (mpdudensity) {
177 /* Our lower layer calculations limit our precision to
193 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
195 const struct ath_rate_table *rate_table = NULL;
196 struct ieee80211_supported_band *sband;
197 struct ieee80211_rate *rate;
201 case IEEE80211_BAND_2GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
204 case IEEE80211_BAND_5GHZ:
205 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
211 if (rate_table == NULL)
214 sband = &sc->sbands[band];
215 rate = sc->rates[band];
217 if (rate_table->rate_cnt > ATH_RATE_MAX)
218 maxrates = ATH_RATE_MAX;
220 maxrates = rate_table->rate_cnt;
222 for (i = 0; i < maxrates; i++) {
223 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
224 rate[i].hw_value = rate_table->info[i].ratecode;
225 if (rate_table->info[i].short_preamble) {
226 rate[i].hw_value_short = rate_table->info[i].ratecode |
227 rate_table->info[i].short_preamble;
228 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
232 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
233 "Rate: %2dMbps, ratecode: %2d\n",
234 rate[i].bitrate / 10, rate[i].hw_value);
238 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
239 struct ieee80211_hw *hw)
241 struct ieee80211_channel *curchan = hw->conf.channel;
242 struct ath9k_channel *channel;
245 chan_idx = curchan->hw_value;
246 channel = &sc->sc_ah->channels[chan_idx];
247 ath9k_update_ichannel(sc, hw, channel);
251 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
256 spin_lock_irqsave(&sc->sc_pm_lock, flags);
257 ret = ath9k_hw_setpower(sc->sc_ah, mode);
258 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
263 void ath9k_ps_wakeup(struct ath_softc *sc)
267 spin_lock_irqsave(&sc->sc_pm_lock, flags);
268 if (++sc->ps_usecount != 1)
271 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
274 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
277 void ath9k_ps_restore(struct ath_softc *sc)
281 spin_lock_irqsave(&sc->sc_pm_lock, flags);
282 if (--sc->ps_usecount != 0)
285 if (sc->ps_enabled &&
286 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
288 SC_OP_WAIT_FOR_PSPOLL_DATA |
289 SC_OP_WAIT_FOR_TX_ACK)))
290 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
293 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
297 * Set/change channels. If the channel is really being changed, it's done
298 * by reseting the chip. To accomplish this we must first cleanup any pending
299 * DMA, then restart stuff.
301 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
302 struct ath9k_channel *hchan)
304 struct ath_hw *ah = sc->sc_ah;
305 struct ath_common *common = ath9k_hw_common(ah);
306 struct ieee80211_conf *conf = &common->hw->conf;
307 bool fastcc = true, stopped;
308 struct ieee80211_channel *channel = hw->conf.channel;
311 if (sc->sc_flags & SC_OP_INVALID)
317 * This is only performed if the channel settings have
320 * To switch channels clear any pending DMA operations;
321 * wait long enough for the RX fifo to drain, reset the
322 * hardware at the new frequency, and then re-enable
323 * the relevant bits of the h/w.
325 ath9k_hw_set_interrupts(ah, 0);
326 ath_drain_all_txq(sc, false);
327 stopped = ath_stoprecv(sc);
329 /* XXX: do not flush receive queue here. We don't want
330 * to flush data frames already in queue because of
331 * changing channel. */
333 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
336 ath_print(common, ATH_DBG_CONFIG,
337 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
338 sc->sc_ah->curchan->channel,
339 channel->center_freq, conf_is_ht40(conf));
341 spin_lock_bh(&sc->sc_resetlock);
343 r = ath9k_hw_reset(ah, hchan, fastcc);
345 ath_print(common, ATH_DBG_FATAL,
346 "Unable to reset channel (%u Mhz) "
348 channel->center_freq, r);
349 spin_unlock_bh(&sc->sc_resetlock);
352 spin_unlock_bh(&sc->sc_resetlock);
354 sc->sc_flags &= ~SC_OP_FULL_RESET;
356 if (ath_startrecv(sc) != 0) {
357 ath_print(common, ATH_DBG_FATAL,
358 "Unable to restart recv logic\n");
363 ath_cache_conf_rate(sc, &hw->conf);
364 ath_update_txpow(sc);
365 ath9k_hw_set_interrupts(ah, sc->imask);
368 ath9k_ps_restore(sc);
373 * This routine performs the periodic noise floor calibration function
374 * that is used to adjust and optimize the chip performance. This
375 * takes environmental changes (location, temperature) into account.
376 * When the task is complete, it reschedules itself depending on the
377 * appropriate interval that was calculated.
379 static void ath_ani_calibrate(unsigned long data)
381 struct ath_softc *sc = (struct ath_softc *)data;
382 struct ath_hw *ah = sc->sc_ah;
383 struct ath_common *common = ath9k_hw_common(ah);
384 bool longcal = false;
385 bool shortcal = false;
386 bool aniflag = false;
387 unsigned int timestamp = jiffies_to_msecs(jiffies);
388 u32 cal_interval, short_cal_interval;
390 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
391 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
394 * don't calibrate when we're scanning.
395 * we are most likely not on our home channel.
397 spin_lock(&sc->ani_lock);
398 if (sc->sc_flags & SC_OP_SCANNING)
401 /* Only calibrate if awake */
402 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
407 /* Long calibration runs independently of short calibration. */
408 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
410 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
411 sc->ani.longcal_timer = timestamp;
414 /* Short calibration applies only while caldone is false */
415 if (!sc->ani.caldone) {
416 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
418 ath_print(common, ATH_DBG_ANI,
419 "shortcal @%lu\n", jiffies);
420 sc->ani.shortcal_timer = timestamp;
421 sc->ani.resetcal_timer = timestamp;
424 if ((timestamp - sc->ani.resetcal_timer) >=
425 ATH_RESTART_CALINTERVAL) {
426 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
428 sc->ani.resetcal_timer = timestamp;
432 /* Verify whether we must check ANI */
433 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
435 sc->ani.checkani_timer = timestamp;
438 /* Skip all processing if there's nothing to do. */
439 if (longcal || shortcal || aniflag) {
440 /* Call ANI routine if necessary */
442 ath9k_hw_ani_monitor(ah, ah->curchan);
444 /* Perform calibration if necessary */
445 if (longcal || shortcal) {
447 ath9k_hw_calibrate(ah,
449 common->rx_chainmask,
453 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
456 ath_print(common, ATH_DBG_ANI,
457 " calibrate chan %u/%x nf: %d\n",
458 ah->curchan->channel,
459 ah->curchan->channelFlags,
460 sc->ani.noise_floor);
464 ath9k_ps_restore(sc);
467 spin_unlock(&sc->ani_lock);
469 * Set timer interval based on previous results.
470 * The interval must be the shortest necessary to satisfy ANI,
471 * short calibration and long calibration.
473 cal_interval = ATH_LONG_CALINTERVAL;
474 if (sc->sc_ah->config.enable_ani)
475 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
476 if (!sc->ani.caldone)
477 cal_interval = min(cal_interval, (u32)short_cal_interval);
479 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
482 static void ath_start_ani(struct ath_softc *sc)
484 unsigned long timestamp = jiffies_to_msecs(jiffies);
486 sc->ani.longcal_timer = timestamp;
487 sc->ani.shortcal_timer = timestamp;
488 sc->ani.checkani_timer = timestamp;
490 mod_timer(&sc->ani.timer,
491 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
495 * Update tx/rx chainmask. For legacy association,
496 * hard code chainmask to 1x1, for 11n association, use
497 * the chainmask configuration, for bt coexistence, use
498 * the chainmask configuration even in legacy mode.
500 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
502 struct ath_hw *ah = sc->sc_ah;
503 struct ath_common *common = ath9k_hw_common(ah);
505 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
506 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
507 common->tx_chainmask = ah->caps.tx_chainmask;
508 common->rx_chainmask = ah->caps.rx_chainmask;
510 common->tx_chainmask = 1;
511 common->rx_chainmask = 1;
514 ath_print(common, ATH_DBG_CONFIG,
515 "tx chmask: %d, rx chmask: %d\n",
516 common->tx_chainmask,
517 common->rx_chainmask);
520 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
524 an = (struct ath_node *)sta->drv_priv;
526 if (sc->sc_flags & SC_OP_TXAGGR) {
527 ath_tx_node_init(sc, an);
528 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
529 sta->ht_cap.ampdu_factor);
530 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
531 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
535 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
537 struct ath_node *an = (struct ath_node *)sta->drv_priv;
539 if (sc->sc_flags & SC_OP_TXAGGR)
540 ath_tx_node_cleanup(sc, an);
543 static void ath9k_tasklet(unsigned long data)
545 struct ath_softc *sc = (struct ath_softc *)data;
546 struct ath_hw *ah = sc->sc_ah;
547 struct ath_common *common = ath9k_hw_common(ah);
549 u32 status = sc->intrstatus;
553 if (status & ATH9K_INT_FATAL) {
554 ath_reset(sc, false);
555 ath9k_ps_restore(sc);
559 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
560 spin_lock_bh(&sc->rx.rxflushlock);
561 ath_rx_tasklet(sc, 0);
562 spin_unlock_bh(&sc->rx.rxflushlock);
565 if (status & ATH9K_INT_TX)
568 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
570 * TSF sync does not look correct; remain awake to sync with
573 ath_print(common, ATH_DBG_PS,
574 "TSFOOR - Sync with next Beacon\n");
575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
578 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
579 if (status & ATH9K_INT_GENTIMER)
580 ath_gen_timer_isr(sc->sc_ah);
582 /* re-enable hardware interrupt */
583 ath9k_hw_set_interrupts(ah, sc->imask);
584 ath9k_ps_restore(sc);
587 irqreturn_t ath_isr(int irq, void *dev)
589 #define SCHED_INTR ( \
600 struct ath_softc *sc = dev;
601 struct ath_hw *ah = sc->sc_ah;
602 enum ath9k_int status;
606 * The hardware is not ready/present, don't
607 * touch anything. Note this can happen early
608 * on if the IRQ is shared.
610 if (sc->sc_flags & SC_OP_INVALID)
614 /* shared irq, not for us */
616 if (!ath9k_hw_intrpend(ah))
620 * Figure out the reason(s) for the interrupt. Note
621 * that the hal returns a pseudo-ISR that may include
622 * bits we haven't explicitly enabled so we mask the
623 * value to insure we only process bits we requested.
625 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
626 status &= sc->imask; /* discard unasked-for bits */
629 * If there are no status bits set, then this interrupt was not
630 * for me (should have been caught above).
635 /* Cache the status */
636 sc->intrstatus = status;
638 if (status & SCHED_INTR)
642 * If a FATAL or RXORN interrupt is received, we have to reset the
645 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
648 if (status & ATH9K_INT_SWBA)
649 tasklet_schedule(&sc->bcon_tasklet);
651 if (status & ATH9K_INT_TXURN)
652 ath9k_hw_updatetxtriglevel(ah, true);
654 if (status & ATH9K_INT_MIB) {
656 * Disable interrupts until we service the MIB
657 * interrupt; otherwise it will continue to
660 ath9k_hw_set_interrupts(ah, 0);
662 * Let the hal handle the event. We assume
663 * it will clear whatever condition caused
666 ath9k_hw_procmibevent(ah);
667 ath9k_hw_set_interrupts(ah, sc->imask);
670 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
671 if (status & ATH9K_INT_TIM_TIMER) {
672 /* Clear RxAbort bit so that we can
674 ath9k_setpower(sc, ATH9K_PM_AWAKE);
675 ath9k_hw_setrxabort(sc->sc_ah, 0);
676 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
681 ath_debug_stat_interrupt(sc, status);
684 /* turn off every interrupt except SWBA */
685 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
686 tasklet_schedule(&sc->intr_tq);
694 static u32 ath_get_extchanmode(struct ath_softc *sc,
695 struct ieee80211_channel *chan,
696 enum nl80211_channel_type channel_type)
700 switch (chan->band) {
701 case IEEE80211_BAND_2GHZ:
702 switch(channel_type) {
703 case NL80211_CHAN_NO_HT:
704 case NL80211_CHAN_HT20:
705 chanmode = CHANNEL_G_HT20;
707 case NL80211_CHAN_HT40PLUS:
708 chanmode = CHANNEL_G_HT40PLUS;
710 case NL80211_CHAN_HT40MINUS:
711 chanmode = CHANNEL_G_HT40MINUS;
715 case IEEE80211_BAND_5GHZ:
716 switch(channel_type) {
717 case NL80211_CHAN_NO_HT:
718 case NL80211_CHAN_HT20:
719 chanmode = CHANNEL_A_HT20;
721 case NL80211_CHAN_HT40PLUS:
722 chanmode = CHANNEL_A_HT40PLUS;
724 case NL80211_CHAN_HT40MINUS:
725 chanmode = CHANNEL_A_HT40MINUS;
736 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
737 struct ath9k_keyval *hk, const u8 *addr,
743 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
744 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
748 * Group key installation - only two key cache entries are used
749 * regardless of splitmic capability since group key is only
750 * used either for TX or RX.
753 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
754 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
756 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
757 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
759 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
762 /* TX and RX keys share the same key cache entry. */
763 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
764 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
765 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
768 /* Separate key cache entries for TX and RX */
770 /* TX key goes at first index, RX key at +32. */
771 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
772 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
773 /* TX MIC entry failed. No need to proceed further */
774 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
775 "Setting TX MIC Key Failed\n");
779 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
780 /* XXX delete tx key on failure? */
781 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
784 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
788 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
789 if (test_bit(i, sc->keymap) ||
790 test_bit(i + 64, sc->keymap))
791 continue; /* At least one part of TKIP key allocated */
793 (test_bit(i + 32, sc->keymap) ||
794 test_bit(i + 64 + 32, sc->keymap)))
795 continue; /* At least one part of TKIP key allocated */
797 /* Found a free slot for a TKIP key */
803 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
807 /* First, try to find slots that would not be available for TKIP. */
809 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
810 if (!test_bit(i, sc->keymap) &&
811 (test_bit(i + 32, sc->keymap) ||
812 test_bit(i + 64, sc->keymap) ||
813 test_bit(i + 64 + 32, sc->keymap)))
815 if (!test_bit(i + 32, sc->keymap) &&
816 (test_bit(i, sc->keymap) ||
817 test_bit(i + 64, sc->keymap) ||
818 test_bit(i + 64 + 32, sc->keymap)))
820 if (!test_bit(i + 64, sc->keymap) &&
821 (test_bit(i , sc->keymap) ||
822 test_bit(i + 32, sc->keymap) ||
823 test_bit(i + 64 + 32, sc->keymap)))
825 if (!test_bit(i + 64 + 32, sc->keymap) &&
826 (test_bit(i, sc->keymap) ||
827 test_bit(i + 32, sc->keymap) ||
828 test_bit(i + 64, sc->keymap)))
832 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
833 if (!test_bit(i, sc->keymap) &&
834 test_bit(i + 64, sc->keymap))
836 if (test_bit(i, sc->keymap) &&
837 !test_bit(i + 64, sc->keymap))
842 /* No partially used TKIP slots, pick any available slot */
843 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
844 /* Do not allow slots that could be needed for TKIP group keys
845 * to be used. This limitation could be removed if we know that
846 * TKIP will not be used. */
847 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
850 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
852 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
856 if (!test_bit(i, sc->keymap))
857 return i; /* Found a free slot for a key */
860 /* No free slot found */
864 static int ath_key_config(struct ath_softc *sc,
865 struct ieee80211_vif *vif,
866 struct ieee80211_sta *sta,
867 struct ieee80211_key_conf *key)
869 struct ath9k_keyval hk;
870 const u8 *mac = NULL;
874 memset(&hk, 0, sizeof(hk));
878 hk.kv_type = ATH9K_CIPHER_WEP;
881 hk.kv_type = ATH9K_CIPHER_TKIP;
884 hk.kv_type = ATH9K_CIPHER_AES_CCM;
890 hk.kv_len = key->keylen;
891 memcpy(hk.kv_val, key->key, key->keylen);
893 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
894 /* For now, use the default keys for broadcast keys. This may
895 * need to change with virtual interfaces. */
897 } else if (key->keyidx) {
902 if (vif->type != NL80211_IFTYPE_AP) {
903 /* Only keyidx 0 should be used with unicast key, but
904 * allow this for client mode for now. */
913 if (key->alg == ALG_TKIP)
914 idx = ath_reserve_key_cache_slot_tkip(sc);
916 idx = ath_reserve_key_cache_slot(sc);
918 return -ENOSPC; /* no free key cache entries */
921 if (key->alg == ALG_TKIP)
922 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
923 vif->type == NL80211_IFTYPE_AP);
925 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
930 set_bit(idx, sc->keymap);
931 if (key->alg == ALG_TKIP) {
932 set_bit(idx + 64, sc->keymap);
934 set_bit(idx + 32, sc->keymap);
935 set_bit(idx + 64 + 32, sc->keymap);
942 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
944 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
945 if (key->hw_key_idx < IEEE80211_WEP_NKID)
948 clear_bit(key->hw_key_idx, sc->keymap);
949 if (key->alg != ALG_TKIP)
952 clear_bit(key->hw_key_idx + 64, sc->keymap);
954 clear_bit(key->hw_key_idx + 32, sc->keymap);
955 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
959 static void setup_ht_cap(struct ath_softc *sc,
960 struct ieee80211_sta_ht_cap *ht_info)
962 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
963 u8 tx_streams, rx_streams;
965 ht_info->ht_supported = true;
966 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
967 IEEE80211_HT_CAP_SM_PS |
968 IEEE80211_HT_CAP_SGI_40 |
969 IEEE80211_HT_CAP_DSSSCCK40;
971 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
972 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
974 /* set up supported mcs set */
975 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
976 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
978 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
981 if (tx_streams != rx_streams) {
982 ath_print(common, ATH_DBG_CONFIG,
983 "TX streams %d, RX streams: %d\n",
984 tx_streams, rx_streams);
985 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
986 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
987 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
990 ht_info->mcs.rx_mask[0] = 0xff;
992 ht_info->mcs.rx_mask[1] = 0xff;
994 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
997 static void ath9k_bss_assoc_info(struct ath_softc *sc,
998 struct ieee80211_vif *vif,
999 struct ieee80211_bss_conf *bss_conf)
1001 struct ath_hw *ah = sc->sc_ah;
1002 struct ath_common *common = ath9k_hw_common(ah);
1004 if (bss_conf->assoc) {
1005 ath_print(common, ATH_DBG_CONFIG,
1006 "Bss Info ASSOC %d, bssid: %pM\n",
1007 bss_conf->aid, common->curbssid);
1009 /* New association, store aid */
1010 common->curaid = bss_conf->aid;
1011 ath9k_hw_write_associd(ah);
1014 * Request a re-configuration of Beacon related timers
1015 * on the receipt of the first Beacon frame (i.e.,
1016 * after time sync with the AP).
1018 sc->sc_flags |= SC_OP_BEACON_SYNC;
1020 /* Configure the beacon */
1021 ath_beacon_config(sc, vif);
1023 /* Reset rssi stats */
1024 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1028 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1031 del_timer_sync(&sc->ani.timer);
1035 /********************************/
1037 /********************************/
1039 static void ath_led_blink_work(struct work_struct *work)
1041 struct ath_softc *sc = container_of(work, struct ath_softc,
1042 ath_led_blink_work.work);
1044 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1047 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1048 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1049 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1051 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1052 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1054 ieee80211_queue_delayed_work(sc->hw,
1055 &sc->ath_led_blink_work,
1056 (sc->sc_flags & SC_OP_LED_ON) ?
1057 msecs_to_jiffies(sc->led_off_duration) :
1058 msecs_to_jiffies(sc->led_on_duration));
1060 sc->led_on_duration = sc->led_on_cnt ?
1061 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1062 ATH_LED_ON_DURATION_IDLE;
1063 sc->led_off_duration = sc->led_off_cnt ?
1064 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1065 ATH_LED_OFF_DURATION_IDLE;
1066 sc->led_on_cnt = sc->led_off_cnt = 0;
1067 if (sc->sc_flags & SC_OP_LED_ON)
1068 sc->sc_flags &= ~SC_OP_LED_ON;
1070 sc->sc_flags |= SC_OP_LED_ON;
1073 static void ath_led_brightness(struct led_classdev *led_cdev,
1074 enum led_brightness brightness)
1076 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1077 struct ath_softc *sc = led->sc;
1079 switch (brightness) {
1081 if (led->led_type == ATH_LED_ASSOC ||
1082 led->led_type == ATH_LED_RADIO) {
1083 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1084 (led->led_type == ATH_LED_RADIO));
1085 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1086 if (led->led_type == ATH_LED_RADIO)
1087 sc->sc_flags &= ~SC_OP_LED_ON;
1093 if (led->led_type == ATH_LED_ASSOC) {
1094 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1095 ieee80211_queue_delayed_work(sc->hw,
1096 &sc->ath_led_blink_work, 0);
1097 } else if (led->led_type == ATH_LED_RADIO) {
1098 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1099 sc->sc_flags |= SC_OP_LED_ON;
1109 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1115 led->led_cdev.name = led->name;
1116 led->led_cdev.default_trigger = trigger;
1117 led->led_cdev.brightness_set = ath_led_brightness;
1119 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1121 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1122 "Failed to register led:%s", led->name);
1124 led->registered = 1;
1128 static void ath_unregister_led(struct ath_led *led)
1130 if (led->registered) {
1131 led_classdev_unregister(&led->led_cdev);
1132 led->registered = 0;
1136 static void ath_deinit_leds(struct ath_softc *sc)
1138 ath_unregister_led(&sc->assoc_led);
1139 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1140 ath_unregister_led(&sc->tx_led);
1141 ath_unregister_led(&sc->rx_led);
1142 ath_unregister_led(&sc->radio_led);
1143 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1146 static void ath_init_leds(struct ath_softc *sc)
1151 if (AR_SREV_9287(sc->sc_ah))
1152 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1154 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1156 /* Configure gpio 1 for output */
1157 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1158 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1159 /* LED off, active low */
1160 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1162 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1164 trigger = ieee80211_get_radio_led_name(sc->hw);
1165 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1166 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1167 ret = ath_register_led(sc, &sc->radio_led, trigger);
1168 sc->radio_led.led_type = ATH_LED_RADIO;
1172 trigger = ieee80211_get_assoc_led_name(sc->hw);
1173 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1174 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1175 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1176 sc->assoc_led.led_type = ATH_LED_ASSOC;
1180 trigger = ieee80211_get_tx_led_name(sc->hw);
1181 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1182 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1183 ret = ath_register_led(sc, &sc->tx_led, trigger);
1184 sc->tx_led.led_type = ATH_LED_TX;
1188 trigger = ieee80211_get_rx_led_name(sc->hw);
1189 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1190 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1191 ret = ath_register_led(sc, &sc->rx_led, trigger);
1192 sc->rx_led.led_type = ATH_LED_RX;
1199 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1200 ath_deinit_leds(sc);
1203 void ath_radio_enable(struct ath_softc *sc)
1205 struct ath_hw *ah = sc->sc_ah;
1206 struct ath_common *common = ath9k_hw_common(ah);
1207 struct ieee80211_channel *channel = sc->hw->conf.channel;
1210 ath9k_ps_wakeup(sc);
1211 ath9k_hw_configpcipowersave(ah, 0, 0);
1214 ah->curchan = ath_get_curchannel(sc, sc->hw);
1216 spin_lock_bh(&sc->sc_resetlock);
1217 r = ath9k_hw_reset(ah, ah->curchan, false);
1219 ath_print(common, ATH_DBG_FATAL,
1220 "Unable to reset channel %u (%uMhz) ",
1221 "reset status %d\n",
1222 channel->center_freq, r);
1224 spin_unlock_bh(&sc->sc_resetlock);
1226 ath_update_txpow(sc);
1227 if (ath_startrecv(sc) != 0) {
1228 ath_print(common, ATH_DBG_FATAL,
1229 "Unable to restart recv logic\n");
1233 if (sc->sc_flags & SC_OP_BEACONS)
1234 ath_beacon_config(sc, NULL); /* restart beacons */
1236 /* Re-Enable interrupts */
1237 ath9k_hw_set_interrupts(ah, sc->imask);
1240 ath9k_hw_cfg_output(ah, ah->led_pin,
1241 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1242 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1244 ieee80211_wake_queues(sc->hw);
1245 ath9k_ps_restore(sc);
1248 void ath_radio_disable(struct ath_softc *sc)
1250 struct ath_hw *ah = sc->sc_ah;
1251 struct ieee80211_channel *channel = sc->hw->conf.channel;
1254 ath9k_ps_wakeup(sc);
1255 ieee80211_stop_queues(sc->hw);
1258 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1259 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1261 /* Disable interrupts */
1262 ath9k_hw_set_interrupts(ah, 0);
1264 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1265 ath_stoprecv(sc); /* turn off frame recv */
1266 ath_flushrecv(sc); /* flush recv queue */
1269 ah->curchan = ath_get_curchannel(sc, sc->hw);
1271 spin_lock_bh(&sc->sc_resetlock);
1272 r = ath9k_hw_reset(ah, ah->curchan, false);
1274 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1275 "Unable to reset channel %u (%uMhz) "
1276 "reset status %d\n",
1277 channel->center_freq, r);
1279 spin_unlock_bh(&sc->sc_resetlock);
1281 ath9k_hw_phy_disable(ah);
1282 ath9k_hw_configpcipowersave(ah, 1, 1);
1283 ath9k_ps_restore(sc);
1284 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1287 /*******************/
1289 /*******************/
1291 static bool ath_is_rfkill_set(struct ath_softc *sc)
1293 struct ath_hw *ah = sc->sc_ah;
1295 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1296 ah->rfkill_polarity;
1299 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1301 struct ath_wiphy *aphy = hw->priv;
1302 struct ath_softc *sc = aphy->sc;
1303 bool blocked = !!ath_is_rfkill_set(sc);
1305 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1308 static void ath_start_rfkill_poll(struct ath_softc *sc)
1310 struct ath_hw *ah = sc->sc_ah;
1312 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1313 wiphy_rfkill_start_polling(sc->hw->wiphy);
1316 void ath_cleanup(struct ath_softc *sc)
1318 struct ath_hw *ah = sc->sc_ah;
1319 struct ath_common *common = ath9k_hw_common(ah);
1322 free_irq(sc->irq, sc);
1323 ath_bus_cleanup(common);
1324 kfree(sc->sec_wiphy);
1325 ieee80211_free_hw(sc->hw);
1328 void ath_detach(struct ath_softc *sc)
1330 struct ieee80211_hw *hw = sc->hw;
1331 struct ath_hw *ah = sc->sc_ah;
1334 ath9k_ps_wakeup(sc);
1336 dev_dbg(sc->dev, "Detach ATH hw\n");
1338 ath_deinit_leds(sc);
1339 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1341 for (i = 0; i < sc->num_sec_wiphy; i++) {
1342 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1345 sc->sec_wiphy[i] = NULL;
1346 ieee80211_unregister_hw(aphy->hw);
1347 ieee80211_free_hw(aphy->hw);
1349 ieee80211_unregister_hw(hw);
1353 tasklet_kill(&sc->intr_tq);
1354 tasklet_kill(&sc->bcon_tasklet);
1356 if (!(sc->sc_flags & SC_OP_INVALID))
1357 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1359 /* cleanup tx queues */
1360 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1361 if (ATH_TXQ_SETUP(sc, i))
1362 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1364 if ((sc->btcoex.no_stomp_timer) &&
1365 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1366 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1368 ath9k_exit_debug(ah);
1369 ath9k_hw_detach(ah);
1373 static int ath9k_reg_notifier(struct wiphy *wiphy,
1374 struct regulatory_request *request)
1376 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1377 struct ath_wiphy *aphy = hw->priv;
1378 struct ath_softc *sc = aphy->sc;
1379 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1381 return ath_reg_notifier_apply(wiphy, request, reg);
1385 * Detects if there is any priority bt traffic
1387 static void ath_detect_bt_priority(struct ath_softc *sc)
1389 struct ath_btcoex *btcoex = &sc->btcoex;
1390 struct ath_hw *ah = sc->sc_ah;
1392 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1393 btcoex->bt_priority_cnt++;
1395 if (time_after(jiffies, btcoex->bt_priority_time +
1396 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1397 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1398 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1399 "BT priority traffic detected");
1400 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1402 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1405 btcoex->bt_priority_cnt = 0;
1406 btcoex->bt_priority_time = jiffies;
1411 * Configures appropriate weight based on stomp type.
1413 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1414 enum ath_stomp_type stomp_type)
1416 struct ath_hw *ah = sc->sc_ah;
1418 switch (stomp_type) {
1419 case ATH_BTCOEX_STOMP_ALL:
1420 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1421 AR_STOMP_ALL_WLAN_WGHT);
1423 case ATH_BTCOEX_STOMP_LOW:
1424 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1425 AR_STOMP_LOW_WLAN_WGHT);
1427 case ATH_BTCOEX_STOMP_NONE:
1428 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1429 AR_STOMP_NONE_WLAN_WGHT);
1432 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1433 "Invalid Stomptype\n");
1437 ath9k_hw_btcoex_enable(ah);
1440 static void ath9k_gen_timer_start(struct ath_hw *ah,
1441 struct ath_gen_timer *timer,
1445 struct ath_common *common = ath9k_hw_common(ah);
1446 struct ath_softc *sc = (struct ath_softc *) common->priv;
1448 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1450 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
1451 ath9k_hw_set_interrupts(ah, 0);
1452 sc->imask |= ATH9K_INT_GENTIMER;
1453 ath9k_hw_set_interrupts(ah, sc->imask);
1457 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1459 struct ath_common *common = ath9k_hw_common(ah);
1460 struct ath_softc *sc = (struct ath_softc *) common->priv;
1461 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1463 ath9k_hw_gen_timer_stop(ah, timer);
1465 /* if no timer is enabled, turn off interrupt mask */
1466 if (timer_table->timer_mask.val == 0) {
1467 ath9k_hw_set_interrupts(ah, 0);
1468 sc->imask &= ~ATH9K_INT_GENTIMER;
1469 ath9k_hw_set_interrupts(ah, sc->imask);
1474 * This is the master bt coex timer which runs for every
1475 * 45ms, bt traffic will be given priority during 55% of this
1476 * period while wlan gets remaining 45%
1478 static void ath_btcoex_period_timer(unsigned long data)
1480 struct ath_softc *sc = (struct ath_softc *) data;
1481 struct ath_hw *ah = sc->sc_ah;
1482 struct ath_btcoex *btcoex = &sc->btcoex;
1484 ath_detect_bt_priority(sc);
1486 spin_lock_bh(&btcoex->btcoex_lock);
1488 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1490 spin_unlock_bh(&btcoex->btcoex_lock);
1492 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1493 if (btcoex->hw_timer_enabled)
1494 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1496 ath9k_gen_timer_start(ah,
1497 btcoex->no_stomp_timer,
1498 (ath9k_hw_gettsf32(ah) +
1499 btcoex->btcoex_no_stomp),
1500 btcoex->btcoex_no_stomp * 10);
1501 btcoex->hw_timer_enabled = true;
1504 mod_timer(&btcoex->period_timer, jiffies +
1505 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1509 * Generic tsf based hw timer which configures weight
1510 * registers to time slice between wlan and bt traffic
1512 static void ath_btcoex_no_stomp_timer(void *arg)
1514 struct ath_softc *sc = (struct ath_softc *)arg;
1515 struct ath_hw *ah = sc->sc_ah;
1516 struct ath_btcoex *btcoex = &sc->btcoex;
1518 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1519 "no stomp timer running \n");
1521 spin_lock_bh(&btcoex->btcoex_lock);
1523 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1524 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1525 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1526 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1528 spin_unlock_bh(&btcoex->btcoex_lock);
1531 static int ath_init_btcoex_timer(struct ath_softc *sc)
1533 struct ath_btcoex *btcoex = &sc->btcoex;
1535 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1536 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1537 btcoex->btcoex_period / 100;
1539 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1540 (unsigned long) sc);
1542 spin_lock_init(&btcoex->btcoex_lock);
1544 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1545 ath_btcoex_no_stomp_timer,
1546 ath_btcoex_no_stomp_timer,
1547 (void *) sc, AR_FIRST_NDP_TIMER);
1549 if (!btcoex->no_stomp_timer)
1556 * Read and write, they both share the same lock. We do this to serialize
1557 * reads and writes on Atheros 802.11n PCI devices only. This is required
1558 * as the FIFO on these devices can only accept sanely 2 requests. After
1559 * that the device goes bananas. Serializing the reads/writes prevents this
1563 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1565 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1566 struct ath_common *common = ath9k_hw_common(ah);
1567 struct ath_softc *sc = (struct ath_softc *) common->priv;
1569 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1570 unsigned long flags;
1571 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1572 iowrite32(val, sc->mem + reg_offset);
1573 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1575 iowrite32(val, sc->mem + reg_offset);
1578 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1580 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1581 struct ath_common *common = ath9k_hw_common(ah);
1582 struct ath_softc *sc = (struct ath_softc *) common->priv;
1585 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1586 unsigned long flags;
1587 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1588 val = ioread32(sc->mem + reg_offset);
1589 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1591 val = ioread32(sc->mem + reg_offset);
1595 static const struct ath_ops ath9k_common_ops = {
1596 .read = ath9k_ioread32,
1597 .write = ath9k_iowrite32,
1601 * Initialize and fill ath_softc, ath_sofct is the
1602 * "Software Carrier" struct. Historically it has existed
1603 * to allow the separation between hardware specific
1604 * variables (now in ath_hw) and driver specific variables.
1606 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1607 const struct ath_bus_ops *bus_ops)
1609 struct ath_hw *ah = NULL;
1610 struct ath_common *common;
1615 /* XXX: hardware will not be ready until ath_open() being called */
1616 sc->sc_flags |= SC_OP_INVALID;
1618 spin_lock_init(&sc->wiphy_lock);
1619 spin_lock_init(&sc->sc_resetlock);
1620 spin_lock_init(&sc->sc_serial_rw);
1621 spin_lock_init(&sc->ani_lock);
1622 spin_lock_init(&sc->sc_pm_lock);
1623 mutex_init(&sc->mutex);
1624 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1625 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1628 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1632 ah->hw_version.devid = devid;
1633 ah->hw_version.subsysid = subsysid;
1636 common = ath9k_hw_common(ah);
1637 common->ops = &ath9k_common_ops;
1638 common->bus_ops = bus_ops;
1640 common->hw = sc->hw;
1642 common->debug_mask = ath9k_debug;
1645 * Cache line size is used to size and align various
1646 * structures used to communicate with the hardware.
1648 ath_read_cachesize(common, &csz);
1649 /* XXX assert csz is non-zero */
1650 common->cachelsz = csz << 2; /* convert to bytes */
1652 r = ath9k_hw_init(ah);
1654 ath_print(common, ATH_DBG_FATAL,
1655 "Unable to initialize hardware; "
1656 "initialization status: %d\n", r);
1660 if (ath9k_init_debug(ah) < 0) {
1661 ath_print(common, ATH_DBG_FATAL,
1662 "Unable to create debugfs files\n");
1666 /* Get the hardware key cache size. */
1667 sc->keymax = ah->caps.keycache_size;
1668 if (sc->keymax > ATH_KEYMAX) {
1669 ath_print(common, ATH_DBG_ANY,
1670 "Warning, using only %u entries in %u key cache\n",
1671 ATH_KEYMAX, sc->keymax);
1672 sc->keymax = ATH_KEYMAX;
1676 * Reset the key cache since some parts do not
1677 * reset the contents on initial power up.
1679 for (i = 0; i < sc->keymax; i++)
1680 ath9k_hw_keyreset(ah, (u16) i);
1682 /* default to MONITOR mode */
1683 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1685 /* Setup rate tables */
1687 ath_rate_attach(sc);
1688 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1689 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1692 * Allocate hardware transmit queues: one queue for
1693 * beacon frames and one data queue for each QoS
1694 * priority. Note that the hal handles reseting
1695 * these queues at the needed time.
1697 sc->beacon.beaconq = ath_beaconq_setup(ah);
1698 if (sc->beacon.beaconq == -1) {
1699 ath_print(common, ATH_DBG_FATAL,
1700 "Unable to setup a beacon xmit queue\n");
1704 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1705 if (sc->beacon.cabq == NULL) {
1706 ath_print(common, ATH_DBG_FATAL,
1707 "Unable to setup CAB xmit queue\n");
1712 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1713 ath_cabq_update(sc);
1715 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1716 sc->tx.hwq_map[i] = -1;
1718 /* Setup data queues */
1719 /* NB: ensure BK queue is the lowest priority h/w queue */
1720 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1721 ath_print(common, ATH_DBG_FATAL,
1722 "Unable to setup xmit queue for BK traffic\n");
1727 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1728 ath_print(common, ATH_DBG_FATAL,
1729 "Unable to setup xmit queue for BE traffic\n");
1733 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1734 ath_print(common, ATH_DBG_FATAL,
1735 "Unable to setup xmit queue for VI traffic\n");
1739 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1740 ath_print(common, ATH_DBG_FATAL,
1741 "Unable to setup xmit queue for VO traffic\n");
1746 /* Initializes the noise floor to a reasonable default value.
1747 * Later on this will be updated during ANI processing. */
1749 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1750 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1752 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1753 ATH9K_CIPHER_TKIP, NULL)) {
1755 * Whether we should enable h/w TKIP MIC.
1756 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1757 * report WMM capable, so it's always safe to turn on
1758 * TKIP MIC in this case.
1760 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1765 * Check whether the separate key cache entries
1766 * are required to handle both tx+rx MIC keys.
1767 * With split mic keys the number of stations is limited
1768 * to 27 otherwise 59.
1770 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1771 ATH9K_CIPHER_TKIP, NULL)
1772 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1773 ATH9K_CIPHER_MIC, NULL)
1774 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1778 /* turn on mcast key search if possible */
1779 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1780 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1783 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1785 /* 11n Capabilities */
1786 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1787 sc->sc_flags |= SC_OP_TXAGGR;
1788 sc->sc_flags |= SC_OP_RXAGGR;
1791 common->tx_chainmask = ah->caps.tx_chainmask;
1792 common->rx_chainmask = ah->caps.rx_chainmask;
1794 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1795 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1797 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1798 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1800 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1802 /* initialize beacon slots */
1803 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1804 sc->beacon.bslot[i] = NULL;
1805 sc->beacon.bslot_aphy[i] = NULL;
1808 /* setup channels and rates */
1810 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1811 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1812 sc->rates[IEEE80211_BAND_2GHZ];
1813 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1814 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1815 ARRAY_SIZE(ath9k_2ghz_chantable);
1817 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1818 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1819 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1820 sc->rates[IEEE80211_BAND_5GHZ];
1821 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1822 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1823 ARRAY_SIZE(ath9k_5ghz_chantable);
1826 switch (ah->btcoex_hw.scheme) {
1827 case ATH_BTCOEX_CFG_NONE:
1829 case ATH_BTCOEX_CFG_2WIRE:
1830 ath9k_hw_btcoex_init_2wire(ah);
1832 case ATH_BTCOEX_CFG_3WIRE:
1833 ath9k_hw_btcoex_init_3wire(ah);
1834 r = ath_init_btcoex_timer(sc);
1837 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1838 ath9k_hw_init_btcoex_hw(ah, qnum);
1839 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1848 /* cleanup tx queues */
1849 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1850 if (ATH_TXQ_SETUP(sc, i))
1851 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1853 ath9k_exit_debug(ah);
1855 ath9k_hw_detach(ah);
1860 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1862 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1863 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1864 IEEE80211_HW_SIGNAL_DBM |
1865 IEEE80211_HW_AMPDU_AGGREGATION |
1866 IEEE80211_HW_SUPPORTS_PS |
1867 IEEE80211_HW_PS_NULLFUNC_STACK |
1868 IEEE80211_HW_SPECTRUM_MGMT;
1870 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1871 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1873 hw->wiphy->interface_modes =
1874 BIT(NL80211_IFTYPE_AP) |
1875 BIT(NL80211_IFTYPE_STATION) |
1876 BIT(NL80211_IFTYPE_ADHOC) |
1877 BIT(NL80211_IFTYPE_MESH_POINT);
1881 hw->channel_change_time = 5000;
1882 hw->max_listen_interval = 10;
1883 /* Hardware supports 10 but we use 4 */
1884 hw->max_rate_tries = 4;
1885 hw->sta_data_size = sizeof(struct ath_node);
1886 hw->vif_data_size = sizeof(struct ath_vif);
1888 hw->rate_control_algorithm = "ath9k_rate_control";
1890 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1891 &sc->sbands[IEEE80211_BAND_2GHZ];
1892 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1893 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1894 &sc->sbands[IEEE80211_BAND_5GHZ];
1897 /* Device driver core initialization */
1898 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1899 const struct ath_bus_ops *bus_ops)
1901 struct ieee80211_hw *hw = sc->hw;
1902 struct ath_common *common;
1905 struct ath_regulatory *reg;
1907 dev_dbg(sc->dev, "Attach ATH hw\n");
1909 error = ath_init_softc(devid, sc, subsysid, bus_ops);
1914 common = ath9k_hw_common(ah);
1916 /* get mac address from hardware and set in mac80211 */
1918 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1920 ath_set_hw_capab(sc, hw);
1922 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1923 ath9k_reg_notifier);
1927 reg = &common->regulatory;
1929 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1930 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1931 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1932 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1935 /* initialize tx/rx engine */
1936 error = ath_tx_init(sc, ATH_TXBUF);
1940 error = ath_rx_init(sc, ATH_RXBUF);
1944 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1945 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1946 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1948 error = ieee80211_register_hw(hw);
1950 if (!ath_is_world_regd(reg)) {
1951 error = regulatory_hint(hw->wiphy, reg->alpha2);
1956 /* Initialize LED control */
1959 ath_start_rfkill_poll(sc);
1964 /* cleanup tx queues */
1965 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1966 if (ATH_TXQ_SETUP(sc, i))
1967 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1969 ath9k_exit_debug(ah);
1970 ath9k_hw_detach(ah);
1976 int ath_reset(struct ath_softc *sc, bool retry_tx)
1978 struct ath_hw *ah = sc->sc_ah;
1979 struct ath_common *common = ath9k_hw_common(ah);
1980 struct ieee80211_hw *hw = sc->hw;
1983 ath9k_hw_set_interrupts(ah, 0);
1984 ath_drain_all_txq(sc, retry_tx);
1988 spin_lock_bh(&sc->sc_resetlock);
1989 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1991 ath_print(common, ATH_DBG_FATAL,
1992 "Unable to reset hardware; reset status %d\n", r);
1993 spin_unlock_bh(&sc->sc_resetlock);
1995 if (ath_startrecv(sc) != 0)
1996 ath_print(common, ATH_DBG_FATAL,
1997 "Unable to start recv logic\n");
2000 * We may be doing a reset in response to a request
2001 * that changes the channel so update any state that
2002 * might change as a result.
2004 ath_cache_conf_rate(sc, &hw->conf);
2006 ath_update_txpow(sc);
2008 if (sc->sc_flags & SC_OP_BEACONS)
2009 ath_beacon_config(sc, NULL); /* restart beacons */
2011 ath9k_hw_set_interrupts(ah, sc->imask);
2015 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2016 if (ATH_TXQ_SETUP(sc, i)) {
2017 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2018 ath_txq_schedule(sc, &sc->tx.txq[i]);
2019 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
2028 * This function will allocate both the DMA descriptor structure, and the
2029 * buffers it contains. These are used to contain the descriptors used
2032 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2033 struct list_head *head, const char *name,
2034 int nbuf, int ndesc)
2036 #define DS2PHYS(_dd, _ds) \
2037 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2038 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2039 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2040 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2041 struct ath_desc *ds;
2043 int i, bsize, error;
2045 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2048 INIT_LIST_HEAD(head);
2049 /* ath_desc must be a multiple of DWORDs */
2050 if ((sizeof(struct ath_desc) % 4) != 0) {
2051 ath_print(common, ATH_DBG_FATAL,
2052 "ath_desc not DWORD aligned\n");
2053 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
2058 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2061 * Need additional DMA memory because we can't use
2062 * descriptors that cross the 4K page boundary. Assume
2063 * one skipped descriptor per 4K page.
2065 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2067 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2070 while (ndesc_skipped) {
2071 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2072 dd->dd_desc_len += dma_len;
2074 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2078 /* allocate descriptors */
2079 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2080 &dd->dd_desc_paddr, GFP_KERNEL);
2081 if (dd->dd_desc == NULL) {
2086 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2087 name, ds, (u32) dd->dd_desc_len,
2088 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2090 /* allocate buffers */
2091 bsize = sizeof(struct ath_buf) * nbuf;
2092 bf = kzalloc(bsize, GFP_KERNEL);
2099 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2101 bf->bf_daddr = DS2PHYS(dd, ds);
2103 if (!(sc->sc_ah->caps.hw_caps &
2104 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2106 * Skip descriptor addresses which can cause 4KB
2107 * boundary crossing (addr + length) with a 32 dword
2110 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2111 BUG_ON((caddr_t) bf->bf_desc >=
2112 ((caddr_t) dd->dd_desc +
2117 bf->bf_daddr = DS2PHYS(dd, ds);
2120 list_add_tail(&bf->list, head);
2124 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2127 memset(dd, 0, sizeof(*dd));
2129 #undef ATH_DESC_4KB_BOUND_CHECK
2130 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2134 void ath_descdma_cleanup(struct ath_softc *sc,
2135 struct ath_descdma *dd,
2136 struct list_head *head)
2138 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2141 INIT_LIST_HEAD(head);
2142 kfree(dd->dd_bufptr);
2143 memset(dd, 0, sizeof(*dd));
2146 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2152 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2155 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2158 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2161 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2164 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2171 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2176 case ATH9K_WME_AC_VO:
2179 case ATH9K_WME_AC_VI:
2182 case ATH9K_WME_AC_BE:
2185 case ATH9K_WME_AC_BK:
2196 /* XXX: Remove me once we don't depend on ath9k_channel for all
2197 * this redundant data */
2198 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2199 struct ath9k_channel *ichan)
2201 struct ieee80211_channel *chan = hw->conf.channel;
2202 struct ieee80211_conf *conf = &hw->conf;
2204 ichan->channel = chan->center_freq;
2207 if (chan->band == IEEE80211_BAND_2GHZ) {
2208 ichan->chanmode = CHANNEL_G;
2209 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2211 ichan->chanmode = CHANNEL_A;
2212 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2215 if (conf_is_ht(conf))
2216 ichan->chanmode = ath_get_extchanmode(sc, chan,
2217 conf->channel_type);
2220 /**********************/
2221 /* mac80211 callbacks */
2222 /**********************/
2225 * (Re)start btcoex timers
2227 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2229 struct ath_btcoex *btcoex = &sc->btcoex;
2230 struct ath_hw *ah = sc->sc_ah;
2232 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2233 "Starting btcoex timers");
2235 /* make sure duty cycle timer is also stopped when resuming */
2236 if (btcoex->hw_timer_enabled)
2237 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2239 btcoex->bt_priority_cnt = 0;
2240 btcoex->bt_priority_time = jiffies;
2241 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2243 mod_timer(&btcoex->period_timer, jiffies);
2246 static int ath9k_start(struct ieee80211_hw *hw)
2248 struct ath_wiphy *aphy = hw->priv;
2249 struct ath_softc *sc = aphy->sc;
2250 struct ath_hw *ah = sc->sc_ah;
2251 struct ath_common *common = ath9k_hw_common(ah);
2252 struct ieee80211_channel *curchan = hw->conf.channel;
2253 struct ath9k_channel *init_channel;
2256 ath_print(common, ATH_DBG_CONFIG,
2257 "Starting driver with initial channel: %d MHz\n",
2258 curchan->center_freq);
2260 mutex_lock(&sc->mutex);
2262 if (ath9k_wiphy_started(sc)) {
2263 if (sc->chan_idx == curchan->hw_value) {
2265 * Already on the operational channel, the new wiphy
2266 * can be marked active.
2268 aphy->state = ATH_WIPHY_ACTIVE;
2269 ieee80211_wake_queues(hw);
2272 * Another wiphy is on another channel, start the new
2273 * wiphy in paused state.
2275 aphy->state = ATH_WIPHY_PAUSED;
2276 ieee80211_stop_queues(hw);
2278 mutex_unlock(&sc->mutex);
2281 aphy->state = ATH_WIPHY_ACTIVE;
2283 /* setup initial channel */
2285 sc->chan_idx = curchan->hw_value;
2287 init_channel = ath_get_curchannel(sc, hw);
2289 /* Reset SERDES registers */
2290 ath9k_hw_configpcipowersave(ah, 0, 0);
2293 * The basic interface to setting the hardware in a good
2294 * state is ``reset''. On return the hardware is known to
2295 * be powered up and with interrupts disabled. This must
2296 * be followed by initialization of the appropriate bits
2297 * and then setup of the interrupt mask.
2299 spin_lock_bh(&sc->sc_resetlock);
2300 r = ath9k_hw_reset(ah, init_channel, false);
2302 ath_print(common, ATH_DBG_FATAL,
2303 "Unable to reset hardware; reset status %d "
2304 "(freq %u MHz)\n", r,
2305 curchan->center_freq);
2306 spin_unlock_bh(&sc->sc_resetlock);
2309 spin_unlock_bh(&sc->sc_resetlock);
2312 * This is needed only to setup initial state
2313 * but it's best done after a reset.
2315 ath_update_txpow(sc);
2318 * Setup the hardware after reset:
2319 * The receive engine is set going.
2320 * Frame transmit is handled entirely
2321 * in the frame output path; there's nothing to do
2322 * here except setup the interrupt mask.
2324 if (ath_startrecv(sc) != 0) {
2325 ath_print(common, ATH_DBG_FATAL,
2326 "Unable to start recv logic\n");
2331 /* Setup our intr mask. */
2332 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2333 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2334 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2336 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2337 sc->imask |= ATH9K_INT_GTT;
2339 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2340 sc->imask |= ATH9K_INT_CST;
2342 ath_cache_conf_rate(sc, &hw->conf);
2344 sc->sc_flags &= ~SC_OP_INVALID;
2346 /* Disable BMISS interrupt when we're not associated */
2347 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2348 ath9k_hw_set_interrupts(ah, sc->imask);
2350 ieee80211_wake_queues(hw);
2352 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2354 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2355 !ah->btcoex_hw.enabled) {
2356 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2357 AR_STOMP_LOW_WLAN_WGHT);
2358 ath9k_hw_btcoex_enable(ah);
2360 if (common->bus_ops->bt_coex_prep)
2361 common->bus_ops->bt_coex_prep(common);
2362 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2363 ath9k_btcoex_timer_resume(sc);
2367 mutex_unlock(&sc->mutex);
2372 static int ath9k_tx(struct ieee80211_hw *hw,
2373 struct sk_buff *skb)
2375 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2376 struct ath_wiphy *aphy = hw->priv;
2377 struct ath_softc *sc = aphy->sc;
2378 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2379 struct ath_tx_control txctl;
2380 int hdrlen, padsize;
2382 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2383 ath_print(common, ATH_DBG_XMIT,
2384 "ath9k: %s: TX in unexpected wiphy state "
2385 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2389 if (sc->ps_enabled) {
2390 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2392 * mac80211 does not set PM field for normal data frames, so we
2393 * need to update that based on the current PS mode.
2395 if (ieee80211_is_data(hdr->frame_control) &&
2396 !ieee80211_is_nullfunc(hdr->frame_control) &&
2397 !ieee80211_has_pm(hdr->frame_control)) {
2398 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2399 "while in PS mode\n");
2400 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2404 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2406 * We are using PS-Poll and mac80211 can request TX while in
2407 * power save mode. Need to wake up hardware for the TX to be
2408 * completed and if needed, also for RX of buffered frames.
2410 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2411 ath9k_ps_wakeup(sc);
2412 ath9k_hw_setrxabort(sc->sc_ah, 0);
2413 if (ieee80211_is_pspoll(hdr->frame_control)) {
2414 ath_print(common, ATH_DBG_PS,
2415 "Sending PS-Poll to pick a buffered frame\n");
2416 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2418 ath_print(common, ATH_DBG_PS,
2419 "Wake up to complete TX\n");
2420 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2423 * The actual restore operation will happen only after
2424 * the sc_flags bit is cleared. We are just dropping
2425 * the ps_usecount here.
2427 ath9k_ps_restore(sc);
2430 memset(&txctl, 0, sizeof(struct ath_tx_control));
2433 * As a temporary workaround, assign seq# here; this will likely need
2434 * to be cleaned up to work better with Beacon transmission and virtual
2437 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2438 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2439 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2440 sc->tx.seq_no += 0x10;
2441 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2442 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2445 /* Add the padding after the header if this is not already done */
2446 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2448 padsize = hdrlen % 4;
2449 if (skb_headroom(skb) < padsize)
2451 skb_push(skb, padsize);
2452 memmove(skb->data, skb->data + padsize, hdrlen);
2455 /* Check if a tx queue is available */
2457 txctl.txq = ath_test_get_txq(sc, skb);
2461 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2463 if (ath_tx_start(hw, skb, &txctl) != 0) {
2464 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2470 dev_kfree_skb_any(skb);
2475 * Pause btcoex timer and bt duty cycle timer
2477 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2479 struct ath_btcoex *btcoex = &sc->btcoex;
2480 struct ath_hw *ah = sc->sc_ah;
2482 del_timer_sync(&btcoex->period_timer);
2484 if (btcoex->hw_timer_enabled)
2485 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2487 btcoex->hw_timer_enabled = false;
2490 static void ath9k_stop(struct ieee80211_hw *hw)
2492 struct ath_wiphy *aphy = hw->priv;
2493 struct ath_softc *sc = aphy->sc;
2494 struct ath_hw *ah = sc->sc_ah;
2495 struct ath_common *common = ath9k_hw_common(ah);
2497 mutex_lock(&sc->mutex);
2499 aphy->state = ATH_WIPHY_INACTIVE;
2501 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2502 cancel_delayed_work_sync(&sc->tx_complete_work);
2504 if (!sc->num_sec_wiphy) {
2505 cancel_delayed_work_sync(&sc->wiphy_work);
2506 cancel_work_sync(&sc->chan_work);
2509 if (sc->sc_flags & SC_OP_INVALID) {
2510 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2511 mutex_unlock(&sc->mutex);
2515 if (ath9k_wiphy_started(sc)) {
2516 mutex_unlock(&sc->mutex);
2517 return; /* another wiphy still in use */
2520 if (ah->btcoex_hw.enabled) {
2521 ath9k_hw_btcoex_disable(ah);
2522 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2523 ath9k_btcoex_timer_pause(sc);
2526 /* make sure h/w will not generate any interrupt
2527 * before setting the invalid flag. */
2528 ath9k_hw_set_interrupts(ah, 0);
2530 if (!(sc->sc_flags & SC_OP_INVALID)) {
2531 ath_drain_all_txq(sc, false);
2533 ath9k_hw_phy_disable(ah);
2535 sc->rx.rxlink = NULL;
2537 /* disable HAL and put h/w to sleep */
2538 ath9k_hw_disable(ah);
2539 ath9k_hw_configpcipowersave(ah, 1, 1);
2540 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2542 sc->sc_flags |= SC_OP_INVALID;
2544 mutex_unlock(&sc->mutex);
2546 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2549 static int ath9k_add_interface(struct ieee80211_hw *hw,
2550 struct ieee80211_if_init_conf *conf)
2552 struct ath_wiphy *aphy = hw->priv;
2553 struct ath_softc *sc = aphy->sc;
2554 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2555 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2556 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2559 mutex_lock(&sc->mutex);
2561 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2567 switch (conf->type) {
2568 case NL80211_IFTYPE_STATION:
2569 ic_opmode = NL80211_IFTYPE_STATION;
2571 case NL80211_IFTYPE_ADHOC:
2572 case NL80211_IFTYPE_AP:
2573 case NL80211_IFTYPE_MESH_POINT:
2574 if (sc->nbcnvifs >= ATH_BCBUF) {
2578 ic_opmode = conf->type;
2581 ath_print(common, ATH_DBG_FATAL,
2582 "Interface type %d not yet supported\n", conf->type);
2587 ath_print(common, ATH_DBG_CONFIG,
2588 "Attach a VIF of type: %d\n", ic_opmode);
2590 /* Set the VIF opmode */
2591 avp->av_opmode = ic_opmode;
2596 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2597 ath9k_set_bssid_mask(hw);
2600 goto out; /* skip global settings for secondary vif */
2602 if (ic_opmode == NL80211_IFTYPE_AP) {
2603 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2604 sc->sc_flags |= SC_OP_TSF_RESET;
2607 /* Set the device opmode */
2608 sc->sc_ah->opmode = ic_opmode;
2611 * Enable MIB interrupts when there are hardware phy counters.
2612 * Note we only do this (at the moment) for station mode.
2614 if ((conf->type == NL80211_IFTYPE_STATION) ||
2615 (conf->type == NL80211_IFTYPE_ADHOC) ||
2616 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2617 sc->imask |= ATH9K_INT_MIB;
2618 sc->imask |= ATH9K_INT_TSFOOR;
2621 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2623 if (conf->type == NL80211_IFTYPE_AP ||
2624 conf->type == NL80211_IFTYPE_ADHOC ||
2625 conf->type == NL80211_IFTYPE_MONITOR)
2629 mutex_unlock(&sc->mutex);
2633 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2634 struct ieee80211_if_init_conf *conf)
2636 struct ath_wiphy *aphy = hw->priv;
2637 struct ath_softc *sc = aphy->sc;
2638 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2639 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2642 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2644 mutex_lock(&sc->mutex);
2647 del_timer_sync(&sc->ani.timer);
2649 /* Reclaim beacon resources */
2650 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2651 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2652 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2653 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2654 ath_beacon_return(sc, avp);
2657 sc->sc_flags &= ~SC_OP_BEACONS;
2659 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2660 if (sc->beacon.bslot[i] == conf->vif) {
2661 printk(KERN_DEBUG "%s: vif had allocated beacon "
2662 "slot\n", __func__);
2663 sc->beacon.bslot[i] = NULL;
2664 sc->beacon.bslot_aphy[i] = NULL;
2670 mutex_unlock(&sc->mutex);
2673 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2675 struct ath_wiphy *aphy = hw->priv;
2676 struct ath_softc *sc = aphy->sc;
2677 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2678 struct ieee80211_conf *conf = &hw->conf;
2679 struct ath_hw *ah = sc->sc_ah;
2680 bool all_wiphys_idle = false, disable_radio = false;
2682 mutex_lock(&sc->mutex);
2684 /* Leave this as the first check */
2685 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2687 spin_lock_bh(&sc->wiphy_lock);
2688 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2689 spin_unlock_bh(&sc->wiphy_lock);
2691 if (conf->flags & IEEE80211_CONF_IDLE){
2692 if (all_wiphys_idle)
2693 disable_radio = true;
2695 else if (all_wiphys_idle) {
2696 ath_radio_enable(sc);
2697 ath_print(common, ATH_DBG_CONFIG,
2698 "not-idle: enabling radio\n");
2702 if (changed & IEEE80211_CONF_CHANGE_PS) {
2703 if (conf->flags & IEEE80211_CONF_PS) {
2704 if (!(ah->caps.hw_caps &
2705 ATH9K_HW_CAP_AUTOSLEEP)) {
2706 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2707 sc->imask |= ATH9K_INT_TIM_TIMER;
2708 ath9k_hw_set_interrupts(sc->sc_ah,
2711 ath9k_hw_setrxabort(sc->sc_ah, 1);
2713 sc->ps_enabled = true;
2715 sc->ps_enabled = false;
2716 ath9k_setpower(sc, ATH9K_PM_AWAKE);
2717 if (!(ah->caps.hw_caps &
2718 ATH9K_HW_CAP_AUTOSLEEP)) {
2719 ath9k_hw_setrxabort(sc->sc_ah, 0);
2720 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2721 SC_OP_WAIT_FOR_CAB |
2722 SC_OP_WAIT_FOR_PSPOLL_DATA |
2723 SC_OP_WAIT_FOR_TX_ACK);
2724 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2725 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2726 ath9k_hw_set_interrupts(sc->sc_ah,
2733 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2734 struct ieee80211_channel *curchan = hw->conf.channel;
2735 int pos = curchan->hw_value;
2737 aphy->chan_idx = pos;
2738 aphy->chan_is_ht = conf_is_ht(conf);
2740 if (aphy->state == ATH_WIPHY_SCAN ||
2741 aphy->state == ATH_WIPHY_ACTIVE)
2742 ath9k_wiphy_pause_all_forced(sc, aphy);
2745 * Do not change operational channel based on a paused
2748 goto skip_chan_change;
2751 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2752 curchan->center_freq);
2754 /* XXX: remove me eventualy */
2755 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2757 ath_update_chainmask(sc, conf_is_ht(conf));
2759 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2760 ath_print(common, ATH_DBG_FATAL,
2761 "Unable to set channel\n");
2762 mutex_unlock(&sc->mutex);
2768 if (changed & IEEE80211_CONF_CHANGE_POWER)
2769 sc->config.txpowlimit = 2 * conf->power_level;
2771 if (disable_radio) {
2772 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2773 ath_radio_disable(sc);
2776 mutex_unlock(&sc->mutex);
2781 #define SUPPORTED_FILTERS \
2782 (FIF_PROMISC_IN_BSS | \
2787 FIF_BCN_PRBRESP_PROMISC | \
2790 /* FIXME: sc->sc_full_reset ? */
2791 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2792 unsigned int changed_flags,
2793 unsigned int *total_flags,
2796 struct ath_wiphy *aphy = hw->priv;
2797 struct ath_softc *sc = aphy->sc;
2800 changed_flags &= SUPPORTED_FILTERS;
2801 *total_flags &= SUPPORTED_FILTERS;
2803 sc->rx.rxfilter = *total_flags;
2804 ath9k_ps_wakeup(sc);
2805 rfilt = ath_calcrxfilter(sc);
2806 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2807 ath9k_ps_restore(sc);
2809 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2810 "Set HW RX filter: 0x%x\n", rfilt);
2813 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2814 struct ieee80211_vif *vif,
2815 enum sta_notify_cmd cmd,
2816 struct ieee80211_sta *sta)
2818 struct ath_wiphy *aphy = hw->priv;
2819 struct ath_softc *sc = aphy->sc;
2822 case STA_NOTIFY_ADD:
2823 ath_node_attach(sc, sta);
2825 case STA_NOTIFY_REMOVE:
2826 ath_node_detach(sc, sta);
2833 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2834 const struct ieee80211_tx_queue_params *params)
2836 struct ath_wiphy *aphy = hw->priv;
2837 struct ath_softc *sc = aphy->sc;
2838 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2839 struct ath9k_tx_queue_info qi;
2842 if (queue >= WME_NUM_AC)
2845 mutex_lock(&sc->mutex);
2847 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2849 qi.tqi_aifs = params->aifs;
2850 qi.tqi_cwmin = params->cw_min;
2851 qi.tqi_cwmax = params->cw_max;
2852 qi.tqi_burstTime = params->txop;
2853 qnum = ath_get_hal_qnum(queue, sc);
2855 ath_print(common, ATH_DBG_CONFIG,
2856 "Configure tx [queue/halq] [%d/%d], "
2857 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2858 queue, qnum, params->aifs, params->cw_min,
2859 params->cw_max, params->txop);
2861 ret = ath_txq_update(sc, qnum, &qi);
2863 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2865 mutex_unlock(&sc->mutex);
2870 static int ath9k_set_key(struct ieee80211_hw *hw,
2871 enum set_key_cmd cmd,
2872 struct ieee80211_vif *vif,
2873 struct ieee80211_sta *sta,
2874 struct ieee80211_key_conf *key)
2876 struct ath_wiphy *aphy = hw->priv;
2877 struct ath_softc *sc = aphy->sc;
2878 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2881 if (modparam_nohwcrypt)
2884 mutex_lock(&sc->mutex);
2885 ath9k_ps_wakeup(sc);
2886 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2890 ret = ath_key_config(sc, vif, sta, key);
2892 key->hw_key_idx = ret;
2893 /* push IV and Michael MIC generation to stack */
2894 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2895 if (key->alg == ALG_TKIP)
2896 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2897 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2898 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2903 ath_key_delete(sc, key);
2909 ath9k_ps_restore(sc);
2910 mutex_unlock(&sc->mutex);
2915 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2916 struct ieee80211_vif *vif,
2917 struct ieee80211_bss_conf *bss_conf,
2920 struct ath_wiphy *aphy = hw->priv;
2921 struct ath_softc *sc = aphy->sc;
2922 struct ath_hw *ah = sc->sc_ah;
2923 struct ath_common *common = ath9k_hw_common(ah);
2924 struct ath_vif *avp = (void *)vif->drv_priv;
2928 mutex_lock(&sc->mutex);
2931 * TODO: Need to decide which hw opmode to use for
2932 * multi-interface cases
2933 * XXX: This belongs into add_interface!
2935 if (vif->type == NL80211_IFTYPE_AP &&
2936 ah->opmode != NL80211_IFTYPE_AP) {
2937 ah->opmode = NL80211_IFTYPE_STATION;
2938 ath9k_hw_setopmode(ah);
2939 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2941 ath9k_hw_write_associd(ah);
2942 /* Request full reset to get hw opmode changed properly */
2943 sc->sc_flags |= SC_OP_FULL_RESET;
2946 if ((changed & BSS_CHANGED_BSSID) &&
2947 !is_zero_ether_addr(bss_conf->bssid)) {
2948 switch (vif->type) {
2949 case NL80211_IFTYPE_STATION:
2950 case NL80211_IFTYPE_ADHOC:
2951 case NL80211_IFTYPE_MESH_POINT:
2953 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2954 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2956 ath9k_hw_write_associd(ah);
2958 /* Set aggregation protection mode parameters */
2959 sc->config.ath_aggr_prot = 0;
2961 ath_print(common, ATH_DBG_CONFIG,
2962 "RX filter 0x%x bssid %pM aid 0x%x\n",
2963 rfilt, common->curbssid, common->curaid);
2965 /* need to reconfigure the beacon */
2966 sc->sc_flags &= ~SC_OP_BEACONS ;
2974 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2975 (vif->type == NL80211_IFTYPE_AP) ||
2976 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2977 if ((changed & BSS_CHANGED_BEACON) ||
2978 (changed & BSS_CHANGED_BEACON_ENABLED &&
2979 bss_conf->enable_beacon)) {
2981 * Allocate and setup the beacon frame.
2983 * Stop any previous beacon DMA. This may be
2984 * necessary, for example, when an ibss merge
2985 * causes reconfiguration; we may be called
2986 * with beacon transmission active.
2988 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2990 error = ath_beacon_alloc(aphy, vif);
2992 ath_beacon_config(sc, vif);
2996 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2997 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2998 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2999 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
3000 ath9k_hw_keysetmac(sc->sc_ah,
3005 /* Only legacy IBSS for now */
3006 if (vif->type == NL80211_IFTYPE_ADHOC)
3007 ath_update_chainmask(sc, 0);
3009 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3010 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3011 bss_conf->use_short_preamble);
3012 if (bss_conf->use_short_preamble)
3013 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3015 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3018 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
3019 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3020 bss_conf->use_cts_prot);
3021 if (bss_conf->use_cts_prot &&
3022 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3023 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3025 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3028 if (changed & BSS_CHANGED_ASSOC) {
3029 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
3031 ath9k_bss_assoc_info(sc, vif, bss_conf);
3035 * The HW TSF has to be reset when the beacon interval changes.
3036 * We set the flag here, and ath_beacon_config_ap() would take this
3037 * into account when it gets called through the subsequent
3038 * config_interface() call - with IFCC_BEACON in the changed field.
3041 if (changed & BSS_CHANGED_BEACON_INT) {
3042 sc->sc_flags |= SC_OP_TSF_RESET;
3043 sc->beacon_interval = bss_conf->beacon_int;
3046 mutex_unlock(&sc->mutex);
3049 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3052 struct ath_wiphy *aphy = hw->priv;
3053 struct ath_softc *sc = aphy->sc;
3055 mutex_lock(&sc->mutex);
3056 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3057 mutex_unlock(&sc->mutex);
3062 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3064 struct ath_wiphy *aphy = hw->priv;
3065 struct ath_softc *sc = aphy->sc;
3067 mutex_lock(&sc->mutex);
3068 ath9k_hw_settsf64(sc->sc_ah, tsf);
3069 mutex_unlock(&sc->mutex);
3072 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3074 struct ath_wiphy *aphy = hw->priv;
3075 struct ath_softc *sc = aphy->sc;
3077 mutex_lock(&sc->mutex);
3079 ath9k_ps_wakeup(sc);
3080 ath9k_hw_reset_tsf(sc->sc_ah);
3081 ath9k_ps_restore(sc);
3083 mutex_unlock(&sc->mutex);
3086 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3087 enum ieee80211_ampdu_mlme_action action,
3088 struct ieee80211_sta *sta,
3091 struct ath_wiphy *aphy = hw->priv;
3092 struct ath_softc *sc = aphy->sc;
3096 case IEEE80211_AMPDU_RX_START:
3097 if (!(sc->sc_flags & SC_OP_RXAGGR))
3100 case IEEE80211_AMPDU_RX_STOP:
3102 case IEEE80211_AMPDU_TX_START:
3103 ath_tx_aggr_start(sc, sta, tid, ssn);
3104 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3106 case IEEE80211_AMPDU_TX_STOP:
3107 ath_tx_aggr_stop(sc, sta, tid);
3108 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3110 case IEEE80211_AMPDU_TX_OPERATIONAL:
3111 ath_tx_aggr_resume(sc, sta, tid);
3114 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3115 "Unknown AMPDU action\n");
3121 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3123 struct ath_wiphy *aphy = hw->priv;
3124 struct ath_softc *sc = aphy->sc;
3126 mutex_lock(&sc->mutex);
3127 if (ath9k_wiphy_scanning(sc)) {
3128 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3131 * Do not allow the concurrent scanning state for now. This
3132 * could be improved with scanning control moved into ath9k.
3134 mutex_unlock(&sc->mutex);
3138 aphy->state = ATH_WIPHY_SCAN;
3139 ath9k_wiphy_pause_all_forced(sc, aphy);
3141 spin_lock_bh(&sc->ani_lock);
3142 sc->sc_flags |= SC_OP_SCANNING;
3143 spin_unlock_bh(&sc->ani_lock);
3144 mutex_unlock(&sc->mutex);
3147 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3149 struct ath_wiphy *aphy = hw->priv;
3150 struct ath_softc *sc = aphy->sc;
3152 mutex_lock(&sc->mutex);
3153 spin_lock_bh(&sc->ani_lock);
3154 aphy->state = ATH_WIPHY_ACTIVE;
3155 sc->sc_flags &= ~SC_OP_SCANNING;
3156 sc->sc_flags |= SC_OP_FULL_RESET;
3157 spin_unlock_bh(&sc->ani_lock);
3158 ath_beacon_config(sc, NULL);
3159 mutex_unlock(&sc->mutex);
3162 struct ieee80211_ops ath9k_ops = {
3164 .start = ath9k_start,
3166 .add_interface = ath9k_add_interface,
3167 .remove_interface = ath9k_remove_interface,
3168 .config = ath9k_config,
3169 .configure_filter = ath9k_configure_filter,
3170 .sta_notify = ath9k_sta_notify,
3171 .conf_tx = ath9k_conf_tx,
3172 .bss_info_changed = ath9k_bss_info_changed,
3173 .set_key = ath9k_set_key,
3174 .get_tsf = ath9k_get_tsf,
3175 .set_tsf = ath9k_set_tsf,
3176 .reset_tsf = ath9k_reset_tsf,
3177 .ampdu_action = ath9k_ampdu_action,
3178 .sw_scan_start = ath9k_sw_scan_start,
3179 .sw_scan_complete = ath9k_sw_scan_complete,
3180 .rfkill_poll = ath9k_rfkill_poll_state,
3186 } ath_mac_bb_names[] = {
3187 { AR_SREV_VERSION_5416_PCI, "5416" },
3188 { AR_SREV_VERSION_5416_PCIE, "5418" },
3189 { AR_SREV_VERSION_9100, "9100" },
3190 { AR_SREV_VERSION_9160, "9160" },
3191 { AR_SREV_VERSION_9280, "9280" },
3192 { AR_SREV_VERSION_9285, "9285" },
3193 { AR_SREV_VERSION_9287, "9287" }
3199 } ath_rf_names[] = {
3201 { AR_RAD5133_SREV_MAJOR, "5133" },
3202 { AR_RAD5122_SREV_MAJOR, "5122" },
3203 { AR_RAD2133_SREV_MAJOR, "2133" },
3204 { AR_RAD2122_SREV_MAJOR, "2122" }
3208 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3211 ath_mac_bb_name(u32 mac_bb_version)
3215 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3216 if (ath_mac_bb_names[i].version == mac_bb_version) {
3217 return ath_mac_bb_names[i].name;
3225 * Return the RF name. "????" is returned if the RF is unknown.
3228 ath_rf_name(u16 rf_version)
3232 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3233 if (ath_rf_names[i].version == rf_version) {
3234 return ath_rf_names[i].name;
3241 static int __init ath9k_init(void)
3245 /* Register rate control algorithm */
3246 error = ath_rate_control_register();
3249 "ath9k: Unable to register rate control "
3255 error = ath9k_debug_create_root();
3258 "ath9k: Unable to create debugfs root: %d\n",
3260 goto err_rate_unregister;
3263 error = ath_pci_init();
3266 "ath9k: No PCI devices found, driver not installed.\n");
3268 goto err_remove_root;
3271 error = ath_ahb_init();
3283 ath9k_debug_remove_root();
3284 err_rate_unregister:
3285 ath_rate_control_unregister();
3289 module_init(ath9k_init);
3291 static void __exit ath9k_exit(void)
3295 ath9k_debug_remove_root();
3296 ath_rate_control_unregister();
3297 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3299 module_exit(ath9k_exit);