drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "initvals.h"
  23
  24 #define ATH9K_CLOCK_RATE_CCK            22
  25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  27
  28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  31                               struct ar5416_eeprom_def *pEepData,
  32                               u32 reg, u32 value);
  33 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  34 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  35
  36 MODULE_AUTHOR("Atheros Communications");
  37 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  38 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  39 MODULE_LICENSE("Dual BSD/GPL");
  40
  41 static int __init ath9k_init(void)
  42 {
  43         return 0;
  44 }
  45 module_init(ath9k_init);
  46
  47 static void __exit ath9k_exit(void)
  48 {
  49         return;
  50 }
  51 module_exit(ath9k_exit);
  52
  53 /********************/
  54 /* Helper Functions */
  55 /********************/
  56
  57 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  58 {
  59         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  60
  61         if (!ah->curchan) /* should really check for CCK instead */
  62                 return clks / ATH9K_CLOCK_RATE_CCK;
  63         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  64                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  65
  66         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  67 }
  68
  69 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  70 {
  71         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  72
  73         if (conf_is_ht40(conf))
  74                 return ath9k_hw_mac_usec(ah, clks) / 2;
  75         else
  76                 return ath9k_hw_mac_usec(ah, clks);
  77 }
  78
  79 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  80 {
  81         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  82
  83         if (!ah->curchan) /* should really check for CCK instead */
  84                 return usecs *ATH9K_CLOCK_RATE_CCK;
  85         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  86                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  87         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  88 }
  89
  90 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  91 {
  92         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  93
  94         if (conf_is_ht40(conf))
  95                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  96         else
  97                 return ath9k_hw_mac_clks(ah, usecs);
  98 }
  99
 100 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 101 {
 102         int i;
 103
 104         BUG_ON(timeout < AH_TIME_QUANTUM);
 105
 106         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 107                 if ((REG_READ(ah, reg) & mask) == val)
 108                         return true;
 109
 110                 udelay(AH_TIME_QUANTUM);
 111         }
 112
 113         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 114                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 115                   timeout, reg, REG_READ(ah, reg), mask, val);
 116
 117         return false;
 118 }
 119 EXPORT_SYMBOL(ath9k_hw_wait);
 120
 121 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 122 {
 123         u32 retval;
 124         int i;
 125
 126         for (i = 0, retval = 0; i < n; i++) {
 127                 retval = (retval << 1) | (val & 1);
 128                 val >>= 1;
 129         }
 130         return retval;
 131 }
 132
 133 bool ath9k_get_channel_edges(struct ath_hw *ah,
 134                              u16 flags, u16 *low,
 135                              u16 *high)
 136 {
 137         struct ath9k_hw_capabilities *pCap = &ah->caps;
 138
 139         if (flags & CHANNEL_5GHZ) {
 140                 *low = pCap->low_5ghz_chan;
 141                 *high = pCap->high_5ghz_chan;
 142                 return true;
 143         }
 144         if ((flags & CHANNEL_2GHZ)) {
 145                 *low = pCap->low_2ghz_chan;
 146                 *high = pCap->high_2ghz_chan;
 147                 return true;
 148         }
 149         return false;
 150 }
 151
 152 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 153                            const struct ath_rate_table *rates,
 154                            u32 frameLen, u16 rateix,
 155                            bool shortPreamble)
 156 {
 157         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 158         u32 kbps;
 159
 160         kbps = rates->info[rateix].ratekbps;
 161
 162         if (kbps == 0)
 163                 return 0;
 164
 165         switch (rates->info[rateix].phy) {
 166         case WLAN_RC_PHY_CCK:
 167                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 168                 if (shortPreamble && rates->info[rateix].short_preamble)
 169                         phyTime >>= 1;
 170                 numBits = frameLen << 3;
 171                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 172                 break;
 173         case WLAN_RC_PHY_OFDM:
 174                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 175                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 176                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 177                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 178                         txTime = OFDM_SIFS_TIME_QUARTER
 179                                 + OFDM_PREAMBLE_TIME_QUARTER
 180                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 181                 } else if (ah->curchan &&
 182                            IS_CHAN_HALF_RATE(ah->curchan)) {
 183                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 184                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 185                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 186                         txTime = OFDM_SIFS_TIME_HALF +
 187                                 OFDM_PREAMBLE_TIME_HALF
 188                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 189                 } else {
 190                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 191                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 192                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 193                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 194                                 + (numSymbols * OFDM_SYMBOL_TIME);
 195                 }
 196                 break;
 197         default:
 198                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 199                           "Unknown phy %u (rate ix %u)\n",
 200                           rates->info[rateix].phy, rateix);
 201                 txTime = 0;
 202                 break;
 203         }
 204
 205         return txTime;
 206 }
 207 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 208
 209 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 210                                   struct ath9k_channel *chan,
 211                                   struct chan_centers *centers)
 212 {
 213         int8_t extoff;
 214
 215         if (!IS_CHAN_HT40(chan)) {
 216                 centers->ctl_center = centers->ext_center =
 217                         centers->synth_center = chan->channel;
 218                 return;
 219         }
 220
 221         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 222             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 223                 centers->synth_center =
 224                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 225                 extoff = 1;
 226         } else {
 227                 centers->synth_center =
 228                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 229                 extoff = -1;
 230         }
 231
 232         centers->ctl_center =
 233                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 234         /* 25 MHz spacing is supported by hw but not on upper layers */
 235         centers->ext_center =
 236                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 237 }
 238
 239 /******************/
 240 /* Chip Revisions */
 241 /******************/
 242
 243 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 244 {
 245         u32 val;
 246
 247         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 248
 249         if (val == 0xFF) {
 250                 val = REG_READ(ah, AR_SREV);
 251                 ah->hw_version.macVersion =
 252                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 253                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 254                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 255         } else {
 256                 if (!AR_SREV_9100(ah))
 257                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 258
 259                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 260
 261                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 262                         ah->is_pciexpress = true;
 263         }
 264 }
 265
 266 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 267 {
 268         u32 val;
 269         int i;
 270
 271         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 272
 273         for (i = 0; i < 8; i++)
 274                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 275         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 276         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 277
 278         return ath9k_hw_reverse_bits(val, 8);
 279 }
 280
 281 /************************************/
 282 /* HW Attach, Detach, Init Routines */
 283 /************************************/
 284
 285 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 286 {
 287         if (AR_SREV_9100(ah))
 288                 return;
 289
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 294         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 295         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 296         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 297         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 298         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 299
 300         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 301 }
 302
 303 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 304 {
 305         struct ath_common *common = ath9k_hw_common(ah);
 306         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 307         u32 regHold[2];
 308         u32 patternData[4] = { 0x55555555,
 309                                0xaaaaaaaa,
 310                                0x66666666,
 311                                0x99999999 };
 312         int i, j;
 313
 314         for (i = 0; i < 2; i++) {
 315                 u32 addr = regAddr[i];
 316                 u32 wrData, rdData;
 317
 318                 regHold[i] = REG_READ(ah, addr);
 319                 for (j = 0; j < 0x100; j++) {
 320                         wrData = (j << 16) | j;
 321                         REG_WRITE(ah, addr, wrData);
 322                         rdData = REG_READ(ah, addr);
 323                         if (rdData != wrData) {
 324                                 ath_print(common, ATH_DBG_FATAL,
 325                                           "address test failed "
 326                                           "addr: 0x%08x - wr:0x%08x != "
 327                                           "rd:0x%08x\n",
 328                                           addr, wrData, rdData);
 329                                 return false;
 330                         }
 331                 }
 332                 for (j = 0; j < 4; j++) {
 333                         wrData = patternData[j];
 334                         REG_WRITE(ah, addr, wrData);
 335                         rdData = REG_READ(ah, addr);
 336                         if (wrData != rdData) {
 337                                 ath_print(common, ATH_DBG_FATAL,
 338                                           "address test failed "
 339                                           "addr: 0x%08x - wr:0x%08x != "
 340                                           "rd:0x%08x\n",
 341                                           addr, wrData, rdData);
 342                                 return false;
 343                         }
 344                 }
 345                 REG_WRITE(ah, regAddr[i], regHold[i]);
 346         }
 347         udelay(100);
 348
 349         return true;
 350 }
 351
 352 static const char *ath9k_hw_devname(u16 devid)
 353 {
 354         switch (devid) {
 355         case AR5416_DEVID_PCI:
 356                 return "Atheros 5416";
 357         case AR5416_DEVID_PCIE:
 358                 return "Atheros 5418";
 359         case AR9160_DEVID_PCI:
 360                 return "Atheros 9160";
 361         case AR5416_AR9100_DEVID:
 362                 return "Atheros 9100";
 363         case AR9280_DEVID_PCI:
 364         case AR9280_DEVID_PCIE:
 365                 return "Atheros 9280";
 366         case AR9285_DEVID_PCIE:
 367                 return "Atheros 9285";
 368         case AR5416_DEVID_AR9287_PCI:
 369         case AR5416_DEVID_AR9287_PCIE:
 370                 return "Atheros 9287";
 371         }
 372
 373         return NULL;
 374 }
 375
 376 static void ath9k_hw_init_config(struct ath_hw *ah)
 377 {
 378         int i;
 379
 380         ah->config.dma_beacon_response_time = 2;
 381         ah->config.sw_beacon_response_time = 10;
 382         ah->config.additional_swba_backoff = 0;
 383         ah->config.ack_6mb = 0x0;
 384         ah->config.cwm_ignore_extcca = 0;
 385         ah->config.pcie_powersave_enable = 0;
 386         ah->config.pcie_clock_req = 0;
 387         ah->config.pcie_waen = 0;
 388         ah->config.analog_shiftreg = 1;
 389         ah->config.ht_enable = 1;
 390         ah->config.ofdm_trig_low = 200;
 391         ah->config.ofdm_trig_high = 500;
 392         ah->config.cck_trig_high = 200;
 393         ah->config.cck_trig_low = 100;
 394         ah->config.enable_ani = 1;
 395         ah->config.diversity_control = ATH9K_ANT_VARIABLE;
 396         ah->config.antenna_switch_swap = 0;
 397
 398         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 399                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 400                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 401         }
 402
 403         ah->config.intr_mitigation = true;
 404
 405         /*
 406          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 407          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 408          * This means we use it for all AR5416 devices, and the few
 409          * minor PCI AR9280 devices out there.
 410          *
 411          * Serialization is required because these devices do not handle
 412          * well the case of two concurrent reads/writes due to the latency
 413          * involved. During one read/write another read/write can be issued
 414          * on another CPU while the previous read/write may still be working
 415          * on our hardware, if we hit this case the hardware poops in a loop.
 416          * We prevent this by serializing reads and writes.
 417          *
 418          * This issue is not present on PCI-Express devices or pre-AR5416
 419          * devices (legacy, 802.11abg).
 420          */
 421         if (num_possible_cpus() > 1)
 422                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 423 }
 424 EXPORT_SYMBOL(ath9k_hw_init);
 425
 426 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 427 {
 428         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 429
 430         regulatory->country_code = CTRY_DEFAULT;
 431         regulatory->power_limit = MAX_RATE_POWER;
 432         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 433
 434         ah->hw_version.magic = AR5416_MAGIC;
 435         ah->hw_version.subvendorid = 0;
 436
 437         ah->ah_flags = 0;
 438         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 439                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 440         if (!AR_SREV_9100(ah))
 441                 ah->ah_flags = AH_USE_EEPROM;
 442
 443         ah->atim_window = 0;
 444         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 445         ah->beacon_interval = 100;
 446         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 447         ah->slottime = (u32) -1;
 448         ah->acktimeout = (u32) -1;
 449         ah->ctstimeout = (u32) -1;
 450         ah->globaltxtimeout = (u32) -1;
 451
 452         ah->gbeacon_rate = 0;
 453
 454         ah->power_mode = ATH9K_PM_UNDEFINED;
 455 }
 456
 457 static int ath9k_hw_rfattach(struct ath_hw *ah)
 458 {
 459         bool rfStatus = false;
 460         int ecode = 0;
 461
 462         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 463         if (!rfStatus) {
 464                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 465                           "RF setup failed, status: %u\n", ecode);
 466                 return ecode;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 473 {
 474         u32 val;
 475
 476         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 477
 478         val = ath9k_hw_get_radiorev(ah);
 479         switch (val & AR_RADIO_SREV_MAJOR) {
 480         case 0:
 481                 val = AR_RAD5133_SREV_MAJOR;
 482                 break;
 483         case AR_RAD5133_SREV_MAJOR:
 484         case AR_RAD5122_SREV_MAJOR:
 485         case AR_RAD2133_SREV_MAJOR:
 486         case AR_RAD2122_SREV_MAJOR:
 487                 break;
 488         default:
 489                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 490                           "Radio Chip Rev 0x%02X not supported\n",
 491                           val & AR_RADIO_SREV_MAJOR);
 492                 return -EOPNOTSUPP;
 493         }
 494
 495         ah->hw_version.analog5GhzRev = val;
 496
 497         return 0;
 498 }
 499
 500 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 501 {
 502         struct ath_common *common = ath9k_hw_common(ah);
 503         u32 sum;
 504         int i;
 505         u16 eeval;
 506
 507         sum = 0;
 508         for (i = 0; i < 3; i++) {
 509                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 510                 sum += eeval;
 511                 common->macaddr[2 * i] = eeval >> 8;
 512                 common->macaddr[2 * i + 1] = eeval & 0xff;
 513         }
 514         if (sum == 0 || sum == 0xffff * 3)
 515                 return -EADDRNOTAVAIL;
 516
 517         return 0;
 518 }
 519
 520 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 521 {
 522         u32 rxgain_type;
 523
 524         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 525                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 526
 527                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 528                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 529                         ar9280Modes_backoff_13db_rxgain_9280_2,
 530                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 531                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 532                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 533                         ar9280Modes_backoff_23db_rxgain_9280_2,
 534                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 535                 else
 536                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 537                         ar9280Modes_original_rxgain_9280_2,
 538                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 539         } else {
 540                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 541                         ar9280Modes_original_rxgain_9280_2,
 542                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 543         }
 544 }
 545
 546 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 547 {
 548         u32 txgain_type;
 549
 550         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 551                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 552
 553                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 554                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 555                         ar9280Modes_high_power_tx_gain_9280_2,
 556                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 557                 else
 558                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 559                         ar9280Modes_original_tx_gain_9280_2,
 560                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 561         } else {
 562                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 563                 ar9280Modes_original_tx_gain_9280_2,
 564                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 565         }
 566 }
 567
 568 static int ath9k_hw_post_init(struct ath_hw *ah)
 569 {
 570         int ecode;
 571
 572         if (!ath9k_hw_chip_test(ah))
 573                 return -ENODEV;
 574
 575         ecode = ath9k_hw_rf_claim(ah);
 576         if (ecode != 0)
 577                 return ecode;
 578
 579         ecode = ath9k_hw_eeprom_init(ah);
 580         if (ecode != 0)
 581                 return ecode;
 582
 583         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 584                   "Eeprom VER: %d, REV: %d\n",
 585                   ah->eep_ops->get_eeprom_ver(ah),
 586                   ah->eep_ops->get_eeprom_rev(ah));
 587
 588         ecode = ath9k_hw_rfattach(ah);
 589         if (ecode != 0)
 590                 return ecode;
 591
 592         if (!AR_SREV_9100(ah)) {
 593                 ath9k_hw_ani_setup(ah);
 594                 ath9k_hw_ani_init(ah);
 595         }
 596
 597         return 0;
 598 }
 599
 600 static bool ath9k_hw_devid_supported(u16 devid)
 601 {
 602         switch (devid) {
 603         case AR5416_DEVID_PCI:
 604         case AR5416_DEVID_PCIE:
 605         case AR5416_AR9100_DEVID:
 606         case AR9160_DEVID_PCI:
 607         case AR9280_DEVID_PCI:
 608         case AR9280_DEVID_PCIE:
 609         case AR9285_DEVID_PCIE:
 610         case AR5416_DEVID_AR9287_PCI:
 611         case AR5416_DEVID_AR9287_PCIE:
 612         case AR9271_USB:
 613                 return true;
 614         default:
 615                 break;
 616         }
 617         return false;
 618 }
 619
 620 static bool ath9k_hw_macversion_supported(u32 macversion)
 621 {
 622         switch (macversion) {
 623         case AR_SREV_VERSION_5416_PCI:
 624         case AR_SREV_VERSION_5416_PCIE:
 625         case AR_SREV_VERSION_9160:
 626         case AR_SREV_VERSION_9100:
 627         case AR_SREV_VERSION_9280:
 628         case AR_SREV_VERSION_9285:
 629         case AR_SREV_VERSION_9287:
 630         case AR_SREV_VERSION_9271:
 631                 return true;
 632         default:
 633                 break;
 634         }
 635         return false;
 636 }
 637
 638 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 639 {
 640         if (AR_SREV_9160_10_OR_LATER(ah)) {
 641                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 642                         ah->iq_caldata.calData = &iq_cal_single_sample;
 643                         ah->adcgain_caldata.calData =
 644                                 &adc_gain_cal_single_sample;
 645                         ah->adcdc_caldata.calData =
 646                                 &adc_dc_cal_single_sample;
 647                         ah->adcdc_calinitdata.calData =
 648                                 &adc_init_dc_cal;
 649                 } else {
 650                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 651                         ah->adcgain_caldata.calData =
 652                                 &adc_gain_cal_multi_sample;
 653                         ah->adcdc_caldata.calData =
 654                                 &adc_dc_cal_multi_sample;
 655                         ah->adcdc_calinitdata.calData =
 656                                 &adc_init_dc_cal;
 657                 }
 658                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 659         }
 660 }
 661
 662 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 663 {
 664         if (AR_SREV_9271(ah)) {
 665                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
 666                                ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
 667                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
 668                                ARRAY_SIZE(ar9271Common_9271_1_0), 2);
 669                 return;
 670         }
 671
 672         if (AR_SREV_9287_11_OR_LATER(ah)) {
 673                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 674                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 675                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 676                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 677                 if (ah->config.pcie_clock_req)
 678                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 679                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 680                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 681                 else
 682                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 683                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 684                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 685                                         2);
 686         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 687                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 688                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 689                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 690                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 691
 692                 if (ah->config.pcie_clock_req)
 693                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 694                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 695                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 696                 else
 697                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 698                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 699                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 700                                   2);
 701         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 702
 703
 704                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 705                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 706                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 707                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 708
 709                 if (ah->config.pcie_clock_req) {
 710                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 711                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 712                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 713                 } else {
 714                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 715                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 716                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 717                                   2);
 718                 }
 719         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 720                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 721                                ARRAY_SIZE(ar9285Modes_9285), 6);
 722                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 723                                ARRAY_SIZE(ar9285Common_9285), 2);
 724
 725                 if (ah->config.pcie_clock_req) {
 726                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 727                         ar9285PciePhy_clkreq_off_L1_9285,
 728                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 729                 } else {
 730                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 731                         ar9285PciePhy_clkreq_always_on_L1_9285,
 732                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 733                 }
 734         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 735                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 736                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 737                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 738                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 739
 740                 if (ah->config.pcie_clock_req) {
 741                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 742                                ar9280PciePhy_clkreq_off_L1_9280,
 743                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 744                 } else {
 745                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 746                                ar9280PciePhy_clkreq_always_on_L1_9280,
 747                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 748                 }
 749                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 750                                ar9280Modes_fast_clock_9280_2,
 751                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 752         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 753                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 754                                ARRAY_SIZE(ar9280Modes_9280), 6);
 755                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 756                                ARRAY_SIZE(ar9280Common_9280), 2);
 757         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 758                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 759                                ARRAY_SIZE(ar5416Modes_9160), 6);
 760                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 761                                ARRAY_SIZE(ar5416Common_9160), 2);
 762                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 763                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 764                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 765                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 766                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 767                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 768                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 769                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 770                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 771                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 772                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 773                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 774                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 775                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 776                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 777                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 778                 if (AR_SREV_9160_11(ah)) {
 779                         INIT_INI_ARRAY(&ah->iniAddac,
 780                                        ar5416Addac_91601_1,
 781                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 782                 } else {
 783                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 784                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 785                 }
 786         } else if (AR_SREV_9100_OR_LATER(ah)) {
 787                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 788                                ARRAY_SIZE(ar5416Modes_9100), 6);
 789                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 790                                ARRAY_SIZE(ar5416Common_9100), 2);
 791                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 792                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 793                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 794                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 795                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 796                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 797                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 798                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 799                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 800                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 801                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 802                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 803                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 804                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 805                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 806                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 807                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 808                                ARRAY_SIZE(ar5416Addac_9100), 2);
 809         } else {
 810                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 811                                ARRAY_SIZE(ar5416Modes), 6);
 812                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 813                                ARRAY_SIZE(ar5416Common), 2);
 814                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 815                                ARRAY_SIZE(ar5416Bank0), 2);
 816                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 817                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 818                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 819                                ARRAY_SIZE(ar5416Bank1), 2);
 820                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 821                                ARRAY_SIZE(ar5416Bank2), 2);
 822                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 823                                ARRAY_SIZE(ar5416Bank3), 3);
 824                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 825                                ARRAY_SIZE(ar5416Bank6), 3);
 826                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 827                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 828                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 829                                ARRAY_SIZE(ar5416Bank7), 2);
 830                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 831                                ARRAY_SIZE(ar5416Addac), 2);
 832         }
 833 }
 834
 835 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 836 {
 837         if (AR_SREV_9287_11_OR_LATER(ah))
 838                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 839                 ar9287Modes_rx_gain_9287_1_1,
 840                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 841         else if (AR_SREV_9287_10(ah))
 842                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 843                 ar9287Modes_rx_gain_9287_1_0,
 844                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 845         else if (AR_SREV_9280_20(ah))
 846                 ath9k_hw_init_rxgain_ini(ah);
 847
 848         if (AR_SREV_9287_11_OR_LATER(ah)) {
 849                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 850                 ar9287Modes_tx_gain_9287_1_1,
 851                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 852         } else if (AR_SREV_9287_10(ah)) {
 853                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 854                 ar9287Modes_tx_gain_9287_1_0,
 855                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 856         } else if (AR_SREV_9280_20(ah)) {
 857                 ath9k_hw_init_txgain_ini(ah);
 858         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 859                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 860
 861                 /* txgain table */
 862                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 863                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 864                         ar9285Modes_high_power_tx_gain_9285_1_2,
 865                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 866                 } else {
 867                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 868                         ar9285Modes_original_tx_gain_9285_1_2,
 869                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 870                 }
 871
 872         }
 873 }
 874
 875 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
 876 {
 877         u32 i, j;
 878
 879         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 880             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 881
 882                 /* EEPROM Fixup */
 883                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 884                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 885
 886                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 887                                 u32 val = INI_RA(&ah->iniModes, i, j);
 888
 889                                 INI_RA(&ah->iniModes, i, j) =
 890                                         ath9k_hw_ini_fixup(ah,
 891                                                            &ah->eeprom.def,
 892                                                            reg, val);
 893                         }
 894                 }
 895         }
 896 }
 897
 898 int ath9k_hw_init(struct ath_hw *ah)
 899 {
 900         struct ath_common *common = ath9k_hw_common(ah);
 901         int r = 0;
 902
 903         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 904                 ath_print(common, ATH_DBG_FATAL,
 905                           "Unsupported device ID: 0x%0x\n",
 906                           ah->hw_version.devid);
 907                 return -EOPNOTSUPP;
 908         }
 909
 910         ath9k_hw_init_defaults(ah);
 911         ath9k_hw_init_config(ah);
 912
 913         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 914                 ath_print(common, ATH_DBG_FATAL,
 915                           "Couldn't reset chip\n");
 916                 return -EIO;
 917         }
 918
 919         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 920                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 921                 return -EIO;
 922         }
 923
 924         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 925                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 926                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 927                         ah->config.serialize_regmode =
 928                                 SER_REG_MODE_ON;
 929                 } else {
 930                         ah->config.serialize_regmode =
 931                                 SER_REG_MODE_OFF;
 932                 }
 933         }
 934
 935         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 936                 ah->config.serialize_regmode);
 937
 938         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 939                 ath_print(common, ATH_DBG_FATAL,
 940                           "Mac Chip Rev 0x%02x.%x is not supported by "
 941                           "this driver\n", ah->hw_version.macVersion,
 942                           ah->hw_version.macRev);
 943                 return -EOPNOTSUPP;
 944         }
 945
 946         if (AR_SREV_9100(ah)) {
 947                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 948                 ah->supp_cals = IQ_MISMATCH_CAL;
 949                 ah->is_pciexpress = false;
 950         }
 951
 952         if (AR_SREV_9271(ah))
 953                 ah->is_pciexpress = false;
 954
 955         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 956
 957         ath9k_hw_init_cal_settings(ah);
 958
 959         ah->ani_function = ATH9K_ANI_ALL;
 960         if (AR_SREV_9280_10_OR_LATER(ah))
 961                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 962
 963         ath9k_hw_init_mode_regs(ah);
 964
 965         if (ah->is_pciexpress)
 966                 ath9k_hw_configpcipowersave(ah, 0, 0);
 967         else
 968                 ath9k_hw_disablepcie(ah);
 969
 970         /* Support for Japan ch.14 (2484) spread */
 971         if (AR_SREV_9287_11_OR_LATER(ah)) {
 972                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 973                        ar9287Common_normal_cck_fir_coeff_92871_1,
 974                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 975                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 976                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 977                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 978         }
 979
 980         r = ath9k_hw_post_init(ah);
 981         if (r)
 982                 return r;
 983
 984         ath9k_hw_init_mode_gain_regs(ah);
 985         ath9k_hw_fill_cap_info(ah);
 986         ath9k_hw_init_11a_eeprom_fix(ah);
 987
 988         r = ath9k_hw_init_macaddr(ah);
 989         if (r) {
 990                 ath_print(common, ATH_DBG_FATAL,
 991                           "Failed to initialize MAC address\n");
 992                 return r;
 993         }
 994
 995         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 996                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 997         else
 998                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 999
1000         ath9k_init_nfcal_hist_buffer(ah);
1001
1002         common->state = ATH_HW_INITIALIZED;
1003
1004         return 0;
1005 }
1006
1007 static void ath9k_hw_init_bb(struct ath_hw *ah,
1008                              struct ath9k_channel *chan)
1009 {
1010         u32 synthDelay;
1011
1012         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1013         if (IS_CHAN_B(chan))
1014                 synthDelay = (4 * synthDelay) / 22;
1015         else
1016                 synthDelay /= 10;
1017
1018         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1019
1020         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1021 }
1022
1023 static void ath9k_hw_init_qos(struct ath_hw *ah)
1024 {
1025         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1026         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1027
1028         REG_WRITE(ah, AR_QOS_NO_ACK,
1029                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1030                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1031                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1032
1033         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1034         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1035         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1036         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1037         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1038 }
1039
1040 static void ath9k_hw_init_pll(struct ath_hw *ah,
1041                               struct ath9k_channel *chan)
1042 {
1043         u32 pll;
1044
1045         if (AR_SREV_9100(ah)) {
1046                 if (chan && IS_CHAN_5GHZ(chan))
1047                         pll = 0x1450;
1048                 else
1049                         pll = 0x1458;
1050         } else {
1051                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1052                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1053
1054                         if (chan && IS_CHAN_HALF_RATE(chan))
1055                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1056                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1057                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1058
1059                         if (chan && IS_CHAN_5GHZ(chan)) {
1060                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1061
1062
1063                                 if (AR_SREV_9280_20(ah)) {
1064                                         if (((chan->channel % 20) == 0)
1065                                             || ((chan->channel % 10) == 0))
1066                                                 pll = 0x2850;
1067                                         else
1068                                                 pll = 0x142c;
1069                                 }
1070                         } else {
1071                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1072                         }
1073
1074                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1075
1076                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1077
1078                         if (chan && IS_CHAN_HALF_RATE(chan))
1079                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1080                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1081                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1082
1083                         if (chan && IS_CHAN_5GHZ(chan))
1084                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1085                         else
1086                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1087                 } else {
1088                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1089
1090                         if (chan && IS_CHAN_HALF_RATE(chan))
1091                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1092                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1093                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1094
1095                         if (chan && IS_CHAN_5GHZ(chan))
1096                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1097                         else
1098                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1099                 }
1100         }
1101         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1102
1103         udelay(RTC_PLL_SETTLE_DELAY);
1104
1105         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1106 }
1107
1108 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1109 {
1110         int rx_chainmask, tx_chainmask;
1111
1112         rx_chainmask = ah->rxchainmask;
1113         tx_chainmask = ah->txchainmask;
1114
1115         switch (rx_chainmask) {
1116         case 0x5:
1117                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1118                             AR_PHY_SWAP_ALT_CHAIN);
1119         case 0x3:
1120                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1121                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1122                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1123                         break;
1124                 }
1125         case 0x1:
1126         case 0x2:
1127         case 0x7:
1128                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1129                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1130                 break;
1131         default:
1132                 break;
1133         }
1134
1135         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1136         if (tx_chainmask == 0x5) {
1137                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1138                             AR_PHY_SWAP_ALT_CHAIN);
1139         }
1140         if (AR_SREV_9100(ah))
1141                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1142                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1143 }
1144
1145 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1146                                           enum nl80211_iftype opmode)
1147 {
1148         ah->mask_reg = AR_IMR_TXERR |
1149                 AR_IMR_TXURN |
1150                 AR_IMR_RXERR |
1151                 AR_IMR_RXORN |
1152                 AR_IMR_BCNMISC;
1153
1154         if (ah->config.intr_mitigation)
1155                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1156         else
1157                 ah->mask_reg |= AR_IMR_RXOK;
1158
1159         ah->mask_reg |= AR_IMR_TXOK;
1160
1161         if (opmode == NL80211_IFTYPE_AP)
1162                 ah->mask_reg |= AR_IMR_MIB;
1163
1164         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1165         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1166
1167         if (!AR_SREV_9100(ah)) {
1168                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1169                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1170                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1171         }
1172 }
1173
1174 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1175 {
1176         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1177                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1178                           "bad ack timeout %u\n", us);
1179                 ah->acktimeout = (u32) -1;
1180                 return false;
1181         } else {
1182                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1183                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1184                 ah->acktimeout = us;
1185                 return true;
1186         }
1187 }
1188
1189 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1190 {
1191         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1192                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1193                           "bad cts timeout %u\n", us);
1194                 ah->ctstimeout = (u32) -1;
1195                 return false;
1196         } else {
1197                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1198                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1199                 ah->ctstimeout = us;
1200                 return true;
1201         }
1202 }
1203
1204 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1205 {
1206         if (tu > 0xFFFF) {
1207                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1208                           "bad global tx timeout %u\n", tu);
1209                 ah->globaltxtimeout = (u32) -1;
1210                 return false;
1211         } else {
1212                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1213                 ah->globaltxtimeout = tu;
1214                 return true;
1215         }
1216 }
1217
1218 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1219 {
1220         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1221                   ah->misc_mode);
1222
1223         if (ah->misc_mode != 0)
1224                 REG_WRITE(ah, AR_PCU_MISC,
1225                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1226         if (ah->slottime != (u32) -1)
1227                 ath9k_hw_setslottime(ah, ah->slottime);
1228         if (ah->acktimeout != (u32) -1)
1229                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1230         if (ah->ctstimeout != (u32) -1)
1231                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1232         if (ah->globaltxtimeout != (u32) -1)
1233                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1234 }
1235
1236 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1237 {
1238         return vendorid == ATHEROS_VENDOR_ID ?
1239                 ath9k_hw_devname(devid) : NULL;
1240 }
1241
1242 void ath9k_hw_detach(struct ath_hw *ah)
1243 {
1244         struct ath_common *common = ath9k_hw_common(ah);
1245
1246         if (common->state <= ATH_HW_INITIALIZED)
1247                 goto free_hw;
1248
1249         if (!AR_SREV_9100(ah))
1250                 ath9k_hw_ani_disable(ah);
1251
1252         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1253
1254 free_hw:
1255         ath9k_hw_rf_free(ah);
1256         kfree(ah);
1257         ah = NULL;
1258 }
1259 EXPORT_SYMBOL(ath9k_hw_detach);
1260
1261 /*******/
1262 /* INI */
1263 /*******/
1264
1265 static void ath9k_hw_override_ini(struct ath_hw *ah,
1266                                   struct ath9k_channel *chan)
1267 {
1268         u32 val;
1269
1270         if (AR_SREV_9271(ah)) {
1271                 /*
1272                  * Enable spectral scan to solution for issues with stuck
1273                  * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1274                  * AR9271 1.1
1275                  */
1276                 if (AR_SREV_9271_10(ah)) {
1277                         val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1278                         REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1279                 }
1280                 else if (AR_SREV_9271_11(ah))
1281                         /*
1282                          * change AR_PHY_RF_CTL3 setting to fix MAC issue
1283                          * present on AR9271 1.1
1284                          */
1285                         REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1286                 return;
1287         }
1288
1289         /*
1290          * Set the RX_ABORT and RX_DIS and clear if off only after
1291          * RXE is set for MAC. This prevents frames with corrupted
1292          * descriptor status.
1293          */
1294         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1295
1296         if (AR_SREV_9280_10_OR_LATER(ah)) {
1297                 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1298                                (~AR_PCU_MISC_MODE2_HWWAR1);
1299
1300                 if (AR_SREV_9287_10_OR_LATER(ah))
1301                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1302
1303                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1304         }
1305
1306         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1307             AR_SREV_9280_10_OR_LATER(ah))
1308                 return;
1309         /*
1310          * Disable BB clock gating
1311          * Necessary to avoid issues on AR5416 2.0
1312          */
1313         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1314 }
1315
1316 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1317                               struct ar5416_eeprom_def *pEepData,
1318                               u32 reg, u32 value)
1319 {
1320         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1321         struct ath_common *common = ath9k_hw_common(ah);
1322
1323         switch (ah->hw_version.devid) {
1324         case AR9280_DEVID_PCI:
1325                 if (reg == 0x7894) {
1326                         ath_print(common, ATH_DBG_EEPROM,
1327                                 "ini VAL: %x  EEPROM: %x\n", value,
1328                                 (pBase->version & 0xff));
1329
1330                         if ((pBase->version & 0xff) > 0x0a) {
1331                                 ath_print(common, ATH_DBG_EEPROM,
1332                                           "PWDCLKIND: %d\n",
1333                                           pBase->pwdclkind);
1334                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1335                                 value |= AR_AN_TOP2_PWDCLKIND &
1336                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1337                         } else {
1338                                 ath_print(common, ATH_DBG_EEPROM,
1339                                           "PWDCLKIND Earlier Rev\n");
1340                         }
1341
1342                         ath_print(common, ATH_DBG_EEPROM,
1343                                   "final ini VAL: %x\n", value);
1344                 }
1345                 break;
1346         }
1347
1348         return value;
1349 }
1350
1351 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1352                               struct ar5416_eeprom_def *pEepData,
1353                               u32 reg, u32 value)
1354 {
1355         if (ah->eep_map == EEP_MAP_4KBITS)
1356                 return value;
1357         else
1358                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1359 }
1360
1361 static void ath9k_olc_init(struct ath_hw *ah)
1362 {
1363         u32 i;
1364
1365         if (OLC_FOR_AR9287_10_LATER) {
1366                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1367                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1368                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1369                                 AR9287_AN_TXPC0_TXPCMODE,
1370                                 AR9287_AN_TXPC0_TXPCMODE_S,
1371                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1372                 udelay(100);
1373         } else {
1374                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1375                         ah->originalGain[i] =
1376                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1377                                                 AR_PHY_TX_GAIN);
1378                 ah->PDADCdelta = 0;
1379         }
1380 }
1381
1382 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1383                               struct ath9k_channel *chan)
1384 {
1385         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1386
1387         if (IS_CHAN_B(chan))
1388                 ctl |= CTL_11B;
1389         else if (IS_CHAN_G(chan))
1390                 ctl |= CTL_11G;
1391         else
1392                 ctl |= CTL_11A;
1393
1394         return ctl;
1395 }
1396
1397 static int ath9k_hw_process_ini(struct ath_hw *ah,
1398                                 struct ath9k_channel *chan)
1399 {
1400         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1401         int i, regWrites = 0;
1402         struct ieee80211_channel *channel = chan->chan;
1403         u32 modesIndex, freqIndex;
1404
1405         switch (chan->chanmode) {
1406         case CHANNEL_A:
1407         case CHANNEL_A_HT20:
1408                 modesIndex = 1;
1409                 freqIndex = 1;
1410                 break;
1411         case CHANNEL_A_HT40PLUS:
1412         case CHANNEL_A_HT40MINUS:
1413                 modesIndex = 2;
1414                 freqIndex = 1;
1415                 break;
1416         case CHANNEL_G:
1417         case CHANNEL_G_HT20:
1418         case CHANNEL_B:
1419                 modesIndex = 4;
1420                 freqIndex = 2;
1421                 break;
1422         case CHANNEL_G_HT40PLUS:
1423         case CHANNEL_G_HT40MINUS:
1424                 modesIndex = 3;
1425                 freqIndex = 2;
1426                 break;
1427
1428         default:
1429                 return -EINVAL;
1430         }
1431
1432         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1433         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1434         ah->eep_ops->set_addac(ah, chan);
1435
1436         if (AR_SREV_5416_22_OR_LATER(ah)) {
1437                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1438         } else {
1439                 struct ar5416IniArray temp;
1440                 u32 addacSize =
1441                         sizeof(u32) * ah->iniAddac.ia_rows *
1442                         ah->iniAddac.ia_columns;
1443
1444                 memcpy(ah->addac5416_21,
1445                        ah->iniAddac.ia_array, addacSize);
1446
1447                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1448
1449                 temp.ia_array = ah->addac5416_21;
1450                 temp.ia_columns = ah->iniAddac.ia_columns;
1451                 temp.ia_rows = ah->iniAddac.ia_rows;
1452                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1453         }
1454
1455         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1456
1457         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1458                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1459                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1460
1461                 REG_WRITE(ah, reg, val);
1462
1463                 if (reg >= 0x7800 && reg < 0x78a0
1464                     && ah->config.analog_shiftreg) {
1465                         udelay(100);
1466                 }
1467
1468                 DO_DELAY(regWrites);
1469         }
1470
1471         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1472                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1473
1474         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1475             AR_SREV_9287_10_OR_LATER(ah))
1476                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1477
1478         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1479                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1480                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1481
1482                 REG_WRITE(ah, reg, val);
1483
1484                 if (reg >= 0x7800 && reg < 0x78a0
1485                     && ah->config.analog_shiftreg) {
1486                         udelay(100);
1487                 }
1488
1489                 DO_DELAY(regWrites);
1490         }
1491
1492         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1493
1494         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1495                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1496                                 regWrites);
1497         }
1498
1499         ath9k_hw_override_ini(ah, chan);
1500         ath9k_hw_set_regs(ah, chan);
1501         ath9k_hw_init_chain_masks(ah);
1502
1503         if (OLC_FOR_AR9280_20_LATER)
1504                 ath9k_olc_init(ah);
1505
1506         ah->eep_ops->set_txpower(ah, chan,
1507                                  ath9k_regd_get_ctl(regulatory, chan),
1508                                  channel->max_antenna_gain * 2,
1509                                  channel->max_power * 2,
1510                                  min((u32) MAX_RATE_POWER,
1511                                  (u32) regulatory->power_limit));
1512
1513         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1514                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1515                           "ar5416SetRfRegs failed\n");
1516                 return -EIO;
1517         }
1518
1519         return 0;
1520 }
1521
1522 /****************************************/
1523 /* Reset and Channel Switching Routines */
1524 /****************************************/
1525
1526 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1527 {
1528         u32 rfMode = 0;
1529
1530         if (chan == NULL)
1531                 return;
1532
1533         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1534                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1535
1536         if (!AR_SREV_9280_10_OR_LATER(ah))
1537                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1538                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1539
1540         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1541                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1542
1543         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1544 }
1545
1546 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1547 {
1548         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1549 }
1550
1551 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1552 {
1553         u32 regval;
1554
1555         /*
1556          * set AHB_MODE not to do cacheline prefetches
1557         */
1558         regval = REG_READ(ah, AR_AHB_MODE);
1559         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1560
1561         /*
1562          * let mac dma reads be in 128 byte chunks
1563          */
1564         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1565         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1566
1567         /*
1568          * Restore TX Trigger Level to its pre-reset value.
1569          * The initial value depends on whether aggregation is enabled, and is
1570          * adjusted whenever underruns are detected.
1571          */
1572         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1573
1574         /*
1575          * let mac dma writes be in 128 byte chunks
1576          */
1577         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1578         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1579
1580         /*
1581          * Setup receive FIFO threshold to hold off TX activities
1582          */
1583         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1584
1585         /*
1586          * reduce the number of usable entries in PCU TXBUF to avoid
1587          * wrap around issues.
1588          */
1589         if (AR_SREV_9285(ah)) {
1590                 /* For AR9285 the number of Fifos are reduced to half.
1591                  * So set the usable tx buf size also to half to
1592                  * avoid data/delimiter underruns
1593                  */
1594                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1595                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1596         } else if (!AR_SREV_9271(ah)) {
1597                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1598                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1599         }
1600 }
1601
1602 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1603 {
1604         u32 val;
1605
1606         val = REG_READ(ah, AR_STA_ID1);
1607         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1608         switch (opmode) {
1609         case NL80211_IFTYPE_AP:
1610                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1611                           | AR_STA_ID1_KSRCH_MODE);
1612                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1613                 break;
1614         case NL80211_IFTYPE_ADHOC:
1615         case NL80211_IFTYPE_MESH_POINT:
1616                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1617                           | AR_STA_ID1_KSRCH_MODE);
1618                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1619                 break;
1620         case NL80211_IFTYPE_STATION:
1621         case NL80211_IFTYPE_MONITOR:
1622                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1623                 break;
1624         }
1625 }
1626
1627 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1628                                                  u32 coef_scaled,
1629                                                  u32 *coef_mantissa,
1630                                                  u32 *coef_exponent)
1631 {
1632         u32 coef_exp, coef_man;
1633
1634         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1635                 if ((coef_scaled >> coef_exp) & 0x1)
1636                         break;
1637
1638         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1639
1640         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1641
1642         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1643         *coef_exponent = coef_exp - 16;
1644 }
1645
1646 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1647                                      struct ath9k_channel *chan)
1648 {
1649         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1650         u32 clockMhzScaled = 0x64000000;
1651         struct chan_centers centers;
1652
1653         if (IS_CHAN_HALF_RATE(chan))
1654                 clockMhzScaled = clockMhzScaled >> 1;
1655         else if (IS_CHAN_QUARTER_RATE(chan))
1656                 clockMhzScaled = clockMhzScaled >> 2;
1657
1658         ath9k_hw_get_channel_centers(ah, chan, &centers);
1659         coef_scaled = clockMhzScaled / centers.synth_center;
1660
1661         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1662                                       &ds_coef_exp);
1663
1664         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1665                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1666         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1667                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1668
1669         coef_scaled = (9 * coef_scaled) / 10;
1670
1671         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1672                                       &ds_coef_exp);
1673
1674         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1675                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1676         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1677                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1678 }
1679
1680 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1681 {
1682         u32 rst_flags;
1683         u32 tmpReg;
1684
1685         if (AR_SREV_9100(ah)) {
1686                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1687                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1688                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1689                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1690                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1691         }
1692
1693         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1694                   AR_RTC_FORCE_WAKE_ON_INT);
1695
1696         if (AR_SREV_9100(ah)) {
1697                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1698                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1699         } else {
1700                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1701                 if (tmpReg &
1702                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1703                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1704                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1705                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1706                 } else {
1707                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1708                 }
1709
1710                 rst_flags = AR_RTC_RC_MAC_WARM;
1711                 if (type == ATH9K_RESET_COLD)
1712                         rst_flags |= AR_RTC_RC_MAC_COLD;
1713         }
1714
1715         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1716         udelay(50);
1717
1718         REG_WRITE(ah, AR_RTC_RC, 0);
1719         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1720                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1721                           "RTC stuck in MAC reset\n");
1722                 return false;
1723         }
1724
1725         if (!AR_SREV_9100(ah))
1726                 REG_WRITE(ah, AR_RC, 0);
1727
1728         if (AR_SREV_9100(ah))
1729                 udelay(50);
1730
1731         return true;
1732 }
1733
1734 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1735 {
1736         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1737                   AR_RTC_FORCE_WAKE_ON_INT);
1738
1739         if (!AR_SREV_9100(ah))
1740                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1741
1742         REG_WRITE(ah, AR_RTC_RESET, 0);
1743         udelay(2);
1744
1745         if (!AR_SREV_9100(ah))
1746                 REG_WRITE(ah, AR_RC, 0);
1747
1748         REG_WRITE(ah, AR_RTC_RESET, 1);
1749
1750         if (!ath9k_hw_wait(ah,
1751                            AR_RTC_STATUS,
1752                            AR_RTC_STATUS_M,
1753                            AR_RTC_STATUS_ON,
1754                            AH_WAIT_TIMEOUT)) {
1755                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1756                           "RTC not waking up\n");
1757                 return false;
1758         }
1759
1760         ath9k_hw_read_revisions(ah);
1761
1762         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1763 }
1764
1765 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1766 {
1767         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1768                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1769
1770         switch (type) {
1771         case ATH9K_RESET_POWER_ON:
1772                 return ath9k_hw_set_reset_power_on(ah);
1773         case ATH9K_RESET_WARM:
1774         case ATH9K_RESET_COLD:
1775                 return ath9k_hw_set_reset(ah, type);
1776         default:
1777                 return false;
1778         }
1779 }
1780
1781 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1782 {
1783         u32 phymode;
1784         u32 enableDacFifo = 0;
1785
1786         if (AR_SREV_9285_10_OR_LATER(ah))
1787                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1788                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1789
1790         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1791                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1792
1793         if (IS_CHAN_HT40(chan)) {
1794                 phymode |= AR_PHY_FC_DYN2040_EN;
1795
1796                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1797                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1798                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1799
1800         }
1801         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1802
1803         ath9k_hw_set11nmac2040(ah);
1804
1805         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1806         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1807 }
1808
1809 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1810                                 struct ath9k_channel *chan)
1811 {
1812         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1813                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1814                         return false;
1815         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1816                 return false;
1817
1818         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1819                 return false;
1820
1821         ah->chip_fullsleep = false;
1822         ath9k_hw_init_pll(ah, chan);
1823         ath9k_hw_set_rfmode(ah, chan);
1824
1825         return true;
1826 }
1827
1828 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1829                                     struct ath9k_channel *chan)
1830 {
1831         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1832         struct ath_common *common = ath9k_hw_common(ah);
1833         struct ieee80211_channel *channel = chan->chan;
1834         u32 synthDelay, qnum;
1835
1836         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1837                 if (ath9k_hw_numtxpending(ah, qnum)) {
1838                         ath_print(common, ATH_DBG_QUEUE,
1839                                   "Transmit frames pending on "
1840                                   "queue %d\n", qnum);
1841                         return false;
1842                 }
1843         }
1844
1845         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1846         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1847                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1848                 ath_print(common, ATH_DBG_FATAL,
1849                           "Could not kill baseband RX\n");
1850                 return false;
1851         }
1852
1853         ath9k_hw_set_regs(ah, chan);
1854
1855         if (AR_SREV_9280_10_OR_LATER(ah)) {
1856                 ath9k_hw_ar9280_set_channel(ah, chan);
1857         } else {
1858                 if (!(ath9k_hw_set_channel(ah, chan))) {
1859                         ath_print(common, ATH_DBG_FATAL,
1860                                   "Failed to set channel\n");
1861                         return false;
1862                 }
1863         }
1864
1865         ah->eep_ops->set_txpower(ah, chan,
1866                              ath9k_regd_get_ctl(regulatory, chan),
1867                              channel->max_antenna_gain * 2,
1868                              channel->max_power * 2,
1869                              min((u32) MAX_RATE_POWER,
1870                              (u32) regulatory->power_limit));
1871
1872         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1873         if (IS_CHAN_B(chan))
1874                 synthDelay = (4 * synthDelay) / 22;
1875         else
1876                 synthDelay /= 10;
1877
1878         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1879
1880         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1881
1882         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1883                 ath9k_hw_set_delta_slope(ah, chan);
1884
1885         if (AR_SREV_9280_10_OR_LATER(ah))
1886                 ath9k_hw_9280_spur_mitigate(ah, chan);
1887         else
1888                 ath9k_hw_spur_mitigate(ah, chan);
1889
1890         if (!chan->oneTimeCalsDone)
1891                 chan->oneTimeCalsDone = true;
1892
1893         return true;
1894 }
1895
1896 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1897 {
1898         int bb_spur = AR_NO_SPUR;
1899         int freq;
1900         int bin, cur_bin;
1901         int bb_spur_off, spur_subchannel_sd;
1902         int spur_freq_sd;
1903         int spur_delta_phase;
1904         int denominator;
1905         int upper, lower, cur_vit_mask;
1906         int tmp, newVal;
1907         int i;
1908         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1909                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1910         };
1911         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1912                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1913         };
1914         int inc[4] = { 0, 100, 0, 0 };
1915         struct chan_centers centers;
1916
1917         int8_t mask_m[123];
1918         int8_t mask_p[123];
1919         int8_t mask_amt;
1920         int tmp_mask;
1921         int cur_bb_spur;
1922         bool is2GHz = IS_CHAN_2GHZ(chan);
1923
1924         memset(&mask_m, 0, sizeof(int8_t) * 123);
1925         memset(&mask_p, 0, sizeof(int8_t) * 123);
1926
1927         ath9k_hw_get_channel_centers(ah, chan, &centers);
1928         freq = centers.synth_center;
1929
1930         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1931         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1932                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1933
1934                 if (is2GHz)
1935                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1936                 else
1937                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1938
1939                 if (AR_NO_SPUR == cur_bb_spur)
1940                         break;
1941                 cur_bb_spur = cur_bb_spur - freq;
1942
1943                 if (IS_CHAN_HT40(chan)) {
1944                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1945                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1946                                 bb_spur = cur_bb_spur;
1947                                 break;
1948                         }
1949                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1950                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1951                         bb_spur = cur_bb_spur;
1952                         break;
1953                 }
1954         }
1955
1956         if (AR_NO_SPUR == bb_spur) {
1957                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1958                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1959                 return;
1960         } else {
1961                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1962                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1963         }
1964
1965         bin = bb_spur * 320;
1966
1967         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1968
1969         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1970                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1971                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1972                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1973         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1974
1975         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1976                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1977                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1978                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1979                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1980         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1981
1982         if (IS_CHAN_HT40(chan)) {
1983                 if (bb_spur < 0) {
1984                         spur_subchannel_sd = 1;
1985                         bb_spur_off = bb_spur + 10;
1986                 } else {
1987                         spur_subchannel_sd = 0;
1988                         bb_spur_off = bb_spur - 10;
1989                 }
1990         } else {
1991                 spur_subchannel_sd = 0;
1992                 bb_spur_off = bb_spur;
1993         }
1994
1995         if (IS_CHAN_HT40(chan))
1996                 spur_delta_phase =
1997                         ((bb_spur * 262144) /
1998                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1999         else
2000                 spur_delta_phase =
2001                         ((bb_spur * 524288) /
2002                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2003
2004         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
2005         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
2006
2007         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2008                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2009                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2010         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
2011
2012         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
2013         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2014
2015         cur_bin = -6000;
2016         upper = bin + 100;
2017         lower = bin - 100;
2018
2019         for (i = 0; i < 4; i++) {
2020                 int pilot_mask = 0;
2021                 int chan_mask = 0;
2022                 int bp = 0;
2023                 for (bp = 0; bp < 30; bp++) {
2024                         if ((cur_bin > lower) && (cur_bin < upper)) {
2025                                 pilot_mask = pilot_mask | 0x1 << bp;
2026                                 chan_mask = chan_mask | 0x1 << bp;
2027                         }
2028                         cur_bin += 100;
2029                 }
2030                 cur_bin += inc[i];
2031                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2032                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2033         }
2034
2035         cur_vit_mask = 6100;
2036         upper = bin + 120;
2037         lower = bin - 120;
2038
2039         for (i = 0; i < 123; i++) {
2040                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2041
2042                         /* workaround for gcc bug #37014 */
2043                         volatile int tmp_v = abs(cur_vit_mask - bin);
2044
2045                         if (tmp_v < 75)
2046                                 mask_amt = 1;
2047                         else
2048                                 mask_amt = 0;
2049                         if (cur_vit_mask < 0)
2050                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2051                         else
2052                                 mask_p[cur_vit_mask / 100] = mask_amt;
2053                 }
2054                 cur_vit_mask -= 100;
2055         }
2056
2057         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2058                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2059                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2060                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2061                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2062                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2063                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2064                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2065         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2066         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2067
2068         tmp_mask = (mask_m[31] << 28)
2069                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2070                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2071                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2072                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2073                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2074                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2075                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2076         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2077         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2078
2079         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2080                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2081                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2082                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2083                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2084                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2085                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2086                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2087         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2088         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2089
2090         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2091                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2092                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2093                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2094                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2095                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2096                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2097                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2098         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2099         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2100
2101         tmp_mask = (mask_p[15] << 28)
2102                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2103                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2104                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2105                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2106                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2107                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2108                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2109         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2110         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2111
2112         tmp_mask = (mask_p[30] << 28)
2113                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2114                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2115                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2116                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2117                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2118                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2119                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2120         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2121         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2122
2123         tmp_mask = (mask_p[45] << 28)
2124                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2125                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2126                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2127                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2128                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2129                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2130                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2131         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2132         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2133
2134         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2135                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2136                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2137                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2138                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2139                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2140                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2141                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2142         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2143         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2144 }
2145
2146 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2147 {
2148         int bb_spur = AR_NO_SPUR;
2149         int bin, cur_bin;
2150         int spur_freq_sd;
2151         int spur_delta_phase;
2152         int denominator;
2153         int upper, lower, cur_vit_mask;
2154         int tmp, new;
2155         int i;
2156         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2157                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2158         };
2159         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2160                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2161         };
2162         int inc[4] = { 0, 100, 0, 0 };
2163
2164         int8_t mask_m[123];
2165         int8_t mask_p[123];
2166         int8_t mask_amt;
2167         int tmp_mask;
2168         int cur_bb_spur;
2169         bool is2GHz = IS_CHAN_2GHZ(chan);
2170
2171         memset(&mask_m, 0, sizeof(int8_t) * 123);
2172         memset(&mask_p, 0, sizeof(int8_t) * 123);
2173
2174         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2175                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2176                 if (AR_NO_SPUR == cur_bb_spur)
2177                         break;
2178                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2179                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2180                         bb_spur = cur_bb_spur;
2181                         break;
2182                 }
2183         }
2184
2185         if (AR_NO_SPUR == bb_spur)
2186                 return;
2187
2188         bin = bb_spur * 32;
2189
2190         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2191         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2192                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2193                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2194                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2195
2196         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2197
2198         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2199                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2200                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2201                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2202                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2203         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2204
2205         spur_delta_phase = ((bb_spur * 524288) / 100) &
2206                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2207
2208         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2209         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2210
2211         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2212                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2213                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2214         REG_WRITE(ah, AR_PHY_TIMING11, new);
2215
2216         cur_bin = -6000;
2217         upper = bin + 100;
2218         lower = bin - 100;
2219
2220         for (i = 0; i < 4; i++) {
2221                 int pilot_mask = 0;
2222                 int chan_mask = 0;
2223                 int bp = 0;
2224                 for (bp = 0; bp < 30; bp++) {
2225                         if ((cur_bin > lower) && (cur_bin < upper)) {
2226                                 pilot_mask = pilot_mask | 0x1 << bp;
2227                                 chan_mask = chan_mask | 0x1 << bp;
2228                         }
2229                         cur_bin += 100;
2230                 }
2231                 cur_bin += inc[i];
2232                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2233                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2234         }
2235
2236         cur_vit_mask = 6100;
2237         upper = bin + 120;
2238         lower = bin - 120;
2239
2240         for (i = 0; i < 123; i++) {
2241                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2242
2243                         /* workaround for gcc bug #37014 */
2244                         volatile int tmp_v = abs(cur_vit_mask - bin);
2245
2246                         if (tmp_v < 75)
2247                                 mask_amt = 1;
2248                         else
2249                                 mask_amt = 0;
2250                         if (cur_vit_mask < 0)
2251                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2252                         else
2253                                 mask_p[cur_vit_mask / 100] = mask_amt;
2254                 }
2255                 cur_vit_mask -= 100;
2256         }
2257
2258         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2259                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2260                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2261                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2262                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2263                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2264                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2265                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2266         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2267         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2268
2269         tmp_mask = (mask_m[31] << 28)
2270                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2271                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2272                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2273                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2274                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2275                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2276                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2277         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2278         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2279
2280         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2281                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2282                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2283                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2284                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2285                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2286                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2287                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2288         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2289         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2290
2291         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2292                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2293                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2294                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2295                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2296                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2297                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2298                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2299         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2300         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2301
2302         tmp_mask = (mask_p[15] << 28)
2303                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2304                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2305                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2306                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2307                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2308                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2309                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2310         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2311         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2312
2313         tmp_mask = (mask_p[30] << 28)
2314                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2315                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2316                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2317                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2318                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2319                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2320                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2321         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2322         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2323
2324         tmp_mask = (mask_p[45] << 28)
2325                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2326                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2327                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2328                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2329                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2330                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2331                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2332         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2333         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2334
2335         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2336                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2337                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2338                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2339                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2340                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2341                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2342                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2343         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2344         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2345 }
2346
2347 static void ath9k_enable_rfkill(struct ath_hw *ah)
2348 {
2349         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2350                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2351
2352         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2353                     AR_GPIO_INPUT_MUX2_RFSILENT);
2354
2355         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2356         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2357 }
2358
2359 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2360                     bool bChannelChange)
2361 {
2362         struct ath_common *common = ath9k_hw_common(ah);
2363         u32 saveLedState;
2364         struct ath9k_channel *curchan = ah->curchan;
2365         u32 saveDefAntenna;
2366         u32 macStaId1;
2367         u64 tsf = 0;
2368         int i, rx_chainmask, r;
2369
2370         ah->txchainmask = common->tx_chainmask;
2371         ah->rxchainmask = common->rx_chainmask;
2372
2373         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2374                 return -EIO;
2375
2376         if (curchan && !ah->chip_fullsleep)
2377                 ath9k_hw_getnf(ah, curchan);
2378
2379         if (bChannelChange &&
2380             (ah->chip_fullsleep != true) &&
2381             (ah->curchan != NULL) &&
2382             (chan->channel != ah->curchan->channel) &&
2383             ((chan->channelFlags & CHANNEL_ALL) ==
2384              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2385              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2386              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2387
2388                 if (ath9k_hw_channel_change(ah, chan)) {
2389                         ath9k_hw_loadnf(ah, ah->curchan);
2390                         ath9k_hw_start_nfcal(ah);
2391                         return 0;
2392                 }
2393         }
2394
2395         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2396         if (saveDefAntenna == 0)
2397                 saveDefAntenna = 1;
2398
2399         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2400
2401         /* For chips on which RTC reset is done, save TSF before it gets cleared */
2402         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2403                 tsf = ath9k_hw_gettsf64(ah);
2404
2405         saveLedState = REG_READ(ah, AR_CFG_LED) &
2406                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2407                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2408
2409         ath9k_hw_mark_phy_inactive(ah);
2410
2411         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2412                 REG_WRITE(ah,
2413                           AR9271_RESET_POWER_DOWN_CONTROL,
2414                           AR9271_RADIO_RF_RST);
2415                 udelay(50);
2416         }
2417
2418         if (!ath9k_hw_chip_reset(ah, chan)) {
2419                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2420                 return -EINVAL;
2421         }
2422
2423         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2424                 ah->htc_reset_init = false;
2425                 REG_WRITE(ah,
2426                           AR9271_RESET_POWER_DOWN_CONTROL,
2427                           AR9271_GATE_MAC_CTL);
2428                 udelay(50);
2429         }
2430
2431         /* Restore TSF */
2432         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2433                 ath9k_hw_settsf64(ah, tsf);
2434
2435         if (AR_SREV_9280_10_OR_LATER(ah))
2436                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2437
2438         if (AR_SREV_9287_12_OR_LATER(ah)) {
2439                 /* Enable ASYNC FIFO */
2440                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2441                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2442                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2443                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2444                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2445                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2446                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2447         }
2448         r = ath9k_hw_process_ini(ah, chan);
2449         if (r)
2450                 return r;
2451
2452         /* Setup MFP options for CCMP */
2453         if (AR_SREV_9280_20_OR_LATER(ah)) {
2454                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2455                  * frames when constructing CCMP AAD. */
2456                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2457                               0xc7ff);
2458                 ah->sw_mgmt_crypto = false;
2459         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2460                 /* Disable hardware crypto for management frames */
2461                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2462                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2463                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2464                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2465                 ah->sw_mgmt_crypto = true;
2466         } else
2467                 ah->sw_mgmt_crypto = true;
2468
2469         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2470                 ath9k_hw_set_delta_slope(ah, chan);
2471
2472         if (AR_SREV_9280_10_OR_LATER(ah))
2473                 ath9k_hw_9280_spur_mitigate(ah, chan);
2474         else
2475                 ath9k_hw_spur_mitigate(ah, chan);
2476
2477         ah->eep_ops->set_board_values(ah, chan);
2478
2479         ath9k_hw_decrease_chain_power(ah, chan);
2480
2481         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2482         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2483                   | macStaId1
2484                   | AR_STA_ID1_RTS_USE_DEF
2485                   | (ah->config.
2486                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2487                   | ah->sta_id1_defaults);
2488         ath9k_hw_set_operating_mode(ah, ah->opmode);
2489
2490         ath_hw_setbssidmask(common);
2491
2492         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2493
2494         ath9k_hw_write_associd(ah);
2495
2496         REG_WRITE(ah, AR_ISR, ~0);
2497
2498         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2499
2500         if (AR_SREV_9280_10_OR_LATER(ah))
2501                 ath9k_hw_ar9280_set_channel(ah, chan);
2502         else
2503                 if (!(ath9k_hw_set_channel(ah, chan)))
2504                         return -EIO;
2505
2506         for (i = 0; i < AR_NUM_DCU; i++)
2507                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2508
2509         ah->intr_txqs = 0;
2510         for (i = 0; i < ah->caps.total_queues; i++)
2511                 ath9k_hw_resettxqueue(ah, i);
2512
2513         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2514         ath9k_hw_init_qos(ah);
2515
2516         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2517                 ath9k_enable_rfkill(ah);
2518
2519         ath9k_hw_init_user_settings(ah);
2520
2521         if (AR_SREV_9287_12_OR_LATER(ah)) {
2522                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2523                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2524                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2525                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2526                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2527                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2528
2529                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2530                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2531
2532                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2533                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2534                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2535                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2536         }
2537         if (AR_SREV_9287_12_OR_LATER(ah)) {
2538                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2539                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2540         }
2541
2542         REG_WRITE(ah, AR_STA_ID1,
2543                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2544
2545         ath9k_hw_set_dma(ah);
2546
2547         REG_WRITE(ah, AR_OBS, 8);
2548
2549         if (ah->config.intr_mitigation) {
2550                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2551                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2552         }
2553
2554         ath9k_hw_init_bb(ah, chan);
2555
2556         if (!ath9k_hw_init_cal(ah, chan))
2557                 return -EIO;
2558
2559         rx_chainmask = ah->rxchainmask;
2560         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2561                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2562                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2563         }
2564
2565         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2566
2567         /*
2568          * For big endian systems turn on swapping for descriptors
2569          */
2570         if (AR_SREV_9100(ah)) {
2571                 u32 mask;
2572                 mask = REG_READ(ah, AR_CFG);
2573                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2574                         ath_print(common, ATH_DBG_RESET,
2575                                 "CFG Byte Swap Set 0x%x\n", mask);
2576                 } else {
2577                         mask =
2578                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2579                         REG_WRITE(ah, AR_CFG, mask);
2580                         ath_print(common, ATH_DBG_RESET,
2581                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2582                 }
2583         } else {
2584                 /* Configure AR9271 target WLAN */
2585                 if (AR_SREV_9271(ah))
2586                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2587 #ifdef __BIG_ENDIAN
2588                 else
2589                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2590 #endif
2591         }
2592
2593         if (ah->btcoex_hw.enabled)
2594                 ath9k_hw_btcoex_enable(ah);
2595
2596         return 0;
2597 }
2598 EXPORT_SYMBOL(ath9k_hw_reset);
2599
2600 /************************/
2601 /* Key Cache Management */
2602 /************************/
2603
2604 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2605 {
2606         u32 keyType;
2607
2608         if (entry >= ah->caps.keycache_size) {
2609                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2610                           "keychache entry %u out of range\n", entry);
2611                 return false;
2612         }
2613
2614         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2615
2616         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2617         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2618         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2619         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2620         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2621         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2622         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2623         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2624
2625         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2626                 u16 micentry = entry + 64;
2627
2628                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2629                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2630                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2631                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2632
2633         }
2634
2635         return true;
2636 }
2637 EXPORT_SYMBOL(ath9k_hw_keyreset);
2638
2639 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2640 {
2641         u32 macHi, macLo;
2642
2643         if (entry >= ah->caps.keycache_size) {
2644                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2645                           "keychache entry %u out of range\n", entry);
2646                 return false;
2647         }
2648
2649         if (mac != NULL) {
2650                 macHi = (mac[5] << 8) | mac[4];
2651                 macLo = (mac[3] << 24) |
2652                         (mac[2] << 16) |
2653                         (mac[1] << 8) |
2654                         mac[0];
2655                 macLo >>= 1;
2656                 macLo |= (macHi & 1) << 31;
2657                 macHi >>= 1;
2658         } else {
2659                 macLo = macHi = 0;
2660         }
2661         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2662         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2663
2664         return true;
2665 }
2666 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2667
2668 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2669                                  const struct ath9k_keyval *k,
2670                                  const u8 *mac)
2671 {
2672         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2673         struct ath_common *common = ath9k_hw_common(ah);
2674         u32 key0, key1, key2, key3, key4;
2675         u32 keyType;
2676
2677         if (entry >= pCap->keycache_size) {
2678                 ath_print(common, ATH_DBG_FATAL,
2679                           "keycache entry %u out of range\n", entry);
2680                 return false;
2681         }
2682
2683         switch (k->kv_type) {
2684         case ATH9K_CIPHER_AES_OCB:
2685                 keyType = AR_KEYTABLE_TYPE_AES;
2686                 break;
2687         case ATH9K_CIPHER_AES_CCM:
2688                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2689                         ath_print(common, ATH_DBG_ANY,
2690                                   "AES-CCM not supported by mac rev 0x%x\n",
2691                                   ah->hw_version.macRev);
2692                         return false;
2693                 }
2694                 keyType = AR_KEYTABLE_TYPE_CCM;
2695                 break;
2696         case ATH9K_CIPHER_TKIP:
2697                 keyType = AR_KEYTABLE_TYPE_TKIP;
2698                 if (ATH9K_IS_MIC_ENABLED(ah)
2699                     && entry + 64 >= pCap->keycache_size) {
2700                         ath_print(common, ATH_DBG_ANY,
2701                                   "entry %u inappropriate for TKIP\n", entry);
2702                         return false;
2703                 }
2704                 break;
2705         case ATH9K_CIPHER_WEP:
2706                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2707                         ath_print(common, ATH_DBG_ANY,
2708                                   "WEP key length %u too small\n", k->kv_len);
2709                         return false;
2710                 }
2711                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2712                         keyType = AR_KEYTABLE_TYPE_40;
2713                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2714                         keyType = AR_KEYTABLE_TYPE_104;
2715                 else
2716                         keyType = AR_KEYTABLE_TYPE_128;
2717                 break;
2718         case ATH9K_CIPHER_CLR:
2719                 keyType = AR_KEYTABLE_TYPE_CLR;
2720                 break;
2721         default:
2722                 ath_print(common, ATH_DBG_FATAL,
2723                           "cipher %u not supported\n", k->kv_type);
2724                 return false;
2725         }
2726
2727         key0 = get_unaligned_le32(k->kv_val + 0);
2728         key1 = get_unaligned_le16(k->kv_val + 4);
2729         key2 = get_unaligned_le32(k->kv_val + 6);
2730         key3 = get_unaligned_le16(k->kv_val + 10);
2731         key4 = get_unaligned_le32(k->kv_val + 12);
2732         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2733                 key4 &= 0xff;
2734
2735         /*
2736          * Note: Key cache registers access special memory area that requires
2737          * two 32-bit writes to actually update the values in the internal
2738          * memory. Consequently, the exact order and pairs used here must be
2739          * maintained.
2740          */
2741
2742         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2743                 u16 micentry = entry + 64;
2744
2745                 /*
2746                  * Write inverted key[47:0] first to avoid Michael MIC errors
2747                  * on frames that could be sent or received at the same time.
2748                  * The correct key will be written in the end once everything
2749                  * else is ready.
2750                  */
2751                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2752                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2753
2754                 /* Write key[95:48] */
2755                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2756                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2757
2758                 /* Write key[127:96] and key type */
2759                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2760                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2761
2762                 /* Write MAC address for the entry */
2763                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2764
2765                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2766                         /*
2767                          * TKIP uses two key cache entries:
2768                          * Michael MIC TX/RX keys in the same key cache entry
2769                          * (idx = main index + 64):
2770                          * key0 [31:0] = RX key [31:0]
2771                          * key1 [15:0] = TX key [31:16]
2772                          * key1 [31:16] = reserved
2773                          * key2 [31:0] = RX key [63:32]
2774                          * key3 [15:0] = TX key [15:0]
2775                          * key3 [31:16] = reserved
2776                          * key4 [31:0] = TX key [63:32]
2777                          */
2778                         u32 mic0, mic1, mic2, mic3, mic4;
2779
2780                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2781                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2782                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2783                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2784                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2785
2786                         /* Write RX[31:0] and TX[31:16] */
2787                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2788                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2789
2790                         /* Write RX[63:32] and TX[15:0] */
2791                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2792                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2793
2794                         /* Write TX[63:32] and keyType(reserved) */
2795                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2796                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2797                                   AR_KEYTABLE_TYPE_CLR);
2798
2799                 } else {
2800                         /*
2801                          * TKIP uses four key cache entries (two for group
2802                          * keys):
2803                          * Michael MIC TX/RX keys are in different key cache
2804                          * entries (idx = main index + 64 for TX and
2805                          * main index + 32 + 96 for RX):
2806                          * key0 [31:0] = TX/RX MIC key [31:0]
2807                          * key1 [31:0] = reserved
2808                          * key2 [31:0] = TX/RX MIC key [63:32]
2809                          * key3 [31:0] = reserved
2810                          * key4 [31:0] = reserved
2811                          *
2812                          * Upper layer code will call this function separately
2813                          * for TX and RX keys when these registers offsets are
2814                          * used.
2815                          */
2816                         u32 mic0, mic2;
2817
2818                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2819                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2820
2821                         /* Write MIC key[31:0] */
2822                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2823                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2824
2825                         /* Write MIC key[63:32] */
2826                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2827                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2828
2829                         /* Write TX[63:32] and keyType(reserved) */
2830                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2831                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2832                                   AR_KEYTABLE_TYPE_CLR);
2833                 }
2834
2835                 /* MAC address registers are reserved for the MIC entry */
2836                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2837                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2838
2839                 /*
2840                  * Write the correct (un-inverted) key[47:0] last to enable
2841                  * TKIP now that all other registers are set with correct
2842                  * values.
2843                  */
2844                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2845                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2846         } else {
2847                 /* Write key[47:0] */
2848                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2849                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2850
2851                 /* Write key[95:48] */
2852                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2853                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2854
2855                 /* Write key[127:96] and key type */
2856                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2857                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2858
2859                 /* Write MAC address for the entry */
2860                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2861         }
2862
2863         return true;
2864 }
2865 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2866
2867 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2868 {
2869         if (entry < ah->caps.keycache_size) {
2870                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2871                 if (val & AR_KEYTABLE_VALID)
2872                         return true;
2873         }
2874         return false;
2875 }
2876 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2877
2878 /******************************/
2879 /* Power Management (Chipset) */
2880 /******************************/
2881
2882 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2883 {
2884         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2885         if (setChip) {
2886                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2887                             AR_RTC_FORCE_WAKE_EN);
2888                 if (!AR_SREV_9100(ah))
2889                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2890
2891                 if(!AR_SREV_5416(ah))
2892                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2893                                     AR_RTC_RESET_EN);
2894         }
2895 }
2896
2897 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2898 {
2899         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2900         if (setChip) {
2901                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2902
2903                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2904                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2905                                   AR_RTC_FORCE_WAKE_ON_INT);
2906                 } else {
2907                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2908                                     AR_RTC_FORCE_WAKE_EN);
2909                 }
2910         }
2911 }
2912
2913 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2914 {
2915         u32 val;
2916         int i;
2917
2918         if (setChip) {
2919                 if ((REG_READ(ah, AR_RTC_STATUS) &
2920                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2921                         if (ath9k_hw_set_reset_reg(ah,
2922                                            ATH9K_RESET_POWER_ON) != true) {
2923                                 return false;
2924                         }
2925                         ath9k_hw_init_pll(ah, NULL);
2926                 }
2927                 if (AR_SREV_9100(ah))
2928                         REG_SET_BIT(ah, AR_RTC_RESET,
2929                                     AR_RTC_RESET_EN);
2930
2931                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2932                             AR_RTC_FORCE_WAKE_EN);
2933                 udelay(50);
2934
2935                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2936                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2937                         if (val == AR_RTC_STATUS_ON)
2938                                 break;
2939                         udelay(50);
2940                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2941                                     AR_RTC_FORCE_WAKE_EN);
2942                 }
2943                 if (i == 0) {
2944                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2945                                   "Failed to wakeup in %uus\n",
2946                                   POWER_UP_TIME / 20);
2947                         return false;
2948                 }
2949         }
2950
2951         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2952
2953         return true;
2954 }
2955
2956 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2957 {
2958         struct ath_common *common = ath9k_hw_common(ah);
2959         int status = true, setChip = true;
2960         static const char *modes[] = {
2961                 "AWAKE",
2962                 "FULL-SLEEP",
2963                 "NETWORK SLEEP",
2964                 "UNDEFINED"
2965         };
2966
2967         if (ah->power_mode == mode)
2968                 return status;
2969
2970         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2971                   modes[ah->power_mode], modes[mode]);
2972
2973         switch (mode) {
2974         case ATH9K_PM_AWAKE:
2975                 status = ath9k_hw_set_power_awake(ah, setChip);
2976                 break;
2977         case ATH9K_PM_FULL_SLEEP:
2978                 ath9k_set_power_sleep(ah, setChip);
2979                 ah->chip_fullsleep = true;
2980                 break;
2981         case ATH9K_PM_NETWORK_SLEEP:
2982                 ath9k_set_power_network_sleep(ah, setChip);
2983                 break;
2984         default:
2985                 ath_print(common, ATH_DBG_FATAL,
2986                           "Unknown power mode %u\n", mode);
2987                 return false;
2988         }
2989         ah->power_mode = mode;
2990
2991         return status;
2992 }
2993 EXPORT_SYMBOL(ath9k_hw_setpower);
2994
2995 /*
2996  * Helper for ASPM support.
2997  *
2998  * Disable PLL when in L0s as well as receiver clock when in L1.
2999  * This power saving option must be enabled through the SerDes.
3000  *
3001  * Programming the SerDes must go through the same 288 bit serial shift
3002  * register as the other analog registers.  Hence the 9 writes.
3003  */
3004 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
3005 {
3006         u8 i;
3007         u32 val;
3008
3009         if (ah->is_pciexpress != true)
3010                 return;
3011
3012         /* Do not touch SerDes registers */
3013         if (ah->config.pcie_powersave_enable == 2)
3014                 return;
3015
3016         /* Nothing to do on restore for 11N */
3017         if (!restore) {
3018                 if (AR_SREV_9280_20_OR_LATER(ah)) {
3019                         /*
3020                          * AR9280 2.0 or later chips use SerDes values from the
3021                          * initvals.h initialized depending on chipset during
3022                          * ath9k_hw_init()
3023                          */
3024                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3025                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3026                                           INI_RA(&ah->iniPcieSerdes, i, 1));
3027                         }
3028                 } else if (AR_SREV_9280(ah) &&
3029                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
3030                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3031                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3032
3033                         /* RX shut off when elecidle is asserted */
3034                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3035                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3036                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3037
3038                         /* Shut off CLKREQ active in L1 */
3039                         if (ah->config.pcie_clock_req)
3040                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3041                         else
3042                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3043
3044                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3045                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3046                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3047
3048                         /* Load the new settings */
3049                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3050
3051                 } else {
3052                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3053                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3054
3055                         /* RX shut off when elecidle is asserted */
3056                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3057                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3058                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3059
3060                         /*
3061                          * Ignore ah->ah_config.pcie_clock_req setting for
3062                          * pre-AR9280 11n
3063                          */
3064                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3065
3066                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3067                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3068                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3069
3070                         /* Load the new settings */
3071                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3072                 }
3073
3074                 udelay(1000);
3075
3076                 /* set bit 19 to allow forcing of pcie core into L1 state */
3077                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3078
3079                 /* Several PCIe massages to ensure proper behaviour */
3080                 if (ah->config.pcie_waen) {
3081                         val = ah->config.pcie_waen;
3082                         if (!power_off)
3083                                 val &= (~AR_WA_D3_L1_DISABLE);
3084                 } else {
3085                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3086                             AR_SREV_9287(ah)) {
3087                                 val = AR9285_WA_DEFAULT;
3088                                 if (!power_off)
3089                                         val &= (~AR_WA_D3_L1_DISABLE);
3090                         } else if (AR_SREV_9280(ah)) {
3091                                 /*
3092                                  * On AR9280 chips bit 22 of 0x4004 needs to be
3093                                  * set otherwise card may disappear.
3094                                  */
3095                                 val = AR9280_WA_DEFAULT;
3096                                 if (!power_off)
3097                                         val &= (~AR_WA_D3_L1_DISABLE);
3098                         } else
3099                                 val = AR_WA_DEFAULT;
3100                 }
3101
3102                 REG_WRITE(ah, AR_WA, val);
3103         }
3104
3105         if (power_off) {
3106                 /*
3107                  * Set PCIe workaround bits
3108                  * bit 14 in WA register (disable L1) should only
3109                  * be set when device enters D3 and be cleared
3110                  * when device comes back to D0.
3111                  */
3112                 if (ah->config.pcie_waen) {
3113                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3114                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3115                 } else {
3116                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3117                               AR_SREV_9287(ah)) &&
3118                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3119                             (AR_SREV_9280(ah) &&
3120                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3121                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3122                         }
3123                 }
3124         }
3125 }
3126 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
3127
3128 /**********************/
3129 /* Interrupt Handling */
3130 /**********************/
3131
3132 bool ath9k_hw_intrpend(struct ath_hw *ah)
3133 {
3134         u32 host_isr;
3135
3136         if (AR_SREV_9100(ah))
3137                 return true;
3138
3139         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3140         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3141                 return true;
3142
3143         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3144         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3145             && (host_isr != AR_INTR_SPURIOUS))
3146                 return true;
3147
3148         return false;
3149 }
3150 EXPORT_SYMBOL(ath9k_hw_intrpend);
3151
3152 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3153 {
3154         u32 isr = 0;
3155         u32 mask2 = 0;
3156         struct ath9k_hw_capabilities *pCap = &ah->caps;
3157         u32 sync_cause = 0;
3158         bool fatal_int = false;
3159         struct ath_common *common = ath9k_hw_common(ah);
3160
3161         if (!AR_SREV_9100(ah)) {
3162                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3163                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3164                             == AR_RTC_STATUS_ON) {
3165                                 isr = REG_READ(ah, AR_ISR);
3166                         }
3167                 }
3168
3169                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3170                         AR_INTR_SYNC_DEFAULT;
3171
3172                 *masked = 0;
3173
3174                 if (!isr && !sync_cause)
3175                         return false;
3176         } else {
3177                 *masked = 0;
3178                 isr = REG_READ(ah, AR_ISR);
3179         }
3180
3181         if (isr) {
3182                 if (isr & AR_ISR_BCNMISC) {
3183                         u32 isr2;
3184                         isr2 = REG_READ(ah, AR_ISR_S2);
3185                         if (isr2 & AR_ISR_S2_TIM)
3186                                 mask2 |= ATH9K_INT_TIM;
3187                         if (isr2 & AR_ISR_S2_DTIM)
3188                                 mask2 |= ATH9K_INT_DTIM;
3189                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3190                                 mask2 |= ATH9K_INT_DTIMSYNC;
3191                         if (isr2 & (AR_ISR_S2_CABEND))
3192                                 mask2 |= ATH9K_INT_CABEND;
3193                         if (isr2 & AR_ISR_S2_GTT)
3194                                 mask2 |= ATH9K_INT_GTT;
3195                         if (isr2 & AR_ISR_S2_CST)
3196                                 mask2 |= ATH9K_INT_CST;
3197                         if (isr2 & AR_ISR_S2_TSFOOR)
3198                                 mask2 |= ATH9K_INT_TSFOOR;
3199                 }
3200
3201                 isr = REG_READ(ah, AR_ISR_RAC);
3202                 if (isr == 0xffffffff) {
3203                         *masked = 0;
3204                         return false;
3205                 }
3206
3207                 *masked = isr & ATH9K_INT_COMMON;
3208
3209                 if (ah->config.intr_mitigation) {
3210                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3211                                 *masked |= ATH9K_INT_RX;
3212                 }
3213
3214                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3215                         *masked |= ATH9K_INT_RX;
3216                 if (isr &
3217                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3218                      AR_ISR_TXEOL)) {
3219                         u32 s0_s, s1_s;
3220
3221                         *masked |= ATH9K_INT_TX;
3222
3223                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3224                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3225                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3226
3227                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3228                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3229                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3230                 }
3231
3232                 if (isr & AR_ISR_RXORN) {
3233                         ath_print(common, ATH_DBG_INTERRUPT,
3234                                   "receive FIFO overrun interrupt\n");
3235                 }
3236
3237                 if (!AR_SREV_9100(ah)) {
3238                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3239                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3240                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3241                                         *masked |= ATH9K_INT_TIM_TIMER;
3242                         }
3243                 }
3244
3245                 *masked |= mask2;
3246         }
3247
3248         if (AR_SREV_9100(ah))
3249                 return true;
3250
3251         if (isr & AR_ISR_GENTMR) {
3252                 u32 s5_s;
3253
3254                 s5_s = REG_READ(ah, AR_ISR_S5_S);
3255                 if (isr & AR_ISR_GENTMR) {
3256                         ah->intr_gen_timer_trigger =
3257                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3258
3259                         ah->intr_gen_timer_thresh =
3260                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3261
3262                         if (ah->intr_gen_timer_trigger)
3263                                 *masked |= ATH9K_INT_GENTIMER;
3264
3265                 }
3266         }
3267
3268         if (sync_cause) {
3269                 fatal_int =
3270                         (sync_cause &
3271                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3272                         ? true : false;
3273
3274                 if (fatal_int) {
3275                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3276                                 ath_print(common, ATH_DBG_ANY,
3277                                           "received PCI FATAL interrupt\n");
3278                         }
3279                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3280                                 ath_print(common, ATH_DBG_ANY,
3281                                           "received PCI PERR interrupt\n");
3282                         }
3283                         *masked |= ATH9K_INT_FATAL;
3284                 }
3285                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3286                         ath_print(common, ATH_DBG_INTERRUPT,
3287                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3288                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3289                         REG_WRITE(ah, AR_RC, 0);
3290                         *masked |= ATH9K_INT_FATAL;
3291                 }
3292                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3293                         ath_print(common, ATH_DBG_INTERRUPT,
3294                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3295                 }
3296
3297                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3298                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3299         }
3300
3301         return true;
3302 }
3303 EXPORT_SYMBOL(ath9k_hw_getisr);
3304
3305 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3306 {
3307         u32 omask = ah->mask_reg;
3308         u32 mask, mask2;
3309         struct ath9k_hw_capabilities *pCap = &ah->caps;
3310         struct ath_common *common = ath9k_hw_common(ah);
3311
3312         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3313
3314         if (omask & ATH9K_INT_GLOBAL) {
3315                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3316                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3317                 (void) REG_READ(ah, AR_IER);
3318                 if (!AR_SREV_9100(ah)) {
3319                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3320                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3321
3322                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3323                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3324                 }
3325         }
3326
3327         mask = ints & ATH9K_INT_COMMON;
3328         mask2 = 0;
3329
3330         if (ints & ATH9K_INT_TX) {
3331                 if (ah->txok_interrupt_mask)
3332                         mask |= AR_IMR_TXOK;
3333                 if (ah->txdesc_interrupt_mask)
3334                         mask |= AR_IMR_TXDESC;
3335                 if (ah->txerr_interrupt_mask)
3336                         mask |= AR_IMR_TXERR;
3337                 if (ah->txeol_interrupt_mask)
3338                         mask |= AR_IMR_TXEOL;
3339         }
3340         if (ints & ATH9K_INT_RX) {
3341                 mask |= AR_IMR_RXERR;
3342                 if (ah->config.intr_mitigation)
3343                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3344                 else
3345                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3346                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3347                         mask |= AR_IMR_GENTMR;
3348         }
3349
3350         if (ints & (ATH9K_INT_BMISC)) {
3351                 mask |= AR_IMR_BCNMISC;
3352                 if (ints & ATH9K_INT_TIM)
3353                         mask2 |= AR_IMR_S2_TIM;
3354                 if (ints & ATH9K_INT_DTIM)
3355                         mask2 |= AR_IMR_S2_DTIM;
3356                 if (ints & ATH9K_INT_DTIMSYNC)
3357                         mask2 |= AR_IMR_S2_DTIMSYNC;
3358                 if (ints & ATH9K_INT_CABEND)
3359                         mask2 |= AR_IMR_S2_CABEND;
3360                 if (ints & ATH9K_INT_TSFOOR)
3361                         mask2 |= AR_IMR_S2_TSFOOR;
3362         }
3363
3364         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3365                 mask |= AR_IMR_BCNMISC;
3366                 if (ints & ATH9K_INT_GTT)
3367                         mask2 |= AR_IMR_S2_GTT;
3368                 if (ints & ATH9K_INT_CST)
3369                         mask2 |= AR_IMR_S2_CST;
3370         }
3371
3372         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3373         REG_WRITE(ah, AR_IMR, mask);
3374         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3375                                            AR_IMR_S2_DTIM |
3376                                            AR_IMR_S2_DTIMSYNC |
3377                                            AR_IMR_S2_CABEND |
3378                                            AR_IMR_S2_CABTO |
3379                                            AR_IMR_S2_TSFOOR |
3380                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3381         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3382         ah->mask_reg = ints;
3383
3384         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3385                 if (ints & ATH9K_INT_TIM_TIMER)
3386                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3387                 else
3388                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3389         }
3390
3391         if (ints & ATH9K_INT_GLOBAL) {
3392                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3393                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3394                 if (!AR_SREV_9100(ah)) {
3395                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3396                                   AR_INTR_MAC_IRQ);
3397                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3398
3399
3400                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3401                                   AR_INTR_SYNC_DEFAULT);
3402                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3403                                   AR_INTR_SYNC_DEFAULT);
3404                 }
3405                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3406                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3407         }
3408
3409         return omask;
3410 }
3411 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
3412
3413 /*******************/
3414 /* Beacon Handling */
3415 /*******************/
3416
3417 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3418 {
3419         int flags = 0;
3420
3421         ah->beacon_interval = beacon_period;
3422
3423         switch (ah->opmode) {
3424         case NL80211_IFTYPE_STATION:
3425         case NL80211_IFTYPE_MONITOR:
3426                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3427                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3428                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3429                 flags |= AR_TBTT_TIMER_EN;
3430                 break;
3431         case NL80211_IFTYPE_ADHOC:
3432         case NL80211_IFTYPE_MESH_POINT:
3433                 REG_SET_BIT(ah, AR_TXCFG,
3434                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3435                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3436                           TU_TO_USEC(next_beacon +
3437                                      (ah->atim_window ? ah->
3438                                       atim_window : 1)));
3439                 flags |= AR_NDP_TIMER_EN;
3440         case NL80211_IFTYPE_AP:
3441                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3442                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3443                           TU_TO_USEC(next_beacon -
3444                                      ah->config.
3445                                      dma_beacon_response_time));
3446                 REG_WRITE(ah, AR_NEXT_SWBA,
3447                           TU_TO_USEC(next_beacon -
3448                                      ah->config.
3449                                      sw_beacon_response_time));
3450                 flags |=
3451                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3452                 break;
3453         default:
3454                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3455                           "%s: unsupported opmode: %d\n",
3456                           __func__, ah->opmode);
3457                 return;
3458                 break;
3459         }
3460
3461         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3462         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3463         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3464         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3465
3466         beacon_period &= ~ATH9K_BEACON_ENA;
3467         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3468                 ath9k_hw_reset_tsf(ah);
3469         }
3470
3471         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3472 }
3473 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3474
3475 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3476                                     const struct ath9k_beacon_state *bs)
3477 {
3478         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3479         struct ath9k_hw_capabilities *pCap = &ah->caps;
3480         struct ath_common *common = ath9k_hw_common(ah);
3481
3482         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3483
3484         REG_WRITE(ah, AR_BEACON_PERIOD,
3485                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3486         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3487                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3488
3489         REG_RMW_FIELD(ah, AR_RSSI_THR,
3490                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3491
3492         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3493
3494         if (bs->bs_sleepduration > beaconintval)
3495                 beaconintval = bs->bs_sleepduration;
3496
3497         dtimperiod = bs->bs_dtimperiod;
3498         if (bs->bs_sleepduration > dtimperiod)
3499                 dtimperiod = bs->bs_sleepduration;
3500
3501         if (beaconintval == dtimperiod)
3502                 nextTbtt = bs->bs_nextdtim;
3503         else
3504                 nextTbtt = bs->bs_nexttbtt;
3505
3506         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3507         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3508         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3509         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3510
3511         REG_WRITE(ah, AR_NEXT_DTIM,
3512                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3513         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3514
3515         REG_WRITE(ah, AR_SLEEP1,
3516                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3517                   | AR_SLEEP1_ASSUME_DTIM);
3518
3519         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3520                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3521         else
3522                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3523
3524         REG_WRITE(ah, AR_SLEEP2,
3525                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3526
3527         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3528         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3529
3530         REG_SET_BIT(ah, AR_TIMER_MODE,
3531                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3532                     AR_DTIM_TIMER_EN);
3533
3534         /* TSF Out of Range Threshold */
3535         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3536 }
3537 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3538
3539 /*******************/
3540 /* HW Capabilities */
3541 /*******************/
3542
3543 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3544 {
3545         struct ath9k_hw_capabilities *pCap = &ah->caps;
3546         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3547         struct ath_common *common = ath9k_hw_common(ah);
3548         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3549
3550         u16 capField = 0, eeval;
3551
3552         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3553         regulatory->current_rd = eeval;
3554
3555         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3556         if (AR_SREV_9285_10_OR_LATER(ah))
3557                 eeval |= AR9285_RDEXT_DEFAULT;
3558         regulatory->current_rd_ext = eeval;
3559
3560         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3561
3562         if (ah->opmode != NL80211_IFTYPE_AP &&
3563             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3564                 if (regulatory->current_rd == 0x64 ||
3565                     regulatory->current_rd == 0x65)
3566                         regulatory->current_rd += 5;
3567                 else if (regulatory->current_rd == 0x41)
3568                         regulatory->current_rd = 0x43;
3569                 ath_print(common, ATH_DBG_REGULATORY,
3570                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3571         }
3572
3573         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3574         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3575
3576         if (eeval & AR5416_OPFLAGS_11A) {
3577                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3578                 if (ah->config.ht_enable) {
3579                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3580                                 set_bit(ATH9K_MODE_11NA_HT20,
3581                                         pCap->wireless_modes);
3582                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3583                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3584                                         pCap->wireless_modes);
3585                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3586                                         pCap->wireless_modes);
3587                         }
3588                 }
3589         }
3590
3591         if (eeval & AR5416_OPFLAGS_11G) {
3592                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3593                 if (ah->config.ht_enable) {
3594                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3595                                 set_bit(ATH9K_MODE_11NG_HT20,
3596                                         pCap->wireless_modes);
3597                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3598                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3599                                         pCap->wireless_modes);
3600                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3601                                         pCap->wireless_modes);
3602                         }
3603                 }
3604         }
3605
3606         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3607         /*
3608          * For AR9271 we will temporarilly uses the rx chainmax as read from
3609          * the EEPROM.
3610          */
3611         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3612             !(eeval & AR5416_OPFLAGS_11A) &&
3613             !(AR_SREV_9271(ah)))
3614                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3615                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3616         else
3617                 /* Use rx_chainmask from EEPROM. */
3618                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3619
3620         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3621                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3622
3623         pCap->low_2ghz_chan = 2312;
3624         pCap->high_2ghz_chan = 2732;
3625
3626         pCap->low_5ghz_chan = 4920;
3627         pCap->high_5ghz_chan = 6100;
3628
3629         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3630         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3631         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3632
3633         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3634         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3635         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3636
3637         if (ah->config.ht_enable)
3638                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3639         else
3640                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3641
3642         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3643         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3644         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3645         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3646
3647         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3648                 pCap->total_queues =
3649                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3650         else
3651                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3652
3653         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3654                 pCap->keycache_size =
3655                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3656         else
3657                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3658
3659         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3660         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3661
3662         if (AR_SREV_9285_10_OR_LATER(ah))
3663                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3664         else if (AR_SREV_9280_10_OR_LATER(ah))
3665                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3666         else
3667                 pCap->num_gpio_pins = AR_NUM_GPIO;
3668
3669         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3670                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3671                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3672         } else {
3673                 pCap->rts_aggr_limit = (8 * 1024);
3674         }
3675
3676         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3677
3678 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3679         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3680         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3681                 ah->rfkill_gpio =
3682                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3683                 ah->rfkill_polarity =
3684                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3685
3686                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3687         }
3688 #endif
3689
3690         pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3691
3692         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3693                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3694         else
3695                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3696
3697         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3698                 pCap->reg_cap =
3699                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3700                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3701                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3702                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3703         } else {
3704                 pCap->reg_cap =
3705                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3706                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3707         }
3708
3709         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3710         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3711             AR_SREV_5416(ah))
3712                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3713
3714         pCap->num_antcfg_5ghz =
3715                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3716         pCap->num_antcfg_2ghz =
3717                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3718
3719         if (AR_SREV_9280_10_OR_LATER(ah) &&
3720             ath9k_hw_btcoex_supported(ah)) {
3721                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3722                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3723
3724                 if (AR_SREV_9285(ah)) {
3725                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3726                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3727                 } else {
3728                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3729                 }
3730         } else {
3731                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3732         }
3733 }
3734
3735 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3736                             u32 capability, u32 *result)
3737 {
3738         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3739         switch (type) {
3740         case ATH9K_CAP_CIPHER:
3741                 switch (capability) {
3742                 case ATH9K_CIPHER_AES_CCM:
3743                 case ATH9K_CIPHER_AES_OCB:
3744                 case ATH9K_CIPHER_TKIP:
3745                 case ATH9K_CIPHER_WEP:
3746                 case ATH9K_CIPHER_MIC:
3747                 case ATH9K_CIPHER_CLR:
3748                         return true;
3749                 default:
3750                         return false;
3751                 }
3752         case ATH9K_CAP_TKIP_MIC:
3753                 switch (capability) {
3754                 case 0:
3755                         return true;
3756                 case 1:
3757                         return (ah->sta_id1_defaults &
3758                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3759                         false;
3760                 }
3761         case ATH9K_CAP_TKIP_SPLIT:
3762                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3763                         false : true;
3764         case ATH9K_CAP_DIVERSITY:
3765                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3766                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3767                         true : false;
3768         case ATH9K_CAP_MCAST_KEYSRCH:
3769                 switch (capability) {
3770                 case 0:
3771                         return true;
3772                 case 1:
3773                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3774                                 return false;
3775                         } else {
3776                                 return (ah->sta_id1_defaults &
3777                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3778                                         false;
3779                         }
3780                 }
3781                 return false;
3782         case ATH9K_CAP_TXPOW:
3783                 switch (capability) {
3784                 case 0:
3785                         return 0;
3786                 case 1:
3787                         *result = regulatory->power_limit;
3788                         return 0;
3789                 case 2:
3790                         *result = regulatory->max_power_level;
3791                         return 0;
3792                 case 3:
3793                         *result = regulatory->tp_scale;
3794                         return 0;
3795                 }
3796                 return false;
3797         case ATH9K_CAP_DS:
3798                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3799                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3800                         ? false : true;
3801         default:
3802                 return false;
3803         }
3804 }
3805 EXPORT_SYMBOL(ath9k_hw_getcapability);
3806
3807 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3808                             u32 capability, u32 setting, int *status)
3809 {
3810         u32 v;
3811
3812         switch (type) {
3813         case ATH9K_CAP_TKIP_MIC:
3814                 if (setting)
3815                         ah->sta_id1_defaults |=
3816                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3817                 else
3818                         ah->sta_id1_defaults &=
3819                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3820                 return true;
3821         case ATH9K_CAP_DIVERSITY:
3822                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3823                 if (setting)
3824                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3825                 else
3826                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3827                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3828                 return true;
3829         case ATH9K_CAP_MCAST_KEYSRCH:
3830                 if (setting)
3831                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3832                 else
3833                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3834                 return true;
3835         default:
3836                 return false;
3837         }
3838 }
3839 EXPORT_SYMBOL(ath9k_hw_setcapability);
3840
3841 /****************************/
3842 /* GPIO / RFKILL / Antennae */
3843 /****************************/
3844
3845 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3846                                          u32 gpio, u32 type)
3847 {
3848         int addr;
3849         u32 gpio_shift, tmp;
3850
3851         if (gpio > 11)
3852                 addr = AR_GPIO_OUTPUT_MUX3;
3853         else if (gpio > 5)
3854                 addr = AR_GPIO_OUTPUT_MUX2;
3855         else
3856                 addr = AR_GPIO_OUTPUT_MUX1;
3857
3858         gpio_shift = (gpio % 6) * 5;
3859
3860         if (AR_SREV_9280_20_OR_LATER(ah)
3861             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3862                 REG_RMW(ah, addr, (type << gpio_shift),
3863                         (0x1f << gpio_shift));
3864         } else {
3865                 tmp = REG_READ(ah, addr);
3866                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3867                 tmp &= ~(0x1f << gpio_shift);
3868                 tmp |= (type << gpio_shift);
3869                 REG_WRITE(ah, addr, tmp);
3870         }
3871 }
3872
3873 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3874 {
3875         u32 gpio_shift;
3876
3877         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3878
3879         gpio_shift = gpio << 1;
3880
3881         REG_RMW(ah,
3882                 AR_GPIO_OE_OUT,
3883                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3884                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3885 }
3886 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3887
3888 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3889 {
3890 #define MS_REG_READ(x, y) \
3891         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3892
3893         if (gpio >= ah->caps.num_gpio_pins)
3894                 return 0xffffffff;
3895
3896         if (AR_SREV_9287_10_OR_LATER(ah))
3897                 return MS_REG_READ(AR9287, gpio) != 0;
3898         else if (AR_SREV_9285_10_OR_LATER(ah))
3899                 return MS_REG_READ(AR9285, gpio) != 0;
3900         else if (AR_SREV_9280_10_OR_LATER(ah))
3901                 return MS_REG_READ(AR928X, gpio) != 0;
3902         else
3903                 return MS_REG_READ(AR, gpio) != 0;
3904 }
3905 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3906
3907 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3908                          u32 ah_signal_type)
3909 {
3910         u32 gpio_shift;
3911
3912         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3913
3914         gpio_shift = 2 * gpio;
3915
3916         REG_RMW(ah,
3917                 AR_GPIO_OE_OUT,
3918                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3919                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3920 }
3921 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3922
3923 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3924 {
3925         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3926                 AR_GPIO_BIT(gpio));
3927 }
3928 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3929
3930 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3931 {
3932         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3933 }
3934 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3935
3936 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3937 {
3938         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3939 }
3940 EXPORT_SYMBOL(ath9k_hw_setantenna);
3941
3942 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3943                                enum ath9k_ant_setting settings,
3944                                struct ath9k_channel *chan,
3945                                u8 *tx_chainmask,
3946                                u8 *rx_chainmask,
3947                                u8 *antenna_cfgd)
3948 {
3949         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3950
3951         if (AR_SREV_9280(ah)) {
3952                 if (!tx_chainmask_cfg) {
3953
3954                         tx_chainmask_cfg = *tx_chainmask;
3955                         rx_chainmask_cfg = *rx_chainmask;
3956                 }
3957
3958                 switch (settings) {
3959                 case ATH9K_ANT_FIXED_A:
3960                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3961                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3962                         *antenna_cfgd = true;
3963                         break;
3964                 case ATH9K_ANT_FIXED_B:
3965                         if (ah->caps.tx_chainmask >
3966                             ATH9K_ANTENNA1_CHAINMASK) {
3967                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3968                         }
3969                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3970                         *antenna_cfgd = true;
3971                         break;
3972                 case ATH9K_ANT_VARIABLE:
3973                         *tx_chainmask = tx_chainmask_cfg;
3974                         *rx_chainmask = rx_chainmask_cfg;
3975                         *antenna_cfgd = true;
3976                         break;
3977                 default:
3978                         break;
3979                 }
3980         } else {
3981                 ah->config.diversity_control = settings;
3982         }
3983
3984         return true;
3985 }
3986
3987 /*********************/
3988 /* General Operation */
3989 /*********************/
3990
3991 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3992 {
3993         u32 bits = REG_READ(ah, AR_RX_FILTER);
3994         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3995
3996         if (phybits & AR_PHY_ERR_RADAR)
3997                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3998         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3999                 bits |= ATH9K_RX_FILTER_PHYERR;
4000
4001         return bits;
4002 }
4003 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
4004
4005 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
4006 {
4007         u32 phybits;
4008
4009         REG_WRITE(ah, AR_RX_FILTER, bits);
4010
4011         phybits = 0;
4012         if (bits & ATH9K_RX_FILTER_PHYRADAR)
4013                 phybits |= AR_PHY_ERR_RADAR;
4014         if (bits & ATH9K_RX_FILTER_PHYERR)
4015                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
4016         REG_WRITE(ah, AR_PHY_ERR, phybits);
4017
4018         if (phybits)
4019                 REG_WRITE(ah, AR_RXCFG,
4020                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
4021         else
4022                 REG_WRITE(ah, AR_RXCFG,
4023                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
4024 }
4025 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
4026
4027 bool ath9k_hw_phy_disable(struct ath_hw *ah)
4028 {
4029         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
4030                 return false;
4031
4032         ath9k_hw_init_pll(ah, NULL);
4033         return true;
4034 }
4035 EXPORT_SYMBOL(ath9k_hw_phy_disable);
4036
4037 bool ath9k_hw_disable(struct ath_hw *ah)
4038 {
4039         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
4040                 return false;
4041
4042         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
4043                 return false;
4044
4045         ath9k_hw_init_pll(ah, NULL);
4046         return true;
4047 }
4048 EXPORT_SYMBOL(ath9k_hw_disable);
4049
4050 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
4051 {
4052         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4053         struct ath9k_channel *chan = ah->curchan;
4054         struct ieee80211_channel *channel = chan->chan;
4055
4056         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
4057
4058         ah->eep_ops->set_txpower(ah, chan,
4059                                  ath9k_regd_get_ctl(regulatory, chan),
4060                                  channel->max_antenna_gain * 2,
4061                                  channel->max_power * 2,
4062                                  min((u32) MAX_RATE_POWER,
4063                                  (u32) regulatory->power_limit));
4064 }
4065 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
4066
4067 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
4068 {
4069         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
4070 }
4071 EXPORT_SYMBOL(ath9k_hw_setmac);
4072
4073 void ath9k_hw_setopmode(struct ath_hw *ah)
4074 {
4075         ath9k_hw_set_operating_mode(ah, ah->opmode);
4076 }
4077 EXPORT_SYMBOL(ath9k_hw_setopmode);
4078
4079 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4080 {
4081         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4082         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4083 }
4084 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
4085
4086 void ath9k_hw_write_associd(struct ath_hw *ah)
4087 {
4088         struct ath_common *common = ath9k_hw_common(ah);
4089
4090         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4091         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4092                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4093 }
4094 EXPORT_SYMBOL(ath9k_hw_write_associd);
4095
4096 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4097 {
4098         u64 tsf;
4099
4100         tsf = REG_READ(ah, AR_TSF_U32);
4101         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4102
4103         return tsf;
4104 }
4105 EXPORT_SYMBOL(ath9k_hw_gettsf64);
4106
4107 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4108 {
4109         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4110         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4111 }
4112 EXPORT_SYMBOL(ath9k_hw_settsf64);
4113
4114 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4115 {
4116         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4117                            AH_TSF_WRITE_TIMEOUT))
4118                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4119                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4120
4121         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4122 }
4123 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
4124
4125 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4126 {
4127         if (setting)
4128                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4129         else
4130                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4131 }
4132 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
4133
4134 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4135 {
4136         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4137                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4138                           "bad slot time %u\n", us);
4139                 ah->slottime = (u32) -1;
4140                 return false;
4141         } else {
4142                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4143                 ah->slottime = us;
4144                 return true;
4145         }
4146 }
4147 EXPORT_SYMBOL(ath9k_hw_setslottime);
4148
4149 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
4150 {
4151         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
4152         u32 macmode;
4153
4154         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
4155                 macmode = AR_2040_JOINED_RX_CLEAR;
4156         else
4157                 macmode = 0;
4158
4159         REG_WRITE(ah, AR_2040_MODE, macmode);
4160 }
4161
4162 /* HW Generic timers configuration */
4163
4164 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4165 {
4166         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4167         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4168         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4169         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4170         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4171         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4172         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4173         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4174         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4175         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4176                                 AR_NDP2_TIMER_MODE, 0x0002},
4177         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4178                                 AR_NDP2_TIMER_MODE, 0x0004},
4179         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4180                                 AR_NDP2_TIMER_MODE, 0x0008},
4181         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4182                                 AR_NDP2_TIMER_MODE, 0x0010},
4183         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4184                                 AR_NDP2_TIMER_MODE, 0x0020},
4185         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4186                                 AR_NDP2_TIMER_MODE, 0x0040},
4187         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4188                                 AR_NDP2_TIMER_MODE, 0x0080}
4189 };
4190
4191 /* HW generic timer primitives */
4192
4193 /* compute and clear index of rightmost 1 */
4194 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4195 {
4196         u32 b;
4197
4198         b = *mask;
4199         b &= (0-b);
4200         *mask &= ~b;
4201         b *= debruijn32;
4202         b >>= 27;
4203
4204         return timer_table->gen_timer_index[b];
4205 }
4206
4207 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4208 {
4209         return REG_READ(ah, AR_TSF_L32);
4210 }
4211 EXPORT_SYMBOL(ath9k_hw_gettsf32);
4212
4213 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4214                                           void (*trigger)(void *),
4215                                           void (*overflow)(void *),
4216                                           void *arg,
4217                                           u8 timer_index)
4218 {
4219         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4220         struct ath_gen_timer *timer;
4221
4222         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4223
4224         if (timer == NULL) {
4225                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4226                           "Failed to allocate memory"
4227                           "for hw timer[%d]\n", timer_index);
4228                 return NULL;
4229         }
4230
4231         /* allocate a hardware generic timer slot */
4232         timer_table->timers[timer_index] = timer;
4233         timer->index = timer_index;
4234         timer->trigger = trigger;
4235         timer->overflow = overflow;
4236         timer->arg = arg;
4237
4238         return timer;
4239 }
4240 EXPORT_SYMBOL(ath_gen_timer_alloc);
4241
4242 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4243                               struct ath_gen_timer *timer,
4244                               u32 timer_next,
4245                               u32 timer_period)
4246 {
4247         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4248         u32 tsf;
4249
4250         BUG_ON(!timer_period);
4251
4252         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4253
4254         tsf = ath9k_hw_gettsf32(ah);
4255
4256         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4257                   "curent tsf %x period %x"
4258                   "timer_next %x\n", tsf, timer_period, timer_next);
4259
4260         /*
4261          * Pull timer_next forward if the current TSF already passed it
4262          * because of software latency
4263          */
4264         if (timer_next < tsf)
4265                 timer_next = tsf + timer_period;
4266
4267         /*
4268          * Program generic timer registers
4269          */
4270         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4271                  timer_next);
4272         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4273                   timer_period);
4274         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4275                     gen_tmr_configuration[timer->index].mode_mask);
4276
4277         /* Enable both trigger and thresh interrupt masks */
4278         REG_SET_BIT(ah, AR_IMR_S5,
4279                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4280                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4281 }
4282 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
4283
4284 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4285 {
4286         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4287
4288         if ((timer->index < AR_FIRST_NDP_TIMER) ||
4289                 (timer->index >= ATH_MAX_GEN_TIMER)) {
4290                 return;
4291         }
4292
4293         /* Clear generic timer enable bits. */
4294         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4295                         gen_tmr_configuration[timer->index].mode_mask);
4296
4297         /* Disable both trigger and thresh interrupt masks */
4298         REG_CLR_BIT(ah, AR_IMR_S5,
4299                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4300                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4301
4302         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4303 }
4304 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
4305
4306 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4307 {
4308         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4309
4310         /* free the hardware generic timer slot */
4311         timer_table->timers[timer->index] = NULL;
4312         kfree(timer);
4313 }
4314 EXPORT_SYMBOL(ath_gen_timer_free);
4315
4316 /*
4317  * Generic Timer Interrupts handling
4318  */
4319 void ath_gen_timer_isr(struct ath_hw *ah)
4320 {
4321         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4322         struct ath_gen_timer *timer;
4323         struct ath_common *common = ath9k_hw_common(ah);
4324         u32 trigger_mask, thresh_mask, index;
4325
4326         /* get hardware generic timer interrupt status */
4327         trigger_mask = ah->intr_gen_timer_trigger;
4328         thresh_mask = ah->intr_gen_timer_thresh;
4329         trigger_mask &= timer_table->timer_mask.val;
4330         thresh_mask &= timer_table->timer_mask.val;
4331
4332         trigger_mask &= ~thresh_mask;
4333
4334         while (thresh_mask) {
4335                 index = rightmost_index(timer_table, &thresh_mask);
4336                 timer = timer_table->timers[index];
4337                 BUG_ON(!timer);
4338                 ath_print(common, ATH_DBG_HWTIMER,
4339                           "TSF overflow for Gen timer %d\n", index);
4340                 timer->overflow(timer->arg);
4341         }
4342
4343         while (trigger_mask) {
4344                 index = rightmost_index(timer_table, &trigger_mask);
4345                 timer = timer_table->timers[index];
4346                 BUG_ON(!timer);
4347                 ath_print(common, ATH_DBG_HWTIMER,
4348                           "Gen timer[%d] trigger\n", index);
4349                 timer->trigger(timer->arg);
4350         }
4351 }
4352 EXPORT_SYMBOL(ath_gen_timer_isr);